HV7351K6-G

Supertex inc. HV7351 Eight Channel Programmable High Voltage Ultrasound Transmit Beamformer Features ►► ►► ►► ►► ►► ►► General Description Eight channels with return to zero Up to ±70V output voltage ±3.0A output current Store up to four different patterns Independent programmable delays Single 11x11 QFN-80 package The Supertex HV7351 is an 8-channel programmable high voltage ultrasound transmit beamformer. Each channel is capable of swinging up to ±70V with an active discharge back to 0V. The outputs can source and sink more than 3.0A to achieve fast output rise and fall times. The active discharge is also capable of sourcing and sinking 3.0A for a fast return to ground. The topology of the HV7351 will significantly reduce the number of I/O logic control lines needed. Application ►► ►► ►► ►► Each pulser has four associated 64-bit shift registers for storing pre-determined transmit patterns and a 10-bit delay counter for controlling the transmit time. One of four arbitrary patterns can be transmitted with adjustable delay, depending on the data loaded into these shift registers and the delay counter. The delay counter can be clocked up to 200MHz, allowing incremental delays down to 5ns. Medical ultrasound imaging NDT, non-destructive testing Arbitrary pattern generator High speed PIN diode driver Typical Application Circuit HV7351 8-channel U1 Array Probe Tx1 tDELAY1 Tx2 tDELAY2 Tx3 tDELAY3 HV7351 8-channel U2 E1 E2 E3 Trigger HV7351 8-channel U16 Tx127 tDELAY127 Tx128 tDELAY128 E127 E128 Trigger Doc.# DSFP-HV7351 NR050213 Supertex inc. www.supertex.com HV7351 Pin Configuration Ordering Information 80 Part Number Package Option Packing HV7351K6-G 80-Lead QFN (11x11) 176/Tray 1 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value VLL, Positive logic supply -0.5V to 5.5V DVDD, Positive logic supply voltage -0.5V to 5.5V PVDD, Positive gate drive supply voltage -0.5V to 5.5V AVDD, Positive analog supply voltage -0.5V to 5.5V PVSS, Negative gate drive supply voltage +0.5V to -5.5V VPP, High voltage positive supply voltage -0.5V to +80V VNN, High voltage negative supply voltage +0.5V to -80V (VPP - VNN), Differential high voltage supply +160V VPF, Positive floating supply voltage VPP - 6.0V to VPP VNF, Negative floating supply voltage VNN to VNN +6.0V VRP, Positive supply for VNF regulator 0V to 15V VRN, Negative supply for VPF regulator 0V to -15V Operating temperature -40°C to +125°C Storage temperature -65°C to +150°C 80-Lead QFN (top view) Package Marking HV7351K6 LLLLLLLLL YYWW AAA CCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 80-Lead QFN Typical Thermal Resistance Package θja 80-Lead QFN 14OC/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Supply Voltages (TJ = 25°C unless otherwise specified) Sym Parameter Min Typ Max VPP Positive high voltage supply 3.0 - 70 V --- VNN Negative high voltage supply -70 - -3.0 V --- VLL Logic interface voltage 2.85 3.30 3.6 V --- AVDD Low voltage positive analog supply voltage 4.75 5.00 5.25 V --- DVDD Low voltage positive digital supply voltage 4.75 5.00 5.25 V --- PVDD Low voltage positive gate drive supply voltage 4.75 5.00 5.25 V --- PVSS Low voltage negative gate drive supply voltage -5.25 -5.00 -4.75 V --- Doc.# DSFP-HV7351 NR050213 2 Units Conditions Supertex inc. www.supertex.com HV7351 Operating Supply Voltages (cont.) (TJ = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions VRP Low voltage positive supply for VNF regulator 4.75 - 12 V --- VRN Low voltage negative supply for VPF regulator -12 - -4.75 V --- TCK Reference voltage logic trip point for TCK pin 0.4VLL 0.5VLL 0.6VLL V --- ITCK TCK input current - - ±10 μA VTCK = 0 to VLL Regulator Outputs (Operating conditions unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ =25ºC) Sym Parameter Min Typ Max VPP -5.00 Units Conditions VPF Positive floating gate drive voltage VPP -5.25 VPP -4.00 V 4.0µF ceramic capacitor across VPF and VPP VNF Negative floating gate drive voltage VNN +4.00 VNN +5.00 VNN +5.25 V 4.0µF ceramic capacitor across VNF and VNN Electrical Characteristics (Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC) Sym Parameter Min Typ Max IVLLQ VLL quiescent current - 384 500 IAVDDQ AVDD quiescent current - 12 30 IDVDDQ DVDD quiescent current - 12 30 IPVDDQ PVDD quiescent current - 70 100 IVRPQ VRP quiescent current - 0.3 6.0 IVRNQ VRN quiescent current - -0.01 6.0 IPVSSQ PVSS quiescent current -85 -45 - IVPPQ VPP quiescent current - 2.6 6.0 IVNNQ VNN quiescent current - -1.6 6.0 IVLLEN VLL enabled quiescent current - 390 500 IAVDDEN AVDD enabled quiescent current - 600 800 IDVDDEN DVDD enabled quiescent current - 22 55 IPVDDEN PVDD enabled quiescent current - 44 100 IVRPEN VRP enabled quiescent current - 450 650 IVRNEN VRN enabled quiescent current -650 -350 - IPVSSEN PVSS enabled quiescent current -100 -44 - IVPPEN VPP enabled quiescent current - 370 620 IVNNEN VNN enabled quiescent current -620 -420 - Doc.# DSFP-HV7351 NR050213 3 Units Conditions µA EN = Low, all inputs are static µA EN = Low, all inputs are static µA EN = Low, all inputs are static µA EN = Low, all inputs are static µA EN = Low, all inputs are static µA EN = High, all inputs are static µA EN = High, all inputs are static µA EN = High, all inputs are static µA EN = High, all inputs are static µA EN = High, all inputs are static µA EN = High, all inputs are static Supertex inc. www.supertex.com HV7351 Electrical Characteristics (cont.) (Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC) Sym Parameter Min Typ Max IVLLCW Units Conditions VLL current at TCK = 80MHz - 500 - µA IDVDDCW DVDD current at CW = 5MHz - 25 - mA IVPPCW VPP current at CW = 5MHz - 141 - mA IVNNCW VNN current at CW = 5MHz - 98 - mA VPP = +5.0V, VNN = -5.0V, EN = High, CW = High, 80MHz on TCK, 0.5VLL on TCK, all 8 channels active at 5.0MHz, No load AC Electrical Characteristics (Operating conditions unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC) Sym Parameter fTCK Transmit clock frequency fSCK Serial clock frequency Min Typ Max Units Conditions 0 - 200 MHz 0 - 80 0 - 70 MHz --No daisy chain Daisy chained tSU-DIN Set-up time data in to SCK 2.0 1.0 - ns --- tH-DIN Hold time SCK to data in 2.0 1.0 - ns --- tSU-CS1 Set-up time CS1 low to SCK 2.0 - - ns --- tSU-CS2 Set-up time CS2 low to SCK 2.0 - - ns --- tSU-TRIG Set-up time TRIG low to TCK 2.0 - - ns --- tW-TRIG TRIG pulse width 2TCK - - - --- tLHDO SCK to data out low to high delay time 3.0 9.0 12 3.0 9.0 10 tHLDO SCK to data out high to low delay time 3.0 9.0 12 3.0 9.0 10 tWA1A0 A1A0 pulse width tW-TRIG +40 - - tSUA1A0 Set-up time A1A0 to TRIG rising edge - 20 - tHA1A0 Hold time A1A0 to TRIG falling edge - 20 - tEN-ON Device enable time - 1.0 tEN-OFF Device disable time - tr1 Output rise time from 0V to +HV tf1 ns ns For DOUT1 For DOUT2 For DOUT1 For DOUT2 ns --- - ms 1.0µF capacitor on every VPF and VNF pin. - 100 ns --- - 9.0 13 Output fall time from 0V to -HV - 9.0 13 tr2 Damping output rise time from -HV to 0V - 9.0 13 ns Load = 330pF//2.5kΩ tf2 Damping output fall time from +HV to 0V - 9.0 13 tr3 Output rise time from -HV to +HV - 17 23 tf3 Output fall time from +HV to -HV - 17 23 trcw CW output rise time - 9.0 16 tfcw CW output fall time - 9.0 16 ns VPP = +5.0V, VNN = -5.0V, Load = 330pF//2.5kΩ Doc.# DSFP-HV7351 NR050213 4 Supertex inc. www.supertex.com HV7351 AC Electrical Characteristics (cont.) (Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC) Sym Parameter Min Typ Max tdr1 Output propagation delay rise time 1 10.85 13.35 15.85 tdf1 Output propagation delay fall time 1 11.35 13.85 16.35 tdr2 Output propagation delay rise time 2 11.25 13.75 16.25 tdf2 Output propagation delay fall time 2 11.75 14.25 16.75 tdr3 Output propagation delay rise time 3 11.35 13.85 16.35 tdf3 Output propagation delay fall time 3 11.45 13.95 16.45 tdcwlh CW output propagation delay time from low to high 10.45 12.95 15.45 tdcwhl CW output propagation delay time from high to low 10.35 12.85 15.35 Delay time matching - ±0.7 tJCW Delay jitter on rise or fall - LAT Latency 3.5TCK Δtdcwhl Units Conditions ns No Load. ns VPP = +5.0V, VNN = -5.0V, No Load - ns P to N, channel-to-channel matching 13 - ps VPP = +5.0V, VNN = -5.0V, Load = 50Ω 3.5TCK 3.5TCK - --- Output P-channel MOSFET to VPP, CW = 0 IOUT Output saturation current 2.2 3.2 - A --- RON Output ON-resistance - 4.2 - Ω IOUT = 100mA COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz Output N-channel MOSFET to VNN, CW = 0 IOUT Output saturation current - -3.2 -2.2 A --- RON Output ON-resistance - 2.4 - Ω IOUT = -100mA COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz Output P-channel MOSFET to VPP, CW = 1 IOUT Output saturation current 1.2 1.5 - A --- RON Output ON-resistance - 8.0 - Ω IOUT = 100mA COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz Output N-channel MOSFET to VNN, CW = 1 IOUT Output saturation current - -1.5 -1.2 A --- RON Output ON-resistance - 6.6 - Ω IOUT = -100mA COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz Doc.# DSFP-HV7351 NR050213 5 Supertex inc. www.supertex.com HV7351 AC Electrical Characteristics (cont.) (Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC) Sym Parameter Min Typ Max Units Conditions Damping P-channel MOSFET to PGND IOUT Output saturation current 2.2 3.2 - A --- RON Output ON-resistance - 4.0 - Ω IOUT = 100mA COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz Damping N-channel MOSFET to PGND IOUT Output saturation current - -3.2 -2.2 A --- RON Output ON-resistance - 2.3 - Ω IOUT = -100mA COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz - ±1.0 - µA VTCK = 0 to VLL Logic Inputs ITCK Input current for TCK VIH Input logic high voltage for TCK TCK +0.15 TCK VLL V Only for TCK input, TCK = 0.5VLL VIL Input logic low voltage for TCK 0 TCK TCK -0.15 V Only for TCK input, TCK = 0.5VLL VIH Input logic high voltage 0.8VLL - VLL V For all logic inputs except TCK VIL Input logic low voltage 0 - 0.2VLL V For all logic inputs except TCK IIH Input logic high current - - 1.0 µA --- IIL Input logic low current -1.0 - - µA --- VOL Output logic low voltage 0 - 0.7 V IOUT = 0 to -10mA VOH Output logic high voltage VLL -0.7 - VLL V IOUT = 0 to 10mA CIN Input logic capacitance - - 5.0 pF --- Doc.# DSFP-HV7351 NR050213 6 Supertex inc. www.supertex.com HV7351 Logic Truth Table Mode Non-CW mode. Outputs not inverted. Outputs are controlled by data in the shift registers Non-CW mode. Outputs are inverted. Outputs are controlled by data in the shift registers Inputs EN CW 10-bit Counter Outputs INV NIN PIN Doc.# DSFP-HV7351 NR050213 P-ch Comments RTZ 1 0 X X 0 0 OFF OFF ON RTZ (return-to-zero) is activated when NIN and PIN are both low. Output is pulled to ground through a series diode. 1 0 X 0 0 1 OFF ON OFF Not inverted. Logic 1 in the P-channel register turns on the output P-channel MOSFET. 1 0 X 0 1 0 ON OFF OFF Not inverted. Logic 1 in the N-channel register turns on the output N-channel MOSFET. 1 0 X X 1 1 OFF OFF OFF Avoids cross over current. A logic 1 in both P- and N-channel registers will put the output in a Hi-Z state. 1 0 X 1 0 1 ON OFF OFF Inverted, for harmonic imaging 1 0 X 1 1 0 OFF ON OFF Inverted, for harmonic imaging 1 X All 1 X X X OFF OFF OFF 1 1 Not all 1 X X X OFF/ ON ON/ OFF OFF 0 X X X X X OFF OFF OFF CW mode. Output follows fcw Device Disabled N-ch 7 Off channels are the ones with all 1’s in their respective 10-bit counters. Output follows the fCW signal. Shift registers for NIN and PIN should remain static to save power. Hi-Z state Supertex inc. www.supertex.com HV7351 Block Diagram VLL AVDD DVDD EN Decoder SIZE CS1 SCK DIN1 DOUT1 A0 A1 VPP VPP P-ch Registers N-ch Registers 16/32-bit Register Pattern 1 16/32-bit Register Pattern 1 Linear Regulator 16/32-bit Register Pattern 2 16/32-bit Register Pattern 2 VRN 16/32-bit Register Pattern 3 16/32-bit Register Pattern 3 16/32-bit Register Pattern 4 16/32-bit Register Pattern 4 VPF VPF VRN VRP VRP Linear Regulator VNF VNF VNN DIN2 DOUT2 8 10-bit Registers for Delay Counters VNN 6-bit for Divide by N CS2 VPP CW INV CW Tx1 VPF TRIG EN 10-bit Delay Counter EN 6-bit Counter Divide by N N = 1 to 64 Divide by 2 fCW VNF Control Logic INV 16/32 bit Serial Shift Reg. EN/LD CW VNN PIN CLK PGND INV 16/32 bit Serial Shift Reg. EN/LD CW NIN PVSS PVDD CLK PGND RTZ GATE Driver Supply Voltages PVDD PVSS VPP EN 10-bit Delay Counter EN 6-bit Counter Divide by N N = 1 to 64 CW Divide by 2 fCW Control Logic INV 16/32 bit Serial Shift Reg. EN/LD CW VPF Tx8 VNF PIN VNN CLK TCK - TCK + DGND VLL to VDD Translator PGND INV 16/32 bit Serial Shift Reg. EN/LD CW CLK NIN PVSS PVDD AGND VSUB Doc.# DSFP-HV7351 NR050213 PGND 8 Supertex inc. www.supertex.com HV7351 Timing Diagram 1 TCk = 1.65V (0.5VLL) 3.5 TCk cycles 3.3V TCk 0V 3.3V Internal CLK (for N=2) 0V tSU-TRIG 3.3V Trig 0V +70V tWTRIG tdr1 Delay time set by Tx1 10-bit counter Tx1 tdf2 90% tWTRIG needs to be at least 2 rising edges of TCk 0V 90% 10% tdf1 10% tr1 tdr2 10% tf2 -70V 10% 90% 90% tf1 tr2 +70V Delay time set by Tx2 10 bit counter Tx2 0V Example with Tx2 delay having two TCk cycles more than Tx1 -70V Timing Diagram 2 TCk = 1.65V (0.5VLL) TCk 3.5 TCk cycles 3.3V 0V Internal CLk (for N=2) 3.3V 0V tSU-TRIG 3.3V Trig 0V +70V Tx1 0V tWTRIG tdf3 tWTRIG needs to be at least 2 rising edges of TCk 90% tdr3 90% Delay time set by Tx1 10-bit counter 10% -70V tf3 10% tr3 +70V Tx2 0V -70V Doc.# DSFP-HV7351 NR050213 Delay time set by Tx2 10 bit counter Example with Tx2 delay having one TCk cycle more than Tx1 9 Supertex inc. www.supertex.com HV7351 Pattern Register Circuit Diagram SIZE A1 A0 CS1 A1 A0 CS1 CS1 A1 SIZE EN DIN 2 to 4 Decoder A0 SIZE 16/32 bits EN Shift Register DIN P-ch. Pattern 1 SCK SCK A1 A0 CS1 Size EN DIN SCK SCK A1 A0 CS1 Size EN DIN SCK 16/32 bits Shift Register P-ch. Pattern 2 16/32 bits Shift Register N-ch. Pattern 1 A1 A0 CS1 16/32 bits Shift Register N-ch. Pattern 2 A1 A0 CS1 DOUT1 16/32 bits Shift Register P-ch. Pattern 3 16/32 bits Shift Register N-ch. Pattern 3 16/32 bits Shift Register P-ch. Pattern 4 16/32 bits Shift Register N-ch. Pattern 4 A1 A0 CS1 A1 A0 CS1 DIN1 Loading Data into the Four 16/32 bit Pattern Registers A detailed circuit diagram of the pattern registers is shown above. There are 4 programmable patterns that can be stored. One of four patterns can be selected via the two input logic decoder pins, A1 and A0. Data can be loaded on the selected pattern. Each pattern can be either 16 or 32 bits wide. The SIZE pin determines whether they are 16 or 32 bits wide. SIZE = H will set the pattern to be 32 bits wide while SIZE = L will set it to 16 bits wide. DIN1 is the input data for the register. When CS1 is high, data will not be shifted in. Data is shifted in only when CS1 is low. DIN1 32 bits for P-ch Pattern 1 SCK 32 bits for N-ch Pattern 1 32 bits for P-ch Pattern 1 S64 S63 S34 DOUT1 32 bits for N-ch Pattern 1 S33 S32 S31 S2 S1 A 2-to-4 decoder is provided to select which of the four patterns is to be used for all of the outputs. Logic inputs A1 and A0 determine which patterns are selected per the decoder truth table shown below. Once A1 and A0 are set, a rising edge on the trigger logic input pin will automatically load the selected pattern to all of the outputs. With SIZE = H, the circuit is effectively a 64-bit serial shift register. The data first enters into the P-channel register and continues to be shifted though to the N-channel register. Data is clocked in during the rising edge of the clock. There is no activity during the falling edge of the clock. The data, DIN1, enters from the P-channel register and exits from the N-channel register from DOUT1. Decoder Truth Table Logic Decoder Input For size = High, 32 bits wide (size = Low, 16-bits wide) A1 = A0 = Low, Pattern 1 selected CS1 = Low, data can be shifted in 64-bit serial shift register: 32 bits for the P-channel and 32 bits for the N-channel Pattern Selected A1 A0 0 0 1 0 1 2 1 0 3 1 1 4 Data is shifted in during the rising edge of the clock. S1 is the first bit shifted in, entering the P-channel register. After 64 clock cycles, S1 will be located in the N-channel register as shown below. It will also be clocked out to DOUT1. Doc.# DSFP-HV7351 NR050213 10 Supertex inc. www.supertex.com HV7351 Loading Data into the Delay Counters and the Divide-by-N Counter though to the 6-bit register for the divide by N counter. Data is clocked in during the rising edge of the clock. There is no activity during the falling edge of the clock. The MSB bit in the 6-bit divide-by-N register is clocked out into DOUT2 for cascading multiple devices if desired. Each output channel, TX, has its own programmable 10-bit delay counter. For 8 channels, 80 bits are needed. A 6-bit divide-by-N counter is also provided to program the desired TX frequency. To program all the individual delay counters and the divide-by-N counter, an 86-bit serial shift register is provided. It uses the same clock input that the pattern registers uses. DIN2 is the input data for this register. When CS2 is high, data will not be shifted in. Data is shifted in only when CS2 is low. 10-Bit Delay Counter The input clock for the 10-bit delay counter is the TCK pin. The TCK pin is the only pin that is capable of high frequency, 200MHz. This helps maximum delay time resolution. The counter counts upward. Please refer to the table below. As shown below, the data first enters into the 10-bit register for the TX8 delay counter and continues to be shifted 86-bit Serial Shift Register: 80 bits for the delay counters and 6 bits for the divide by N DIN2 SCK 10 bits Tx8 10 bits Tx7 10 bits Tx6 10 bits Tx5 10 bits for Tx8 delay Counter 10 bits Tx4 10 bits Tx3 10 bits Tx2 10 bits for Tx7 delay Counter MSB LSB DOUT2 6 bits for divide by N S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 LSB 6 bits divide by N 10 bits Tx1 MSB S6 S5 S4 S3 LSB S2 S1 MSB Delay Counter Table MSB LSB Delay Time 0 0 0 0 0 0 0 0 0 0 1023 TCK cycles 0 0 0 0 0 0 0 0 0 1 1022 TCK cycles 0 0 0 0 0 0 0 0 1 0 1021 TCK cycles 0 0 0 0 0 0 0 0 1 1 1020 TCK cycles I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 1 1 1 1 1 1 1 1 0 0 3 TCK cycles 1 1 1 1 1 1 1 1 0 1 2 TCK cycles 1 1 1 1 1 1 1 1 1 0 1 TCK cycle 1 1 1 1 1 1 1 1 1 1 No trigger Doc.# DSFP-HV7351 NR050213 11 Supertex inc. www.supertex.com HV7351 6-Bit Divide-by-N Counter clock cycle will set the TX output to be either at VPP, VNN, ground, or high impedance depending on what was preprogrammed in their corresponding registers. The input clock for the 6-bit divide-by-N counter is the TCK pin. It generates the clock frequency for the 16/32 bit serial shift register for the output P- and N-channel patterns. Each MSB LSB Output Shift Register Clock Frequency 0 0 0 0 0 0 fTCK ÷ 64 0 0 0 0 0 1 fTCK ÷ 63 0 0 0 0 1 0 fTCK ÷ 62 0 0 0 0 1 1 fTCK ÷ 61 I I I I I I I I I I I I I I I I I I I I I 1 1 1 1 0 0 fTCK ÷ 4 1 1 1 1 0 1 fTCK ÷ 3 1 1 1 1 1 0 fTCK ÷ 2 1 1 1 1 1 1 fTCK ÷ 1 Pin Description Pin Name Description 1 AVDD Positive analog supply voltage (+5.0V). 2 DIN2 Serial data in for delay counters and frequency divider. 3 CS2 Activates DIN2. Input logic high = off, input logic low = on. 4 SIZE Sets pattern width to either 16-bits or 32-bits. Logic low = 16-bits, logic high = 32-bits. 5 INV Inverts the TX output waveform. See logic truth table for details. 6 CW Activates CW mode. Logic low = non-CW mode, logic high = CW mode. See logic truth table for details. 7 DOUT2 8 EN 9 SCK 10 DVDD Positive digital supply voltage (+5.0V). 11 DGND Digital ground. 12 TRIG Toggles all TX outputs to transmit. Needs to be high for 2 rising edges of TCK. Delay counters will start on the rising edge of the TCK pin right after the falling edge of the TRIG signal. See timing diagram for details. 13 TCK Transmitter clock for the delay counters and input frequency for the divide by N. Can be CMOS, LVDS, or SSTL. 14 TCK Logic trip point TCK. Can be set to a DC value from 0.4VLL to 0.6VLL or driven differentially with TCK. 15 VLL Logic interface supply voltage (3.0V or 3.3V). 16 CS1 Activates DIN1. Input logic high = off, input logic low = on. 17 DOUT1 Doc.# DSFP-HV7351 NR050213 Data out for delay counters and frequency divider. Enables and disables device. Logic low = off, logic high = on. Serial clock input for serial shift registers. Data out for P-channel and N-channel pattern registers. 12 Supertex inc. www.supertex.com HV7351 Pin Description (cont.) Pin Name 18 A0 19 A1 20 DIN1 Serial data in for P-channel and N-channel pattern registers. 21 VRN Negative supply for VPF regulator (-5.0V). 22 PVDD 23 PGND 24 PGND 25 PVSS 26 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total. 27 NC No connection. 28 VNF Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total. 29 VNN Negative high voltage supply (-3.0V to -70V). 30 TX1 Transmit pulser outputs for channel 1. 31 VPP 32 VPP 33 TX2 34 VNN 35 VNN 36 TX3 37 VPP 38 VPP 39 TX4 40 VNN 41 VNN 42 VNF 43 DGND 44 VPP Positive high voltage supply (+3.0V to +70V). 45 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total. 46 PGND Power ground path for RTZ output transistors. 47 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V). 48 PGND Power ground path for RTZ output transistors. 49 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V). Doc.# DSFP-HV7351 NR050213 Description Decoded to select 1 of 4 patterns to be loaded. Positive gate drive supply voltage for RTZ output transistors (+5.0V). Power ground path for RTZ output transistors. Negative gate drive supply voltage for RTZ output transistors (-5.0V). Positive high voltage supply (+3.0V to +70V). Transmit pulser outputs for channel 2. Negative high voltage supply (-3.0V to -70V). Transmit pulser outputs for channel 3. Positive high voltage supply (+3.0V to +70V). Transmit pulser outputs for channel 4. Negative high voltage supply (-3.0V to -70V). Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total. Digital ground. 13 Supertex inc. www.supertex.com HV7351 Pin Description (cont.) Pin Name Description 50 DVDD Positive digital supply voltage (+5.0V). 51 DGND Digital ground. 52 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V). 53 PGND Power ground path for RTZ output transistors. 54 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V). 55 PGND Power ground path for RTZ output transistors. 56 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total. 57 VPP Positive high voltage supply (+3.0V to +70V). 58 DGND 59 VNF 60 VNN 61 VNN 62 TX5 63 VPP 64 VPP 65 TX6 66 VNN 67 VNN 68 TX7 69 VPP 70 VPP 71 TX8 Transmit pulser outputs for channel 8. 72 VNN Negative high voltage supply (-3.0V to -70V). 73 VNF Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total. 74 NC No connection. 75 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total. 76 PVSS 77 PGND 78 PGND 79 PVDD 80 VRP VSUB Doc.# DSFP-HV7351 NR050213 Digital ground. Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total. Negative high voltage supply (-3.0V to -70V). Transmit pulser outputs for channel 5. Positive high voltage supply (+3.0V to +70V). Transmit pulser outputs for channel 6. Negative high voltage supply (-3.0V to -70V). Transmit pulser outputs for channel 7. Positive high voltage supply (+3.0V to +70V). Negative gate drive supply voltage for RTZ output transistors (-5.0V). Power ground path for RTZ output transistors. Positive gate drive supply voltage for RTZ output transistors (+5.0V). Positive supply for VNF regulator (+5.0V). Exposed center pad. Needs to be externally connected to digital ground, DGND. 14 Supertex inc. www.supertex.com HV7351 80-Lead QFN Package Outline (K6) 11.00x11.00mm body, 1.00mm height (max), 0.50mm pitch D 80 D2 80 1 1 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e E2 E b View B Top View Bottom View Note 3 θ A A3 Seating Plane A1 L Note 2 L1 View B Side View Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.18 10.90 9.50 10.90 9.50 0.25 11.00 9.65 11.00 9.65 0.30 11.10 9.75 11.10 9.75 0.50 BSC L L1 θ 0.30 0.00 0O 0.40 - - 0.50 0.15 14O Drawings are not to scale. Supertex Doc.#: DSPD-80QFNK611X11P050, Version A111511 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV7351 NR050213 15 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com