HV7358DB1
User’s Guide
2020 Microchip Technology Inc.
DS50002951A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
DS50002951A-page 2
ISBN: 978-1-5224-5573-8
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 5
Introduction............................................................................................................ 5
Document Layout .................................................................................................. 5
Conventions Used in this Guide ............................................................................ 6
Recommended Reading........................................................................................ 7
The Microchip Website.......................................................................................... 7
Customer Support ................................................................................................. 7
Document Revision History ................................................................................... 7
Chapter 1. HV7358 Overview......................................................................................... 9
1.1 Introduction ..................................................................................................... 9
1.2 Features ....................................................................................................... 10
1.3 Device summary ........................................................................................... 10
1.4 Functional Description .................................................................................. 12
1.5 What the HV7358DB1 ADM00732 Kit Includes ........................................... 12
Chapter 2. HV7358 Overview....................................................................................... 13
2.1 Getting Started ............................................................................................. 13
2.2 USB Driver Installation ................................................................................. 13
2.3 HV7358DB1 GUI Installation ........................................................................ 19
Chapter 3. HV7358DB1 GUI Operation ....................................................................... 23
3.1 Getting Started ............................................................................................. 23
3.2 Setup Procedure .......................................................................................... 23
3.3 HV7358DB1 Power Supply Requirements ................................................... 24
3.4 MUPB002 and GUI/USB Programming ........................................................ 25
3.5 Running the HV7358DB1 ............................................................................. 37
3.6 Stopping the HV7358DB1 ............................................................................ 37
3.7 Sample Waveform ........................................................................................ 38
Chapter 4. MUPB002 FPGA Configuration ................................................................ 39
4.1 Introduction ................................................................................................... 39
4.2 Hardware and Software Required ................................................................ 39
4.3 Setup Procedure .......................................................................................... 39
4.4 Software Execution ...................................................................................... 40
4.5 Conclusion .................................................................................................... 45
Chapter 5. PCB Design and Layout Techniques....................................................... 47
5.1 Introduction ................................................................................................... 47
2020 Microchip Technology Inc.
DS50002951A-page 3
HV7358DB1 User’s Guide
Appendix A. HV7835DB1 and MUPB002 Schematics and Layouts .........................49
A.1 Introduction .................................................................................................. 49
A.2 HV7358DB1 – Schematic ............................................................................ 50
A.3 MUPB002 Schematic – Top Block Diagram ................................................ 51
A.4 MUPB002 Schematic – Demo Board Connectors ....................................... 52
A.5 MUPB002 Schematic – FPGA ..................................................................... 53
A.6 MUPB002 Schematic – SPI Flash for FPGA Configuration ......................... 54
A.7 MUPB002 Schematic – Programmable Clock ............................................. 55
A.8 MUPB002 Schematic – FPGA Decoupling Capacitors ................................ 56
A.9 HV7358DB1 – Top Silk ................................................................................ 57
A.10 HV7358DB1 – Top Copper and Silk .......................................................... 57
A.11 HV7358DB1 – Top Copper ........................................................................ 58
A.12 HV7358DB1 – Bottom Copper ................................................................... 58
A.13 HV7358DB1 – Bottom Copper and Silk ..................................................... 59
A.14 HV7358DB1 – Bottom Silk ......................................................................... 59
A.15 MUPB002 – Top Silk .................................................................................. 60
A.16 MUPB002 – Top Copper and Silk .............................................................. 60
A.17 MUPB002 – Top Copper ............................................................................ 61
A.18 MUPB002 – Bottom Copper ...................................................................... 61
A.19 MUPB002 – Bottom Copper and Silk ......................................................... 62
A.20 MUPB002 – Bottom Silk ............................................................................ 62
Appendix B. Bill of Materials (BOM) ...........................................................................63
Appendix C. HV7358DB1 Waveforms .........................................................................69
C.1 MIC2800 Evaluation Board Test Waveform Examples ................................ 69
Appendix D. HV7358 GUI Parameter and Default ......................................................75
D.1 HV7358 GUI Parameter Limits and Default Page-1 .................................... 75
D.2 HV7358DB1 GUI Parameter Initial Value and Limits Page-2 ...................... 76
D.3 HV7358DB1 GUI Parameter Initial Value and Limits Page-3 ...................... 77
Worldwide Sales and Service .....................................................................................78
DS50002951A-page 4
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our website
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
HV7358DB1. Items discussed in this chapter include:
•
•
•
•
•
•
Document Layout
Conventions Used in this Guide
Recommended Reading
The Microchip Website
Customer Support
Document Revision History
DOCUMENT LAYOUT
This document describes how to use the HV7358DB1 User’s Guide as a development
tool. The document is organized as follows:
• Chapter 1. “HV7358 Overview” – Important information about the HV7358DB1
User’s Guide.
• Chapter 2. “HV7358 Overview” – This chapter includes a detailed description of
installing the required USB driver and GUI program to your computer.
• Chapter 3. “HV7358DB1 GUI Operation” – This chapter includes a detailed
description of each function of the demonstration board and instructions for how to
begin using the HV7358 Evaluation Board.
• Chapter 4. “MUPB002 FPGA Configuration” – This chapter explains how to
load software into the FPGA on the MPUB002.
• Chapter 5. “PCB Design and Layout Techniques” – The HV7358 deals with
high-speed, high-frequency and high-current signals. This chapter will explain
PCB layout techniques for these conditions.
2020 Microchip Technology Inc.
DS50002951A-page 5
HV7358DB1 User’s Guide
• Appendix A. “HV7835DB1 and MUPB002 Schematics and Layouts” – Shows
the schematics and layouts for the HV7358DB1 and MUP002.
• Appendix B. “Bill of Materials (BOM)” – Lists the parts used to build the
HV7358DB1 Evaluation Board.
• Appendix C. “HV7358DB1 Waveforms” – Shows sample output waveforms
generated by the HV7358DB1.
• Appendix D. “HV7358 GUI Parameter and Default” – Documents GUI limits
and default values.
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Arial font:
Italic characters
Initial caps
Quotes
Underlined, italic text with
right angle bracket
Bold characters
N‘Rnnnn
Text in angle brackets < >
Courier New font:
Plain Courier New
Represents
Referenced books
Emphasized text
A window
A dialog
A menu selection
A field name in a window or
dialog
A menu path
MPLAB® IDE User’s Guide
...is the only compiler...
the Output window
the Settings dialog
select Enable Programmer
“Save project before build”
A dialog button
A tab
A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
A key on the keyboard
Click OK
Click the Power tab
4‘b0010, 2‘hF1
Italic Courier New
Sample source code
Filenames
File paths
Keywords
Command-line options
Bit values
Constants
A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe
character: { | }
Ellipses...
Choice of mutually exclusive
arguments; an OR selection
Replaces repeated text
Represents code supplied by
user
DS50002951A-page 6
Examples
File>Save
Press ,
#define START
autoexec.bat
c:\mcc18\h
_asm, _endasm, static
-Opa+, -Opa0, 1
0xFF, ‘A’
file.o, where file can be
any valid filename
mcc18 [options] file
[options]
errorlevel {0|1}
var_name [,
var_name...]
void main (void)
{ ...
}
2020 Microchip Technology Inc.
Preface
RECOMMENDED READING
This user’s guide describes how to use the HV7358DB1 Evaluation Board. The following Microchip document is available and recommended as a supplemental reference
resource.
• HV7358 Data Sheet – “16-Channel, 3-Level HV Ultrasound Transmitter with
Built-In Transmit Beamformer” (20005918)
THE MICROCHIP WEBSITE
Microchip provides online support via our website at www.microchip.com. This website
is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the website contains the following
information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the website at:
http://www.microchip.com/support.
DOCUMENT REVISION HISTORY
Revision A (January 2020)
• Initial release of this document.
2020 Microchip Technology Inc.
DS50002951A-page 7
HV7358DB1 User’s Guide
NOTES:
DS50002951A-page 8
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Chapter 1. HV7358 Overview
1.1
INTRODUCTION
The HV7358DB1 Evaluation Board (ADM00732), working with the MUPB002
(ADM00900), provides a demonstration platform to test and characterize the HV7358.
The HV7358 is a 16-channel, 3 level, ±80V, 1.6A ultrasound transmit beamformer. It is
designed primarily for portable medical ultrasound image applications, but it is applicable to cart-based medical ultrasound systems, as well as NDT applications. The output
MOSFET transistors’ maximum current can be programmed to ±0.3A, ±0.5A, ±1.0A or
±1.6A. Each channel has a T/R switch, RX-damp switch, bleed resistor and diode
clamps to VPP and VNN.
Internal floating power supplies generate the gate drive voltages required for the TX
output FETs. These supplies function at any VPP/VNN voltage.
The 200 MHz clock retiming capability provides low jitter in CW, PW and B mode. The
clock synchronization realigns all internal logic clock signals to a master clock, reducing
the various propagation delays caused by any jitter from the external FPGA.
The HV7358 features an internal low jitter PLL clock multiplier for generating the delay
clock for the digital beamformer. The clock input can accept LVDS differential signals
from 30 MHz (min.) to 80 MHz (max.) in the PLL mode and from 30 MHz to 200 MHz
in the non-PLL mode. At 200 MHz, the incremental delay is 5 ns. The clock multiplier
is programmable by x1, x2, x3, x4, x5, x6 and x8. The transmitter outputs are
synchronized with the delay clock to reduce phase noise.
Note:
2020 Microchip Technology Inc.
The HV7358DB1 Evaluation Board uses hazardous high voltages. Use
caution when operating the HV7358DB1.
DS50002951A-page 9
HV7358DB1 User’s Guide
FIGURE 1-1:
1.2
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.3
HV7358DB1 Board Photo.
HV7358DB1 16-channel, ultrasound, beamforming transmitter
Designed to work with the Microchip Ultrasound Platform Board (MUPB002)
Three-level output: VPP, VNN and RTZ
VPP/VNN up to ±80V high voltages
Up to ±1.6A source and sink current capability
On-board 330 pF||2.5K dummy load per channel
Built-in RX damping circuit
Built-in 200 MHz LVDS SPI clock
Built-in LVDS TX clock, selectable from 80, 120, 160 or 200 MHz (non-PLL)
Built-in LVDS TX clock, selectable from 30, 40, 60 or 80 MHz (PLL mode)
Daisy-chain capable
User-controllable per-channel beamforming delay and apodization
Evaluates the RX echo signals with an on-board LNA emulator
Demonstrates B mode and CW mode waveform control
On-board SPI EEPROM for the ultrasound demonstration board ID
Test points for convenient measurement
On-board 5V and 3.3V voltage supplies available for user
DEVICE SUMMARY
The HV7358DB1 Evaluation Board contains the following Microchip products:
• HV7358: 16-Channel, 3-Level, ±80V, 1.6A Ultrasound TX Beamformer
• MCP1727: 1.5A Low-Voltage, Low-Quiescent Current LDO Regulator
• SY58611U: Dual 350 mV, 3.2 Gbps LVDS MUX Switch
DS50002951A-page 10
2020 Microchip Technology Inc.
HV7358 Overview
TABLE 1-1:
HV7358DB1 TECHNICAL SPECIFICATIONS
Parameter
Value
Modes of Operation
16-Channel TX Beamforming B mode, PW Mode and
CW Mode
B Mode Output Pulses Peak Voltage and Current
(CW = 0)
Up to ±80V and ±1.6A
CW Output Peak Voltage and Current (CW = 1)
16-Channel 0 to ±8V and ±300 mA (typical)
HV7358 TX Clock Input Frequency (PEN = 1)
30 to 80 MHz in PLL Mode
HV7358 TX Clock Input Frequency (PEN = 0)
80 to 200 MHz in non-PLL Mode
CW Frequency Range
Programmable CW Frequency from 1 MHz to 7 MHz
Interface of FPGA Control Signals and USB PC GUI
Software
J5 and J12 Connects MUPB002 Interface Board
Logic Circuitry, 2.5V VLL Voltage Supply LDO Regulator Built-in with Optional Voltage Source from MUPB002 or
J10
TX R-C Test Load and User’s Transducer Interface
Built-in, 330 pF||2.5K per Channel with Jumper and
50 SMA
On-Board LED Indicator of Signals
EN, CW, INV, BEN, PEN, OTPN and LCKDN
Overtemperature Protection
Open-Drain Output to J5 and J12 to MUPB002
Floating Gate Driver Voltage Regulators
Built-in Floating Regulators in HV7358
PCB Board Dimension
127 x 102 mm (5.0 x 4.0 Inch)
FIGURE 1-2:
HV7358DB1 Block Diagram.
2020 Microchip Technology Inc.
DSXXXXXX-page 11
HV7358DB1 User’s Guide
1.4
FUNCTIONAL DESCRIPTION
The HV7358DB1/MUPB002 combination demonstrates a 16-channel, 3-level, ±80V,
1.6A ultrasound transmit beamformer. Features include T/R switches with RX damping
switch, diode clamps to VPP and VNN and programmable TX current limit, and internal
voltage regulators to generate the required gate drive voltages. The HV7358 is a
high-voltage, monolithic IC packaged in a 13x13 mm, 168-lead TFBGA package.
The HV7358 is applicable to medical ultrasound as well as NDT applications.
Both the HV7358DB1 and the MPUB002 boards are required. They are connected
together by two high-speed, impedance matched, right-angle, backplane connectors.
The HV7358DB1 contains the HV7358, LED indicators for the logic signals, and a
transimpedance amplifier to emulate an LNA and an LDO. The MUPB002 contains the
USB interface and an FPGA.
Each TX output has a 330 pf||2.5K load, which requires a shorting connector to be
attached; without the connector, the output will be open.
The 200 MHz clock retiming provides low jitter in CWD, PW or B mode. The clock
synchronization realigns the logic input signals to the master clock, which reduces
various propagation delays caused by FPGA output jitter.
An SPI EEPROM on the HV7358DB1 Demonstration Board is for MUPB002 and PC
GUI software to automatically identify the demonstration board ID.
All of the 16 TX outputs are accessible at test points on the HV7358DB1. There are also
four SMA connectors on the board that can be connected to the TX outputs via jumper
shorting plugs.
The output of any of the T/R switches can be connected to the on-board
transimpedance amplifier (U4). This is done via a jumper shorting plug. The amplifier
output is available at an SMA connector (J13).
1.5
WHAT THE HV7358DB1 ADM00732 KIT INCLUDES
The HV7358DB1 includes:
• HV7358DB1 ADM00732 Evaluation Board
• Important Information Sheet
DS50002951A-page 12
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Chapter 2. HV7358DB1 Software Installation
2.1
GETTING STARTED
The HV7358DB1 Evaluation Board requires the use of the MUPB002 board, PC GUI
software and multiple voltage rails power supply for the full functional demonstration.
Both the MPUB002 board and the HV7358DB1 are required to test the boards.
A USB driver may need to be installed to communicate with the MPUB002. Detailed
installation instructions are presented.
A GUI to program the MPUB002 is also required. Detailed installation instructions are
presented.
Note:
2.2
To update the latest software driver and demonstration program, go to the
www.microchip.com website.
USB DRIVER INSTALLATION
To communicate with the MPUB002/HV7358DB1, the correct USB driver must be
installed.
Follow the steps below to determine which USB driver to install:
1. Connect the USB cable from the lower male Micro-B connector on the MPUB002
board to any USB connector on your PC. The USB will power the board.
Note: Do not connect any other power supplies at this time.
2. Open “Device Manager”. Look at “Bridge device”. If it has a yellow triangle/
exclamation mark as shown in Figure 2-1 and Figure 2-2, the correct USB driver
needs to be installed.
Note: If the yellow triangle/exclamation mark does not exist, skip to
Section 2.3 “HV7358DB1 GUI Installation”; otherwise, complete this
section.
3. Download the “MPLAB® Connect Configurator Tool” using the following link:
https://www.microchip.com/design-centers/usb/mplab-connect-configurator
4. Unzip the downloaded folder titled, MPLABConnect_V2.3. This folder will be
used later.
5. Right click on “Bridge device”.
2020 Microchip Technology Inc.
DS50002951A-page 13
HV7358DB1 User’s Guide
DS50002951A-page 14
FIGURE 2-1:
View of “Device Manager” Screen.
FIGURE 2-2:
Close-up of “Bridge device” with Error.
2020 Microchip Technology Inc.
HV7358DB1 Software Installation
6. A pop-up window will open as shown in Figure 2-3 below. Choose “Update
driver” and click on it.
FIGURE 2-3:
2020 Microchip Technology Inc.
“Update driver” Pop-up Window.
DS50002951A-page 15
HV7358DB1 User’s Guide
7. After clicking on “Update driver”, the window in Figure 2-4 will appear. Choose
“Browse my computer for driver software”.
FIGURE 2-4:
Driver Search Window.
8. The following window will open. Click on the Browse button.
FIGURE 2-5:
DS50002951A-page 16
Driver Browse Choice Window.
2020 Microchip Technology Inc.
HV7358DB1 Software Installation
9. The following window will open. Go to the MPLABConnect_V2.3.4 folder
recently downloaded from the Microchip website and choose the “Drivers”
sub-directory. Double click on “Drivers”.
FIGURE 2-6:
Browse to “Drivers” Folder Window.
The window in Figure 2-7 will appear. The path shown will point to the drivers
used by the MPLABConnect tool.
10. Click the Next button.
FIGURE 2-7:
2020 Microchip Technology Inc.
Browse for Drivers Screen.
DS50002951A-page 17
HV7358DB1 User’s Guide
The window shown in Figure 2-8 will appear.
11. Click the Install button.
FIGURE 2-8:
Install Verification Screen.
12. After successful installation, the window shown in Figure 2-9 will appear. This
verifies that you have installed the USB driver.
FIGURE 2-9:
DS50002951A-page 18
USB Driver Installation Verification Screen.
2020 Microchip Technology Inc.
HV7358DB1 Software Installation
2.3
HV7358DB1 GUI INSTALLATION
Download the MUPB002/HV7358DB1 GUI Installation tool from the Microchip website.
The HV7358 GUI program will require about 2.6 MB hard drive space.
1. Double click on the file named, MUPB002 – HV7358 GUI Setup. The window in
Figure 2-10 below will pop up.
2. Click Next.
FIGURE 2-10:
HV7358 Setup Wizard Opening Window.
3. The License Agreement will appear, as in Figure 2-11. Read and if you agree,
select I agree, then Next to continue. If you do not agree, the installation will stop.
FIGURE 2-11:
2020 Microchip Technology Inc.
License Agreement.
DS50002951A-page 19
HV7358DB1 User’s Guide
4. The next window, shown in Figure 2-12, sets the Select Installation Folder. The
default folder is shown. A different folder may also be specified.
FIGURE 2-12:
Installation Folder.
5. The next window, shown in Figure 2-13, confirms that you are ready to install the
HV7358 GUI. If so, click Next; otherwise, you can go back and make changes or
Cancel.
FIGURE 2-13:
DS50002951A-page 20
Installation Confirmation.
2020 Microchip Technology Inc.
HV7358DB1 Software Installation
6. The following window, shown in Figure 2-14, will be visible during the actual GUI
installation.
FIGURE 2-14:
Installation Window.
Once installation is complete, the following window will appear, as shown in Figure 2-15.
Click on Close when the installation is complete. The GUI window will disappear.
FIGURE 2-15:
Installation Complete Window.
The icon below in Figure 2-16 will be left on your desktop. Double click to open the
HV7358 GUI. The GUI Installation is complete.
FIGURE 2-16:
2020 Microchip Technology Inc.
HV7358 GUI Icon.
DS50002951A-page 21
HV7358DB1 User’s Guide
NOTES:
DS50002951A-page 22
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Chapter 3. HV7358DB1 GUI Operation
3.1
GETTING STARTED
The HV7358DB1 is a 16-channel, 3-level, ±80V, 1.6A ultrasound beamformer
evaluation board. To operate, it requires the use of the MUPB002 board (ADM00900),
the PC GUI software and multiple voltage rails for the full functional demonstration.
Note:
3.2
To update the latest software driver and demonstration program, please go
to the www.microchip.com website.
SETUP PROCEDURE
To operate the HV7358DB1, the following steps must be completed:
1. Connect J1 and J2 of the MPUB002 board to J5 and J12 of the HV7358DB1.
2. Connect a USB cable from the lower male Micro-B connector (J7) on the
MPUB002 board to any USB connector on your PC.
3. Install jumpers, J6, J14, J15, J16 and JP1 (JP1 requires two jumpers), as per
Table 3-1.
TABLE 3-1:
JUMPER FUNCTION
Power Jumper
Powered Bank
Selection (2.5V/3.3V)
J6
Bank1
+2.5V
J14
Bank0
+2.5V
J15
Auxiliary
+3.3V
J16
Bank3
+2.5V
JP1
GND
0V
4. Jumpers, J19 through J35, connect a 330 pF||2.5K load to each respective TX
output. Without the jumper, the TX output will be open. If the load is wanted, add
the jumpers.
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DS50002951A-page 23
HV7358DB1 User’s Guide
3.3
HV7358DB1 POWER SUPPLY REQUIREMENTS
Connect all power supplies to the HV7358DB1 power supply connector (J10). The
voltage and current requirements can be found in Table 3-2 below. Leave the power
supplies turned off.
TABLE 3-2:
J10 POWER SUPPLY CONNECTION INFORMATION
Terminal
Rail Name
Voltage
Average Current Limit
J10-1
VCC
+5V
50 mA
J10-2
VDD
+5V
180 mA
J10-3
VGN
-5V
30 mA
J10-4
VPP
0 to +80V
5 mA
J10-5
GND
0V
—
J10-6
VNN
0 to -80V
5 mA
The power-up and down sequencing is shown in Table 3-3 below.
TABLE 3-3:
DS50002951A-page 24
POWER-UP/DOWN SEQUENCE
Step #
Power-up
Step #
Power-Down
1
VCC, VDD On
1
EN = 0
2
VGN On
2
VPP, VNN Off
3
VPP, VNN On
3
VGN Off
4
EN = 1
4
VCC, VDD Off
2020 Microchip Technology Inc.
HV7358DB1 GUI Operation
3.4
MUPB002 AND GUI/USB PROGRAMMING
Open and run the GUI by double clicking the HV7358DB1 icon. The GUI will open
showing the following screen:
FIGURE 3-1:
Full GUI Screen.
At the bottom left hand corner, there should be the “USB Status: Connected” note, as
shown in Figure 3-2 below.
FIGURE 3-2:
USB Status Note.
When the MUPB002 board is connected to the PC, or when the GUI is started, the USB
should connect automatically. If it does not, there is a USB Connect button at the upper
right corner of the GUI. If it is required to disconnect the USB, there is also a USB
Close button. See Figure 3-3 below.
FIGURE 3-3:
2020 Microchip Technology Inc.
USB Connect and Close Buttons.
DS50002951A-page 25
HV7358DB1 User’s Guide
In the upper left corner there is a “Demo Board Info” box, as shown in Figure 3-4 below.
Click on the Check DB ID button. An HV7358DB1 revision number and an FPGA code
version number should be shown.
If the USB status is “Connected” and the “Demo Board Info” is shown per above, then
the GUI has successfully connected to the MUPB002 board.
FIGURE 3-4:
3.4.1
“Demo Board Info” Box.
HV7358 Pin Settings Box
The “HV7358 Pin Settings” box is shown in Figure 3-5.
3.4.1.1
EN (ENABLE) PIN
The HV7358 Enable pin sets all TX outputs to High-Z.
TABLE 3-4:
3.4.1.2
ENABLE SIGNAL
EN
TX Outputs
0
High-Z
1
Active
BEN (BUFFER ENABLE) PIN
BFEN is an input logic pin that can disable the LVDS pins used to broadcast or
daisy-chain multiple HV7358 chips. This ability can be used to reduce power dissipation. The BEN pin function can be overwritten with the BSEL and BFEN I2C signals.
BSEL determines if BEN or BFEN actually controls the LVDS outputs.
TABLE 3-5:
DS50002951A-page 26
BUFFER ENABLE LOGIC
BEN
BFEN
BSEL
LVDS Output
Control Signal
LVDS Output
0
0
0
BEN
Disabled
1
0
0
BEN
Enabled
0
1
0
BEN
Disabled
1
1
0
BEN
Enabled
0
0
1
BFEN
Disabled
1
0
1
BFEN
Disabled
0
1
1
BFEN
Enabled
1
1
1
BFEN
Enabled
2020 Microchip Technology Inc.
HV7358DB1 GUI Operation
3.4.1.3
SLEEP (SLEEP MODE ENABLE) PIN
If the SLEEP pin is enabled, then the device is in power-saving mode. All the internal
registers’ data will be preserved and the internal clocks will freeze. The I2C interface is
still active.
TABLE 3-6:
SLEEP LOGIC
SLEEP
3.4.1.4
HV7358 State
0
Enabled/Active
1
Sleep/Low Power
SPIB (SPI FAST PROGRAMMING INTERFACE) PIN
This pin switches between the SPI Broadcast mode and the Daisy-Chain mode.
TABLE 3-7:
SPIB LOGIC
SPIB
3.4.1.5
Mode
0
Daisy-Chain
1
SPI Broadcast
PEN (PLL ENABLE) PIN
PEN is an input logic pin that can enable or disable the internal PLL. The PEN pin
function can be changed by the PLLEN and PSEL I2C signals. PSEL determines if the
PEN or PLLEN bit in the I2C register actually controls the PLL.
TABLE 3-8:
PEN LOGIC
PEN
PLLEN
PSEL
PLL Control
Signal
Internal PLL
0
0
0
PEN
Disabled
1
0
0
PEN
Enabled
0
1
0
PEN
Disabled
1
1
0
PEN
Enabled
0
0
1
PLLEN
Disabled
1
0
1
PLLEN
Disabled
0
1
1
PLLEN
Enabled
1
1
1
PLLEN
Enabled
3.4.1.6
SET BUTTON
Sends the selected data to the HV7358 data input pins.
Select the signals appropriate for your application and press the SET button.
3.4.1.7
DISC BUTTON
The DISC button will send a pulse to the HV7358 that activates the internal VPP and
VNN switches that discharge their respective supply rails.
These switches have a 5 mA capability and are meant to discharge the bypass caps
only. The supplies need to be turned off before activating the discharge switches.
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DS50002951A-page 27
HV7358DB1 User’s Guide
3.4.1.8
RSTN BUTTON
The RSTN button will send a pulse to the RESET pin on the HV7358. This will reset all
HV7358 internal SPI and I2C registers to their default value.
FIGURE 3-5:
3.4.2
“HV7358 Pin Settings” Box.
VPP/VNN Values
The actual VPP and VNN values must be entered in the box as shown in Figure 3-6. The
box is at the top center of the GUI page. An example of the window is shown below.
VPP = 55V and VNN = -55V were entered in Figure 3-6. These values will be used to
calculate the power dissipation.
Enter the VPP and VNN values.
FIGURE 3-6:
3.4.3
VPP and VNN Voltage Window.
Mode and Power Calculation
Click either the B mode or the CW mode button.
Click the Validate Setting button. The GUI will calculate the duty cycle (D%) and the
power dissipation. It will also confirm that the power is within the limit of the HV7358. If
the power is acceptable, the box will read “Power Within Limit”; otherwise, it will read
“Power Outside Limit” and the Start button will be disabled.
For CW mode, 100% will be used for the duty cycle.
FIGURE 3-7:
DS50002951A-page 28
Mode and Power Dissipation Window.
2020 Microchip Technology Inc.
HV7358DB1 GUI Operation
3.4.4
Transmit Clock Frequency Configuration Window
The “Transmit Clock Frequency” box is shown below in Figure 3-8.
FTCK is the external frequency. The internal clock frequency is FC. FC is a function of
FTCK, PEN and mode setting.
The frequency choice is a function of the PEN variable. When PEN = 1, it turns the PLL
on. The frequency selections for both PEN choices are shown below.
If the PLL mode is off (PEN = 0), then the external frequency choices are 80 MHz,
120 MHz, 160 MHz or 200 MHz. They are shown on the left side of Figure 3-8.
If the PLL mode is on (PEN = 1), the external frequency choices are 30 MHz, 40 MHz,
60 MHz or 80 MHz. They are shown on the right side of Figure 3-8. When in PLL mode,
the frequency selections are on the left of Figure 3-8.
In B mode with PEN = 0, the PLL is disabled and the internal clock frequency will be:
EQUATION 3-1:
B MODE, NO PLL
FC = FTCK
If PEN = 1, the PLL circuitry is enabled; then, the I2C parameter, “N”, will be part of the
equation:
EQUATION 3-2:
B MODE WITH PLL
FC = FTCK * N
In CW-Mode, the TX(x) output frequency will be:
EQUATION 3-3:
CW MODE
FCW = FTCK/(2 * CWFD)
In CW mode, the PLL function cannot be used. Therefore, PEN and the PLL are
disabled.
Choose the frequency by clicking on the appropriate box, then click on the
Set CLK + FPGA button.
PEN = 0
FIGURE 3-8:
2020 Microchip Technology Inc.
PEN = 1
Transmit Clock Frequency Window.
DS50002951A-page 29
HV7358DB1 User’s Guide
3.4.5
I2C Box
The “I2C Read/Write” box is shown in Figure 3-9.
This box can read the current I2C settings or write new ones. The default settings can
be used for most applications. The HV7358DB1 is the slave and the HV7358 GUI is the
master. The slave address (‘111’ by default) can be changed by adding jumpers on
J28, J30 and J31. Clicking the Read button shows the current settings. Making a
change to any of the values and clicking Write changes the current settings.
FIGURE 3-9:
3.4.6
“I2C Read/Write” Box.
Line Duration Cycles and TXRW Low Time
The “Line Duration” and “TXRW Low Time” entry box is shown in Figure 3-10.
Line Duration (LD) is the time it takes for one complete transmit pulse to be completed.
It includes time for the actual TX waveform and the receive part. This is sometimes
referred to as the “pulse repetition frequency”. The following limit must be observed:
(TGW * RPC)>>LDR
Line Duration cycles can be calculated from the following Equation 3-4.
Choose the LD time or frequency. Calculate LD cycles using Equation 3-4 and enter
them into the Line Duration Cycles box shown in Figure 3-10.
EQUATION 3-4:
LD Cycles = (LD Time) x FTCK
Where:
LD = Line Duration
DS50002951A-page 30
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HV7358DB1 GUI Operation
The “TXRW Low Time” is the programmable time allowed for the SPI or I2C bus to
complete all required read/write commands after the pulse is completed. It is actually
part of the LD time calculated above. It can be calculated using Equation 3-5.
EQUATION 3-5:
TXRW Cycles = (TXRW Low Time) x FTCK
Choose the required “TXRW Low Time” and use Equation 3-5 to determine the “TXRW
Low Time Cycles”. Enter the “Line Duration Cycles” in the box and enter the “TXRW
Low Time Cycles” in the box, as shown in Figure 3-10.
FIGURE 3-10:
3.4.7
“Line Duration” and “TXRW Low Time”.
Waveform Definition
The “Waveform Definition” box is shown in Figure 3-11.
The HV7358 can store four different waveforms in the beamformer. They are
numbered: Waveform 0 through Waveform 3.
TGP: Stands for Time Global Positive. TGN: Stands for Time Global Negative. These
signals are disabled in the GUI. They could be used to set the delay time on a per TXx basis.
TGW: Sets the maximum TX Global Pulse Width (PW). It does this by setting the
number of FC time periods that the pulse remains high. The actual TGW is a 9-bit binary
word. The GUI accepts a number between 0 and 511 and makes the conversion. TGW
can be calculated from the following equation:
EQUATION 3-6:
TGW PW x FTCK
PW is the default maximum pulse width for any of the TX pulses, either positive or negative.
RPC: Sets the number of pulses in the waveform before returning to GND. If RPC = 1,
a single positive pulse will be defined. If RPC = 2, one positive and one negative pulse
will be done. RPC = 3 will be a positive, a negative and another positive pulse, etc.
The beamformer can hold up to four different waveforms. The parameters defined in
this box are “global”. A global waveform is the same for each TX(0) through TX(15), but
they can be different for each Waveform 0 through 3.
FIGURE 3-11:
“Waveform Definition” Box.
Knowing the maximum pulse width, calculate TGW. Enter into the TGW box for each
waveform. Enter into the RPC box for each waveform. See Figure 3-11.
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DS50002951A-page 31
HV7358DB1 User’s Guide
3.4.8
I2C Parameters Read-Back Window
The I2C parameters that are programmed into the GUI can be seen in the I2C
Parameters Read Back window shown in Figure 3-12. They can also be changed to
meet specific application requirements.
The I2C Parameters Read Back window is located at the low middle of the GUI screen.
All the parameters are read back from the HV7358 I2C registers.
3.4.8.1
BOC[1:0] BITS
The BOC bits are the I2C control for B mode TX output peak current limit setting. This
is a global signal that applies to every TX channel.
TABLE 3-9:
TX CURRENT LIMIT SETTING
BOC[1:0] (Binary)
BOC (GUI)
TX Current Limit
00
0
±1.6A
01
1
±900mA
10
2
±600mA
11
3
±300mA
3.4.8.2
CWOC BIT
CWOC is the I2C control bit that determines the CW output RON selection.
TABLE 3-10:
3.4.8.3
CWOC RON
CWOC
RON
0
30Ω
1
45Ω
CWFD[7:0] BITS
These bits set the CW frequency divisor I2C register. A complete explanation can be
found in Section 3.4.4 “Transmit Clock Frequency Configuration Window”.
3.4.8.4
N[2:0] BITS
These bits set the PLL frequency multiplier number in the I2C register. The bits are used
in determining the FTCK frequency when in PLL mode. See Section 3.4.4 “Transmit
Clock Frequency Configuration Window”.
TABLE 3-11:
DS50002951A-page 32
FREQUENCY MULTIPLIER
N[2:0] in GUI
N[2:0] in HV7358
1
1
2
2
3
3
4
4
5
5
6
6
7
8
2020 Microchip Technology Inc.
HV7358DB1 GUI Operation
3.4.8.5
TRDLY[4:0] BITS
The TRDLY bits set the I2C T/R Switch On-Time Delay Selection Control register. The
TRDLY are a 5-bit binary word. The GUI accepts 0 to 31 in decimal. The actual delay
time is calculated from the equation:
EQUATION 3-7:
TTRDLY = K/FC
K is determined by Table 3-12.
TABLE 3-12:
TRDLY
D4
D3
D2
D1
D0
Decimal
K
0
0
0
0
0
0
1
0
0
0
0
1
1
8
0
0
0
1
0
2
12
0
0
0
1
1
3
16
0
0
1
0
0
4
20
0
0
1
0
1
5
24
0
0
1
1
0
6
36
0
0
1
1
1
7
40
0
1
0
0
0
8
48
0
1
0
0
1
9
60
0
1
0
1
0
10
64
0
1
0
1
1
11
72
0
1
1
0
0
12
80
0
1
1
0
1
13
96
0
1
1
1
0
14
100
0
1
1
1
1
15
120
1
0
0
0
0
16
128
1
0
0
0
1
17
144
1
0
0
1
0
18
160
1
0
0
1
1
19
192
1
0
1
0
0
20
200
1
0
1
0
1
21
240
1
0
1
1
0
22
288
3.4.8.6
PSEL BIT
PSEL is the I2C bit that determines if PLLEN or PEN controls the PLL enable.
TABLE 3-13:
PSEL EFFECT
PSEL
2020 Microchip Technology Inc.
Controlling Signal
0
PEN
1
PLLEN
DS50002951A-page 33
HV7358DB1 User’s Guide
3.4.8.7
PLLEN BIT
PLLEN is the I2C bit that determines if the PLL is used when PSEL = 1.
TABLE 3-14:
3.4.8.8
PLLEN
PLLEN
PLL
0
Off
1
On
LOCKD BIT
LOCKD is the I2C bit that determines if the PLL is used when PSEL = 1.
TABLE 3-15:
LOCKD
LOCKD
3.4.8.9
PLL Locked?
0
No
1
Yes
EOT BIT
EOT is a read-only I2C bit that signals that the transmit signals are complete. EOT is a
global signal looking at all 16 channels.
TABLE 3-16:
3.4.8.10
EOT
EOT
TX Complete?
0
No
1
Yes
BSEL BIT
BSEL is the I2C bit that determines if BFEN or BEN controls the output buffer enable.
TABLE 3-17:
BSEL
BSEL
3.4.8.11
Buffer Enable Signal
0
BEN
1
BFEN
SPISEL BIT
SPISEL determines which signal controls the broadcast enable.
TABLE 3-18:
3.4.8.12
SPISEL
SPISEL
Control Signal
0
SPIB
1
SPIBC
V(x)UV BITS
These five bits are output flags. They can be read, but not written. They signal an
undervoltage on their respective power supply. V(x)UV can stand for: VNFUV, VPFUV,
VPLLUV, VDDUV or VLLUV.
DS50002951A-page 34
2020 Microchip Technology Inc.
HV7358DB1 GUI Operation
3.4.8.13
OTP BIT
OTP is an I2C bit that signals an overtemperature condition inside the HV7358 part.
The flag is reset by the I2C reading of the ADDR = 01h register. If the overtemperature
event continues, the flag will be retriggered at the next EN rising edge. See Table 3-19.
3.4.8.14
BFEN BIT
BFEN is the I2C bit that determines the output buffer enable when BSEL = 1.
TABLE 3-19:
BFEN FOR BSEL = 1
OTP
3.4.8.15
Temperature
0
In Range
1
Overtemperature
EOTC BIT
Determines when the RTZ+ and TRSW delay starts. If EOTC = 0, the period starts
immediately after all channels are finished. If EOTC = 1, the period starts at the first FC
clock rising edge after ETI becomes high and after all channels finish the TXCH period.
3.4.8.16
SPIBC BIT
Enables the SPI Broadcast mode when SPISEL = 1.
TABLE 3-20:
SPIBC FOR SPISEL = 1
SPIBC
3.4.8.17
0
Disabled
1
Enabled
Manually Read BUTTON
The Manually Read button will read and display the current values of the I2C registers.
FIGURE 3-12:
2020 Microchip Technology Inc.
I2C Parameter Read Back Window.
DS50002951A-page 35
HV7358DB1 User’s Guide
3.4.9
Loading and Saving Table
The table function buttons are shown in Figure 3-13 below.
A table is a file that stores all the data from the HV7358 GUI. It will save the “HV7358
Pin Settings”, “Transmit Clock Frequency”, “Line Duration”, “TRSW Low Time”,
“Waveform Definition” and “TCK Cycles” data.
When the GUI is closed, the data are automatically saved in the default file:
C:\Users\Public\Documents\hv7358db1_GUI.json
The Save Table button will save all the settings to the default file. The Save Table As
button will ask for a unique filename to save to. The Load Table will ask for the filename
to be loaded.
FIGURE 3-13:
3.4.10
Table Function Buttons.
Invert and Individual Delay and Pulse-Width Control
This GUI window is shown in Figure 3-14.
INV: Will invert every waveform. By default, the first pulse is positive. With INV
checked, the first pulse will be negative. This is a global control bit. It will be the same
for each TX channel and each waveform.
Delay: Each channel can have its own unique delay. The starting point is TGW, which
sets the longest delay. For details, see Section 3.4.7 “Waveform Definition”. TGW is
the maximum delay time and is common to all channels. The total delay can be
decreased, on a per channel basis, with the Delay bit. Delay is a 12-bit word. The GUI
will accept anything from 0 to 4095.
The delay for each channel will be:
EQUATION 3-8:
TIMEDELAYX = (TGW – DELAYX) x (1/FTCK)
This allows a unique time delay for each channel.
TLP and TLN: Each channel and polarity can have its own unique pulse width. The
starting point is PW, which sets the longest pulse width. For details, see
Section 3.4.7 “Waveform Definition”. PW is the maximum delay time and is common
to all channels. The total delay can be decreased, on a per channel, per polarity basis,
with the TLPx and TLNx bits.
The pulse for each channel will be:
EQUATION 3-9:
POSITIVE PULSE WIDTHX = (PW – TLPx) x (1/FTCK)
EQUATION 3-10:
NEGATIVE PULSE WIDTHX = (PW – TLNx) x (1/FTCK)
DS50002951A-page 36
2020 Microchip Technology Inc.
HV7358DB1 GUI Operation
This allows a unique pulse width for each polarity of each channel.
FIGURE 3-14:
3.5
Invert and Individual Delay and Individual Pulse-Width Control.
RUNNING THE HV7358DB1
1. Connect the scope probes to the appropriate signals.
2. Turn on the power supplies, observing the power-up sequence in Table 3-3.
3. Click on the Start button. The HV7358DB1 is now running.
3.6
STOPPING THE HV7358DB1
1. Click on the Stop button.
2. Power down the power supplies, observing the power-down sequence in
Table 3-3.
3. Complete.
2020 Microchip Technology Inc.
DS50002951A-page 37
HV7358DB1 User’s Guide
3.7
SAMPLE WAVEFORM
A sample of the waveform generation is shown in Figure 3-15.
FIGURE 3-15:
DS50002951A-page 38
Sample Waveform from Multiple Channels of the HV7358.
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Chapter 4. MUPB002 FPGA Configuration
4.1
INTRODUCTION
The MUPB002 board connects to and controls the HV7358DB1. It connects to the host
PC and interfaces with the GUI. The MUPB002 is preprogrammed and ready for
immediate use. However, if changes in the code are required, the directions below will
allow changes to the configuration.
4.2
HARDWARE AND SOFTWARE REQUIRED
4.2.1
Hardware Required
• MUPB002 Board
• Type A Male to Type Micro-B Male USB Cable
• Xilinx® Platform Cable USB II
4.2.2
Software Required
• “Xilinx ISE Design Suite 14.7” must be installed to the host PC.
• FPGA configuration file, hv7358_top_main.bit, available from the
Microchip website.
• Flash memory configuration file, HV7358_BVLDS_TRIG.mcs, available from the
Microchip website.
4.3
SETUP PROCEDURE
This procedure explains how to reconfigure the Flash memory (U15) on MUPB002.
After the Flash memory is reconfigured, the latest configuration is automatically used
when the MUPB002 powers up.
Note:
The Flash memory has been configured at the factory. This chapter is
ONLY required when the default program needs to be changed.
1. Connect a USB cable (M-to-M, Type A to Type Micro-B) between the PC and the
Micro-B USB female (J7) connector of MUPB002. This connection powers up the
MUPB002 board. LED4 will light up, showing the MUPB002 is being powered
through the USB cable.
2. Connect the Xilinx Platform Cable USB II hardware between the PC and J4
connector of MUPB002. The light of the platform cable turns on in green.
2020 Microchip Technology Inc.
DS50002951A-page 39
HV7358DB1 User’s Guide
4.4
SOFTWARE EXECUTION
1. Start the iMPACT tool of Xilinx by clicking on the iMPACT icon. See Figure 4-1.
FIGURE 4-1:
iMPACT Icon.
2. The window in Figure 4-2 will appear.
3. Left click on “Boundary Scan” as shown in Figure 4-2.
4. Right click on top of the “Right click to Add Device or Initialize JTAG chain”
statement.
FIGURE 4-2:
iMPACT Window.
5. Choose “Add Xilinx Device…” from the menu and click.
FIGURE 4-3:
DS50002951A-page 40
Xilinx Setup Window.
2020 Microchip Technology Inc.
MUPB002 FPGA Configuration
The window in Figure 4-4 will appear. The actual files are a function of what is on your
PC. They will not match Figure 4-4.
6. Browse in your PC to the file, hv7358_top_main.bit. Then click on the Open
button.
FIGURE 4-4:
Assign New FPGA Configuration File Selection.
The window in Figure 4-5 will appear. Only the upper right corner of the window
is shown for clarity. It shows an external block diagram of the FPGA (xc6slx25).
Now we will choose the Flash memory that we want to configure.
7. Right click on the “SPI/BPI?” statement on top of the FPGA symbol.
FIGURE 4-5:
2020 Microchip Technology Inc.
SPI/BPI Window.
DS50002951A-page 41
HV7358DB1 User’s Guide
The small box with “Add SPI/BPI Flash” will appear (see Figure 4-6).
8. Click on the “Add SPI/BPI Flash...” box.
FIGURE 4-6:
“Add SPI/BPI Flash...” Box.
The box in Figure 4-7 will appear.
9. Browse to the file named, HV7358_BLVDS_TRIG.mcs.
10. Click on the Open button.
FIGURE 4-7:
SPI/BPI File Choice.
The window in Figure 4-8 will appear.
11. Select “S25FL128S” for the 128 MB Flash memory (U15) installed on the
MUPB002 board.
12. Click the OK button.
FIGURE 4-8:
DS50002951A-page 42
Select Attached SPI/BPI Window.
2020 Microchip Technology Inc.
MUPB002 FPGA Configuration
Figure 4-9 shows the upper left part of the next window.
13. There is a FLASH button in the upper right. Click on it.
FIGURE 4-9:
FLASH Button.
The FLASH button will turn green as shown in Figure 4-10.
14. Click on the green FLASH button.
FIGURE 4-10:
2020 Microchip Technology Inc.
Green FLASH Button.
DS50002951A-page 43
HV7358DB1 User’s Guide
The Device Programming Properties window, shown in Figure 4-11, will appear.
15. Click the OK button.
FIGURE 4-11:
Device Programming Properties Window.
The FPGA will be programmed. This may take over a minute.
When completed, the window in Figure 4-12 will appear.
FIGURE 4-12:
DS50002951A-page 44
Complete Window.
2020 Microchip Technology Inc.
MUPB002 FPGA Configuration
4.5
CONCLUSION
A procedure to program the MUPB002 FPGA for use with the HV7358DB1 has been
presented. This procedure with different file names can be used to program the
MUPB002 for different Microchip ultrasound transmitters.
2020 Microchip Technology Inc.
DS50002951A-page 45
HV7358DB1 User’s Guide
NOTES:
DS50002951A-page 46
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Chapter 5. PCB Design and Layout Techniques
5.1
INTRODUCTION
The PCB layout techniques are a very important part of the ultrasound system design.
The HV7358DB1 generates high-voltage, high-current, high-frequency and high-speed
pulses. Proper PCB layout is required to optimize the waveforms.
5.1.1
High-Speed Trace, Grounding and Heatsinking PCB Design
Techniques
A solid GND plane must be created. It should be a solid copper layer, on Layer 2,
directly under HV7358.
To optimize heatsinking of the HV7358, use as many vias from VSUB, RGND and GND
to the GND plane as possible. These signals carry large currents. Their PCB traces
should be on the top layer; they should be as short as possible and have as many vias
as possible. Maximize the number of vias on all the power supply traces.
High-speed (200 MHz) PCB trace design practices should be used as a starting point.
The TX outputs are high-voltage and high-speed traces. VPP and VNN are high-voltage
and high-current traces. Additional trace spacing may be required for the high-voltage
traces. Also, any parasitic coupling from the HV7358 TX outputs to digital input signals
may cause error signals on the logic input pins. Adequate spacing and possible
isolation are required. Additional width is required for the high-current traces.
5.1.2
Bypass Caps
The VLL, VDD, VGP, VGN, VPP/1 and VNN/1 power supply pins, and the CPF0/1, CNF0/1,
CPOS and CNEG internal gate driver floating supply rails all require bypass capacitors.
All can draw fast transient currents of up to 2.8 Amperes each. X7R or X5R-type
capacitors, 1.0 to 2.2 μF are recommended.They must be located as close to the
HV7358 pins as possible. PCB trace width should be capable of handling these
transients.
5.1.3
PCB Layout Techniques for TCKP/TCKN
The clock can be driven with a pair of LVDS connections or a single-ended clock.
For LVDS implementations, an 100Ω differential termination resistor must be
connected as close as possible to the LVDS input pair.
LVDS clock traces on the PCB should be designed as two 50Ω transmission lines with
respect to the GND plane. The differential traces should be as close as possible after
they leave the LVDS buffer IC.
With a single-ended clock, a 33Ω series termination resistor is required for each buffer
output. These resistors should be as close to the clock buffer output pin as possible.
The clock trace on the PCB should be designed as a 50Ω transmission line with respect
to the GND plane.
2020 Microchip Technology Inc.
DS50002951A-page 47
HV7358DB1 User’s Guide
5.1.4
Decoupling Capacitors
The PCB layout decoupling capacitor’s placement rule is simple: place the capacitor as
close as possible to the pin being decoupled. The actual placement of the capacitor
may generate EMI/RFI. The placement determines the return current path. The return
path is from the GND side of the bypass cap, through the PCB trace, through any vias,
through the GND plane and back to the GND pin on the HV7358.This path also needs
to be as short as possible. There are also high current spikes from the VPP and VNN
supplies to the HV7358 TX outputs. Use the same design rules with TX output traces
and vias.
5.1.5
Return Current Design in PCB Layout
Many EMI problems associated with the high-speed circuits are due to improper design
of the return current path. PCB designers put considerable effort into carefully
designing traces with the proper length, proper transmission line impedance, etc., but
neglect the return current path that completes the current loop. These EMI problems
can usually be avoided with proper design of the return current path.
DS50002951A-page 48
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Appendix A. HV7835DB1 and MUPB002 Schematics and Layouts
A.1
INTRODUCTION
This appendix contains the following schematics and layouts for the HV7358DB1 and
MUPB002:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HV7358DB1 – Schematic
MUPB002 Schematic – Top Block Diagram
MUPB002 Schematic – Demo Board Connectors
MUPB002 Schematic – FPGA
MUPB002 Schematic – SPI Flash for FPGA Configuration
MUPB002 Schematic – Programmable Clock
MUPB002 Schematic – FPGA Decoupling Capacitors
HV7358DB1 – Top Silk
HV7358DB1 – Top Copper and Silk
HV7358DB1 – Top Copper
HV7358DB1 – Bottom Copper
HV7358DB1 – Bottom Copper and Silk
HV7358DB1 – Bottom Silk
MUPB002 – Top Silk
MUPB002 – Top Copper and Silk
MUPB002 – Top Copper
MUPB002 – Bottom Copper
MUPB002 – Bottom Copper and Silk
MUPB002 – Bottom Silk
2020 Microchip Technology Inc.
DS50002951A-page 49
HV7358DB1 – SCHEMATIC
3
SHDN
1.27k 1.27k
200
C85
C84
C51
PVDD
1.27k
Q
TP34
TP35
C88
DNC10
DNC9
CNEG
SDON
C99
C101
C100
TP89
CSOP
TP90
CSON
R11
RDCP
TP37
R26
J25
R25
TX6
TX7
J21
C10
C14
C13
1μ 100V
C98
C25
C27
C26
1μ 100V
1μ 100V
R16
TP40
2.5K 1W
R33
J24
R51
TX8
J41
RX2
TP47
RX3
TP48
RX4
RX5
RX4
TP49
RX6
TP51
RX7
TP53
RX8
RX9
RX8
TP60
RX10
TP61
RX11
TP63
RX12
RX13
RX12
TP64
RX14
TP81
RX15
TP83
1
2
50
OUT3
R64
(+4.7V)
(+5V)
(+5V)
(-8V)
PWR
VDD
VGN
(+8 to +80V)
VPP
VNN
C94
(-8 to -80V)
VNN
J39
VLL
C107
D10A
D13
B1100-13
D11B
J27
DNP
1
2
R50
R46
J33
R54
50
R55
OUT4
2.5K 1W
TP59
R56
TP68
3
1μ 10V
VGN
D10B
C127
C129
C128
2.2μ 10V
SELTCK
J10
C130
C131
R73
1.27k
J8
2
1
C36
C29
J28
1
2
J30
1
2
J32
1
2
BAV99/SOT_1
INF
R62
2.5K 1W
330p 250V
DNP
1
2
R53
TP62
2.5K 1W
10μ 16V
0.22
330p 250V
R52
TX15
R24
499
R28
1K
1
2
DNP
INF
R60
C64
2.5K 1W
330p 250V
J9
2
1
R27
249
10 nF
D9
DNP
INF
C61
J7
C113
1μ 10V
VNN
4
D8A
C46
R72
1.27k
1
2
C65
J29
2.5K 1W
330p 250V
330p 250V
J37
R49
INF
R57
C63
VDD
R29
499
COM
TP45
R58
2
-
3
+
U4
AD8099
C41
R71
1.27k
DNP
50
C109
C114
1
2
J4
1
TP54
TX14
2.5K 1W
330p 250V
330p 250V
TP52
1
2
INF
R63
TP57
2.5K 1W
C60
C62
D14
B1100-13
DNP
INF
TX11
R23
2
1
1
2
C66
R43
2.5K 1W
330p 250V
TP55
R44
TX10
INF
R45
330p 250V
TP44
J31
1μ 100V
2
1
DNP
C57
TX9
TX12
C120
J6
TP69
1
2
J3
1
2.5K 1W
C67
RX0
TP46
RX1
2.5K 1W
330p 250V
330p 250V
TP41
RX0
INF
R47
DNP
1
2
J35
C95
DNP
INF
C19
VNN
C12
1
2
3
A13
B13
D15
H15
M15
R13
T13
VPP
VPP
VPP
VPP
VPP
VPP
VPP
A12
B12
C15
G15
L15
R12
T12
CPF
CPF
CPF
CPF
CPF
CPF
CPF
PVDD
PVDD
PVDD
PVDD
PVDD
PVDD
2.5K 1W
TX13
C96
VLL
10 nF
2.5K 1W
330p 250V
330p 250V
C58
1K
C97
CNF
TCKN
C118
2.2μ 10V
C87
C108
C115
0.1
R19
1μ 10V
D8B
C119
R22
J2
1
TP15
C105
C106
CSON
TCKP
TCK1P
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
L10
M10
N10
P10
R10
T10
OUT2
TX5
R21
RX12
SDOP
TP88
TP6
RX8
TP87
100
TCK1N
A7
B7
G8
H8
R7
T7
C4
E3
H3
L3
P4
P6
VDD
VDD
VDD
VDD
VDD
VDD
T6
T5
CPLL
AGND
VLL C1
VLL H1
VLL L1
VLL P1
A3
CSP
B3
CSN
AVDD T4
VNN
TP7
VGN
RX0
CKON
50
C20
A16
B16
C16
D16
E16
F16
G16
H16
J16
K16
L16
M16
N16
P16
R16
T16
A8
B8
RDCN
1μ 10V
RX4
TP86
1
2
TP23
R34
9
J22
C111
CKOP
2
12
M8
DNC8
N8
DNC9
P8
DNC10
C6
DNC11
1.27k
TP85
3
Q
A2
SDIP
B2
SDIN
INV
LPWM
SDLY
TXRW
SPIB
TCKN
TCKP
TRIGP
TRIGN
W0
W1
B5
RSTN
K2
DISC
TP76
R17
TX4
1K
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
A0
10 nF
INF
DNP
C21
3
TP28
R18
HV7358
A1
0.1
1
2
TP9
U5
2
NC
C117
TP30
2.5K 1W
330p 250V
R20
VPP
1
VT1
VCC 13
SY58611U
SEL
4
C116
11
GND
17
GND
10
GND
U7
3 V
REF1
TP25
DNC1
DNC2
DNC3
DNC4
DNC5
DNC6
DNC7
A0
A1
A2
SDA
SCL
VCC
8 V
CC
VT0
2 V
REF0
14
16
1
J1
F1
K1
E1
E2
N2
N1
M1
M2
A4
B4
TP79
TP77
CKON
SDOP
TCK0N
R14
3
TP72
TCK0P
J12
TE6469169-1
2.5K 1W
330p 250V
C42
10 nF
6
C43
2 pF
50
3
DNC7
SDON
CSOP
VLL
INF
R48
DNP
1
2
TX3
J13
1
LNAOUT
TP50
TP65
2
TP31
R81
+3V3
15
2020 Microchip Technology Inc.
2
1
DNP
1
DNC6
CKOP
IN0
J34
1
2
INF
C18
C79
7
DNC5
TP22
SCK
MOSI
1.27k
C69
4
8
5
DNC4
TP21
TP71
R80
8
7
6
5
C92
RDCN
TP29
R6
C7
C8
D8
E8
F8
L8
D1
D2
D3
G2
G1
A6
B6
A11
B11
R1
T1
VCC
HLD
SCK
DQ0
C90
PVDD
1
R30
1
S
2
DQ1
3
W
4 V
SS
C81
T11
DNC3
VLL
N25Q128
C78
CPLL
DNC2
TP20
RSTN
DISC
U6
C80
A15
B15
F15
K15
P15
R15
T15
1.27k
C77
A2
R83
0.1
C76
R15
TX2
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
RGND
RGND
CNF
CNF
CNF
CNF
CNF
CNF
CNF
C112
J26
C72
A14
B14
E15
J15
N15
R14
T14
DNC1
TP19
2
+3V3
R4
TP4
1μ 100V
C4
C59
CPF
CNEG
CNEG
CNEG
CNEG
CNEG
CNEG
TP18
VGN
SELTCK
DISC
TP94
CSB
MISO
TP33
TP32
TP16
TP95
TP91
C75
C103
DNC11
DNC8
TP14
INV
LPWM TP73
SDLY
TXRW
SPIB
TCKN
TCKP
TRIGP TP27
TRIGN
W0
W1
TP93
C3
EN
SLEEP
PEN
BEN
CW
1
0.22
K3
F2
G3
N3
J2
TP13
4
0.22
IN0
22
C1
D1
DG1
C2
D2
DG2
C3
D3
DG3
C4
D4
DG4
C5
D5
DG5
C6
D6
DG6
C7
D7
DG7
C8
D8
DG8
C9
D9
DG9
C10
D10
DG10
IN1
R78
C1
D1
DG1
C2
D2
DG2
C3
D3
DG3
C4
D4
DG4
C5
D5
DG5
C6
D6
DG6
C7
D7
DG7
C8
D8
DG8
C9
D9
DG9
C10
D10
DG10
IN1
MISO
MOSI
A1
B1
BG1
A2
B2
BG2
A3
B3
BG3
A4
B4
BG4
A5
B5
BG5
A6
B6
BG6
A7
B7
BG7
A8
B8
BG8
A9
B9
BG9
A10
B10
BG10
6
SCK
CSB
A1
B1
BG1
A2
B2
BG2
A3
B3
BG3
A4
B4
BG4
A5
B5
BG5
A6
B6
BG6
A7
B7
BG7
A8
B8
BG8
A9
B9
BG9
A10
B10
BG10
7
100
C23
5
1.27k 100
C24
C5
1μ 10V
A9
B9
J9
K9
R9
T9
A0
A1
A2
SDA
SCL
TP96
TP17
330p 250V
C22
VPP
C6
C102
VDD
A5
(DO Not Connect)
+3V3
1μ 10V
TP11
TP12
6
ETI
ETO
C3
OTPN
R4
ETI
R5
ETO
P3
LCKD
TP24
R3
CSOP
T3
CSON
(DNC1-7 )
TCK0P
TCK0N
TE6469169-1
PWR
R82
1μ 100V
J20
TP80
TP82
EN
SLEEP
PEN
BEN
CW
CW
BEN
J1
1
PVDD
VDD
100
R2
SDOP
T2
SDON
OTPN
ETI
ETO
LCKD
CSOP
CSON
TP92
R66
OUT1
2.5K 1W
RDCP
J11
SDOP
SDON
1.27k
100
50
R13
C68
C93
TP10
CKON
CKOP
R74
R65
1
1.27k
SDA
SCL
C31
R79
1
2
TX1
3
R70
1.27k
CLKP
CLKN
100
A1
CLKP
B1
CLKN
R69
C16
VNN
VNN
VNN
VNN
VNN
VNN
VNN
CW
INV
R67
CSN
CSP
SDIN
SDIP
CLKN
CLKP
J5
+3V3
R77
R3
1μ 100V
TP3
C17
1
2
3
4
5
6
TP98
RSTN
C71
TP2
C104 C110 C74
CSP
CSN
SDIP
SDIN
VSUB
VSUB
VSUB
VSUB
CKOP
CKON
TXRW
LPWM
C1
D1
DG1
C2
D2
DG2
C3
D3
DG3
C4
D4
DG4
C5
D5
DG5
C6
D6
DG6
C7
D7
DG7
C8
D8
DG8
C9
D9
DG9
C10
D10
DG10
4
INV
SDLY
C121
C11
0
3
SLEEP
OTPN
C32
1μ 100V
J19
R35
TP26
C15
6
SPIB
LCKD
C1
D1
DG1
C2
D2
DG2
C3
D3
DG3
C4
D4
DG4
C5
D5
DG5
C6
D6
DG6
C7
D7
DG7
C8
D8
DG8
C9
D9
DG9
C10
D10
DG10
C33
VDD
2.2μ 10V
0.22
1
100
W0
W1
A1
B1
BG1
A2
B2
BG2
A3
B3
BG3
A4
B4
BG4
A5
B5
BG5
A6
B6
BG6
A7
B7
BG7
A8
B8
BG8
A9
B9
BG9
A10
B10
BG10
VPP
C28
C70
2.2μ 10V
2.2μ 10V
0
2
1
A1
B1
BG1
A2
B2
BG2
A3
B3
BG3
A4
B4
BG4
A5
B5
BG5
A6
B6
BG6
A7
B7
BG7
A8
B8
BG8
A9
B9
BG9
A10
B10
BG10
TP1
C91
C126
1 nF
1μ 10V
EN
PEN
VPP
2.2μ 10V
C125
C124
TX0
D17A
AVDD
0.22
TP97
C122
VLL
C7
TCK1P
TCK1N
C86
C89
PWR
R68
TP8
C123
C83
C9
R36
C30
TRIGP
TRIGN
VDD
VLL
C82
2V5
6
CDELAY
3
1μ 10V
R76
0
2
200
VOUT
SENSE
2
C8
R9
VLL
TP5
R12
2
200
(+2.5V)
4
8
7
2
200
SLEEP
200
BEN
EN
PEN
200
3
6
R8
R75
200
D17B
U3
MCP1727-2502E/SN
1 V
2 IN
VIN
1
2
R7
VCC
GRN
4
GND
5
PWRGD
1
R6
(+5V)
OTPN
LCKD
D6
RED
2
2
YLW
LCKD
1
1
D5
YLW
R5
OTP
1
1
R31
INV
D4
2
GRN
CW
D3
2
1
D2
RED
R32
SLEEP
D1
2
RED
2
GRN
D18
2
D7
BEN
1
PEN
1
EN
HV7358DB1 User’s Guide
DS50002951A-page 50
A.2
TP74
TP75
TP78
TP84
MH1
MH2
MH3
MH4
MUPB002 SCHEMATIC – TOP BLOCK DIAGRAM
3V3_VDD
To connector for
programming the SPI Flash
for FPGA program.
J5
1
3
5
7
2
4
6
8
HDR-2.54 Male 2x4
GND_D
HDR-2.54 Male 1x4
4 3 2 1
Demo Board connectors.SchDoc
SPI_MISO
SPI_MOSI
SPI_SCLK
JP1
DBID_EEPROM_CS
DB_MEMORY_CS
FPGA_FLASH_CS
MUPB_FLASH_CS
MISO
MOSI
SCLK
DBID_EEPROM_CS
PLUG_DETECT
PLUG_DETECT
SPI Flash for FPGA configuration.SchDoc
MISO
MOSI
SCLK
FLASH_CS
SPI_MISO
SPI_MOSI
SPI_SCLK
DB_MEMORY_CS
USB to SPI bridge.SchDoc
FPGA.SchDoc
SPI_MISO
SPI_MOSI
SPI_SCLK
MISO
MOSI
SCLK
MISO
MOSI
SCLK
PLUG_DETECT
PLUG_DETECT
FPGA_FLASH_CS
FPGA_COMMAND_CS
DBID_EEPROM_CS
FPGA_FLASH_CS
FPGA_COMMAND_CS
DBID_EEPROM_CS
FPGA_FLASH_CS
FPGA_COMMAND_CS
SOFT_RST
SOFT_RST
SOFT_RST
USB_TO_SPI_ATTACH
PROGB_IN
FPGA_DONE
PROGB
FPGA_DONE
PROGB_IN
FPGA_DONE
GP3
GP4
GP7
GP3
GP4
GP7
Programmable Clock.SchDoc
GP3
GP4
GP7
CTRL_OEC
CTRL_OED
CTRL_OEB
CTRL_OEC
CTRL_OED
CTRL_OEB
CTRL_OEC
CTRL_OED
CTRL_OEB
CTRL_SCK
CTRL_CSB
SDO
CTRL_SDI
CTRL_SCK
CTRL_CSB
SDO
CTRL_SDI
CTRL_SCK
CTRL_CSB
SDO
CTRL_SDI
40MHz_N
40MHz_P
40MHz_N
40MHz_P
40MHz_N
40MHz_P
CLK0_P
CLK0_N
CLK0_P
CLK0_N
CLK0_P
CLK0_N
CLK1_P
CLK1_N
CLK1_P
CLK1_N
CLK1_P
CLK1_N
CLK2_P
CLK2_N
CLK2_P
CLK2_N
CLK4
IO_0_P
IO_0_N
IO_1_P
IO_1_N
IO_0_P
IO_0_N
IO_1_P
IO_1_N
IO_0_P
IO_0_N
IO_1_P
IO_1_N
IO_2_P
IO_2_N
IO_3_P
IO_3_N
IO_4_P
IO_4_N
IO_5_P
IO_5_N
IO_2_P
IO_2_N
IO_3_P
IO_3_N
IO_4_P
IO_4_N
IO_5_P
IO_5_N
IO_2_P
IO_2_N
IO_3_P
IO_3_N
IO_4_P
IO_4_N
IO_5_P
IO_5_N
IO_6_P
IO_6_N
IO_7_P
IO_7_N
IO_8_P
IO_8_N
IO_9_P
IO_9_N
IO_6_P
IO_6_N
IO_7_P
IO_7_N
IO_8_P
IO_8_N
IO_9_P
IO_9_N
IO_6_P
IO_6_N
IO_7_P
IO_7_N
IO_8_P
IO_8_N
IO_9_P
IO_9_N
IO_10_P
IO_10_N
IO_11_P
IO_11_N
IO_12_P
IO_12_N
IO_13_P
IO_13_N
IO_14_P
IO_14_N
IO_31_P
IO_31_N
IO_10_P
IO_10_N
IO_11_P
IO_11_N
IO_12_P
IO_12_N
IO_13_P
IO_13_N
IO_14_P
IO_14_N
IO_31_P
IO_31_N
IO_10_P
IO_10_N
IO_11_P
IO_11_N
IO_12_P
IO_12_N
IO_13_P
IO_13_N
IO_14_P
IO_14_N
IO_31_P
IO_31_N
IO_32_P
IO_32_N
IO_35
IO_32_P
IO_32_N
IO_35
CLK4
IO_32_P
IO_32_N
IO_35
CLK2_P
CLK2_N
CLK2_P
CLK2_N
CLK4
CLK4
CLK3_P
CLK3_N
CLK5
DS50002951A page-51
Power Conditioning.SchDoc
IO_17_P
IO_17_N
IO_19_P
IO_19_N
IO_20_P
IO_20_N
IO_21_P
IO_21_N
IO_17_P
IO_17_N
IO_19_P
IO_19_N
IO_20_P
IO_20_N
IO_21_P
IO_21_N
IO_17_P
IO_17_N
IO_19_P
IO_19_N
IO_20_P
IO_20_N
IO_21_P
IO_21_N
IO_36_P
IO_36_N
IO_37_P
IO_37_N
IO_38_P
IO_38_N
IO_39_P
IO_39_N
IO_40_P
IO_40_N
IO_41_P
IO_41_N
IO_42_P
IO_42_N
IO_43_P
IO_43_N
IO_44_P
IO_44_N
IO_45
IO_46
IO_36_P
IO_36_N
IO_37_P
IO_37_N
IO_38_P
IO_38_N
IO_39_P
IO_39_N
IO_40_P
IO_40_N
IO_41_P
IO_41_N
IO_42_P
IO_42_N
IO_43_P
IO_43_N
IO_44_P
IO_44_N
IO_45
IO_46
IO_36_P
IO_36_N
IO_37_P
IO_37_N
IO_38_P
IO_38_N
IO_39_P
IO_39_N
IO_40_P
IO_40_N
IO_41_P
IO_41_N
IO_42_P
IO_42_N
IO_43_P
IO_43_N
IO_44_P
IO_44_N
IO_45
IO_46
CLK3_P
CLK3_N
CLK3_P
CLK3_N
CLK5
CLK5
TP26
TP27
TP28
TP29
GND_D GND_D GND_D GND_D
Ground Posts for Scope Probe ground
HV7358DB1 and MUPB002 Schematics and Layouts
2020 Microchip Technology Inc.
A.3
MUPB002 SCHEMATIC – DEMO BOARD CONNECTORS
3V3_VDD
3V3_VDD
R2
4.7k
0402
1%
PWR5V0
C1
33 µF
10V
TANT-B
VCC 5
Y
GND_D
4
PWR5V0
SN74LVC1G126
C2
C90
GND_D
0.1 µF
50V
0603
33 μF
10V
TANT-B
R75
4.7k
0402
1%
J1
GND_D
A1
B1
BG1
A2
B2
BG2
A3
B3
BG3
A4
B4
BG5
A5
B5
BG4
A6
B6
BG6
A7
B7
BG7
A8
B8
BG8
A9
B9
BG9
A10
B10
BG10
IO_1_P
IO_1_N
IO_3_P
IO_3_N
BANK1 - REGION RB
U2
1
OE
2
A
3
GND
SCLK
D5V
C133
0.1 µF
50V
0402
IO_5_P
IO_5_N
IO_7_P
IO_7_N
IO_9_P
IO_9_N
IO_11_P
IO_11_N
IO_13_P
IO_13_N
IO_31_P
IO_31_N
IO_35
CLK4
C1
D1
DG1
C2
D2
DG2
C3
D3
DG3
C4
D4
DG4
C5
D5
DG5
C6
D6
DG6
C7
D7
DG7
C8
D8
DG8
C9
D9
DG9
C10
D10
DG10
LVDS25
LVDS25
DBID_EEPROM_CS
IO_4_P
IO_4_N
LVDS25
MISO
MOSI
IO_8_N
IO_8_P
IO_10_P
IO_10_N
3V3_VDD
LVDS25
R84
4.7k
0402
1%
IO_32_N
IO_32_P
CLK2_P
CLK2_N
IO_20_P
IO_20_N
IO_38_P
IO_38_N
IO_12_P
IO_12_N
IO_14_N
IO_14_P
A1
B1
BG1
A2
B2
BG2
A3
B3
BG3
A4
B4
BG5
A5
B5
BG4
A6
B6
BG6
A7
B7
BG7
A8
B8
BG8
A9
B9
BG9
A10
B10
BG10
IO_36_P
IO_36_N
BANK0 - REGION TL
LVDS25
IO_40_P
IO_40_N
IO_42_P
IO_42_N
IO_44_P
IO_44_N
CLK5
2020 Microchip Technology Inc.
EDGE 40P Female
GND_D
33 μF
10V
TANT-B
0.1 µF
50V
0603
J2
IO_2_P
IO_2_N
C131
C132
0.1 µF
50V
0603
GND_D
BANK3 - REGION LB
PWR3V3
C89
IO_0_P
IO_0_N
IO_6_P
IO_6_N
3V3_VDD
D5V
GND_D
C1
D1
DG1
C2
D2
DG2
C3
D3
DG3
C4
D4
DG4
C5
D5
DG5
C6
D6
DG6
C7
D7
DG7
C8
D8
DG8
C9
D9
DG9
C10
D10
DG10
IO_17_P
IO_17_N
IO_19_P
IO_19_N
IO_21_P
IO_21_N
IO_37_P
IO_37_N
IO_39_P
IO_39_N
IO_41_P
IO_41_N
IO_43_P
IO_43_N
IO_45
IO_46
CLK3_P
CLK3_N
LVDS33
EDGE 40P Female
GND_D
GND_D
GND_D
PLUG_DETECT
HV7358DB1 User’s Guide
DS50002951A-page 52
A.4
MUPB002 SCHEMATIC – FPGA
That's why SCLK is bidirectional from the FPGA's
point of view.
R11
T11
M12
M11
P10
T10
N12
P12
N11
P11
N9
P9
L10
M10
R9
T9
M9
N8
P8
T8
P7
M7
R7
T7
P6
T6
R5
T5
N5
P5
L8
L7
P4
T4
M6
N6
R3
T3
IO_L1P_CCLK_2
IO_L1N_M0_CMPMISO_2
IO_L2P_CMPCLK_2
IO_L2N_CMPMOSI_2
IO_L3P_D0_DIN_MISO_MISO1_2
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L12P_D1_MISO2_2
IO_L12N_D2_MISO3_2
IO_L13P_M1_2
IO_L13N_D10_2
IO_L14P_D11_2
IO_L14N_D12_2
IO_L16P_2
IO_L16N_VREF_2
IO_L23P_2
IO_L23N_2
IO_L29P_GCLK3_2
IO_L29N_GCLK2_2
IO_L30P_GCLK1_D13_2
IO_L30N_GCLK0_USERCCLK_2
IO_L31P_GCLK31_D14_2
IO_L31N_GCLK30_D15_2
IO_L32P_GCLK29_2
IO_L32N_GCLK28_2
IO_L47P_2
IO_L47N_2
IO_L48P_D7_2
IO_L48N_RDWR_B_VREF_2
IO_L49P_D3_2
IO_L49N_D4_2
IO_L62P_D5_2
IO_L62N_D6_2
IO_L63P_2
IO_L63N_2
IO_L64P_D8_2
IO_L64N_D9_2
IO_L65P_INIT_B_2
IO_L65N_CSO_B_2
FPGA_SCK
M0
R63
R64
SCLK
22R
22R
MISO
MOSI
M1
3V3_VDD
3V3_VDD
LD3
GREEN
R8
GREEN
R6
330R
0603
5%
SOFT_RST
LD2
330R
0603
5%
FPGA_COMMAND_CS
GP3
GP4
3V3_VDD
R1
GP7
INIT_B
FLASH_CS
4.7k
0402
1%
BANK 3
BANK 2
U1C
FPGA_FLASH_CS
XC6SLX25-2FTG256C
A3
B3
F5
F6
E3
E4
F3
F4
A2
B2
G5
G6
B1
C1
D1
D3
C2
C3
K6
K5
E1
E2
L5
L4
H3
H4
H5
J6
J4
K3
F1
F2
G1
G3
H1
H2
J1
J3
K1
K2
L1
L3
M1
M2
N1
N3
P1
P2
R1
R2
N4
M5
M3
M4
CTRL_SDI
CTRL_CSB
SDO
CTRL_SCK
CTRL_OEB
CTRL_OED
TP21
TP22
CTRL_OEC
CTRL_SDI
CTRL_CSB
BANK 1
The USB to SPI bridge generates the SCLK, when it's
sending commands to the FPGA. (The FPGA is the
SPI bus slave.)
U1B
IO_L83N_VREF_3
IO_L83P_3
IO_L55N_M3A14_3
IO_L55P_M3A13_3
IO_L54N_M3A11_3
IO_L54P_M3RESET_3
IO_L53N_M3A12_3
IO_L53P_M3CKE_3
IO_L52N_M3A9_3
IO_L52P_M3A8_3
IO_L51N_M3A4_3
IO_L51P_M3A10_3
IO_L50N_M3BA2_3
IO_L50P_M3WE_3
IO_L49N_M3A2_3
IO_L49P_M3A7_3
IO_L48N_M3BA1_3
IO_L48P_M3BA0_3
IO_L47N_M3A1_3
IO_L47P_M3A0_3
IO_L46N_M3CLKN_3
IO_L46P_M3CLK_3
IO_L45N_M3ODT_3
IO_L45P_M3A3_3
IO_L44N_GCLK20_M3A6_3
IO_L44P_GCLK21_M3A5_3
IO_L43N_GCLK22_IRDY2_M3CASN_3
IO_L43P_GCLK23_M3RASN_3
IO_L42N_GCLK24_M3LDM_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L41N_GCLK26_M3DQ5_3
IO_L41P_GCLK27_M3DQ4_3
IO_L40N_M3DQ7_3
IO_L40P_M3DQ6_3
IO_L39N_M3LDQSN_3
IO_L39P_M3LDQS_3
IO_L38N_M3DQ3_3
IO_L38P_M3DQ2_3
IO_L37N_M3DQ1_3
IO_L37P_M3DQ0_3
IO_L36N_M3DQ9_3
IO_L36P_M3DQ8_3
IO_L35N_M3DQ11_3
IO_L35P_M3DQ10_3
IO_L34N_M3UDQSN_3
IO_L34P_M3UDQS_3
IO_L33N_M3DQ13_3
IO_L33P_M3DQ12_3
IO_L32N_M3DQ15_3
IO_L32P_M3DQ14_3
IO_L2N_3
IO_L2P_3
IO_L1N_VREF_3
IO_L1P_3
SDO
CTRL_SCK
CTRL_OEB
CTRL_OED
CTRL_OEC
TP23
TP24
IO_44_N
IO_44_P
IO_45
IO_46
IO_43_N
IO_43_P
IO_42_N
IO_42_P
IO_41_N
IO_41_P
IO_40_N
IO_40_P
IO_39_N
IO_39_P
IO_38_N
IO_38_P
IO_37_N
IO_37_P
IO_36_N
IO_36_P
IO_21_N
IO_21_P
IO_20_N
IO_20_P
IO_19_N
IO_19_P
IO_17_N
IO_17_P
IO_44_N
IO_44_P
IO_45
IO_46
IO_43_N
IO_43_P
IO_42_N
IO_42_P
IO_41_N
IO_41_P
IO_40_N
IO_40_P
IO_39_N
IO_39_P
IO_38_N
IO_38_P
IO_37_N
IO_37_P
IO_36_N
IO_36_P
IO_21_N
IO_21_P
IO_20_N
IO_20_P
IO_19_N
IO_19_P
IO_17_N
IO_17_P
XC6SLX25-2FTG256C
IO_L1P_A25_1
IO_L1N_A24_VREF_1
IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1
IO_L30P_A21_M1RESET_1
IO_L30N_A20_M1A11_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1
IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1
IO_L35P_A11_M1A7_1
IO_L35N_A10_M1A2_1
IO_L36P_A9_M1BA0_1
IO_L36N_A8_M1BA1_1
IO_L37P_A7_M1A0_1
IO_L37N_A6_M1A1_1
IO_L38P_A5_M1CLK_1
IO_L38N_A4_M1CLKN_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1
IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L41N_GCLK8_M1CASN_1
IO_L42P_GCLK7_M1UDM_1
IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L43P_GCLK5_M1DQ4_1
IO_L43N_GCLK4_M1DQ5_1
IO_L44P_A3_M1DQ6_1
IO_L44N_A2_M1DQ7_1
IO_L45P_A1_M1LDQS_1
IO_L45N_A0_M1LDQSN_1
IO_L46P_FCS_B_M1DQ2_1
IO_L46N_FOE_B_M1DQ3_1
IO_L47P_FWE_B_M1DQ0_1
IO_L47N_LDC_M1DQ1_1
IO_L48P_HDC_M1DQ8_1
IO_L48N_M1DQ9_1
IO_L49P_M1DQ10_1
IO_L49N_M1DQ11_1
IO_L50P_M1UDQS_1
IO_L50N_M1UDQSN_1
IO_L51P_M1DQ12_1
IO_L51N_M1DQ13_1
IO_L52P_M1DQ14_1
IO_L52N_M1DQ15_1
IO_L53P_1
IO_L53N_VREF_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1
E13
E12
B15
B16
F12
G11
D14
D16
F13
F14
C15
C16
E15
E16
F15
F16
G14
G16
H15
H16
G12
H11
H13
H14
J11
J12
J13
K14
K12
K11
J14
J16
K15
K16
N14
N16
M15
M16
L14
L16
P15
P16
R15
R16
R14
T15
T14
T13
R12
T12
L12
L13
M13
M14
U1A
ClassName: BANK1_REGION_RB
CLK1_P
CLK1_N
CLK0_P
CLK0_N
IO_1_P
IO_1_N
IO_3_P
IO_3_N
IO_5_P
IO_5_N
IO_11_P
IO_11_N
IO_9_P
IO_9_N
IO_7_P
IO_7_N
IO_13_P
IO_13_N
IO_31_P
IO_31_N
IO_32_P
IO_32_N
IO_35
OUT2
CLK1_P
CLK1_N
CLK0_P
CLK0_N
IO_1_P
IO_1_N
IO_3_P
IO_3_N
IO_5_P
IO_5_N
IO_11_P
IO_11_N
IO_9_P
IO_9_N
IO_7_P
IO_7_N
IO_13_P
IO_13_N
IO_31_P
IO_31_N
IO_32_P
IO_32_N
IO_35
OUT1
BANK 0
U1D
When the FPGA is loading its firmware from the SPI
Flash, the FPGA genetaes the SCLK. (The FPGA is
the SPI bus master.)
IO_L66N_SCP0_0
IO_L66P_SCP1_0
IO_L65N_SCP2_0
IO_L65P_SCP3_0
IO_L64N_SCP4_0
IO_L64P_SCP5_0
IO_L63N_SCP6_0
IO_L63P_SCP7_0
IO_L62N_VREF_0
IO_L62P_0
IO_L40N_0
IO_L40P_0
IO_L39N_0
IO_L39P_0
IO_L38N_VREF_0
IO_L38P_0
IO_L37N_GCLK12_0
IO_L37P_GCLK13_0
IO_L36N_GCLK14_0
IO_L36P_GCLK15_0
IO_L35N_GCLK16_0
IO_L35P_GCLK17_0
IO_L34N_GCLK18_0
IO_L34P_GCLK19_0
IO_L33N_0
IO_L33P_0
IO_L7N_0
IO_L7P_0
IO_L6N_0
IO_L6P_0
IO_L5N_0
IO_L5P_0
IO_L4N_0
IO_L4P_0
IO_L3N_0
IO_L3P_0
IO_L2N_0
IO_L2P_0
IO_L1N_VREF_0
IO_L1P_HSWAPEN_0
D12
D11
A14
B14
E11
F10
A13
C13
A12
B12
D9
F9
A11
C11
C8
D8
C10
E10
E8
E7
A10
B10
A9
C9
A8
B8
C6
D6
A7
C7
E6
F7
A6
B6
C5
D5
A5
B5
A4
C4
TP21
TP21
TP22
TP22
TP23
TP23
TP24
TP24
TP LOOP Silver
TP LOOP Silver
TP LOOP Silver
TP LOOP Silver
40MHz_N
40MHz_P
IO_14_N
IO_14_P
IO_12_N
IO_12_P
IO_6_N
IO_6_P
IO_8_N
IO_8_P
IO_10_N
IO_10_P
IO_4_N
IO_4_P
IO_2_N
IO_2_P
IO_0_N
IO_0_P
IO_14_N
IO_14_P
IO_12_N
IO_12_P
IO_6_N
IO_6_P
IO_8_N
IO_8_P
IO_10_N
IO_10_P
IO_4_N
IO_4_P
IO_2_N
IO_2_P
IO_0_N
IO_0_P
XC6SLX25-2FTG256C
GND_D
XC6SLX25-2FTG256C
ClassName: BANK0_REGION_TL
ClassName: BANK3_REGION_LB
J8
SMA Female
1
2
OUT1
GND_D
OUT1
3V3_VDD
3V3_VDD
R9
R4
J9
FPGA_DONE
PROG_B
C14
TCK
C12
TDI
E14
TDO
A15
TMS
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
CMPCS_B_2
FPGA_DONE
ClassName: JTAG
J4
HDR-2 MM Male 2x7
PROGB_IN
SW2
TACT SPST
GND_D
R5
C84
4.7k
0402
1%
L11
XC6SLX25-2FTG256C
GND_D
0.1uF
50V
0402
GND_D
Push button to force FPGA
configuration download from
Flash
FPGA_TDI
FPGA_TDO
FPGA_TCK
FPGA_TMS
OUT2
GND_D
CLOCK TERMINATION WAS REMOVED FROM THIS SCHEMATIC.
THE TERMINATION WAS ADDED TO THE USB SCHEMATIC
GND_D
XC6SLX9-2FTG256I
XC6SLX9-2FTG256C - this i use
DS50002951A page-53
Default config set to Master Serial M[1:0] = 01
3V3_VDD
3V3_VDD
3V3_VDD
FPGA power.SchDoc
R10
22R
0402
1%
LD1
R11
GREEN
22R
0402
1%
R12
M1
M0
3
R14
22R
0402
1%
GND_D
R15
22R
0402
1%
GND_D
FPGA_DONE
SMA Female
1
GND_D
VCCAUX
2 4 6 8 10 12 14
1 3 5 7 9 11 13
P13
2
DONE_2
T2
PROGRAM_B_2
P14
SUSPEND
4.7k
0402
1%
1
U1E
330R
0603
5%
2
OUT2
330R
0603
5%
Q1
1
BSS123
2
GND_D
"DONE" LED
HV7358DB1 and MUPB002 Schematics and Layouts
2020 Microchip Technology Inc.
A.5
MUPB002 SCHEMATIC – SPI FLASH FOR FPGA CONFIGURATION
MOSI
SCLK
R61
MISO
22R
0402
1%
3V3_VDD
3V3_VDD
R62
R65
2.43k
0402
1%
3V3_VDD
Partial list of SPI Flash ICs
which we can use with
Spartan-6:
S25FL127SABMFI101,
S25FL127SABMFV101.
3V3_VDD
C138
10k
0402
1%
0.1 µF
50V
0402
U15
S25FL127SABMFI101
1
2
3
4
FLASH_CS
HDR-2.54 Male 1x2
VDD
CE
SO/SIO1 HOLD/SIO3
WP/SIO2
SCK
VSS
SI/SIO0
Write-protect jumper
2 1
JP2
GND_D
GND_D
3V3_VDD
R67
2020 Microchip Technology Inc.
100R
0402
1%
R68
Termination network
see fig. 2-12 and discussion on pp. 56-57
in Xilunx UG380
100R
0402
1%
GND_D
8
7
6
5
GND_D
R66
10k
0402
1%
HV7358DB1 User’s Guide
DS50002951A-page 54
A.6
MUPB002 SCHEMATIC – PROGRAMMABLE CLOCK
J7
USB 2.0 MICRO-B FEMALE
USB_5V
VBUS 1
2
USB_N
D3
USB_P
D+
4
ID
5
GND
D5V
D2
MBR0540T1G
C44
C45
0
4.7 μF
16V
1206
4.7 μF
16V
1206
GND_D
GND_D
GND_D
C46
0.1 µF
50V
0603
R45
330R
0603
5%
3V3_VDD
GND_D
GND_D
R19
3V3_VDD
100k
0402
1%
U3A
R16
1k
0402
1%
Upstream
41
FLEX_USBUP_DP/PRT_DIS_P0
40
FLEX_USBUP_DM/PRT_DIS_M0
USB_P
USB_N
R18
1k
0402
1%
36
VBUS_DET
C134
0.1 µF
50V
0402
VBUS
TP1
U9
42
FLEX_HSIC_UP_DATA
39
FLEX_HSIC_UP_STROBE
100k
0402
1%
10000 pF
25V
0402
HSIC / USB 2.0 Downstream
3
SWAP_USBDN1_DM/PRT_DIS_M1
4
SWAP_USBDN1_DP/PRT_DIS_P1
5
USBDN2_DM/PRT_DIS_M2
6
USBDN2_DP/PRT_DIS_P2
1
OE
2
A
3
GND
R21
C47
GND_D
100k
0402
1%
Y
4
SCLK
R69
GND_D
10k
0402
1%
GND_D
USB 2.0 Downstream
TP LOOP Silver
VCC 5
SN74LVC1G126
R3
GND_D
GND_D
8
USBDN3_DM/PRT_DIS_M3
9
USBDN3_DP/PRT_DIS_P3
3V3_VDD
GND_D
10
USBDN4_DM/PRT_DIS_M4
11
USBDN4_DP/PRT_DIS_P4
Port Power
PLUG_DETECT
SOFT_RST
16
OCS1_N
20
OCS2_N
28
UART_RX/OCS3_N
30
UART_TX/OCS4_N
PIO18
GP7
C135
15
PRTPWR1/PRTCTL1
19
PRTPWR2/PRTCTL2
21
PRTPWR3/PRTCTL3
29
PRTPWR4/PRTCTL4
PIO42
PIO43
GP3
GP4
TP6
0.1 µF
50V
0402
TP7
SPI/OCS
27
SPI_CLK
26
SPI_DO/SPI_SPD_SEL
24
SPI_DI
25
SPI_CE_N
U13
1
OE
2
A
3
GND
UNBUFFERED_SCLK
UNBUFFERED_MOSI
R95
PROGB
3V3_VDD
RESET_N
14
SUSPEND
13
SOF
22
NC
23
NC
34
NC
FPGA_DONE
1k
0402
1%
XTAL1/REFCLK
R60
4.7k
0402
1%
RBIAS
35
RESET
44
XTAL1
FLASH_SI
MOSI
R70
0.1 µF
50V
0402
U14
10k
0402
1%
R7
4.7k
0402
1%
R58
10k
0402
1%
GND_D
TP8
SST26VF016B
1
2
3
4
R38
3.3M
0402
1%
R54
12k
0402
1%
C136
10k
0402
1%
45
NC
3V3_VDD
R57
43
XTAL2
46
4
GND_D
Common
GND_D
Y
SN74LVC1G126
3V3_VDD
EEPROM/SMBus
33
SCL/SMBCLK
31
SDA/SMBDATA
TP LOOP Silver
GND_D
VCC 5
TP LOOP Silver
GND_D
MISO
R71
USB4604
GND_D
X1
24 MHz
The purpose of this SPI Flash is to store the configuration
for the USB4604.
C130
(This is not the Flash that stores the FPGA configuration.)
C129
18 pF
50V
0402
GND_D
VDD 8
CE
7
SO/SIO1 HOLD/SIO3
6
WP/SIO2
SCK
5
VSS
SI/SIO0
18 pF
50V
0402
10k
0402
1%
3V3_VDD
GND_D
R50
GND_D
100k
0402
1%
GND_D
2
3V3_VDD
C49
GND_D
4.7k
0402
1%
C48
4.7 µF
6.3V
0402
0.1 µF
50V
0402
GND_D
1
OUT
Standby
GND
3
0.1 µF
50V
0603
DSC1001CL5-024.0000T
Output
ON
ON
OFF
Standby#
Hi Level
NC
Low Level
SW1
TACT SPST
C137
2
GND_D
3V3_VDD
1
U11
4 V
DD
R51
GND_D
GND_D
R72
10k
0402
1%
USB_TO_SPI_ATTACH
R73
10k
0402
1%
R74
10k
0402
1%
R92
DS50002951A page-55
1k
0402
1%
To connector for
programming the SPI Flash
for FPGA program. Allows
to detach the USB to SPI
bridge from the SPI from the
connector.
FPGA_FLASH_CS
R93
VDDCORE
47 V
DDCOREREG
2
NC
7
NC
38 V
DD12
VDD12
17 V
DDCR12
0
C50
4.7 µF
6.3V
0402
C79
0.1 µF
50V
0402
GND_D GND_D
C80
0.1 µF
50V
0402
GND_D
C103
0.1 µF
50V
0402
GND_D
C104
0.1 µF
50V
0402
GND_D
C105
4.7 µF
6.3V
0402
GND_D
C106
0.1 µF
50V
0402
GND_D
GND_D
TP9
3V3_VDD
U3B
VDD33
Power
VBAT
VDD33
VDD33
VDDA33
VDDA33
VDDA33
TP LOOP Silver
1
1k
0402
1%
FPGA_COMMAND_CS
VDD33
18
32
12
37
48
DBID_EEPROM_CS
VDD33
EP
USB4604
TP12
TP LOOP Silver
C111
0.1 µF
50V
0402
GND_D
C112
0.1 µF
50V
0402
GND_D
C113
0.1 µF
50V
0402
GND_D
C114
0.1 µF
50V
0402
GND_D
C115
4.7 µF
6.3V
0402
GND_D
C116
0.1 µF
50V
0402
GND_D
HV7358DB1 and MUPB002 Schematics and Layouts
2020 Microchip Technology Inc.
A.7
MUPB002 SCHEMATIC – FPGA DECOUPLING CAPACITORS
J3
D5V
D1
MBR0540T1G
0
USB 2.0 MICRO-B FEMALE
VBUS 1
2
D3
D+
4
ID
5
GND
R42
C41
C43
4.7 μF
16V
1206
4.7 μF
16V
1206
GND_D
GND_D
330R
0603
5%
0.1 µF
50V
0603
GND_D
GND_D
C42
GND_D
D5V
D5V
1V2_VCCINT
C51
C52
10 μF
10V
0805
0.1 μF
50V
0603
MCP172X ADJ DFN-8
1 V
VOUT 8
2 VIN
IN
7
ADJ
3
CDELAY 6
SHDN
9
EP
5
4
PWRGD
GND
R23
10k
0402
1%
MCP172X ADJ DFN-8
1 V
VOUT 8
2 IN
VIN
7
ADJ
3
CDELAY 6
SHDN
9
EP
5
4
PWRGD
GND
TP2
R17
19.1k
0603
1%
C53
C54
10 μF
10V
0805
0.1 μF
50V
0603
Via_2.5x1.5
D3
BAT54XV2T1G
C59
C60
10 μF
10V
0805
0.1 μF
50V
0603
U6
U4
PG_1V2_VCCINT
R22
GND_D
PG_3V3_CLK
10k
0603
1%
3V3_VDD
TP4
Via_2.5x1.5
R26
69.8k
0603
1%
R29
C61
C62
10 μF
10V
0805
0.1 μF
50V
0603
D4
BAT54XV2T1G
10k
0603
1%
GND_D
D5V
GND_D
R30
PG_3V3_VDD
GND_D
D5V
10k
0402
1%
R24
10k
0402
1%
2V5_VDD
D5V
2020 Microchip Technology Inc.
C55
C56
10 μF
10V
0805
0.1 μF
50V
0603
3.6V (Supply to Ripple Blocker)
D5V
MCP172X ADJ DFN-8
1 V
VOUT 8
2 IN
VIN
7
ADJ
3
CDELAY 6
SHDN
9
EP
5
4
PWRGD
GND
R27
390R
0603
5%
U5
TP3
Via_2.5x1.5
R25
51k
0603
1%
R28
C57
C58
10 μF
10V
0805
0.1 μF
50V
0603
GREEN
GND_D
C64
10 μF
10V
0805
0.1 μF
50V
0603
D5
BAT54XV2T1G
PG_3V3_CLK
U7
3V3_CLK
GND_D
TP5
Via_2.5x1.5
R31
82k
0603
1%
C65
10 μF
10V
0805
R32
10.7k
0603
1%
GND_D
GND_D
10k
0603
1%
GND_D
LD4
C63
MCP172X ADJ DFN-8
1 V
VOUT 8
2 IN
VIN
7
ADJ
3
CDELAY 6
SHDN
9
EP
5
4
PWRGD
GND
C66
0.1 μF
50V
0603
D6
BAT54XV2T1G
HV7358DB1 User’s Guide
DS50002951A-page 56
A.8
HV7358DB1 and MUPB002 Schematics and Layouts
A.9
HV7358DB1 – TOP SILK
A.10 HV7358DB1 – TOP COPPER AND SILK
2020 Microchip Technology Inc.
DS50002951A-page 57
HV7358DB1 User’s Guide
A.11 HV7358DB1 – TOP COPPER
A.12 HV7358DB1 – BOTTOM COPPER
DS50002951A-page 58
2020 Microchip Technology Inc.
HV7358DB1 and MUPB002 Schematics and Layouts
A.13 HV7358DB1 – BOTTOM COPPER AND SILK
A.14 HV7358DB1 – BOTTOM SILK
2020 Microchip Technology Inc.
DS50002951A-page 59
HV7358DB1 User’s Guide
A.15 MUPB002 – TOP SILK
A.16 MUPB002 – TOP COPPER AND SILK
DS50002951A-page 60
2020 Microchip Technology Inc.
HV7358DB1 and MUPB002 Schematics and Layouts
A.17 MUPB002 – TOP COPPER
A.18 MUPB002 – BOTTOM COPPER
2020 Microchip Technology Inc.
DS50002951A-page 61
HV7358DB1 User’s Guide
A.19 MUPB002 – BOTTOM COPPER AND SILK
A.20 MUPB002 – BOTTOM SILK
DS50002951A-page 62
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Appendix B. Bill of Materials (BOM)
TABLE B-1:
Qty.
HV7358DB1 BILL OF MATERIALS (BOM)(1)
Reference
16 C11, C18-21,
C57-67
3
Description
Capacitor, Ceramic, 330 pF, 250V,
U2J, 0805
C112, C116, C119 Capacitor, Ceramic, 0.1 µF, 10V,
10%, X7R, 0402
Manufacturer
Murata
Electronics®
TDK Corporation
Part Number
GCM21A7U2E331JX01D
C1005X7R1A104K050BB
18 C3-6, C10,
C12-14, C22,
C25-28, C32-33,
C98, C120-121
Capacitor, Ceramic, 1 µF, 100V, 10%, TDK Corporation
X7S, 0805
CGA4J3X7S2A105K125AB
1
C36
Capacitor, Ceramic, 10 µF, 16V, X5R, Yageo Corporation
0805
CC0805KKX5R6BB106
4
C41, C42, C117,
C118
Capacitor, Ceramic, 10000 pF, 50V,
±10%, X7R, 0402
TDK Corporation
CGA2B3X7R1H103K050BB
1
C43
Capacitor, Ceramic, 2.0 pF, 50V,
0603
Panasonic® - ECG
CGJ3E2C0G1H020C080AA
1
C51
Capacitor, Ceramic, 1000 pF, 16V,
X7R, 0603
AVX Corporation
0603YC102KAT2A
5
C7, C15, C23,
C24, C29
Capacitor, Ceramic, .22 µF, 16V,
X7R, 10%, 0603
TDK Corporation
C1608X7R1C224K
18 C75-78, C80-81,
C90, C92, C93,
C100-106, C108,
C110
Capacitor, Ceramic, 1 µF, 16V, X5R,
0402
TDK Corporation
CGB2A1X5R1C105M033BC
8
Capacitor, Ceramic, 1 µF, 10V, X7S,
0402
TDK Corporation
C1005X7S1A105K050BC
36 C9, C16-17,
C68-72, C79,
C82-89, C91,
C94-97, C107,
C109, C114-115,
C122-131
Capacitor, Ceramic, 2.2 µF, 10V,
X5R, 0402
TDK Corporation
C1005X5R1A225K050BC
3
LED, Thin, 635NM, Red, DIFF
Lumex® Inc.
SML-LXT0805IW-TR
C8, C30-31, C46,
C74, C99, C111,
C113
D1, D5, D18
Diode, Schottky, 100V, 1A
Diodes
Incorporated®
2
D13, D14
B1100-13F
3
D2, D6, D7
LED, Thin, 565NM, Green, DIFF
Lumex Inc.
SML-LXT0805GW-TR
2
D3, D4
LED, Thin, 585NM, Yellow, DIFF
Lumex Inc.
SML-LXT0805YW-TR
4
D8, D10, D11, D17 Diode, Schottky, Dual, 30V
Diodes Incorporated
BAT54DW-7
1
D9
Fairchild
Semiconductor®
BAV99WT1G
5
J1, J2, J3, J4, J13 SMA, Jack End Launch PCB
Johnson
142-0711-821
Note 1:
Diode, Switch, SS, Dual, 70V
The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
2020 Microchip Technology Inc.
DS50002951A-page 63
HV7358DB1 User’s Guide
TABLE B-1:
Qty.
HV7358DB1 BILL OF MATERIALS (BOM)(1) (CONTINUED)
Reference
Description
Manufacturer
Part Number
1
J10
Connector, Header, Vertical, .100,
6POS
TE Connectivity, Ltd. 3-641213-6
2
J5, J12
Connector, Header, 40POS, R/A,
HM-ZD
TE Connectivity, Ltd. 6469169-1
25 J6-9, J11, J19-35,
J37, J39, J41
Connector, Header, Vertical, .100,
2POS,
Molex®
7
Shunt, Econ, PHBR, 5AU, Black
TE Connectivity, Ltd. 382811-8
J6, 11, 15, 19-22
22-28-4023
4
MH1-4
Screw Machine Phillips, 4-40X1/4
B&F
4
MH1, MH2, MH3,
MH4
Standoff, HEX, 4-40 THR, .250"L
Keystone Electronics 1891
Corp.
PMS 440 0025 PH
3
R12, R35, R36
Resistor, SMD, 0.0Ω, Jumper
Panasonic - ECG
ERJ-3GEY0R00V
16 R13-14,16,19,22,4 Resistor, 2.55 kΩ, 1W, 1%, 2512
5,47-48,50,53,55,5
7,60,62-64
Panasonic - ECG
ERJ-1TNF2551U
2
R24, R29
Resistor, 499Ω, 1/10W, 1%, 0603
Panasonic - ECG
ERJ-3EKF4990V
1
R27
Resistor, 249Ω, 1/10W, 1%, 0603
Panasonic - ECG
ERJ-3EKF2490V
3
R28, R18, R21
Resistor, 1.00 kΩ, 1/16W, 1%, 0603
Panasonic - ECG
ERJ-3EKF1001V
6
R3, R17, R23,
R51, R54, R58
Resistor, 49.9Ω, 1/16W, 1%, 0603
Panasonic - ECG
ERJ-3EKF49R9V
13 R30, R69-77,
R80-81, R83
Resistor, 1.27 kΩ, ±1%, 1/10W, 0603 Panasonic - ECG
ERJ-3EKF1271V
7
Resistor, 100Ω, 1/10W, 1%, 0402
Panasonic - ECG
ERJ-2RKF1000X
Not installed
NA
NA
R34, R65, R66,
R67, R68, R79,
R82
12 R4, R15, R20,
R25, R26, R33,
R43, R44, R46,
R49, R52, R56
8
R5, R6, R7, R8,
Resistor, 200Ω, 1/10W, 1%, 0603
R9, R10, R31, R32
Panasonic - ECG
ERJ-3GEYJ201V
1
R78
Resistor, SMD, 22.1Ω, 1%, 1/10W,
0402
Panasonic - ECG
ERJ-2RKF22R1X
6
TP50, 65, 74, 75,
78, 84
Connector, PC, Pin, Circular,
0.030 Diameter
Mill-Max Mfg.
Corporation
3132-0-00-15-00-00-08-0
1
U3
IC, Reg, LDO, 2.5V, 1.5A,
8-Lead SOIC
Microchip
Technology Inc.
MCP1727-2502E/SN
1
U4
IC, Op Amp, VFB, 510 MHz,
8-Lead SOIC
ADI
AD8099ARDZ
1
U5
16-Channel, ±80V, 1.8A, Ultrasound
Beamformer
Microchip
Technology Inc.
HV7358TFBGA
1
U6
IC, Flash, 128 Mbit, 108 MHz,
8-Lead SOIC
Micron Technology
Inc.
N25Q128A13ESE40F
1
U7
IC, 2.5V, 2:1, LVDS, Mux in 3x3,
16-Lead QFN
Microchip
Technology Inc.
SY58611UMG
Note 1:
The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
DS50002951A-page 64
2020 Microchip Technology Inc.
Bill of Materials (BOM)
TABLE B-2:
Qty.
MUPB002 BILL OF MATERIALS (BOM)(1)
Reference
Description
Manufacturer
Part Number
8
C1, C10, C11, C12,
C27, C28, C90,
C131
Capacitor, Tantalum, 33 µF, 10V, 10%, KEMET
1.4 Ohm, SMD, B
T494B336K010AT
2
C129, C130
Capacitor, Ceramic, 18 pF, 50V, 5%,
C0G, SMD, 0402
GRM1555C1H180JA01D
Murata Electronics
14 C2, C41, C46, C52, Capacitor, Ceramic, 0.1 µF, 50V, 20%, TDK Corporation
C54, C56, C58, C60, X7R, SMD, 0603
C62, C64, C66, C89,
C132, C137
C1608X7R1H104M
1
C3
TPSB107K006R0400
6
C4, C13, C17, C21, Capacitor, Ceramic, 0.047 µF, 16V,
C30, C33
10%, X7R, SMD, 0402
2
C42, C43
Capacitor, Ceramic, 4.7 µF, 16V, 10%, KEMET
X7R, SMD, 1206
C1206C475K4RACTU
0
C44, C45
Capacitor, Ceramic, 4.7 µF, 16V, 10%, KEMET
X7R, SMD, 1206, NOT POPULATED
C1206C475K4RACTU
Capacitor, Tantalum, 100 µF, 6.3V,
10%, 0.4 Ohm, SMD, B
13 C47, C73, C74, C75, Capacitor, Ceramic, 10000 pF, 25V,
C76, C77, C78, C87, 20%, X7R, SMD, 0402
C88, C91, C100,
C101, C102
AVX Corporation
Taiyo Yuden Co., Ltd. EMK105B7473KV-F
TDK Corporation
C1005X7R1E103M
0
C48
Capacitor, Ceramic, 0.1 µF, 50V, 10%, TDK Corporation
X7R, SMD, 0402, NOT POPULATED
C1005X7R1H104K050BB
0
C49
Capacitor, Ceramic, 4.7 µF, 6.3V,
20%, X5R, SMD, 0402,
NOT POPULATED
GRM155R60J475ME47D
Murata Electronics
36 C5, C6, C7, C8, C9, Capacitor, Ceramic, 1000 pF, 25V,
C14, C15, C16, C18, 5%, C0G, SMD, 0201
C19, C20, C22, C23,
C24, C25, C26, C29,
C31, C32, C34, C35,
C36, C37, C38, C39,
C40, C117, C118,
C119, C120, C123,
C124, C125, C126,
C127, C128
Digi-Key® Electronics 587-5297-1-ND
3
C50, C105, C115
Murata Electronics
8
C51, C53, C55, C57, Capacitor, Ceramic, 10 µF, 10V, 10%, Samsung
C59, C61, C63, C65 X7R, SMD, 0805
Electro-Mechanics
America, Inc
Capacitor, Ceramic, 4.7 µF, 6.3V,
20%, X5R, SMD, 0402
GRM155R60J475ME47D
CL21B106KPQNFNE
24 C67, C68, C79, C80, Capacitor, Ceramic, 0.1 µF, 50V, 10%, TDK Corporation
C81, C82, C84, C92, X7R, SMD, 0402
C93, C94, C95,
C103, C104, C106,
C111, C112, C113,
C114, C116, C133,
C134, C135, C136,
C138
C1005X7R1H104K050BB
2
C1608X5R1C475K080AC
C69, C70
Note 1:
Capacitor, Ceramic, 4.7 µF, 16V, 10%, TDK Corporation
X5R, SMD, 0603
The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
2020 Microchip Technology Inc.
DS50002951A-page 65
HV7358DB1 User’s Guide
TABLE B-2:
Qty.
MUPB002 BILL OF MATERIALS (BOM)(1) (CONTINUED)
Reference
Description
Manufacturer
Part Number
2
C71, C107
Capacitor, Ceramic, 10000 pF, 50V,
10%, X7R, SMD, 0603
AVX Corporation
06035C103KAT2A
1
C72
Capacitor, Ceramic, 4700 pF, 50V,
10%, X7R, SMD, 0603
KEMET
C0603C472K5RACTU
2
D1, D2
Diode, Schottky, MBR0540T1G,
510 mV, 500 mA, 40V, SMD,
SOD-123
ON® Semiconductor MBR0540T1G
5
D3, D4, D5, D6, D7
Diode, Schottky, BAT54XV2T1G, 30V, ON Semiconductor
200 mA, 40V, SOD-523
2
J1, J2
Connector, Edge, HMZd, 2.5 mm,
40P, Female, TH, R/A
Tyco Electronics
1469028-1
(TE Connectivity Ltd.)
2
J3, J7
Connector, USB 2.0, Micro-B,
Female, SMD, R/A
FCI
1
J4
Connector, Header, 2 mm, Male, 2x7, Molex, LLC
Milli-Grid, Gold, Shroud, SMD,
Vertical
878321420
0
J5
Connector, Header-2.54, Male, 2x4,
Gold, 5.84 MH, SMT, Vertical,
NOT POPULATED
Sullins Connector
Solutions
GBC04DABN-M30
4
J6, J14, J15, J16
Connector, Header-2.54, Male, 1x3,
Tin, 6.75 MH, TH, Vertical
Molex
90120-0123
0
J8, J9
Connector, RF, Coaxial, SMA,
Female, 2P, TH, Vertical,
NOT POPULATED
TE Connectivity Ltd.
5-1814832-1
1
JP1
Connector, Header-2.54, Male, 1x4,
Tin, 5.84 MH, TH, Vertical
FCI
68002-404HLF
1
JP2
Connector, Header-2.54 Male, 1x2,
Gold, 5.84 MH, TH, Vertical
FCI
77311-118-02LF
4
LD1, LD2, LD3, LD4 Diode, LED, Green, 2.2V, 25 mA,
15 mcd, Clear, SMD, 0603
Kingbright Electronic APT1608SGC
Co., Ltd.
1
Q1
Transformer, FET, N-CH, BSS123,
100V, 170 mA, 300 mW,
3-Lead SOT-23
Diodes Incorporated BSS123-7-F
5
R1, R2, R4, R60,
R84
Resistor, TKF, 4.7k, 1%, 1/10W, 0402 KOA Speer
Electronic, Inc.
0
R10, R15
Resistor, TKF, 22R, 1%, 1/20W, SMD, Panasonic Electronic ERJ-2RKF22R0X
0402, NOT POPULATED
Components
5
R11, R14, R61, R63, Resistor, TKF, 22R, 1%, 1/20W, SMD, Panasonic Electronic ERJ-2RKF22R0X
R64
0402
Components
5
R16, R18, R92, R93, Resistor, TKF, 1k, 1%, 1/10W, SMD,
R95
0402
Panasonic - ECG
ERJ-2RKF1001X
1
R17
Panasonic - ECG
ERJ-3EKF1912V
5
R20, R37, R39, R67, Resistor, TKF, 100R, 1%, 1/16W,
R68
SMD, 0402
Yageo Corporation
RC0402FR-07100RL
3
R22, R28, R29
Vishay Beyschlag
MCT06030C1002FP500
Note 1:
Resistor, TKF, 19.1k, 1%, 1/10W,
SMD, 0603
Resistor, TF, 10k, 1%, 1/8W, SMD,
0603
BAT54XV2T1G
10118192-0001LF
RK73H1ETTP4701F
The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
DS50002951A-page 66
2020 Microchip Technology Inc.
Bill of Materials (BOM)
TABLE B-2:
Qty.
MUPB002 BILL OF MATERIALS (BOM)(1) (CONTINUED)
Reference
Description
Manufacturer
Part Number
9
R23, R24, R30, R33, Resistor, TKF, 10k, 1%, 1/10W, SMD, Panasonic - ECG
R65, R66, R72, R73, 0402
R74
ERJ-2RKF1002X
1
R25
Resistor, TKF, 51k, 1%, 1/10W, SMD, Panasonic - ECG
0603
ERJ-3EKF5102V
1
R26
Resistor, TKF, 69.8k, 1%, 1/10W,
SMD, 0603
Panasonic - ECG
ERJ-3EKF6982V
1
R27
Resistor, TKF, 390R, 5%, 1/10W,
SMD, 0603
Panasonic - ECG
ERJ-3GEYJ391V
5
R3, R19, R21, R36, Resistor, TKF, 100k, 1%, 1/10W,
R50
SMD, 0402
Panasonic - ECG
ERJ-2RKF1003X
1
R31
Resistor, TKF, 82k, 1%, 1/10W, SMD, Panasonic Electronic ERJ-3EKF8202V
0603
Components
1
R32
Resistor, TKF, 10.7k, 1%, 1/10W,
SMD, 0603
0
Panasonic - ECG
ERJ-3EKF1072V
R34, R35, R40, R41 Resistor, TKF, 0R, 1/16W, SMD,
0402, NOT POPULATED
Yageo Corporation
RC0402JR-070RL
0
R38
Resistor, TKF, 3.3M, 1%, 1/16W,
SMD, 0402, NOT POPULATED
Yageo Corporation
RC0402FR-073M3L
0
R5, R7, R51, R75
Resistor, TKF, 4.7k, 1%, 1/10W, 0402, KOA Speer
NOT POPULATED
Electronic, Inc.
RK73H1ETTP4701F
1
R43
Resistor, TKF, 100k, 1%, 1/10W,
SMD, 0603
Panasonic - ECG
ERJ-3EKF1003V
1
R44
Resistor, TKF, 78.7k, 1%, 1/10W,
SMD, 0603
Panasonic Electronic ERJ-3EKF7872V
Components
1
R54
Resistor, TKF, 12k, 1%, 1/16W, SMD, ROHM
0402
Semiconductor
0
R57, R58, R69, R70, Resistor, TKF, 10k, 1%, 1/10W, SMD, Panasonic - ECG
R71
0402, NOT POPULATED
6
R6, R8, R9, R12,
R42, R45
Resistor, MF, 330R, 5%, 1/16W, SMD, Panasonic Electronic ERA-V33J331V
0603
Components
1
R62
Resistor, TKF, 2.43k, 1%, 1/16W,
SMD, 0402
0
MCR01MZPF1202
ERJ-2RKF1002X
Yageo Corporation
RC0402FR-072K43L
R76, R77, R78, R79, NOT POPULATED
R80, R81, R82, R83
Panasonic - ECG
ERJ-3GSY0R00V
2
SW1, SW2
TE Connectivity
Alcoswitch
FSM2JMTR
0
TP1, TP6, TP7, TP8, Connector, TP, Loop, Silver, 3.4x5,
TP9, TP12, TP21,
SMD, NOT POPULATED
TP22, TP23, TP24,
TP30, TP31
Component
Corporation
TP-107-2
0
TP26, TP27, TP28,
TP29
NOT POPULATED
1
U1
IC, FPGA, XC6SLX25-2FTG256C,
186 I/O, 1.2V, BGA-256
Xilinx Inc.
XC6SLX25-2FTG256C
1
U10
Microchip Clock Generation, Quad,
156.25 MHz, SM803004UMY,
48-Lead QFN
Microchip
Technology Inc.
SM803004UMY
Note 1:
Switch, TACT, SPST, 24V, 50 mA,
FSM2JMTR, SMD
The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
2020 Microchip Technology Inc.
DS50002951A-page 67
HV7358DB1 User’s Guide
TABLE B-2:
Qty.
MUPB002 BILL OF MATERIALS (BOM)(1) (CONTINUED)
Reference
Description
Manufacturer
0
U11
Microchip Clock Oscillator, Single,
24 MHz, DSC6003CI2A-024.0000,
SMD, 4-Lead DFN,
NOT POPULATED
0
U14
Microchip Memory Serial Flash, 16M, Microchip
104 MHz, SST26VF016B-104I/SM,
Technology Inc.
8-Lead SOIJ, NOT POPULATED
SST26VF016B-104I/SM
1
U15
Flash – NOR Memory IC, 128 Mb
(16Mx8), SPI – Quad, I/O, 108 MHz,
8-Lead SOIC
S25FL127SABMFV101
3
U2, U9, U13
IC, Bus, BUFF, TRI-ST, N-INV, Single, Texas Instruments
SN74LVC1G126, SOT-553
SN74LVC1G126DRLR
1
U3
Microchip Interface, USB, Hub/Flash, Microchip
USB4604-1080HN, 48-Lead SQFN
Technology Inc.
USB4604-1080HN
4
U4, U5, U6, U7
Microchip Analog, LDO, 0.8V-5V,
MCP1727T-ADJE/MF, 8-Lead DFN
Microchip
Technology Inc.
MCP1727T-ADJE/MF
1
U8
Microchip Analog, LDO, ADJ,
MIC94325YMT-TR, 6-Lead TDFN
Microchip
Technology Inc.
MIC94325YMT-TR
1
X1
Crystal, 24 MHz, 18 pF, SMD,
ABM8G
Abracon Corporation ABM8G-24.000MHZ-18-D2
(LLC)
Y-T
1
X2
Crystal, 40 MHz, 12 pF, SMD,
L5W3.2H0.9
TXC Corporation
2
C96, C97
Resistor, TKF, 0, 1%, 1/10W, SMD,
0402
Panasonic Electronic ERJ-2GE0R00X
Components
Note 1:
Microchip
Technology Inc.
Part Number
Cypress
Semiconductor
Corporation
DSC6003CI2A-024.0000
7B-40.000MAAE-T
The components listed in this Bill of Materials are representative of the PCB assembly. The released BOM
used in manufacturing uses all RoHS-compliant components.
DS50002951A-page 68
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Appendix C. HV7358DB1 Waveforms
C.1
MIC2800 EVALUATION BOARD TEST WAVEFORM EXAMPLES
Appendix C shows sample waveforms created with the MUPB002 and HV7358DB1
combination.
FIGURE C-1:
2020 Microchip Technology Inc.
5 MHz VPP/VNN= ± 80V Load: 330 pF//2.5K.
DS50002951A-page 69
HV7358DB1 User’s Guide
DS50002951A-page 70
FIGURE C-2:
10 MHz VPP/VNN = ±70V Load: 330 pF//2.5K.
FIGURE C-3:
TX Output 20 MHz 4-Cycle 17.8 V(p-p) 330 pF//2.5K Load.
2020 Microchip Technology Inc.
HV7358DB1 Waveforms
FIGURE C-4:
All Channels On.
Ch8-11 VPP/VNN = ±80V, 5 MHz with 330 pF//2.5K,
FIGURE C-5:
Rise Fall Time of ±80V, 5 MHz RTZ, 330 pF//2.5K Load.
2020 Microchip Technology Inc.
DS50002951A-page 71
HV7358DB1 User’s Guide
DS50002951A-page 72
FIGURE C-6:
TX and RX B Mode, 5 MHz, 1-Cycle with 330 pF//2.5k Load.
FIGURE C-7:
TX and RX in PW Mode, 5 MHz, 8-Cycle, 330 pF/2.5K Load.
2020 Microchip Technology Inc.
HV7358DB1 Waveforms
FIGURE C-8:
4-Cycle Canceling, 5 MHz, 4-Cycle Canceling, 5 MHz.
FIGURE C-9:
LNAOut RX0 Signal After TX, 1-Cycle, ±80V.
2020 Microchip Technology Inc.
DS50002951A-page 73
HV7358DB1 User’s Guide
NOTES:
DS50002951A-page 74
2020 Microchip Technology Inc.
HV7358DB1
USER’S GUIDE
Appendix D. HV7358 GUI Parameter and Default
D.1
HV7358 GUI PARAMETER LIMITS AND DEFAULT PAGE-1
HV7358DB1 GUI Parameter Limits and Initial Default Values
GUI SYM
Parameter
Unit
Min
Ini. Default
Max
Note-1
H/W System Variables
VLL
Logic voltage at VLL pin
V
2.375
2.5
3.625
fixed by H/W
VDD
Digital voltage at VDD & AVDD pin
V
4.75
5
5.25
fixed by H/W
VGN
LV bias voltage at VGN pin
V
-5.25
-5
-4.75
fixed by H/W
VPF
Pos gate-drive voltage at CPF pin
V
4.5
5.1
5.2
fixed by H/W
VNF
Neg gate-drive voltage at CNF pin
V
-5.2
-5.2
-4.5
fixed by H/W
ser Entered Variables
HV Positive in CW-Mode
VPP
V
HV Positive in B-Mode
HV Negative in CW-Mode
VNN
V
HV Negative in B-Mode
0
5
7
User must enter a measured value
8
70
81
User must enter a measured value
-7
-5
0
User must enter a measured value
-81
-70
-8
User must enter a measured value
Opposite to CW bit (pin)
Calculated Vriables
B-Mode
fTCK
B-Mode Display
Tx Clock Pin Freq. PEN=1
Binary
MHz
Tx Clock Pin Freq. PEN=0
0
NOT(CW)
1
30
40
80
GUI Select: 30, 40, 65, 80MHz if PEN=1. From SM803004
30
80
200
GUI Select: 80, 120, 160, 200MHz if PEN=0. From SM803004
fC
IC Internal Clock Freq.
MHz
160
Calculated
240
fC=fTCK if PEN=0, fC=N*fTCK if PEN=LCKD=1. See MathCAD Limitation Calculation.
fVCO
PLL VCO freq.
Ultrasound Frequency in B-mode
MHz
160
Calculated
240
No Display
1
Calculated
20
Display on GUI When CW=0
1
Calculated
20
Display on GUI When CW=1
fRF
Ultrasound Frequency in CW-mode
LDR
D% Max
Line Duration
Tx B-mode pulses burst-duty-cycle
MHz
fC Cyc.
%
Tx CW-duty-cycle
5.0E+04 Calculated 1.6E+05 Note: Limited by D%, See MathCAD Limitation Calculation
0
20
100
0
5
8
CW=1 See MathCAD Limitation Calculation
CW=0 See MathCAD Limitation Calculation
t(TXRW)
TX or R/W mode control signal
us
50
Calculated
500
GUI calculated commend to FPGA. See MathCAD Limitation Calculation
Auto Stop
Tx auto stop time
sec
NA
60
300
Demo Tx waveform auto off feature for safety
SPI, Read back from I2C
TGP(0)
Globle-off-time P
fC Cyc.
0
0
127
7-bit (as example of selcted in this table)
TGN(0)
Globle-off-time N
fC Cyc.
0
0
127
7-bit (as example of selcted in this table)
TGW(0)
Globle Pulse Width
fC Cyc.
2
16
511
9-bit (as example of selcted in this table)
RPC(0)
Rep. Pulses #
fC Cyc.
0
3
32
8-bit (as example of selcted in this table)
TGP(1)
Globle-off-time P
fC Cyc.
0
0
127
7-bit
TGN(1)
Globle-off-time N
fC Cyc.
0
0
127
7-bit
TGW(1)
Globle Pulse Width
fC Cyc.
2
16
511
9-bit
RPC(1)
Rep. Pulses #
fC Cyc.
0
2
32
8-bit
TGP(2)
Globle-off-time P
fC Cyc.
0
0
127
7-bit
TGN(2)
Globle-off-time N
fC Cyc.
0
0
127
7-bit
TGW(2)
Globle Pulse Width
fC Cyc.
2
4
511
9-bit
RPC(2)
Rep. Pulses #
fC Cyc.
0
5
32
8-bit
TGP(3)
Globle-off-time P
fC Cyc.
0
0
127
7-bit
TGN(3)
Globle-off-time N
fC Cyc.
0
0
127
7-bit
TGW(3)
Globle Pulse Width
fC Cyc.
2
10
511
9-bit
RPC(3)
Rep. Pulses #
fC Cyc.
0
3
32
8-bit
DLY(0)
Beamform dely Ch-0
fC Cyc.
0
10
4095
12-bit
DLY(1)
Beamform dely Ch-1
fC Cyc.
0
15
4095
12-bit
DLY(2)
Beamform dely Ch-2
fC Cyc.
0
20
4095
12-bit
DLY(3)
Beamform dely Ch-3
fC Cyc.
0
25
4095
12-bit
DLY(4)
Beamform dely Ch-4
fC Cyc.
0
30
4095
12-bit
DLY(5)
Beamform dely Ch-5
fC Cyc.
0
35
4095
12-bit
DLY(6)
Beamform dely Ch-6
fC Cyc.
0
40
4095
12-bit
DLY(7)
Beamform dely Ch-7
fC Cyc.
0
45
4095
12-bit
DLY(8)
Beamform dely Ch-8
fC Cyc.
0
50
4095
12-bit
DLY(9)
Beamform dely Ch-9
fC Cyc.
0
55
4095
12-bit
DLY(10)
Beamform dely Ch-10
fC Cyc.
0
60
4095
12-bit
DLY(11)
Beamform dely Ch-11
fC Cyc.
0
65
4095
12-bit
DLY(12)
Beamform dely Ch-12
fC Cyc.
0
70
4095
12-bit
DLY(13)
Beamform dely Ch-13
fC Cyc.
0
75
4095
12-bit
DLY(14)
Beamform dely Ch-14
fC Cyc.
0
80
4095
12-bit
DLY(15)
Beamform dely Ch-15
fC Cyc.
0
85
4095
12-bit
TLP(0)
Local PWM P-OFF-Time Ch-0
fC Cyc.
0
2
127
7-bit
TLP(1)
Local PWM P-OFF-Time Ch-1
fC Cyc.
0
2
127
7-bit
2020 Microchip Technology Inc.
DS50002951A-page 75
HV7358DB1 User’s Guide
D.2
HV7358DB1 GUI PARAMETER INITIAL VALUE AND LIMITS PAGE-2
HV7358DB1 GUI Parameter Limits and Initial Default Values
GUI SYM
Parameter
Unit
Min
Ini. Default
Max
Note-1
H/W System Variables
VLL
Logic voltage at VLL pin
V
2.375
2.5
3.625
fixed by H/W
VDD
Digital voltage at VDD & AVDD pin
V
4.75
5
5.25
fixed by H/W
VGN
LV bias voltage at VGN pin
V
-5.25
-5
-4.75
fixed by H/W
VPF
Pos gate-drive voltage at CPF pin
V
4.5
5.1
5.2
fixed by H/W
VNF
Neg gate-drive voltage at CNF pin
V
-5.2
-5.2
-4.5
fixed by H/W
ser Entered Variables
HV Positive in CW-Mode
VPP
V
HV Positive in B-Mode
HV Negative in CW-Mode
VNN
V
HV Negative in B-Mode
0
5
7
User must enter a measured value
8
70
81
User must enter a measured value
-7
-5
0
User must enter a measured value
-81
-70
-8
User must enter a measured value
Opposite to CW bit (pin)
Calculated Vriables
B-Mode
fTCK
B-Mode Display
Tx Clock Pin Freq. PEN=1
Binary
MHz
Tx Clock Pin Freq. PEN=0
0
NOT(CW)
1
30
40
80
GUI Select: 30, 40, 65, 80MHz if PEN=1. From SM803004
30
80
200
GUI Select: 80, 120, 160, 200MHz if PEN=0. From SM803004
fC
IC Internal Clock Freq.
MHz
160
Calculated
240
fC=fTCK if PEN=0, fC=N*fTCK if PEN=LCKD=1. See MathCAD Limitation Calculation.
fVCO
PLL VCO freq.
Ultrasound Frequency in B-mode
MHz
160
Calculated
240
No Display
1
Calculated
20
Display on GUI When CW=0
1
Calculated
20
Display on GUI When CW=1
fRF
Ultrasound Frequency in CW-mode
LDR
D% Max
Line Duration
Tx B-mode pulses burst-duty-cycle
MHz
fC Cyc.
%
Tx CW-duty-cycle
5.0E+04 Calculated 1.6E+05 Note: Limited by D%, See MathCAD Limitation Calculation
0
20
100
0
5
8
CW=1 See MathCAD Limitation Calculation
CW=0 See MathCAD Limitation Calculation
t(TXRW)
TX or R/W mode control signal
us
50
Calculated
500
GUI calculated commend to FPGA. See MathCAD Limitation Calculation
Auto Stop
Tx auto stop time
sec
NA
60
300
Demo Tx waveform auto off feature for safety
SPI, Read back from I2C
TGP(0)
Globle-off-time P
fC Cyc.
0
0
127
7-bit (as example of selcted in this table)
TGN(0)
Globle-off-time N
fC Cyc.
0
0
127
7-bit (as example of selcted in this table)
TGW(0)
Globle Pulse Width
fC Cyc.
2
16
511
9-bit (as example of selcted in this table)
RPC(0)
Rep. Pulses #
fC Cyc.
0
3
32
8-bit (as example of selcted in this table)
TGP(1)
Globle-off-time P
fC Cyc.
0
0
127
7-bit
TGN(1)
Globle-off-time N
fC Cyc.
0
0
127
7-bit
TGW(1)
Globle Pulse Width
fC Cyc.
2
16
511
9-bit
RPC(1)
Rep. Pulses #
fC Cyc.
0
2
32
8-bit
TGP(2)
Globle-off-time P
fC Cyc.
0
0
127
7-bit
TGN(2)
Globle-off-time N
fC Cyc.
0
0
127
7-bit
TGW(2)
Globle Pulse Width
fC Cyc.
2
4
511
9-bit
RPC(2)
Rep. Pulses #
fC Cyc.
0
5
32
8-bit
TGP(3)
Globle-off-time P
fC Cyc.
0
0
127
7-bit
TGN(3)
Globle-off-time N
fC Cyc.
0
0
127
7-bit
TGW(3)
Globle Pulse Width
fC Cyc.
2
10
511
9-bit
RPC(3)
Rep. Pulses #
fC Cyc.
0
3
32
8-bit
DLY(0)
Beamform dely Ch-0
fC Cyc.
0
10
4095
12-bit
DLY(1)
Beamform dely Ch-1
fC Cyc.
0
15
4095
12-bit
DLY(2)
Beamform dely Ch-2
fC Cyc.
0
20
4095
12-bit
DLY(3)
Beamform dely Ch-3
fC Cyc.
0
25
4095
12-bit
DLY(4)
Beamform dely Ch-4
fC Cyc.
0
30
4095
12-bit
DLY(5)
Beamform dely Ch-5
fC Cyc.
0
35
4095
12-bit
DLY(6)
Beamform dely Ch-6
fC Cyc.
0
40
4095
12-bit
DLY(7)
Beamform dely Ch-7
fC Cyc.
0
45
4095
12-bit
DLY(8)
Beamform dely Ch-8
fC Cyc.
0
50
4095
12-bit
DLY(9)
Beamform dely Ch-9
fC Cyc.
0
55
4095
12-bit
DLY(10)
Beamform dely Ch-10
fC Cyc.
0
60
4095
12-bit
DLY(11)
Beamform dely Ch-11
fC Cyc.
0
65
4095
12-bit
DLY(12)
Beamform dely Ch-12
fC Cyc.
0
70
4095
12-bit
DLY(13)
Beamform dely Ch-13
fC Cyc.
0
75
4095
12-bit
DLY(14)
Beamform dely Ch-14
fC Cyc.
0
80
4095
12-bit
DLY(15)
Beamform dely Ch-15
fC Cyc.
0
85
4095
12-bit
TLP(0)
Local PWM P-OFF-Time Ch-0
fC Cyc.
0
2
127
7-bit
TLP(1)
Local PWM P-OFF-Time Ch-1
fC Cyc.
0
2
127
7-bit
DS50002951A-page 76
2020 Microchip Technology Inc.
HV7358 GUI Parameter and Default
D.3
HV7358DB1 GUI PARAMETER INITIAL VALUE AND LIMITS PAGE-3
2020 Microchip Technology Inc.
DS50002951A-page 77
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DS50002951A-page 78
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2020 Microchip Technology Inc.
05/14/19
