HV7361LA-G

HV7360/HV7361 High-Speed ±100V 2.5A Two-or-Three-Level Ultrasound Pulsers Features General Description HVCMOS® Technology for High Performance High Density Integration AC-coupled Pulser 0V to ±100V Output Voltage ±2.5A Source and Sink Minimum Pulse Current Up to 35 MHz Operating Frequency 2 ns Matched Delay Times 2.5V, 3.3V or 5V CMOS Logic Interface Built-in Two-terminal Low-noise Interface for HV7361 • Low Power Consumption and No Floating Power Supply Rails or Decoupling Capacitors HV7360/HV7361 are high-voltage and high-speed pulse generators with built-in fast return-to-zero damping Field-Effect Transistors (FETs). An added feature to HV7361 is an integrated two-terminal low-noise T/R switch. These integrated circuits are designed not only for portable medical ultrasound image devices but also for NDT and test equipment applications. • • • • • • • • Applications Both HV7360/HV7361 are composed of controller logic interface circuits, level translators and AC-coupled Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) gate drivers. They also have high-voltage and high-current P-channel and N-channel MOSFETs as output stages. • • • • The peak output currents of each channel are guaranteed to be over ±2.5A with up to ±100V of pulse swing. The AC coupling topology for the gate drivers not only saves two floating voltage supplies but also makes the PCB layout easier. Medical Ultrasound Imaging Piezoelectric Transducer Drivers Ultrasound Industrial NDT Pulse Waveform Generator Package Type 22-lead CABGA (Top View)  2016 Microchip Technology Inc. DS20005570A-page 1 HV7360/HV7361 HV7360 Typical Application Circuit +10V +10V VDD VH 0 to +100V VL3 SP1 +2.5/3.3V VLL PE DP1 HVOUT DN1 INA 0 to -100V 2.5/3.3V Logic Input INB SN1 SP2 INC DP2 IND DN2 GND VSS VL1 SN2 VL2 +/-100V 2.5A Three-level RTZ Transmit Pulsers HV7361 Typical Application Circuit +10V +10V 0 to +100V VDD VH SP1 VL3 +2.5/3.3V VLL PE DP1 DN1 INA 2.5/3.3V Logic Input 0 to -100V INB SN1 INC SP2 IND DP2 DN2 SN2 GND VSS VL1 VL2 RX T/R SW XDCR to Rx LNA +/-100V 2.5A Three-level RTZ Transmit Pulsers with T/R Switch DS20005570A-page 2  2016 Microchip Technology Inc. HV7360/HV7361 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Chip Power Supply Voltage (VDD-VSS) ................................................................................................... –0.5 to +12.5V VH Output High Supply Voltage ......................................................................................................VL–0.5 to VDD +0.5V VL Output Low Supply Voltage..................................................................................................... VSS–0.5V to VH +0.5V VSS Low Side Supply Voltage ....................................................................................................................... –6 to +0.5V Differential High Voltage (VSP1-VSN1), (VSP2-VSN2).............................................................................................. +220V VSP1,2 Positive High Voltage ......................................................................................................................–0.5 to +110V VSN1,2 Negative High Voltage ....................................................................................................................+0.5 to –110V All Logic Input Voltages.............................................................................................................VSS–0.5V to GND +5.5V Rx to XDCR Differential Drop................................................................................................................................ ±140V Coupling Capacitor Breakdown Voltage.................................................................................................................±110V Maximum Junction Temperature ............................................................................................................................125°C Operating Temperature ...............................................................................................................................–20 to +85°C † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. OPERATING SUPPLY VOLTAGES AND CURRENT Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Logic Supply Voltage Range Supply Voltage Sym. Min. Typ. Max. Units VLL 2.25 — 3.63 V VDD-VSS 4.75 — 11.5 V Low Side Supply Voltage VSS –5.5 — 0 V Gate Drive High Side Voltage VH VSS+4 — VDD V Gate Drive Low Side Voltage VL VSS — VDD-4 V Output Positive High Voltage VSP1,2 0 — 100 V Output Negative High Voltage VSN1,2 –100 — 0 V VDD Quiescent Current IDDQ — 50 — μA VH Quiescent Current IHQ — 2 — μA VDD Quiescent Current IDDQ — 1 — mA VH Quiescent Current IHQ — 2 — μA VDD Average Current IDD — 4 — mA VH Average Current IH — 10 — mA Input Logic Voltage High VIH VPE-0.3 — VPE V Input Logic Voltage Low VIL 0 — 0.3 V Input Logic Current High IIH — — 1 μA μA Input Logic Current Low IIL — — 1 PE Input Logic Voltage High VPEH 1.7 3.3 5.25 V PE Input Logic Voltage Low VPEL 0 — 0.3 V PE Input Impedance to GND RINPE 100 — — kΩ  2016 Microchip Technology Inc. Conditions 4 ≤ VDD ≤ 11.5V VH-VL ≥ 4V No input transitions, PE = 0 No input transitions, PE = 1 One channel On at 5 MHz, No load For logic inputs INA, INB, INC and IND For logic input PE DS20005570A-page 3 HV7360/HV7361 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Sym. Min. Typ. Max. Units Input or PE Rise and Fall Time Input to Output Delay Output Rise and Fall Time Rise and Fall Time Matching Propagation Matching Propagation Delay Matching PE On-time tirf td1-4 tr/f1-2 ∆trf ∆tdC2C ∆tdD2D tPE-ON — — — — — — — — 7.5 9.5 2 1 ±2 — 10 — — — — — 5 ns ns ns Logic input edge speed requirement RLOAD = 1Ω CLOAD = 330 pF, RLOAD = 2.5 kΩ ns Channel to channel ns PE Off-time tPE–OFF — — 4 COG CVH — — 10 0.22 — — Device to device delay match VPE = 1.7 ~ 5.25V, VDD = 7.5 ~ 11.5V, –20 ~ 85°C 100V X7S 16V X7R Output to MOSFET Gate Cap VH to VL3 Decoupling Cap µs nF µF Conditions ELECTRICAL CHARACTERISTICS Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Sym. Min. Typ. Max. Units PULSER AND DAMPING P-CHANNEL MOSFET DC PARAMETERS –200 — — V Drain-to-source Breakdown Voltage BVDSS Gate Threshold Voltage VGS(th) –1 — –2.4 V ∆VGS(th) — — 4.5 mV/°C Change in VGS(th) with Temperature RGS 10 — 50 kΩ Gate-to-source Shunt Resistor Gate-to-source Zener Voltage VZGS 13.2 — 25 V Zero-gate Voltage Drain Current ON-state Drain Current Static Drain-to-source ON-state Resistance — — –10 μA — — –1 mA –1.2 –2.3 — — — — –2.5 — — — — — 8.5 7 1 IDSS ID(ON)  RDS(ON) A Ω ∆RDS(ON) %/°C Change in RDS(ON) with Temperature AC PARAMETERS 400 — — mmho Forward Transconductance GFS — 75 — Input Capacitance CISS Common Source Output Capacitance COSS — 21 — pF — 6.5 — Reverse Transfer Capacitance CRSS DIODE PARAMETERS — — 1.8 V Diode Forward Voltage Drop VSBD — 300 — ns Reverse Recovery Time of Body Diode trrBD PULSER AND DAMPING N-CHANNEL MOSFET DC PARAMETERS 200 — — V Drain-to-source Breakdown Voltage BVDSS Gate Threshold Voltage VGS(th) 1 — 2.4 V DS20005570A-page 4 Conditions VGS = 0V, ID = –2 mA VGS = VDS, ID = –1 mA VGS = VDS, ID = –1 mA IGS = 100 µA, if applied IGS = –2 mA, if applied VDS = Maximum rating, VGS = 0V VDS = 0.8 maximum rating, VGS = 0V, TA = 125°C VGS = –5V, VDS = –25V VGS = –10V, VDS = –50V VGS = –5V, ID = –150 mA VGS = –10V, ID = –1A VGS = –10V, ID = –1 mA VDS = –25V, ID = –500 mA VGS = 0V,  VDS = –25V,  f = 1 MHz VGS = 0V, ISD = 500 mA VGS = 0V, ID = 2 mA VGS = VDS, ID = 1 mA  2016 Microchip Technology Inc. HV7360/HV7361 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = –100V, TA = 25°C unless otherwise specified. Parameters Change in VGS(th) with Temperature Gate-to-source Shunt Resistor Gate-to-source Zener Voltage Zero Gate Voltage Drain Current Change in RDS(ON) with Temperature AC PARAMETERS Forward Transconductance Input Capacitance Common Source Output Capacitance Reverse Transfer Capacitance DIODE PARAMETERS Diode Forward Voltage Drop Reverse Recovery Time of Body Diode Min. Typ. Max. Units ∆VGS(th) RGS VZGS — 10 13.2 — — — –4.5 50 25 — — 10 — — 1 ∆RDS(ON) 1.3 2.3 — — — — 2.5 — — — — — 6.5 6 1 mV/°C VGS = VDS, ID = 1 mA kΩ IGS = 100 µA V IGS = 2 mA VDS = Maximum rating,  μA VGS = 0V VDS = 0.8 maximum rating, mA VGS = 0V, TA = 125°C VGS = 5V, VDS = 25V A VGS = 10V, VDS = 50V VGS = 5V, ID = 150 mA Ω VGS = 10V, ID = 1A %/°C VGS = 10V, ID = 1A GFS CISS COSS CRSS 400 — — — — 56 13 2 — — — — mmho VDS = 25V, ID = 500 mA VGS = 0V, pF VDS = 25V, f = 1 MHz VSBD trrBD — — — 300 1.8 — V ns IDSS ON-state Drain Current Static Drain-to-source ON-state Resistance Sym. ID(ON)  RDS(ON) Conditions VGS = 0V, ISD = 500 mA HV7631 T/R SWITCH CHARACTERISTICS Parameters Sym. Min. Typ. Max. Units BVA-B ±130 — — V IA-B = ±1 mA Switch-on Resistance from XDCR to Rx RSW — 15 — Ω IA-B = ±5 mA VA-B Trip Point to Turn Off VTRIP — ±1 ±2 V Breakdown Voltage from XDCR to Rx Switch Turn-off Voltage Conditions VOFF — ±2 — V IA-B = ±1 mA IA-B(OFF) — ±200 ±300 µA VA-B = ±130V Peak Switching Current IPEAK — ±60 — mA Turn-off Time TOFF — — 20 ns Switch-off Current Turn-on Time TON — — 20 ns Switch-on Capacitance from A to B or B to A CSW(ON) — 21 — pF SW = On Switch-off Capacitance from A to B or B to A CSW(OFF) — 15 — pF VSW = 25V BW — 100 — MHz Small Signal Bandwidth  2016 Microchip Technology Inc. RLOAD = 50Ω DS20005570A-page 5 HV7360/HV7361 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, for all specifications TA = TJ = +25°C. Parameters Sym. Min. Typ. Max. Units TJ(MAX) — TA –20 125 — °C — +85 °C JA — 106 — °C/W Conditions TEMPERATURE RANGES Maximum Junction Temperature Operating Temperature PACKAGE THERMAL RESISTANCE 22-Lead CABGA POWER-UP AND POWER-DOWN SEQUENCE (Note 1) Power-Up Step 1 2 3 4 Note 1: Power-Down Description Step Description 1 PE inactive VLL 2 VPP and VNN off VDD, VH, VSS and VL with signal logic low 3 VDD, VH, VSS and VL off VPP and VNN PE active 4 VLL off Powering up or down in any arbitrary sequence will not cause any damage to the device. The power-up sequence and power-down sequence are only recommended to minimize possible inrush current. LOGIC CONTROL TABLE PE 1 0 Input Pulse Output MOSFETs INA INB INC IND 1 X X X 0 X X X X X 1 X X X 0 X X X X X 1 X X X 0 X X X X X 1 X X X 0 X DS20005570A-page 6 SP1 to DP1 DN1 to SN1 SP2 to DP2 DN2 to SN2 ON X X X OFF X X X OFF X ON X X X OFF X X OFF X X ON X X X OFF X OFF X X X ON X X X OFF OFF  2016 Microchip Technology Inc. HV7360/HV7361 2.0 PAD DESCRIPTION Table 2-1 details HV7360/HV7361. TABLE 2-1: the description of pads in PAD FUNCTION TABLE Pad Location HV7360 Symbol HV7361 Symbol A1 GND GND Driver and level translator circuit ground return (0V) A2 IND IND Damping N-FET control signal logic input, controlling N-FET2 Description A3 INC INC Damping P-FET control signal logic input, controlling P-FET2 A4 VSS VSS Negative voltage power supply (0V) A6 VDD VDD Positive voltage supply (+10V), should connect to an external decoupling cap to VSS (0V) A7 INB INB Pulsing N-FET control signal logic input, controlling N-FET1 A8 INA INA Pulsing P-FET control signal logic input, controlling P-FET1 A9 PE PE Drive power enable Hi = On, Low = Off, logic ‘1’ voltage reference input (+2.5V to +3.3V) B2 VL2 VL2 Gate-drive negative voltage power supply (0V) B8 VL1 VL1 Gate-drive negative voltage power supply (0V) F4 VH VH Gate-drive positive voltage power supply (+10V) F7 VL3 VL3 VH to VL decoupling cap. The trace connecting VL1, VL2, and VL3 (0V) to ground plane should be as short as possible. NC — No connection for HV7360 G4 P1 — RX T/R switch output for HV7361 SP2 SP2 Source of P-FET2, positive high voltage power supply (0 to +100V) or GND P2 DP2 DP2 Drain of P-FET2, transmit pulser output P3 DN2 DN2 Drain of N-FET2, transmit pulser output P4 SN2 SN2 NC — — XDCR SP1 SP1 Source of P-FET1, positive high voltage power supply (0 to +100V) P5 P6 Source of N-FET2, negative high voltage power supply (0 to –100V) or GND No connection for HV7360 T/R switch input for HV7361 P7 DP1 DP1 Drain of P-FET1, transmit pulser output P8 DN1 DN1 Drain of N-FET1, transmit pulser output P9 SN1 SN1 Source of N-FET1, negative high voltage power supply (0 to –100V)  2016 Microchip Technology Inc. DS20005570A-page 7 HV7360/HV7361 3.0 FUNCTIONAL DESCRIPTION 50% INA INB 50% INB td3 td1 IOUT INA td4 td2 50% 0A TX + DMP 0A tf2 tr1 50% 90% IOUT TX + DMP 10% tr2 tf1 +10V +10V +100V 10% VDD VH SP1 VL3 +2.5/3.3V VLL 90% PE DP1 INA DN1 R1 -100V INB 2.5/3.3V Logic Input SN1 SP2 INC DP2 IND DN2 SN2 GND VSS VL1 VL2 RX FIGURE 3-1: T/R SW XDCR Pulser Timing Test for HV7360/HV7361. +IPEAK IA-B IA-B = +200μA -130V -VOFF +1.0mA -VTRIP +VTRIP +VOFF VA-B +130V +1.0mA IA-B = -200μA RSW = 15Ω -IPEAK FIGURE 3-2: DS20005570A-page 8 T/R Switch I-V curve for HV7361.  2016 Microchip Technology Inc. HV7360/HV7361 +10V +10V VDD VH 0 to +100V VL3 SP1 +2.5/3.3V VLL PE DP1 HVOUT DN1 INA 0 to -100V INB 2.5/3.3V Logic Input SN1 SP2 INC DP2 IND DN2 GND FIGURE 3-3: HV7360. VSS VL1 VL2 SN2 Typical Bipolar One-channel Three-level Ultrasound Transmitter Application Circuit for +10V +10V 0 to +200V VDD +2.5/3.3V VLL VH VL3 PE DP1 TX1 DN1 INA INB 2.5/3.3V Logic Input SP1 SN1 SP2 INC DP2 IND DN2 GND FIGURE 3-4: HV7361. VSS VL1 VL2 0 to +200V TX2 SN2 Typical Unipolar Two-channel Two-level Ultrasound Transmitter Application Circuit for  2016 Microchip Technology Inc. DS20005570A-page 9 HV7360/HV7361 4.0 PACKAGING INFORMATION 4.1 Package Marking Information Legend: XX...X Y YY WW NNN e3 * Note: XXXXXX XX e3 YYWWNNN HV7360 GA e3 1624111 XXXXXX XX e3 YYWWNNN HV7361 GA e3 1618555 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  DS20005570A-page 10  2016 Microchip Technology Inc. HV7360/HV7361 22-Ball Chip Array Ball Grid Array (JY) - 5x7 mm Body [CABGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.10 C 22X NOTE 1 D A 0.08 C B E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C A1 A2 A eD 2X (0.25) C SEATING PLANE SIDE VIEW eE e 2X (0.50) e 22X Øb 0.15 0.08 eE 2 C A B C BOTTOM VIEW Microchip Technology Drawing C04-414A Sheet 1 of 2  2016 Microchip Technology Inc. DS20005570A-page 11 HV7360/HV7361 22-Ball Chip Array Ball Grid Array (JY) - 5x7 mm Body [CABGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals e Pitch A Overall Height Ball Height A1 A2 Package Thickness Overall Length D eD Overall Terminal Pitch E Overall Width eE Overall Terminal Pitch b Ball Diameter MIN 0.91 0.12 0.66 0.20 MILLIMETERS NOM 22 0.50 BSC 0.98 0.15 0.70 5.00 BSC 4.00 BSC 7.00 BSC 6.50 BSC 0.25 MAX 1.05 0.74 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-414A Sheet 2 of 2 DS20005570A-page 12  2016 Microchip Technology Inc. HV7360/HV7361 22-Ball Chip Array Ball Grid Array (JY) - 5x7 mm Body [CABGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 G E ØX C2 G E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Diameter (X22) X Contact Pad to Contact Pad G MIN MILLIMETERS NOM 0.50 BSC 4.00 6.50 0.25 MAX 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2414A  2016 Microchip Technology Inc. DS20005570A-page 13 HV7360/HV7361 NOTES: DS20005570A-page 14  2016 Microchip Technology Inc. HV7360/HV7361 APPENDIX A: REVISION HISTORY Revision A (June 2016) • Converted Supertex Doc# DSFP-HV7360 and Supertex Doc# DSFP-HV7361 to Microchip DS20005570A. • Meged HV7360 and HV7361 into one document. • Replaced the 22-lead LFGA “LA” package with 22-lead CABGA “GA” package. • Made minor text changes throughout the document. DS20005570A-page 15  2016 Microchip Technology Inc. HV7360/HV7361 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. - Package Options Device X - Environmental X Examples: a) HV7360GA-G: Media Type b) HV7361GA-G: Device: HV7360 = High-voltage High-speed Pulse Generator with Built-in Fast RTZ Damping FETs HV7361 = High-voltage High-speed Pulse Generator with Built-in Fast RTZ Damping FETs and an Integrated Two-terminal Low-noise T/R Switch Packages: GA = 22-lead CABGA Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 364/Tray for GA Package  2016 Microchip Technology Inc. High-voltage High-speed Pulse Generator with Built-in Fast RTZ Damping FET, 22-lead CABGA Package, 364/Tray High-voltage High-speed Pulse  Generator with Built-in Fast RTZ Damping FET and an Integrated Two-terminal Low-noise T/R Switch, 22-lead CABGA Package, 364/Tray DS20005570A-page 16 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2016 Microchip Technology Inc. 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Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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