HV748K6-G

HV748 4-Channel High-Speed Bipolar ±75V 1.25A Ultrasound Pulser Features General Description • • • • • • • • The HV748 is a 4-channel high-voltage high-speed pulse generator. It is designed for portable medical ultrasound applications. This high-voltage and high-speed integrated circuit can also be used for piezoelectric, capacitive or MEMS sensing in ultrasonic non-destructive detection and sonar ranger applications. High-Density Integrated Ultrasound Transmitter 0V to ±75V Output Voltage 1.25A Source and Sink Current in Pulse Mode ±300 mA Current in CW Mode Up to 20 MHz Operating Frequency Matched Delay Times 2.5V to 3.3V CMOS Logic Interface Built-in Output Drain Bleed Resistors Applications • • • • The HV748 consists of a controller logic interface circuit, level translators, MOSFET gate drivers and high-power P-channel and N-channel MOSFETs as the output stages for each channel. The output stages of each channel are designed to provide peak output currents of over ±1.8A for pulsing, when in Mode 4, with up to ±75 volt swings. When in Mode 1, all the output stages drop the peak current to ±400 mA for low-voltage CW mode operation to decrease the power consumption of the IC. The drivers are supplied by two floating power supplies referenced to VPP and VNN. This direct coupling topology of the gate drivers not only eliminates two high-voltage capacitors per channel but also makes the PCB layout easier. Portable Medical Ultrasound Imaging Piezoelectric Transducer Drivers Non-Destructive Testing Pulse Waveform Generator Package Type 48-lead (7 X 7) VQFN (Top view) 48 1 See Table 2-1 for pin information.  2018 Microchip Technology Inc. DS20005898A-page 1 HV748 Functional Block Diagram +9.0V +1.8 to 3.3V +75V C1 C2 C3 VLL VDD VSUB OTP EN MC0 +1.8 to 3.3V Logic VPP -9.0V C4 0 to +75V C5 VPF VPP SUB RGND EN_PWR Level Translator MC1 PIN1 Level Translator NIN1 RP1 P-Driver N-Driver VSS HV748 TXN1 D2 HVOUT1 X1 RGND VNF C7 VNN +9.0V DS20005898A-page 2 D1 RN1 1 of 4 Channels GREF TXP1 VNN C6 0 to -75V  2018 Microchip Technology Inc. HV748 Typical Application Circuit  2018 Microchip Technology Inc. DS20005898A-page 3 HV748 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Power Supply Reference, VSS .................................................................................................................................... 0V Positive Logic Supply, VLL ......................................................................................................................... –0.5V to +7V Positive Logic and Level Translator Supply, VDD .................................................................................... –0.5V to +14V Positive Floating Gate Drive Supply, VPP–VPF ........................................................................................ –0.5V to +14V Negative Floating Gate Drive Supply, VNF–VNN ...................................................................................... –0.5V to +14V Differential High-Voltage Supply, VPP–VNN .......................................................................................................... +170V High-Voltage Positive Supply, VPP .......................................................................................................... –0.5V to +85V High-Voltage Negative Supply, VNN ........................................................................................................ –0.5V to –85V Overtemperature Protection Output, OTP.................................................................................................. –0.5V to +7V All Logic Input PINX, NINX and EN Voltages ............................................................................................. –0.5V to +7V Substrate to VSS Voltage Difference, VSUB–VSS .................................................................................................. +170V VPP to TXPX Voltage Difference, VPP–TXPX ......................................................................................................... +170V Substrate to TXPX Voltage Difference, VSUB–TXPX ............................................................................................. +170V TXNX to VNN Voltage Difference, TXNX–VNN ....................................................................................................... +170V Operating Junction Temperature, TJ .................................................................................................... –40°C to +125°C Storage Temperature, TS ..................................................................................................................... –65°C to +150°C ESD Rating (Note 1) ............................................................................................................................... ESD Sensitive † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Devices are ESD sensitive. Handling precautions are recommended. OPERATING SUPPLY VOLTAGES AND CURRENT  (FOUR ACTIVE CHANNELS) Electrical Specifications: VSS = 0V, VLL = +3.3V, VDD = +9V, VPP–VPF = +9V, VNN–VNF = –9V, VPP =+75V, VNN = –75V, TA = 25°C unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit 1.2 1.8 to 3.3 5 V Logic Voltage Reference VLL Internal Voltage Supply VDD 8 9 12 V Positive Gate Driver Supply VPF (VPP–12) (VPP–9) (VPP–8) V Negative Gate Drive Supply VNF (VNN+8) (VNN+9) (VNN+12) V IC Substrate Voltage VSUB VDD VPP +75 V Positive High-Voltage Supply VPP 0 — +75 V Negative High-Voltage Supply VNN –75 — 0 V SRMAX — — 25 V/μs Slew Rate Limit of VPP, VNN Conditions Floating driver voltage supplies Must be the most positive potential of the IC Built-in slew rate detection protection (Note 1) VLL Current EN = Low ILL — 35 120 μA VDD Current EN = Low IDDQ — 15 — μA VDD Current EN = High IDDEN — 0.75 2 mA f = 0 MHz VDD Current MODE = 4 IDDEN — 0.75 — mA VDD Current MODE = 1 IDDENCW — 2 — mA f = 5 MHz, continuous, no load VPP Current EN = Low IPPQ — 10 25 μA f = 0 MHz Note 1: Design guidance only DS20005898A-page 4  2018 Microchip Technology Inc. HV748 OPERATING SUPPLY VOLTAGES AND CURRENT  (FOUR ACTIVE CHANNELS) (CONTINUED) Electrical Specifications: VSS = 0V, VLL = +3.3V, VDD = +9V, VPP–VPF = +9V, VNN–VNF = –9V, VPP =+75V, VNN = –75V, TA = 25°C unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit Conditions VPP Current MODE = 4 IPPEN — 250 — mA VPP Current MODE = 1 IPPENCW — 170 — mA f = 5 MHz, continuous no load VNN Current EN = Low INNQ — 15 30 μA f = 0 MHz VNN Current MODE = 4 INNEN — 250 — mA f = 5 MHz, continuous, No load VNN Current MODE = 1 INNENCW — 170 — mA VPF Current EN = Low IPFQ — 10 25 μA f = 0 MHz VPF Current MODE = 4 IPFEN — 50 — mA VPF Current MODE = 1 IPFENCW — 12 — mA f = 5 MHz, continuous, No load VNF Current EN = Low INFQ — 20 30 μA f = 0 MHz VNF Current MODE = 4 INFEN — 25 — mA VNF Current MODE = 1 INFENCW — 12 — mA f = 5 MHz, continuous, No load Note 1: Design guidance only UNDERVOLTAGE AND OVERTEMPERATURE PROTECTION Parameter Open Drain Pull-Up Voltage Sym. Min. Typ. Max. Unit VPULL_UP — — 5 V VUVDD 3.5 — 6.5 V VLL Threshold VUVLL 0.7 — 1 V VPF, VNF Threshold VUVVF 3.5 — 6.5 V OTP Flag Output Low Voltage VOL_OTP — — 1 V Maximum Open-Drain Output Current IOTP — 1 — mA Overtemperature Threshold TOTP 95 110 125 THYS — VDD Threshold OTP Output Reset Hysteresis 7 — °C Conditions VLL = 3.3V, OTP = Active, IPULL_UP = 1 mA If overtemperature occurred, OTP low and all TX outputs will be High-Z. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: VSS = 0V, VLL = +3.3V, VDD = +9V, VPP–VPF = +9V, VNN–VNF = –9V, VPP = +75V, VNN = –75V, TA = 25°C unless otherwise specified. Parameter Sym. Min. Typ. P-CHANNEL MOSFET OUTPUT, TXP1-4 (MC [1:0] = 11b) 1.25 1.8 Output Saturation Current IOUT — 8 Channel Resistance RON — 100 Output Capacitance COSS N-CHANNEL MOSFET OUTPUT, TXN1-4 (MC [1:0] = 11b) 1.25 1.8 Output Saturation Current IOUT — 7.5 Channel Resistance RON Output Capacitance COSS — 40 MOSFET DRAIN BLEED RESISTOR Note 1: Design guidance only  2018 Microchip Technology Inc. Max. Unit Conditions — — — A Ω pF ISD = 100 mA VDS = 25V, f = 1 MHz (Note 1) — — — A Ω pF ISD = 100 mA VDS = 25V, f = 1 MHz (Note 1) DS20005898A-page 5 HV748 DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: VSS = 0V, VLL = +3.3V, VDD = +9V, VPP–VPF = +9V, VNN–VNF = –9V, VPP = +75V, VNN = –75V, TA = 25°C unless otherwise specified. Parameter Sym. Output Bleed Resistance RP/N1~4 Bleed Resistors Power Limit PRO LOGIC INPUT Input Logic High Voltage VIH Input Logic Low Voltage VIL Input Logic High Current IIH Input Logic Low Current IIL Input Logic Capacitance CIN Note 1: Design guidance only Min. Typ. Max. Unit Conditions 10 — 15 — 30 40 kΩ mW Note 1 (VLL–0.4) 0 — –10 — — — — — — VLL 0.4 10 — 5 V V μA μA pF Note 1 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VSS = 0V, VLL = +3.3V, VDD = +9V, VPP–VPF = +9V, VNN–VNF = –9V, VPP = +75V, VNN = –75V, TA = 25°C unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit Output Rise Time tr — 35 — ns Output Fall Time tf — 43 — ns Output Frequency Range fOUT — — 20 Second Harmonic Distortion Conditions 330 pF//2.5 kΩ load MHz 100Ω resistor load HD2 — –40 — dB 100Ω resistor load (Note 1) Enable Time tEN — 180 500 μs 100Ω resistor load Disable Time tDIS — 2.8 10 μs 100Ω resistor load Delay Time on Inputs Rise tdr — 18 — ns Delay Time on Inputs Fall tdf — 18 — ns 3.9Ω resistor load  (See Timing Waveforms.) ∆tDELAY — ±2 — ns P to N, channel to channel tdm — 2.5 10 μs 100Ω resistor load VPP/VNN = ±25V, input tr 50% to HVOUT tr or tf 50%, with 330 pF//2.5 kΩ load (Note 1) Delay Time Matching Delay on Mode Change Delay Jitter on Rise or Fall Note 1: tj — 15 — ps Design guidance only TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Operating Junction Temperature TJ –40 — +125 °C Storage Temperature TS –65 — +150 °C Conditions TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE 48-lead VQFN JA — 18 — °C/W 48-lead VQFN  (Junction to Thermal Pad) JC — 2 — °C/W DS20005898A-page 6  2018 Microchip Technology Inc. HV748 Timing Waveforms NINx PINx 90% VPP tf OUTPUT 10% 0 10% tr VNN  2018 Microchip Technology Inc. 90% DS20005898A-page 7 HV748 2.0 PIN DESCRIPTION The details on the pins of HV748 are listed in Table 2-1. Refer to Package Type for the location of pins. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name Description 1 VDD Positive internal voltage supply (+9V) 2 VSS Power supply return (0V) 3 PIN1 Input logic control of high-voltage output P-FET of channel 1, High = on, Low = off 4 NIN1 Input logic control of high-voltage output N-FET of channel 1, High = on, Low = off 5 PIN2 Input logic control of high-voltage output P-FET of channel 2, High = on, Low = off 6 NIN2 Input logic control of high-voltage output N-FET of channel 2, High = on, Low = off 7 PIN3 Input logic control of high-voltage output P-FET of channel 3, High = on, Low = off 8 NIN3 Input logic control of high-voltage output N-FET of channel 3, High = on, Low = off 9 PIN4 Input logic control of high-voltage output P-FET of channel 4, High = on, Low = off 10 NIN4 Input logic control of high-voltage output N-FET of channel 4, High = on, Low = off 11 VSS Power supply return (0V) 12 VDD Positive internal voltage supply (+9V) 13 OTP Overtemperature protection output, open N-FET drain, active low if IC temperature >110°C. 14 MC1 15 MC0 16 Output Current mode control pins (See Table 3-3.) Substrate of the IC. Substrate bottom is internally connected to the central thermal Thermal pad on the bottom of package. It must be connected to VSUB, the most positive Pad (VSUB) potential of the IC externally. 17 VPF P-FET drive floating power supply, (VPP–VPF) = +9V VPP Positive high-voltage power supply (+75V) VNN Negative high-voltage power supply (–75V) VNF N-FET drive floating power supply, (VNF–VNN) = +9V 18 19 20 21 22 23 24 25 Substrate of the IC. Substrate bottom is internally connected to the central thermal Thermal pad on the bottom of package. It must be connected to VSUB, the most positive Pad (VSUB) potential of the IC externally. 26 RGND Bleed resistors common return ground. (Both pins must be used.) 27 TXN4 Output N-FET drain (open drain output) for Channel 4 28 TXP4 Output P-FET drain (open drain output) for Channel 4 29 TXN3 Output N-FET drain (open drain output) for Channel 3 30 TXP3 Output P-FET drain (open drain output) for Channel 3 31 TXN2 Output N-FET drain (open drain output) for Channel 2 32 TXP2 Output P-FET drain (open drain output) for Channel 2 33 TXN1 Output N-FET drain (open drain output) for Channel 1 34 TXP1 Output P-FET drain (open drain output) for Channel 1 35 RGND Bleed resistors common return ground. (Both pins must be used.) DS20005898A-page 8  2018 Microchip Technology Inc. HV748 TABLE 2-1: Pin Number 36 37 PIN FUNCTION TABLE (CONTINUED) Pin Name Description Substrate of the IC. Substrate bottom is internally connected to the central thermal Thermal pad on the bottom of package. It must be connected to VSUB, the most positive Pad (VSUB) potential of the IC externally. VNF N-FET drive floating power supply, (VNF–VNN) = +9V VNN Negative high-voltage power supply (–75V) VPP Positive high-voltage power supply (+75V) VPF P-FET drive floating power supply, (VPP–VPF) = +9V 38 39 40 41 42 43 44 45 Substrate of the IC. Substrate bottom is internally connected to the central thermal Thermal pad on the bottom of package. It must be connected to VSUB, the most positive Pad (VSUB) potential of the IC externally. 46 EN Chip power enable High = on, Low = off 47 GREF Logic Low reference, logic ground (0V) 48 VLL  2018 Microchip Technology Inc. Logic High-voltage reference input (+3.3V) DS20005898A-page 9 HV748 3.0 FUNCTIONAL DESCRIPTION Follow the steps in Table 3-1 to power up and power down the HV748: TABLE 3-1: POWER-UP AND POWER-DOWN SEQUENCE Power-Up Step Power-Down Description Step Description VSUB All logic signals go to low 1 1 2 VLL with logic signal low 2 VPP and VNN 3 VDD 3 (VPP–VPF) and (VNF–VNN) 4 VDD 4 (VPP–VPF) and (VNF –VNN) 5 VPP and VNN 5 VLL 6 Logic control signals 6 VSUB Note: Powering up or powering down in any arbitrary sequence will not damage the device. The power-up sequence and power-down sequence are only recommended to minimize possible inrush current. TABLE 3-2: TRUTH FUNCTION TABLE (ALL MODES) Logic Inputs EN Note 1: Outputs PINX NINX TXPX TXNX 1 0 0 OFF OFF 1 1 0 ON OFF 1 0 1 OFF ON 1 1 1 ON (Note 1) ON (Note 1) 0 X X OFF OFF Not allowed. May damage IC. TABLE 3-3: DRIVE MODE CONTROL TABLE Mode MC1 MC0 ISC (A) (Note 2) RONP (Ω) RON (Ω) (Note 3) 1 0 0 0.41 35 33 2 0 1 0.58 25 23 3 1 0 0.97 15 14 1 1 1.8 8 7.5 4 Note 1: 2: 3: VPP/VNN = +/–75V, VDD = (VPP–VPF) = (VNF–VNN) = +9V ISC is current into 1Ω to GND. RON is calculated from VOUT into 100Ω load. DS20005898A-page 10  2018 Microchip Technology Inc. HV748 VLL OTP EN VSUB VDD VPF VPP SUB RGND EN_PWR MC0 MC1 Level Translator PIN1 RP1 P-Driver TXP1 TXN1 NIN1 Level Translator N-Driver RN1 1of n Channels GREF R1 RGND VSS VNF 50% PINx R2 NINx VNN 50% tdfp tdrp IOUT tdfn tdrn 50% TXPx 0A TXNx 0A 50% IOUT FIGURE 3-1: Switch Test Timing Diagram.  2018 Microchip Technology Inc. DS20005898A-page 11 HV748 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 48-lead QFN XXXXXXXX e3 YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005898A-page 12 Example HV748K6 e3 1831987 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2018 Microchip Technology Inc. HV748 48-Lead QFN Package Outline (K6) 7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 48 48 Note 1 (Index Area D/2 x E/2) 1 1 Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 θ A3 A L Seating Plane L1 Note 2 A1 View B Side View Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Notes: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. 2. 'HSHQGLQJRQWKHPHWKRGRIPDQXIDFWXULQJDPD[LPXPRIPPSXOOEDFN/PD\EHSUHVHQW 3. 7KHLQQHUWLSRIWKHOHDGPD\EHHLWKHUURXQGHGRUVTXDUH Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 0.18 6.85* 1.25 6.85* 1.25 0.25 7.00 - 7.00 - 0.30 7.15* 5.45 7.15* 5.45 e 0.50 BSC L L1 ș 0.30† 0.00 0O 0.40† - - 0.50† 0.15 14O JEDEC Registration MO-220, Variation VKKD-6, Issue K, June 2006. 7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ ‚7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ Drawings are not to scale.   2018 Microchip Technology Inc. DS20005898A-page 13 HV748 NOTES: DS20005898A-page 14  2018 Microchip Technology Inc. HV748 APPENDIX A: REVISION HISTORY Revision A (November 2018) • Converted Supertex Doc# DSFP-HV748 to Microchip DS20005898A • Removed “HVCMOS® Technology for high performance” in the Features section • Changed the package marking format • Made minor text changes throughout the document  2018 Microchip Technology Inc. DS20005898A-page 15 HV748 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. PART NO. Device Device: XX - Package Options HV748 = X - Environmental X Media Type K6 = 48-lead VQFN Environmental: G Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = DS20005898A-page 16 a) HV748K6-G: 4-Channel High-Speed Bipolar ±75V1.25A Ultrasound Pulser, 48-lead VQFN, 260/Tray 4-Channel High-Speed Bipolar ±75V 1.25A Ultrasound Pulser Package: = Example: 260/Tray for a K6 Package  2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3840-3 == ISO/TS 16949 ==  2018 Microchip Technology Inc. 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