HV9911NG-G-M901

HV9911 Switch-Mode LED Driver IC with High Current Accuracy Features General Description • Switch-mode Controller for Single-switch Drivers: - Buck - Boost - Buck-boost - SEPIC • Works with High-side Current Sensing • Closed-loop Control of Output Current • High Pulse-Width Modulation (PWM) Dimming Ratio • Internal 250V Linear Regulator (can be extended using external Zener Diodes) • Internal 2% Voltage Reference (0°C < TA < 85°C) • Constant Frequency or Constant Off-time Operation • Programmable Slope Compensation • Logic Input for Enable and PWM Dimming • +0.2A/-0.4A Gate Driver • Output Short-circuit Protection • Output Overvoltage Protection • Synchronization Capability • Programmable Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) Current Limit The HV9911 is an LED driver IC designed to control single-switch PWM converters (buck, boost, buck-boost and SEPIC) in a Constant Frequency or Constant Off-time mode. The controller uses a peak current control scheme with programmable slope compensation and includes an internal transconductance amplifier to control the output current in closed loop, enabling high output current accuracy. In the Constant Frequency mode, multiple HV9911s can be synchronized with each other or with an external clock using the sync pin. Programmable MOSFET current limit enables current limiting during Input Undervoltage and Output Overload conditions. The IC also includes a 0.2A source and 0.4A sink gate driver for high-power applications. An internal 9V–250V linear regulator powers the IC, eliminating the need for a separate power supply. The HV9911 provides a TTL-compatible PWM dimming input that can accept an external control signal with a duty ratio of 0%–100% and a frequency of up to a few kilohertz. The IC also provides a FAULT output which, can be used to disconnect the LEDs in case of a Fault condition, using an external disconnect FET. The HV9911-based LED driver is ideal for RGB backlight applications with DC inputs. HV9911-based LED lamp drivers can achieve efficiency in excess of 90% for buck and boost applications. Applications • RGB Backlight Applications • Battery-powered LED Lamps • Other DC/DC LED Drivers Package Type 16-lead SOIC (Top view) VIN 1 16 FDBK 2 15 IREF GATE 3 14 COMP GND 4 13 PWMD CS 5 12 OVP SC 6 11 FAULT RT 7 10 REF 8 9 CLIM VDD SYNC See Table 2-1 for pin information.  2017 Microchip Technology Inc. DS20005580A-page 1 HV9911 Functional Block Diagram Linear Regulator VIN Vbg REF POR VDD GATE _ CLIM DIS + Blanking 100ns FAULT + CS Q R _ ramp + _ SC + _ FDBK Gm 13R Q R Q S POR + S _ 1:2 OVP DIS _ SYNC + IREF VBG R One Shot RT COMP DIS 2 PWMD DS20005580A-page 2 GND  2017 Microchip Technology Inc. HV9911 Typical Application Circuit (Boost) L1 CIN 1 D1 Q1 VIN GATE 3 5 CDD RSC 2 VDD CS 4 GND OVP 12 6 SC FAULT 11 7 RT RCS ROVP1 CO ROVP2 SC RSLOPE HV9911 RT FDBK 16 CREF RL2 Q2 CC 10 REF COMP 14 9 CLIM PWMD 13 15 IREF SYNC 8 RL1 RR1 RS RR2 Typical Application Circuit (Buck) RS CIN 1 VIN 2 VDD 4 GND 6 SC OVP CO D1 12 CDD HV7800 L1 FAULT 11 GATE 3 CS 5 Q1 RSLOPE RT HV9911 7 RT COMP 14 CREF 10 REF RL2 9 RSC RCS CC FDBK 16 CLIM PWMD 13 15 IREF SYNC 8 RL1 RR1 RR2  2017 Microchip Technology Inc. DS20005580A-page 3 HV9911 Typical Application Circuit (SEPIC) L1 D1 L2 1 VIN 2 VDD CS 4 GND OVP 12 6 SC FAULT 11 GATE 3 5 CDD RSC RSLOPE RT RR1 DS20005580A-page 4 CO ROVP2 Q2 7 RT FDBK 16 CC RL1 RCS ROVP1 HV9911 CREF RL2 C1 Q1 CIN 10 REF COMP 14 9 CLIM PWMD 13 15 IREF SYNC 8 RS RR2  2017 Microchip Technology Inc. HV9911 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VIN to GND................................................................................................................................................ –0.5 to +250V VDD to GND............................................................................................................................................ –0.3V to +13.5V CS to GND ...................................................................................................................................... –0.3V to (VDD+0.3V) PWMD to GND................................................................................................................................ –0.3V to (VDD+0.3V) Gate to GND ................................................................................................................................... –0.3V to (VDD+0.3V) All Other Pins to GND ..................................................................................................................... –0.3V to (VDD+0.3V) Continuous Power Dissipation (TA= +25°C; Derate 10 mW/°C above +25°C) ................................................ 1000 mW Operating Ambient Temperature, TA .......................................................................................................–40°C to +85°C Maximum Junction Temperature, TJ(MAX) ...........................................................................................................+125°C Storage Temperature, TS ......................................................................................................................–65°C to +150°C † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = 25°C and VIN = 24V unless otherwise specified. Sym. Min. Typ. Max. Unit INPUT Input DC Supply Voltage Range Parameter Conditions VINDC Note 2 — 250 V Shutdown Mode Supply Current IINSD — 1 1.5 mA VDD 7.25 7.75 8.25 V VIN = 9V–250V, IDD(EXT) = 0, PWMD connected to GND (Note 1) UVLO 6.65 6.9 7.2 V VDD Rising ∆UVLO — 500 — mV VDD(EXT) — — 12 V DC input voltage (Note 1) PWMD connected to GND, VIN = 24V (Note 1) INTERNAL REGULATOR Internally Regulated Voltage VDD Undervoltage Lockout Threshold VDD Undervoltage Lockout Hysteresis Steady State External Voltage that can be applied at the VDD Pin REFERENCE Note 3 REF bypassed with a 0.1 µF capacitor to GND, IREF = 0, VDD = 7.75V, PWMD = GND (Note 1) REF bypassed with a 0.1 µF Line Regulation of Reference capacitor to GND, IREF = 0, VREFLINE 0 — 20 mV Voltage VDD = 7.25V–12V,  PWMD = GND Note 1: Denotes specifications which apply over the full operating ambient temperature range of  –40°C < TA < +85°C 2: See Section 3.3 “Minimum Input Voltage at VIN Pin” for minimum input voltage. 3: Parameters might not be within specifications if the external VDD voltage is greater than VDD(EXT) or if VDD is less than 7.25V. 4: For design guidance only REF Pin Voltage  2017 Microchip Technology Inc. VREF 1.225 1.25 1.275 V DS20005580A-page 5 HV9911 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: TA = 25°C and VIN = 24V unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit Conditions VREFLOAD 0 — 10 mV REF bypassed with a 0.1 µF capacitor to GND,  IREF = 0µ–500µ,  PWMD = GND VPWMD(LO) VPWMD(HI) RPWMD — 2 50 — — 100 0.8 — 150 V V kΩ VDD = 7.25V–12V (Note 1) VDD = 7.25V–12V (Note 1) VPWMD = 5V ISOURCE ISINK TRISE TFALL 0.2 0.4 — — — — 50 25 — — 85 45 A A ns ns VGATE = 0V, VDD = 7.75V VGATE = 7.75V, VDD = 7.75V CGATE = 1 nF, VDD = 7.75V CGATE = 1 nF, VDD = 7.75V VOVP 1.215 1.25 1.285 V VDD = 7.25V–12V,  OVP rising (Note 1) CURRENT SENSE Leading Edge Blanking TBLANK 100 — 375 ns Delay to Output of COMP Comparator TDELAY1 — — 180 ns Delay to Output of CLIMIT Comparator TDELAY2 — — 180 ns –10 — 10 mV Load Regulation of Reference Voltage PMW DIMMING PWMD Input Low Voltage PWMD Input High Voltage PWMD Pull-down Resistance GATE Gate Short-circuit Current Gate Sinking Current Gate Output Rise Time Gate Output Fall Time OVERVOLTAGE PROTECTION IC Shutdown Voltage Comparator Offset Voltage VOFFSET INTERNAL TRANSCONDUCTANCE OPAMP Gain Bandwidth Product GB — 1 — MHz Open-loop DC Gain Input Common Mode Range Output Voltage Range Transconductance Input Offset Voltage Input Bias Current OSCILLATOR AV VCM VO gm 66 –0.3 0.7 340 –2 — — — — 435 — 0.5 — 3 6.75 530 4 1 dB V — µA/V mV nA VOFFSET IBIAS COMP = VDD, CLIM = REF, VCS = 0 mV to 600 mV  (step up) COMP = VDD, CLIM = 300 mV, VCS = 0 mV to 400 mV (step up) 75 pF capacitance at COMP pin (Note 4) Output open Note 4 VDD = 7.75V (Note 4) Note 4 88 100 112 kHz RT = 909 kΩ (Note 1) 308 350 392 kHz RT = 261 kΩ (Note 1) Maximum Duty Cycle — 90 — % Sync Output Current IOUTSYNC — 10 20 µA Sync Input Current IINSYNC 0 — 200 µA VSYNC < 0.1V Note 1: Denotes specifications which apply over the full operating ambient temperature range of  –40°C < TA < +85°C 2: See Section 3.3 “Minimum Input Voltage at VIN Pin” for minimum input voltage. 3: Parameters might not be within specifications if the external VDD voltage is greater than VDD(EXT) or if VDD is less than 7.25V. 4: For design guidance only Oscillator Frequency DS20005580A-page 6 fOSC1 fOSC2 DMAX  2017 Microchip Technology Inc. HV9911 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: TA = 25°C and VIN = 24V unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit Conditions TOFF — — 250 ns IREF = 200 mV,  FDBK = 450 mV, FAULT goes from high to low Fault Output Rise Time TRISE, FAULT — — 300 ns 1 nF capacitor at FAULT pin Fault Output Fall Time Amplifier Gain at IREF Pin SLOPE COMPENSATION Current sourced out of SC Pin TFALL, FAULT GFAULT — 1.8 — 2 200 2.2 ns — 1 nF capacitor at FAULT pin IREF = 200 mV ISLOPE 0 — 100 µA OUTPUT SHORT CIRCUIT  Propagation Time for Short-circuit Detection ISLOPE = 50 µA,  RCSENSE= 1 kΩ Denotes specifications which apply over the full operating ambient temperature range of  –40°C < TA < +85°C See Section 3.3 “Minimum Input Voltage at VIN Pin” for minimum input voltage. Parameters might not be within specifications if the external VDD voltage is greater than VDD(EXT) or if VDD is less than 7.25V. For design guidance only Internal Current Mirror Ratio Note 1: 2: 3: 4: GSLOPE 1.8 2 2.2 — TEMPERATURE SPECIFICATIONS Temperature Characteristics: Unless otherwise noted, for all specifications TA =TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Operating Ambient Temperature TA –40 — +85 °C Maximum Junction Temperature TJ(MAX) — — +125 °C Ts –65 — +150 °C JA — 83 — °C/W Conditions TEMPERATURE RANGE Storage Temperature PACKAGE THERMAL RESISTANCE 16-lead SOIC  2017 Microchip Technology Inc. DS20005580A-page 7 HV9911 2.0 PIN DESCRIPTION Table 2-1 shows the description of pins in HV9911. Refer to Package Type for the location of pins. TABLE 2-1: PIN DESCRIPTION TABLE Pin Number Pin Name Description 1 VIN 2 VDD 3 Gate 4 GND 5 CS 6 SC 7 RT 8 Sync 9 CLIM 10 REF 11 FAULT 12 OVP 13 PWMD 14 COMP 15 IREF 16 FDBK This pin is the input of a 250V high-voltage regulator. This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND (at least 0.1 uF). This pin is the output gate driver for an external N-channel power MOSFET. This is the ground return for all circuits. This pin must be connected to the return path from the input. This pin is used to sense the drain current of the external power FET. It includes a built-in 100 ns (minimum) blanking time. This is slope compensation for current sense. A resistor between SC and GND will program the slope compensation. In case of constant Off-time mode of operation, slope compensation is unnecessary and the pin can be left open. This pin sets the frequency or the off-time of the power circuit. A resistor between RT and GND will program the circuit in Constant Frequency mode. A resistor between RT and gate will program the circuit in a constant Off-time mode. This I/O pin may be connected to the sync pin of other HV9911 circuits and will cause the oscillators to lock to the highest frequency oscillator. This pin provides a programmable input current limit for the converter. The current limit can be set by using a resistor divider from the REF pin. This pin provides 2% accurate reference voltage. It must be bypassed with at least a 10 nF–0.22 µF capacitor to GND. This pin is pulled to ground when there is an Output Short-circuit condition or Output Overvoltage condition. This pin can be used to drive an external MOSFET in the case of boost converters to disconnect the load from the source. This pin provides the overvoltage protection for the converter. When the voltage at this pin exceeds 1.25V, the gate output of the HV9911 is turned off and FAULT goes low. The IC will turn on when the power is recycled. When this pin is pulled to GND (or left open), switching of the HV9911 is disabled. When an external TTL high level is applied to it, switching will resume. Stable closed-loop control can be accomplished by connecting a compensation network between COMP and GND. The voltage at this pin sets the output current level. The current reference can be set using a resistor divider from the REF pin. This pin provides output current feedback to the HV9911 by using a current sense resistor. DS20005580A-page 8  2017 Microchip Technology Inc. HV9911 3.0 DETAILED DESCRIPTION 3.1 Power Topology The built-in linear regulator of the HV9911 can operate up to 250V at the VIN pin. The linear regulator provides an internally regulated voltage of 7.75V (typical) at VDD if the input voltage is within 9V to 250V. This voltage is used to power the IC and also provide the power to external circuits connected at the VDD and VREF pins. This linear regulator can be turned off by overdriving the VDD pin using an external bootstrap circuit at voltages higher than 8.25V (up to 12V). In practice, the input voltage range of the IC is limited by the current drawn by the IC. Thus, it becomes important to determine the current drawn by the IC to find out the maximum and minimum operating voltages at the VIN pin. The main component of the current drawn by the IC is the current drawn by the switching FET driver at the gate pin. To estimate this current, we need to know a few parameters of the FET being used in the design and the switching frequency. The typical waveform of the current being sourced out of gate is illustrated in Figure 3-1. Figure 3-2 shows the equivalent circuit of the gate driver and the external FET. The values of VDD and RGATE for the HV9911 are 7.75V and 40Ω, respectively. Note: The equations given below are approximations and are to be used for estimation purposes only. The actual values will likely differ from the computed values. Consider the case when the external FET is FDS3692 and the switching frequency is fS = 200 kHz with an LED string voltage VO = 80V. With the FET’s specifications, the following parameters can be determined: C ISS = 746pF C GD = C RSS = 27pF C GS = C ISS – C GD = 719pF V TH = 3V IPK I1 Iavg 0 FIGURE 3-1: t1 t3 t2 Current Sourced Out of Gate at FET Turn-on Driver. CGD RGATE VDD HV9911 FIGURE 3-2: CGS Equivalent Circuit of the Gate Driver.  2017 Microchip Technology Inc. DS20005580A-page 9 HV9911 When the external FET is being turned on, current is being sourced out of the gate, and that current is being drawn from the input. Thus, the average current drawn from VDD (and from VIN) needs to be computed. Without going into the details of the FET operation, the various values in the graph in Figure 3-1 can be computed as specified in Table 3-1. TABLE 3-1: Parameter Formula Value (for a given example) IPK VDD/RGATE 193.75 mA I1 (VDD – VTH)/RGATE 118.75 mA t1 –RGATE x CISS x In (I1/IPK) 14.61 ns t2 [(VO – VTH) x CGD]/I1 ( 1) 17.5 ns [(VIN – VTH) x GD]/I1 ( 2) t3 2.3 x RGATE x CGS 66 ns Iavg [I1 x (t1 + t2) + 0.5 x (IPK – I1) x t1 + 0.5 x I1 x t3] x fS 1.66 mA Note 1: 2: For a boost converter For a buck converter The total current being drawn from the linear regulator for a typical HV9911 circuit can be computed as shown in Table 3-2. TABLE 3-2: Current Quiescent Current Formula Typical Value ( 2) 1000 µA 1000 µA Current sourced out of REF pin (VREF/RL1 + RL2) + (VREF/RR1 + RR2) 100 µA Current sourced out of RT pin 6V/RT 13.25 µA Current sourced out of SC pin ( 1) (1/2) x (2.5V/RSLOPE) 30.8 µA Current sourced out of CS pin ( 1) 2.5V/RSLOPE 61.6 µA Current drawn by FET Gate Driver IAVG 1660 µA Total Current drawn from the Linear Regulator Note 1: 2: 3.2 Maximum Input Voltage at VIN Pin Computed using the Power Dissipation Limit When the regulator is drawing about 2.8 mA, the maximum input voltage that the HV9911 can withstand without damage will depend on the ambient temperature. If we consider an ambient temperature of 40°C, the power dissipation in the package cannot exceed the PMAX in Equation 3-1: EQUATION 3-1: P MAX = 1000mW – 10mW   40C – 25C  = 850mW The above equation is based on package power dissipation limits as indicated in the Absolute Maximum Ratings † of this data sheet. To dissipate a maximum power of 850 mW in the package, the maximum input voltage cannot exceed the value in Equation 3-2: EQUATION 3-2: V INMAX = P MAX  I TOTAL = 296V Since the maximum voltage is far greater than the actual input voltage of 24V, power dissipation will not be a problem for this design. For this design, at 24V input, the increase in the junction temperature of the IC (over ambient) is determined as show in Equation 3-3: EQUATION 3-3:  = V IN  I TOTAL   ja = 5.64C Where: θja is the junction to ambient thermal impedance of HV9911’s 16-lead SOIC package. 2.865 mA For a Discontinuous mode converter, the currents sourced out of the SC and CS pins will be zero. The values provided are based on the Continuous Conduction mode boost design in the Microchip application note, “AN-H55 Boost Converter LED Drivers Using the HV9911.” DS20005580A-page 10  2017 Microchip Technology Inc. HV9911 3.3 Minimum Input Voltage at VIN Pin The minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. The internal linear regulator will control the voltage at the VDD pin when VIN is between 9V and 250V. However, when VIN is less than 9V, the converter will still function as long as VDD is greater than the undervoltage lockout. Thus, the converter might be able to start at input voltages lower than 9V. The start/stop voltages at the VIN pin can be determined using the minimum voltage drop across the linear regulator as a function of the current drawn. This data is shown in Figure 3-3 for different junction temperatures. 14 -40°C 13 12 Input Current (mA) 11 25°C 10 9 Note: 3.4 Reference The HV9911 includes a 2% accurate 1.25V reference, which can be used as the reference for the output current as well as to set the switch current limit. This reference is also used internally to set the overvoltage protection threshold. The reference is buffered so that it can deliver a maximum of 500 µA external current to drive the external circuitry. The reference should be bypassed with at least a 10 nF low ESR capacitor. Note: 85°C 8 In some cases, if the gate drive draws too much current, VIN(START) might be less than VIN(STOP). In such cases, the control IC will oscillate between on and off if the input voltage is between the start and stop voltages. In these circumstances, it is recommended that the input voltage be kept higher than VIN(STOP). 125°C 7 To avoid abnormal startup conditions, the bypass capacitor at the REF pin should not exceed 0.22 µF. 6 3.5 5 4 3 2 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Minimum drop in Linear Regulator (V) FIGURE 3-3: Graph of the Input Current vs. Minimum Voltage Drop Across Linear Regulator for Different Junction Temperatures. Assume a maximum junction temperature of 85°C (this gives a reasonable temperature rise of 45°C at an ambient temperature of 40°C). At 2.86 mA input current, the minimum voltage drop from Figure 3-3 can be approximately estimated to be VDROP = 0.75V. However, before the IC starts switching, the current drawn will be the total current minus the gate drive current. In this case, that current is IQ_TOTAL = 1.2 mA. At this current level, the voltage drop is approximately VDROP1 = 0.4V. Thus, the start/stop VIN voltages can be computed as demonstrated in Equation 3-4 and Equation 3-5 below. EQUATION 3-4: V IN  START  = UVLO MAX + V DROP1 = 7.2V + 0.4V = 7.60V EQUATION 3-5: V IN  STOP  = UVLO MAX – 0.5V + V DROP = 7.2V – 0.5V + 0.75V = 7.45V  2017 Microchip Technology Inc. Oscillator The oscillator can be set in two ways. Connecting the oscillator resistor between the RT and gate pins will program the off-time. Connecting the resistor between RT and GND will program the time period. In both cases, resistor RT sets the current, which charges an internal oscillator capacitor. The capacitor voltage ramps up linearly and when the voltage increases beyond the internal set voltage, a comparator triggers the set input of the internal SR flip-flop. This starts the next switching cycle. The time period of the oscillator can be computed as shown in Equation 3-6. EQUATION 3-6: T S  R T  11pF 3.6 Slope Compensation For converters operating in the Constant Frequency mode, slope compensation becomes necessary to ensure stability of the Peak Current mode controller, if the operating duty cycle is greater than 50%. Choosing a slope compensation which is one half of the down slope of the inductor current ensures that the converter will be stable for all duty cycles. Slope compensation can be programmed by two resistors RSLOPE and RSC. Assuming a down slope of DS (A/µs) for the inductor current, the slope compensation resistors can be computed as illustrated in Equation 3-7. DS20005580A-page 11 HV9911 3.9 EQUATION 3-7: 6 R SLOPE =  10  R SC    DS  10  T S  R CS  A typical value for RSC is 499Ω. Note: 3.7 The maximum current that can be sourced out of the SC pin is 100 µA. This limits the minimum value of the RSLOPE resistor to 25 kΩ. If the equation for slope compensation produces a value of RSLOPE less than this value, then RSC would have to be increased accordingly. It is recommended that RSLOPE be chosen within the range of 25 kΩ–50 kΩ. Current Sense The current sense input of the HV9911 includes a built-in 100 ns (minimum) blanking time to prevent spurious turn off due to the initial current spike when the FET turns on. The HV9911 includes two high-speed comparators— one is used during normal operation and the other is used to limit the maximum input current during Input Undervoltage or Overload conditions. The IC includes an internal resistor divider network, which steps down the voltage at the COMP pin by a factor of 15. This stepped-down voltage is given to one of the comparators as the current reference. The reference to the other comparator, which acts to limit the maximum inductor current, is given externally. It is recommended that the sense resistor RCS be chosen so as to provide about 250 mV current sense signal. 3.8 Current Limit Current limit has to be set by a resistor divider from the 1.25V reference available on the IC. Assuming a maximum operating inductor current Ipk (including the ripple current), the voltage at the CLIM pin can be set as shown in Equation 3-8. EQUATION 3-8: V CLIM  1.2  I PK  R CS +  5  R SC  R SLOPE   0.9 Note that this equation assumes a current limit at 120% of the maximum input current. Also, if VCLIM is greater than 450 mV, the saturation of the internal opamp will determine the limit on the input current rather than the CLIM pin. In such a case, the sense resistor RCS should be reduced until VCLIM reduces below 450 mV. Fault Protection The HV9911 has a built-in output overvoltage protection and output short-circuit protection. Both protection features are latched, which means that the power to the IC must be recycled to reset the IC. The IC also includes a FAULT pin which goes low during any Fault condition. At startup, a monoshot circuit (triggered by the POR circuit) resets an internal flip-flop which causes FAULT to go high and remains high during normal operation. This also allows the gate drive to function normally. This pin can be used to drive an external disconnect switch (Q2 in the Typical Application Circuit (Boost)) which will disconnect the load during a Fault condition. This disconnect switch is very important in a boost converter, as turning off the switching FET (Q1) during an Output Short-circuit condition will not remove the fault (Q1 is not in the path of the fault current). The disconnect switch will help to disconnect the shorted load from the input. 3.10 Overvoltage Protection Overvoltage protection is achieved by connecting the output voltage to the OVP pin through a resistive divider. The voltage at the OVP pin is constantly compared to the internal 1.25V. When the voltage at this pin exceeds 1.25V, the IC is turned off and FAULT goes low. 3.11 Output Short-circuit Protection The output short circuit condition is indicated by FAULT. As mentioned earlier, at startup, a monoshot circuit (triggered by the POR circuit) resets an internal flip-flop, which causes FAULT to go high and remains high during normal operation. This also makes the gate drive function normally. The steady state current is reflected in the reference voltage connected to the transconductance amplifier. The instantaneous output current is sensed from the FDBK terminal of the amplifier. The short circuit threshold current is internally set to 200% of the steady-state current. During Short-circuit condition, when the current exceeds the internally set threshold, the SR flip-flop is set and FAULT goes low. At the same time, the gate driver of the power FET is inhibited, providing a latching protection. The system can be reset by cycling the input voltage to the IC. Note: The short circuit FET should be connected before the current sense resistor as reversing RS and Q2 will affect the accuracy of the output current (due to the additional voltage drop across Q2 which will be sensed). It is recommended that no capacitor be connected between CLIM and GND. DS20005580A-page 12  2017 Microchip Technology Inc. HV9911 3.12 Synchronization The sync pin is an input/output (I/O) port to a fault tolerant peer-to-peer and/or master clock synchronization circuit. For synchronization, the sync pins of multiple HV9911-based converters can be connected together and may also be connected to the open drain output of a master clock. When connected in this manner, the oscillators will lock to the device with the highest operating frequency. When synchronizing multiple ICs, it is recommended that the same timing resistor corresponding to the switching frequency be used in all the HV9911 circuits. 3.14 Linear dimming can be achieved by varying the voltage at the IREF pin, as the output current is proportional to the voltage at the IREF pin. This can be done either by using a potentiometer from the IREF pin or applying an external voltage source to the IREF pin. Note: Due to the length of the connecting lines for the sync pins, a resistor between sync and GND may be required to damp any ringing due to parasitic capacitances on rare occasions. It is recommended that the resistor chosen be greater than 300 kΩ. When synchronized in this manner, a permanent High or Low condition on the sync pin will result in a loss of synchronization, but the HV9911-based converters will continue to operate at their individually set operating frequencies. Since loss of synchronization will not result in a total system failure, the sync pin is considered fault tolerant. Note: 3.13 The HV9911 is designed to sync up to four ICs at a time without the use of an external buffer. To sync more than four ICs, it is recommended that a buffered external clock be used. Internal 1 MHz Transconductance Amplifier The HV9911 includes a built-in 1 MHz transconductance amplifier with tri-state output, which can be used to close the feedback loop. The output current sense signal is connected to the FDBK pin and the current reference is connected to the IREF pin. The output of the opamp is controlled by the signal applied to the PWMD pin. When PWMD is high, the output of the opamp is connected to the COMP pin. When PWMD is low, the output is left open. This enables the integrating capacitor to hold the charge when the PWMD signal has turned off the gate drive. When the IC is enabled, the voltage on the integrating capacitor will force the converter into Steady state almost instantaneously. The output of the opamp is buffered and connected to the current sense comparator using a 15:1 divider. The buffer helps prevent the integrator capacitor from discharging during the PWM Dimming state.  2017 Microchip Technology Inc. Linear Dimming 3.15 Due to the offset voltage of the transconductance opamp, pulling the IREF pin very close to GND will cause the internal short circuit comparator to trigger and shut down the IC. This limits the linear dimming range of the IC. However, a 1:10 linear dimming range can be easily obtained. It is recommended that the PWMD pin be used to get zero output current rather than pull the IREF pin to GND. PWM Dimming PWM dimming can be achieved by driving the PWMD pin with a TTL-compatible source. The PWM signal is connected internally to three different nodes—the transconductance amplifier, the FAULT output and the gate output. When the PWMD signal is high, the gate and FAULT pins are enabled, and the transconductance opamp’s output is connected to the external compensation network. Thus, the internal amplifier controls the output current. When the PWMD signal goes low, the output of the transconductance amplifier is disconnected from the compensation network. Therefore the integrating capacitor maintains the voltage across it. The gate is disabled, so the converter stops switching and the FAULT pin goes low, turning off the disconnect switch. The output capacitor of the converter determines the converter’s PWM dimming response because the capacitor has to get charged and discharged whenever the PWMD signal goes high or low. In the case of a buck converter, since the inductor current is continuous, a very small capacitor is used across the LEDs. This minimizes the effect of the capacitor on the PWM dimming response of the converter. However, in the case of a boost converter, the output current is discontinuous, and a very large output capacitor is required to reduce the ripple in the LED current. Thus, this capacitor will have a significant impact on the PWM dimming response. By turning off the disconnect switch when PWMD goes low, the output capacitor is prevented from being discharged. This dramatically improves the boost converter’s PWM dimming response. DS20005580A-page 13 HV9911 Note: Note: 3.16 Disconnecting the capacitor might cause a sudden spike in the capacitor voltage as the energy in the inductor is dumped into the capacitor. This might trigger the OVP comparator if the OVP point is set too close to the maximum operating voltage. Thus, either the capacitor has to be sized slightly larger or the OVP set point has to be increased. Pulling the PWMD pin 0.3V below the GND may cause latch-up conditions on the HV911 IC. This abnormal condition can happen if there is a long cable between the PWM signal and the PWMD pin of the IC. It is recommended that a 1 kΩ resistor be connected between the PWMD pin and the PWM signal input to the HV9911. This resistor, when placed close to the IC, will damp out any ringing that might cause the voltage at the PWMD pin to go below GND. Avoiding False Shutdowns of the HV9911 The HV9911 has two fault modes which trigger a latched Protection mode—an Overcurrent (or Short-circuit) Protection and an Overvoltage Protection. To prevent false triggering due to the tripping of the overvoltage comparator resulting from noise in the GND traces on the PCB, it is recommended that a  1 nF–10 nF capacitor be connected between the OVP pin and GND. Although this capacitor slightly slows down the response of the Overvoltage Protection circuitry, it does not affect the overall performance of the converter as the large output capacitance in the boost design will limit the rate of output voltage increase. In some cases, the Overcurrent Protection may be triggered during PWM dimming, when the FAULT goes high and the disconnect switch is turned on. This triggering of the Overcurrent Protection is related to the parasitic capacitance of the LED string (shown as a lumped capacitance CLED in Figure 3-4). DS20005580A-page 14 VO CO CLED ROVP2 VD FAULT Q2 FDBK RS iSENSE FIGURE 3-4: Output of the Boost Converter Showing LED Parsed Capacitance. During normal PWM dimming operation, the HV9911 maintains the voltage across the output capacitor (CO) by turning off the disconnect switch and preserving the charge in the output capacitance when the PWM dimming signal is low. At the same time, the voltage at the drain of the disconnect FET is some non-zero value VD. When the PWM dimming signal goes high, FET Q2 is turned on. This causes the voltage at the drain of the FET (VD) to instantly become zero. Assuming a constant output voltage VO, isense can be computed as shown in Equation 3-9. EQUATION 3-9: i SENSE = C LED  d   VO – V D   dt = – C LED  dV D  dt In this case, the rate of fall of the disconnect FET’s drain voltage is a large value (since the FET turns on very quickly) and this causes a spike of current through the sense resistor, which could trigger the overcurrent protection (depending on the parasitic capacitance of the LED string). To prevent this condition, a simple RC low-pass filter network can be added as shown in Figure 3-5. Typical values are RF = 1 kΩ and CF = 470 pF. This filter will block the FDBK pin from seeing the turn-on spike and normalize the PWM dimming operation of the HV9911 boost converter. This will have a minimal effect on the stability of the loop but will increase the response time to an output short. If the increase in the response time is large, it might damage the output current sense resistor due to exceeding its peak-current rating.  2017 Microchip Technology Inc. HV9911 EQUATION 3-11: VO 2 P SC = I SAT  R S = 11W CO ROVP2 CLED For a 1.24Ω 1/4W resistor, the maximum power it can dissipate for a single 1 ms pulse of current is 11W. Since the total short-circuit time is about 350 ns, including the 300 ns time for turn-off, the resistor should be able to handle the current. VD FAULT Q2 FDBK Cf RS iSENSE FIGURE 3-5: Adding a Low-pass Filter to Prevent Pulse Triggering. The increase in the short-circuit response time can be computed using the various component values of the boost converter. Consider a boost converter with a nominal output current IO = 350 mA, an output sense resistor RS = 1.24Ω, LED string voltage VO = 100V and an output capacitor CO = 2 mF. The disconnect FET is a TN2510N8 which has a saturation current ISAT = 3A (at VGS = 6V). See “TN2510N8 N-Channel Enhancement-Mode Vertical DMOS FET.” The increase in the short-circuit response time due to the RC filter can then be computed as shown in Equation 3-10: EQUATION 3-10: IO t  R F  C F  In  1 – ---------------------- I SAT – I O 0.35A = 1k  470pF  In  1 – ---------------------------  3A – 0.35A  66ns This increase is found to be negligible (note that the equation is valid for ∆T