HV9982
Three-Channel, Closed-Loop, Switch Mode
LED Drive IC
Features
Description
• Switch mode controller for single-switch converters
• Closed loop control of output current
- Buck
- Boost
- SEPIC
• High PWM dimming ratio
• Internal 40V linear regulator
• Constant frequency operation
• Programmable slope compensation
• Linear and PWM dimming
• +0.2A/-0.4A gate drives for the switching FETs
• Output short circuit protection
• Output over voltage protection
• Hiccup-mode protection
• Analog control of PWM dimming
HV9982 is a three-channel, closed loop, peak-current
mode PWM controller designed to drive a constant output current. It can be used for driving either RGB LEDs
or multiple channels of white LEDs.
Applications
HV9982 includes a 40V linear regulator which provides
an 8.0V supply to power the IC. The switching frequencies of the three converters are controlled by an external clock signal. The channels operate at a switching
frequency of 1/12th of the external clock frequency and
are positioned 120° out-of-phase to reduce the input
current ripple. Each converter is driven by a peak current mode controller with output current feedback.
The three output currents can be individually dimmed
using either linear or PWM dimming. The IC also
includes three disconnect FET drivers, which enable
high PWM-dimming ratios and also help to disconnect
the input in case of an output short-circuit condition.
HV9982 includes a Hiccup-mode protection for both
open LED and short-circuit condition with automatic
recovery when the fault clears.
• RGB backlight applications
• Multiple string, white-LED driver applications
2014 Microchip Technology Inc.
DS20005295B-page 1
HV9982
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DS20005295B-page 2
2014 Microchip Technology Inc.
HV9982
31
40
VDD1
GATE3
GND3
VDD2
GND2
GATE2
FLT2
CS2
FDBK2
GND1
GATE1
Pin Diagram
30
1
VDD3
FLT1
FLT3
CS1
CS3
COMP3
COMP1
FDBK1
FDBK3
GND
REF1
REF3
OVP1
OVP3
VIN
CLK
VDD
NS
11
21
S2
S1
PWMD3
PWMD2
PWMD1
RAMP
SKIP
OVP2
REF2
20
COMP2
10
GND
EN
40-Lead QFN
Typical Application Circuit
VIN
GATE1
CS1
VDD
GND1
VDD1
OVP1
VDD2
FLT1
VDD3
FDBK1
PWMD1
PWMD2
GATE2
PWMD3
CS
REF1
REF2
HV9982
REF3
GND2
OVP2
FLT2
FDBK2
EN
CLK
GND
GATE3
COMP1
CS3
COMP2
GND3
OVP3
COMP3
FLT3
SKIP
S1
S2
2014 Microchip Technology Inc.
FDBK3
RAMP
DS20005295B-page 3
HV9982
1.0
ELECTRICAL
CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS †
VIN to GND ........................................................ -0.5V to +45V
VDD to GND, VDD 1-3 to GND ..........................--0.3V to +10V
All other pins to GND ......................... ....-0.3V to (VDD + 0.3V)
Operating temperature ..................................-40°C to +125°C
Storage temperature .....................................-65°C to +150°C
Continuous power dissipation (TA = +25°C).............5000 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions, above those indicated in the operational listings of this specification, is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.1
ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Symbol
ELECTRICAL CHARACTERISTICS (SHEET 1 OF 3)1
Parameter
Note
Min
Typ
Max
Units Conditions
Input
VINDC
Input DC supply voltage
1
10
-
40
V
IINSD
Shut-down mode supply
current
1
-
-
500
μA
Supply current
-
-
-
4.5
mA
EN ≥ 2.0V; PWMD1 = PWMD2
= PWMD3 = GND
Pull-down resistor
-
75
130
160
kΩ
VEN = 5.0V
IIN
REN
DC input voltage
EN ≤ 0.8V
Internal Regulator
VDD
Internally regulated voltage
1
7.25
7.75
8.25
V
UVLO
VDD under voltage lockout
threshold
-
6.0
-
6.5
V
-
-
500
-
mV
-
0.8
V
---
UVLOHYST VDD under voltage hysteresis
VIN= 12-40V; EN = HIGH;
PWMD1-3 = VDD; GATE1-3 =
1nF; CLK = 6MHz
VDD falling
VDD rising
PWM Dimming (PWMD1, PWMD2 and PWMD3)
VPWMD(lo)
PWMD input low voltage
1
-
VPWMD(hi)
PWMD input high voltage
1
2.0
-
-
V
---
RPWMD
PWMD pull down resistor
-
75
130
160
kΩ
VPWMD = 5.0V
0.2
-
-
A
0.4
-
-
A
Gate (GATE1, GATE2 and GATE3)
ISOURCE
Gate short circuit current,
sourcing
2
ISINK
Gate sinking current
2
TRISE
Gate output rise time
-
-
-
85
ns
CGATE = 1.0nF
TFALL
Gate output fall time
-
-
-
45
ns
CGATE = 1.0nF
Maximum duty cycle
2
-
91.7
-
%
---
DMAX
Note 1:
2:
VGATE = 0V
VGATE = VDD
Applies over the full operating ambient temperature range of 0°C < TA < +85°C.
For design guidance only.
DS20005295B-page 4
2014 Microchip Technology Inc.
HV9982
ELECTRICAL CHARACTERISTICS (CONTINUED) (SHEET 2 OF 3)1
TABLE 1-1:
Symbol
Parameter
Note
Min
Typ
Max
Units Conditions
Over-voltage Protection (OVP1, OVP2 and OVP3)
VOVP,rising
Over voltage rising trip point
1
4.5
5.0
5.5
V
OVP rising
VOVP,HYST
Over voltage hysteresis
-
-
0.5
-
V
OVP falling
Current Sense (CS1, CS2 and CS3)
TBLANK
Leading edge blanking
1
100
-
250
ns
---
TDELAY
Delay to output of gate
1
-
-
200
ns
100mV overdrive to the current
sense
Discharge resistance for
slope compensation
1
-
-
650
Ω
RDIS
Gate = Low
Internal Transconductance Opamp (Gm1, Gm2 and Gm3)
GB
Gain bandwidth product
2
-
1.0
-
MHz
AV
Open loop DC gain
-
65
-
-
dB
Output open
VCM
75pF capacitance at COMP pin
Input common-mode range
2
-0.3
-
3.0
V
---
VO
Output voltage range
2
0.7
-
VDD
V
---
Gm
Transconductance
-
500
600
700
μA/V
---
VOFFSET
Input offset voltage
-
-5.0
-
5.0
mV
---
Input bias current
2
-
0.5
1.0
nA
---
IBIAS
Oscillator (CLOCK)
fOSC1
Oscillator frequency
-
-
500
-
kHz
KSW
Oscillator divider ratio
2
-
12
-
-
Phi1
GATE1 - GATE2 phase
delay
2
-
120
-
°
Phi1
GATE1 - GATE3 phase
delay
2
-
240
-
°
TOFF
CLOCK low time
2
50
-
-
ns
TON
CLOCK high time
2
50
-
-
ns
---
VCLOCK,HI
CLOCK input high
1
2.0
-
-
V
---
1
-
-
0.8
V
---
TRISE,FAULT Fault output rise time
-
-
-
450
ns
330pF capacitor at FAULT pin
TFALL,FAULT Fault output fall time
-
-
-
200
ns
330pF capacitor at FAULT pin
VCLOCK,LO CLOCK input low
FCLOCK = 6.0MHz
---------
Disconnect Driver (FLT1, FLT2 and FLT3)
Short Circuit Protection (all three channels)
TBLANK,SC
Blanking time
1
400
-
700
ns
---
GSC
Gain for short circuit comparator
-
1.85
2.00
2.15
-
---
Vomin
Minimum current limit
threshold
2
0.15
-
0.25
V
REF = GND
TOFF
Propagation time for short
circuit detection
-
-
-
250
ns
FDBK = 2 • REF + 0.1V
-
-
10
-
μA
HICCUP timer
IHC,SOURCE Current source at SKIP pin used
for hiccup mode protection
Note 1:
2:
---
Applies over the full operating ambient temperature range of 0°C < TA < +85°C.
For design guidance only.
2014 Microchip Technology Inc.
DS20005295B-page 5
HV9982
TABLE 1-1:
Symbol
ELECTRICAL CHARACTERISTICS (CONTINUED) (SHEET 3 OF 3)1
Parameter
Note
Min
Typ
Max
Units Conditions
VTH(H)
High threshold at SKIP pin
2
-
5.0
-
V
---
VTH(L)
Low threshold at SKIP pin
2
-
0.1
-
V
---
CRAMP for Analog Control of PWM Dimming
FRAMP,min
Minimum frequency
-
-
110
-
Hz
CRAMP = 10nF
FRAMP,max
Maximum frequency
-
-
1250
-
Hz
CRAMP = 1.0nF
Note 1:
2:
Applies over the full operating ambient temperature range of 0°C < TA < +85°C.
For design guidance only.
1
TABLE 1-2:
THERMAL RESISTANCE
DS20005295B-page 6
Package
θja
40-Lead QFN
24°C/W
2014 Microchip Technology Inc.
HV9982
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN DESCRIPTION (SHEET 1 OF 2)
Pin #
Name
Description
1
VDD1
Power supply pin for channel 1. It can either be connected to the VDD pin or supplied
with an external power supply. It must be bypassed with a low ESR capacitor to GND1
(at least 0.1 μF). All VDD pins (VDD, VDD1-3) must be connected together externally.
An external supply (7.0-9.0V) can be connected to these pins to power the IC if the
internal regulator is not used.
2
FLT1
Used to drive an external disconnect switch. The disconnect switch is used to protect the
LEDs in case of fault conditions and also help to provide excellent PWM dimming
response by disconnecting and reconnecting the LEDs from the output capacitor during
PWM dimming.
3
CS1
Used to sense the source current of the external power FET used with channel 1. It
includes a built-in 100 ns (min) blanking timer. An R-C network at this pin programs the
slope compensation. Refer to the Slope Compensation section for additional information.
4
COMP1
Stable closed loop control for channel 1 can be accomplished by connecting a
compensation network between each COMP1 pin and GND1.
5
FDBK1
Output current feedback input for channel 1. It receives a voltage signal from an external
sense resistor.
6
REF1
The voltage at this pin sets the output current level for channel 1. Recommended voltage
range for this pin is 0-1.25V.
7
OVP1
Provides the over-voltage protection for the channel 1. When the voltage at this pin
exceeds 5.0V, the HV9982 is turned off and the fault timer starts. Upon completion of the
fault timer the IC attempts to restart.
8
VIN
Input of the internal 40V linear regulator.
9
VDD
Output of the linear regulator. It maintains a regulated 7.75V as long as the voltage of the
VIN pin is between 10 and 40V. It must be bypassed with a low ESR capacitor to GND
(at least 0.1 μF). Can be used as a power supply for the three channels.
10
EN
When pin is pulled below 0.8V, the IC goes into a standby mode and draws minimal
current.
11
GND
12
COMP2
Ground connection for the common circuitry in the HV9982.
13
REF2
The voltage at this pin sets the output current level for channel 2. Recommended voltage
range for this pin is 0-1.25V.
14
OVP2
Provides the over voltage protection for the channel 2. When the voltage at this pin
exceeds 5.0V, the HV9982 is turned off and the fault timer starts. Upon completion of the
fault timer the IC attempts to restart.
15
SKIP
Programs the hiccup timer for fault conditions. A capacitor to GND programs the hiccup
time.
16
RAMP
Provides a ramp signal which is used while dimming the channels with pulse-width modulation with an analog input. A capacitor to GND programs the PWM-dimming frequency.
17
PWMD1
18
PWMD2
19
PWMD3
PWM dimming of the three channels is accomplished by using the PWMD pins. If S1 is
LOW, then the three pins directly control the PWM dimming of the three channels and a
square wave input should be applied at these pins. If S1 is high, then a 0-2.0V analog
signal should be applied at these pins. The PWM dimming is then done by comparing
the analog voltage to the voltage at the RAMP pin.
20
S1
21
S2
Digital input pins which select the operating mode of the PWMD inputs. Refer to the
PWM dimming section for additional information.
22
NC
No connect.
Stable closed loop control for channel 2 can be accomplished by connecting a
compensation network between each COMP2 pin and GND2.
2014 Microchip Technology Inc.
DS20005295B-page 7
HV9982
TABLE 2-1:
PIN DESCRIPTION (CONTINUED) (SHEET 2 OF 2)
Pin #
Name
23
CLK
Clock input for the HV9982. The input to the CLK pin should be a TTL compatible square
wave signal. The three channels will switch at 1/12th the switching frequency of the
signal applied at the CLK pin.
24
OVP3
Provides the over voltage protection for the channel 3. When the voltage at this pin
exceeds 5.0V, the HV9982 is turned off and the fault timer starts. Upon completion of the
fault timer the IC attempts to restart.
25
REF3
The voltage at this pin sets the output current level for channel 3. Recommended voltage
range for this pin is 0-1.25V.
26
FDBK3
Output current feedback input for channel 3. It receives a voltage signal from an external
sense resistor.
27
COMP3
Stable closed loop control for channel 3 can be accomplished by connecting a
compensation network between each COMP3 pin and GND3.
28
CS3
Used to sense the source current of the external power FET used with channel 3. It
includes a built-in 100 ns (min) blanking timer. An R-C network at this pin programs the
slope compensation. Refer to the Slope Compensation section for additional information.
29
FLT3
Used to drive an external disconnect switch. The disconnect switch is used to protect the
LEDs in case of fault conditions and also help to provide excellent PWM-dimming
response by disconnecting and reconnecting the LEDs from the output capacitor during
PWM dimming.
30
VDD3
Power supply pin for channel 3. It can either be connected to the VDD pin or supplied
with an external power supply. It must be bypassed with a low ESR capacitor to GND3
(at least 0.1 μF). All VDD pins (VDD, VDD1-3) must be connected together externally.
An external supply (7.0-9.0V) can be connected to these pins to power the IC if the internal regulator is not used.
31
GATE3
Output gate drive for an external N-channel power MOSFET.
32
GND3
Ground return for channel 3. It is recommended that all the GNDs of the IC be connected
together in a STAR connection at the input GND terminal to ensure best performance.
33
VDD2
Power supply pin for channel 2. It can either be connected to the VDD pin or supplied
with an external power supply. It must be bypassed with a low ESR capacitor to GND2
(at least 0.1 μF). All VDD pins (VDD, VDD1-3) must be connected together externally.
An external supply (7.0-9.0V) can be connected to these pins to power the IC if the internal regulator is not used.
34
GND2
Ground return for channel 2. It is recommended that all the GNDs of the IC be connected
together in a STAR connection at the input GND terminal to ensure best performance.
35
GATE2
Output gate drive for an external N-channel power MOSFET.
36
FLT2
Used to drive an external disconnect switch. The disconnect switch is used to protect the
LEDs in case of fault conditions and also help to provide excellent PWM-dimming
response by disconnecting and reconnecting the LEDs from the output capacitor during
PWM dimming.
37
CS2
Used to sense the source current of the external power FET used with channel 2. It
includes a built-in 100 ns (min) blanking timer. An R-C network at this pin programs the
slope compensation. Refer to the Slope Compensation section for additional information.
38
FDBK2
Output current feedback input for channel 2. It receives a voltage signal from an external
sense resistor.
39
GND1
Ground return for channel 1. It is recommended that all the GNDs of the IC be connected
together in a STAR connection at the input GND terminal to ensure best performance.
40
GATE1
Output gate drive for an external N-channel power MOSFET.
DS20005295B-page 8
Description
2014 Microchip Technology Inc.
HV9982
3.0
FUNCTIONAL DESCRIPTION
3.1
Power Topology
HV9982 is a three-channel, switch-mode converter
LED driver designed to control a continuous conduction
mode buck, boost or SEPIC converter in a constant frequency mode. The IC includes an internal linear regulator, which operates from input voltages 10V to 40V.
The IC can also be powered directly using the VDD
pins and bypassing the internal linear regulator. The IC
includes features typically required in LED drivers such
as open LED protection, output short circuit protection,
linear and PWM dimming, programmable input current
limiting, and accurate control of the LED current. A high
current gate drive output enables the controller to be
used in high power converters. The IC is ideally suited
for backlight application using either RGB or multichannel white LED configurations.
3.2
Power Supply to the IC (VIN, VDD,
VDD1-3)
HV9982 can be powered directly from its VIN pin which
withstands a voltage up to 40V. When a voltage is
applied at the VIN pin, the HV9982 tries to maintain a
constant 7.75V (typ) at the VDD pin. The regulator also
has a built in under-voltage lockout, which shuts off the
IC if the voltage at the VDD pin falls below the UVLO
threshold. By connecting this VDD pin to pins VDD1-3
of the other three channels, the internal regulator can
be used to power all three channels in the IC.
If the internal regulator is not utilized, an external power
supply (7.0-9.0V) can be used to power the IC. In this
case, the power supply is directly connected to the
VDD1-3 pins and the VIN pin is left unconnected.
All four VDD pins must by bypassed by a low ESR
capacitor (≥0.1 µF) to provide a low impedance path for
the high frequency current of the output gate driver.
These capacitors must be referenced to the individual
grounds for proper noise rejection (see 3.13 “Layout
Considerations”). Also, in all cases, the four VDD pins
must be connected together externally.
The input current drawn from the external power supply
(or VIN pin) is a sum of the 4.5 mA (max) current drawn
by all the internal circuitry and the current drawn by the
gate drivers (which in turn depends on the switching
frequency and the gate charge of the external FET).
I IN =
4.5mA + Q g1 + Q g2 + Q g3 f s
In the above equation, fS is the switching frequency of
the converters and Qg1-3 are the gate charges of the
external FETs (which can be obtained from the FET
data sheets).
2014 Microchip Technology Inc.
The EN pin is a TTL-compatible input used to disable
the IC. Pulling the EN pin to GND will shut down the IC
and reduce the quiescent current drawn by the IC to be
less than 500 μA. If the enable function is not required,
the EN pin can be connected to VDD.
3.3
Clock Input (CLK)
The switching frequency of the converters is set by
using a TTL-compatible square wave input at the CLK
pin. The switching frequencies of the three converters
will be 1/12TH the frequency of the external clock.
3.4
Current Sense (CS1-3)
The current sense input is used to sense the source
current of the switching FET. Each CS input of the
HV9982 includes a built-in, 100 ns (minimum) blanking
time to prevent spurious turn off due to the initial current
spike when the FET turns on.
The IC includes an internal, resistor-divider network,
which steps down the voltage at the COMP pins by a
factor of 13. This voltage is used as the reference for
the current sense comparators. Since the maximum
voltage of the COMP pin is (VDD – 1.0V), this voltage
determines the maximum reference current for the current sense comparator, and thus the maximum inductor
current.
The current sense resistor, RCS, should be chosen so
that the input inductor current is kept below the saturation current level of the input inductor. For discontinuous conduction mode of operation, no slope
compensation is necessary. In this case, the current
sense resistor is chosen as:
V DD – 1.0V
R CS = ---------------------------13 I IN pk
where IIN,pk is the maximum desired peak input current.
For continuous conduction mode converters operating
in the constant frequency mode, slope compensation
becomes necessary to ensure stability of the peak current mode controller, if the operating duty cycle is
greater than 0.5. This factor must also be accounted for
when determining RCS (see 3.5 “Slope Compensation”).
3.5
Slope Compensation
Choosing a slope compensation, which is one half of
the down slope of the inductor current, ensures that the
converter will be stable for all duty cycles.
Slope compensation in the HV9982 can be programmed by two external components, see Figure 3-1.
A resistor for VDD sets a current, which is almost constant since the VDD voltage is much larger than the voltage at the CS pin. This current flows into the capacitor
and produces a ramp voltage across the capacitor. The
voltage at the CS pin is then the sum of the voltage
DS20005295B-page 9
HV9982
across the capacitor and the voltage across the current
sense resistor. The voltage across the capacitor provides the required slope compensation. When the
GATE turns off, an internal pull down FET discharges
the capacitor. The 650Ω resistance of the internal FET
will prevent the voltage at the CS pin from going all the
way to zero.
FIGURE 3-1:
SLOPE COMPENSATION
VDD
+
CS
3.7
RSC
CSC
GATE
RCS
The minimum value of the voltage will instead be:
V DD
V CS MIN = --------- 650
R SC
The slope compensation capacitor is chosen so that it
can be completely discharged by the internal 650Ω
FET at the CS pin during the time the FET is off.
Assuming the worst case switch duty cycle of 92%,
0.08
C SC = ---------------------------------3 650 f S
Assuming a down slope of DS (A/ms) for the inductor
current, the current sense resistor and the slope compensation resistor can be computed as:
V DD – 1
1
R CS = ------------------ -----------------------------------------------------------------6
13
DS 10 0.92
---------------------------------------- + I IN pk
2 fS
2 V DD
R SC = ------------------------------------------------------6
DS 10 C SC R CS
3.6
Control of the LED Current
The LED currents in the HV9982 are controlled in a
closed-loop manner. The current references which set
the three LED currents are provided at the REF pins
(REF1-3). This reference voltage is compared to the
voltage at the FDBK1-3 pins which sense the LED currents in the three channels using current sense resistors. HV9982 includes three 1 MHz transconductance
amplifiers with tri-state output, which are used to close
the feedback loops and provide accurate current control. The compensation networks are connected at the
COMP pins (COMP1-3).
The output of the op-amps are buffered and connected to
the current sense comparators using a 12R:1R resistor
divider.
DS20005295B-page 10
The outputs of the op-amps are controlled by the signal
applied to the PWMD pins (PWMD1-3). When PWMD
is high, the output of the op-amp is connected to the
COMP pin. When PWMD is low, the output is left open.
This enables the integrating capacitor to hold the
charge when the PWMD signal has turned off the gate
drive. When the IC is enabled, the voltage on the integrating capacitor will force the converter into steady
state almost instantaneously.
Linear Dimming
Linear Dimming can be accomplished in the HV9982
by varying the voltages at the REF pins. Note that since
the HV9982 is a peak current mode controller, it has a
minimum on-time for the GATE outputs. This minimum
on-time will prevent the converters from completely
turning off even when the REF pins are pulled to GND.
Thus, linear dimming cannot accomplish true zero LED
current. To get zero LED current, PWM dimming has to
be used. Different signals can be connected to the
three REF pins if desired and they need not be connected together.
Due to the offset voltage of the short circuit comparator
as well as the non-linearity of the X2 gain stage, pulling
the REF pin very close to GND would cause the internal short circuit comparator to trigger and shut down
the IC. To overcome this, the output of the gain stage is
limited to 125 mV (minimum), allowing the REF pin to
be pulled all the way to 0V without triggering the short
circuit comparator.
3.8
PWM Dimming
PWM dimming in the HV9982 can be accomplished in
one of two ways: true PWM dimming using TTL-compatible square wave sources at the PWMD pins
(PWMD1-3), or an analog control of PWM dimming by
applying a 0-2.0V linear signal to the PWMD pins. The
analog control of PWM dimming helps the HV9982 to
be backward compatible with CCFL controllers. All
three channels can be individually PWM dimmed as
desired.
The mode of PWM dimming is set using control pins S1
and S2. The truth table for S1 and S2 control is given in
Table 3-1. It is recommended that the pins be connected to either VDD or GND and not left unconnected.
TABLE 3-1:
S1 AND S2 CONTROL
S1
S2
0
0
PWMD Output
0
1
1
0
Input DC zero volt corresponds to 100%
duty cycle output
1
1
Input DC two volt corresponds to 100%
duty cycle output
The output will follow PWMD input signal
2014 Microchip Technology Inc.
HV9982
When S1 is high and the HV9982 is operating in the
analog control of PWM dimming mode, the PWM dimming frequency is set by a capacitor connected at the
RAMP pin. The RAMP frequency range is 100Hz1.0kHz and the capacitor can be selected as:
1.0s
f H Z = ----------------C RAMP
Note:
In the following description of the PWMdimming performance the PWMD signals
refer to the internal PWM dimming signal
and not to the signal applied at the PWMD
pins
When the PWM signal is high, the GATE and FLT pins
are enabled and the output of the transconductance
op-amp is connected to the external compensation network. Thus, the internal amplifier controls the output
current. When the PWMD signal goes low, the output of
the transconductance amplifier is disconnected from
the compensation network. Thus, the integrating
capacitor maintains the voltage across it. The GATE is
disabled, so the converter stops switching and the FLT
pin goes low, turning off the disconnect switch.
The output capacitor of the converter determines the
PWM-dimming response of the converter, because it is
charged and discharged whenever the PWMD signal
goes high or low. In the case of a buck converter, since
the inductor current is continuous, a very small capacitor is used across the LEDs. This minimizes the effect
of the capacitor on the PWM-dimming response of the
converter. However, in the case of a boost converter,
the output current is discontinuous and a very large
output capacitor is required to reduce the ripple in the
LED current. Thus, this capacitor will have a significant
impact on the PWM-dimming response. By turning off
the disconnect switch when PWMD goes low, the output capacitor is prevented from being discharged and
thus the PWM-dimming response of the boost converter Improves dramatically.
Disconnecting the LED load during PWM dimming
causes the energy stored in the inductor to be dumped
into the output capacitor. The filter capacitor should be
chosen large enough so that it can absorb the inductor
energy without significant change to the voltage across it.
3.9
Fault Conditions
The HV9982 is a robust controller which can protect the
LEDs and the LED driver in case of fault conditions.
The HV9982 includes both open LED protection and
output short circuit protection. In both cases, the
HV9982 shuts down and attempts a restart. The hiccup
time can be programmed by a single external capacitor
at the SKIP pin.
During start-up, or when a fault condition is detected,
both GATE and FLT outputs are disabled, the COMP
pins and SKIP pins are pulled to GND. Once the volt-
2014 Microchip Technology Inc.
age at the SKIP pin falls below 0.1V and the fault condition(s) have disappeared, the capacitor at the SKIP
pin is released and is charged slowly by a 10μA current
source. When the capacitor is charged to 5.0V, the
COMP pins are released and GATE and FLT pins are
allowed to turn on. If the hiccup time is long enough, it
will ensure that the compensation networks are all
completely discharged and that the converters start at
minimum duty cycle.
The hiccup timing capacitor can be programmed as:
10A t HICCUP
C RAMP = -------------------------------------4.9V
3.10
Short Circuit Protection
When a short circuit condition is detected (output current becomes higher than twice the steady state current), the GATE and FLT outputs are pulled low. As
soon as the disconnect FET is turned off, the output
current goes to zero and the short circuit condition disappears. At this time, the hiccup timer is started (Fig.
3). Once the timing is complete, the converter attempts
to restart. If the fault condition still persists, the converter shuts down and goes through the cycle again. If
the fault condition is cleared, due to a momentary output short, the converter will start regulating the output
current normally. This allows the LED driver to recover
from accidental shorts without having to reset the IC.
During short circuit conditions, there are two conditions
that determine the hiccup time.
The first condition is the time required to discharge the
compensation capacitors. Assuming a pole-zero R-C
network at the COMP pin (series combination of RZ
and CZ in parallel with CC),
t COMP n = 3 R Zn C Zn
where n refers to the channel number.
If the compensation networks are only type 1 (single
capacitor), then:
t COMP n = 3 650 C Zn
Thus, the maximum compensation time required can
be computed as:
tCOMP max = max t COMP1 ,t COMP2 ,t COMP3
The second condition is the time required for the inductors to completely discharge following a short circuit.
This time can be computed as:
t IND N = --- L N C ON
4
DS20005295B-page 11
HV9982
where L and CO are the input inductor and output
capacitor of each power stage.
Thus, the maximum time required to discharge the
inductors can be computed as:
t IND MAX = max t IND1 ,t IND2 ,t IND3
The hiccup time is then chosen as:
t HICCUP max t COMP MAX ,tIND MAX
3.11
False Triggering of the Short
Circuit Comparator During PWM
Dimming
During PWM dimming, the parasitic capacitance of the
LED string causes a spike in the output current when
the disconnect FET is turned on. If this spike is
detected by the short circuit comparator, it will cause
the IC to falsely detect an over current condition and
shut down.
In the HV9982, to prevent these false triggers, there is
a built in 500 ns blanking network for the short circuit
comparator. This blanking network activates when the
PWMD input goes high. Thus, the short circuit comparator will not see the spike in the LED current during the
PWM Dimming turn-on transition. Once the blanking
timer is completed, the short circuit comparator will
start monitoring the output current. Thus, the total delay
time for detecting a short circuit will depend on the condition of the PWMD input.
If the output short circuit exists before the PWM-dimming signal goes high, the total detection time will be:
t DETECT1 = tBLANK + t DELAY 950ns max
If the short circuit occurs when the PWM dimming signal is already high, the time to detect will be:
t DETECT1 = tDELAY 250ns max
3.12
Over-voltage Protection
The HV9982 provides hysteretic over voltage protection allowing the IC to recover in case the LED load is
momentarily disconnected.
When the load is disconnected in a boost converter, the
output voltage rises as the output capacitor starts
charging. When the output voltage reaches the OVP rising threshold, the HV9982 detects an over voltage condition and turns off the converter. The converter is turned
back on only when the output voltage falls below the falling OVP threshold (which is 10% lower than the rising
threshold). This time is mostly dictated by the R-C time
constant of the output capacitor CO and the resistor network used to sense over voltage (ROVP1+ ROVP2). In
DS20005295B-page 12
case of a persistent open circuit condition, this cycle
keeps repeating maintaining the output voltage within a
10% band.
In most designs, the lower threshold voltage of the over
voltage protection (VOVP – 10%) at which point the
HV9982 attempts to restart will be more than the LED
string voltage. Thus, when the LED load is reconnected
to the output of the converter, the voltage differential
between the actual output voltage and the LED string
voltage will cause a spike in the output current. This
causes a short circuit to be detected and the HV9982
will trigger short circuit protection. This behavior continues till the output voltage becomes lower than the LED
string voltage at which point, no fault will be detected
and normal operation of the circuit will commence.
3.13
Layout Considerations
For multi-channel peak current mode controller IC to
work properly with minimum interference between the
channels, it is important to have a good PCB layout
which minimizes noise. Following the layout rules
stated below will help to ensure proper performance of
all three channels.
1.
GND connection
The IC has four separate ground connections – one for
each of the three channels and one analog ground for
the common circuitry. It is recommended that four separate ground planes be used in the PCB and all the
GND planes be connected together at the return terminal of the input power lines.
2.
VDD Connection
Each VDD pin should be by passed with a low ESR
capacitor to its OWN ground (i.e. VDD1 is bypassed to
GND1 and so on). The common VDD pin can be
bypassed to the common GND.
3.
REF Connection
If all the references are going to be driven from a single
voltage source, it is recommended to have a small R-C
low pass filter (1.0k, 1.0 nF) at each REF pin with the
filter being referenced to the appropriate channel’s
ground (as in the case of the VDD pins). If the REF pins
are driven with three individual voltage sources, then
just a small capacitor (1.0 nF) at each pin would suffice.
4.
GATE and CS connection
The connection from GATE output to the gate of the
external FET as well as the connection from the CS pin
to the external sense resistor made as short as possible to avoid false triggering.
5.
OVP protection
Typically, the OVP resistor dividers would be located
away from the IC. To prevent false triggering of the IC
due to noise at the OVP pin, a small bypass capacitor
(1.0nF) right at the OVP pin is recommended.
2014 Microchip Technology Inc.
HV9982
FIGURE 3-2:
LAYOUT GUIDELINES
VDD
Connection
Input
Return
Terminal
GND1
Star
Connection
of GND
GND2 VDD2
VDD1
VDD3
HV9982
Reference
GND3
REF1
REF3
VDD
GND
REF2
REF
Connection
GND Tab
Connection
2014 Microchip Technology Inc.
DS20005295B-page 13
HV9982
FIGURE 3-3:
INTERNAL BLOCK DIAGRAM
VIN
REF
Bandgap
CLK
VDD
EN
Linear
Regulator
UVLO
CLKA
CLKB
CLKC
1/12
POR
Shared circuitry
PWMDA
CLKA
RAMP
RAMP
Generator
RAMP
RAMP
S
Q
R
Q
GATE1
FC
+
S1 S2
Blanking
CLKA
+
RAMP
+
-
PWMDA
PWMDA
+
-
PWMD1
PWMDA
FC
FLT1
OVP1
+
-
REF
CS1
SCDA
OVDA
+
2
REF1
FDBK1
Blanking
FDA
PWMDA
COMP1
DIS
Replicated for each channel
S1
S1
S2
S2
POR
FDA
FDB
FDC
S
0.1V
5V
SKIP
+
+
-
Q
Fault
R
DIS
Fault
FC
DS20005295B-page 14
Shared circuitry
HV9982
2014 Microchip Technology Inc.
HV9982
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
40-Lead QFN
Example
XXXXXXX
XXXXXXXX
XXXXXX e3
YYWWNNN
HV9982 e3
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2014 Microchip Technology Inc.
DS20005295B-page 15
HV9982
40 Lead QFN
D
40
D2
40
1
1
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
E
E2
b
View B
Top View
Bottom View
Note 3
θ
A
L
A3
Seating
Plane
L1
Note 2
A1
Side View
View B
Notes:
1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/
identifier; an embedded metal marker; or a printed indicator.
2: Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3: The inner tip of the lead may be either rounded or square.
4: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Symbol
Dimension
(mm)
A
A1
MIN
0.80
0.00
NOM
0.90
0.02
MAX
1.00
0.05
A3
0.20
REF
b
D
D2
E
E2
0.18
5.85*
1.05
5.85*
1.05
0.25
6.00
-
6.00
-
0.30
6.15*
4.45
6.15*
4.45
e
L
L1
θ°
0.50
BSC
0.30†
0.00
0
0.40†
-
-
0.50†
0.15
14
JEDEC Registration MO-220, Variation VJJD-6, Issue K, June 2006.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
DS20005295B-page 16
2014 Microchip Technology Inc.
HV9982
APPENDIX A:
REVISION HISTORY
Revision A (May 2014)
• Original Release of this Document.
Revision B (September 2014)
• Updated template to the Microchip template
• Updated the package marking information
2014 Microchip Technology Inc.
DS20005295B-page 17
HV9982
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
DS20005295B-page 18
2014 Microchip Technology Inc.
HV9982
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
-
XX
X
-
Package Environmental
Options
X
Reel
Device:
HV9982 = Three-Channel, Closed-Loop, Switch Mode
LED Drive IC
Package:
K6
= 40-lead (6x6) QFN
Environmental
G
= Lead (Pb)-free/ROHS-compliant package
Reel:
Examples:
a)
HV9982K6-G:
40-lead QFN package,
490/Tray.
b)
HV9982K6-G-M935:
40-lead QFN package,
2000/Reel.
(nothing) = Tray
M935
= Reel
2014 Microchip Technology Inc.
DS20005295B-page 19
HV9982
DS20005295B-page 20
2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-578-9
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005295B-page 21
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2943-5100
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Tel: 43-7242-2244-39
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Tel: 45-4450-2828
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Tel: 678-957-9614
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Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS20005295B-page 22
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
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Tel: 86-28-8665-5511
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Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
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Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
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Tel: 86-25-8473-2460
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China - Qingdao
Tel: 86-532-8502-7355
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Tel: 86-21-5407-5533
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Tel: 86-29-8833-7252
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Tel: 81-6-6152-7160
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Japan - Tokyo
Tel: 81-3-6880- 3770
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Tel: 82-53-744-4301
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Tel: 33-1-69-53-63-20
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Tel: 49-2129-3766400
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Tel: 49-7231-424750
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Tel: 39-0331-742611
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Tel: 39-049-7625286
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Tel: 60-3-6201-9857
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Netherlands - Drunen
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03/25/14
2014 Microchip Technology Inc.