HV9985K6-G

HV9985 3-Channel Closed-Loop Switch-Mode LED Driver IC Features General Description • Switch Mode Controller for Single-Switch Converters • Gate Drivers Optimized for Driving Logic Level FETs - 0.25A Sourcing - 0.5A Sinking • Typical ±2% Absolute and String-to-String Current Accuracy (with ±1% Sense Resistors) • High Pulse-Width Modulation (PWM) Dimming Ratio up to 5000:1 • 10V to 40V Input Range • Constant Frequency Operation up to 1 MHz • On-Chip Clock or External Clock Option • Programmable Slope Compensation • Linear and PWM Dimming • Output LED Short-Circuit Protection • Output Overvoltage Protection • Hiccup Mode Protection The HV9985 is a 3-channel Peak Current mode PWM controller for driving single-switch converters in a constant output Current mode. It can be used for driving either RGB LEDs or multiple channels of white LEDs. The HV9985 features a 40V linear regulator, which provides a 5V supply to power the IC. The switching frequencies of the three converters in the IC are controlled either with an external clock signal (the channels operate at a switching frequency of 1/12th of the external clock frequency) or using the internal oscillator. The three channels are positioned 120° out-of-phase to reduce the input current ripple. Each converter is driven by a Peak Current mode controller with output current feedback. The three output currents can be individually dimmed using either linear or PWM dimming. The IC also includes three disconnect FET drivers, which enable high PWM dimming ratios and disconnect the LED load in case of an output LED Short-circuit condition. The HV9985 includes Hiccup mode protection for both open LED and Short-circuit condition to prevent the IC from shutting down in cases of intermittent Fault conditions. Applications • RGB Backlight Applications • Boost, Buck, and SEPIC Topologies • Multiple String White LED Driver Applications Package Type VDD1 1 GATE3 GND3 VDD2 GND2 FLT2 GATE2 FDBK2 CS2 GND1 GATE1 40-lead QFN (Top view) 40 VDD3 FLT1 FLT3 CS1 CS3 COMP3 COMP1 FDBK1 FDBK3 GND REF1 REF3 OVP1 OVP3 VIN CLK VDD RT EP NC PWMD3 PWMD1 PWMD2 NC SKIP OVP2 REF2 GND NC COMP2 EN Refer to Table 2-1 for pin information.  2019 Microchip Technology Inc. DS20005558B-page 1 HV9985 Typical Application D1b (Optional) CIN Q1a L1 CIN1 D1a CSC1 CVDD1 CVDD VDD VDD1 RCS1 GATE1 CS1 GND1 OVP1 HV9985 (One Channel Shown) RT RT PWMD1 CLK SKIP CSKIP DS20005558B-page 2 ROVP1b Q1b FLT1 GND CO1 RSC1 VIN EN ROVP1a FDBK1 COMP1 CC1 REF1 CREF1 RREF1 RS1 REF  2019 Microchip Technology Inc. HV9985 Functional Block Diagram VIN POR FDA FDB FDC S Q 0.1V + Fault EN VDD GND Linear Regulator UVLO POR R - 5μA 1.6V + - SKIP DIS CLK A CLK B CLK C Fault θ=0 θ = 120 θ = 240 CLK FC RT Common Circuitry Circuitry for a single channel PWMDA CLKA VDD1 S R GATE1 FC Q 1 + - PWMDA PWMD1 Q 100kΩ CS1 BLANKING CLKA GND1 1 PWMDA FC FLT1 R 1 + + OVP1 REF - FDA 0.2V 8R PWMDA REF1 + - FDBK1 2 BLANKING PWMDA COMP1 DIS 1  2019 Microchip Technology Inc. DS20005558B-page 3 HV9985 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VIN to GND ................................................................................................................................................–0.3V to +45V VDD to GND, VDD1-3 to GND .......................................................................................................................–0.3V to +6V All other pins to GND .....................................................................................................................–0.3V to (VDD +0.3V) Junction Temperature, TJ ..................................................................................................................... –40°C to +150°C Storage Ambient Temperature, TS ....................................................................................................... –65°C to +150°C Continuous Power Dissipation (TA= +25°C) .................................................................................................... 4000 mW † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise noted, specifications are at TA = 25°C. VIN = 24V, VDD1 = VDD2 = VDD3 = VDD unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit INPUT Input DC Supply Voltage Shutdown Mode Supply Current Supply Current VINDC IINSD IIN 10 — — — — — 40 200 1.5 V µA mA DC input voltage (Note 1) VEN ≤ 0.8V (Note 1) VEN ≥ 2V, PWMD1 = PWMD2 = PWMD3 = GND VDD 4.75 5 5.25 V VIN = 10V to 40V, EN = HIGH, PWMD1-3 = VDD; GATE1-3 = 2 nF; CLK = 6 MHz (Note 1) VDD rising INTERNAL REGULATOR Internally Regulated Voltage Conditions VDD Undervoltage Lockout UVLORISE 4.25 — 4.75 V Threshold UVLOHYST — 250 — mV VDD falling VDD Undervoltage Lockout Hysteresis ENABLE INPUT EN Input Low Voltage VEN(LO) — — 0.8 V Note 1 EN Input High Voltage VEN(HI) 2 — — V Note 1 EN Pull-Down Resistor REN 50 100 150 kΩ VEN = 5V PWM DIMMING (PWMD1, PWMD2, AND PWMD3) PWMD Input Low Voltage VPWMD(LO) — — 0.8 V Note 1 PWMD Input High Voltage VPWMD(HI) 2 — — V Note 1 PWMD Pull-Down Resistor RPWMD 50 100 150 kΩ VPWMD = 5V GATE (GATE1, GATE2, AND GATE3) VGATE = 0V (Note 2) GATE Short-Circuit Current, ISOURCE 0.25 — — A Sourcing VGATE = VDD (Note 2) GATE Sinking Current ISINK 0.5 — — A GATE Output Rise Time TRISE — — 85 ns CGATE = 2 nF (Note 1) GATE Output Fall Time TFALL — — 45 ns CGATE = 2 nF (Note 1) Maximum Duty Cycle DMAX — 91.7 — % Note 2 Note 1: Specifications apply over the full operating ambient temperature range of –40°C < TA < +85ºC. Limits are obtained by design and characterization. 2: For design guidance only DS20005558B-page 4  2019 Microchip Technology Inc. HV9985 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, specifications are at TA = 25°C. VIN = 24V, VDD1 = VDD2 = VDD3 = VDD unless otherwise indicated. Parameter Sym. Min. Typ. OVERVOLTAGE PROTECTION (OVP1, OVP2, AND OVP3) Overvoltage Rising Trip Point VOVP,RISING 1.13 1.25 Overvoltage Hysteresis VOVP,HYST — 125 CURRENT SENSE (CS1, CS2, and CS3) Leading Edge Blanking TBLANK 100 — Delay to Output of GATE TDELAY — — Max. Unit Conditions 1.37 — V mV OVP rising (Note 1) OVP falling 250 200 ns ns Note 1 100 mV overdrive to the current sense comparator GATE = Low (Note 1) Discharge Resistance for Slope RDIS — — 100 Ω Compensation INTERNAL TRANSCONDUCTANCE OP-AMP (OTA1, OTA2, AND OTA3) Gain Bandwidth Product GBW — 1 — MHz 75 pF capacitance at COMP pin (Note 2) Open-Loop DC Gain AV 65 — — dB Output open Input Common-Mode Range VCM –0.3 — 3 V Note 2 Output Voltage Range VO — — VDD — Note 2 Transconductance gm 500 625 750 µA/V Input Offset Voltage VOFFSET –5 — 5 mV Input Bias Current IBIAS — 0.5 1 nA Note 2 Resistor Divider Ratio — 0.11 — — Note 2 RRATIO (∆VCS/∆VCOMP) EXTERNAL CLOCK INPUT Oscillator Frequency fOSC1 — 500 — kHz FCLOCK = 6 MHz Oscillator Divider Ratio KSW — 12 — — Note 2 GATE1–GATE2 Phase Delay — 120 — ° Note 2 PHI1 GATE1–GATE3 Phase Delay — 240 — ° Note 2 Minimum CLOCK Low Time TOFF,MIN 50 — — ns Note 2 Minimum CLOCK High Time TON,MIN 50 — — ns Note 2 CLOCK Input High VCLOCK,HI 2 — — V Note 1 CLOCK Input Low VCLOCK,LO — — 0.8 V Note 1 OSCILLATOR 110 125 140 kHz RT = 400 kΩ FOSC1 Switching Frequency (Common for all Channels) FOSC2 440 500 560 kHz RT = 100 kΩ Switching Frequency Range FOSC — — 1000 kHz Note 2 DISCONNECT DRIVER (FLT1, FLT2, AND FLT3) Fault Output Rise Time TRISE,FAULT — — 300 ns 500 pF capacitor at FLT pin (Note 1) Fault Output Fall Time TFALL,FAULT — — 200 ns 500 pF capacitor at FLT pin (Note 1) SHORT-CIRCUIT PROTECTION (ALL THREE CHANNELS) PWMD changes from low to high. 400 — 700 ns Blanking Time TBLANK,SC (Note 1) Gain for Short-Circuit GSC 1.85 2 2.15 — Comparator Minimum Current Limit 0.15 — 0.25 V REF = GND VCL(MIN) Threshold Note 1: Specifications apply over the full operating ambient temperature range of –40°C < TA < +85ºC. Limits are obtained by design and characterization. 2: For design guidance only  2019 Microchip Technology Inc. DS20005558B-page 5 HV9985 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, specifications are at TA = 25°C. VIN = 24V, VDD1 = VDD2 = VDD3 = VDD unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Conditions Propagation Time for TOFF — — 250 ns VFDBK = 2 • VREF + 0.1V (Note 1) Short-Circuit Detection SKIP TIMER — 5 — µA Current Source at SKIP Pin IHC,SOURCE used for Hiccup Mode Protection — 1.5 — V Note 2 Voltage Swing at SKIP Pin ΔVSKIP Note 1: Specifications apply over the full operating ambient temperature range of –40°C < TA < +85ºC. Limits are obtained by design and characterization. 2: For design guidance only TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit TA –40 — +85 °C Operating Junction Temperature TJ –40 — +125 °C Maximum Junction Temperature TJ(ABSMAX) — — +150 °C TS –65 — +150 °C JA — 24 — °C/W Conditions TEMPERATURE RANGES Operating Ambient Temperature Storage Ambient Temperature PACKAGE THERMAL RESISTANCES 40-lead QFN Note 1: Note 1 JA for QFN package is based on a four-layer PCB as per JESD51-9. DS20005558B-page 6  2019 Microchip Technology Inc. HV9985 2.0 PIN DESCRIPTION The details on the pins of HV9985 40-lead QFN are listed in Table 2-1. Refer to Package Type for the location of pins. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name Description 1 VDD1 33 VDD2 30 VDD3 These pins are the power supply pins of the three channels. They can either be connected to the VDD pin or powered by an external power supply. They must be bypassed with a low-ESR capacitor to their respective GNDs (at least 0.1 μF). All VDD pins (VDD, VDD1-3) must be connected together externally when the internal 5V linear regulator is used. An external 5V supply can be connected to these pins to power the IC if the internal regulator is not used. 2 FLT1 36 FLT2 29 FLT3 3 CS1 37 CS2 28 CS3 4 COMP1 12 COMP2 27 COMP3 5 FDBK1 38 FDBK2 26 FDBK3 6 REF1 13 REF2 These pins are used to drive external logic-level disconnect switches. The disconnect switches are used to protect the LEDs in case of Fault conditions and serve to provide excellent PWM dimming response by disconnecting and reconnecting the LEDs from the output capacitor during PWM dimming. These pins are used to sense the source current of the external power FETs. They include a built-in 100 ns (minimum) blanking timer. Connecting an RC-network to these pins programs the slope compensation. Refer to Section 3.5 “Slope Compensation” for additional information. Stable closed-loop control can be accomplished by connecting a compensation network between each COMP pin and its respective GND. These pins are the output current feedback inputs for each channel. They receive voltage signal from external sense resistors. The voltage at these pins sets the output current level for each channel. The recommended voltage range for these pins is 0V to 1.25V. 25 REF3 7 OVP1 14 OVP2 24 OVP3 8 VIN This is the input of the internal 40V maximum input linear regulator with 5V regulated output. 9 VDD This pin is the output of the linear regulator. It maintains a regulated 5V as long as the voltage of the VIN pin is between 10V and 40V. It must be bypassed with a low-ESR capacitor to GND (at least 0.1 µF). This pin can be used as a power supply for the three channels. 10 EN When the pin is pulled below 0.8V, the IC goes into a Standby mode and draws minimal current. 11 GND Ground connection for the common circuitry in the HV9985 15 SKIP This pin programs the hiccup timer for Fault conditions. A capacitor to GND programs the hiccup time. 16 NC 17 PWMD1 18 PWMD2 19 PWMD3 20 21 NC These pins provide the overvoltage protection for the three channels. When the voltage at any of these pins exceeds 1.25V, the HV9985 is turned off. The fault timer starts when the voltage drops below 1.125V. Upon completion of the fault timer, the IC attempts to restart. No connect PWM dimming of the three channels is accomplished by using the PWMD pins. The three pins directly control the PWM dimming of the three channels, and a square wave input should be applied to these pins. No connect  2019 Microchip Technology Inc. DS20005558B-page 7 HV9985 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number Pin Name Description 22 RT A resistor at this pin programs the on-board oscillator. If an external clock is being used, this pin should be either left open or connected to GND. 23 CLK This pin is the clock input for the HV9985. The input to the CLK pin should be a TTL-compatible square wave signal. The three channels will switch at 1/12th the frequency of the signal applied at the CLK pin. This pin is used if multiple HV9985s are being used in a system. If the on-chip oscillator is being used, this pin should be connected to GND. 40 GATE1 35 GATE2 31 GATE3 39 GND1 34 GND2 32 GND3 EP GND DS20005558B-page 8 These pins are the gate drivers which drive the external logic-level N-channel boost converter MOSFETs. Ground return for each of the channels. It is recommended that all the GNDs of the IC be connected together in a STAR connection at the input GND terminal to ensure best performance. Exposed backside pad. It must be connected to pin 11 and GND plane on PCB to maximize the thermal performance of the package.  2019 Microchip Technology Inc. HV9985 3.0 FUNCTIONAL DESCRIPTION 3.1 Power Topology The HV9985 is a 3-channel Switch-mode converter LED driver designed to control a boost, a buck, or a SEPIC converter in a constant frequency, Peak Current-controlled mode. The IC includes an internal linear regulator, which operates from input voltage 10V to 40V and provides a 5V supply to power the IC. The IC can also be powered directly with the VDD pins and bypassing the internal linear regulator. The IC includes features typically required in LED drivers like open LED protection, output LED string short-circuit protection, linear and PWM dimming, and accurate control of the LED current. The IC is ideally suited for backlight application using either RGB or multi-channel white LED configurations. 3.2 Power Supply to the IC (VIN, VDD, and VDD1–3) The device can be powered directly from its VIN pin that takes a voltage up to 40V. When a voltage is applied to the VIN pin, the HV9985 tries to maintain a constant 5V (typical) at the VDD pin. The regulator also has a built-in under-voltage lockout which shuts off the IC if the voltage at the VDD pin falls below the UVLO threshold. By connecting this VDD pin to the individual VDD pins of the three channels, the internal regulator can be used to power all three channels in the IC. If the internal regulator is not utilized, an external power supply (5V +/– 10%) can be used to power the IC. In this case, the power supply is directly connected to the VDD pins and the VIN pin. All four VDD pins must be bypassed by a low-ESR capacitor (≥0.1 μF) to provide a low impedance path for the high frequency current of the output gate driver. These capacitors must be referenced to the individual grounds for proper noise rejection (see Figure 3-5 for more information). Also, in all cases, the four VDD pins must be connected together externally. The input current drawn from the external power supply or VIN pin is the sum of the 1 mA (maximum) current drawn by the internal circuitry for all three channels and the current drawn by the gate drivers. In turn, the current drawn by the gate drivers depends on the switching frequency and the gate charge of the external FET. EQUATION 3-1: I IN = 1mA +  Q G1 + Q G2 + Q G3   f S In Equation 3-1, fS is the switching frequency of the converters, and QG1-3 are the gate charges of the external FETs which can be obtained from the FET data sheets.  2019 Microchip Technology Inc. The EN pin is a TTL-compatible input used to disable the IC. Pulling the EN pin to GND will shut down the IC and reduce the quiescent current drawn by the IC to less than 200 μA. If the enable function is not required, the EN pin can be connected to VDD. 3.3 Clock Input (CLK) The switching frequency of the converters can be set in two ways. The first is by using the on-chip oscillator with a resistor at the RT pin. In this case, the CLK pin should be connected to GND. If the on-chip clock is used, two or more HV9985s cannot be synchronized with each other. The second is by using a TTL compatible square wave input at the CLK pin. The switching frequencies of the 3 converters will be 1/12th the frequency of the external clock. By using the same clock for multiple ICs, all the ICs can be synchronized together. In this case, the RT pin can either be left open or connected to GND. 3.4 Current Sense (CS1–CS3) The current sense input is used to sense the source current of the switching FET. Each CS input of the HV9985 includes a built-in 100 ns (minimum) blanking time to prevent spurious turn-off due to the initial current spike when the FET turns on. The IC includes an internal resistor divider network, which steps down the voltage at the COMP pins by a factor of 9. This voltage is used as the reference for the current sense comparators. Since the maximum voltage of the COMP pin is approximately (VDD–1V), this voltage determines the maximum reference current for the current sense comparator and thus the maximum inductor current. The current sense resistor RCS should be chosen, so that the input inductor current is limited to below the saturation current level of the input inductor. For Discontinuous Conduction mode, no slope compensation is necessary. In this case, the current sense resistor is chosen with Equation 3-2. EQUATION 3-2: V DD – 1V R CS = -----------------------9  I IN PK Where: “IIN,PK” is the maximum desired peak input current For Continuous Conduction mode converters operating in Constant Frequency mode, slope compensation becomes necessary to ensure the stability of the Peak Current mode controller if the operating duty cycle is DS20005558B-page 9 HV9985 greater than 50%. This factor must also be accounted for when determining RCS. (Refer to Section 3.5 “Slope Compensation”.) 3.5 Slope Compensation Choosing a slope compensation that is one half of the down slope of the inductor current ensures that the converter will be stable for all duty cycles. VDD CS CSC GATE FIGURE 3-1: RCS Slope Compensation. As illustrated in Figure 3-1, slope compensation in HV9985 can be programmed by two external components. A resistor for VDD sets a current, which is almost constant since the VDD voltage is much larger than the voltage at the CS pin. This current flows into the capacitor and produces a ramp voltage across the capacitor. The voltage at the CS pin is then the sum of the voltage across the capacitor and the voltage across the current sense resistor, with the voltage across the capacitor providing the required slope compensation. When the GATE turns off, an internal pull-down FET discharges the capacitor. The 100Ω resistance of the internal FET (RDIS) will prevent the voltage at the CS pin from going all the way to zero. Equation 3-3 shows how much the minimum value of the voltage will become. EQUATION 3-3: V DD V CS MIN = -----------  R DIS R SC The slope compensation capacitor is chosen, so that it can be completely discharged by the internal FET at the CS pin when FET is switched off. Assuming the worst case switch duty cycle of 92%, CSC may be determined with Equation 3-4. EQUATION 3-4: 0.08 C SC = -----------------------------3  R DIS  f S DS20005558B-page 10 EQUATION 3-5: V DD – 1 1 R CS = --------------------  ----------------------------------------------------------------9 DS  10 6  0.92 -------------------------------------- + I IN PK 2  fS 2  V DD R SC = ---------------------------------------------------DS  10 6  C SC  R CS RSC + Assuming a down slope current slew rate of DS (A/μs) for the inductor current, the current sense resistor and the slope compensation resistor can be computed as demonstrated in Equation 3-5. Note that sometimes excessive stray inductance in the current sense path may cause the slope compensation circuit to mistrigger. Figure 3-2 shows the detailed slope compensation circuit with a parasitic inductance LP between the ground of the boost converter power stage and the ground of the respective controller channel in HV9985. The figure also includes the drain capacitance of the boost FET Q1, which is the total capacitance at the drain node. GATE Q1 VDD CS + RSC CDRAIN CSC + VDRAIN - GATE Q2 RCS - VLP + GND LP FIGURE 3-2: Operation. ILP Slope Compensation Circuit When the boost FET Q1 is turned off, the internal discharge FET Q2 is turned on and capacitor CSC is discharged. Also, CDRAIN is charged to the output voltage VO. When the FET Q1 is turned on, the drain node of the FET Q1 is pulled to ground. (Q2 is turned off just before Q1 is turned on.) This causes the drain capacitance to discharge through the FET, leading to a current spike as illustrated in Figure 3-3. This current spike causes a voltage to develop across the parasitic inductance. As long as the current is increasing through the inductance, the voltage developed across parasitic inductance is successfully blocked by the body diode of Q2. However, during the falling edge of the current spike, the voltage across the parasitic inductor causes the body diode to become forward biased. This conduction path through the body diode of  2019 Microchip Technology Inc. HV9985 Q2 causes pre-charge of CSC. The pre-charge voltage can be fairly high since the rate of fall of the current is very large. VDRAIN ILP VLP FIGURE 3-3: Waveforms during Turn-on. EQUATION 3-6: 3A V PRE – CHARGE = 10nH  ------------ = 600mV 50ns As shown in the equation, a very optimistic estimate of the pre-charge voltage is already larger than the Steady state peak current sense voltage. This will cause the converter to false trip. To prevent this behavior, a resistor REXT (typically 500Ω to 800Ω) can be added in series with the capacitor CSC as shown in Figure 3-4. This resistor limits the charging current from parasitic inductance into the capacitor. However, the resistor will also slow down the discharge of the capacitor during the FET off-time, so a smaller CSC will be necessary. The component values for the slope compensation design that include REXT can be computed by substituting REXT + RDIS in place of RDIS in Equation 3-3 to Equation 3-5. GATE Q1 VDD - RSC CS REXT CDRAIN CSC GATE RCS Q2 GND LED Current Control The LED currents in the HV9985 are controlled using three independent current feedbacks. The reference voltage inputs, which set the three LED currents, should be provided at each REF pin (REF1-3). These reference voltages are compared to the voltage from the LED current sense resistors at the corresponding FDBK pins (FDBK1-3) by the respective transconductance amplifiers. HV9985 includes three 1 MHz transconductance amplifiers with tri-state output, which are used to close the feedback loops and provide accurate current control. The compensation networks are connected to the COMP pins (COMP1-3). The full brightness LED current in each channel can be set by Equation 3-7. For example, a typical current spike usually lasts about 100 ns. Assuming a 3A peak current, which is the FET’s typical saturation current, and equal distribution between the rise and fall times, a 10 nH parasitic inductance causes a pre-charge voltage. Refer to Equation 3-6. + 3.6 - VLP + LP ILP FIGURE 3-4: Modified Slope Compensation Circuit.  2019 Microchip Technology Inc. + VDRAIN - EQUATION 3-7: V REFn I On = --------------R Sn Where n is the channel number. The output of each op-amp is buffered and connected to the current sense comparators using an 8:1 divider. The outputs of the op-amps are controlled by the signal applied to the PWMD pins (PWMD1-3). When PWMD is high, the op-amp output is connected to the COMP pin. When PWMD is low, the output is left open. This enables the integrating capacitor to hold the charge and the voltage at the COMP pin unchanged when the PWMD signal is low, and the gate driver output (GATE1-3) is off. When PWMD is changed from low back to high again, the voltage on the integrating capacitor will force the converter into Steady state almost instantly. 3.7 Linear Dimming Linear dimming can be achieved by varying the voltages at the REF pins. Since the HV9985 is a Peak Current mode controller, it has a minimum on-time for the GATE outputs. This minimum on-time prevents the converters from completely turning off even when the REF pins are pulled to GND. Thus, linear dimming cannot accomplish true zero-LED current. To get zero-LED current, PWM dimming has to be used for this IC device. Different signals can be connected to the three REF pins if desired, and these inputs need not be connected together. Due to the offset voltage of the short-circuit comparator and the non-linearity of the X2 gain stage, pulling the REF pin very close to GND would cause the internal short-circuit comparator to trigger and shut down the IC. To overcome this, the output of the gain stage is limited to 125 mV (minimum), allowing the REF pin to be pulled all the way to 0V without triggering the short-circuit comparator. DS20005558B-page 11 HV9985 3.8 PWM Dimming PWM dimming in the HV9985 can be done using TTL compatible square wave sources at the PWMD pins (PWMD1-3). All three channels can be individually PWM dimmed as desired. When the PWM signal is high, the GATE and FLT pins are enabled and the output of the transconductance op-amp is connected to the external compensation network. Thus, the internal amplifier controls the output current. When the PWMD signal goes low, the output of the transconductance amplifier is disconnected from the compensation network. Thus, the integrating capacitor maintains the voltage across it. The GATE is disabled, so the converter stops switching, and the FLT pin goes low, turning off the disconnect switch. The output capacitor of the converter determines its PWM dimming response since it has to get charged and discharged whenever the PWMD signal goes high or low. In the case of a buck converter, since the inductor current is continuous, a very small capacitor is used across the LEDs. This minimizes the effect of the capacitor on the PWM dimming response of the converter. However, for a boost converter, the output current is discontinuous, and a large output capacitor is required to reduce the ripple in the LED current. Therefore, this capacitor will have a significant impact on the PWM dimming response. By turning off the disconnect switch when PWMD goes low, the output capacitor is prevented from being discharged, and the PWM dimming response of the boost converter improves dramatically. Note that disconnecting the LED load during PWM dimming causes the energy stored in the inductor to be dumped into the output capacitor. The chosen filter capacitor should be large enough, so that it can absorb the inductor energy without causing any significant change in voltage across it. 3.9 Fault Conditions hiccup time is long enough, it will ensure that the compensation networks are all completely discharged and that the converters start at a minimum duty cycle. The hiccup timing capacitor can be programmed as demonstrated in Equation 3-8: EQUATION 3-8: 5A  t HICCUP C SKIP = ------------------------------------1.5V 3.10 Output LED Short-Circuit Protection When an output LED string Short-circuit condition is detected (i.e. output current becomes higher than twice the Steady state current), the GATE and FLT outputs are pulled low. As soon as the disconnect FET is turned off, the output current goes to zero and the Short-circuit condition disappears. At this time, the hiccup timer is started. Once the timing is complete, the converter attempts to restart. If the Fault condition still persists, the converter shuts down and goes through the cycle again. If the Fault condition is cleared (a momentary output short), the converter will start regulating the output current. This allows the LED driver to recover from accidental shorts without the need to reset the IC. During Short-circuit conditions, there are two factors that determine the hiccup time. First is the time required to discharge the compensation capacitors. Assuming a pole-zero R-C network at the COMP pin (series combination of RZ and CZ in parallel with CC), tCOMP,n is calculated as shown in Equation 3-9: EQUATION 3-9: t COMP n = 3  R Zn  C Zn Where: n refers to the channel number HV9985 is a robust controller which can protect the LEDs and the LED driver in Fault conditions. The outputs of the HV9985 LED driver are protected from both Open and Short LED conditions. In both cases, the HV9985 shuts down and attempts to restart. The hiccup time can be programmed by a single external capacitor at the SKIP pin. When the compensation networks are only of Type 1 (single capacitor), the computation in Equation 3-10 is used. During start-up or when a Fault condition is detected, both GATE and FLT outputs are disabled, the COMP and SKIP pins are pulled to GND. Once the voltage at the SKIP pin falls below 0.1V, and the Fault condition(s) have disappeared, the capacitor at the SKIP pin is released, and it begins charging slowly from a 5 μA current source. Once the capacitor is charged to 1.6V, the COMP pins are released, and the gate driver outputs (GATE and FLT) are allowed to turn on. If the Therefore, the maximum COMP discharge time required can be calculated as specified in Equation 3-11: DS20005558B-page 12 EQUATION 3-10: t COMP n = 3  300  C Zn EQUATION 3-11: t COMP MAX = max  t COMP1 t COMP2 t COMP3   2019 Microchip Technology Inc. HV9985 The second factor is the time required for the inductors to discharge completely after the Short-circuit condition has been cleared. The time can be computed as illustrated in Equation 3-12: 3.12 EQUATION 3-12: When the load is disconnected in a boost converter, the output voltage rises as the output capacitor starts charging. When the output voltage reaches the OVP rising threshold, HV9985 detects an Overvoltage condition and turns off the converter. The converter is turned back on only when the output voltage falls below the falling OVP threshold, which is 10% lower than the rising threshold. This time is mostly dictated by the R-C time constant of the output capacitor CO and the resistor network used to sense overvoltage (ROVP1+ ROVP2). In case of a persistent Open Circuit condition, this cycle maintains the output voltage within a 10% band.  t IND n = ---- L n  C On 4 Where: L and CO are input inductor and output capacitor of each power stage. n refers to the channel number. The hiccup time is then chosen as shown in Equation 3-13: EQUATION 3-13: t HICCUP  max  t COMP MAX t IND MAX  3.11 False Triggering of the Short-Circuit Comparator During PWM Dimming During PWM dimming, the parasitic capacitance of the LED string causes a spike in the output current when the disconnect FET is turned on. If this spike is detected by the short-circuit comparator, it will cause the IC to falsely detect an Overcurrent condition and shut down. In HV9985, to prevent these false triggerings, a built-in 500 ns blanking network for the short-circuit comparator is included. This blanking network is activated when the PWMD input goes high. Thus, the short-circuit comparator will not see the spike in the LED current during the turn-on transition of the PWM Dimming. Once the blanking time is over, the short-circuit comparator will start monitoring the output current. Thus, the total delay time for detecting a short-circuit will depend on the condition of the PWMD input. If the output short-circuit exists before the PWM dimming signal goes high, the total detection time is computed as shown in Equation 3-14: EQUATION 3-14: t DETECT1 = t BLANK + t DELAY  900ns  max  If the short-circuit occurs when the PWM dimming signal is already high, the time to detect will be calculated as illustrated in Equation 3-15: EQUATION 3-15: t DETECT1 = t DELAY  200ns  max   2019 Microchip Technology Inc. Overvoltage Protection HV9985 provides hysteretic overvoltage protection, allowing the IC to recover in case the LED load is disconnected momentarily. In most designs, the falling OVP threshold is more than the LED string voltage. Therefore, when the LED load is reconnected to the output of the converter, the voltage differential between the actual output voltage and the LED string voltage results in a spike in output current. This leads to the detection of a short circuit, and the short-circuit protection in the HV9985 is triggered. This behavior continues until the output voltage becomes lower than the LED string voltage. When this occurs, no Fault condition will be detected, and the normal operation of the circuit will commence. Note: 3.13 The overvoltage thresholds for the three channels in the HV9985 are derived using resistor dividers from the respective VDDs. The resistor dividers are adjusted to give a 1.25V OVP rising trip point and a 1.125V OVP falling trip point at VDD = 5V. The OVP trip points mentioned in the electrical characteristics table of the data sheet assume a VDD voltage generated by the linear regulator of the HV9985. Using an external voltage source at VDD will change the OVP trip points proportionally. Layout Considerations For multi-channel Peak Current mode controller IC to work properly with minimum interference between the channels, it is important to have a good PCB layout which minimizes noise. (Refer to Figure 3-5.) Following the layout rules stated below will help ensure proper performance of all three channels. 3.13.1 GND CONNECTION The IC has four separate ground connections—one for each of the three channels and one analog ground for the common circuitry. It is recommended that four DS20005558B-page 13 HV9985 separate ground planes be used in the PCB, and all the GND planes be connected together at the return terminal of the input power lines. 3.13.2 VDD CONNECTION Each VDD pin should be bypassed with a low-ESR capacitor to its OWN ground (i.e. VDD1 is bypassed to GND1 and so on). The common VDD pin can be bypassed to the common GND. 3.13.3 3.13.5 OVP PROTECTION Typically, the OVP resistor dividers are located away from the IC. To prevent false trigerrings of the IC due to noise at the OVP pin, placing a small bypass capacitor (1 nF) right at the OVP pin is recommended. REF CONNECTION In case all the references are going to be driven from a single voltage source, it is recommended to have a small R-C low pass filter (1k, 1 nF) at each REF pin with the filter being referenced to the appropriate channel’s ground (as in the case of the VDD pins). If the REF pins are driven with three individual voltage sources, then a small capacitor (1 nF) at each pin would be suitable. 3.13.4 GATE AND CS CONNECTION The connection from GATE output to the gate of the external FET and the connection from the CS pin to the external sense resistor are designed to be short to avoid false trigerrings. VDD Connection Input Return Terminal GND2 VDD2 GND1 VDD1 GND3 VDD3 Star Connection of GND HV9985 REF1 REF3 Reference VDD GND REF2 REF Connection GND Exposed Pad Connection FIGURE 3-5: DS20005558B-page 14 Layout Guidelines.  2019 Microchip Technology Inc. HV9985 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 40-lead QFN XXXXXX XX e3 YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example HV9985 K6 e3 1925456 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2019 Microchip Technology Inc. DS20005558B-page 15 HV9985 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. DS20005558B-page 16  2019 Microchip Technology Inc. HV9985 APPENDIX A: REVISION HISTORY Revision A (August 2019) • Converted Supertex Doc #s DSFP-HV9985 to Microchip DS20005558B • Removed the 44-lead QSOP Package and the K6 M935 media type • Made minor text changes throughout the document Revision B (September 2019) • Changed "PWMD changes from low to high (Note 1)" to "Note 2" in Switching Frequency Range conditions under the Electrical Characteristics Table • Changed “Note 1” to “PWMD changes from low to high (Note 1)” in Blanking Time conditions under the Electrical Characteristics Table  2019 Microchip Technology Inc. DS20005558B-page 17 HV9985 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. Device - Package Options X - Environmental X Media Type Device: HV9985 = 3-Channel Closed-Loop Switch-Mode LED Driver IC Package: K6 = 40-lead QFN (6x6) Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 490/Tray for K6 Package DS20005558B-page 18 Example: a) HV9985K6-G: 3-Channel Closed-Loop Switch-Mode LED Driver IC, 40-lead QFN (6x6), 490/Tray  2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2019 Microchip Technology Inc. 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