KS8737-EVAL

KS8737 Micrel KS8737 3.3V 10/100BaseTX/FX MII Physical Layer Transceiver Rev 3.11 General Description Features Operating at 3.3 Volts to meet low voltage and low power requirement, the KS8737 is a 10/100BaseTX/FX Physical Layer Transceiver which provides MII interface to transmit and receive data. It contains the 100BaseTX/FX Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), and Physical Coding Sub-layer (PCS) functions. Moreover, the KS8737 has on-chip 10BaseT encoder/decoder and output filtering, which eliminates the need for external filters and makes possible a single set of line magnetics to be used to meet requirement for both 100BaseTX/ FX and 10BaseT. The KS8737 can automatically configure itself for 100 or 10 Mbps and full or half duplex operation, using on-chip AutoNegotiation algorithm. It’s an ideal choice of physical layer transceiver for 100BaseTX/100BaseFX/10BaseT applications. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. • Single chip 100BaseTX/100BaseFX/10BaseT physical layer solution • 3.3V CMOS design, 70mA operating current (excluding transmit output driver current) • Fully compliant to IEEE 802.3u standard • Support Media Independent Interface (MII) mode • Support 10BaseT, 100BaseTX and 100BaseFX Fiber Channel with Far_End_Fault Detection • Support power down mode and power saving mode • Configurable through MII serial management ports or via external control pins • Support auto-negotiation and manual selection for 10Mbps or 100Mbps speed • Support auto-negotiation and manual selection for fulland half-duplex mode • Standard CSMA/CD or full-duplex operation at 10Mbps or 100Mbps • On-chip built-in filtering for both 100BaseTX and 10BaseT Functional Diagram TXP TXM Transmitter 10/100 Pulse Shaper NRZ/NRZI MLT3 Encoder 4B/5B Encoder Scrambler Parallel/Serial Parallel/Serial Manchester Encoder RXP RXM Adaptive EQ Base Line Wander Correction MLT3 Decoder NRZI/NRZ Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel MII Registers and Controller Interface Auto Negotiation 10BaseT Receiver Manchester Decoder Serial/Parallel TXD3 TXD2 TXD1 TXD0 TXER TXC TXEN CRS COL MDIO MDC RXD3 RXD2 RXD1 RXD0 RXER RXDV RXC FXMODEB FIBIP Power Down or Saving FIBIM X1 X2 PLL PWRDWN PWRSAVE LED Driver LINK ACT COL FDX SPD Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com August 2003 1 KS8737 KS8737 Micrel Features (continued) Ordering Information • LED outputs for link, activity, full/half duplex, collision and speed • Supports back to back FX to TX for media converter applications • Available in 64-pin TQFP surface mount package (10 mm × 10 mm × 1.0 mm) KS8737 Part Number KS8737 2 Temperature Range Package 0°C to +70°C 64-Pin TQFP August 2003 KS8737 Micrel Revision History Revision Date Summary of Changes 3.0 7/01/02 Update to company logo and format. Add new feature on pin 33(DISTX/LPBK); disable the transmit only during media converter mode and select the loopback mode with TST2 pin. Change RXC type from I/O to O. Change the Register 1fh.9 to reserved. Change the Register 1fh.5 mode from RW to RO. Update on the 10/100BT MII receiving timing. Change on register 1fh.1 to reserved. Add the fiber mode description. 3.1 4/01/03 Change the company logo, legal disclaimer, contact info. 3.11 8/29/03 Convert to new format. August 2003 3 KS8737 KS8737 Micrel Table Of Contents Pin Description ............................................................................................................................................................ 5 Pin Configuration ........................................................................................................................................................ 8 Functional Description ................................................................................................................................................ 9 100BaseTX Transmit ............................................................................................................................................. 9 100BaseTX Receive .............................................................................................................................................. 9 PLL Clock Synthesizer ........................................................................................................................................... 9 Scrambler/De-scrambler (100BaseTX only) .......................................................................................................... 9 10BaseT Transmit ................................................................................................................................................. 9 10BaseT Receive .................................................................................................................................................. 9 SQE and Jabber Function (10Base only) .............................................................................................................. 9 Auto-Negotiation .................................................................................................................................................. 10 MII Management Interface ................................................................................................................................... 10 MII Data Interface ................................................................................................................................................ 10 Transmit Clock ............................................................................................................................................. 10 Receive Clock .............................................................................................................................................. 10 Transmit Enable ........................................................................................................................................... 10 Receive Data Valid ...................................................................................................................................... 10 Error Signals ................................................................................................................................................ 11 Carrier Sense ............................................................................................................................................... 11 Collision ....................................................................................................................................................... 11 Power Management ............................................................................................................................................. 11 Fiber Mode ........................................................................................................................................................... 11 Media Converter Option ....................................................................................................................................... 11 Register Map ........................................................................................................................................................... 12 Register 0h: Basic Conrol ................................................................................................................................... 12 Register 1h: Basic Status .................................................................................................................................... 12 Register 2h: PHY Identifier 1 .............................................................................................................................. 13 Register 3h: PHY Identifier 2 .............................................................................................................................. 13 Register 4h: Auto-Negotiation Advertisement ..................................................................................................... 13 Register 5h: Auto-Negotiation Link Partner Ability .............................................................................................. 14 Register 6h: Auto-Negotiation Expansion ........................................................................................................... 14 Register 7h: Auto-Negotiation Next Page ........................................................................................................... 14 Register 15h: RXER Counter .............................................................................................................................. 14 Register 1bh: Interrupt Control/Status Register .................................................................................................. 15 Register 1fh: 100BaseTX PHY Controller ........................................................................................................... 15 Mode Selection for Registers ................................................................................................................................... 17 Typical Application Circuit ....................................................................................................................................... 18 Absolute Maximum Ratings ..................................................................................................................................... 19 Operating Ratings ..................................................................................................................................................... 19 Electrical Characteristics .......................................................................................................................................... 19 Timing Diagrams ....................................................................................................................................................... 21 Selection of Isolation Transformers ........................................................................................................................ 27 Selection of Reference Crystals ............................................................................................................................... 27 Package Outline and Dimensions ............................................................................................................................ 28 KS8737 4 August 2003 KS8737 Micrel Pin Description Pin Number Pin Name Type(Note 1) 1 CRS O 2 INTRPT 3 RXENB I/O MII Receive Enable Input. Active Low. If this pin is High, the Receive output of MII (RXD[3:0], RXDV, RXER, RXC) will be in tri-state. This pin becomes an I/O pin for factory testing in the test mode. 4 PHYAD4 I/O PHY Address Bit [4] Input. This pin becomes an I/O pin for factory testing in the test mode. 5 PHYAD3 I/O PHY Address Bit [3] Input. This pin becomes an I/O pin for factory testing in the test mode. 6 PHYAD2 I/O PHY Address Bit [2] Input. This pin becomes an I/O pin for factory testing in the test mode. 7 PHYAD1 I/O PHY Address Bit [1] Input. This pin becomes an I/O pin for factory testing in the test mode. 8 PHYAD0 I/O PHY Address Bit [0] Input. This pin becomes an I/O pin for factory testing in the test mode. 9, 19, 24, 37, 53 VDD P 10, 22, 26, 31, 43, 52, 63 GND GND 11 X2 O Crystal Oscillator Output. This pin is connected to the other terminal of the 25MHz crystal. If X1 is driven by an external clock, X2 must be left open. 12 X1 I Crystal Oscillator Input. Input for a crystal or an external 25MHz clock. 13 FDX I/O Full-Duplex Input. If this pin is High, it sets full-duplex operation. If this pin is Low, it sets half duplex operation. The input signal of this pin is latched at reset. After reset, this pin becomes test pin for factory test. 14 15 MODE0 MODE1 I/O Mode Select Input. These pins carry encoded input signals that are latched at reset and power up to set mode of operation. After reset, they become test pins for factory test. These pins are I/O pins in the test mode. 16 RSTB* I Hardware Reset Input. Active Low signal. It forces the device to a known state. Internal 100kΩ pull-up. 17,35, 36 NC 33 DISTX/LPBK Note 1. Pin Function MII Carrier Sense Output. Active High. High impedance when PHY is isolated. I/O Interrupt Output. This pin requires an external 10k pull-up resistor. This pin becomes an I/O pin for factory testing in the test mode. 3.3V power supply Ground. No Connect. I Disable transmit Input. If this pin is high, it disables transmit only during the Media converter mode. Floating is for normal operation. The DISTX/LPBK pin also selects several functions together with the TST2 pin. LPBK/DISTX TST2 High High Disable Transmit High Float Local Loopback Low High Remote Loopback Low Float Remote Loopback 18 FXSD I Fiber Signal Detect. To detect fiber signal. Left open when not in use. 20 PWRSAVE/ FXSD_THD I Power Saving Mode Initialization Input. (Affecting Register 1f.15). To disable power saving mode, tie this pin low; otherwise, power saving mode is asserted. This pin can also be used to set FX signal detect threshold in fiber mode. P = power supply G = ground I = input O = output I/O = bi-directional August 2003 5 KS8737 KS8737 Micrel Pin Number Pin Name Type(Note 1) 21 23 TXP TXM O Twisted Pair Transmit Outputs. Differential transmit outputs for 100BaseTX or 10BaseT to magnetic. 25 ISET O Transmit Current Set. Connecting an external reference resistor to set transmitter output current. This pin connected to a 22.1kΩ 1% resistor to ground if a transformer of 1:1 turns ratio is used. 27 28 FIBIP FIBIM I Fiber Receive Inputs. Differential pseudo-ECL receive pairs compatible with standard fiber transceiver for 100BaseFX. Both pins should be tied to ground if not used or if not in the FX mode. 29 30 RXP RXM I Twisted Pair Receive Input. Differential receive input pins for 100BaseTX or 10BaseT from the magnetics. 32 TST2 I Test Pin. During normal operation this pin should be left open. When tied high through a 1k resistor the chip will operate in back to back TX to FX mode. In this case, TXC becomes an input pin. 34 PWRDWN I Power Down Select Input. When this pin is tied high, the chip is in power down mode. When this pin is open or tied low, the chip is in normal operation.. 38 LEDSPD I/O LED Output. During normal operation, this pin lights the SPEED LED to indicate 100Mbps is selected. This pin becomes an I/O pin for factory testing in the test mode. Active Low. 39 LEDCOL I/O LED Output. During normal operation, this pin lights the COL LED to indicate a collision. It will flash at a rate of 50ms high and 50ms low when active. This pin becomes an I/O pin for factory testing in the test mode. Active Low. 40 LEDLINK I/O LED Output. During normal operation, this pin lights the LINK LED to indicate a good link is detected. This pin becomes an I/O pin for factory testing in the test mode. Active Low. 41 LEDACT I/O LED Output. During normal operation, this pin lights the Activity LED when transmitting or receiving. It will flash at a rate of 50ms high and 50ms low when active. This pin becomes an I/O pin for factory testing in the test mode. Active Low. 42 LEDFDX I/O LED Output. During normal operation, this pin lights the FDX LED to indicate a full-duplex mode. This pin becomes an I/O pin for factory testing in the test mode. Active Low. 44 MDIO I/O Serial Management Data Input/Output. This pin requires an external 10k pull-up resistor. 45 MDC I Serial Management Interface Clock Input. This pin is synchronous to the MDIO data interface. 46 FXMODEB I FX Mode Select Input. Active Low. When this pin is low, the KS8737 is in the 100BaseFX mode. 47 48 49 50 RXD3 RXD2 RXD1 RXD0 O MII Receive Data Output. Active High, clocked out on the falling edge of RXCLK. RXD0 is the LSB. High impedance when PHY is isolated or if RXEN is deasserted. 51 RXDV/ CRSDV O MII Receive Data Valid Output. Active High, clocked out on the falling edge of RXCLK. This signal indicates that recovered and decoded data nibbles are being presented synchronously to RXCLK. High impedance when PHY is isolated or if RXEN is de-asserted. 54 RXC O MII Receive Clock Output. 25MHz in 100BaseTX mode, 2.5MHz in 10BaseT nibble mode. High impedance when PHY is isolated or if RXEN is de-asserted. Note 1. Pin Function P = power supply G = ground I = input O = output I/O = bi-directional KS8737 6 August 2003 KS8737 Micrel Pin Number Pin Name Type(Note 1) 55 RXER O MII Receive Error Output. Driven High synchronously on the falling edge of RXCLK when invalid symbol has been detected in 100BaseTX mode. This pin is ignored in 10BaseT operation. High impedance when PHY is isolated 56 TXER I MII Transmit Error Input. A High on this pin causes the 4B/5B encode process to substitute the Transmit Error code-group for the encoded data word. This pin is ignored in a 10BaseT operation. When TXER is not used, this pin should be tied Low through a 10kΩ resistor. 57 TXC I/O MII Transmit Clock Output / Back to Back Mode Clock Input. During normal operation TXC is an output pin. It provides 25MHz in 100BaseTX mode, 2.5MHz in 10BaseT nibble mode. In back to back mode it becomes an input pin. High impedance when PHY is isolated. 58 TXEN I/O MII Transmit Enable Input. A High on this pin causes the transmit data TXD[3:0] to be encoded and scrambled for transmission. 59 60 61 62 TXD0 TXD1 TXD2 TXD3 I MII Transmit Data Input. TXD0 is the LSB. High impedance when PHY is isolated. 64 COL O MII Collision Detect Output. Active High. High impedance when PHY is isolated. This signal is de-asserted in full-duplex operation. Note 1. Pin Function P = power supply G = ground I = input O = output I/O = bi-directional August 2003 7 KS8737 KS8737 Micrel COL GND TXD3 TXD2 TXD1 TXD0 TXEN TXC TXER RXER RXC VDD GND RXDV RXD0 RXD1 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CRS INTRPT RXENB PHYAD4 PHYAD3 PHYAD2 PHYAD1 PHYAD0 VDD GND X2 X1 FDX MODE0 MODE1 RSTB 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RXD2 RXD3 FXMODEB MDC MDIO GND LEDFDX LEDACT LEDLINK LEDCOL LEDSPD VDD NC NC PWRDWN DISTX/LPBK NC FXSD VDD PWRSAVE/FXSD_THD TXP GND TXM VDD ISET GND FIBIP FIBIM RXP RXM GND TST2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-Pin TQFP (TQ) KS8737 8 August 2003 KS8737 Micrel Functional Description 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the 25 MHz, 4-bit nibbles into a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from NRZ to NRZI format, then transmitted in MLT3 current output. The output current is set by an external 1% 22.1kΩ resistor for the 1: 1 transformer ratio. It has a typical rise/fall times of 4 ns and is complied to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output driver is also incorporated into the 100BaseTX driver, and the total output capacitance is typical 7pF with short PC board traces assumed. 100BaseTX Receive The 100BaseTX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristic to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized 25MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both TXC and RXC clocks continue to run. PLL Clock Synthesizer The KS8737 generates 125MHz, 25MHz and 20MHz clocks for system timing. An internal crystal oscillator circuit provides the reference clock for the synthesizer. Scrambler/De-scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The KS8737 provides a scrambler-bypass mode for testing purpose. Bypassing the scrambler causes the PCS-layer encoder to be bypassed such that the MII is operated in the 5B mode. 10BaseT Transmit When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8737 will continue to encode and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into the 100Base driver to allow transmission with the same magnetic. They are internally wave-shaped and preemphasized into outputs with typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BaseT Receive On the receive side, input buffer and level detecting squelch circuit are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8737 decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception. The KS8737 supports extended length cables for 10BaseT by selecting a lower squelch level around 150mV. SQE and Jabber Function (10BaseT only) In 10BaseT operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test of the 10BaseT transmit/receive path and is called SQE test. The 10BaseT transmitter will be disabled and COL will go High if TXEN is High for more than 46 us (Jabbering) If TXEN then goes Low for more than 368 us, the 10BaseT transmitter will be re-enabled and COL will go Low. August 2003 9 KS8737 KS8737 Micrel Auto-Negotiation The KS8737 performs auto-negotiation by hardware (mode[1:0]) or software (Register 0.12). It will automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever autonegotiation is enabled. It can also be configured to advertise 100BaseTX or 10BaseT in either full- or half-duplex mode. The auto-negotiation is disabled in the FX mode. During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the conditions of power-on, link-loss or re-start. At the same time, the KS8737 will monitor incoming data to determine its mode of operation. Parallel detection circuit will be enabled as soon as either 10BaseT idle or 100BaseTX idle is detected. The operation mode gets configured based on the following priority: Priority 1: 100BaseTX, Full-duplex Priority 2: 100BaseTX, Half-duplex Priority 3: 10BaseT, Full-duplex Priority 4: 10BaseT, Half-duplex When the KS8737 receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8737 detects the second code words, it then configures itself according to above-mentioned priority. In addition, the KS8737 also checks 100BaseTX idle or 10BaseT NLP symbol. If either is detected, the KS8737 automatically configures to match the detected operating speed. MII Management Interface The KS8737 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8737. The MDIO interface consists of the following: • A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT) • A specific protocol which runs across the above-mentioned physical connection and allows one controller to communicate with multiple KS8737 devices. Each KS8737 assigned an MII address between 0 and 31 by the PHYAD inputs. • An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality. The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on the KS8737 based on 1fh.14 level control. Register 1bh[15:8] are the interrupt enable bits. Register 1bh[7:0] are the interrupt conditions bits. The interrupt is activated when changes made to the following conditions: • Link Status • Duplex Status Reading Register 1bh clears this interrupt. MII Data Interface The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller (MAC) to the KS8737, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4bit wide nibbles). Transmit Clock (TXC): The transmit clock is normally generated by the KS8737 from an external 25MHz reference source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8737 normally samples these signals on the rising edge of the TXC. Receive Clock (RXC): For 100BaseTX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-negotiation is disabled, receive clock operates off the master input clock (X1 or TXC). For 10BaseT links, received is recovered from the line while carrier is active, and operates from the master input clock when the line is idled. The KS8737 synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. Transmit Enable: The MAC must assert TXEN the same time as the first nibble of preamble, and de-assert TXEN after the last bit of the packet. Receive Data Valid: The KS8737 asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way: • For 100BaseTX link with the MII in 4B mode, RXDV is asserted from the first nibble of preamble to the last nibble of the data packet. • For 10BaseT links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “ 5D” and remains asserted until the end of the packet. KS8737 10 August 2003 KS8737 Micrel Error Signals: Whenever the KS8737 receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on the RXD pins. When the MAC asserts TXER, the KS8737 will drive “H” symbols out on the line. Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8737 asserts its collision signal which is asynchronous to any clock. Power Management The KS8737 offers the following modes for power management: • Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin PWRDWN High. • Power Saving Mode: This mode can be enabled by writing to Register 1fh.15. or using an external initialization pin. The KS8737 will then turn off everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KS8737 will shutdown most of the internal circuits to save power if there is no link. Fiber Mode Fiber mode is activated by setting FXMODEB (pin46) low. Under this mode, the FIBP/M are become the receiving port, and the TXP/M are the transmit port. FXSD (+) and FXSD_THD (-) are used as differential signal for Fiber signal detect port. If driven single-ended with FXSD and FXSD_THD should be set by an external voltage divider for the proper reference voltage, there is no internal voltage for this pin. Under Fiber mode, the link is up only when FXSD>FXSD_THD and the proper idle pattern is received. If FXSD