KS8993M

KS8993M/ML/MI Product Brief www.micrel.com Integrated 3-Port 10/100 Managed Switch with PHY Description The KS8993M family is a highly integrated Layer 2 managed switch designed for low-port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes tag/port-based VLAN, QoS priority, switch management, MIB counters, MII/SMI interface, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KS8993M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address look-up engine, and an on-chip frame buffer memory. Both PHY ports support 10BASE-T and 100BASE-TX with Auto-MDIX for reliable detection of and correction for straight-through and crossover cables. In addition, one PHY port supports 100BASE-FX for managed media converter applications. QoS prioritization, both tag and port-based, makes the KS8993M family ideal for latency critical applications such as Voice over Internet Protocol (VoIP) phones and industrial Ethernet applications. The KS8993M is available in a wide variety of power supply, packaging, and temperature options to fit the Commer demanding needs of today’s applications. Commercial temperature range: 0oC to +70oC; Industrial temperature tempera range: –40oC to +85oC. For additional information, contact your local Micrel Field Application Engineer or salesperson. Block Diagram AUTO TO MDI/MDI-X 10/100 T/TX/FX PHY 1 10/100 T/TX PHY 2 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 MII/SNI SNI SPI SPI MIIM FIFO, Flow Control, VLAN Tagging, Priority AUTO TO MDI/MDI-X 1K Look-Up Engine Control Registers I2C P2 LED[3:0] Micrel Semiconductor LED Drivers TEL: 1.408.944.0800 Buffer Management Frame Buffers MIB Counters EEPROM Interface SMI P1 LED[3:0] Queue Management Strap-In Configuration FAX: 1.408.474.1000 HTTP:// www.micrel.com Features Benefits • QoS packet prioritization support – Per port, 802.1p, and DiffServ-based – Re-mapping of IEEE 802.1p priority field per port basis • Enables latency critical applications to transport network traffic with minimal interruption. Per port re-mapping enforces priority policies by overriding embedded levels. • IEEE 802.1q VLAN support for up to 16 groups – Tag/untag on per port basis • Secures and segregates network traffic – Supports a full range of VLAN IDs (4096) • Advanced switch features – IEEE 802.1d Spanning Tree Protocol support – Programmable rate limiting from 0Mbps to 100Mbps – Broadcast storm protection with % control • Allows redundancy and shape/protect traffic – Resolves loops and permits redundancy – Allocates bandwidth with 32kbps granularity – Guards against denial of service (DoS) attacks • Switch management – Port mirroring/sniffing: 34 MIB counters per port. • Delivers comprehensive remote management capability – Enables complete view of network activity • Multiple register access options – SMI, SPI, and I2C interface to all registers – MII management (MIIM) access to PHY registers • Interfaces with a wide variety of devices – Connects to EEPROM/CPU for un/managed operations – On the fly configuration of switch/PHY parameters • Optimized power modes, packaging, and power supplies – Full-chip hardware power-down, port-based software power save mode. – Lead-free and standard packages available – 1.8V and 2.5V/3.3V or 3.3V only option – Industrial and commercial temperature options. – Available in 128-pin PQFP • Provides packages/power options for each environment – Delivers an average power consumption of