KSZ8051MNL/RNL
10BASE-T/100BASE-TX Automotive
Physical Layer Transceiver
Features
Target Applications
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• AEC-Q100 Qualified for Automotive Applications
• MII Interface Support (KSZ8051MNL)
• RMII v1.2 Interface Support with a 50 MHz Reference Clock Output to MAC, and an Option to
Input a 50 MHz Reference Clock (KSZ8051RNL)
• Back-to-Back Mode Support for a 100 Mbps Copper Repeater
• MDC/MDIO Management Interface for PHY Register Configuration
• Programmable Interrupt Output
• LED Outputs for Link, Activity, and Speed Status
Indication
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Power-Down and Power-Saving Modes
• LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 32-pin 5 mm x 5 mm QFN Package
• Automotive In-Vehicle Networking
2018 Microchip Technology Inc.
DS00002310B-page 1
KSZ8051MNL/RNL
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00002310B-page 2
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 15
4.0 Register Descriptions .................................................................................................................................................................... 34
5.0 Operational Characteristics ........................................................................................................................................................... 44
6.0 Electrical Characteristics ............................................................................................................................................................... 45
7.0 Timing Diagrams ........................................................................................................................................................................... 47
8.0 Reset Circuit ................................................................................................................................................................................. 56
9.0 Reference Circuits — LED Strap-In Pins ...................................................................................................................................... 57
10.0 Reference Clock - Connection and Selection ............................................................................................................................. 58
11.0 Magnetic - Connection and Selection ......................................................................................................................................... 59
12.0 Package Outline .......................................................................................................................................................................... 61
Appendix A: Data Sheet Revision History ........................................................................................................................................... 62
The Microchip Web Site ...................................................................................................................................................................... 63
Customer Change Notification Service ............................................................................................................................................... 63
Customer Support ............................................................................................................................................................................... 63
Product Identification System ............................................................................................................................................................. 64
2018 Microchip Technology Inc.
DS00002310B-page 3
KSZ8051MNL/RNL
1.0
INTRODUCTION
1.1
General Description
The KSZ8051 is an AEC-Q100 standard qualified single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver.
The KSZ8051 is a highly integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core.
The KSZ8051MNL offers the Media Independent Interface (MII) and the KSZ8051RNL offers the Reduced Media Independent Interface (RMII) for direct connection with MII-/RMII-compliant Ethernet MAC processors and switches.
A 25 MHz crystal is used to generate all required clocks, including the 50 MHz RMII reference clock output for the
KSZ8051RNL.
The KSZ8051 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8051 I/Os and the board. Microchip
LinkMD® TDR-based cable diagnostics identify faulty copper cabling.
The KSZ8051MNL and KSZ8051RNL are available in 32-pin, lead-free QFN packages.
SYSTEM BLOCK DIAGRAM
10/100Mbps
MII/RMII MAC
MII/RMII
ON-CHIP TERMINATION
RESISTORS
MDC/MDIO
MANAGEMENT
KSZ8051MNL/
KSZ8051RNL
50MHz
(KSZ8051RNLU)
REF_CLK
MAGNETICS
FIGURE 1-1:
RJ-45
CONNECTOR
MEDIA TYPES:
10BASE-T
100BASE-TX
XI
XO
25MHz
XTAL
22pF
DS00002310B-page 4
22pF
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
PIN DESCRIPTION AND CONFIGURATION
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8051MNL (TOP VIEW)
RST#
LED1/SPEED
LED0/NWAYEN
CRS/CONFIG1
COL/CONFIG0
TXD3
TXD2
FIGURE 2-1:
TXD1
2.0
32 31 30 29 28 27 26 25
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
1
24
2
23
6
19
TXP
XO
7
18
8
17
22
4
Paddle
Ground
5
(on bottom of chip)
10 11 12 13 14
TABLE 2-1:
20
RXDV/CONFIG2
VDDIO
15 16
XI
REXT
MDIO
MDC
RXD3/PHYAD0
RXD2/PHYAD1
RXD1/PHYAD2
9
21
RXD0/DUPLEX
3
TXD0
TXEN
TXC
INTRP/NAND_Tree#
RXER/ISO
RXC/B-CAST_OFF
SIGNALS - KSZ8051MNL
Pin
Number
Pin
Name
Type
Note
2-1
1
GND
GND
2
VDD_1.2
P
1.2V core VDD (power supplied by KSZ8051MNL)
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (– differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (– differential)
2018 Microchip Technology Inc.
Description
Ground.
DS00002310B-page 5
KSZ8051MNL/RNL
TABLE 2-1:
SIGNALS - KSZ8051MNL (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback for 25 MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
9
XI
I
Crystal/Oscillator/External Clock input
25 MHz ±50 ppm
10
REXT
I
Set PHY transmit output current
Connect a 6.49 kΩ resistor to ground on this pin.
11
MDIO
Ipu/
Opu
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
12
MDC
Ipu
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
13
RXD3/
PHYAD0
14
RXD2/
PHYAD1
15
RXD1/
PHYAD2
Description
Ipu/O
MII mode: MII Receive Data Output[3] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de assertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
Ipd/O
MII mode: MII Receive Data Output[2] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the
deassertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
Ipd/O
MII mode: MII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de assertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
16
RXD0/
DUPLEX
Ipu/O
MII mode: MII Receive Data Output[0] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the deassertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
17
VDDIO
P
18
RXDV/
CONFIG2
19
RXC/
B-CAST_OFF
20
RXER/ISO
DS00002310B-page 6
3.3V, 2.5V, or 1.8V digital VDD
Ipd/O
MII mode: MII Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the deassertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
Ipd/O
MII mode: MII Receive Clock output
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de assertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
Ipd/O
MII mode: MII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the deassertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
TABLE 2-1:
Pin
Number
SIGNALS - KSZ8051MNL (CONTINUED)
Type
Note
2-1
Pin
Name
Description
21
INTRP/
NAND_Tree#
Ipu/
Opu
Interrupt output: Programmable interrupt output
This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
22
TXC
I/O
MII mode: MII Transmit Clock output
MII back-to-back mode: MII Transmit Clock input
23
TXEN
I
MII mode: MII Transmit Enable input
24
TXD0
I
MII mode: MII Transmit Data Input[0] (Note 2-3)
25
TXD1
I
MII mode: MII Transmit Data Input[1] (Note 2-3)
26
TXD2
I
MII mode: MII Transmit Data Input[2] (Note 2-3)
27
TXD3
I
MII Mode: MII Transmit Data Input[3] (Note 2-3)
28
COL/
CONFIG0
29
CRS/
CONFIG1
Ipd/O
MII mode: MII Collision Detect output
Config mode: The pull-up/pull-down value is latched as CONFIG0 at the deassertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
Ipd/O
MII mode: MII Carrier Sense output
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the deassertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
LED output: Programmable LED0 output
Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the
de-assertion of reset.
See the Strap-In Options - KSZ8051MNL section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined
as follows.
LED Mode = [00]
30
LED0/
NWAYEN
Ipu/O
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED Mode = [01]
LED Mode = [10], [11]: Reserved
2018 Microchip Technology Inc.
DS00002310B-page 7
KSZ8051MNL/RNL
TABLE 2-1:
Pin
Number
SIGNALS - KSZ8051MNL (CONTINUED)
Pin
Name
Type
Note
2-1
Description
LED output: Programmable LED1 output
Config mode: Latched as Speed (register 0h, bit [13]) at the de-assertion of
reset.
See the Strap-In Options - KSZ8051MNL section for details.
The LED1 pin is programmable using register 1Fh bits [5:4], and is defined as
follows.
LED mode = [00]
31
LED1/SPEED
Ipu/O
Speed
Pin State
LED Definition
10BASE-T
High
OFF
100BASE-TX
Low
ON
Activity
Pin State
LED Definition
No activity
High
OFF
Activity
Toggle
Blinking
LED mode = [01]
LED mode = [10], [11]: Reserved
32
RST#
Ipu
PADDLE
GND
GND
Chip reset (active low)
Ground
Note 2-1
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
Note 2-2
MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0]
presents valid data to the MAC.
Note 2-3
MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]
presents valid data from the MAC.
DS00002310B-page 8
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-2:
STRAP-IN OPTIONS - KSZ8051MNL
Pin Number
Pin Name
Type
Note 2-4
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
13
PHYAD0
Ipu/O
18
CONFIG2
29
CONFIG1
28
20
31
16
30
19
21
Note 2-4
SPEED
DUPLEX
NWAYEN
B-CAST_OFF
PHYAD[2:0] is latched at de-assertion of reset and is configurable to
any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
CONFIG[2:0] Mode
Ipd/O
CONFIG0
ISO
Description
000
MII (default)
110
MII back-to-back
001 – 101,
111
Reserved, not used
Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
Ipu/O
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into register 0h,
bit [13] as the speed select, and also is latched into register 4h (autonegotiation advertisement) as the speed capability support.
Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
NAND Tree Mode:
Pull-up (default) = Disable
NAND_Tree#
Ipu/Opu
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up and output with internal pull-up.
2018 Microchip Technology Inc.
DS00002310B-page 9
KSZ8051MNL/RNL
TXD1
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8051RNL (TOP VIEW)
RST#
LED1/SPEED
LED0/NWAYEN
CONFIG1
CONFIG0
NC
NC
FIGURE 2-2:
32 31 30 29 28 27 26 25
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
1
24
2
23
6
19
TXP
XO
7
18
8
17
22
4
Paddle
Ground
5
(on bottom of chip)
10 11 12 13 14
TABLE 2-3:
20
CRS_DV/CONFIG2
VDDIO
15 16
XI
REXT
MDIO
MDC
PHYAD0
PHYAD1
RXD1/PHYAD2
9
21
RXD0/DUPLEX
3
TXD0
TXEN
NC
INTRP/NAND_Tree#
RXER/ISO
REF_CLK/B-CAST_OFF
SIGNALS - KSZ8051RNL
Pin
Number
Pin Name
Type
Note 2-1
1
GND
GND
2
VDD_1.2
P
1.2V core VDD (power supplied by KSZ8091RNB)
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (– differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (– differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback for 25 MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
9
XI
I
25 MHz Mode: 25 MHz ±50 ppm Crystal/Oscillator/External Clock Input
50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input
10
REXT
I
Set PHY transmit output current
Connect a 6.49 kΩ resistor to ground on this pin.
DS00002310B-page 10
Description
Ground.
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
TABLE 2-3:
SIGNALS - KSZ8051RNL (CONTINUED)
Pin
Number
Pin Name
11
MDIO
12
MDC
Ipu
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of
reset.
See the Strap-In Options - KSZ8051RNL section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of
reset.
See the Strap-In Options - KSZ8051RNL section for details.
15
RXD1/
PHYAD2
Ipd/O
RMII mode: RMII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
16
RXD0/
DUPLEX
Ipu/O
RMII mode: RMII Receive Data Output[0] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the deassertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
17
VDDIO
P
18
19
20
Type
Note 2-1
Description
Management Interface (MII) Data I/O
Ipu/Opu This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
CRS_DV/
CONFIG2
REF_CLK/
B-CAST_OFF
RXER/ISO
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
3.3V, 2.5V, or 1.8V digital VDD
Ipd/O
RMII mode: RMII Carrier Sense/Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the deassertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
Ipd/O
RMII mode: 25 MHz mode: This pin provides the 50 MHz RMII reference clock
output to the MAC. See also XI (pin 9).
50 MHz mode: This pin is a no connect. See also XI (pin 9).
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
Ipd/O
RMII mode: RMII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the deassertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
Interrupt output: Programmable interrupt output
This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
Ipu/Opu
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
21
INTRP/
NAND_Tree#
22
NC
23
TXEN
I
RMII Transmit Enable input
24
TXD0
I
RMII Transmit Data Input[0] (Note 2-3)
25
TXD1
I
26
NC
NC
27
NC
NC
28
CONFIG0
2018 Microchip Technology Inc.
—
Ipd/O
No connect – This pin is not bonded and can be left floating.
RMII Transmit Data Input[1] (Note 2-3)
No connect – This pin is not bonded and can be left floating.
No connect – This pin is not bonded and can be left floating.
The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of
reset.
See the Strap-In Options - KSZ8051RNL section for details.
DS00002310B-page 11
KSZ8051MNL/RNL
TABLE 2-3:
SIGNALS - KSZ8051RNL (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
29
CONFIG1
Ipd/O
Description
The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of
reset.
See the Strap-In Options - KSZ8051RNL section for details.
LED output: Programmable LED0 output
Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as
follows.
LED Mode = [00]
30
LED0/
NWAYEN
Ipu/O
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Pin State
LED Definition
LED Mode = [01]
Link
No Link
High
OFF
Link
Low
ON
LED Mode = [10], [11]: Reserved
LED output: Programmable LED1 output
Config mode: Latched as SPEED (Register 0h, bit [13]) at the de-assertion of
reset.
See the Strap-In Options - KSZ8051RNL section for details.
The LED1 pin is programmable using Register 1Fh bits [5:4], and is defined as
follows.
LED Mode = [00]
31
LED1/
SPEED
Ipu/O
Speed
Pin State
LED Definition
10BASE-T
High
OFF
100BASE-TX
Low
ON
Pin State
LED Definition
LED Mode = [01]
Activity
No Activity
High
OFF
Activity
Toggle
Blinking
LED Mode = [10], [11]: Reserved
32
PADDLE
Note 2-1
RST#
Ipu
GND
GND
Chip reset (active low)
Ground
P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
NC = Pin is not bonded to the die.
DS00002310B-page 12
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
Note 2-2
RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
Note 2-3
RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-4:
Pin Number
STRAP-IN OPTIONS - KSZ8051RNL
Pin Name
Type
Note 2-4
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
13
PHYAD0
Ipu/O
18
CONFIG2
29
CONFIG1
28
20
31
16
30
19
SPEED
DUPLEX
NWAYEN
B-CAST_OFF
2018 Microchip Technology Inc.
PHYAD[2:0] is latched at de-assertion of reset and is configurable to
any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
CONFIG[2:0] Mode
Ipd/O
CONFIG0
ISO
Description
001
RMII (default)
101
RMII back-to-back
000, 010 –
Reserved, not used
100, 110, 111
Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
Ipu/O
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [13] as the speed select, and also is latched into Register 4h
(auto-negotiation advertisement) as the speed capability support.
Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
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KSZ8051MNL/RNL
TABLE 2-4:
Pin Number
21
Note 2-4
STRAP-IN OPTIONS - KSZ8051RNL (CONTINUED)
Pin Name
NAND_Tree#
Type
Note 2-4
Ipu/Opu
Description
NAND Tree Mode:
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up and output with internal pull-up.
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2018 Microchip Technology Inc.
KSZ8051MNL/RNL
3.0
FUNCTIONAL DESCRIPTION
The KSZ8051 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8051 supports 10Base-T and 100Base-TX for transmission and reception of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8051MNL offers the Media Independent Interface (MII) and the KSZ8051RNL
offers the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC
processors and switches, respectively.
The MII management bus option gives the MAC processor complete access to the KSZ8051 control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
KSZ8051MNL/RNL is used in this data sheet to refer to both the KSZ8051MNL and the KSZ8051RNL devices.
3.1
3.1.1
10BASE-T/100BASE-TX Transceiver
100BASE-TX TRANSMIT
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 6.49 kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX transmitter.
3.1.2
100BASE-TX RECEIVE
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder.
Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC.
3.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
3.1.4
10BASE-T TRANSMIT
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of
2.5V peak. The 10Base-T signals have harmonic contents that are at least 27 dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
2018 Microchip Technology Inc.
DS00002310B-page 15
KSZ8051MNL/RNL
3.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8051MNL/RNL decodes a data frame. The receive clock is kept active during
idle periods between data receptions.
3.1.6
SQE AND JABBER FUNCTION (10BASE-T ONLY)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed
to test the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the
10Base-T transmitter is re-enabled and COL is de-asserted (returns to low).
3.1.7
PLL CLOCK SYNTHESIZER
The KSZ8051MNL/RNL generates all internal clocks and all external clocks for system timing from an external 25 MHz
crystal, oscillator, or reference clock. For the KSZ8051RNL in RMII 50 MHz clock mode, these clocks are generated
from an external 50 MHz oscillator or system clock.
3.1.8
AUTO-NEGOTIATION
The KSZ8051MNL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
•
•
•
•
Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
If auto-negotiation is not supported or the KSZ8051MNL/RNL link partner is forced to bypass auto-negotiation, then the
KSZ8051MNL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which allows the KSZ8051MNL/RNL to establish a link by listening for a fixed signal protocol in the absence of the autonegotiation advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (register 0h, bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex
is set by register 0h, bit [8].
The auto-negotiation link-up process is shown in Figure 3-1.
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KSZ8051MNL/RNL
FIGURE 3-1:
AUTO-NEGOTIATION FLOW CHART
START AUTO-NEGOTIATION
FORCE LINK SETTING
NO
PARALLEL
OPERATION
YES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
ATTEMPT AUTONEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
3.2
MII Data Interface (KSZ8051MNL Only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8051MNL is configured to MII mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting).
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DS00002310B-page 17
KSZ8051MNL/RNL
3.2.1
MII SIGNAL DEFINITION
Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-1:
MII SIGNAL DEFINITION
MII Signal
Name
Direction with
Respect to PHY,
KSZ8051MNL
Signal
Direction with
Respect to MAC
TXC
Output
Input
Description
Transmit Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data[3:0]
RXC
Output
Input
Receive Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data[3:0]
RXER
Output
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
3.2.1.1
Input or not required Receive Error
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0], and TXER.
TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.1.2
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the
first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is
negated before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
3.2.1.3
Transmit Data[3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted by the PHY
for transmission. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while
TXEN is de-asserted are ignored by the PHY.
3.2.1.4
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10 Mbps mode, RXC is recovered from the line while the carrier is active. When the line is idle or the link is down,
RXC is derived from the PHY’s reference clock.
In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.1.5
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted
until the end of the frame.
In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
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KSZ8051MNL/RNL
3.2.1.6
Receive Data[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
3.2.1.7
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY
can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
3.2.1.8
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
3.2.1.9
Collision Detection (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
3.2.2
MII SIGNAL DIAGRAM
The KSZ8051MNL MII pin connections to the MAC are shown in Figure 3-2.
FIGURE 3-2:
KSZ8051MNL MII INTERFACE
'
KSZ8051MNL
TXC
TXEN
TXD[3:0]
RXC
2018 Microchip Technology Inc.
MII
Ethernet MAC
TXC
TXEN
TXD[3:0]
RXC
RXDV
RXD[3:0]
RXDV
RXER
RXER
RXD[3:0]
CRS
CRS
COL
COL
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KSZ8051MNL/RNL
3.3
RMII Data Interface (KSZ8051RNL Only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference
clock).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.
3.3.1
RMII - 25 MHZ CLOCK MODE
The KSZ8051RNL is configured to RMII - 25 MHz clock mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 0 (default value) to select 25 MHz clock mode.
3.3.2
RMII - 50 MHZ CLOCK MODE
The KSZ8051RNL is configured to RMII - 50 MHz clock mode after it is powered up or hardware reset with the following:
• An external 50 MHz clock source (oscillator) connected to XI (pin 9).
• The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 1 to select 50 MHz clock mode.
3.3.3
RMII SIGNAL DEFINITION
Table 3-2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
TABLE 3-2:
RMII SIGNAL DEFINITION
RMII Signal
Name
Direction with Respect to
PHY KSZ8051RNL Signal
Direction with
Respect to MAC
REF_CLK
Output (25 MHz clock
mode)/
(50 MHz clock mode)
Input/Input or
Description
Synchronous 50 MHz reference clock for
receive, transmit, and control interface
TXEN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data[1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
Input
Receive Data[1:0]
RXD[1:0]
Output
RXER
Output
3.3.4
Input or not required Receive Error
REFERENCE CLOCK (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0] and
RX_ER.
For 25 MHz clock mode, the KSZ8051RNL generates and outputs the 50 MHz RMII REF_CLK to the MAC at REF_CLK
(pin 19).
For 50 MHz clock mode, the KSZ8051RNL takes in the 50 MHz RMII REF_CLK from the MAC or system board at XI
(pin 9) and leaves the REF_CLK (pin 19) as a no connect.
3.3.5
TRANSMIT ENABLE (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
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2018 Microchip Technology Inc.
KSZ8051MNL/RNL
3.3.6
TRANSMIT DATA[1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for
transmission.
TXD[1:0] is 00 to indicate idle when TXEN is de-asserted. The PHY ignores values other than 00 on TXD[1:0] while
TXEN is de-asserted.
3.3.7
CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)
The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is
detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are
detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the
frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on
RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
3.3.8
RECEIVE DATA[1:0] (RXD[1:0])
RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,
RXD[1:0] transfers two bits of recovered data from the PHY.
RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while
CRS_DV is de-asserted.
3.3.9
RECEIVE ERROR (RXER)
RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a
PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RXER has no effect on the
MAC.
3.3.10
COLLISION DETECTION (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
3.3.11
RMII SIGNAL DIAGRAM
The KSZ8051RNL RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-3. The connections
for 50 MHz clock mode are shown in Figure 3-4.
2018 Microchip Technology Inc.
DS00002310B-page 21
KSZ8051MNL/RNL
FIGURE 3-3:
KSZ8051RNL RMII INTERFACE (25 MHZ CLOCK MODE)
RMII MAC
KSZ8051RNL
CRS_DV
CRS_DV
RXD[1:0]
RXD[1:0]
RXER
RX_ER
TX_EN
TXD[1:0]
TXEN
TXD[1:0]
REF_CLK
XO
REF_CLK
XI
25MHz
XTAL
22pF
FIGURE 3-4:
22pF
KSZ8051RNL RMII INTERFACE (50 MHZ CLOCK MODE)
KSZ8051RNL
RMII MAC
CRS_DV
RXD[1:0]
CRS_DV
RXD[1:0]
RXER
RX_ER
TXEN
TX_EN
TXD[1:0]
TXD[1:0]
REF_CLK
XI
50MHz
OSC
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2018 Microchip Technology Inc.
KSZ8051MNL/RNL
3.4
Back-to-Back Mode – 100 Mbps Copper Repeater
Two KSZ8051MNL/RNL devices can be connected back-to-back to form a 100BASE-TX copper repeater.
FIGURE 3-5:
3.4.1
KSZ8051MNL/RNL TO KSZ8051MNL/RNL BACK-TO-BACK COPPER REPEATER
MII BACK-TO-BACK MODE (KSZ8051MNL ONLY)
In MII back-to-back mode, a KSZ8051MNL interfaces with another KSZ8051MNL to provide a complete 100 Mbps copper repeater solution.
The KSZ8051MNL devices are configured to MII back-to-back mode after power-up or reset with the following:
• Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 110.
• A common 25 MHz reference clock connected to XI (Pin 9) of both KSZ8051MNL devices.
• MII signals connected as shown in Table 3-3.
TABLE 3-3:
MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE (100BASE-TX COPPER
REPEATER)
KSZ8051MNL (100BASE-TX Copper)
[Device 1]
KSZ8051MNL (100BASE-TX Copper)
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
RXDV
18
Output
TXEN
23
Input
RXD3
13
Output
TXD3
27
Input
RXD2
14
Output
TXD2
26
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
RXDV
18
Output
TXD3
27
Input
RXD3
13
Output
TXD2
26
Input
RXD2
14
Output
TXD1
25
Input
RXD1
15
Output
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KSZ8051MNL/RNL
TABLE 3-3:
MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE (100BASE-TX COPPER
REPEATER) (CONTINUED)
KSZ8051MNL (100BASE-TX Copper)
[Device 1]
KSZ8051MNL (100BASE-TX Copper)
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
TXD0
24
Input
RXD0
16
Output
3.4.2
RMII BACK-TO-BACK MODE (KSZ8051RNL ONLY)
In RMII back-to-back mode, a KSZ8051RNL interfaces with another KSZ8051RNL to provide a complete 100 Mbps copper repeater solution.
The KSZ8051RNL devices are configured to RMII back-to-back mode after power-up or reset with the following:
• Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 101.
• A common 50 MHz reference clock connected to XI (pin 9) of both KSZ8051RNL devices.
• RMII signals connected as shown in Table 3-4.
TABLE 3-4:
RMII SIGNAL CONNECTION FOR RMII BACK-TO-BACK MODE (100BASE-TX
COPPER REPEATER)
KSZ8051RNL (100BASE-TX Copper)
[Device 1]
Pin Name
3.5
Pin Number
KSZ8051RNL (100BASE-TX Copper)
[Device 2]
Pin Type
Pin Name
Pin Number
Pin Type
CRSDV
18
Output
TXEN
23
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
CRSDV
18
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
MII Management (MIIM) Interface
The KSZ8051MNL/RNL supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8051MNL/RNL. An external device with MIIM capability is used to read the PHY status and/
or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See the Register Descriptions section.
As the default, the KSZ8051MNL/RNL supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter
is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MNL/RNL device, or write
to multiple KSZ8051MNL/RNL devices simultaneously.
PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF,
pin 19) or software (Register 16h, bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strap-in pins are used to assign a unique PHY address between 0 and 7 to each KSZ8051MNL/RNL
device.
The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock.
Table 3-5 shows the MII management frame format for the KSZ8051MNL/RNL.
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KSZ8051MNL/RNL
TABLE 3-5:
MII MANAGEMENT FRAME FORMAT FOR THE KSZ8051MNL/RNL
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA
Data Bits[15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
3.6
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8051MNL/RNL PHY Register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8051MNL/RNL control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
3.7
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8051MNL/RNL and its link partner. This feature allows the KSZ8051MNL/RNL to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8051MNL/RNL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, bit [13]. MDI and MDI-X mode
is selected by Register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 3-6 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
TABLE 3-6:
MDI/MDI-X PIN DESCRIPTION
MDI
3.7.1
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
2
TX+
1
RX+
TX–
2
RX–
3
6
RX+
3
TX+
RX–
6
TX–
STRAIGHT CABLE
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-6 shows
a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
2018 Microchip Technology Inc.
DS00002310B-page 25
KSZ8051MNL/RNL
FIGURE 3-6:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
1
2
2
TRANSMIT PAIR
RECEIVE PAIR
3
STRAIGHT
CABLE
3
4
4
5
5
6
6
7
7
8
8
RECEIVE PAIR
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
MODULAR CONNECTOR
(RJ-45)
NIC
3.7.2
CROSSOVER CABLE
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-7:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
RECEIVE PAIR
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
CROSSOVER
CABLE
1
RECEIVE PAIR
2
2
3
3
4
4
5
5
6
6
7
7
8
8
TRANSMIT PAIR
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
DS00002310B-page 26
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
3.8
Loopback Mode
The KSZ8051MNL/RNL supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
3.8.1
LOCAL (DIGITAL) LOOPBACK
This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8051MNL/RNL and the
external MAC, and is supported for both speeds (10/100 Mbps) at full-duplex.
The loopback data path is shown in Figure 3-8.
1.
2.
3.
4.
The MII/RMII MAC transmits frames to the KSZ8051MNL/RNL.
Frames are wrapped around inside the KSZ8051MNL/RNL.
The KSZ8051MNL/RNL transmits frames back to the MII/RMII MAC.
Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.
FIGURE 3-8:
LOCAL (DIGITAL) LOOPBACK
KSZ8051MNL/RNL
AFE
PCS
(ANALOG)
(DIGITAL)
MII/
RMII
MII/RMII
MAC
The following programming action and register settings are used for local loopback mode:
For 10/100 Mbps loopback:
Set Register 0h,
Bit [14] = 1
// Enable local loopback mode
Bit [13] = 0/1
// Select 10 Mbps/100 Mbps speed
Bit [12] = 0
// Disable auto-negotiation
Bit [8] = 1
// Select full-duplex mode
3.8.2
REMOTE (ANALOG) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between the KSZ8051MNL/RNL and its link partner, and is supported for 100BASE-TX full-duplex
mode only.
The loopback data path is shown in Figure 3-9.
1.
2.
3.
The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8051MNL/RNL.
Frames are wrapped around inside the KSZ8051MNL/RNL.
The KSZ8051MNL/RNL transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner.
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DS00002310B-page 27
KSZ8051MNL/RNL
FIGURE 3-9:
REMOTE (ANALOG) LOOPBACK
KSZ8051MNL/RNL
RJ-45
AFE
(ANALOG)
PCS
(DIGITAL)
MII/
RMII
CAT-5
(UTP)
RJ-45
100BASE-TX
LINK PARTNER
The following programming steps and register settings are used for remote loopback mode:
1.
Set Register 0h,
Bits [13] = 1 // Select 100 Mbps speed
Bit [12] = 0
// Disable auto-negotiation
Bit [8] = 1
// Select full-duplex mode
Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner.
2.
Set Register 1Fh,
Bit [2] = 1
// Enable remote loopback mode
LinkMD® Cable Diagnostic
3.9
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides
the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as
a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with Register 1Fh,
the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as
the cable differential pair for testing.
3.9.1
USAGE
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
1.
2.
3.
4.
Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
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2018 Microchip Technology Inc.
KSZ8051MNL/RNL
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
5.
Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38.
The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
·
D Dis tan ce to cable fault in meters = 0.38 Register 1Dh, bits[8:0]
Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
3.10
NAND Tree Support
The KSZ8051MNL/RNL provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8051MNL/RNL digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the
nested NAND gates.
The NAND tree test process includes:
•
•
•
•
Enabling NAND tree mode
Pulling all NAND tree input pins high
Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 3-7 and Table 3-8 list the NAND tree pin orders for KSZ8051MNL and KSZ8051RNL, respectively.
TABLE 3-7:
NAND TREE TEST PIN ORDER FOR KSZ8051MNL
Pin Number
Pin Name
NAND Tree Description
11
MDIO
Input
12
MDC
Input
13
RXD3
Input
14
RXD2
Input
15
RXD1
Input
16
RXD0
Input
18
RXDV
Input
19
RXC
Input
20
RXER
Input
21
INTRP
Input
22
TXC
Input
23
TXEN
Input
24
TXD0
Input
25
TXD1
Input
26
TXD2
Input
27
TXD3
Input
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DS00002310B-page 29
KSZ8051MNL/RNL
TABLE 3-7:
Pin Number
Pin Name
NAND Tree Description
30
LED0
Input
31
LED1
Input
28
COL
Input
29
CRS
Output
TABLE 3-8:
3.10.1
NAND TREE TEST PIN ORDER FOR KSZ8051MNL (CONTINUED)
NAND TREE TEST PIN ORDER FOR KSZ8051RNL
Pin Number
Pin Name
NAND Tree Description
11
MDIO
Input
12
MDC
Input
13
PHYAD0
Input
14
PHYAD1
Input
15
RXD1
Input
16
RXD0
Input
18
CRS_DV
Input
19
REF_CLK
Input
20
RXER
Input
21
INTRP
Input
23
TXEN
Input
24
TXD0
Input
25
TXD1
Input
30
LED0
Input
31
LED1
Input
28
CONFIG0
Input
29
CONFIG1
Output
NAND TREE I/O TESTING
Use the following procedure to check for faults on the KSZ8051MNL/RNL digital I/O pin connections to the board:
1.
2.
3.
Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 21) or software (Register 16h,
Bit [5]).
Use board logic to drive all KSZ8051MNL/RNL NAND tree input pins high.
Use board logic to drive each NAND tree input pin, in KSZ8051MNL/RNL NAND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low
to indicate that the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to
high to indicate that the second pin is connected properly.
d) Leave the first pin (MDIO) and the second pin (MDC) low.
e) Toggle the third pin (RXD3/PHYAD0) from high to low, and verify that the CRS/CONFIG1 pin switches from
high to low to indicate that the third pin is connected properly.
f) Continue with this sequence until all KSZ8051MNL/RNL NAND tree input pins have been toggled.
Each KSZ8051MNL/RNL NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or lowto-high to indicate a good connection. If the CRS/CONFIG1 pin fails to toggle when the KSZ8051MNL/RNL input pin
toggles from high to low, the input pin has a fault.
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KSZ8051MNL/RNL
3.11
Power Management
The KSZ8051MNL/RNL incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
3.11.1
POWER-SAVING MODE
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled
by writing a ‘1’ to Register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link).
In this mode, the KSZ8051MNL/RNL shuts down all transceiver blocks, except for the transmitter, energy detect, and
PLL circuits.
By default, power-saving mode is disabled after power-up.
3.11.2
ENERGY-DETECT POWER-DOWN MODE
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8051MNL/RNL transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8051MNL/RNL and its link
partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable
is connected between them.
By default, energy-detect power-down mode is disabled after power-up.
3.11.3
POWER-DOWN MODE
Power-down mode is used to power down the KSZ8051MNL/RNL device when it is not in use after power-up. It is
enabled by writing a ‘1’ to Register 0h, bit [11].
In this mode, the KSZ8051MNL/RNL disables all internal functions except the MII management interface. The
KSZ8051MNL/RNL exits (disables) power-down mode after Register 0h, bit [11] is set back to ‘0’.
3.11.4
SLOW-OSCILLATOR MODE
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow
oscillator when the KSZ8051MNL/RNL device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,
bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8051MNL/RNL device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1.
2.
3.
Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].
Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
3.12
Reference Circuit for Power and Ground Connections
The KSZ8051MNL/RNL is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Figure 3-10 and Table 3-9 for 3.3V VDDIO.
2018 Microchip Technology Inc.
DS00002310B-page 31
KSZ8051MNL/RNL
FIGURE 3-10:
KSZ8051MNL/RNL POWER AND GROUND CONNECTIONS
Ferrite
Bead
`
3
`
22uF
2.2uF
0.1uF
VDD_1.2
2
VDDA_3.3
0.1uF
KSZ8051MNL/RNL
17
3.3V
VDDIO
`
22uF
0.1uF
GND
1
TABLE 3-9:
3.13
Paddle
KSZ8051MNL/RNL POWER PIN DESCRIPTION
Power Pin
Pin Number
Description
VDD_1.2
2
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
VDDA_3.3
3
Connect to board’s 3.3V supply through a ferrite bead.
Decouple with 22 µF and 0.1 µF capacitors to ground.
VDDIO
17
Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22 µF and 0.1 µF capacitors to ground.
Typical Current/Power Consumption
Table 3-10, Table 3-11, and Table 3-12 show typical values for current consumption by the transceiver (VDDA_3.3) and
digital I/O (VDDIO) power pins, and typical values for power consumption by the KSZ8051MNL/RNL device for the indicated nominal operating voltages. These current and power consumption values include the transmit driver current and
on-chip regulator current for the 1.2V core.
TABLE 3-10:
TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Condition
3.3V Transceiver
(VDDA_3.3)
3.3V Digital I/Os
(VDDIO)
Total Chip Power
100BASE-TX Link-up (no traffic)
34 mA
12 mA
152 mW
100BASE-TX Full-duplex @ 100% utilization
34 mA
13 mA
155 mW
10BASE-T Link-up (no traffic)
14 mA
11 mA
82.5 mW
10BASE-T Full-duplex @ 100% utilization
30 mA
11 mA
135 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
14 mA
10 mA
79.2 mW
EDPD mode (Reg. 18h, Bit [11] = 0)
10 mA
10 mA
66 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.77 mA
1.54 mA
17.5 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
2.59 mA
1.51 mA
13.5 mW
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KSZ8051MNL/RNL
TABLE 3-10:
TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Condition
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
TABLE 3-11:
3.3V Transceiver
(VDDA_3.3)
3.3V Digital I/Os
(VDDIO)
Total Chip Power
1.36 mA
0.45 mA
5.97 mW
TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Condition
3.3V Transceiver
(VDDA_3.3)
2.5V Digital I/Os
(VDDIO)
Total Chip Power
100BASE-TX Link-up (no traffic)
34 mA
11 mA
140 mW
100BASE-TX Full-duplex @ 100% utilization
34 mA
12 mA
142 mW
10BASE-T Link-up (no traffic)
15 mA
10 mA
74.5 mW
10BASE-T Full-duplex @ 100% utilization
27 mA
10 mA
114 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
15 mA
10 mA
74.5 mW
EDPD mode (Reg. 18h, Bit [11] = 0)
11 mA
10 mA
61.3 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.55 mA
1.35 mA
15.1 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
2.29 mA
1.34 mA
10.9 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.15 mA
0.29 mA
4.52 mW
TABLE 3-12:
TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Condition
3.3V Transceiver
(VDDA_3.3)
1.8V Digital I/Os
(VDDIO)
Total Chip Power
100BASE-TX Link-up (no traffic)
34 mA
11 mA
132 mW
100BASE-TX Full-duplex @ 100% utilization
34 mA
12 mA
134 mW
10BASE-T Link-up (no traffic)
15 mA
9 mA
65.7 mW
10BASE-T Full-duplex @ 100% utilization
27 mA
9 mA
105 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
15 mA
9 mA
65.7 mW
EDPD mode (Reg. 18h, Bit [11] = 0)
11 mA
9 mA
52.5 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
4.05 mA
1.21 mA
15.5 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
2.79 mA
1.21 mA
11.4 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.65 mA
0.19 mA
5.79 mW
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DS00002310B-page 33
KSZ8051MNL/RNL
4.0
REGISTER DESCRIPTIONS
4.1
Register Map
TABLE 4-1:
REGISTERS SUPPORTED BY KSZ8051MNL/RNL
Register Number (hex)
Description
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Auto-Negotiation Link Partner Next Page Ability
9h
Reserved
10h
Digital Reserved Control
11h
AFE Control 1
12h - 14h
Reserved
15h
RXER Counter
16h
Operation Mode Strap Override
17h
Operation Mode Strap Status
18h
Expanded Control
19h - 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch
Reserved
1Dh
LinkMD Control/Status
1Eh
PHY Control 1
1Fh
PHY Control 2
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KSZ8051MNL/RNL
4.2
Register Descriptions
TABLE 4-2:
Address
REGISTER DESCRIPTIONS
Name
Description
Mode
Note 4-1
Default
Register 0h – Basic Control
0.15
Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC
0
0.14
Loopback
1 = Loopback mode
0 = Normal operation
RW
0
0.13
1 = 100 Mbps
0 = 10 Mbps
Speed Select
This bit is ignored if auto-negotiation is enabled
(Register 0.12 = 1).
RW
Set by the SPEED
strap-in pin.
See the Strap-In
Options KSZ8051MNL section
for details.
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
RW
If enabled, the auto-negotiation result overrides the
settings in Registers 0.13 and 0.8.
Set by the NWAYEN
strap-in pin.
See the Strap-In
Options KSZ8051MNL section
for details.
0.12
Auto-Negotiation Enable
0.11
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is used to exit
power-down mode (Register 0.11 = 1), two softPower-Down
ware reset writes (Register 0.15 = 1) are required.
The first write clears power-down mode; the second write resets the chip and re-latches the pin
strapping pin values.
1 = Electrical isolation of PHY from MII/RMII
0 = Normal operation
0.10
Isolate
0.9
1 = Restart auto-negotiation process
Restart Auto0 = Normal operation.
Negotiation
This bit is self-cleared after a ‘1’ is written to it.
RW
0
RW
Set by the ISO strapin pin.
See the Strap-In
Options KSZ8051MNL section
for details.
RW/SC
0
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
The inverse of the
DUPLEX strap-in pin
value.
See the Strap-In
Options KSZ8051MNL section
for details.
0.7
Collision Test
1 = Enable COL test
0 = Disable COL test
RW
0
0.6:0
Reserved
Reserved
RO
000_0000
1 = T4 capable
0 = Not T4 capable
RO
0
RO
1
Register 1h - Basic Status
1.15
100BASE-T4
1.14
100BASE-TX 1 = Capable of 100 Mbps full-duplex
Full-Duplex
0 = Not capable of 100 Mbps full-duplex
2018 Microchip Technology Inc.
DS00002310B-page 35
KSZ8051MNL/RNL
TABLE 4-2:
Address
REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
Note 4-1
Default
1.13
100BASE-TX 1 = Capable of 100 Mbps half-duplex
Half-Duplex 0 = Not capable of 100 Mbps half-duplex
RO
1
1.12
10BASE-T
Full-Duplex
1 = Capable of 10 Mbps full-duplex
0 = Not capable of 10 Mbps full-duplex
RO
1
1.11
10BASE-T
Half-Duplex
1 = Capable of 10 Mbps half-duplex
0 = Not capable of 10 Mbps half-duplex
RO
1
1.10:7
Reserved
Reserved
RO
000_0
1.6
1 = Preamble suppression
No Preamble
0 = Normal preamble
RO
1
1.5
Auto-Negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
RO
0
1.4
Remote Fault
1 = Remote fault
0 = No remote fault
RO/LH
0
1.3
Auto-Negotiation Ability
1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber
Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
RO/LH
0
1.0
Extended
Capability
1 = Supports extended capability registers
RO
1
Register 2h - PHY Identifier 1
2.15:0
PHY ID
Number
Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). KENDIN ComRO
munication’s OUI is 0010A1 (hex).
0022h
Register 3h - PHY Identifier 2
3.15:10
Assigned to the 19th through 24th bits of the OrgaPHY ID Numnizationally Unique Identifier (OUI). KENDIN Com- RO
ber
munication’s OUI is 0010A1 (hex).
0001_01
3.9:4
Model Number
Six-bit manufacturer’s model number
RO
01_0110
3.3:0
Revision
Number
Four-bit manufacturer’s revision number
RO
Indicates silicon
revision.
Register 4h - Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
0 = No next page capability
RW
0
4.14
Reserved
Reserved
RO
0
4.13
Remote Fault
1 = Remote fault supported
0 = No remote fault
RW
0
4.12
Reserved
Reserved
RO
0
4.11:10
Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW
00
4.9
100BASE-T4
1 = T4 capable
0 = No T4 capability
RO
0
DS00002310B-page 36
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
TABLE 4-2:
Address
4.8
REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
100BASE-TX 1 = 100 Mbps full-duplex capable
Full-Duplex
0 = No 100 Mbps full-duplex capability
Mode
Note 4-1
Default
RW
Set by the SPEED
strap-in pin.
See the Strap-In
Options KSZ8051MNL section
for details.
4.7
100BASE-TX 1 = 100 Mbps half-duplex capable
Half-Duplex 0 = No 100 Mbps half-duplex capability
RW
Set by the SPEED
strap-in pin.
See the Strap-In
Options KSZ8051MNL section
for details.
4.6
10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability
RW
1
4.5
10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability
RW
1
4.4:0
Selector
Field
[00001] = IEEE 802.3
RW
0_0001
Register 5h - Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
RO
0
5.14
Acknowledge
1 = Link code word received from partner
0 = Link code word not yet received
RO
0
5.13
Remote Fault
1 = Remote fault detected
0 = No remote fault
RO
0
5.12
Reserved
Reserved
RO
0
5.11:10
Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO
00
5.9
100BASE-T4
1 = T4 capable
0 = No T4 capability
RO
0
5.8
100BASE-TX 1 = 100 Mbps full-duplex capable
Full-Duplex
0 = No 100 Mbps full-duplex capability
RO
0
5.7
100BASE-TX 1 = 100 Mbps half-duplex capable
Half-Duplex 0 = No 100 Mbps half-duplex capability
RO
0
5.6
10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability
RO
0
5.5
10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability
RO
0
5.4:0
Selector
Field
[00001] = 802.3 after AN completes.
RO
0_0000
Register 6h - Auto-Negotiation Expansion
6.15:5
Reserved
Reserved
RO
0000_0000_000
6.4
Parallel
Detection
Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection
RO/LH
0
6.3
Link Partner
Next Page
Able
1 = Link partner has next page capability
RO
0 = Link partner does not have next page capability
2018 Microchip Technology Inc.
0
DS00002310B-page 37
KSZ8051MNL/RNL
TABLE 4-2:
Address
REGISTER DESCRIPTIONS (CONTINUED)
Mode
Note 4-1
Name
Description
Default
6.2
Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page capabil- RO
ity
1
6.1
Page
Received
1 = New page received
0 = New page not received yet
RO/LH
0
6.0
Link Partner
Auto-Negotiation Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
RO
0
Register 7h - Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next pages will follow
0 = Last page
RW
0
7.14
Reserved
Reserved
RO
0
7.13
Message
Page
1 = Message page
0 = Unformatted page
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
7.11
Toggle
1 = Previous value of the transmitted link code
word equaled logic 1
0 = Logic 0
RO
0
7.10:0
Message
Field
11-bit wide field to encode 2048 messages
RW
000_0000_0001
Register 8h - Link Partner Next Page Ability
8.15
Next Page
1 = Additional next pages will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message
Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Can act on the information
0 = Cannot act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link code word
equal to logic 0
0 = Previous value of transmitted link code word
equal to logic 1
RO
0
8.10:0
Message
Field
11-bit wide field to encode 2048 messages
RO
000_0000_0000
Register 10h – Digital Reserved Control
10.15:5
Reserved
Reserved
RW
0000_0000_000
10.4
PLL Off
1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for EDPD mode
RW
0
10.3:0
Reserved
Reserved
RW
0000
RW
0000_0000_00
Register 11h – AFE Control 1
11.15:6
Reserved
DS00002310B-page 38
Reserved
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
TABLE 4-2:
Address
REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
Note 4-1
Default
11.5
Slow-oscillator mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
Slow-Oscilla- KSZ8051MNL/RNL device is not in use after
tor Mode
power-up.
RW
Enable
1 = Enable
0 = Disable
This bit automatically sets software power-down to
the analog side when enabled.
0
11.4:0
Reserved
RW
0_0000
RO/SC
0000h
Reserved
Register 15h – RXER Counter
15.15:0
RXER
Counter
Receive error counter for symbol error frames
Register 16h – Operation Mode Strap Override
16.15:11
Reserved
Reserved
RW
0000_0
16.10
Reserved
Reserved
RO
0
16.9
BCAST_OFF
Override
1 = Override strap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast.
RW
0
16.8
Reserved
Reserved
RW
0
16.7
MII B-to-B
Override
1 = Override strap-in for MII back-to-back mode
(also set bit 0 of this register to ‘1’)
This bit applies only to KSZ8051MNL.
RW
0
16.6
RMII B-to-B
Override
1 = Override strap-in for RMII back-to-back mode
(also set bit 1 of this register to ‘1’)
This bit applies only to KSZ8051RNL.
RW
0
16.5
NAND Tree
Override
1 = Override strap-in for NAND tree mode
RW
0
16.4:2
Reserved
Reserved
RW
0_00
16.1
RMII
Override
1 = Override strap-in for RMII mode
This bit applies only to KSZ8051RNL.
RW
0
16.0
MII Override
1 = Override strap-in for MII mode
This bit applies only to KSZ8051MNL.
RW
1
RO
—
Register 17h - Operation Mode Strap Status
17.15:13
PHYAD[2:0]
Strap-In Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
17.12:10
Reserved
Reserved
RO
—
17.9
BCAST_OFF
Strap-In
Status
1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast.
RO
—
17.8
Reserved
Reserved
RO
—
2018 Microchip Technology Inc.
DS00002310B-page 39
KSZ8051MNL/RNL
TABLE 4-2:
Address
REGISTER DESCRIPTIONS (CONTINUED)
Mode
Note 4-1
Name
Description
17.7
MII B-to-B
Strap-In
Status
1 = Strap to MII back-to-back mode
This bit applies only to KSZ8051MNL.
RO
—
17.6
RMII B-to-B
Strap-In
Status
1 = Strap to RMII back-to-back mode
This bit applies only to KSZ8051RNL.
RO
—
17.5
NAND Tree
Strap-In
Status
1 = Strap to NAND tree mode
RO
—
17.4:2
Reserved
Reserved
RO
—
17.1
RMII Strap-In 1 = Strap to RMII mode
Status
This bit applies only to KSZ8051RNL.
RO
—
17.0
MII Strap-In
Status
RO
—
1 = Strap to MII mode
This bit applies only to KSZ8051MNL.
Default
Register 18h - Expanded Control
18.15:12
Reserved
Reserved
RW
0000
18.11
EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW
1
18.10
1 = MII output is random latency
0 = MII output is fixed latency
100BASE-TX
For both settings, all bytes of received preamble
Latency
are passed to the MII output.
This bit applies only to the KSZ8051MNL.
RW
0
18.9:7
Reserved
Reserved
RW
00_0
18.6
10BASE-T
Preamble
Restore
1 = Restore received preamble to MII output
0 = Remove all seven bytes of preamble before
sending frame (starting with SFD) to MII output
This bit applies only to the KSZ8051MNL.
RW
0
18.5:0
Reserved
Reserved
RW
00_0001
Register 1Bh – Interrupt Control/Status
1B.15
Jabber Interrupt Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
RW
0
1B.14
Receive
Error Interrupt Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt
RW
0
1B.13
Page
Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
RW
0
1B.12
Parallel
Detect Fault
Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt
RW
0
1B.11
Link Partner
Acknowledge Interrupt Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt
RW
0
DS00002310B-page 40
2018 Microchip Technology Inc.
KSZ8051MNL/RNL
TABLE 4-2:
Address
REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
1B.10
Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt
1B.9
Mode
Note 4-1
Default
RW
0
Remote Fault
1 = Enable remote fault interrupt
Interrupt
0 = Disable remote fault interrupt
Enable
RW
0
1B.8
Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt
RW
0
1B.7
Jabber
Interrupt
1 = Jabber occurred
0 = Jabber did not occur
RO/SC
0
1B.6
Receive
Error
Interrupt
1 = Receive error occurred
0 = Receive error did not occur
RO/SC
0
1B.5
Page
Receive
Interrupt
1 = Page receive occurred
0 = Page receive did not occur
RO/SC
0
1B.4
Parallel
Detect Fault
Interrupt
1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur
RO/SC
0
1B.3
Link Partner
Acknowledge Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur
RO/SC
0
1B.2
Link-Down
Interrupt
1 = Link-down occurred
0 = Link-down did not occur
RO/SC
0
1B.1
Remote Fault 1 = Remote fault occurred
Interrupt
0 = Remote fault did not occur
RO/SC
0
1B.0
Link-Up
Interrupt
RO/SC
0
1 = Link-up occurred
0 = Link-up did not occur
Register 1Dh – LinkMD Control/Status
1D.15
Cable Diagnostic Test
Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled) has
completed and the status information is valid for
read.
RW/SC
0
1D.14:13
Cable Diagnostic Test
Result
[00] = Normal condition
[01] = Open condition has been detected in cable
[10] = Short condition has been detected in cable
[11] = Cable diagnostic test has failed
RO
00
1D.12
Short Cable
Indicator
1 = Short cable (
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