KSZ8061MNX/MNG
10BASE-T/100BASE-TX Physical Layer
Transceiver
Highlights
Features
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Quiet-Wire® Technology to Reduce Line Emissions and Enhance Immunity
• Ultra-Deep Sleep Standby Mode
• AEC-Q100 Grade 2 Automotive
• Quiet-Wire Programmable EMI Filter
• MII Interface with MDC/MDIO Management Interface for Register Configuration
• On-Chip Termination Resistors for the Differential
Pairs
• LinkMD®+ Receive Signal Quality Indicator
• Fast Start-Up and Link
• Ultra-Deep Sleep Standby Mode: CPU or Signal
Detect Activated
• Loopback Modes for Diagnostics
• Programmable Interrupt Output
Target Applications
•
•
•
•
•
Industrial Control
Vehicle On-Board Diagnostics (OBD)
Automotive Gateways
Camera and Sensor Networking
Infotainment
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 1
KSZ8061MNX/MNG
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DS00002038E-page 2
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 13
4.0 Register Descriptions .................................................................................................................................................................... 30
5.0 Operational Characteristics ........................................................................................................................................................... 43
6.0 Electrical Characteristics ............................................................................................................................................................... 44
7.0 Timing Diagrams ........................................................................................................................................................................... 48
8.0 Reset Circuit ................................................................................................................................................................................. 55
9.0 Reference Clock — Connection and Selection ............................................................................................................................. 56
10.0 Magnetic – Connection and Selection ........................................................................................................................................ 57
11.0 Package Outlines ........................................................................................................................................................................ 58
Appendix A: Data Sheet Revision History ........................................................................................................................................... 61
The Microchip Web Site ...................................................................................................................................................................... 63
Customer Change Notification Service ............................................................................................................................................... 63
Customer Support ............................................................................................................................................................................... 63
Product Identification System ............................................................................................................................................................. 64
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 3
KSZ8061MNX/MNG
1.0
INTRODUCTION
1.1
General Description
The KSZ8061MNX/MNG is a single-chip, 10BASE-T/100BASE-TX, Ethernet physical layer transceiver for transmission
and reception of data over unshielded twisted pair (UTP) cable.
The KSZ8061MNX/MNG features Quiet-Wire® internal filtering to reduce line emissions. It is ideal for applications, such
as automotive or industrial networks, where stringent radiated emission limits need to be met. Quiet-Wire can use lowcost unshielded cable, where previously only shielded cable solutions were possible. The KSZ8061MNX/MNG also features enhanced immunity to environmental EM noise.
The KSZ8061MNX/MNG offers the Media Independent Interface (MII) for direct connection with MII-compliant Ethernet
MAC processors and switches.
It is designed to exceed Automotive AEC-Q100 and EMC requirements, and features an extended temperature range
of -40°C to +105°C.
The KSZ8061MNX is supplied in a 32-lead, 5 mm × 5 mm QFN or WQFN package, while the KSZ8061MNG is in a 48lead, 7 mm × 7 mm QFN package.
The KSZ8061RNB and KSZ8061RND devices have an RMII interface and are described in a separate data sheet.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
MII
KSZ8061MN
INTRP
SIGNAL DETECT
XO
MAGNETICS
10/100 Mbps
MII MAC
Quiet-Wire®
FILTERING
MDC/MDIO
MANAGEMENT
UTP CABLE
CONNECTOR
Media Types:
10BASE-T
100BASE-TX
XI
25 MHz
XTAL
DS00002038E-page 4
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
TABLE 2-1:
32-QFN OR WQFN KSZ8061MNX PIN ASSIGNMENT (TOP VIEW)
SIGNALS - KSZ8061MNX (32-PIN PACKAGES)
Pin Number
Name
Type
(Note 2-1)
1
XI
I
Crystal/Oscillator/External Clock Input
25 MHz ±50ppm. This input references the AVDDH power supply.
2
XO
O
Crystal feedback for 25-MHz crystal
This pin is a no connect if oscillator or external clock source is used.
3
AVDDH
Pwr
3.3V supply for analog TX drivers and XI/XO oscillator circuit
4
TXP
I/O
Physical transmit or receive signal (+ differential)
Transmit when in MDI mode, Receive when in MDI-X mode
5
TXM
I/O
Physical transmit or receive signal (‒ differential)
Transmit when in MDI mode, Receive when in MDI-X mode
6
RXP
I/O
Physical receive or transmit signal (+ differential)
Receive when in MDI mode, Transmit when in MDI-X mode
7
RXM
I/O
Physical receive or transmit signal (‒ differential)
Receive when in MDI mode, Transmit when in MDI-X mode
8
AVDDL
Pwr
1.2V (nominal) supply for analog core
9
VDDL
Pwr
1.2V (nominal) supply for digital core
Description
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 5
KSZ8061MNX/MNG
TABLE 2-1:
SIGNALS - KSZ8061MNX (32-PIN PACKAGES) (CONTINUED)
Pin Number
Name
Type
(Note 2-1)
Description
10
MDIO
Ipu/Opu
Management Interface (MIIM) Data I/O
This pin has a weak pull-up, is open-drain like, and requires an external
1.0-kΩ pull-up resistor.
11
MDC
Ipu
12
RXER/QWF
Ipd/O
MII Receive Error Output
Config mode: The pull-up or pull-down value is latched as QWF at the
deassertion of reset. See Table 2-2 for details.
13
RXDV/
CONFIG2
Ipd/O
MII Receive Data Valid Output
Config mode: The pull-up or pull-down value is latched as CONFIG2 at
the deassertion of reset. See Table 2-2 for details.
14
RXD3/
PHYAD0
Ipu/O
MII Receive Data Output[3] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as PHYADDR[0]
at the deassertion of reset. See Table 2-2 for details.
15
VDDIO
Pwr
16
RXD2/
PHYAD1
Ipd/O
MII Receive Data Output[2] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as PHYADDR[1]
at the deassertion of reset. See Table 2-2 for details.
17
RXD1/
PHYAD2
Ipd/O
MII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as PHYADDR[2]
at the deassertion of reset. See Table 2-2 for details.
18
RXD0/
AUTONEG
Ipu/O
MII Receive Data Output[0] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as AUTONEG at
the deassertion of reset. See Table 2-2 for details.
19
RXC/
CONFIG0
Ipd/O
MII Receive Clock Output
Config mode: The pull-up or pull-down value is latched as CONFIG0 at
the deassertion of reset. See Table 2-2 for details.
20
TXC
O
MII Transmit Clock Output
21
TXEN
I
MII Transmit Enable Input
22
TXD0
I
MII Transmit Data Input[0] (Note 2-3)
23
TXD1
I
MII Transmit Data Input[1] (Note 2-3)
24
LED0
O
LED0 Output
25
TXD2
I
MII Transmit Data Input[2] (Note 2-3)
26
TXD3
I
MII Transmit Data Input[3] (Note 2-3)
27
CRS/
CONFIG1
Ipd/O
28
RESET#
Ipu
Management Interface (MIIM) Clock Input
This clock pin is synchronous to the MDIO data pin.
3.3V, 2.5V, or 1.8V supply for digital I/O
MII Carrier Sense Output
Config mode: The pull-up or pull-down value is latched as CONFIG1 at
the deassertion of reset. See Table 2-2 for details.
Chip Reset (active low)
Programmable Interrupt Output (active low (default) or active high)
This pin has a weak pull-up, is open drain like, and requires an external
1.0-kΩ pull-up resistor.
Config mode: The pull-up or pull-down value is latched as NAND_Tree#
at the deassertion of reset. See Table 2-2 for details.
29
INTRP/
NAND_Tree#
Ipu/O
30
VDDL
Pwr
31
REXT
I
Set PHY transmit output current
Connect a 6.04-kΩ 1% resistor from this pin to ground.
32
SIGDET
O
Signal Detect, active high
Bottom
Paddle
GND
Gnd
DS00002038E-page 6
1.2V (nominal) supply for digital (and analog)
Ground
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
Note 2-1
Pwr = power supply
Gnd = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value)
Ipd = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value)
Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during
power-up or reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value) during
power-up or reset; output pin otherwise.
Ipu/Opu = Input and output with internal pull-up (see Section 6.0, "Electrical Characteristics" for value)
Note 2-2
MII mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents
valid data to the MAC device.
Note 2-3
MII mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] accepts
valid data from the MAC device.
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 7
KSZ8061MNX/MNG
The strap-in pins are latched at the deassertion of reset. In some systems, the MAC MII receive input pins may drive
high or low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
the unintended high or low states. In this case, external pull-up or pull-down resistors (4.7 kΩ) should be added on these
PHY strap-in pins to ensure the intended values are strapped in correctly.
TABLE 2-2:
STRAP-IN OPTIONS - KSZ8061MNX (32-PIN PACKAGES)
Pin Number
Pin Name
Type
(Note 2-1)
17
16
14
RXD1/PHYAD2
RXD2/PHYAD1
RXD3/PHYAD0
Ipd/O
Ipd/O
Ipu/O
Description
The PHY Address is latched at deassertion of reset and is configurable to any value from 0 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the deassertion of
reset.
CONFIG[2:0] Mode
13
27
19
RXDV/CONFIG2
CRS/CONFIG1
RXC/CONFIG0
18
RXD0/
AUTONEG
29
INTRP/
NAND_Tree#
12
Note 2-1
RXER/QWF
Ipd/O
Ipd/O
Ipd/O
000 (default)
MII normal mode; Auto MDI/MDI-X disabled.
001
Reserved, not used.
010
MII normal mode; Auto MDI/MDI-X enabled.
011 - 101
Reserved, not used.
110
MII Back-to-Back; Auto MDI/MDI-X enabled.
111
Reserved, not used.
Ipu/O
Auto-Negotiation Disable
Pull-up (default) = Disable Auto-Negotiation
Pull-down = Enable Auto-Negotiation
At the deassertion of reset, this pin value is inverted, and then
latched into register 0h, bit [12].
Ipu/O
NAND Tree mode
Pull-up (default) = Disable NAND Tree (normal operation)
Pull-down = Enable NAND Tree
At the deassertion of reset, this pin value is latched by the chip.
Ipd/O
Quiet-Wire® Filtering Disable
Pull-up = Disable Quiet-Wire Filtering
Pull-down (default) = Enable Quiet-Wire Filtering
At the deassertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during
power-up or reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value) during
power-up or reset; output pin otherwise.
DS00002038E-page 8
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
48-QFN KSZ8061MNG PIN ASSIGNMENT (TOP VIEW)
SIGDET
REXT
GND
VDDL
INTRP
GND
RESET#
VDDIO
LED1
LED0
CRS
TXD3
FIGURE 2-2:
48 47 46 45 44 43 42 41 40 39 38 37
XI
XO
AVDDH
GND
TXP
TXM
GND
RXP
RXM
GND
GND
AVDDL
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Bottom paddle is GND
GND
TXD2
TXER
VDDIO
TXD1
TXD0
TXEN
TXC
GND
VDDL
RXC
RXD0
GND
VDDL
COL
MDIO
MDC
RXER
RXDV
RXD3
GND
VDDIO
RXD2
RXD1
13 14 15 16 17 18 19 20 21 22 23 24
TABLE 2-3:
SIGNALS - KSZ8061MNG (48-PIN PACKAGE)
Pin Number
Pin Name
Type
(Note 2-1)
1
XI
I
Crystal/Oscillator/External Clock Input
25 MHz ±50 ppm. This input references the AVDDH power supply.
2
XO
O
Crystal feedback for 25-MHz crystal
This pin is a no connect if oscillator or external clock source is used.
3
AVDDH
Pwr
3.3V supply for analog TX drivers and XI/XO oscillator circuit
4
GND
Gnd
Ground
5
TXP
I/O
Physical transmit or receive signal (+ differential)
Description
6
TXM
I/O
Physical transmit or receive signal (‒ differential)
7
GND
Gnd
Ground
8
RXP
I/O
Physical receive or transmit signal (+ differential)
9
RXM
I/O
Physical receive or transmit signal (‒ differential)
10
GND
Gnd
Ground
11
GND
Gnd
Ground
12
AVDDL
Pwr
1.2V (nominal) supply for analog core
13
GND
Gnd
Ground
14
VDDL
Pwr
1.2V (nominal) supply for digital core
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 9
KSZ8061MNX/MNG
TABLE 2-3:
SIGNALS - KSZ8061MNG (48-PIN PACKAGE) (CONTINUED)
Pin Number
Pin Name
Type
(Note 2-1)
15
COL/BCAST_OFF
Ipd/O
16
MDIO
Ipu/Opu
17
MDC
Ipu
18
RXER/QWF
Ipd/O
MII Receive Error Output
Config mode: The pull-up or pull-down value is latched as QWF at the
deassertion of reset. See Table 2-4 for details.
19
RXDV/
CONFIG2
Ipd/O
MII Receive Data Valid Output
Config mode: The pull-up or pull-down value is latched as CONFIG2 at
the deassertion of reset. See Table 2-4 for details.
20
RXD3/PHYAD0
Ipu/O
MII Receive Data Output[3] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as PHYADDR[0]
at the deassertion of reset. See Table 2-4 for details.
21
GND
Gnd
Ground
22
VDDIO
Pwr
3.3V, 2.5V, or 1.8V supply for digital I/O
23
RXD2/PHYAD1
Ipd/O
MII Receive Data Output[2] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as PHYADDR[1]
at the deassertion of reset. See Table 2-4 for details.
24
RXD1/PHYAD2
Ipd/O
MII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as PHYADDR[2]
at the deassertion of reset. See Table 2-4 for details.
25
RXD0/
DUPLEX
Ipu/O
MII Receive Data Output[0] (Note 2-2)
Config mode: The pull-up or pull-down value is latched as DUPLEX at
the deassertion of reset. See Table 2-4 for details.
26
RXC/CONFIG0
Ipd/O
MII Receive Clock Output
Config mode: The pull-up or pull-down value is latched as CONFIG0 at
the deassertion of reset. See Table 2-4 for details.
27
VDDL
Pwr
28
GND
Gnd
29
TXC
O
MII Transmit Clock Output
30
TXEN
I
MII Transmit Enable Input
31
TXD0
I
MII Transmit Data Input[0] (Note 2-3)
Description
MII Collision Detect Output
Config mode: The pull-up or pull-down value is latched as
B-CAST_OFF at the deassertion of reset. See Table 2-4 for details.
Management Interface (MIIM) Data I/O
This pin has a weak pull-up, is open-drain like, and requires an external
1.0-kΩ pull-up resistor.
Management Interface (MIIM) Clock Input
This clock pin is synchronous to the MDIO data pin.
1.2V (nominal) supply for digital core
Ground
32
TXD1
I
33
VDDIO
Pwr
3.3V, 2.5V, or 1.8V supply for digital I/O
34
TXER
Ipd
MII Transmit Error Input
If the MAC does not provide a TXER output signal, this pin may be
unconnected.
35
TXD2
I
36
GND
Gnd
37
TXD3
I
38
CRS/CONFIG1
DS00002038E-page 10
Ipd/O
MII Transmit Data Input[1] (Note 2-3)
MII Transmit Data Input[2] (Note 2-3)
Ground
MII Transmit Data Input[3] (Note 2-3)
MII Carrier Sense Output
Config mode: The pull-up or pull-down value is latched as CONFIG1 at
the deassertion of reset. See Table 2-4 for details.
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
TABLE 2-3:
Pin Number
39
SIGNALS - KSZ8061MNG (48-PIN PACKAGE) (CONTINUED)
Pin Name
LED0/
AUTONEG
Type
(Note 2-1)
Description
Ipu/O
LED0
Active low. Its function is programmable; by default it indicates link/
activity.
Config mode: The pull-up or pull-down value is latched as AUTONEG at
the deassertion of reset. See Table 2-4 for details.
LED1
Active low. Its function is programmable; by default it indicates link
speed.
Config mode: The pull-up or pull-down value is latched as SPEED at
the deassertion of reset. See Table 2-4 for details.
40
LED1/SPEED
Ipu/O
41
VDDIO
Pwr
42
RESET#
Ipu
Chip Reset (active low)
43
GND
Gnd
Ground
Programmable Interrupt Output [active low (default) or active high]
This pin has a weak pull-up, is open drain like, and requires an external
1.0-kΩ pull-up resistor.
Config mode: The pull-up or pull-down value is latched as NAND_Tree#
at the deassertion of reset. See Table 2-4 for details.
44
INTRP/
NAND_Tree#
Ipu/O
45
VDDL
Pwr
46
GND
Gnd
3.3V, 2.5V, or 1.8V supply for digital I/O
1.2V (nominal) supply for digital (and analog)
Ground
47
REXT
I
Set PHY transmit output current.
Connect a 6.04-kΩ 1% resistor from this pin to ground.
48
SIGDET
O
Signal Detect, active high
Bottom
Paddle
GND
Gnd
Ground
Note 2-1
Pwr = power supply
Gnd = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value)
Ipd = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value)
Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
Ipu/Opu = Input and output with internal pull-up (see Section 6.0, "Electrical Characteristics" for value)
Note 2-2
MII mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents
valid data to the MAC device.
Note 2-3
MII mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] accepts
valid data from the MAC device.
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 11
KSZ8061MNX/MNG
The strap-in pins are latched at the deassertion of reset. In some systems, the MAC MII receive input pins may drive
high or low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
the unintended high or low states. In this case, external pull-ups or pull-down resistors (4.7 kΩ) should be added on
these PHY strap-in pins to ensure the intended values are strapped in correctly.
TABLE 2-4:
STRAP-IN OPTIONS - KSZ8061MNG (48-PIN PACKAGE)
Pin
Number
Pin Name
Type
(Note 2-1)
24
23
20
RXD1/PHYAD2
RXD2/PHYAD1
RXD3/PHYAD0
Ipd/O
Ipd/O
Ipu/O
Description
The PHY Address is latched at deassertion of reset and is configurable to any value from 0 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the deassertion of reset.
CONFIG[2:0] Mode
19
38
26
RXDV/CONFIG2
CRS/CONFIG1
RXC/CONFIG0
39
LED0/AUTONEG
44
INTRP/
NAND_Tree#
18
40
25
15
Note 2-1
RXER/QWF
LED1/SPEED
RXD0/DUPLEX
COL/
B-CAST_OFF
Ipd/O
Ipd/O
Ipd/O
000 (default)
MII normal mode; Auto MDI/MDI-X disabled.
001
Reserved, not used.
010
MII normal mode; Auto MDI/MDI-X enabled.
011 - 101
Reserved, not used.
110
MII normal mode; Auto MDI/MDI-X enabled.
111
Reserved, not used.
Ipu/O
Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the deassertion of reset, this pin value is latched into register 0h, bit
[12].
Ipu/O
NAND Tree mode
Pull-up (default) = Disable
Pull-down = Enable
At the deassertion of reset, this pin value is latched by the chip.
Ipd/O
Quiet-Wire Filtering Disable
Pull-up = Disable Quiet-Wire Filtering
Pull-down (default) = Enable Quiet-Wire Filtering
At the deassertion of reset, this pin value is latched by the chip.
Ipu/O
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the deassertion of reset, this pin value is latched into register 0h, bit
[13] as the speed select, and also is latched into register 4h (autonegotiation advertisement) as the speed capability support.
Ipu/O
Duplex mode
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the deassertion of reset, this pin value is inverted, and then latched
into register 0h, bit [8].
Ipd/O
Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as a unique PHY address.
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address.
At the deassertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
DS00002038E-page 12
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
3.0
FUNCTIONAL DESCRIPTION
The KSZ8061MN is an integrated Fast Ethernet transceiver that features Quiet-Wire® internal filtering to reduce line
emissions. When Quiet-Wire filtering is disabled, it is fully compliant with the IEEE 802.3 Specification. The KSZ8061
also has a high noise immunity.
On the copper media side, the KSZ8061MN supports 10BASE-T and 100BASE-TX for transmission and reception of
data over a standard CAT-5 or a similar unshielded twisted pair (UTP) cable and HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8061MN offers the Media Independent Interface (MII) for direct connection with
MII-compliant Ethernet MAC processors and switches.
The MII management bus gives the MAC processor complete access to the KSZ8061MN control and status registers.
Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
Auto-negotiation and Auto MDI/MDI-X can be disabled at power-on to significantly reduce initial time to link up.
A signal detect pin (SIGDET) is available to indicate when the link partner is inactive. An option is available for the
KSZ8061MN to automatically enter Ultra-Deep Sleep mode when SIGDET is deasserted. Ultra-Deep Sleep mode may
also be entered by command of the MAC processor. Additional low power modes are available.
3.1
3.1.1
Transceiver
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion that converts the MII data from the MAC into a 125-MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by a precision external resistor on REXT for the 1:1 transformer ratio.
The output signal has a typical rise or fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125-MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the descrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
3.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The scrambler is used to spread the power spectrum of the transmitted signal to reduce EMI and baseline wander. The
descrambler is needed to recover the scrambled signal.
3.1.4
10BASE-T TRANSMIT
The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output 10BASE-T signals with a typical amplitude of 2.5V peak. The 10BASE-T signals have harmonic contents that are at least 27 dB below the fundamental
frequency when driven by an all-ones Manchester-encoded signal.
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KSZ8061MNX/MNG
3.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and
NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at
the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks
onto the incoming signal and the KSZ8061MN decodes a data frame. The receive clock is kept active during idle periods
in between data reception.
3.1.6
SQE AND JABBER FUNCTION (10BASE-T ONLY; NOT SUPPORTED IN 32-PIN PACKAGE)
In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is required
as part of the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the
10BASE-T transmitter is re-enabled and COL is deasserted (returns to low).
3.1.7
PLL CLOCK SYNTHESIZER
The KSZ8061MN generates all internal clocks and all external clocks for system timing from an external 25-MHz crystal,
oscillator, or reference clock.
3.1.8
AUTO-NEGOTIATION
The KSZ8061MN conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification. Autonegotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority:
•
•
•
•
Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
If the KSZ8061MN is using auto-negotiation, but its link partner is not, then the KSZ8061MN sets its operating speed
by observing the signal at its receiver. This is known as parallel detection and allows the KSZ8061MN to establish link
by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. Duplex is set by register 0h, bit [8] because the KSZ8061MN cannot determine duplex by parallel detection.
If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. For
the 48-pin device, these two bits are initialized at power-up or reset by strapping options on pins 40 and 25, respectively.
For the 32-pin device, the default is 100BASE-TX, full-duplex, and there are no strapping options to change this default.
Auto-negotiation is enabled or disabled by hardware pin strapping (AUTONEG) and by software (register 0h, bit [12]).
By default, auto-negotiation is enabled in the 48-pin device after power-up or hardware reset, but it may be disabled by
pulling the LED0 pin low at that time. For the 32-pin device, auto-negotiation is disabled by default, but it may be enabled
by pulling the RXD0 pin low during reset. Afterwards, auto-negotiation can be enabled or disabled by register 0h, bit
[12]. When the link is 10BASE-T or the link partner is using auto-negotiation, and the Ultra-Deep Sleep mode is used,
then the Signal Detect assertion timing delay bit, register 14h bit [1], must be set.
The auto-negotiation link up process is shown in Figure 3-1.
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2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
FIGURE 3-1:
AUTO-NEGOTIATION FLOW CHART
START AUTONEGO TIATIO N
FORCE LINK
SETTING?
NO
PARAL LEL
OPE RA TION
YES
NO
BYP ASS AUTONEGOTIATION
AND S ET LINK MODE
ATTEMPT
AUTONEGOTIATION
LISTEN FOR 100BA SE-TX
IDL ES
LISTEN FOR 10BAS E-T LINK
PULSE S
JOIN FLOW
LINK MODE
SET?
YES
LINK MODE SET
3.2
Quiet-Wire® Filtering
Quiet-Wire is a feature to enhance 100BASE-TX EMC performance by reducing both conducted and radiated emissions
from the TXP/M signal pair. It can be used either to reduce absolute emissions, or to enable replacement of shielded
cable with unshielded cable, all while maintaining interoperability with standard 100BASE-TX devices.
Quiet-Wire filtering is implemented internally, with no additional external components required. It is enabled or disabled
at power-up and reset by a strapping option on the RXER pin. Once the KSZ8061 is powered up, Quiet-Wire can be
disabled by writing to register 16h, bit [12].
The default setting for Quiet-Wire reduces emissions primarily above 60 MHz, with less reduction at lower frequencies.
Several dB of reduction is possible. Signal attenuation is approximately equivalent to increasing the cable length by 10
to 20 meters, thus reducing cable reach by that amount. For applications needing more modest improvement in emissions, the level of filtering can be reduced by writing a series of registers.
3.3
Fast Link-Up
Link-up time is normally determined by the time it takes to complete auto-negotiation. Additional time may be added by
the auto MDI/MDI-X feature. The total link-up time from power-up or cable-connect is typically a second or more.
Fast Link-up mode significantly reduces 100BASE-TX link-up time by disabling both auto-negotiation and auto MDI/
MDI-X, and fixing the TX and RX channels. This is done via the CONFIG[2:0] and AUTONEG strapping options.
Because these are strapping options, fast link-up is available immediately upon power-up. Fast link-up is available only
for 100BASE-TX link speed. To force the link speed to 10BASE-TX requires a register write.
Fast link-up is intended for specialized applications where both link partners are known in advance. The link must also
be known so that the fixed transmit channel of one device connects to the fixed receive channel of the other device, and
vice versa.
If a device in Fast Link-up mode is connected to a normal device (auto-negotiate and auto-MDI/MDI-X), there will be no
problems linking, but the speed advantage of fast link-up will not be realized.
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KSZ8061MNX/MNG
3.4
Internal and External RX Termination
By default, the RX differential pair is internally terminated. This minimizes the board component count by eliminating all
components between the KSZ8061MN and the magnetics (transformer and common mode choke). The KSZ8061MN
has the option to turn off the internal termination and allow the use of external termination. External termination does
increase the external component count, but these external components can be of tighter tolerances than the internal
termination resistors. Enabling or disabling of internal RX termination is controlled by register 14h, bit [2].
If external termination is used in place of the internal termination, it should consist of a 100Ω resistor between RXP and
RXM, with a 0.1 μF or 1 μF capacitor at the midpoint.
3.5
MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• KSZ8061MNG (48-pin package) has full MII:
- Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
- 10-Mbps and 100-Mbps data rates are supported at both half and full duplex.
- Data transmission and reception are independent and belong to separate signal groups.
- Transmit data and receive data are each 4-bit wide, a nibble.
• KSZ8061MNX (32-pin package) has MII-Lite:
- Pin count is 15 pins (no COL signal).
- Full duplex only; half duplex is not supported.
3.5.1
MII SIGNAL DEFINITION
Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-1:
MII SIGNAL
MII Signal Name
Direction
Direction
(with respect to MAC
(KSZ8061MN Signal)
device)
TXC
Output
Input
Description
Transmit Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
TXER
Input
Output
Transmit Error (not implemented)
RXC
Output
Input
Receive Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
RXER
Output
Input or (not required)
Receive Error
3.5.1.1
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection (KSZ8061MNG only)
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. When
the PHY links at 10 Mbps, TXC is 2.5 MHz. When the PHY links at 100 Mbps, TXC is 25 MHz.
3.5.1.2
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC.
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KSZ8061MNX/MNG
3.5.1.3
Transmit Error (TXER)
The TXER symbol error function for the transmitted frame onto the line is not implemented in this device.
3.5.1.4
Transmit Data [3:0] (TXD[3:0])
When TXEN is asserted, TXD[3:0] are the data nibbles accepted by the PHY for transmission. TXD[3:0] is 00 to indicate
idle when TXEN is deasserted. TXD[3:0] transitions synchronously with respect to TXC.
3.5.1.5
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
• In 10-Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or the link is down.
• In 100-Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the
PHY’s reference clock.
When the PHY links at 10 Mbps, RXC is 2.5 MHz. When the PHY links at 100 Mbps, RXC is 25 MHz.
3.5.1.6
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10-Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), 5Dh, and remains
asserted until the end of the frame.
• In 100-Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
3.5.1.7
Receive Data[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
3.5.1.8
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (for example, a coding error that a PHY
is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY. RXER transitions synchronously with respect to RXC.
3.5.1.9
Carrier Sense (CRS)
CRS is asserted and deasserted as follows:
• In 10-Mbps mode, CRS assertion is based on the reception of valid preambles. CRS deassertion is based upon
the reception of an end-of-frame (EOF) marker.
• In 100-Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer deasserts
CRS if IDLE symbols are received without /T/R.
3.5.1.10
Carrier Sense (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY. COL is supported only in the 48-pin
package option. Therefore, the 32-pin package option does not support half duplex. When interfacing the 32-pin device
to a MAC with a COL input, that input should be pulled low.
3.5.2
MII SIGNAL DIAGRAM
The KSZ8061MN MII pin connections to the MAC are shown in Figure 3-2.
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KSZ8061MNX/MNG
FIGURE 3-2:
KSZ8061MN MII INTERFACE
KSZ8061MN
TXC
TXEN
TXD[3:0]
TXC
TXEN
TXD[3:0]
TXER
TXER
RXC
RXC
RXDV
RXD[3:0]
RXER
DS00002038E-page 18
MII
ETHERNET MAC
RXDV
RXD[3:0]
RXER
CRS
CRS
COL
(KSZ8061MNG ONLY)
COL
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KSZ8061MNX/MNG
3.6
Back-to-Back Mode – 100 Mbps Repeater
Two KSZ8061MN devices can be connected back-to-back to form a 100BASE-TX to 100BASE-TX repeater. For testing
purposes, it can also be used to loopback data on the MII bus by physically connecting the MII receive bus to the MII
transmit bus.
FIGURE 3-3:
KSZ8061MN TO KSZ8061MN BACK-TO-BACK REPEATER
RxD
RXP/RXM
TXP/TXM
KSZ8061MN
TxD
XI
25MHz
OSC
XI
TXP/TXM
KSZ8061MN
TxD
RXP/RXM
FIGURE 3-4:
RxD
KSZ8061MN BACK-TO-BACK FOR MII BUS LOOPBACK
RxD
RXP/RXM
TXP/TXM
LINE INTERFACE
3.6.1
KSZ8061MN
TxD
MII INTERFACE
MII BACK-TO-BACK MODE
In MII Back-to-Back mode, a KSZ8061MN interfaces with another KSZ8061MN to provide a complete 100-Mbps
repeater solution. RXC and TXC are not connected; they are both outputs.
The KSZ8061MN devices are configured to MII Back-to-Back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] set to ‘110’
• A common 25-MHz reference clock connected to XI of both KSZ8061MN devices
• MII signals connected as shown in Table 3-2
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KSZ8061MNX/MNG
TABLE 3-2:
MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE
KSZ8061MN (100BASE-TX)
[Device 1]
Pin Name
3.6.2
KSZ8061MN (100BASE-TX)
[Device 1 or 2]
Pin Type
Pin Name
Pin Type
RXDV
Output
TXEN
Input
RXD3
Output
TXD3
Input
RXD2
Output
TXD2
Input
RXD1
Output
TXD1
Input
RXD0
Output
TXD0
Input
TXEN
Input
RXDV
Output
TXD3
Input
RXD3
Output
TXD2
Input
RXD2
Output
TXD1
Input
RXD1
Output
TXD0
Input
RXD0
Output
BACK-TO-BACK MODE AND 10BASE-T
If Back-to-Back mode is used and the line interface is operating at 10BASE-T, it is necessary to also set register 18h bit
[6].
3.7
MII Management (MIIM) Interface
The KSZ8061MN supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface enables an upper-layer device, like a MAC processor, to monitor and control the
state of the KSZ8061MN. An external device with MIIM capability is used to read the PHY status, configure the PHY
settings, or both. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the aforementioned physical connection that allows the external controller
to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Supported registers [0:8] are standard registers, and their functions are defined per
the IEEE 802.3 Specification. The additional registers are provided for expanded functionality. See the Register
Map section for details.
The KSZ8061MN supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The broadcast address is
defined per the IEEE 802.3 Specification, and can be used to write to multiple KSZ8061MN devices simultaneously.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8061MN device.
Table 3-3 shows the MII Management frame format.
TABLE 3-3:
MII MANAGEMENT FRAME FORMAT
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
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KSZ8061MNX/MNG
3.8
LED Output Pins
The LED0 and LED1 pins indicate line status and are intended for driving LEDs. Bits [5:4] in register 1Fh allow the definition of these pins to be changed. The KSZ8061MNX and KSZ8061MNG have different default settings.
On the KSZ8061MNX, the default function for LED0 is Link Status. The KSZ8061MNX does not have an LED1 pin.
On the KSZ8061MNG, the default function for LED0 is Link/Activity and LED1 indicates Link Speed.
• Link Status: The LED indicates that the serial link is up.
• Link/Activity: When the link is up but there is no traffic, the LED is on. When packets are being received or transmitted, the LED blinks.
• Activity: The LED blinks when packets are received or transmitted. It is off when there is no activity.
• Speed: When the link is up, the LED is on to indicate a 100BASE-TX link, and is off to indicate a 10BASE-T link.
3.9
Interrupt (INTRP)
INTRP is an interrupt output signal that may be used to inform the external controller that there has been a status update
to the KSZ8061MN PHY register. This eliminates the need for the processor to poll the PHY for status changes such as
link up or down.
Register 1Bh, bits [15:8] are the interrupt control bits to enable and disable the conditions for asserting the INTRP signal.
Register 1Bh, bits [7:0] are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt
status bits are cleared after reading register 1Bh.
Register 1Fh, bit [9] sets the interrupt level to active high or active low. The default is active low.
3.10
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8061MN and its link partner. This feature allows the KSZ8061MN to use either type of cable to connect
with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from
the link partner and then assigns transmit and receive pairs of the KSZ8061MN accordingly.
Auto MDI/MDI-X is initially either enabled or disabled at a hardware reset by strapping the hardware pin (CONFIG[2:0]).
Afterwards, it can be enabled or disabled by register 1Fh, bit [13]. When Auto MDI/MDI-X is disabled, serial data is normally transmitted on the pin pair TXP/TXM, and data is received on RXP/RXM. However, this may be reversed by writing
to register 1Fh, bit [14].
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 3-4 illustrates how the IEEE 802.3 Standard defines MDI and MDI-X.
TABLE 3-4:
MDI/MDI-X PIN DEFINITION
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
TX+
1
RX+
2
TX-
2
RX-
3
RX+
3
TX+
6
RX-
6
TX-
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KSZ8061MNX/MNG
3.10.1
STRAIGHT CABLE
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Table 3-5 depicts a
typical straight cable connection between a NIC card (MDI device) and a switch, or hub (MDI-X device).
FIGURE 3-5:
3.10.2
TYPICAL STRAIGHT CABLE CONNECTION
CROSSOVER CABLE
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-6 depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-6:
3.11
TYPICAL CROSSOVER CABLE CONNECTION
Loopback Modes
The KSZ8061MN supports the following loopback operations to verify analog and/or digital data paths.
• Local (Digital) Loopback
• Remote (Analog) Loopback
3.11.1
LOCAL (DIGITAL) LOOPBACK MODE
This loopback mode is a diagnostic mode for checking the MII transmit and receive data paths between KSZ8061MN
and external MAC, and is supported for both speeds (10/100 Mbps) at full-duplex.
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KSZ8061MNX/MNG
The loopback data path is shown in Figure 3-7.
1.
2.
3.
MII MAC transmits frames to KSZ8061MN.
Frames are wrapped around inside KSZ8061MN.
KSZ8061MN transmits frames back to MII MAC.
FIGURE 3-7:
LOCAL (DIGITAL) LOOPBACK
KSZ8061MN
AFE
PCS
(ANALOG)
(DIGITAL)
MII
MAC
MII
The following programming steps and register settings are used for Local Loopback mode.
For 10/100 Mbps loopback:
1.
Set Register 0h,
• Bit [14] = 1 // Enable Local Loopback mode
• Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed
• Bit [12] = 0 // Disable Auto-Negotiation
• Bit [8] = 1 // Select full-duplex mode
2. Set Register 1Ch,
• Bit [5] = 1
3.11.2
REMOTE (ANALOG) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between KSZ8061MN and its link partner, and is supported for 100BASE-TX full-duplex mode only.
The loopback data path is shown in Figure 3-8.
1.
2.
3.
Fast Ethernet (100BASE-TX) PHY Link Partner transmits frames to KSZ8061MN.
Frames are wrapped around inside KSZ8061MN.
KSZ8061MN transmits frames back to Fast Ethernet (100BASE-TX) PHY Link Partner.
FIGURE 3-8:
REMOTE (ANALOG) LOOPBACK
KSZ8061MN
RJ-45
AFE
PCS
(ANALOG)
(DIGITAL)
MII
CAT-5
(UTP)
RJ-45
2022 Microchip Technology Inc. and its subsidiaries
100BASE-TX
LINK PARTNER
DS00002038E-page 23
KSZ8061MNX/MNG
The following programming steps and register settings are used for Remote Loopback mode.
1.
Set Register 0h,
• Bit [13] = 1 // Select 100 Mbps speed
• Bit [12] = 0 // Disable Auto-Negotiation
• Bit [8] = 1 // Select full-duplex mode
Or simply auto-negotiate and link up at 100BASE-TX full-duplex mode with link partner.
2.
Set Register 1Fh,
• Bit [2] = 1 // Enable Remote Loopback mode
3.12
LinkMD® Cable Diagnostics
The LinkMD® function utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, and then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides
the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as
a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing the LinkMD Control/Status Register (register 1Dh) and the PHY Control 2 Register (register 1Fh). The latter register is used to disable auto MDI/MDI-X and to select either MDI or MDI-X as the cable differential pair for testing.
A two-step process is used to analyze the cable. The first step uses a small pulse (for short cables), while the second
step uses a larger pulse (for long cables). The steps are shown here:
For short cables:
1.
2.
3.
4.
5.
Write MMD address 1Bh, register 0, bits [7:4] = 0x2. Note that this is the power-up default value.
Write register 13h, bit [15] = 0. Note that this is the power-up default value.
Write register 1Fh. Disable auto MDI/MDI-X in bit [13], and select either MDI or MDI-X in bit [14] to specify the
twisted pair to test.
Write register 1Dh bit [15] = 1 to initiate the LinkMD test.
Read register 1Dh to determine the result of the first step. Bit [15] = 0 indicates that the test is complete. After
that, the result is read in bits [14:12]. Remember the result.
For long cables:
1.
2.
3.
4.
Write MMD address 1Bh, register 0, bits [7:4] = 0x7.
Write register 13h, bit [15] = 1.
Write register 1Dh bit [15] = 1 to initiate the LinkMD test.
Read register 1Dh to determine the result of the first step. Bit [15] = 0 indicates that the test is complete. After
that, the result is read in bits [14:12].
Register 1Dh bits [14:13] indicate the basic result of the test. When an Open or Short condition is reported, the distance
to the open or short is determined from the distance value read from register bits [8:0].
Distance (m) = (count value * 4(ns)/4.8(ns/m)) / 2
When Normal condition is reported, the distance value is not relevant.
If either test reveals a short, then there is a short. If either test reveals an open, then there is an open. If both tests indicate normal, then the cable is normal.
3.13
LinkMD®+ Enhanced Diagnostics: Receive Signal Quality Indicator
The KSZ8061MN provides a receive Signal Quality Indicator (SQI) feature that indicates the relative quality of the
100BASE-TX receive signal. It approximates a signal-to-noise ratio, and is affected by cable length, cable quality, and
environmental EM noise.
The raw SQI value is available for reading at any time from indirect register: MMD 1Ch, register ACh, bits [14:8]. A lower
value indicates better signal quality, while a higher value indicates worse signal quality. Even in a stable configuration
in a low-noise environment, the value read from this register may vary. The value should therefore be averaged by taking
multiple readings. The update interval of the SQI register is 2 µs, so measurements taken more frequently than 2 µs are
DS00002038E-page 24
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
redundant. In a quiet environment, six to ten readings are suggested for averaging. In a noisy environment, individual
readings are unreliable, so a minimum of thirty readings are suggested for averaging. The SQI circuit does not include
any hysteresis.
Table 3-5 lists typical SQI values for various CAT5 cable lengths when linked to a typical 100BASE-TX device in a quiet
environment. In a noisy environment or during immunity testing, the SQI value increases.
TABLE 3-5:
3.14
TYPICAL SQI VALUES
CAT5 Cable Length
Typical SQI Value (MMD 1Ch, Register ACh, Bits [14:8]
10m
2
30m
2
50m
3
80m
3
100m
4
130m
5
NAND Tree Support
The KSZ8061MN provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree is a chain of nested NAND gates in which each KSZ8061MN digital I/O (NAND tree input) pin is an input to one
NAND gate along the chain. At the end of the chain, the CRS pin provides the output for the next NAND gates.
The NAND tree test process includes:
•
•
•
•
Enabling NAND tree mode
Pulling all NAND tree input pins high
Driving low each NAND tree input pin sequentially per the NAND tree pin order
Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 3-6 and Table 3-7 list the NAND tree pin order.
TABLE 3-6:
KSZ8061MNX NAND TREE TEST PIN ORDER
Pin Number
Pin Name
NAND Tree Description
10
MDIO
Input
11
MDC
Input
12
RXER
Input
13
RXDV
Input
14
RXD3
Input
16
RXD2
Input
17
RXD1
Input
18
RXD0
Input
19
RXC
Input
20
TXC
Input
21
TXEN
Input
22
TXD0
Input
23
TXD1
Input
24
LED0
Input
25
TXD2
Input
26
TXD3
Input
29
INTRP
Input
27
CRS
Output
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 25
KSZ8061MNX/MNG
TABLE 3-7:
3.14.1
KSZ8061MNG NAND TREE TEST PIN ORDER
Pin Number
Pin Name
NAND Tree Description
15
COL
Input
16
MDIO
Input
17
MDC
Input
18
RXER
Input
19
RXDV
Input
20
RXD3
Input
23
RXD2
Input
24
RXD1
Input
25
RXD0
Input
26
RXC
Input
29
TXC
Input
30
TXEN
Input
31
TXD0
Input
32
TXD1
Input
34
TXER
Input
35
TXD2
Input
37
TXD3
Input
39
LED0
Input
40
LED1
Input
44
INTRP
Input
38
CRS
Output
NAND TREE I/O TESTING
The following procedure can be used to check for faults on the KSZ8061MN digital I/O pin connections to the board:
1.
2.
3.
Enable NAND tree mode by INTRP pin strapping option.
Use board logic to drive all KSZ8061MN NAND tree input pins high.
Use board logic to drive each NAND tree input pin, per KSZ8061MN NAND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify the CRS pin switch from high to low to indicate that
the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify the CRS pin switch from low to high to indicate that
the second pin is connected properly.
d) Leave the first pin (MDIO) and the second pin (MDC) low.
e) Toggle the third pin (RXD3) from high to low, and verify the CRS pin switch from high to low to indicate that
the third pin is connected properly.
f) Continue with this sequence until all KSZ8061MN NAND tree input pins have been toggled.
Each KSZ8061MN NAND tree input pin must cause the CRS output pin to toggle high-to-low or low-to-high to indicate
a good connection. If the CRS pin fails to toggle when the KSZ8061MN input pin toggles from high to low, the input pin
has a fault.
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2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
3.15
Power Management
The KSZ8061MN offers the following power management modes, which are enabled and disabled by register control.
3.15.1
POWER SAVING MODE
Power Saving mode is used to reduce the transceiver power consumption when the cable is unplugged. This mode does
not interfere with normal device operation. It is enabled by writing a one to register 1Fh, bit [10], and is in effect when
auto-negotiation mode is enabled and cable is disconnected (no link).
In this mode, the KSZ8061MN shuts down all transceiver blocks except for the transmitter, energy detect, and PLL circuits. By default, Power Saving mode is disabled after power-up.
3.15.2
ENERGY DETECT POWER DOWN MODE
Energy Detect Power Down (EDPD) mode is used to further reduce the transceiver power consumption when the cable
is unplugged, relative to Power Saving mode. This mode does not interfere with normal device operation. It is enabled
by writing a zero to register 18h, bit [11], and is in effect when auto-negotiation mode is enabled and cable is disconnected (no link).
EDPD mode can be optionally enhanced with a PLL Off feature, which turns off all KSZ8061MN transceiver blocks,
except for transmitter and energy detect circuits. PLL Off is set by writing a one to register 10h, bit [4].
Further power reduction is achieved by extending the time interval in between transmissions of link pulses while in this
mode. The periodic transmission of link pulses is needed to ensure two link partners in the same low power state and
with auto MDI/MDI-X disabled can wake up when the cable is connected between them. By default, EDPD mode is disabled after power-up.
3.15.3
POWER DOWN MODE
Power Down mode is used to power down the KSZ8061MN when it is not in use after power-up. It is enabled by writing
a one to register 0h, bit [11].
In this mode, the KSZ8061MN disables all internal functions except the MII management interface. The KSZ8061MN
exits (disables) Power Down mode after register 0h, bit [11] is set back to zero.
3.15.4
SLOW OSCILLATOR MODE
Slow Oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 1) and select the on-chip slow
oscillator when the KSZ8061MN is not in use after power-up. It is enabled by writing a one to register 11h, bit [6].
Slow Oscillator mode works in conjunction with Power Down mode to put the KSZ8061MN into a lower power state with
all internal functions disabled, except for the MII management interface. To properly exit this mode and return to normal
PHY operation, use the following programming sequence:
1.
2.
3.
Disable Slow Oscillator mode by writing a zero to register 11h, bit [6].
Disable Power Down mode by writing a zero to register 0h, bit [11].
Initiate software reset by writing a one to register 0h, bit [15].
3.15.5
ULTRA-DEEP SLEEP MODE
Ultra-Deep Sleep mode is used to achieve the lowest possible power consumption while retaining the ability to detect
activity on the Tx/Rx cable pairs, and is intended for achieving negligible battery drain during long periods of inactivity.
It is controlled by several register bits. Ultra-Deep Sleep mode may be entered by writing to a register, or it may be initiated automatically when signal detect (SIGDET) is deasserted. Details are given in the Signal Detect (SIGDET) and
Ultra-Deep Sleep mode section.
In Ultra-Deep Sleep mode, the KSZ8061MN disables all internal functions and I/Os except for the ultra-low power signal
detect circuit and the signal detect pin (SIGDET), which are powered by VDDIO. For the lowest power consumption, the
1.2V supply (VDDL and AVDDL) may be turned off externally. A hardware reset is required to exit Ultra-Deep Sleep
mode.
3.15.6
NON-VOLATILE REGISTERS
Most of the logic circuitry of the KSZ8061MN, including the status and control registers, is powered by the 1.2V supply.
When the 1.2V supply is turned off in Ultra-Deep Sleep mode, the content of the registers is lost. Because of the importance of register 14h and bit [0] of register 13h, which control the various power modes, these bits are duplicated in a
logic block powered by the 3.3V supply. These register bits are therefore “non-volatile” while in Ultra-Deep Sleep mode.
2022 Microchip Technology Inc. and its subsidiaries
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KSZ8061MNX/MNG
To access the non-volatile (3.3V) registers, bit [4] of register 14h must first be set. Otherwise, writes to these registers
modify only the volatile versions of these registers and not the non-volatile versions.
3.16
Signal Detect (SIGDET) and Ultra-Deep Sleep Mode
SIGDET is an output signal that may be used for power reduction, either by directly turning off selected power or by
signaling to a host controller when no signal is detected on the line interface. It is asserted when sufficient energy is
detected on either of the differential pairs, and is deasserted when cable energy is not detected. The signal detection
circuit consumes almost no power from the VDDIO supply, and does not use the 1.2V supply at all.
Ultra-Deep Sleep mode may be entered either automatically in unison with the Signal Detect signal (automatic method),
or manually by setting a register bit (CPU control method).
The signal detect feature and Ultra-Deep Sleep mode are controlled via multiple bits in register 14h:
• Register 14h, bit [6] Ultra-Deep Sleep method: either automatic or CPU control
• Register 14h, bit [5] Manually enter Ultra-Deep Sleep mode when CPU control method is selected
• Register 14h, bit [4] Enable R/W access to non-volatile versions of register 14h and bits [9:8] and [1:0] of register
13h. Set this bit when bit [3] is set.
• Register 14h, bit [3] Enable Ultra-Deep Sleep mode and SIGDET
• Register 14h, bit [1] Extend timing for SIGDET deassertion and entry into Ultra-Deep Sleep mode
• Register 14h, bit [0] SIGDET output polarity
3.16.1
CPU CONTROL METHOD (MIIM INTERFACE)
In the CPU control method, the KSZ8061MN drives the SIGDET signal to the CPU. SIGDET defaults to force high, to
not interfere with PHY initialization by the CPU. At power-on, the KSZ8061MN drives SIGDET high, without consideration of cable energy level. During initialization, the CPU writes data 0x0058 to register 14h.
• Bit [4] enables access to the non-volatile copy of register 14h.
• Enable Ultra-Deep Sleep mode and SIGDET by setting register 14h, bit [3].
• Automatic Ultra-Deep Sleep functionality is disabled by setting register 14h, bit [6].
SIGDET is now enabled and changes state as the cable energy changes. Typically, in response to the deassertion of
SIGDET, the CPU puts KSZ8061MN into Ultra-Deep Sleep mode by setting register 14h, bit [5]. To further reduce power,
the CPU may disable the 1.2V supply to the KSZ8061MN. The KSZ8061MN asserts SIGDET when energy is detected
on the cable. To activate the KSZ8061MN, the CPU enables the 1.2V supply and asserts hardware reset (RESET#) to
the KSZ8061MN. Because the KSZ8061MN has been completely reset, the registers must also be re-initialized.
Alternatively, it is possible to maintain register access during Ultra-Deep Sleep mode by preserving the 1.2V power supply and setting register 13h, bit [0] to enable Slow Oscillator mode. Ultra-Deep Sleep mode can then be exited by writing
to register 14h. The 1.2V supply results in increased power consumption.
3.16.2
AUTOMATIC ULTRA-DEEP SLEEP METHOD
The board may be designed such that the KSZ8061MN SIGDET signal enables the 1.2V power supply to KSZ8061MN.
At power-on, the KSZ8061MN drives SIGDET high, without consideration of cable energy level. During initialization,
CPU writes data 0x001A or 0x0018 to register 14h.
•
•
•
•
Bit [4] enables access to the non-volatile copy of register 14h.
Enable Ultra-Deep Sleep mode and SIGDET by setting register 14h, bit [3].
Automatic Ultra-Deep Sleep functionality is enabled by clearing register 14h, bit [6].
SIGDET timing bit [1] must be set unless the link partner is not using auto-negotiation, auto-MDI/MDI-X is disabled, and the link is at 100 Mbps.
When the KSZ8061MN detects signal loss, it automatically enters Ultra-Deep Sleep mode and deasserts SIGDET.
SIGDET may be used to disable the 1.2V supply. When the KSZ8061MN detects a signal, it asserts SIGDET (which
enables the 1.2V supply) and automatically wakes up. SIGDET may be used to wake up the CPU, which then re-initializes the KSZ8061MN.
Alternatively, a hardware reset (RESET#) brings the KSZ8061MN out of Ultra-Deep Sleep mode. Note that the contents
of register 14h and bits [9:8] and [1:0] of register 13h are preserved during Ultra-Deep Sleep mode, but are lost during
hardware reset.
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KSZ8061MNX/MNG
3.17
Reference Circuit for Power and Ground Connections
The KSZ8061MNX and KSZ8061MNG require a minimum of two supply voltages. 1.2V is required for VDDL and
AVDDL. 3.3V is required for VDDIO and AVDDH. Optionally, VDDIO may be operated at 2.5V or 1.8V.
FIGURE 3-9:
KSZ8061MNX POWER AND GROUND CONNECTIONS
FERRITE
BEAD
3.3V
3
AVDDH
FERRITE
BEAD
8
AVDDL
0.1μF
10μF
3.3V,
2.5V,
OR
1.8V
15 VDDIO
10μF
10μF
0.1μF
KSZ8061MNX
VDDL
0.1μF
9
0.1μF
VDDL 30
1.2V
GND
0.1μF
ePAD
FIGURE 3-10:
3.3V
10μF
KSZ8061MNG POWER AND GROUND CONNECTIONS
FERRITE
BEAD
3
FERRITE
BEAD
AVDDL 12
AVDDH
0.1μF
10μF
3.3V,
2.5V,
OR
1.8V
10μF
0.1μF
VDDL 14
22 VDDIO
0.1μF
KSZ8061MNG
0.1μF
VDDL 27
33 VDDIO
0.1μF
0.1μF
VDDL 45
41 VDDIO
10μF
0.1μF
`
4, 7, 10, 11,
13, 21, 28,
36, 43, 46,
ePAD
2022 Microchip Technology Inc. and its subsidiaries
1.2V
GND
0.1μF
10μF
DS00002038E-page 29
KSZ8061MNX/MNG
4.0
REGISTER DESCRIPTIONS
This chapter describes the various control and status registers (CSRs). All registers follow the IEEE 802.3 (clause
22.2.4) management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition, allowing for addressing of these registers via
the Serial Management Interface (SMI) protocol.
4.1
Register Map
The register space within the KSZ8061MN consists of two distinct areas:
• Standard registers // Direct register access
• MDIO Manageable device (MMD) registers // Indirect register access
TABLE 4-1:
STANDARD REGISTERS
Register Number (hex)
Description
IEEE-Defined Registers
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
9h - Ch
Dh
Auto-Negotiation Link Partner Next Page Ability
Reserved
MMD Access Control Register
Eh
MMD Access Address Data Register
Fh
Reserved
Vendor-Specific Registers
10h
Digital Control
11h
AFE Control 0
12h
AFE Control 1
13h
AFE Control 2
14h
AFE Control 3
15h
RXER Counter
16h
Operation Mode
17h
Operation Mode Strap Status
18h
Expanded Control
19h - 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch
Function Control
1Dh
LinkMD® Control/Status
1Eh
PHY Control 1
1Fh
PHY Control 2
The KSZ8061MN supports the following MMD device addresses and their associated register addresses, which make
up the indirect MMD registers.
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KSZ8061MNX/MNG
TABLE 4-2:
MMD REGISTERS
Device Address (hex)
Register Address (hex)
3Ch
7h
4.2
3Dh
Description
Reserved
Reserved
1Bh
0h
AFED Control
1Ch
ACh
Signal Quality
Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 standard. Within this address space, the first 16 registers (0h to Fh) are defined according to the IEEE Specification, while the remaining 16 registers (10h to 1Fh) are defined specific to the PHY vendor.
TABLE 4-3:
Address
STANDARD REGISTER DESCRIPTION
Name
Description
Mode
(Note 4-1)
Default
RW/SC
0
Register 0h - Basic Control
Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
0.14
Loopback
1 = Loopback mode (MII TX to MII RX. Line side is
disconnected.)
0 = Normal operation
Loopback must be enabled both here and in register 1Ch.
RW
0
0.13
1 = 100 Mbps
0 = 10 Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
Speed Select
At reset, this bit is set by strapping in pin 40 of the
48-pin device. (The 32-pin device has no strapping
option for speed; this bit default is 1.) After reset,
this bit may be overwritten.
RW
1
0.12
AutoNegotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides settings in register 0.13 and 0.8.
RW
Set by AUTONEG
strapping pin.
See Table 2-2 for
details.
0.11
Power Down
1 = Power down mode
0 = Normal operation
If software reset (register 0.15) is used to exit
Power Down mode (register 0.11 = 1), two software
reset writes (register 0.15 = 1) are required. First
write clears Power Down mode; second write
resets chip and re-latches the pin strapping pin values.
RW
0
0.10
Isolate
1 = Electrical isolation of PHY from MII
0 = Normal operation
RW
0
0.9
1 = Restart auto-negotiation process
Restart Auto0 = Normal operation.
Negotiation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC
0
0.15
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 31
KSZ8061MNX/MNG
TABLE 4-3:
STANDARD REGISTER DESCRIPTION (CONTINUED)
Mode
(Note 4-1)
Default
0.8
1 = Full-duplex
0 = Half-duplex
At reset, the duplex mode is set by strapping in pin
Duplex Mode 25 of the 48-pin device. This bit value is the inverse
of the strapping input. (The 32-pin device has no
strapping option for duplex mode.) After reset, this
bit may be overwritten.
RW
1
0.7
1 = Enable COL test
Collision Test 0 = Disable COL test
Note: COL is not supported in the 32-pin package.
RW
0
Reserved
—
RO
000_0000
1 = T4 capable
0 = Not T4 capable
RO
0
Address
0.6:0
Name
Description
Register 1h - Basic Status
1.15
100BASE-T4
1.14
100BASE-TX 1 = Capable of 100 Mbps full-duplex
Full-Duplex
0 = Not capable of 100 Mbps full-duplex
RO
1
1.13
100BASE-TX 1 = Capable of 100 Mbps half-duplex
Half-Duplex 0 = Not capable of 100 Mbps half-duplex
RO
1
1.12
10BASE-T
Full-Duplex
1 = Capable of 10 Mbps full-duplex
0 = Not capable of 10 Mbps full-duplex
RO
1
1.11
10BASE-T
Half-Duplex
1 = Capable of 10 Mbps half-duplex
0 = Not capable of 10 Mbps half-duplex
RO
1
Reserved
—
RO
000_0
1.6
No Preamble
1 = Preamble suppression acceptable
0 = Normal preamble required
RW
1
1.5
AutoNegotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
RO
0
1.4
Remote Fault
1 = Remote fault
0 = No remote fault
RO/LH
0
1.3
AutoNegotiation
Ability
1 = Capable to perform auto-negotiation
0 = Not capable to perform auto-negotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber
Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
RO/LH
0
1.0
Extended
Capability
1 = Supports extended capabilities registers
RO
1
RO
0022h
1.10:7
Register 2h - PHY Identifier 1
2.15:0
PHY ID
Number
Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex)
Register 3h - PHY Identifier 2
3.15:10
PHY ID
Number
Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex)
RO
0001_01
3.9:4
Model
Number
Six bit manufacturer’s model number
RO
01_0111
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2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
TABLE 4-3:
Address
3.3:0
STANDARD REGISTER DESCRIPTION (CONTINUED)
Name
Revision
Number
Description
Four bit manufacturer’s revision number
Mode
(Note 4-1)
Default
RO
Indicates silicon revision
Register 4h - Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
0 = No next page capability
RW
1
4.14
Reserved
—
RO
0
4.13
1 = Remote fault supported
Remote Fault
0 = No remote fault
RW
0
4.12
Reserved
—
RO
0
Pause
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
RW
00
4.9
100BASE-T4
1 = T4 capable
0 = No T4 capability
RO
0
4.8
100BASE-TX 1 = 100 Mbps full-duplex capable
Full-Duplex
0 = No 100 Mbps full-duplex capability
RW
1
4.7
100BASE-TX 1 = 100 Mbps half-duplex capable
Half-Duplex 0 = No 100 Mbps half-duplex capability
RW
1
4.6
10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability
RW
1
4.5
10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability
RW
1
Selector
Field
[00001] = IEEE 802.3
RW
0_0001
4.11:10
4.4:0
Register 5h - Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
RO
0
5.14
Acknowledge
1 = Link code word received from partner
0 = Link code word not yet received
RO
0
5.13
Remote Fault
1 = Remote fault detected
0 = No remote fault
RO
0
5.12
Reserved
—
RO
0
Pause
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
RO
00
5.9
100BASE-T4
1 = T4 capable
0 = No T4 capability
RO
0
5.8
100BASE-TX 1 = 100 Mbps full-duplex capable
Full-Duplex
0 = No 100 Mbps full-duplex capability
RO
0
5.7
100BASE-TX 1 = 100 Mbps half-duplex capable
Half-Duplex 0 = No 100 Mbps half-duplex capability
RO
0
5.5
10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability
RO
0
5.5
10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability
RO
0
Selector
Field
[00001] = IEEE 802.3
RO
0_0001
5.11:10
5.4:0
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 33
KSZ8061MNX/MNG
TABLE 4-3:
Address
STANDARD REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
RO
0000_0000_000
RO/LH
0
Register 6h - Auto-Negotiation Expansion
6.15:5
Reserved
—
6.4
Parallel
Detection
Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection
6.3
Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page capability
RO
0
6.2
Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page capability
RO
1
6.1
Page
Received
1 = New page received
0 = New page not received yet
RO/LH
0
6.0
Link Partner
Auto-Negotiation Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
RO
0
Register 7h - Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
RW
0
7.14
Reserved
—
RO
0
7.13
Message
Page
1 = Message page
0 = Unformatted page
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
7.11
Toggle
1 = Previous value of the transmitted link code
word equaled logic one
0 = Logic zero
RO
0
Message
Field
11-bit wide field to encode 2048 messages
RW
000_0000_0001
7.10:0
Register 8h - Link Partner Next Page Ability
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message
Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
RO
0
Toggle
1 = Previous value of transmitted link code word
equal to logic zero
0 = Previous value of transmitted link code word
equal to logic one
RO
0
Message
Field
—
RO
000_0000_0000
RW
00
8.11
8.10:0
Register Dh - MMD Access Control Register
D.15:14
Function
DS00002038E-page 34
00 = address
01 = data, no post increment
10 = data, post increment on reads and writes
11 = data, post increment on writes only
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
TABLE 4-3:
Address
STANDARD REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
00_0000_000
D.13:5
Reserved
Write as 0, ignore on read
RW
D.4:0
DEVAD
Device address
RW
Register Eh - MMD Access Address Data Register
E.15:0
Address
Data
If D.15:14 = 00, this is MMD DEVAD’s address register.
Otherwise, this is MMD DEVAD’s data register as
indicated by the contents of its address register.
RW
0000_0000_0000_00
00
Register 10h - Digital Control Register
10.15:5
10.4
10.3:0
Reserved
—
RW
0000_0000_000
PLL off in
EDPD Mode
This mode may optionally be combined with EDPD
mode for additional power reduction.
1 = PLL is off in EDPD mode
0 = PLL is on in EDPD mode
RW
0
Reserved
—
RW
0000
Register 11h - AFE Control 0 Register
11.15:7
Reserved
—
RW
0000_0000_0
11.6
Slow
Oscillator
Mode
This mode substitutes the 25-MHz clock with a
slow oscillator clock, to save oscillator power
during power down.
1 = Slow Oscillator mode enabled
0 = Slow Oscillator mode disabled
RW
0
11.5:0
Reserved
—
RW
00_0000
Trim 100BT TX amplitude
Sequence of values:
1000 = maximum amplitude
1001
1010
1011
1100
1101
100BT ampli- 1110
tude
1111
0000 = default
0001
0010
0011
0100
0101
0110
0111 = minimum amplitude
RW
0000
Reserved
RW
0000_0000_0000
RW
0
RW
000_0000_0000_000
Register 12h - AFE Control 1 Register (Note 4-2)
12.15:12
12.11:0
—
Register 13h - AFE Control 2 Register
13.15
LinkMD
Detector
Threshold
Sets the threshold for the LinkMD pulse detector.
Use high threshold with the large LinkMD pulse,
and the low threshold with the small LinkMD pulse.
Also see MMD address 1Bh, register 0h bits [7:4].
1 = Enable high threshold comparator
0 = Disable high threshold comparator
13.14:1
Reserved
—
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 35
KSZ8061MNX/MNG
TABLE 4-3:
Address
13.0
STANDARD REGISTER DESCRIPTION (CONTINUED)
Description
Mode
(Note 4-1)
Default
This mode substitutes the 25-MHz clock with a
slow oscillator clock, to save oscillator power if register access is required during Ultra-Deep Sleep
mode. Note that the 1.2V supply is required if this
mode is used.
1 = Slow Oscillator mode enabled
0 = Slow Oscillator mode disabled
RW
0
Name
Slow
Oscillator
Mode for
Ultra-Deep
Sleep mode
Register 14h - AFE Control 3 Register
14.15:7
Reserved
—
RW
0000_0000_0
14.6
Ultra-Deep
Sleep
Method
1 = CPU Control method. Entry into Ultra-Deep
Sleep mode determined by value of register bit
14.5
0 = Automatic method. Enter into Ultra-Deep Sleep
mode automatically when no cable energy is
detected
RW
0
14.5
1 = Enter into Ultra-Deep Sleep mode
0 = Normal operation
Manual UltraThis bit is used to enter Ultra-Deep Sleep mode
Deep Sleep
when the CPU Control method is selected in bit
mode
14.6. To exit Ultra-Deep Sleep mode, a hardware
reset is required.
RW
0
14.4
NV Register
Access
1 = Enable non-volatile copy of register 14h and
bits [9:8] and [1:0] of register 13h
0 = Disable access to non-volatile registers
When Ultra-Deep Sleep mode is enabled, this bit
must be set to 1.
RW
0
14.3
Ultra-Deep
Sleep mode
and SIGDET
Enable
1 = Ultra-Deep Sleep mode is not enabled (but not
necessarily entered), and SIGDET indicates cable
energy detected
0 = Ultra-Deep Sleep mode is disabled, and SIGDET output signal is forced true.
RW
0
14.2
Disable RX
Internal
Termination
1 = Disable RX internal termination
0 = Enable RX internal termination
[Has no effect on TX internal termination.]
RW
0
RW
0
RW
0
When Ultra-Deep Sleep mode is enabled, this bit
determines the delay from loss of cable energy to
deassertion of SIGDET. When automatic method is
selected for Ultra-Deep Sleep mode, this delay
also applies to powering down.
14.1
14.0
1 = Increased delay. This setting is required to
Signal Detect allow automatic exiting of Ultra-Deep Sleep mode
Deassertion (automatic method) if the link partner auto-negotiaTiming Delay tion is enabled, if auto-MDI/MDI-X is enabled, or if
linking at 10BASE-T.
0 = Minimum delay. When using the Automatic
method for Ultra-Deep Sleep, use this setting only
if the link partner’s auto-negotiation is disabled,
auto-MDI/MDI-X is disabled, and linking is at
100BASE-TX. This setting may also be used for
CPU Control method.
Signal Detect 1 = SIGDET is active low (low = signal detected)
Polarity
0 = SIGDET is active high (high = signal detected)
DS00002038E-page 36
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
TABLE 4-3:
Address
STANDARD REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
RO/SC
0000h
Register 15h - RXER Counter
15.15:0
RXER
Counter
Receive error counter for symbol error frames
Register 16h - Operation Mode
16.15:13
16.12
16.11:0
Reserved
—
RW
000
QWF disable
1 = Disable Quiet-Wire Filtering
0 = Enable Quiet-Wire Filtering
RW
Strapping input at
RXER pin
Reserved
—
RW
0000_0000_0000
RO
—
Register 17h - Operation Mode Strap Status
17.15:13
PHYAD[2:0]
strap-in
status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
17.12:9
Reserved
—
RO
—
17.8
QWF strap-in 1 = Strap to disable Quiet-Wire Filtering
status
0 = Strap to enable Quiet-Wire Filtering
RO
Strapping input at
RXER pin
17.7
MII B-to-B
strap-in
status
1 = Strap to MII Back-to-Back mode
RO
—
17.6
Reserved
—
RO
—
17.5
NAND Tree
strap-in
status
1 = Strap to NAND Tree mode
RO
—
Reserved
—
RO
—
MII strap-in
status
1 = Strap to MII normal mode
RO
—
RW
0000
RW
1
RW
0
RW
00_0
Enable 10BT When in Back-to-Back mode and in 10BASE-T, this
Preamble
bit must be set.
RW
0
Reserved
RW
00_0001
17.4:1
17.0
Register 18h - Expanded Control
18.15:12
18.11
Reserved
—
Energy
1 = Disable Energy Detect Power Down (EDPD)
Detect Power
mode
Down Mode
0 = Enable EDPD mode
disable
18.10
RX PHY
Latency
1 = Variable RX PHY latency with no preamble
suppression
0 = Fixed RX PHY latency with possible suppression of one preamble nibble. There is an 80%
chance of this happening on the first packet
received after link-up. The loss is seen at the MII
interface. Preamble suppression cannot occur
again until after the next link-up.
18.9:7
Reserved
—
18.6
18.5:0
—
2022 Microchip Technology Inc. and its subsidiaries
DS00002038E-page 37
KSZ8061MNX/MNG
TABLE 4-3:
Address
STANDARD REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
Register 1Bh - Interrupt Control/Status
1B.15
Jabber Interrupt Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
RW
0
1B.14
Receive
Error Interrupt Enable
1 = Enable Receive Error Interrupt
0 = Disable Receive Error Interrupt
RW
0
1B.13
Page
Received
Interrupt
Enable
1 = Enable Page Received Interrupt
0 = Disable Page Received Interrupt
RW
0
1B.12
Parallel
Detect Fault
Interrupt
Enable
1 = Enable Parallel Detect Fault Interrupt
0 = Disable Parallel Detect Fault Interrupt
RW
0
1B.11
Link Partner
Acknowledge Interrupt Enable
1 = Enable Link Partner Acknowledge Interrupt
0 = Disable Link Partner Acknowledge Interrupt
RW
0
1B.10
Link Down
Interrupt
Enable
1 = Enable Link Down Interrupt
0 = Disable Link Down Interrupt
RW
0
1B.9
Remote Fault
1 = Enable Remote Fault Interrupt
Interrupt
0 = Disable Remote Fault Interrupt
Enable
RW
0
1B.8
Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
0 = Disable Link Up Interrupt
RW
0
1B.7
Jabber
Interrupt
1 = Jabber occurred
0 = Jabber did not occur
RO/SC
0
1B.6
Receive
Error
Interrupt
1 = Receive Error occurred
0 = Receive Error did not occur
RO/SC
0
1B.5
Page
Receive
Interrupt
1 = Page Receive occurred
0 = Page Receive did not occur
RO/SC
0
1B.4
Parallel
Detect Fault
Interrupt
1 = Parallel Detect Fault occurred
0 = Parallel Detect Fault did not occur
RO/SC
0
1B.3
Link Partner
Acknowledge Interrupt
1 = Link Partner Acknowledge occurred
0 = Link Partner Acknowledge did not occur
RO/SC
0
1B.2
Link Down
Interrupt
1 = Link Down occurred
0 = Link Down did not occur
RO/SC
0
1B.1
Remote Fault 1 = Remote Fault occurred
0 = Remote Fault did not occur
Interrupt
RO/SC
0
1B.0
Link Up
Interrupt
RO/SC
0
RW
0000_0000_00
1 = Link Up occurred
0 = Link Up did not occur
Register 1Ch - Function Control
1C.15:6
Reserved
DS00002038E-page 38
—
2022 Microchip Technology Inc. and its subsidiaries
KSZ8061MNX/MNG
TABLE 4-3:
Address
STANDARD REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
Local Loopback Option
1 = Enable local loopback
0 = Disable local loopback
Local loopback must be enabled both here and in
register 0h.
RW
0
1C.4:2
Reserved
—
RW
1_00
1C.1:0
Reserved
—
RO
00
RW/SC
0
1C.5
®
Register 1Dh - LinkMD Control/Status
1D.15
Cable Diagnostic Test
Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled) has
completed and the status information is valid for
read.
1D.14:13
Cable Diagnostic Test
Result
[00] = normal condition
[01] = open condition has been detected in cable
[10] = short condition has been detected in cable
[11] = cable diagnostic test has failed
RO
00
1D.12
Short Cable
Indicator
1 = Short cable (
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