KSZ8091MNX/RNB
10BASE-T/100BASE-TX
Physical Layer Transceiver
Features
Target Applications
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• MII Interface Support (KSZ8091MNX)
• RMII v1.2 interface support with a 50 MHz reference clock output to MAC, and an option to input
a 50 MHz reference clock (KSZ8091RNB)
• Back-to-Back Mode Support for a 100 Mbps Copper Repeater
• MDC/MDIO Management Interface for PHY Register Configuration
• Programmable Interrupt Output
• LED Outputs for Link and Activity Status Indication, plus speed indication for KSZ8091RNB
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Energy Efficient Ethernet (EEE) Support with
Low-Power Idle (LPI) Mode and Clock Stoppage
(MII Version Only) for 100BASE-TX and Transmit
Amplitude Reduction with 10BASE-Te Option
• Wake-on-LAN (WOL) Support with Either Magic
Packet, Link Status Change, or Robust CustomPacket Detection
• HBM ESD Rating (6 kV)
• Power-Down and Power-Saving Modes
• LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 32-pin 5 mm x 5 mm QFN Package
•
•
•
•
•
•
2016-2019 Microchip Technology Inc.
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DS00002275B-page 1
KSZ8091MNX/RNB
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00002275B-page 2
2016-2019 Microchip Technology Inc.
KSZ8091MNX/RNB
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration ................................................................................................................................................... 5
3.0 Functional Description .................................................................................................................................................................. 15
4.0 Register Descriptions .................................................................................................................................................................... 40
5.0 Operational Characteristics ........................................................................................................................................................... 57
6.0 Electrical Characteristics ............................................................................................................................................................... 58
7.0 Timing Diagrams ........................................................................................................................................................................... 60
8.0 Reset Circuit ................................................................................................................................................................................. 69
9.0 Reference Circuits — LED Strap-In Pins ...................................................................................................................................... 70
10.0 Reference Clock - Connection and Selection ............................................................................................................................. 71
11.0 Magnetic - Connection and Selection ......................................................................................................................................... 72
12.0 Package Outline .......................................................................................................................................................................... 74
Appendix A: Data Sheet Revision History ........................................................................................................................................... 75
The Microchip Web Site ...................................................................................................................................................................... 76
Customer Change Notification Service ............................................................................................................................................... 76
Customer Support ............................................................................................................................................................................... 76
Product Identification System ............................................................................................................................................................. 77
2016-2019 Microchip Technology Inc.
DS00002275B-page 3
KSZ8091MNX/RNB
1.0
INTRODUCTION
1.1
General Description
The KSZ8091 is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8091 is a highly integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs, by integrating a low-noise regulator to supply the 1.2V core, and by offering
a flexible 1.8/2.5/3.3V digital I/O interface.
The KSZ8091MNX offers the Media Independent Interface (MII) and the KSZ8091RNB offers the Reduced Media Independent Interface (RMII) for direct connection with MII/RMII-compliant Ethernet MAC processors and switches.
Energy Efficient Ethernet (EEE) provides further power saving during idle traffic periods and Wake-on-LAN (WOL) provides a mechanism for the KSZ8091 to wake up a system that is in standby power mode.
The KSZ8091 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8091 I/Os and the board. LinkMD®
TDR-based cable diagnostics identify faulty copper cabling.
The KSZ8091MNX and KSZ8091RNB are available in 32-pin, lead-free QFN packages.
SYSTEM BLOCK DIAGRAM
10/100Mbps
MII/RMII MAC
MII/RMII
ON-CHIP TERMINATION
RESISTORS
MDC/MDIO
MANAGEMENT
KSZ8091MNX/
KSZ8091RNB
50MHz
(KSZ8091RNB)
REF_CLK
PME_N
(SYSTEM
POWER
CIRCUIT)
RJ-45
CONNECTOR
MEDIA TYPES:
10BASE-T
100BASE-TX
XI
XO
25MHz
XTAL
22pF
DS00002275B-page 4
MAGNETICS
FIGURE 1-1:
22pF
2016-2019 Microchip Technology Inc.
KSZ8091MNX/RNB
PIN DESCRIPTION AND CONFIGURATION
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091MNX (TOP VIEW)
RST#
TXER
LED0/PME_N1/NWAYEN
CRS/CONFIG1
COL/CONFIG0
TXD3
TXD2
FIGURE 2-1:
TXD1
2.0
32 31 30 29 28 27 26 25
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
1
24
2
23
6
19
TXD0
TXEN
TXC/PME_EN
INTRP/PME_N2/NAND_TREE#
RXER/ISO
RXC/B-CAST_OFF
TXP
XO
7
18
RXDV/CONFIG2
8
17
VDDIO
22
4
PADDLE
GROUND
5
(ON BOTTOM OF CHIP)
10 11 12 13 14
TABLE 2-1:
20
15 16
XI
REXT
MDIO
MDC
RXD3/PHYAD0
RXD2/PHYAD1
RXD1/PHYAD2
9
21
RXD0/DUPLEX
3
SIGNALS - KSZ8091MNX
Pin
Number
Pin
Name
Type
Note
2-1
1
GND
GND
2
VDD_1.2
P
1.2V core VDD (power supplied by KSZ8091MNX)
Decouple with 2.2 μF and 0.1 μF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (– differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
2016-2019 Microchip Technology Inc.
Description
Ground.
DS00002275B-page 5
KSZ8091MNX/RNB
TABLE 2-1:
SIGNALS - KSZ8091MNX (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
6
TXM
I/O
Physical transmit or receive signal (– differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback for 25 MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
9
XI
I
Crystal/Oscillator/External Clock input
25 MHz ±50 ppm
10
REXT
I
Set PHY transmit output current
Connect a 6.49 kΩ resistor to ground on this pin.
11
MDIO
Ipu/
Opu
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
12
MDC
Ipu
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
13
RXD3/
PHYAD0
14
RXD2/
PHYAD1
15
RXD1/
PHYAD2
Description
Ipu/O
MII mode: MII Receive Data Output[3] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de assertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
Ipd/O
MII mode: MII Receive Data Output[2] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the
deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
Ipd/O
MII mode: MII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de assertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
16
RXD0/
DUPLEX
Ipu/O
MII mode: MII Receive Data Output[0] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
17
VDDIO
P
18
RXDV/
CONFIG2
19
RXC/
B-CAST_OFF
20
RXER/ISO
DS00002275B-page 6
3.3V, 2.5V, or 1.8V digital VDD
Ipd/O
MII mode: MII Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
Ipd/O
MII mode: MII Receive Clock output
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de assertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
Ipd/O
MII mode: MII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
2016-2019 Microchip Technology Inc.
KSZ8091MNX/RNB
TABLE 2-1:
Pin
Number
21
SIGNALS - KSZ8091MNX (CONTINUED)
Pin
Name
INTRP/
PME_N2/
NAND_Tree#
Type
Note
2-1
Description
Ipu/
Opu
Interrupt output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status register, for programming the interrupt conditions and
reading the interrupt status. Register 1Fh, bit [9] sets the interrupt output to
active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an external 1.0 kΩ pull-up resistor to VDDIO (digital VDD).
MII mode: MII Transmit Clock output
MII back-to-back mode: No connection
Config mode: The pull-up/pull-down value is latched as PME_EN at the deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
22
TXC/
PME_EN
Ipd/O
23
TXEN
I
MII mode: MII Transmit Enable input
24
TXD0
I
MII mode: MII Transmit Data Input[0] (Note 2-3)
25
TXD1
I
MII mode: MII Transmit Data Input[1] (Note 2-3)
26
TXD2
I
MII mode: MII Transmit Data Input[2] (Note 2-3)
27
TXD3
I
MII Mode: MII Transmit Data Input[3] (Note 2-3)
28
COL/
CONFIG0
29
CRS/
CONFIG1
Ipd/O
MII mode: MII Collision Detect output
Config mode: The pull-up/pull-down value is latched as CONFIG0 at the deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
Ipd/O
MII mode: MII Carrier Sense output
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the deassertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
2016-2019 Microchip Technology Inc.
DS00002275B-page 7
KSZ8091MNX/RNB
TABLE 2-1:
Pin
Number
SIGNALS - KSZ8091MNX (CONTINUED)
Pin
Name
Type
Note
2-1
Description
LED output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1)
In this mode, this pin has a weak pull-up, is an open-drain, and requires an
external 1.0 kΩ pull-up resistor to VDDIO (digital VDD).
Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the
de-assertion of reset.
See the Strap-In Options - KSZ8091MNX section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined
as follows.
LED Mode = [00]
30
LED0/
PME_N1/
NWAYEN
Ipu/O
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED Mode = [01]
LED Mode = [10], [11]: Reserved
31
TXER
Ipd
MII mode: MII Transmit Error input
For EEE mode, this pin is driven by the EEEMAC to pull up this pin for
KSZ8091MNX transmit into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to
KSZ8091MNX and can be left as a no connect.
For NAND Tree testing, this pin should be pulled high by a pull-up resistor.
32
RST#
Ipu
Chip reset (active low)
PADDLE
GND
GND
Ground
Note 2-1
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipd = Input with internal pull-down (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
Note 2-2
MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0]
presents valid data to the MAC.
DS00002275B-page 8
2016-2019 Microchip Technology Inc.
KSZ8091MNX/RNB
Note 2-3
MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]
presents valid data from the MAC.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-2:
Pin Number
STRAP-IN OPTIONS - KSZ8091MNX
Pin Name
Type
Note 2-4
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
13
PHYAD0
Ipu/O
18
CONFIG2
29
CONFIG1
28
CONFIG0
22
20
16
30
19
21
Note 2-4
PME_EN
ISO
DUPLEX
NWAYEN
B-CAST_OFF
Description
PHYAD[2:0] is latched at de-assertion of reset and is configurable to
any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
CONFIG[2:0] Mode
Ipd/O
000
MII (default)
110
MII back-to-back
001 – 101,
111
Reserved, not used
Ipd/O
PME output for Wake-on-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register
16h, bit [15].
Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
NAND Tree Mode:
Pull-up (default) = Disable
NAND_Tree#
Ipu/Opu
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up and output with internal pull-up.
2016-2019 Microchip Technology Inc.
DS00002275B-page 9
KSZ8091MNX/RNB
TXD1
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091RNB (TOP VIEW)
RST#
LED1/SPEED
LED0/PME_N1/NWAYEN
CONFIG1
CONFIG0
NC
NC
FIGURE 2-2:
32 31 30 29 28 27 26 25
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
1
24
2
23
6
19
TXD0
TXEN
PME_EN
INTRP/PME_N2/NAND_TREE#
RXER/ISO
REF_CLK/B-CAST_OFF
TXP
XO
7
18
CRS_DV/CONFIG2
17
VDDIO
3
22
4
PADDLE
GROUND
5
(ON BOTTOM OF CHIP)
21
8
15 16
RXD0/DUPLEX
10 11 12 13 14
XI
REXT
MDIO
MDC
PHYAD0
PHYAD1
RXD1/PHYAD2
9
TABLE 2-3:
20
SIGNALS - KSZ8091RNB
Pin
Number
Pin Name
Type
Note 2-1
1
GND
GND
2
VDD_1.2
P
3
VDDA_3.3
P
4
RXM
I/O
Physical receive or transmit signal (– differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (– differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback for 25 MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
DS00002275B-page 10
Description
Ground.
1.2V core VDD (power supplied by KSZ8091RNB)
Decouple with 2.2 μF and 0.1 μF capacitors to ground.
3.3V analog VDD
2016-2019 Microchip Technology Inc.
KSZ8091MNX/RNB
TABLE 2-3:
SIGNALS - KSZ8091RNB (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
9
XI
I
25 MHz Mode:25 MHz ±50 ppm Crystal/Oscillator/External Clock Input
50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input
10
REXT
I
Set PHY transmit output current
Connect a 6.49 kΩ resistor to ground on this pin.
11
MDIO
12
MDC
Ipu
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of
reset.
See the Strap-In Options - KSZ8091RNB section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of
reset.
See the Strap-In Options - KSZ8091RNB section for details.
15
RXD1/
PHYAD2
Ipd/O
RMII mode: RMII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
16
RXD0/
DUPLEX
Ipu/O
RMII mode: RMII Receive Data Output[0] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the deassertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
17
VDDIO
P
18
CRS_DV/
CONFIG2
19
20
21
REF_CLK/
B-CAST_OFF
RXER/ISO
INTRP/
PME_N2/
NAND_Tree#
Description
Management Interface (MII) Data I/O
Ipu/Opu This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
3.3V, 2.5V, or 1.8V digital VDD
Ipd/O
RMII mode: RMII Carrier Sense/Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the deassertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
Ipd/O
RMII mode: 25 MHz mode: This pin provides the 50 MHz RMII reference clock
output to the MAC. See also XI (pin 9).
50 MHz mode: This pin is a no connect. See also XI (pin 9).
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
Ipd/O
RMII mode: RMII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the deassertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
Interrupt output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status register, for programming the interrupt conditions and
reading the interrupt status. Register 1Fh, bit [9] sets the interrupt output to
active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
Ipu/Opu
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an external 1.0 kΩ pull-up resistor to VDDIO (digital VDD).
2016-2019 Microchip Technology Inc.
DS00002275B-page 11
KSZ8091MNX/RNB
TABLE 2-3:
SIGNALS - KSZ8091RNB (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
22
PME_EN
Ipd/O
23
TXEN
I
RMII Transmit Enable input
24
TXD0
I
RMII Transmit Data Input[0] (Note 2-3)
25
TXD1
I
RMII Transmit Data Input[1] (Note 2-3)
26
NC
NC
No connect – This pin is not bonded and can be left floating.
27
NC
NC
No connect – This pin is not bonded and can be left floating.
28
CONFIG0
Ipd/O
The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of
reset.
See the Strap-In Options - KSZ8091RNB section for details.
29
CONFIG1
Ipd/O
The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of
reset.
See the Strap-In Options - KSZ8091RNB section for details.
Description
The pull-up/pull-down value is latched as PME_EN at the de-assertion of
reset.
See the Strap-In Options - KSZ8091RNB section for details.
LED output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1). In this mode,
this pin has a weak pull-up, is an open-drain, and requires an external 1.0 kΩ
pull-up resistor to VDDIO (digital VDD).
Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNB section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as
follows.
30
LED0/
PME_N1/
NWAYEN
LED Mode = [00]
Ipu/O
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED Mode = [01]
LED Mode = [10], [11]: Reserved
LED output: Programmable LED1 output
Config mode: Latched as SPEED (Register 0h, bit [13]) at the de-assertion of
reset.
See the Strap-In Options - KSZ8091RNB section for details.
The LED1 pin is programmable using Register 1Fh bits [5:4], and is defined as
follows.
LED Mode = [00]
31
LED1/
SPEED
Ipu/O
Speed
Pin State
LED Definition
10BASE-T
High
OFF
100BASE-TX
Low
ON
Activity
Pin State
LED Definition
No Activity
High
OFF
Activity
Toggle
Blinking
LED Mode = [01]
LED Mode = [10], [11]: Reserved
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KSZ8091MNX/RNB
TABLE 2-3:
SIGNALS - KSZ8091RNB (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
32
RST#
Ipu
GND
GND
PADDLE
Description
Chip reset (active low)
Ground
Note 2-1
P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
NC = Pin is not bonded to the die.
Note 2-2
RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
Note 2-3
RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-4:
STRAP-IN OPTIONS - KSZ8091RNB
Pin Number
Pin Name
Type
Note 2-4
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
13
PHYAD0
Ipu/O
18
CONFIG2
29
CONFIG1
22
CONFIG[2:0] Mode
CONFIG0
PME_EN
2016-2019 Microchip Technology Inc.
PHYAD[2:0] is latched at de-assertion of reset and is configurable to
any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
Ipd/O
28
Description
Ipd/O
001
RMII
101
RMII back-to-back
000,
010 – 100,
110, 111
Reserved, not used
PME output for Wake-on-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register
16h, bit [15].
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KSZ8091MNX/RNB
TABLE 2-4:
Pin Number
STRAP-IN OPTIONS - KSZ8091RNB (CONTINUED)
Pin Name
20
31
16
30
19
21
Note 2-4
ISO
SPEED
DUPLEX
NWAYEN
B-CAST_OFF
NAND_Tree#
Type
Note 2-4
Description
Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
Ipu/O
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [13] as the speed select, and also is latched into Register 4h
(auto-negotiation advertisement) as the speed capability support.
Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
Ipu/Opu
NAND Tree Mode:
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up and output with internal pull-up.
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KSZ8091MNX/RNB
3.0
FUNCTIONAL DESCRIPTION
The KSZ8091 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8091 supports 10BASE-T and 100BASE-TX for transmission and reception of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8091MNX offers the Media Independent Interface (MII) and the KSZ8091RNB
offers the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC
processors and switches, respectively.
The MII management bus option gives the MAC processor complete access to the KSZ8091 control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
The KSZ8091MNX/RNB is used to refer to both KSZ8091MNX and KSZ8091RNB versions in this data sheet.
3.1
3.1.1
10BASE-T/100BASE-TX Transceiver
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII/RMII data from the MAC into a 125 MHz
serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The
serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output
current is set by an external 6.49 kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder.
Finally, the NRZ serial data is converted to MII/RMII format and provided as the input data to the MAC.
3.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
3.1.4
10BASE-T TRANSMIT
The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output 10BASE-T signals with a typical amplitude of 2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASET/10BASE-Te signals have harmonic contents that are at least 27 dB below the fundamental frequency when driven by
an all-ones Manchester-encoded signal.
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KSZ8091MNX/RNB
3.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8091MNX/RNB decodes a data frame. The receive clock is kept active
during idle periods between data receptions.
3.1.6
SQE AND JABBER FUNCTION (10BASE-T ONLY)
In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed
to test the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the
10BASE-T transmitter is re-enabled and COL is de-asserted (returns to low).
3.1.7
PLL CLOCK SYNTHESIZER
The KSZ8091MNX/RNB generates all internal clocks and all external clocks for system timing from an external 25 MHz
crystal, oscillator, or reference clock. For the KSZ8091RNB in RMII 50 MHz clock mode, these clocks are generated
from an external 50 MHz oscillator or system clock.
3.1.8
AUTO-NEGOTIATION
The KSZ8091MNX/RNB conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
•
•
•
•
Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
If auto-negotiation is not supported or the KSZ8091MNX/RNB link partner is forced to bypass auto-negotiation, then the
KSZ8091MNX/RNB sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which allows the KSZ8091MNX/RNB to establish a link by listening for a fixed signal protocol in the absence of the autonegotiation advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (Register 0h, bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, bit [13], and the duplex
is set by Register 0h, bit [8].
The auto-negotiation link-up process is shown in Figure 3-1.
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KSZ8091MNX/RNB
FIGURE 3-1:
AUTO-NEGOTIATION FLOW CHART
START AUTO-NEGOTIATION
FORCE LINK SETTING
NO
PARALLEL
OPERATION
YES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
ATTEMPT AUTONEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
3.2
MII Data Interface (KSZ8091MNX Only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8091MNX is configured to MII mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting).
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KSZ8091MNX/RNB
3.2.1
MII SIGNAL DEFINITION
Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-1:
MII SIGNAL DEFINITION
MII Signal
Name
Direction with
Respect to PHY,
KSZ8091MNX
Signal
Direction with
Respect to MAC
TXC
Output
Input
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data[3:0]
TXER
Input
Output or not
implemented
RXC
Output
Input
Receive Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
Description
Transmit Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
Transmit Error
(KSZ8091MNX implements only the EEE function for
this pin. See Transmit Error (TXER) for details.)
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data[3:0]
RXER
Output
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
3.2.1.1
Input or not required Receive Error
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0], and TXER.
TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.1.2
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the
first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is
negated before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
3.2.1.3
Transmit Data[3:0] (TXD[3:0])
When TXEN is asserted, TXD[3:0] are the data nibbles presented by the MAC and accepted by the PHY for transmission.
When TXEN is de-asserted, the MAC drives TXD[3:0] to either 0000 for the idle state (non-EEE mode) or 0001 for the
LPI state (EEE mode).
TXD[3:0] transitions synchronously with respect to TXC.
3.2.1.4
Transmit Error (TXER)
TXER is implemented only for the EEE function.
For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MNX transmit into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to KSZ8091MNX and can be left as a no
connect.
TXER transitions synchronously with respect to TXC.
3.2.1.5
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10 Mbps mode, RXC is recovered from the line while the carrier is active. When the line is idle or the link is down,
RXC is derived from the PHY’s reference clock.
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KSZ8091MNX/RNB
In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.1.6
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted
until the end of the frame.
In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
3.2.1.7
Receive Data[3:0] (RXD[3:0])
For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY.
When RXDV is de-asserted, the PHY drives RXD[3:0] to either 0000 for the idle state (non-EEE mode) or 0001 for the
LPI state (EEE mode).
RXD[3:0] transitions synchronously with respect to RXC.
3.2.1.8
Receive Error (RXER)
When RXDV is asserted, RXER is asserted for one or more RXC periods to indicate that a symbol error (for example,
a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected somewhere
in the frame that is being transferred from the PHY to the MAC.
In EEE mode only, when RXDV is de-asserted, RXER is driven by the PHY to inform the MAC that the KSZ8091MNX
receive is in the LPI state.
RXER transitions synchronously with respect to RXC.
3.2.1.9
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
3.2.1.10
Collision Detection (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
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KSZ8091MNX/RNB
3.2.2
MII SIGNAL DIAGRAM
The KSZ8091MNX MII pin connections to the MAC are shown in Figure 3-2.
FIGURE 3-2:
KSZ8091MNX MII INTERFACE
'
KSZ8091MNX
TXC
TX_EN
TXD[3:0]
TXC
TX_EN
TXD[3:0]
TXER
TXER
RXC
RXC
RXDV
RXDV
RXD[3:0]
RXER
3.3
MII
ETHERNET MAC
RXD[3:0]
RXER
CRS
CRS
COL
COL
RMII Data Interface (KSZ8091RNB Only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference
clock).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.
3.3.1
RMII - 25 MHZ CLOCK MODE
The KSZ8091RNB is configured to RMII - 25 MHz clock mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 0 (default value) to select 25 MHz clock mode.
3.3.2
RMII - 50 MHZ CLOCK MODE
The KSZ8091RNB is configured to RMII - 50 MHz clock mode after it is powered up or hardware reset with the following:
• An external 50 MHz clock source (oscillator) connected to XI (pin 9).
• The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 1 to select 50 MHz clock mode.
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KSZ8091MNX/RNB
3.3.3
RMII SIGNAL DEFINITION
Table 3-2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
TABLE 3-2:
RMII SIGNAL DEFINITION
RMII Signal
Name
Direction with Respect to
PHY KSZ8091RNB Signal
Direction with
Respect to MAC
REF_CLK
Output (25 MHz clock
mode)/
(50 MHz clock mode)
Input/Input or
Description
Synchronous 50 MHz reference clock for
receive, transmit, and control interface
TXEN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data[1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data[1:0]
RXER
Output
3.3.4
Input or not required Receive Error
REFERENCE CLOCK (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0] and
RX_ER.
For 25 MHz clock mode, the KSZ8091RNB generates and outputs the 50 MHz RMII REF_CLK to the MAC at REF_CLK
(pin 19).
For 50 MHz clock mode, the KSZ8091RNB takes in the 50 MHz RMII REF_CLK from the MAC or system board at XI
(pin 9) and leaves the REF_CLK (pin 19) as a no connect.
3.3.5
TRANSMIT ENABLE (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
3.3.6
TRANSMIT DATA[1:0] (TXD[1:0])
When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission.
When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
TXD[1:0] transitions synchronously with respect to REF_CLK.
3.3.7
CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)
The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is
detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are
detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the
frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on
RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
3.3.8
RECEIVE DATA[1:0] (RXD[1:0])
For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY.
When CRS_DV is de-asserted, the PHY drives RXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
RXD[1:0] transitions synchronously with respect to REF_CLK.
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KSZ8091MNX/RNB
3.3.9
RECEIVE ERROR (RXER)
When CRS_DV is asserted, RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for
example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected
somewhere in the frame that is being transferred from the PHY to the MAC.
RXER transitions synchronously with respect to REF_CLK.
3.3.10
COLLISION DETECTION (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
3.3.11
RMII SIGNAL DIAGRAM
The KSZ8091RNB RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-3. The connections
for 50 MHz clock mode are shown in Figure 3-4.
FIGURE 3-3:
KSZ8091RNB RMII INTERFACE (25 MHZ CLOCK MODE)
KSZ8091RNB
RMII MAC
CRS_DV
CRS_DV
RXD[1:0]
RXD[1:0]
RXER
RX_ER
TXEN
TX_EN
TXD[1:0]
REF_CLK
TXD[1:0]
REF_CLK
XI
XO
25MHz
XTAL
22pF
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22pF
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KSZ8091MNX/RNB
FIGURE 3-4:
KSZ8091RNB RMII INTERFACE (50 MHZ CLOCK MODE)
RMII MAC
KSZ8091RNB
CRS_DV
CRS_DV
RXD[1:0]
RXD[1:0]
RXER
RX_ER
TXEN
TX_EN
TXD[1:0]
TXD[1:0]
REF_CLK
XI
50MHz
OSC
3.4
Back-to-Back Mode – 100 Mbps Copper Repeater
Two KSZ8091MNX/RNB devices can be connected back-to-back to form a 100BASE-TX copper repeater.
FIGURE 3-5:
KSZ8091MNX/RNB TO KSZ8091MNX/RNB BACK-TO-BACK COPPER
REPEATER
RxD
RXP/RXM
TXP/TXM
KSZ8091MNX/RNB
(COPPER MODE)
TxD
25MHz/
50MHz
XI
OSC
XI
TXP/TXM
RXP/RXM
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KSZ8091MNX/RNB
(COPPER MODE)
TxD
RxD
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KSZ8091MNX/RNB
3.4.1
MII BACK-TO-BACK MODE (KSZ8091MNX ONLY)
In MII back-to-back mode, a KSZ8091MNX interfaces with another KSZ8091MNX to provide a complete 100 Mbps copper repeater solution.
The KSZ8091MNX devices are configured to MII back-to-back mode after power-up or reset with the following:
• Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 110.
• A common 25 MHz reference clock connected to XI (Pin 9) of both KSZ8091MNX devices.
• MII signals connected as shown in Table 3-3.
TABLE 3-3:
MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE (100BASE-TX COPPER
REPEATER)
KSZ8091MNX (100BASE-TX Copper)
[Device 1]
Pin Name
3.4.2
Pin Number
KSZ8091MNX (100BASE-TX Copper)
[Device 2]
Pin Type
Pin Name
Pin Number
Pin Type
RXDV
18
Output
TXEN
23
Input
RXD3
13
Output
TXD3
27
Input
RXD2
14
Output
TXD2
26
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
RXDV
18
Output
TXD3
27
Input
RXD3
13
Output
TXD2
26
Input
RXD2
14
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
RMII BACK-TO-BACK MODE (KSZ8091RNB ONLY)
In RMII back-to-back mode, a KSZ8091RNB interfaces with another KSZ8091RNB to provide a complete 100 Mbps
copper repeater solution.
The KSZ8091RNB devices are configured to RMII back-to-back mode after power-up or reset with the following:
• Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 101.
• A common 50 MHz reference clock connected to XI (pin 9) of both KSZ8091RNB devices.
• RMII signals connected as shown in Table 3-4.
TABLE 3-4:
RMII SIGNAL CONNECTION FOR RMII BACK-TO-BACK MODE (100BASE-TX
COPPER REPEATER)
KSZ8091RNB (100BASE-TX Copper)
[Device 1]
Pin Name
Pin Number
KSZ8091RNB (100BASE-TX Copper)
[Device 2]
Pin Type
Pin Name
Pin Number
Pin Type
CRSDV
18
Output
TXEN
23
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
CRSDV
18
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
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KSZ8091MNX/RNB
3.5
MII Management (MIIM) Interface
The KSZ8091MNX/RNB supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8091MNX/RNB. An external device with MIIM capability is used to read the PHY status and/
or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more PHY devices.
• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indirect access to MMD addresses and registers. See the Register Descriptions section.
As the default, the KSZ8091MNX/RNB supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter
is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8091MNX/RNB device, or write
to multiple KSZ8091MNX/RNB devices simultaneously.
PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF,
pin 19) or software (Register 16h, bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8091MNX/RNB
device.
The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock.
Table 3-5 shows the MII management frame format for the KSZ8091MNX/RNB.
TABLE 3-5:
MII MANAGEMENT FRAME FORMAT FOR THE KSZ8091MNX/RNB
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA
Data Bits[15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
3.6
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8091MNX/RNB PHY Register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8091MNX/RNB control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
3.7
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8091MNX/RNB and its link partner. This feature allows the KSZ8091MNX/RNB to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8091MNX/RNB accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, bit [13]. MDI and MDI-X mode
is selected by Register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 3-6 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
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KSZ8091MNX/RNB
TABLE 3-6:
MDI/MDI-X PIN DESCRIPTION
MDI
3.7.1
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
TX+
1
RX+
2
TX–
2
RX–
3
RX+
3
TX+
6
RX–
6
TX–
STRAIGHT CABLE
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-6 shows
a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
FIGURE 3-6:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
1
2
2
TRANSMIT PAIR
RECEIVE PAIR
3
STRAIGHT
CABLE
3
4
4
5
5
6
6
7
7
8
8
RECEIVE PAIR
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
NIC
3.7.2
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
CROSSOVER CABLE
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
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KSZ8091MNX/RNB
FIGURE 3-7:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
RECEIVE PAIR
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
CROSSOVER
CABLE
1
RECEIVE PAIR
2
2
3
3
4
4
5
5
6
6
7
7
8
8
TRANSMIT PAIR
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
3.8
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
Loopback Mode
The KSZ8091MNX/RNB supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
3.8.1
LOCAL (DIGITAL) LOOPBACK
This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8091MNX/RNB and the
external MAC, and is supported for both speeds (10/100 Mbps) at full-duplex.
The loopback data path is shown in Figure 3-8.
1.
2.
3.
4.
The MII/RMII MAC transmits frames to the KSZ8091MNX/RNB.
Frames are wrapped around inside the KSZ8091MNX/RNB.
The KSZ8091MNX/RNB transmits frames back to the MII/RMII MAC.
Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.
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KSZ8091MNX/RNB
FIGURE 3-8:
LOCAL (DIGITAL) LOOPBACK
KSZ8091MNX/RNB
AFE
PCS
(ANALOG)
(DIGITAL)
MII/
RMII
MII/RMII
MAC
The following programming action and register settings are used for local loopback mode:
For 10/100 Mbps loopback:
Set Register 0h,
Bit [14] = 1
// Enable local loopback mode
Bit [13] = 0/1
// Select 10 Mbps/100 Mbps speed
Bit [12] = 0
// Disable auto-negotiation
Bit [8] = 1
// Select full-duplex mode
3.8.2
REMOTE (ANALOG) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between the KSZ8091MNX/RNB and its link partner, and is supported for 100BASE-TX full-duplex
mode only.
The loopback data path is shown in Figure 3-9.
1.
2.
3.
The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8091MNX/RNB.
Frames are wrapped around inside the KSZ8091MNX/RNB.
The KSZ8091MNX/RNB transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner.
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KSZ8091MNX/RNB
FIGURE 3-9:
REMOTE (ANALOG) LOOPBACK
KSZ8091MNX/RNB
RJ-45
AFE
(ANALOG)
PCS
(DIGITAL)
MII/
RMII
CAT-5
(UTP)
RJ-45
100BASE-TX
LINK PARTNER
The following programming steps and register settings are used for remote loopback mode:
1.
Set Register 0h,
Bits [13] = 1 // Select 100 Mbps speed
Bit [12] = 0
// Disable auto-negotiation
Bit [8] = 1
// Select full-duplex mode
Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner.
2.
Set Register 1Fh,
Bit [2] = 1
// Enable remote loopback mode
LinkMD® Cable Diagnostic
3.9
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides
the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as
a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with Register 1Fh,
the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as
the cable differential pair for testing.
3.9.1
USAGE
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
1.
2.
3.
4.
Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
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KSZ8091MNX/RNB
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
5.
Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38.
The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
·
D Dis tan ce to cable fault in meters = 0.38 Register 1Dh, bits[8:0]
Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
3.10
NAND Tree Support
The KSZ8091MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8091MNX/RNB digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the
nested NAND gates.
The NAND tree test process includes:
•
•
•
•
Enabling NAND tree mode
Pulling all NAND tree input pins high
Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 3-7 and Table 3-8 list the NAND tree pin orders for KSZ8091MNX and KSZ8091RNB, respectively.
TABLE 3-7:
NAND TREE TEST PIN ORDER FOR KSZ8091MNX
Pin Number
Pin Name
NAND Tree Description
11
MDIO
Input
12
MDC
Input
13
RXD3
Input
14
RXD2
Input
15
RXD1
Input
16
RXD0
Input
18
RXDV
Input
18
RXC
Input
20
RXER
Input
21
INTRP
Input
22
TXC
Input
23
TXEN
Input
24
TXD0
Input
25
TXD1
Input
26
TXD2
Input
27
TXD3
Input
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KSZ8091MNX/RNB
TABLE 3-7:
Pin Number
Pin Name
NAND Tree Description
30
LED0
Input
TABLE 3-8:
3.10.1
NAND TREE TEST PIN ORDER FOR KSZ8091MNX (CONTINUED)
28
COL
Input
29
CRS
Output
NAND TREE TEST PIN ORDER FOR KSZ8091RNB
Pin Number
Pin Name
NAND Tree Description
11
MDIO
Input
12
MDC
Input
15
RXD1
Input
16
RXD0
Input
18
CRS_DV
Input
19
REF_CLK
Input
20
RXER
Input
21
INTRP
Input
22
PME_EN
Input
23
TXEN
Input
24
TXD0
Input
25
TXD1
Input
30
LED0
Input
31
LED1
Input
28
CONFIG0
Input
29
CONFIG1
Output
NAND TREE I/O TESTING
Use the following procedure to check for faults on the KSZ8091MNX/RNB digital I/O pin connections to the board:
1.
2.
3.
Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 21) or software (Register 16h,
Bit [5]).
Use board logic to drive all KSZ8091MNX/RNB NAND tree input pins high.
Use board logic to drive each NAND tree input pin, in KSZ8091MNX/RNB NAND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low
to indicate that the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to
high to indicate that the second pin is connected properly.
d) Leave the first pin (MDIO) and the second pin (MDC) low.
e) Toggle the third pin (RXD3/PHYAD0) from high to low, and verify that the CRS/CONFIG1 pin switches from
high to low to indicate that the third pin is connected properly.
f) Continue with this sequence until all KSZ8091MNX/RNB NAND tree input pins have been toggled.
Each KSZ8091MNX/RNB NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or lowto-high to indicate a good connection. If the CRS/CONFIG1 pin fails to toggle when the KSZ8091MNX/RNB input pin
toggles from high to low, the input pin has a fault.
3.11
Power Management
The KSZ8091MNX/RNB incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
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KSZ8091MNX/RNB
3.11.1
POWER-SAVING MODE
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled
by writing a ‘1’ to Register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link).
In this mode, the KSZ8091MNX/RNB shuts down all transceiver blocks, except for the transmitter, energy detect, and
PLL circuits.
By default, power-saving mode is disabled after power-up.
3.11.2
ENERGY-DETECT POWER-DOWN MODE
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8091MNX/RNB transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091MNX/RNB and its link
partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable
is connected between them.
By default, energy-detect power-down mode is disabled after power-up.
3.11.3
POWER-DOWN MODE
Power-down mode is used to power down the KSZ8091MNX/RNB device when it is not in use after power-up. It is
enabled by writing a ‘1’ to Register 0h, bit [11].
In this mode, the KSZ8091MNX/RNB disables all internal functions except the MII management interface. The
KSZ8091MNX/RNB exits (disables) power-down mode after Register 0h, bit [11] is set back to ‘0’.
3.11.4
SLOW-OSCILLATOR MODE
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow
oscillator when the KSZ8091MNX/RNB device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,
bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091MNX/RNB device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1.
2.
3.
Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].
Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
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KSZ8091MNX/RNB
3.12
Energy Efficient Ethernet (EEE)
The KSZ8091MNX implements Energy Efficient Ethernet (EEE) for the Media Independent Interface (MII) as described
in IEEE Standard 802.3az. The Standard is defined around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support special signaling associated with EEE. EEE saves power by keeping the
AC signal on the copper Ethernet cable at approximately 0V peak-to-peak as often as possible during periods of no
traffic activity, while maintaining the link-up status. This is referred to as low-power idle (LPI) mode or state.
Similarly, the KSZ8091RNB implements EEE for the Reduced Media Independent Interface (RMII) as described in IEEE
Standard 802.3az for line signaling by the two differential pairs (analog side) and according to the multi-source agreement (MSA) of collaborating Fast Ethernet chip vendors for the RMII (digital side). This agreement is based on the IEEE
Standard’s EEE implementation for MII (100 Mbps).
During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation
immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal
100 Mbps operating mode. Wake-up time is
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