KSZ8765CLXIC

KS8765CLX Integrated 5-Port 10/100 Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces Revision 1.0 General Description The KSZ8765CLX is a highly integrated, Layer 2managed, five-port switch with numerous features designed to reduce overall system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8765CLX incorporates a small package outline, the lowest power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, highperformance memory bandwidth, and a shared memorybased switch fabric with non-blocking support. The KSZ8765CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the GMII, RGMII, MII, and RMII modes. The KSZ8765CLX product is built upon Micrel’s industryleading Ethernet’s latest analog and digital technology, with features designed to offload host processing and streamline the overall design.  Two integrated MAC/PHYs 100Base-FX on Port 1 and Port 2  Two integrated MAC/PHYs 10/100Base-T/TX on Port 3 and Port 4  One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces  Small 80-pin LQFP package A robust assortment of power management features including energy-efficient Ethernet (EEE), power management event (PME), and wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments. All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. Datasheets and support documentation are available on Micrel’s website at: www.micrel.com. Functional Diagram Figure 1. KSZ8765CLX Functional Block Diagram Auto MDI/MDI-X is a trademark of Hewlett Packard. Magic Packet is a trademark of Advanced Micro Devices. LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com July 23, 2014 Revision 1.0 Micrel, Inc. KSZ8765CLX Advanced Switch Capabilities Features  Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 1024-entry forwarding table  64kb frame buffer RAM  IEEE 802.1q VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs)  IEEE 802.1p/q tag insertion or removal on a per port basis (egress)  VLAN ID tag/untag options on per port basis  Fully compliant with IEEE 802.3/802.3u standards  IEEE 802.3x full-duplex with force mode option and halfduplex back-pressure collision flow control  IEEE 802.1w rapid spanning tree protocol support  IGMP v1/v2/v3 snooping for multicast packet filtering  QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per port basis on four priority levels  IPv4/IPv6 QoS support  IPv6 multicast listener discovery (MLD) snooping  Programmable rate limiting at the ingress and egress ports on a per port basis  Jitter-free per-packet-based rate limiting support  Tail tagging mode (one byte added before FCS) support on Port 5 to inform the processor which ingress port receives the packet and its priority  Broadcast storm protection with percentage control (global and per port basis)  1kb entry forwarding table with 64kb frame buffer  Four priority queues with dynamic packet mapping for IEEE 802.1p, IPv4 ToS (DIFFSERV), IPv6 traffic class, etc.  Supports wake-on-LAN (WoL) using AMD’s Magic Packet™  VLAN and address filtering  Supports 802.1x port-based security, authentication, and MAC-based authentication via access control lists (ACL)  Provides port-based and rule-based ACLs to support Layer 2 MAC SA/DA address, Layer 3 IP address and IP mask, Layer 4 TCP/UDP port number, IP protocol, TCP flag, and compensation for the port security filtering  Ingress and egress rate limit based on bit per second (bps) and packet-based rate limiting (pps) Management Capabilities  The KSZ8765CLX includes all the functions of a 10/100Base-T/TX and 100Base-FX switch system, which combines a switch engine, frame buffer management, address look-up table, queue management, MIB counters, media access controllers (MAC), and PHY transceivers  Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 1024-entry forwarding table  Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port  MIB counters for fully compliant statistics gathering - 36 counters per port  Hardware support for port-based flush and freeze command in MIB counter.  Multiple loopback of remote, PHY, and MAC modes support for the diagnostics  Rapid spanning tree support (RSTP) for topology management and ring/linear recovery Robust PHY Ports  Four integrated IEEE 802.3/802.3u-compliant Ethernet transceivers supporting 10Base-T and 100Base-TX  802.1az EEE supported  On-chip termination resistors and internal biasing for differential pairs to reduce power  HP Auto MDI/MDI-X™ crossover support eliminates the need to differentiate between straight or crossover cables in applications MAC and GMAC Ports  Four internal media access control (MAC1 to MAC4) units and one internal Gigabit media access control (GMAC5) unit  GMII, RGMII, MII, or RMII interfaces support for the Port 5 GMAC5 with uplink  2kb jumbo packet support  Tail tagging mode (one byte added before FCS) support on Port 5 to inform the processor which ingress port receives the packet and its priority  Supports reduced media independent interface (RMII) with 50MHz reference clock output  Supports media independent interface (MII) in either PHY mode or MAC mode on Port 5  Micrel LinkMD® cable diagnostic capabilities for determining cable opens, shorts, and length July 23, 2014 Configuration Registers Access  High speed (4-wire, up to 50MHz) interface (SPI) to access all internal registers  MII management interface (MIIM, MDC/MDIO 2-wire) to access all PHY registers per clause 22.2.4.5 of the IEEE 802.3 specification 2 Revision 1.0 Micrel, Inc. KSZ8765CLX  I/O pin strapping facility to set certain register bits from I/O pins during reset time  Control registers configurable on-the-fly Additional Features  Single 25MHz +50ppm reference clock requirement  Comprehensive programmable two LED indicator support for link, activity, full/half duplex, and 10/100 speed Power and Power Management  Full-chip software power down (all registers value are not saved and strap-in value will re-strap after release of the power down)  Per-port software power down  Energy detect power down (EDPD), which disables the PHY transceiver when cables are removed  Supports IEEE P802.3az energy-efficient Ethernet to reduce power consumption in transceivers in LPI state even though cables are not removed  Dynamic clock tree control to reduce clocking in areas not in use  Low power consumption without extra power consumption on transformers  Voltages: Using external LDO power supplies.  Analog VDDAT 3.3V  VDDIO support 3.3V, 2.5V, and 1.8V  Low 1.2V voltage for analog and digital core power  Wake-on-LAN support with configurable packet control July 23, 2014 Packaging and Environmental  Commercial temperature range: 0°C to +70°C  Industrial temperature range: –40oC to +85oC  Package available in an 80-pin lead free (RoHS) LQFP form factor  Supports HBM ESD rating of 5kV  0.065µm CMOS technology for lower power consumption Applications  Industrial Ethernet applications that employ IEEE 802.3compliant MACs (Ethernet/IP, Profinet, MODBUS TCP, etc.)  VoIP phone  Set-top/game box  Automotive  Industrial control  IPTV POF  SOHO residential gateway with full wire speed of four LAN ports  Broadband gateway/firewall/VPN  Integrated DSL/cable modem  Wireless LAN access point + gateway  Standalone 10/100 switch  Networked measurement and control systems 3 Revision 1.0 Micrel, Inc. KSZ8765CLX Ordering Information Part Number Temperature Range Package Lead Finish/Grade KSZ8765CLXCC 0°C to 70°C 80-Pin LQFP Pb-Free/Commercial KSZ8765CLXIC -40°C to +85°C 80-Pin LQFP Pb-Free/Industrial KSZ8765CLX-EVAL Evaluation Board Revision History Revision 1.0 July 23, 2014 Date 7/21/14 Summary of Changes Initial document created. 4 Revision 1.0 Micrel, Inc. KSZ8765CLX Contents List of Figures .......................................................................................................................................................................... 9 List of Tables ......................................................................................................................................................................... 10 Pin Configuration ................................................................................................................................................................... 11 Pin Description ...................................................................................................................................................................... 12 Strap-In Options .................................................................................................................................................................... 18 Introduction............................................................................................................................................................................ 20 Functional Overview: Physical Layer (PHY) ......................................................................................................................... 20 100BASE-TX Transmit ..................................................................................................................................................... 20 100BASE-TX Receive ...................................................................................................................................................... 20 PLL Clock Synthesizer ...................................................................................................................................................... 20 Scrambler/Descrambler (100BASE-TX Only) ................................................................................................................... 21 100BASE-FX Operation.................................................................................................................................................... 21 100BASE-FX Signal Detection ......................................................................................................................................... 21 100BASE-FX Far End Fault.............................................................................................................................................. 21 10BASE-T Transmit .......................................................................................................................................................... 21 10BASE-T Receive ........................................................................................................................................................... 21 MDI/MDI-X Auto Crossover .............................................................................................................................................. 21 Straight Cable ............................................................................................................................................................... 22 Crossover Cable ........................................................................................................................................................... 22 Auto-Negotiation ............................................................................................................................................................... 23 ® LinkMD Cable Diagnostics .............................................................................................................................................. 24 Access .......................................................................................................................................................................... 24 Usage ........................................................................................................................................................................... 24 ® A LinkMD Example ..................................................................................................................................................... 25 On-Chip Termination and Internal Biasing ....................................................................................................................... 25 Functional Overview: Media Access Controller (MAC) ......................................................................................................... 26 Media Access Controller Operation .................................................................................................................................. 26 Inter-Packet Gap (IPG) ................................................................................................................................................. 26 Backoff Algorithm ......................................................................................................................................................... 26 Late Collision ................................................................................................................................................................ 26 Illegal Frames ............................................................................................................................................................... 26 Flow Control.................................................................................................................................................................. 26 Half-Duplex Back Pressure .......................................................................................................................................... 27 Broadcast Storm Protection .......................................................................................................................................... 27 Functional Overview: Switch Core ........................................................................................................................................ 28 Learning ............................................................................................................................................................................ 28 Migration ........................................................................................................................................................................... 28 Aging ................................................................................................................................................................................. 28 Forwarding ........................................................................................................................................................................ 28 Switching Engine .............................................................................................................................................................. 29 Functional Overview: Power ................................................................................................................................................. 30 July 23, 2014 5 Revision 1.0 Micrel, Inc. KSZ8765CLX Functional Overview: Power Management ........................................................................................................................... 30 Normal Operation Mode ................................................................................................................................................... 30 Energy Detect Mode ......................................................................................................................................................... 30 Soft Power-Down Mode .................................................................................................................................................... 31 Port-Based Power-Down Mode ........................................................................................................................................ 31 Energy-Efficient Ethernet (EEE) ....................................................................................................................................... 31 LPI Signalling ................................................................................................................................................................ 32 LPI Assertion ................................................................................................................................................................ 32 LPI Detection ................................................................................................................................................................ 32 PHY LPI Transmit Operation ........................................................................................................................................ 32 PHY LPI Receive Operation ......................................................................................................................................... 33 Negotiation with EEE Capability ................................................................................................................................... 33 Wake-on-LAN (WoL) ........................................................................................................................................................ 33 Direction of Energy ....................................................................................................................................................... 34 Direction of Link-up ....................................................................................................................................................... 34 Magic Packet™ ............................................................................................................................................................ 34 Example of Magic Packet: ............................................................................................................................................ 34 Interrupt (INT_N/PME_N) ................................................................................................................................................. 34 Functional Overview: Interfaces ............................................................................................................................................ 35 Configuration Interface ..................................................................................................................................................... 35 SPI Slave Serial Bus Configuration .............................................................................................................................. 35 MII Management Interface (MIIM) ................................................................................................................................ 38 Switch Port 5 GMAC Interface .......................................................................................................................................... 39 Standard GMII/MII Interface ......................................................................................................................................... 39 Reduced Gigabit Media Independent Interface (RGMII) .............................................................................................. 39 Reduced Media Independent Interface (RMII) ............................................................................................................. 39 Port 5 GMAC5 SW5-MII Interface ................................................................................................................................ 40 Port 5 GMAC5 SW5-GMII Interface ............................................................................................................................. 41 Port 5 GMAC5 SW5-RGMII Interface ........................................................................................................................... 41 Port 5 GMAC5 SW5-RMII Interface .................................................................................................................................. 42 Functional Overview: Advanced Functionality ...................................................................................................................... 43 QoS Priority Support ......................................................................................................................................................... 43 Port-Based Priority ....................................................................................................................................................... 44 802.1p-Based Priority ................................................................................................................................................... 44 DiffServ-Based Priority ................................................................................................................................................. 44 Spanning Tree Support ..................................................................................................................................................... 45 Rapid Spanning Tree Support .......................................................................................................................................... 46 Tail Tagging Mode ............................................................................................................................................................ 47 IGMP Support ................................................................................................................................................................... 48 IPv6 MLD Snooping .......................................................................................................................................................... 48 Port Mirroring Support ...................................................................................................................................................... 48 VLAN Support ................................................................................................................................................................... 49 July 23, 2014 6 Revision 1.0 Micrel, Inc. KSZ8765CLX Rate Limiting Support ....................................................................................................................................................... 50 Ingress Rate Limit ......................................................................................................................................................... 51 Egress Rate Limit ......................................................................................................................................................... 51 Transmit Queue Ratio Programming ............................................................................................................................ 51 VLAN and Address Filtering ............................................................................................................................................. 52 IEEE 802.1x Port-Based Security ..................................................................................................................................... 52 Authentication Register and Programming Model ........................................................................................................ 53 Access Control List (ACL) Filtering ................................................................................................................................... 53 Access Control Lists ..................................................................................................................................................... 53 Matching Field Mode MD [1:0]...................................................................................................................................... 54 Action Field ................................................................................................................................................................... 55 Processing Field ........................................................................................................................................................... 56 Denial of Service (DoS) Attack Prevention via ACL ..................................................................................................... 56 Device Registers ................................................................................................................................................................... 57 Direct Register Description ................................................................................................................................................... 59 Global Registers ............................................................................................................................................................... 61 Advanced Control Registers ............................................................................................................................................. 81 Indirect Register Description ............................................................................................................................................... 101 Static MAC Address Table .................................................................................................................................................. 102 VLAN Table ......................................................................................................................................................................... 104 Dynamic MAC Address Table ............................................................................................................................................. 107 PME Indirect Registers ....................................................................................................................................................... 109 Programming Examples ................................................................................................................................................. 110 Read Operation .......................................................................................................................................................... 110 Write Operation .......................................................................................................................................................... 110 ACL Rule Table and ACL Indirect Registers ....................................................................................................................... 111 ACL Register and Programming Model .......................................................................................................................... 111 ACL Indirect Registers .................................................................................................................................................... 112 Read Operation .......................................................................................................................................................... 120 Write Operation .......................................................................................................................................................... 121 EEE Indirect Registers ........................................................................................................................................................ 122 Programming Examples ................................................................................................................................................. 128 Read Operation .......................................................................................................................................................... 128 Write Operation .......................................................................................................................................................... 128 Management Information Base (MIB) Counters ................................................................................................................. 129 For Port 2, the base is 0x20, same offset definition (0x20-0x3f) .................................................................................... 130 For Port 3, the base is 0x40, same offset definition (0x40-0x5f) .................................................................................... 130 For Port 4, the base is 0x60, same offset definition (0x60-0x7f) .................................................................................... 130 For Port 5, the base is 0x80, same offset definition (0x80-0x9f) .................................................................................... 130 MIIM Registers .................................................................................................................................................................... 133 Absolute Maximum Ratings ................................................................................................................................................ 137 Operating Ratings ............................................................................................................................................................... 137 Electrical Characteristics ..................................................................................................................................................... 137 July 23, 2014 7 Revision 1.0 Micrel, Inc. KSZ8765CLX Timing Diagram ................................................................................................................................................................... 140 GMII Timing .................................................................................................................................................................... 140 RGMII Timing .................................................................................................................................................................. 141 MII Timing ....................................................................................................................................................................... 142 RMII Timing..................................................................................................................................................................... 144 SPI Timing ...................................................................................................................................................................... 145 Auto-Negotiation Timing ................................................................................................................................................. 147 MDC/MDIO Timing ......................................................................................................................................................... 148 Power-Down/Power-Up and Reset Timing ..................................................................................................................... 149 Reset Circuit Diagram ..................................................................................................................................................... 150 Selection of Isolation Transformer ...................................................................................................................................... 151 Selection of Reference Crystal............................................................................................................................................ 151 Package Information ........................................................................................................................................................... 152 July 23, 2014 8 Revision 1.0 Micrel, Inc. KSZ8765CLX List of Figures Figure 1. KSZ8765CLX Functional Block Diagram ............................................................................................................... 1 Figure 2. 80-Pin LQFP ........................................................................................................................................................ 11 Figure 3. Typical Straight Cable Connection ...................................................................................................................... 22 Figure 4. Typical Crossover Cable Connection .................................................................................................................. 22 Figure 5. Auto-Negotiation and Parallel Operation ............................................................................................................. 23 Figure 6. Destination Adddress Look-up and Resolution Flow Chart ................................................................................. 29 Figure 7. EEE Transmit and Receive Signaling Paths ....................................................................................................... 31 Figure 8. Traffic Activity and EEE LPI Operations .............................................................................................................. 33 Figure 9. SPI Access Timing ............................................................................................................................................... 36 Figure 10. SPI Multiple Access Timing ................................................................................................................................. 37 Figure 11. 802.1p Priority Field Format ................................................................................................................................ 44 Figure 12. Tail Tag Frame Format ........................................................................................................................................ 47 Figure 13. ACL Format .......................................................................................................................................................... 54 Figure 14. Interface and Register Mapping ........................................................................................................................... 57 Figure 15. ACL Table Access ............................................................................................................................................. 111 Figure 16. GMII Signals Timing Diagram ............................................................................................................................ 140 Figure 17. RGMII v2.0 Specification ................................................................................................................................... 141 Figure 18. MAC Mode MII Timing – Data Received from MII ............................................................................................. 142 Figure 19. MAC Mode MII Timing – Data Transmitted from MII ......................................................................................... 142 Figure 20. PHY Mode MII Timing – Data Received from MII .............................................................................................. 143 Figure 21. PHY Mode MII Timing – Data Transmitted from MII .......................................................................................... 143 Figure 22. RMII Timing – Data Received from RMII ........................................................................................................... 144 Figure 23. RMII Timing – Data Transmitted to RMII ........................................................................................................... 144 Figure 24. SPI Input Timing ................................................................................................................................................ 145 Figure 25. SPI Output Timing.............................................................................................................................................. 146 Figure 26. Auto-Negotiation Timing Diagram ...................................................................................................................... 147 Figure 27. MDC/MDIO Timing Diagram .............................................................................................................................. 148 Figure 28. Reset Timing Diagram ....................................................................................................................................... 149 Figure 29. Recommended Reset Circuit ............................................................................................................................. 150 Figure 30. Recommended Circuit for Interfacing with CPU/FPGA Reset ........................................................................... 150 Figure 31. 80-Pin LQFP ...................................................................................................................................................... 152 July 23, 2014 9 Revision 1.0 Micrel, Inc. KSZ8765CLX List of Tables Table 1. MDI/MDI-X Pin Definitions .................................................................................................................................... 21 Table 2. Internal Function Block Status .............................................................................................................................. 30 Table 3. Available Interfaces ............................................................................................................................................... 35 Table 4. SPI Connections ................................................................................................................................................... 35 Table 5. MII Management Interface Frame Format ............................................................................................................ 38 Table 6. Signals of GMII/RGMII/MII/RMII ........................................................................................................................... 39 Table 7. Port 5 SW5-MII Connection .................................................................................................................................. 40 Table 8. Port 5 SW5-GMII Connection ............................................................................................................................... 41 Table 9. Port 5 SW5-RGMII Connection ............................................................................................................................. 41 Table 10. Port 5 SW5-RGMII Clock Delay Configuration with Connection Partner .............................................................. 42 (6) Table 11. Port 5 SW5-RMII Connection ............................................................................................................................. 43 Table 12. Port Settings and Software Actions for Spanning Tree States ............................................................................. 45 Table 13. Port Settings and Software Actions for Rapid Spanning Tree States ................................................................... 46 Table 14. Tail Tag Rules ....................................................................................................................................................... 47 Table 15. FID+DA Look-Up in the VLAN Mode .................................................................................................................... 49 Table 16. FID+SA Look-Up in the VLAN Mode .................................................................................................................... 49 Table 17. 10/100/1000Mbps Rate Selection for the Rate Limit ............................................................................................ 50 Table 18. Mapping of Functional Areas within the Address Space ...................................................................................... 58 Table 19. Format of Static MAC Addresses for Reads (32 Entries) ................................................................................... 102 Table 20. Format of Static MAC Addresses for Writes (32 Entries) ................................................................................... 103 Table 21. VLAN Table ......................................................................................................................................................... 104 Table 22. Indirect Registers and VLAN ID .......................................................................................................................... 106 Table 23. Dynamic MAC Address Table ............................................................................................................................. 107 Table 24. PME Indirect Registers ....................................................................................................................................... 109 Table 25. Temporary Storage for 14-Bytes ACL Rules ...................................................................................................... 112 Table 26. ACL Read and Write Control .............................................................................................................................. 120 Table 27. EEE Global Registers ......................................................................................................................................... 122 Table 28. EEE Port Registers ............................................................................................................................................. 123 Table 29. Port 1 MIB Counter Indirect Memory Offerts ...................................................................................................... 129 Table 30. Format of Per-Port MIB Counters ....................................................................................................................... 130 Table 31. All Port-Dropped Packet MIB Counters .............................................................................................................. 130 Table 32. Format of Per-Port Total RX/TX Bytes MIB Counters ........................................................................................ 131 Table 33. Format of All Port Dropped Packet MIB Counters .............................................................................................. 131 Table 34. GMII Timing Parameters ..................................................................................................................................... 140 Table 35. RGMII v2.0 Specification .................................................................................................................................... 141 Table 36. MAC Mode MII Timing Parameters ..................................................................................................................... 142 Table 37. PHY Mode MII Timing Parameters ..................................................................................................................... 143 Table 38. RMII Timing Parameters ..................................................................................................................................... 144 Table 39. SPI Input Timing Parameters .............................................................................................................................. 145 Table 40. SPI Output Timing Parameters ........................................................................................................................... 146 Table 41. Auto-Negotiation Timing Parameters .................................................................................................................. 147 Table 42. MDC/MDIO Timing Parameters .......................................................................................................................... 148 Table 43. Reset Timing Parameters ................................................................................................................................... 149 Table 44. Transformer Selection Criteria ............................................................................................................................ 151 Table 45. Qualified Magnetic Vendors ................................................................................................................................ 151 Table 46. Typical Reference Crystal Characteristics .......................................................................................................... 151 July 23, 2014 10 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Configuration Figure 2. 80-Pin LQFP July 23, 2014 11 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Description Type (1) Port Pin Function (2) Pin Number Pin Name 1 VDD12A P 1.2V core power. 2 VDDAT P 3.3V analog power. 3 GNDA GND 4 RXP1 I 1 Port 1 physical receive signal + (differential). 5 RXM1 I 1 Port 1 physical receive signal - (differential). 6 TXP1 O 1 Port 1 physical transmit signal + (differential). 7 TXM1 O 1 Port 1 physical transmit signal - (differential). 8 RXP2 I 2 Port 2 physical receive signal + (differential). 8 RXM2 I 2 Port 2 physical receive signal - (differential). 10 TXP2 O 2 Port 2 physical transmit signal + (differential). 11 TXM2 O 2 Port 2 physical transmit signal - (differential). 12 VDDAT P 13 RXP3 I 3 Port 3 physical receive signal + (differential). 14 RXM3 I 3 Port 3 physical receive signal - (differential). 15 TXP3 O 3 Port 3 physical transmit signal + (differential). 16 TXM3 O 3 Port 3 physical transmit signal – (differential). 17 RXP4 I 4 Port 4 physical receive signal + (differential). 18 RXM4 I 4 Port 4 physical receive signal - (differential). 19 TXP4 O 4 Port 4 physical transmit signal + (differential). 20 TXM4 O 4 Port 4 physical transmit signal - (differential). 21 GNDA GND 22 NC NC 23 INTR_N OPU Analog ground. 3.3V analog power. Analog ground. No connect. Interrupt. Active low. This pin is an open-drain output pin. Port 3 LED Indicator 1. See global Register 11 bits [5:4] for details. Strap option: Switch Port 5 GMAC5 interface mode select by 24 LED3_1 IPU/O 3 LED3[1:0] 00 = MII for SW5-MII 01 = RMII for SW5-RMII 10 = GMII for SW5-GMII 11 = RGMII for SW5-RGMII (default) Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bi-directional. GND = Ground. IPU = Input with internal pull-up. IPD = Input with internal pull-down. IPD/O = Input with internal pull-down during reset, output pin otherwise. IPU/O = Input with internal pull-up during reset, output pin otherwise. OTRI = Output tri-stated. 2. PU = Strap pin pull-up. PD = Strap pin pull-down. NC = No connect or tied to ground for this product. July 23, 2014 12 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Description (Continued) Pin Number Pin Name 25 LED3_0 Type (1) IPU/O Port 3 Pin Function (2) Port 3 LED Indicator 0. See global Register 11 bits [5:4] for details. Strap option: see LED3_1 26 VDD12D P 27 GNDD GND 28 LED4_1 IPU/O 1.2V core power. Digital ground. 4 Port 4 LED Indicator 1. See global Register 11 bits [5:4] for details. GMII/MII/RMII: Port 5 switch transmit enable. 29 TXEN5/TXD5_CTL IPD 5 30 TXD5_0 IPD 5 GMII/RGMII/MII/RMII: Port 5 switch transmit bit [0]. 31 LED4_0 IPU/O 4 Port 4 LED Indicator 0. See global Register 11 bits [5:4] for details. 32 TXD5_1 IPD 5 GMII/RGMII/MII/RMII: Port 5 switch transmit bit [1]. 33 GNDD GND 34 VDDIO P 35 36 37 38 39 40 41 July 23, 2014 TXD5_2 TXD5_3 TXER5 TXD5_4 TXD5_5 TXD5_6 TXD5_7 IPD IPD IPD IPD IPD IPD IPD RGMII: Transmit data control. Digital ground. 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 5 5 5 5 5 5 5 GMII/RGMII/MII: Port 5 switch transmit bit [2]. RMII: No connection. GMII/RGMII/MII: Port 5 switch transmit bit [3]. RMII: No connection. GMII/MII: Port 5 switch transmit error. RGMII/RMII: No connection. GMII: Port 5 switch transmit bit [4]. RGMII/MII/RMII: No connection. GMII: Port 5 switch transmit bit [5]. RGMII/MII/RMII: No connection. GMII: Port 5 switch transmit bit [6]. RGMII/MII/RMII: No connection. GMII: Port 5 switch transmit bit [7]. RGMII/MII/RMII: No connection. 13 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Description (Continued) Pin Number Pin Name Type (1) Port Pin Function (2) Port 5 Switch GMAC5 Clock Pin: MII: 2.5/25MHz clock, PHY mode is output, MAC mode is input. 43 TXC5/REFCLKI5 /GTXC5 I/O 5 RMII: Input for receiving 50MHz clock in normal mode. GMII: Input 125MHz clock for the transmit. RGMII: Input 125MHz clock with falling and rising edge to latch data for the transmit. Port 5 Switch GMAC5 Clock Pin: MII: 2.5/25MHz clock, PHY mode is output, MAC mode is input. 44 RXC5/GRXC5 I/O 5 RMII: Output 50MHz reference clock for the receiving/transmit in clock mode. GMII: Output 125MHz clock for the receiving. RGMII: Output 125MHz clock with falling and rising edge to latch data for the receiving. 45 RXD5_0 IPD/O 5 GMII/RGMII/MII/RMII: Port 5 switch receive bit [0]. 46 RXD5_1 IPD/O 5 GMII/RGMII/MII/RMII: Port 5 switch receive bit [1]. 47 GNDD GND 48 VDDIO P 49 50 RXD5_2 RXD5_3 IPD/O IPD/O Digital ground. 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 5 5 GMII/RGMII/MII: Port 5 switch receive bit [2]. RMII: No connection GMII/RGMII/MII: Port 5 switch receive bit [3]. RMII: No connection GMII/MII: RXDV5 is for Port 5 switch GMII/MII receive data valid. 51 RXDV5/CRSDV5 /RXD5_CTL IPD/O 5 RMII: CRSDV5 is for Port 5 RMII carrier sense/receive data valid output. RGMII: RXD5_CTL is for Port 5 RGMII receive data control 52 53 54 July 23, 2014 RXER5 CRS5 COL5 IPD/O IPD/O IPD/O 5 5 5 GMII/MII: Port 5 switch receive error. RGMII/RMII: No connection. GMII/MII: Port 5 switch MII modes carrier sense. RGMII/RMII: No connection. GMII/MII: Port 5 switch MII collision detect. RGMII/RMII: No connection. 14 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Description (Continued) Pin Number Pin Name Type (1) Port Pin Function (2) 25MHz Clock Output (Option) 55 REFCLKO IPU/O Controlled by the strap Pin LED2_0 and the global Register 11 bit 1. Default is enabled. It is better to disable it if not using it. Power Management Event 56 57 58 59 PME_N RXD5_4 RXD5_5 RXD5_6 This output signal indicates that a wake-on-LAN event has been detected as a result of a wake-up frame being detected. The KSZ8765CLX is requesting that the system wake up from low power mode. Its assertion polarity is programmable with the default polarity to be active low. I/O IPD/O IPD/O IPD/O 60 RXD5_7 IPD/O 61 GNDD GND 5 5 5 5 GMII: Port 5 switch receive bit [4]. RGMII/MI/RMII: No connection. GMII: Port 5 switch receive bit [5]. RGMII/MII/RMII: No connection. GMII: Port 5 switch receive bit [6]. RGMII/MII/RMII: No connection. GMII: Port 5 switch receive bit [7]. RGMII/MII/RMII: No connection. Digital ground. Port 2 LED Indicator 1. See global Register 11 bits [5:4] for details. Strap option: Port 5 GMII/MII and RMII mode select When Port 5 is GMII/MII mode: PU = GMII/MII is in GMAC/MAC mode. (default) PD = GMII/MII is in GPHY/PHY mode. 62 LED2_1 IPU/O 2 Note: When set GMAC5 GMII to GPHY mode, the CRS and COL pins will change from the input to output. When setting MII to PHY mode, the CRS, COL, RXC, and TXC pins will change from the input to output. When Port 5 is RMII mode: PU = Clock mode in RMII, using 25MHz OSC clock and provide 50MHz RMII clock from Pin RXC5. PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the Port 5 RMII will receive an external 50MHz clock Note: Port 5 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit[7]. July 23, 2014 15 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Description (Continued) Pin Number Pin Name Type (1) Port Pin Function (2) Port 2 LED Indicator 0. See global Register 11 bits [5:4] for details. Strap option: REFCLKO enable 63 LED2_0 IPU/O 2 PU = REFCLK_O (25MHz) is enabled. (default) PD = REFCLK_O is disabled Note: It is better to disable this 25MHz clock if not providing an extra 25MHz clock for system. Port 1 LED Indicator 1. See global Register 11 bits [5:4] for details. Strap option: PLL clock source select 64 LED1_1 IPU/O 1 PU = Still use 25MHz clock from XI/XO pin even though it is in port 5 RMII normal mode (default). PD = Use external clock from pin TXC5 in Port 5 RMII normal mode. Note: If received clock in Port 5 RMII normal mode has too much clock jitter, you still can select the 25MHz crystal/oscillator as the switch’s clock source. Port 1 LED Indicator 0. See global Register 11 bits [5:4] for details. Strap option: Speed select in Port 5 GMII/RGMII 65 LED1_0 IPU/O 1 PU = 1Gbps in GMII/RGMII.(default) PD = 10/100Mbps in GMII/RGMII. Note: Programmable through internal registers also. SPI Serial Data Output in SPI Slave Mode. Strap option: Serial bus configuration 66 SPIQ IPD/O All PD = SPI slave mode. PU = MDC/MDIO mode. Note: An external pull-up or pull-down resistor is required. 67 SCL_MDC IPU All Clock Input for SPI or MDC/MDIO Interface. 1. Input clock up to 50MHz in SPI slave mode. 2. Input clock up to 25MHz in MDC/MDIO for MIIM access. 68 SDA_MDIO IPU/O All Data for SPI or MDC/MDIO Interface. 1. Serial data input in SPI slave mode. 2. MDC/MDIO interface data input/output. SPI Slave Mode Chip Select (Active Low) SPIS_N IPU 70 VDDIO P 71 GNDD GND Digital ground. 72 RST_N IPU Reset This active low signal resets the hardware in the device. See the timing requirements in the Timing Diagram section. July 23, 2014 All SPI data transfer start in SPI slave mode. When SPIS_N is high, the KSZ8765CLX is deselected and SPIQ is held in the high impedance state. A high-to-low transition initiates the SPI data transfer. This pin is active low. 69 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 16 Revision 1.0 Micrel, Inc. KSZ8765CLX Pin Description (Continued) Type (1) Port Pin Function (2) Pin Number Pin Name 73 VDD12D P 74 FXSD2 I 2 Fiber signal detect pin for Port 2. 75 FXSD1 I 1 Fiber signal detect pin for Port 1. 76 VDDAT P 77 ISET 78 GNDA 1.2V core power. 3.3V analog power Transmit Output Current Set This pin configures the physical transmit output current. It should be connected to GND thru a 12.4kΩ 1% resistor. GND Analog ground. 79 XI I Crystal Clock Input/Oscillator Input When using a 25MHz crystal, this input is connected to one end of the crystal circuit. When using a 3.3V oscillator, this is the input from the oscillator. The crystal or oscillator should have a tolerance of ±50ppm. 80 XO O Crystal Clock Output When using a 25MHz crystal, this output is connected to one end of the crystal circuit. July 23, 2014 17 Revision 1.0 Micrel, Inc. KSZ8765CLX Strap-In Options The KSZ8765CLX can function as a managed switch and utilizes strap-in pins to configure the device for different modes. The strap-in option pins are configured by using external pull-up/down resistors to create a high or low state on the pins which are sampled during the power down reset or warm reset. The functions are described in the table below. Pin Number 63 Pin Name LED2_0 (3) PU/PD IPU/O Description REFCLKO Enable Strap Option: PU = REFCLK_O (25MHz) is enabled. (default) PD = REFCLK_O is disabled Port 5 GMII/MII and RMII Mode Select Strap Option: When Port 5 is GMII/MII mode: PU = GMII/MII is in GMAC/MAC mode. (default) PD = GMII/MII is in GPHY/PHY mode. 62 LED2_1 IPU/O Note: When setting GMAC5 GMII to GPHY mode, the CRS and COL pins will change from the input to output. When setting MII to PHY mode, the CRS, COL, RXC, and TXC pins will change from the input to output. When Port 5 is RMII mode: PU = Clock mode in RMII, using 25MHz OSC clock and provide 50MHz RMII clock from pin RXC5. PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the port 5 RMII will receive an external 50MHz clock Note: Port 5 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit[7]. Switch Port 5 GMAC5 Interface Mode Select Strap Option: 24,25 LED3[1,0] IPU/O 00 = MII for SW5-MII 01 = RMII for SW5-RMII 10 = GMII for SW5-GMII 11 = RGMII for SW5-RGMII (default) Note: 3. IPD/O = Input with internal pull-down during reset, output pin otherwise. IPU/O = Input with internal pull-up during reset, output pin otherwise. July 23, 2014 18 Revision 1.0 Micrel, Inc. KSZ8765CLX Strap-In Options (Continued) Pin Number Pin Name (3) PU/PD Description Port 5 Gigabit Select Strap Option: 65 LED1_0 IPU/O PU = 1Gbps in GMII/RGMII (default). PD = 10/100Mbps in GMII/RGMII. Note: Also programmable through internal register. PLL Clock Source Select Strap Option: 64 LED1_1 IPU/O PD = Still uses 25MHz clock from XI/XO pin even though it is in Port 5 RMII normal mode (default). PU = Uses external clock from TXC5 pin in Port 5 RMII normal mode. Note: If received clock in Port 5 RMII normal mode has too much clock jitter, you still can select the 25MHz crystal/oscillator as the switch’s clock source. Serial Bus Configuration Strap Option: 66 SPIQ IPD/O PD = SPI slave mode. (default) PU = MDC/MDIO mode. Note: An external pull-up or pull-down resistor is required. July 23, 2014 19 Revision 1.0 Micrel, Inc. KSZ8765CLX Introduction The KSZ8765CLX contains four 10/100 physical layer transceivers, four media access control (MAC) units, and one Gigabit media access control (GMAC) units with an integrated Layer 2-managed switch. The device runs in two modes. The first mode is as a four-port standalone switch. The second is as a five-port switch where the fifth port is provided through a Gigabit media independent interface that supports GMII, RGMII, MII, and RMII. This is useful for implementing an integrated broadband router. The KSZ8765CLX has the flexibility to reside in a managed mode. In a managed mode, a host processor has complete control of the KSZ8765CLX via the SPI bus or the MDC/MDIO interface. On the media side, the KSZ8765CLX supports IEEE 802.3 100Base-FX on Port 1 and Port 2 fiber ports and 10/100BASET/TX on Port 3 and Port 4 copper ports with Auto-MDI/MDI-X. The KSZ8765CLX can be used as a fully managed five-port switch or hooked up to a microprocessor via its SW-GMII/RGMII/MII/RMII interfaces to allow for integrating into a variety of environments. Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP technology that makes the design more efficient, allows for reduced power consumption, and smaller die size. Major enhancements from the KSZ8995FQ and KS8895FMQ to the KSZ8765CLX include more host interface options such as the GMII and RGMII interfaces, power saving features such as IEEE 802.1az energy-efficient Ethernet (EEE), MLD snooping, wake-on-LAN (WoL), port-based ACL filtering for port security, enhanced QoS priority, rapid spanning tree, IGMP snooping, port mirroring support, and flexible rate limiting. Functional Overview: Physical Layer (PHY) 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for intersymbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KSZ8765CLX generates 125MHz, 83MHz, 41MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. July 23, 2014 20 Revision 1.0 Micrel, Inc. KSZ8765CLX Scrambler/Descrambler (100BASE-TX Only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the same sequence at the transmitter. 100BASE-FX Operation 100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode, the auto-negotiation feature is bypassed because there is no standard that supports fiber auto-negotiation regardless auto-negotiation to be enabled or disabled. 100BASE-FX Signal Detection The physical port runs in 100BASE-FX fiber mode for the Port 1 and Port 2 of the KSZ8765CLX. This signal is internally referenced to 1.7V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.8V reference, indicating signal detect, and FXSDx ‘L’ is below the 1.7V reference to indicate no signal. There is no autonegotiation for 100BASE-FX mode, the ports must be forced to either 100/full-duplex or 100/half-duplex for the fiber ports. 100BASE-FX Far End Fault Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 ones followed by a zero in the idle period between frames. 10BASE-T Transmit The 10BASE-T output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffers and level-detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into a clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse-widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8765CLX decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. MDI/MDI-X Auto Crossover To eliminate the need for crossover cables between similar devices, the KSZ8765CLX supports HP Auto-MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto-MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KSZ8765CLX device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the Port control registers, or MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are in the table below. Table 1. MDI/MDI-X Pin Definitions MDI MDI-X RJ-45 Pins Signals RJ-45 Pins Signals 1 TD+ 1 RD+ 2 TD- 2 RD- 3 RD+ 3 TD+ 6 RD- 6 TD- July 23, 2014 21 Revision 1.0 Micrel, Inc. KSZ8765CLX Straight Cable A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC (MDI) and a switch or hub (MDI-X). Figure 3. Typical Straight Cable Connection Crossover Cable A crossover cable connects an MDI device to another MDI device or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). Figure 4. Typical Crossover Cable Connection July 23, 2014 22 Revision 1.0 Micrel, Inc. KSZ8765CLX Auto-Negotiation The KSZ8765CLX conforms to the auto-negotiation protocol as described by the IEEE 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. Auto-negotiation is supported only for the copper ports. The following list shows the speed and duplex operation mode from highest to lowest.  Highest: 100Base-TX, full-duplex  High: 100Base-TX, half-duplex  Low: 10Base-T, full-duplex  Lowest: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8765CLX link partner is forced to bypass auto-negotiation, the KSZ8765CLX sets its operating mode by observing the signal at its receiver. This is known as parallel detection and allows the KSZ8765CLX to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart. Figure 5. Auto-Negotiation and Parallel Operation July 23, 2014 23 Revision 1.0 Micrel, Inc. KSZ8765CLX ® LinkMD Cable Diagnostics ® The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable digital format. Please note that cable diagnostics are only valid for copper connections. Access LinkMD is initiated by accessing the PHY’s special control/status Registers {58, 74} and the LinkMD result Registers {59, 75} for Ports 3 and 4 respectively and in conjunction with the Port control 10 Register for Ports 3 and 4 respectively to disable Auto-MDI/MDI-X. Alternatively, the MIIM PHY Registers 0 and 1d can also be used for LinkMD access. Usage The following is a sample procedure for using LinkMD with Registers {58, 59, 61} on Port 3. 1. Disable Auto-MDI/MDI-X by writing a ‘1’ to Register 61, bit [2] to enable manual control over the differential pair used to transmit the LinkMD pulse. 2. Start cable diagnostic test by writing a ‘1’ to Register 58, bit [4]. This enable bit is self-clearing. 3. Wait (poll) for Register 58, bit [4] to return a ‘0’, and indicating cable diagnostic test is completed. 4. Read cable diagnostic test results in Register 58, bits [6:5]. The results are as follows:  00 = normal condition (valid test)  01 = open condition detected in cable (valid test)  10 = short condition detected in cable (valid test)  11 = cable diagnostic test failed (invalid test) The ‘11’ case, invalid test, occurs when the KSZ8765CLX is unable to shut down the link partner. In this instance, the test is not run because it would be impossible for the KSZ8765CLX to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenating Register 58, bit [0] and Register 59, bits [7:0] and multiplying the result by a constant of 0.4. The distance to the cable fault can be determined by the following formula: D (distance to cable fault meter) = 0.4 x (Register 58, bit [0], Register 59, bits [7:0]) D (distance to cable fault) is expressed in meters. Concatenated value of Registers 58 bit [0] and 59 bits [7:0] should be converted to decimal before multiplying by 0.4. The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. For Port 4 and using the MIIM PHY registers, LinkMD usage is similar. July 23, 2014 24 Revision 1.0 Micrel, Inc. KSZ8765CLX ® A LinkMD Example ® The following is a sample procedure for using LinkMD on Port 3 and Port 4. //Disable Auto-MDI/MDI-X and force to MDI-X mode //’w’ is WRITE the register. ‘r’ is READ register below w 3d 04 w 4d 04 //Set internal registers temporary by indirect registers, adjust for LinkMD w 6e a0 w 6f 4d w a0 80 //Enable LinkMD testing with fault cable for Port 1, Port 2, Port 3 and Port 4 w 3a 10 w 4a 10 //Wait until Port Register Control 8 bit [4] returns a ‘0’ (self-clear) //Diagnosis results r 3a r 3b r 4a r 4b //For example on Port 3, the result analysis based on the values of the register 0x3a and 0x3b //The register 0x3a bits [6-5] are for the open or the short detection. //The register 0x3a bit [0] + the register 0x3b bits [7-0] = CDT_Fault_Count [8-0] //The distance to fault is about 0.4 x (CDT_Fault_Count [8-0]) On-Chip Termination and Internal Biasing The KSZ8765CLX reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without external termination resistors. The combination of the on-chip termination and the internal biasing will save more PCB space and power consumption in system, compared with using external biasing and termination resistors for multiple ports’ switches because the transformers do not consume power anymore. The center taps of the transformer should not need to be tied to the analog power. July 23, 2014 25 Revision 1.0 Micrel, Inc. KSZ8765CLX Functional Overview: Media Access Controller (MAC) Media Access Controller Operation The KSZ8765CLX strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KSZ8765CLX implements the IEEE 802.3 standard binary exponential backoff algorithm and optional “aggressive mode” backoff. After 16 collisions, the packet will optionally be dropped depending upon the chip configuration in Register 3. Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KSZ8765CLX discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KSZ8765CLX can also be programmed to accept frames up to 2k bytes in Register 3 bit [6]. Because the KSZ8765CLX supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KSZ8765CLX supports standard IEEE 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8765CLX receives a pause control frame, the KSZ8765CLX will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow-controlled), only flow control packets from the KSZ8765CLX will be transmitted. On the transmit side, the KSZ8765CLX has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues, and available receive queues. The KSZ8765CLX flow controls a port that has just received a packet if the destination port resource is busy. The KSZ8765CLX issues a flow control frame (XOFF) containing the maximum pause time defined in the IEEE 802.3x standard. Once the resource is freed up, the KSZ8765CLX sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent overactivation and deactivation of the flow control mechanism. The KSZ8765CLX flow controls all ports if the receive queue becomes full. July 23, 2014 26 Revision 1.0 Micrel, Inc. KSZ8765CLX Half-Duplex Back Pressure The KSZ8765CLX also provides a half-duplex back pressure option (this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KSZ8765CLX sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standards, after a certain period of time, the KSZ8765CLX discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier-sense-deferred state. If the port has packets to send during a back pressure situation, the carrier-sense-type back pressure is interrupted and those packets are transmitted instead. If there are no more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:  Aggressive backoff (Register 3, bit [0])  No excessive collision drop (Register 4, bit [3])  Back pressure (Register 4, bit [5]) These bits are not set as the default because this is not the IEEE standard. Broadcast Storm Protection The KSZ8765CLX has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources (bandwidth and available space in transmit queues). The KSZ8765CLX has the option to include multicast packets for storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per port basis. The rate is based on a 50ms (0.05s) interval for 100BT and a 500ms (0.5s) interval for 10BT. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows: 148,80 frames/sec × 50ms (0.05s)/interval × 1% = 74 frames/interval (approx.) = 0x4A July 23, 2014 27 Revision 1.0 Micrel, Inc. KSZ8765CLX Functional Overview: Switch Core The internal look-up table stores MAC addresses and their associated information. It contains a 1k unicast address table plus switching information. The KSZ8765CLX is guaranteed to learn 1k addresses and distinguishes itself from a hashbased look-up table, which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine updates its table with a new entry if the following conditions are met:  The received packet’s source address (SA) does not exist in the look-up table.  The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full then the last entry of the table is deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly. Migration happens when the following conditions are met:  The received packet’s SA is in the table, but the associated source port information is different.  The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 ±75 seconds. This feature can be enabled or disabled through Register 3 bit [2]. Forwarding The KSZ8765CLX will forward packets using an algorithm that is depicted in the following flowcharts. The next figure shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and then comes up with port to forward 1 (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes and authentication to come up with port to forward 2 (PTF2), as shown in the figure below. The authentication and ACL have highest priority in the forwarding process, ACL result will overwrite the result of the forwarding process. This is where the packets will be sent. The KSZ8765CLX will not forward the following packets:  Error packets: These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal size packet errors.  IEEE 802.3x PAUSE frames: KSZ8765CLX intercepts these packets and performs full-duplex flow control accordingly.  Local packets: Based on destination address (DA) lookup, if the destination port from the look-up table matches the port from which the packet originated, the packet is defined as local. July 23, 2014 28 Revision 1.0 Micrel, Inc. KSZ8765CLX Figure 6. Destination Address Look-up and Resolution Flow Chart Switching Engine The KSZ8765CLX features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward modes, while the efficient switching mechanism reduces overall latency. The KSZ8765CLX has a 64kb internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers available. Each buffer is sized at 128 bytes. July 23, 2014 29 Revision 1.0 Micrel, Inc. KSZ8765CLX Functional Overview: Power The KSZ8765CLX device requires 3.3V analog power. An external 1.2V LDO provides the necessary 1.2V to power the analog and digital logic cores. The various I/Os can be operated at 1.8V, 2.5V, and 3.3V. The table below illustrates the various voltage options and requirements of the device. Power Signal Name Device Pin Requirement VDDAT 2,12,76 3.3V input power to the analog blocks of transceiver in the device. VDDIO 34,48,70 Choice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input power pins power the I/O circuitry of the device. VDD12A 1 VDD12D 26, 42, 73 1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V to power the internal analog and digital cores. GNDA 3, 21, 78 Analog ground. GNDD 27, 33, 47, 61, 71 Digital ground. Functional Overview: Power Management The KSZ8765CLX supports enhanced power management in a low power state, with energy detection to ensure low power dissipation during device idle periods. There are three operation modes under the power management function which are controlled by the Register 14 bits [4:3] and the Port Control 10 Register bit [3] as shown below:  Register 14 bits [4:3] = 00 normal operation mode  Register 14 bits [4:3] = 01 energy detect mode  Register 14 bits [4:3] = 10 soft power-down mode  Register 14 bits [4:3] = 11 reserved The Port Control 10 Register 29, 45, 61, 77 bit [3] = 1 are for the port-based power-down mode. Table 2 indicates all internal function block statuses under four different power management operation modes. Table 2. Internal Function Block Status Power Management Operation Modes KSZ8765CLX Function Blocks Normal Mode Energy Detect Mode Soft Power-Down Mode Internal PLL Clock Enabled Disabled Disabled TX/RX PHY Enabled Energy detect at RX Disabled MAC Enabled Disabled Disabled Host Interface Enabled Disabled Disabled Normal Operation Mode This is the default setting bits [4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8765CLX is in normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is ready for CPU read or write. During normal operation mode, the host CPU can set the bits [4:3] in Register 14 to change the current normal operation mode to any one of the other three power management operation modes. Energy Detect Mode Energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8765CLX port is not connected to an active link partner. In this mode, the device will save more power when the July 23, 2014 30 Revision 1.0 Micrel, Inc. KSZ8765CLX cables are unplugged. If the cable is not plugged in, the device can automatically enter a low power state—the energy detect mode. In this mode, the device will keep transmitting 120ns-wide pulses at a rate of 1 pulse per second. Once activity resumes due to plugging in a cable or an attempt by the far end to establish a link, the device can automatically power up to normal power state in energy detect mode. Energy detect mode consists of the normal power state and low power state. While in low power state, the device reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bits [4:3] = 01 in Register 14. When the KSZ8765CLX is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bits [7:0] go-sleep time in Register 15, KSZ8765CLX will go into low power state. When KSZ8765CLX is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable, the device will enter normal power state. When the device is at normal power state, it is able to transmit or receive packet from the cable. Soft Power-Down Mode The soft power-down mode is entered by setting bits [4:3] = 10 in Register 14. When KSZ8765CLX is in this mode, all PLL clocks are disabled, also all of the PHYs and MACs are off. Any dummy host access will wake-up this device from current soft power-down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. Port-Based Power-Down Mode In addition, the KSZ8765CLX features a per-port power-down mode. To save power, a PHY port that is not in use can be powered down via the Port Control 10 Register bit [3] or MIIM PHY Register 0 bit [11]. Energy-Efficient Ethernet (EEE) Along with supporting different power saving modes, the KSZ8765CLX extends its green functionality by supporting EEE features defined in IEEE P802.3az, March 2010. Both 10Base-T and 100Base-TX EEE functions are supported in KSZ8765CLX. In 100Base-TX, the EEE operation is asymmetric on the same link, which means one direction could be in low power idle (LPI) state while another direction could handle packet transfer activity. Different from other types of power saving modes, EEE is able to maintain the link while conserving power. Based on IEEE specification, the energy saving from EEE is done at the PHY level. KSZ8765CLX reduces the power consumption not only at PHY level but also at MAC and switch level by shutting down the unused clocks as much as possible when the device is in low power idle phase. Figure 7. EEE Transmit and Receive Signaling Paths July 23, 2014 31 Revision 1.0 Micrel, Inc. KSZ8765CLX The KSZ8765CLX supports the IEEE 802.3az energy-efficient Ethernet standard for both 10 and 100Mbps interfaces. The EEE capability combines switch, MAC, and PHY to support operation in low power idle (LPI) mode. When the LPI mode is enabled, systems on both sides of the link can save power during periods of low link utilization. EEE implementation provides a protocol to coordinate transitions to or from lower power consumption without changing the link status and without dropping or corrupting frames. The transition time into and out of the lower power consumption is kept small enough to be transparent to upper layer protocols and applications. EEE specifies the means to exchange capabilities between link partners to determine whether EEE is supported and to select the best set of parameters common to both sides. Besides supporting the 100BASE-TX PHY EEE, KSZ8765CLX also supports 10BASE-T with reduced transmit amplitude requirements for 10Mbps mode to allow a reduction in power consumption. LPI Signalling Low power idle signaling allows the switch to indicate to the PHY, and to the link partner, that a break in the data stream is expected. The switch can use this information to enter power-saving modes that require additional time to resume normal operation. LPI signaling also informs the switch when the link partner has sent such an indication. The definition of LPI signaling uses the MAC for simplified full-duplex operation with carrier sense deferral. This provides full-duplex operation but uses the carrier sense signal to defer transmission when the PHY is in the LPI mode. The decision on when to signal LPI (LPI request) to the link partner is made by the switch and communicated to the PHY through the MAC MII interface. The switch is also informed when the link partner is signaling LPI and indicating LPI activation (LPI indication) on the MAC interface. The conditions under which the switch decides to send LPI and what actions are taken by the switch when it receives LPI from the link partner are specified in the implementation section. LPI Assertion Without LPI assertion, the normal traffic transition continues on the MII interface. As soon as an LPI request is asserted, the LPI assert function starts to transmit the “Assert LPI” encoding on the MII and stops the MAC from transmitting normal traffic. Once the LPI request is de-asserted, the LPI assert function starts to transmit the normal inter-frame encoding on the MII again. After a delay, the MAC is allowed to start transmitting again. This delay is provided to allow the link partner to prepare for normal operation. Figure 8 illustrates the EEE LPI between two active data idles. LPI Detection In the absence of “Assert LPI” encoding on the receive MII, the LPI detect function maps the receive MII signals as normal conditions. At the start of LPI, indicated by the transition from normal inter-frame encoding to the “Assert LPI” encoding on the receive MII, the LPI detect function continues to indicate idle on interface and asserts LP_IDLE indication. At the end of LPI, indicated by the transition from the “Assert LPI” encoding to any other encoding on the receive MII, LP_IDLE indication is de-asserted and the normal decoding operation resumes. PHY LPI Transmit Operation When the PHY detects the start of “Assert LPI” encoding on the MII, the PHY signals sleep to its link partner to indicate that the local transmitter is entering LPI mode. The EEE capability requires the PHY transmitter to go quiet after sleep is signaled. LPI requests are passed from one end of the link to the other and system energy savings can be achieved even if the PHY link does not go into a low power mode. The transmit function of the local PHY is enabled periodically to transmit refresh signals that are used by the link partner to update adaptive filters and timing circuits in order to maintain link integrity. This quiet-refresh cycle continues until the reception of the normal inter-frame encoding on the MII. The transmit function in the PHY communicates this to the link partner by sending a wake signal for a predefined period of time. The PHY then enters the normal operating state. No data frames are lost or corrupted during the transition to or from the LPI mode. In 100BT/full-duplex EEE operation, refresh transmissions are used to maintain the link and the quiet periods are used for power saving. Approximately every 20-22ms a refresh of 200-220µs is sent to the link partner. The refresh transmission and quiet periods are shown in Figure 8. July 23, 2014 32 Revision 1.0 Micrel, Inc. KSZ8765CLX Figure 8. Traffic Activity and EEE LPI Operations PHY LPI Receive Operation On receive, entering the LPI mode is triggered by the reception of a sleep signal from the link partner, which indicates that the link partner is about to enter the LPI mode. After sending the sleep signal, the link partner ceases transmission. When the receiver detects the sleep signal, the local PHY indicates “Assert LPI” on the MII and the local receiver can disable some functionality to reduce power consumption. The link partner periodically transmits refresh signals that are used by the local PHY. This quiet-refresh cycle continues until the link partner initiates transition back to normal mode by transmitting the wake signal for a predetermined period of time controlled by the LPI assert function. This allows the local receiver to prepare for normal operation and transition from the “Assert LPI” encoding to the normal inter-frame encoding on the MII. After a system-specified recovery time, the link supports the nominal operational data rate. Negotiation with EEE Capability The EEE capability is advertised during the auto-negotiation stage. Auto-negotiation provides a linked device with the capability to detect the abilities supported by the device at the other end of the link, determine common abilities, and configure for joint operation. Auto-negotiation is performed at power-up or reset, on command from management, due to link failure, or due to user intervention. During auto-negotiation, both link partners indicate their EEE capabilities. EEE is supported only if both the local device and link partner advertise the EEE capability for the resolved PHY type during auto-negotiation. If EEE is not supported, all EEE functionality is disabled and the LPI client does not assert LPI. If EEE is supported by both link partners for the negotiated PHY type, then the EEE function can be used independently in either direction. Wake-on-LAN (WoL) Wake-on-LAN allows a computer to be turned on or woken up by a network message. The message is usually sent by a program executed on another computer on the same local area network. Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet™, a management request from a remote administrator, or simply network traffic directly targeted to the local system. The KSZ8765CLX can be programmed to notify the host of the Wake-up frame detection with the assertion of the interrupt signal (INTR_N) or assertion of the power management event (PME) signal. The PME control is by PME indirect registers. KSZ8765CLX MAC supports the detection of the following wake-up events:  Detection of an energy signal over a pre-configured value: Port PME Control Status Register bit [0] in PME indirect registers.  Detection of a link-up in the network link state: Port PME Control Status Register bit [1] in the PME indirect registers.  Receipt of a Magic Packet: Port PME Control Status Register bit [2] in the PME indirect registers. July 23, 2014 33 Revision 1.0 Micrel, Inc. KSZ8765CLX There are also other types of Wake-up events that are not listed here as manufacturers may choose to implement these in their own ways. Direction of Energy Energy is detected from the cable and is continuously presented for a time longer than the pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. Direction of Link-up Link status wake events are useful to indicate a link-up in the network’s connectivity status. Magic Packet™ The Magic Packet™ is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF) followed by sixteen repetitions of the target computer's 48-bit DA MAC address. Because the Magic Packet is only scanned for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer protocol. Magic Packet technology is used to remotely wake up a sleeping or powered-off PC on a LAN. This is accomplished by sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller. When the LAN controller receives a Magic Packet frame, it will alert the system to wake up. Once the KSZ8765CLX has been enabled for Magic Packet detection in Port PME Control Mask Register bit [2] in the PME indirect register, it scans all incoming frames addressed to the node for a specific data sequence that indicates to the controller this is a Magic Packet frame. A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as source address (SA), destination address (DA), which may be the receiving station’s IEEE MAC address, or a multicast or broadcast address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the address of the machine to be awakened. Example of Magic Packet: If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scanning for the data sequence (assuming an Ethernet frame): DA - SA - TYPE - FF FF FF FF FF FF - 11 22 33 44 55 66 -11 22 33 44 55 66-11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 3344 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 MISC-CRC. There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the frame’s destination. If the scans do not find the specific sequence shown above, it discards the frame and takes no further action. However, if the KSZ8765CLX detects the data sequence, it then alerts the PC’s power management circuitry (asserts the PME pin) to wake up the system. Interrupt (INT_N/PME_N) INT_N is an interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8765CLX interrupt status register. Bits [3:0] of Register 125 are the interrupt mask control bits to enable and disable the conditions for asserting the INT_N signal. Bits [3:0] of Register 124 are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading those bits in the Register 124. PME_N is an optional PME interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8765CLX interrupt status register. Bits [4] of Register 125 are the PME mask control bits to enable and disable the conditions for asserting the PME_N signal. Bits [4] of Register 124 are the PME interrupt status bits to indicate which PME interrupt conditions have occurred. The PME interrupt status bit [4] is cleared after reading this bit of the Register 124. Additionally, the interrupt pins of INT_N and PME_N eliminate the need for the processor to poll the switch for status change. July 23, 2014 34 Revision 1.0 Micrel, Inc. KSZ8765CLX Functional Overview: Interfaces The KSZ8765CLX device incorporates a number of interfaces that enable it to be designed into a standard network environment as well as a vendor-unique environment. The available interfaces are summarized in the table below. The detail of each usage in this table is provided in the sections that follow. Table 3. Available Interfaces Registers Accessed Interface Type Usage SPI Configuration and Register Access [As Slave Serial Bus] - External CPU or controller can R/W all internal registers through this interface. MIIM Configuration and Register Access MDC/MDIO-capable CPU or controllers can R/W 4 PHYs registers. GMII Data Flow Interface to the Port 5 GMAC using the standard GMII timing. N/A MII Data Flow Interface to the Port 5 GMAC using the standard MII timing. N/A RGMII Data Flow Interface to the Port 5 GMAC using the faster reduced GMII timing. N/A RMII Data Flow Interface to the Port 5 GMAC using the faster reduced MII timing. N/A All PHYs Only Configuration Interface SPI Slave Serial Bus Configuration The KSZ8765CLX can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including VLAN, IGMP snooping, MIB counters, and more. The external master device can access any register from Register 0 to Register 127 randomly. The system should configure all the desired settings before enabling the switch in the KSZ8765CLX. To enable the switch, write a "1" to Register 1 bit [0]. Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed configuration time, the KSZ8765CLX also supports multiple reads or writes. After a byte is written to or read from the KSZ8765CLX, the internal address counter automatically increments if the SPI slave select signal (SPIS_N) continues to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the master out slave input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low again before issuing another command and address. The address counter wraps back to zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a single command and address. The KSZ8765CLX is able to support a SPI bus up to 50MHz. A high performance SPI master is recommended to prevent internal counter overflow. To use the KSZ8765CLX SPI: 1. At the board level, connect the KSZ8765CLX pins as follows. Table 4. SPI Connections KSZ8765CLX Signal Name Microprocessor Signal Description SPIS_N (S_CS) SPI slave select SCL (S_CLK) SPI clock SDA (S_DI) Master out. Slave input. SPIQ (S_DO) Master input. Slave output. July 23, 2014 35 Revision 1.0 Micrel, Inc. KSZ8765CLX 2. Configure the serial communication to SPI slave mode by pulling down pin SPIQ with a pull-down resistor. 3. Write configuration data to registers using a typical SPI write data cycle as shown in Figure 9 or SPI multiple write as shown in Figure 10. Note that data input on SDA is registered on the rising edge of SCL clock. 4. Registers can be read and the configuration can be verified with a typical SPI read data cycle as shown in Figure 9 or a multiple read as shown in Figure 10. Note that read data is registered out of SPIQ on the falling edge of SCL clock. Figure 9. SPI Access Timing July 23, 2014 36 Revision 1.0 Micrel, Inc. KSZ8765CLX Figure 10. SPI Multiple Access Timing July 23, 2014 37 Revision 1.0 Micrel, Inc. KSZ8765CLX MII Management Interface (MIIM) The KSZ8765CLX supports the standard IEEE 802.3 MII management interface, also known as the management data input/output (MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8765CLX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further details on the MIIM interface are found in clause 22.2.4.5 of the IEEE 802.3u specification. The MIIM interface consists of the following:  A physical connection that incorporates the data line MDIO and the clock line MDC.  A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8765CLX device.  Access to a set of eight 16-bit registers, consisting of eight standard MIIM Registers [0:5h], 1d and 1f MIIM registers per port. The MIIM interface can operate up to a maximum clock speed of 25MHz MDC clock. The following table depicts the MII management interface frame format. Table 5. MII Management Interface Frame Format (4) Preamble Start of Frame Read/Write OP Code PHY Address Bits[4:0] REG Address Bits[4:0] TA Data Bits[15:0] Idle Read 32 1s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z Note: 4. Preamble: Consists of 32 1s Start of Frame: The start of frame is indicated by a 01 pattern. This pattern assures transitions from the default logic one line state to zero and back to one. OP Code: The operation code for a read transaction is 10, while the operation code for a write transaction is 01. PHY Address: The PHY address is five bits, allowing 32 unique PHY addresses. The first PHY address bit transmitted and received is the MSB of the address. REG Address: The register address is five bits, allowing 32 individual registers to be addressed within each PHY. The first register address bit transmitted and received is the MSB of the address. TA: The turnaround (TA) time is 2-bit time spacing between the register address field and the data field of a frame to avoid contention during a read transaction. For a read transaction, both the master and the PHYs shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shall drive a 0 bit during the second bit time of the turnaround of a read transaction. During a write transaction, the master shall drive a 1 bit for the first bit time of the turnaround and a 0 bit for the second bit time of the turnaround. DATA: The data field is 16 bits. The first data bit transmitted and received shall be bit 15 of the register being addressed. At the beginning of each transaction, the master device shall send a sequence of 32 contiguous logic 1 bits on MDIO with 32 corresponding cycles on MDC as a clock to provide the device with a pattern that it can use to establish synchronization. The device starts respond to any transaction only after observes a sequence of 32 contiguous 1 bits on MDIO with 32 corresponding cycles on MDC. The MIIM interface does not have access to all the configuration registers in the KSZ8765CLX. It can only access the standard MIIM registers. See MIIM Registers. The SPI interface, on the other hand, can be used to access all registers with the entire KSZ8765CLX feature set. July 23, 2014 38 Revision 1.0 Micrel, Inc. KSZ8765CLX Switch Port 5 GMAC Interface The KSZ8765CLX GMAC5 interface supports four GMII/MII/RGMII/RMII interface protocols and shares one set of input/output signals. The purpose of this interface is to provide a simple, inexpensive, and easy-to-implement interconnection between the GMAC/MAC sub-layer and a GPHY/PHY. Data on these interfaces are framed using the IEEE Ethernet standard. As such, it consists of a preamble, start of frame delimiter, Ethernet headers, protocol-specific data, and a cyclic redundancy check (CRC) checksum. Transmit and receive signals for GMII/MII/RGMII/RMII interfaces are shown in the table below. Table 6. Signals of GMII/RGMII/MII/RMII Direction Type GMII RGMII MII RMII Input (Output) GTXC GTXC Input TXER TXC REFCLKI Input TXEN Input (Output) COL Input TXD[7:0] TXD[3:0] TXD[3:0] TXD[1:0] Input (Output) GRXC GRXC RXC RXC Output RXER RXER RXER Output RXDV RXDV CRS_DV Input (Output) CRS Output RXD[7:0] TXER TXD_CTL TXEN TXEN COL RXD_CTL CRS RXD[3:0] RXD[3:0] RXD[1:0] Standard GMII/MII Interface For MII and GMII, the interface is capable of supporting 10/100Mbps and 1000Mbps operation. Data and delimiters are synchronous to clock references. It provides independent four-bit-wide (MII) or eight-bit-wide (GMII) transmit and receive data paths and uses signal levels; two media status signals are also provided. The CRS indicates the presence of carrier, and the COL indicates the occurrence of a collision. Both half- and full-duplex operations are provided by MII and fullduplex operation is used for GMII. GMII is based on MII. MII signal names have been retained and the functions of most signals are the same, but additional valid combinations of signals have been defined for 1000Mbps operation. GMII supports only 1000Mbps operation. Operation at 10Mbps and 100Mbps is supported by the MII interface. MII transfers data using 4-bit words (nibble) in each direction And is clocked at 2.5/25MHz to achieve the speed of 10/100Mbps. GMII transfers data using 8-bit words (nibble) in each direction, clocked at 125MHz to achieve 1000Mbps speed. Reduced Gigabit Media Independent Interface (RGMII) RGMII is intended to be an alternative to the IEEE 802.3u MII and the IEEE 802.3z GMII. The principle objective is to reduce the number of pins required to interconnect the GMAC and the GPHY in a cost-effective and technologyindependent manner. In order to accomplish this, the data paths and all associated control signals are reduced, control signals are multiplexed together, and both edges of the clock are used. For Gigabit operation, the clocks operate at 125MHz with the rising edge and falling edge used to latch the data. Reduced Media Independent Interface (RMII) RMII specifies a low pin count media independent interface (MII). The KSZ8765CLX supports the RMII interface on the Port 5 GMAC5 and provides the following key characteristics:  Supports 10Mbps and 100Mbps data rates. July 23, 2014 39 Revision 1.0 Micrel, Inc. KSZ8765CLX  Uses a single 50MHz clock reference (provided internally or externally). In internal mode, the chip provides a reference clock from the RXC5 to the opposite clock input pin for RMII interface. In external mode, the chip receives 50MHz reference clock from an external oscillator or opposite RMII interface.  Provides independent 2-bit wide (bi-bit) transmit and receive data paths. Port 5 GMAC5 SW5-MII Interface The table below shows two connection methods. The first is an external MAC connecting in SW5-MII PHY mode. The second is an external PHY connecting in SW5-MII MAC mode. The MAC mode or PHY mode setting is determined by the strap Pin 62 LED2_1. Table 7. Port 5 SW5-MII Connection MAC-to-MAC Connection KSZ8765CLX MAC5 SW5-MII PHY Mode MAC-to-PHY Connection KSZ8765CLX MAC5 SW5-MII MAC Mode External MAC SW5-MII Signals Type Description External PHY SW5-MII Signals Type MTXEN TXEN5 Input Transmit Enable MTXEN RXDV5 Output MTXER TXER5 Input Transmit Error MTXER RXER5 Output MTXD[3:0] TXD5[3:0] Input Transmit Data Bit[3:0] MTXD[3:0] RXD5[3:0] Output MTXC TXC5 Output Transmit Clock MTXC RXC5 Input MCOL COL5 Output Collision Detection MCOL COL5 Input MCRS CRS5 Output Carrier Sense MCRS CRS5 Input MRXDV RXDV5 Output Receive Data Valid MRXDV TXEN5 Input MRXER RXER5 Output Receive Error MRXER TXER5 Input MRXD[3:0] RXD5[3:0] Output Receive Data Bit[3:0] MRXD[3:0] TXD5[3:0] Input MRXC RXC5 Output Receive Clock MRXC TXC5 Input The MII interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a COL signal that indicates a collision has occurred during transmission. Note: Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing with the KSZ8765CLX has an MRXER pin, it can be tied low. For MAC mode operation with an external PHY, if the device interfacing with the KSZ8765CLX has an MTXER pin, it can be tied low. July 23, 2014 40 Revision 1.0 Micrel, Inc. KSZ8765CLX Port 5 GMAC5 SW5-GMII Interface The table below shows two connection methods. The first is an external GMAC connecting in SW5-GMII GPHY mode. The second is an external GPHY connecting in SW5-GMII GMAC mode. The MAC mode or PHY mode setting is determined by the strap Pin 62 LED2_1. Table 8. Port 5 SW5-GMII Connection GMAC-to-GMAC Connection KSZ8765CLX GMAC5 SW5-GMII GPHY Mode GMAC-to-GPHY Connection KSZ8765CLX GMAC5 SW5-GMII GMAC Mode External GMAC SW5-GMII Signals Type Description External GPHY SW5-GMII Signals Type MRXDV TXEN5 Input Transmit Enable MTXEN RXDV5 Output MRXER TXER5 Input Transmit Error MTXER RXER5 Output MRXD[7:0] TXD5[7:0] Input Transmit Data Bit[3:0] MTXD[7:0] RXD5[7:0] Output MGRXC GTXC5 Input Transmit Clock MGTXC GRXC5 Output MCOL COL5 Output Collision Detection MCOL COL5 Input MCRS CRS5 Output Carrier Sense MCRS CRS5 Input MRXEN RXDV5 Output Receive Data Valid MRXDV TXEN5 Input MTXER RXER5 Output Receive Error MRXER TXER5 Input MRXD[7:0] RXD5[3:0] Output Receive Data Bit[3:0] MRXD[7:0] TXD5[7:0] Input MGRXC GRXC5 Output Receive Clock MGRXC GTXC5 Input The Port 5 GMAC5 SW5-GMII interface operates at up to 1Gbps. In 1Gbps mode, GMII supports the full-duplex only. The GMII interface is 8-bits of data in each direction. Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation in 10/100Mbps mode, there is a COL signal that indicates a collision has occurred during transmission. Port 5 GMAC5 SW5-RGMII Interface The table below shows the RGMII reduced connections when connecting to an external GMAC or GPHY. Table 9. Port 5 SW5-RGMII Connection KSZ8765CLX SW5-RGMII Connection External GMAC/GPHY SW5-RGMII Signals Type Description MRX_CTL TXD5_CTL Input Transmit Control MRXD[3:0] TXD5[3:0] Input Transmit Data Bit[3:0] MRX_CLK GTX5_CLK Input Transmit Clock MTX_CTL RXD5_CTL Output Receive Control MTXD[3:0] RXD5[3:0] Output Receive Data Bit[3:0] MGTX_CLK GRXC5 Output Receive Clock July 23, 2014 41 Revision 1.0 Micrel, Inc. KSZ8765CLX The RGMII interface operates at up to a 1Gbps speed rate. Additional transmit and receive signals control the different directions of data transfer. This RGMII interface supports RGMII Rev. 2.0 with adjustable ingress clock and egress clock delay by Register 86 (0x56). For proper RGMII configuration with the connection partner, the Register 86 (0x56) bits [4:3] need to setup correctly. A configuration table is shown below. Table 10. Port 5 SW5-RGMII Clock Delay Configuration with Connection Partner KSZ8765 Register 86 Bits [4:3] Configuration Bit [4:3] = 11 Mode Bit [4:3] = 10 Mode Bit [4:3] = 01 Mode Bit [4:3] = 00 Mode RGMII Clock Mode (Receive and Transmit) KSZ8765 Register 86 (0x56) KSZ8765 RGMII Clock Delay/Slew Configuration Connection Partner RGMII Clock (5) Configuration Ingress Clock Input Bit [4] = 1 Delay No Delay Egress Clock Output Bit [3] = 1 Delay No Delay Ingress Clock Input Bit [4] = 1 Delay No Delay Egress Clock Output Bit [3] = 0 No Delay Delay Ingress Clock Input Bit [4] = 0 (default) No Delay Delay Egress Clock Output Bit [3] = 1 (default) Delay No Delay Ingress Clock Input Bit [4] = 0 No Delay Delay Egress Clock Output Bit [3] = 0 No Delay Delay Note: 5. A processor with RGMII, an external GPHY, or KSZ8765 back-to-back connection. For example, two KSZ8765 devices are the back-to-back connection. If one device set bit [4:3] = ’11’, another one should set bit [4:3] = ‘00’. If one device set bit [4:3] =’01’, another one should set bit [4:3] = ‘01’ too. The RGMII mode is configured by the strap-in Pin LED3 [1:0] = ’11’ (default) or Register 86 (0x56) bits [1:0] = ‘11’ (default). The speed choice is set by the strap-in pin LED1_0 or Register 86 (0x56) bit [6], the default speed is 1Gbps with bit [6] = ‘1’, set bit [6] = ‘0’ is for 10/100Mbps speed in RGMII mode. KSZ8765CLX provides Register 86 bits [4:3] with the adjustable clock delay and Register 164 bits [6:4] with the adjustable drive strength for best RGMII timing on board level in 1Gbps mode. Port 5 GMAC5 SW5-RMII Interface The reduced media independent interface (RMII) specifies a low pin count media independent interface (MII). The KSZ8765CLX supports RMII interface on Port 5 and provides the following key characteristics:  Supports 10Mbps and 100Mbps data rates.  Uses a single 50MHz clock reference (provided internally or externally): In internal mode, the chip provides a reference clock from the RXC5 pin to the opposite clock input pin for RMII interface when Port 5 RMII is set to clock mode.  In external mode, the chip receives 50MHz reference clock on the TXC5/REFCLKI5 pin from an external oscillator or opposite RMII interface when the device is set to normal mode.  Provides independent 2-bit wide (bi-bit) transmit and receive data paths. For the details of SW5-RMII (Port 5 GMAC5 RMII) signal connection, see the table below: When the device is strapped to normal mode, the reference clock comes from the TXC5/REFCLKI5 pin and will be used as the device’s clock source. The strap pin LED1_1 can select the device’s clock source either from the TXC5/REFCLKI5 pin or from an external 25MHz crystal/oscillator clock on the XI/XO pin. In internal mode, when using an internal 50MHz clock as SW5-RMII reference clock, the KSZ8765CLX Port 5 should be set to clock mode by the strap pin LED2_1 or the port Register 86 bit 7. The clock mode of the KSZ8765CLX device will provide the 50MHz reference clock to the Port 5 RMII interface. July 23, 2014 42 Revision 1.0 Micrel, Inc. KSZ8765CLX In external mode, when using an external 50MHz clock source as SW5-RMII reference clock, the KSZ8765CLX Port 5 should be set to normal mode by the strap pin LED2_1 or the port Register 86 bit 7. The normal mode of the KSZ8765CLX device will start to work when it receives the 50MHz reference clock on the TXC5/REFCLKI5 pin from an external 50MHz clock source. Table 11. Port 5 SW5-RMII Connection (6) MAC-to-MAC Connection KSZ8765CLX SW5-RMII PHY Mode MAC-to-PHY Connection KSZ8765CLX SW5-RMII MAC Mode External MAC SW5-RMII Signals Type Description External PHY SW5-RMII Signals Type REF_CLKI RXC5 Output 50MHz in Clock Mode Reference Clock 50MHz REFCLKI5 Input 50MHz in Normal Mode CRS_DV RXDV5/CRSDV5 Output Carrier Sense/Receive Data Valid CRS_DV TXEN5 Input Receive Error RXER TXER5 Input RXD[1:0] RXD5[1:0] Output Receive Data Bit[1:0] RXD[1:0] TXD5[1:0] Input TX_EN TXEN5 Input Transmit Data Enable TX_EN RXDV5/CRSDV5 Output TXD[1:0] TXD5[1:0] Input Transmit Data Bit 1 TXD[1:0] RXD5[1:0] Output 50MHz REFCLKI5 Input 50MHz in Clock Mode Reference Clock REF_CLKI RXC5 Output 50MHz in Clock Mode Note: 6. MAC/PHY mode in RMII is different from MAC/PHY mode in MII. There is no strap pin and register configuration request in RMII; just follow the singal connections in the table above. Functional Overview: Advanced Functionality QoS Priority Support The KSZ8765CLX provides quality of service (QoS) for applications such as VoIP and video conferencing. The KSZ8765CLX offers one, two, or four priority queues per port by setting the Port Control 13 Registers bit [1] and the Port Control 0 Registers bit [0]. The 1/2/4 queues split as follows.  [Port Control 9 Registers bit [1], Control 0 bit [0]] = 00 Single output queue as default.  [Port Control 9 Registers bit [1], Control 0 bit [0]] = 01 Egress port can be split into two priority transmit queues.  [Port Control 9 Registers bit [1], Control 0 bit [0]] = 10 Egress port can be split into four priority transmit queues. The four priority transmit queue is a new feature in the KSZ8765CLX. Queue 3 is the highest priority queue and Queue 0 is the lowest priority queue. The Port Control 9 Registers bit [1] and the Port Control 0 Registers bit [0] are used to enable split transmit queues for Ports 1, 2, 3, 4, and 5, respectively. If a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. There is an additional option to either always deliver high priority packets first or to use programmable weighted fair queuing for the four priority queue scale by the Port Control 14, 15, 16, and 17 Registers (default values are 8, 4, 2, 1 by their bits [6:0]. Register 130 bit [7:6] Prio_2Q[1:0] is used when the two-queue configuration is selected. These bits are used to map the 2-bit result of IEEE 802.1p from Registers 128 and 129 or TOS/DiffServ mapping from Registers 144-159 (for four queues) into two-queue mode with priority high or low. Please see the descriptions of Register 130 bits [7:6] for more detail. July 23, 2014 43 Revision 1.0 Micrel, Inc. KSZ8765CLX Port-Based Priority With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received at the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. The Port Control 0 Registers bits [4:3] is used to enable port-based priority for Ports 1, 2, 3, 4, and 5, respectively. 802.1p-Based Priority For 802.1p-based priority, the KSZ8765CLX examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the priority mapping value, as specified by Registers 128 and 129. Both Register 128 and 129 can map 3-bit priority fields of 0-7 value to 2-bit results of 0-3 priority levels. The priority mapping value is programmable. The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. Figure 11. 802.1p Priority Field Format 802.1p-based priority is enabled by bit [5] of the Port Control 0 Registers for Ports 1, 2, 3, 4, and 5, respectively. The KSZ8765CLX provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the two-byte VLAN protocol ID (VPID) and the two-byte tag control information (TCI) field, is also referred to as the IEEE 802.1Q VLAN tag. Tag insertion is enabled by bit[2] of the Port Control 0 Registers and the Port Control 8 Registers to select which source port (ingress Port) PVID can be inserted on the egress port for Ports 1, 2, 3, 4, and 5, respectively. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the Port Control 3 and Control 4 Registers for Ports 1, 2, 3, 4, and 5, respectively. The KSZ8765CLX will not add tags to already tagged packets. Tag removal is enabled by bit [1] of the Port Control 0 Registers for Ports 1, 2, 3, 4, and 5, respectively. At the egress port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8765CLX will not modify untagged packets. The CRC is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a QoS feature that allows the KSZ8765CLX to set the user priority ceiling at any ingress port by the Port Control 2 Register bit [7]. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. DiffServ-Based Priority DiffServ-based priority uses the ToS registers (Registers 144 to 159) in the advanced control registers section. The ToS priority control registers implement a fully decoded, 128-bit differentiated services code point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP register to determine priority. July 23, 2014 44 Revision 1.0 Micrel, Inc. KSZ8765CLX Spanning Tree Support Port 5 is the designated port for spanning tree support. The other ports (Port 1 through Port 4) can be configured in one of the five spanning tree states via transmit enable, receive enable, and learning disable register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4, respectively. The KSZ8765CLX supports common spanning tree (CST). To support spanning tree, the host port (Port 5) is the designated port for the processor. The other ports can be configured in one of the five spanning tree states via transmit enable, receive enable, and learning disable register settings in Port Control 2 Registers. The following table shows the port setting and software actions taken for each of the five spanning tree states. Table 12. Port Settings and Software Actions for Spanning Tree States Disable State Port Setting Software Action The port should not forward or receive any packets. Learning is disabled. Transmit enable = 0, Receive enable = 0, Learning disable = 1 The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with overriding bit set) and the processor should discard those packets. Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state. Blocking State Port Setting Software Action Only packets to the processor are forwarded. Learning is disabled. Transmit enable = 0, Receive enable = 0, Learning disable = 1 The processor should not send any packets to the port(s) in this state. The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The overriding bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Listening State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is disabled. Transmit enable = 0, Receive enable = 0, Learning disable = 1 The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see Tail Tagging Mode section for details. Address learning is disabled on the port in this state. Learning State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is enabled. Transmit enable = 0, Receive enable = 0, Learning disable = 0 The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see Tail Tagging Mode section for details. Address learning is enabled on the port in this state. Forwarding State Port Setting Software Action Transmit enable = 1, Receive enable = 1, Learning disable = 0 The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see Tail Tagging Mode section for details. Address learning is enabled on the port in this state. Packets are forwarded and received normally. Learning is enabled. July 23, 2014 45 Revision 1.0 Micrel, Inc. KSZ8765CLX Rapid Spanning Tree Support There are three operational states—discarding, learning, and forwarding—assigned to each port for RSTP. Discarding ports do not participate in the active topology and do not learn MAC addresses. Ports in the learning states learn MAC addresses, but do not forward user traffic. Ports in the forwarding states fully participate in both data forwarding and MAC learning. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP configuration BPDUs with the exception of a type field set to “version 2” for RSTP, “version 0” for STP, and a flag field carrying additional information. Table 13. Port Settings and Software Actions for Rapid Spanning Tree States Disable State Port Setting Software Action The state includes three states of the disable, blocking and listening of STP. Transmit enable = 0, Receive enable = 0, Learning disable = 1 The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with overriding bit set) and the processor should discard those packets. When disabling the port’s learning capability (learning disable = ’1’), set the Register 1 bit [5] and bit [4] will rapidly the port-related entries in the dynamic MAC table and static MAC table. Note: processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state. Learning State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is enabled. Transmit enable = 0, Receive enable = 0, Learning disable = 0 The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see Tail Tagging Mode section for details. Address learning is enabled on the port in this state. Forwarding State Port Setting Software Action Transmit enable = 1, Receive enable = 1, Learning disable = 0 The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see Tail Tagging Mode section for details. Address learning is enabled on the port in this state. Packets are forwarded and received normally. Learning is enabled. July 23, 2014 46 Revision 1.0 Micrel, Inc. KSZ8765CLX Tail Tagging Mode The tail tag is only seen and used by the Port 5 interface, which should be connected to a processor by the SW5-GMII, RGMII, MII, or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on Port 5. Only bits [3:0] are used for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting Register 12 bit [1]. Figure 12. Tail Tag Frame Format Table 14. Tail Tag Rules Ingress to Port 5 (Host to KSZ8765CLX) Bits [3:0] Destination 0,0,0,0 Reserved 0,0,0,1 Port 1 (direct forward to Port 1) 0,0,1,0 Port 2 (direct forward to Port 2) 0,1,0,0 Port 3 (direct forward to Port 3) 1,0,0,0 Port 4 (direct forward to Port 4) 1,1,1,1 Port 1, 2, 3, and 4 (direct forward to Port 1, 2, 3,4) Bits [7:4] 0,0,0,0 Queue 0 is used at destination port 0,0,0,1 Queue 1 is used at destination port 0,0,1,0 Queue 2 is used at destination port 0,0,1,1 Queue 3 is used at destination port 0, 1,x,x Anyhow send packets to specified port in bits [3:0] 1, x,x,x Bits [6:0] will be ignored as normal (address look-up) Egress from Port 5 (KSZ8765CLX to Host) Bits [1:0] Source 0,0 Port 1 (packets from Port 1) 0,1 Port 2 (packets from Port 2) 1,0 Port 3 (packets from Port 3) 1,1 Port 4 (packets from Port 4) July 23, 2014 47 Revision 1.0 Micrel, Inc. KSZ8765CLX IGMP Support There are two components involved with the support of the Internet Group Management Protocol (IGMP) in Layer 2. The first part is IGMP snooping, the second part is this IGMP packet which is sent back to the subscribed port. Those components are described below.  IGMP Snooping: The KSZ8765CLX traps IGMP packets and forwards them only to the processor (Port 5 SW5RGMII/MII/RMII). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. Set Register 5 bit [6] to ‘1’ to enable IGMP snooping.  IGMP Send Back to the Subscribed Port: Once the host responds to the received IGMP packet the the host should know the original IGMP ingress port and send back the IGMP packet to this port only. This prohibits the IGMP packet from being broadcast to all ports, which will downgrade the performance. With tail tag mode enabled, the host will know the port from which that IGMP packet has been received via tail tag bits [1:0] and can send back the response IGMP packet to this subscribed port by setting bits [3:0] in the tail tag. Enable tail tag mode by setting Register 12 bit [1]. IPv6 MLD Snooping The KSZ8765CLX traps IPv6 multicast listener discovery (MLD) packets and forwards them only to the processor (Port 5). MLD snooping is controlled by Register 164 bit [2] (MLD snooping enable) and Register 164 bit [3] (MLD option). With MLD snooping enabled, the KSZ8765CLX traps packets that meet all of the following conditions:  IPv6 multicast packets  Hop count limit = 1  IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58). If the MLD option bit is set to “1”, the KSZ8765CLX traps packets with the following additional condition:  IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60) For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows on which port the MLD packet was received. This is achieved by setting Register 12 bit [1]. Port Mirroring Support The KSZ8765CLX supports port mirroring as described below:  “Receive Only” mirror on a port: All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “RX sniff” and Port 5 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined to Port 4 after the internal look-up. The KSZ8765CLX will forward the packet to both Port 4 and Port 5. KSZ8765CLX can optionally forward “bad” received packets to Port 5.  “Transmit Only” mirror on a port: All the packets transmitted on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “TX sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to Port 1 after the internal look-up. The KSZ8765CLX will forward the packet to both Ports 1 and 5.  “Receive and Transmit” mirror on two ports: All the packets received on Port A and transmitted on Port B will be mirrored on the sniffer port. To turn on the “AND” feature, set Register 5 bit [0] to ‘1’. For example, Port 1 is programmed to be “RX sniff,” Port 2 is programmed to be “TX sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined to Port 4 after the internal look-up. The KSZ8765CLX will forward the packet to Port 4 only, because it does not meet the “AND” condition. A packet, received on Port 1, is destined to Port 2 after the internal look-up. The KSZ8765CLX will forward the packet to both Port 2 and Port 5. Multiple ports can be selected to be “RX sniff” or “TX sniff.” Any port can be selected to be the “sniffer port.” All these per port features can be selected through the Port Control 1 Register. July 23, 2014 48 Revision 1.0 Micrel, Inc. KSZ8765CLX VLAN Support The KSZ8765CLX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8765CLX provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up, with a maximum of 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for look-up when IEEE 802.1q is enabled by the global Register 5 Control 3 bit [7]. In the VLAN mode, the look-up process starts from the VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table. FID+DA is used to determine the destination port. The following table describes the different actions in different situations of DA and FID+DA in the static MAC table and dynamic MAC table after the VLAN table finishes a look-up action. FID+SA is used for learning purposes. The following table also describes learning in the dynamic MAC table when the VLAN table has completed a look-up in the static MAC table without a valid entry. Table 15. FID+DA Look-Up in the VLAN Mode DA Found in Static MAC Table? Use FID Flag? FID Match? DA+FID Found in Dynamic MAC Table? No Don’t Care Don’t Care No Broadcast to the membership ports defined in the VLAN table bits [11:7]. No Don’t Care Don’t Care Yes Send to the destination port defined in the dynamic MAC table bits [58:56]. Yes 0 Don’t Care Don’t Care Send to the destination port(s) defined in the static MAC table bits [52:48]. Yes 1 No No Broadcast to the membership ports defined in the VLAN table bits [11:7]. Yes 1 No Yes Send to the destination port defined in the dynamic MAC table bits [58:56]. Yes 1 Yes Don’t Care Send to the destination port(s) defined in the static MAC table bits [52:48]. Action Table 16. FID+SA Look-Up in the VLAN Mode SA+FID Found in Dynamic MAC Table? Action No The SA+FID will be learned into the dynamic table. Yes Time stamp will be updated. Advanced VLAN features are also supported in KSZ8765CLX, such as VLAN ingress filtering and discard non-PVID defined in bits [6:5] of the Port Control 2 Register. These features can be controlled on a per port basis. July 23, 2014 49 Revision 1.0 Micrel, Inc. KSZ8765CLX Rate Limiting Support The KSZ8765CLX provides a fine resolution hardware rate limiting based on both bps (bits per second) and pps (packets per second). For bps, the rate step is 64kbps when the rate limit is less than 1Mbps for 100BT or 10BT and 640kbps for 1000. The rate step is 1Mbps when the rate limit is more than 1Mbps for 100BT or 10BT and 10Mbps for 1000. For pps, the rate step is 128pps (besides the 1st one which is 64pps) when the rate limit is less than 1Mbps for 100BT or 10BT and 1280pps (except the 1st one of 640pps) for 1000. The rate step is 1Mbps when the rate limit is more than 1.92kpps for 100BT or 10BT 19.2kpps for 1000. The data rate selection table is below. Note that the pps limiting is bounded by bps rate for each pps setting; the mapping is shown in the second column of the table. Table 17. 10/100/1000Mbps Rate Selection for the Rate Limit Item bps Bound of pps (Egress Only) Code Code pps bps pps bps pps bps 7’d0 7’d0 19.2kpps 10Mbps 192kpps 100Mbps 1.92Mpps 1000Mbps 7d’1 to 7d’10 7d’3,6, (8x)10 1.92kpps * code 1Mbps * code 1.92kpps * code 1Mbps * code 19.2kpps * code 10Mbps * code 7d’11 to 7d’100 7d’11 – 7d’100 10Mbps 1.92kpps * code 1Mbps * code 19.2kpps * code 10Mbps * code 7d’101 7d’102 64pps 64kbps 64pps 64kbps 640pps 640kbps 7d’102 7d’104 128pps 128kbps 128pps 128kbps 1280pps 1280kbps 7d’103 7d’108 256pps 192kbps 256pps 192kbps 2560pps 1920kbps 7d’104 7d’112 384pps 256kbps 384pps 256kbps 3840pps 2560kbps 7d’105 7d’001 512pps 320kbps 512pps 320kbps 5120pps 3200kbps 7d’106 7d’001 640pps 384kbps 640pps 384kbps 6400pps 3840kbps 7d’107 7d’001 768pps 448kbps 768pps 448kbps 7680pps 4480kbps 7d’108 7d’002 896pps 512kbps 896pps 512kbps 8960pps 5120kbps 7d’109 7d’002 1024pps 576kbps 1024pps 576kbps 10240pps 5760kbps 7d’110 7d’002 1152pps 640kbps 1152pps 640kbps 11520pps 6400kbps 7d’111 7d’002 1280pps 704kbps 1280pps 704kbps 12800pps 7040kbps 7d’112 7d’002 1408pps 768kbps 1408pps 768kbps 14080pps 7680kbps 7d’113 7d’003 1536pps 832kbps 1536pps 832kbps 15360pps 8320kbps 7d’114 7d’003 1664pps 896kbps 1664pps 896kbps 16640pps 8960kbps 7d’115 7d’003 1792pps 969kbps 1792pps 969kbps 17920pps 9690kbps 10Mbps 100Mbps 1000Mbps The rate limit operates independently on the “receive side” and on the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. On the transmit side, the data transmit rate for each queue at each port can be limited by setting up egress rate control registers. For bps mode, the size of each frame has options to include minimum inter-frame gap (IFG) or preamble byte, in addition to the data field (from packet DA to FCS). July 23, 2014 50 Revision 1.0 Micrel, Inc. KSZ8765CLX Ingress Rate Limit For ingress rate limiting, KSZ8765CLX provides options to selectively choose frames from all types: multicast, broadcast, and flooded unicast frames via bits [3:2] of the Port Rate Limit Control Register. The KSZ8765CLX counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is enabled by the Port Rate Limit Control Register bit [4]. The ingress rate limiting supports the port-based, IEEE 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4:3] of the Port Control 0 Register. The IEEE 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129. In the ingress rate limit, set Register 135 Global Control 19 bit [3] to enable queue-based rate limiting if using two-queue or four-queue mode. All related ingress ports and egress ports should be split to two-queue or four-queue mode by the Port Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0] of the Port Register Ingress Limit Control 14. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the port ingress limit control 1-2 Registers. The priority levels in the packets of the IEEE 802.1p and DiffServ can be programmed to priority 0-3 via the Register 128 and 129 for re-mapping. Egress Rate Limit For egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic. Interframe gap is stretched on a per frame basis to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified by the data rate selection table followed by the egress rate limit control registers. If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress, and may be slightly less than the specified egress rate. The egress rate limiting supports the port-based, IEEE 802.1p, and DiffServ-based priorities. The port-based priority is fixed priority 0-3 selection by bits [4:3] of the Port Control 0 Register. The IEEE 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129. In the egress rate limit, set Register 135 Global Control 19 bit [3] to enable queue-based rate limiting if using twoqueue or four-queue mode. All related ingress ports and egress ports should be split to two-queue or four-queue mode by the Port Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0] of the Port Egress Limit Control 1-4 Register. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the Port Egress Rate Limit Control 1-2 Register. The priority levels in the packets of the IEEE 802.1p and DiffServ can be programmed to priority 0-3 by Register 128 and 129 for re-mapping. When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will be based upon the data rate selection table (see Table 17). If the egress rate limit uses more than one queue per port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table for the rate limit’s exact number. Other lower priority packet rates will be limited based upon an 8:4:2:1 (default) priority ratio, which is based on the highest priority rate. The transmit queue priority ratio is programmable. To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth. Transmit Queue Ratio Programming In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by the Port Control 10, 11, 12, and 13 Registers. When the transmit rate exceeds the ratio limit in the transmit queue, the transmit rate will be limited by the transmit queue 0-3 ratio of the Port Control 10, 11, 12, and 13 Registers. The highest priority queue will not be limited. Other lower priority queues will be limited based on the transmit queue ratio. July 23, 2014 51 Revision 1.0 Micrel, Inc. KSZ8765CLX VLAN and Address Filtering To prevent certain kinds of packets that could degrade the quality of the switch in applications such as voice over Internet protocol (VoIP), the switch provides the mechanism to filter and map the packets with the following MAC addresses and VLAN IDs.  Self-address packets  Unknown unicast packets  Unknown multicast packets  Unknown VID packets  Unknown IP multicast packets The packets sourced from switch itself can be filtered out by enabling self-address filtering via the Global Control 18 Register bit [6]. The self-address filtering will filter packets on the egress port, self MAC address is assigned in the Register 104-109 MAC Address Registers 0-5. The unknown unicast packet filtering can be enabled by the Global Control Register 15 bit [5] and bits [4:0] specify the port map for forwarding. The unknown multicast packet filtering can be enabled by the Global Control Register 16 bit [5] and the forwarding port map is specified in bits [4:0]. The unknown VID packet filtering can be enabled by Global Control Register 17 bit [5] with the forwarding port map specified in bits [4:0]. The unknown IP multicast packet filtering can be enabled by Global Control Register 18 bit [5] with the forwarding port map specified in bits [4:0]. The filters above are globally based. IEEE 802.1x Port-Based Security IEEE 802.1x is a port-based authentication protocol. EAPOL is the protocol normally used by the authentication process as an uncontrolled port. By receiving and extracting special EAPOL frames, the microprocessor (CPU) can control whether the ingress and egress ports should forward packets or not. If a user port wants service from another port (authenticator), it must get approval from the authenticator. The KSZ8765CLX detects EAPOL frames by checking the destination address of the frame. The destination addresses should be either a multicast address as defined in IEEE 802.1x (01-80-C2-00-00-03) or an address used in the programmable reserved multicast address domain with offset -0003. Once EAPOL frames are detected, the frames are forwarded to the CPU so it can send the frames to the authenticator server. Eventually, the CPU determines whether the requestor is qualified or not based on its MAC_Source addresses and frames are either accepted or dropped. When the KSZ8765CLX is configured as an authenticator, the ports of the switch must then be configured for authorization. In an authenticator-initiated port authorization, a client is powered-up or plugs into the port and the authenticator port sends an extensible authentication protocol (EAP) PDU to the supplicant requesting the identification of the supplicant. At this point in the process, the port on the switch is connected from a physical standpoint; however, the IEEE 802.1x process has not authorized the port and no frames are passed from the port on the supplicant into the switching fabric. If the PC attached to the switch did not understand the EAP PDU that it received from the switch, it is not be able to send an ID and the port remains unauthorized. In this state, the port would never pass any user traffic and would be as good as disabled. If the client PC is running the IEEE 802.1x EAP, it would respond to the request with its configured ID. This could be a user name/password combination or a certificate. After the switch, the authenticator receives the ID from the PC (the supplicant). The KSZ8765CLX then passes the ID information to an authentication server (RADIUS server) that can verify the identification information. The RADIUS server responds to the switch with either a success or failure message. If the response is successful, the port will be authorized and user traffic will be allowed to pass through the port like any switch port connected to an access device. If the response is a failure, the port will remain unauthorized and, therefore, unused. If there is no response from the server, the port will also remain unauthorized and will not pass any traffic. July 23, 2014 52 Revision 1.0 Micrel, Inc. KSZ8765CLX Authentication Register and Programming Model The port authentication control registers define the control of port-based authentication. The per-port authentication can be programmed in these registers. The KSZ8765CLX provides three modes for implementing the IEEE 802.1x feature. Each mode can be selected by setting the appropriate bits in the port authentication registers. In pass mode (AUTHENTICATION_MODE = 00), forced-authorization is enabled and a port is always authorized that does not require any messages from either the supplicant or the authentication server. This is typically the case when connecting to another switch, a router, or a server, and also when connecting to clients that do not support IEEE 802.1x. When ACL is enabled, all the packets are passed if they miss ACL rules; otherwise, ACL actions apply. The block mode (AUTHENTICATION_MODE = 01) is the standard port-based authentication mode. A port in this mode sends EAP packets to the supplicant and will not become authorized unless it receives a positive response from the authentication server. Before authentication, traffic is blocked to all of the incoming packets. Upon authentication, software will switch to pass mode to allow all the incoming packets. In this mode, the source address of incoming packets is not checked, including the EAP address. The forwarding map of all the reserved multicast addresses needs to be configured to allow forwarding before and after authentication in the look-up table. When ACL is enabled, packets except ACL hits are blocked. The third mode is trap mode (AUTHENTICATION_MODE = 11'b). In this mode, all the packets are sent to CPU port. If ACL is enabled, the missed packets are forwarded to the CPU rather than dropped. All these per-port features can be selected through the Port Control 5 Register; bit [2] is used to enable ACL, bits [1:0] are for the modes selected. Access Control List (ACL) Filtering An ACL can be created to perform the protocol-independent Layer 2 MAC, Layer 3 IP, or Layer 4 TCP/UDP ACL filtering that manages incoming Ethernet packets based on the ACL rule table. The feature allows the switch to filter customer traffic based on the source MAC address in the Ethernet header, the IP address in the IP header, and the port number and protocol in the TCP header. This function can be performed through the MAC table and ACL rule table. Besides multicast filtering using entries in the static table, ACLs can be configured for all routed network protocols to filter the packets of those protocols as the packets pass through the switch. Access lists can prevent certain traffic from entering or exiting a network. Access Control Lists KSZ8765CLX offers a rule-based access control list. The ACL rule table is an ordered list of access control entries. Each entry specifies certain rules (a set of matching conditions and action rules) to permit or deny the packet access to the switch fabric. The meaning of ‘permit’ or ‘deny’ depends on the context in which the ACL is used. When a packet is received on an interface, the switch compares the fields in the packet against any applied ACLs to verify that the packet has the permissions required to be forwarded, based on the conditions specified in the lists. The filter tests the packets against the ACL entries one-by-one. Usually, the first match determines whether the router accepts or rejects packets. However, it is allowed to cascade the rules to form more robust and/or stringent requirements for incoming packets. ACLs allow switch filter ingress traffic based on the source, destination MAC address and Ethernet type in the Layer 2 header, the source and destination IP address in the Layer 3 header, and port number protocol in the Layer 4 header of a packet. Each list consists of three parts: the matching field, the action field, and the processing field. The matching field specifies the rules that each packet matches against and the action field specifies the action taken if the test succeeds against the rules. The figure below shows the format of ACL and a description of the individual fields. July 23, 2014 53 Revision 1.0 Micrel, Inc. KSZ8765CLX Figure 13. ACL Format Matching Fields MD [1:0]: MODE - there are three modes of operation defined in ACL. MD = 00 disables the current rule list. No action will be taken. MD = 01 is qualification rules for Layer 2 MAC header filtering. MD = 10 is used for Layer 3 IP address filtering. MD = 11 performs Layer 4 TCP port number/protocol filtering. ENB [1:0]: ENABLE – Enables different rules in the current list. When MD = 01, If ENB = 00, the 11 bits of the aggregated bit field from PM, P, RPE, RP, MM in the action field specify a count value for packets matching the MAC address and type in the matching fields. The count unit is defined in MSB of the forward bit field; while = 0, µsec will be used and while = 1, msec will be used. The second MSB of the forwarded bit determines the algorithm used to generate an interrupt when the counter terminates. When = 0, an 11-bit counter is loaded with the count value from the ACL and starts counting down every unit July 23, 2014 54 Revision 1.0 Micrel, Inc. KSZ8765CLX of time. An interrupt is generated when it expires (i.e., the next qualified packet has not been received within the period specified by the value). When = 1, the counter is incremented on every matched packet received and an interrupt is generated when the terminal count reaches the count value in the ACL. The count resets thereafter. If ENB = 01, the MAC address bit field is used for testing; If ENB = 10, the MAC type bit field is used for testing; If ENB = 11, both the MAC address and type are tested against these bit fields in the list. When MD = 10, If ENB = 01, the IP address and mask or IP protocol is enabled to be tested accordingly. If ENB = 10, the source and destination addresses are compared. The drop/forward decision is based on the EQ bit setting. When MD = 11, If ENB = 00, protocol comparison is enabled. If ENB = 01, TCP address comparison is selected. If ENB = 10, UDP address comparison is selected. If ENB = 11, the sequence number of the TCP is compared. S/D: Source or destination selection S/D = 0, the destination address/port is compared; S/D = 1, the source is chosen. E/Q: comparison algorithm: E/Q = 0, match if they are not equal; E/Q = 1, match if they are equal. MAC Address [47:0]: MAC source or destination address TYPE [15:0]: MAC Ether Type IP Address [31:0]: IP source or destination address IP Mask [31:0]: IP address mask for group address filtering MAX Port [15:0], MIN Port [15:0] (Sequence Number [31:0]): The range of TCP port number or sequence number matching. PC [1:0]: Port comparison PC = 00, the comparison is disabled. PC = 01, matches either one of MAX or MIN. PC = 10, match if the port number is in the range of MAX to MIN. PC = 11, match if the port number is out of the range. PRO [7:0]: IP protocol to be matched FME: Flag match enable FME = 0, disable TCP FLAG matching. FME = 1, enable TCP FLAG matching. FLAG [5:0]: TCP flag to be matched. Action Field PM [1:0]: Priority mode July 23, 2014 55 Revision 1.0 Micrel, Inc. KSZ8765CLX PM = 00, no priority is selected, the priority is determined by the QoS/classification is used. PM = 01, the priority in P bit field is used if it is greater than QoS result. PM = 10, the priority in P bit field is used if it is smaller than QoS result. PM = 11, the P bit field will replace the priority determined by QoS. P [2:0]: Priority. RPE: Remark priority enable RPE = 0, no remarking is necessary. RPE = 1, the VLAN priority bits in the tagged packets are replaced by RP bit field in the list. RP [2:0]: Remarked priority. MM [1:0]: Map mode MM = 00, no forwarding remapping is necessary. MM = 01, the forwarding map in FORWARD is OR’ed with the forwarding map from the look-up table. MM = 10, the forwarding map in FORWARD is AND’ed with the forwarding map from the look-up table. MM = 11, the forwarding map in FORWARD replaces the Forwarding map from the look-up table. FORWARD Bits [4:0]: Forwarding port(s) - Each bit indicates the forwarding decision of one port. Processing Field FRN Bits [3:0]: First rule number – Assigns which entry with its Action Field in 16 entries is used in the rule set. For the rule set, see description below. RULESET Bits [15:0]: Rule set - Group of rules to be qualified, there are 16 entries rule can be assigned to a rule set per port by the two rule set registers. The rule table allows the rules to be cascaded. There are 16 entries in the RTB. Each entry can be a rule on its own, or can be cascaded with other entries to form a rule set. The test result of incoming packets against rule set will be the AND’ed result of all the test result of incoming packets against the rules included in this rule set. The action of the rule set will be the action of the first rule specified in FRN field. The rule with higher priority will have lower index number. Or rule 0 is the highest priority rule and rule 15 is the lowest priority. ACL rule table entry is disabled when mode bits are set to 2’b00. A rule set is used to select the match results of different rules against incoming packets. These selected match results will be AND’ed to determine whether the frame matches or not. The conditions of different rule sets having the same action will be OR’ed for comparison with frame fields, and the CPU will program the same action to those rule sets that are to be OR’ed together. For matched rule sets, different rule sets having different actions will be arbitrated or chosen based upon the first rule number (FRN) of each rule set. The rule table will be set up with the high priority rule at the top of the table or with the smaller index. Regardless whether the matched rule sets have the same or different action, the hardware will always compare the first rule number of different rule sets to determine the final rule set and action. Denial of Service (DoS) Attack Prevention via ACL The ACL can provide certain detection/protection of the following DoS attack types based on rule setting, which can be programmed to drop or not to drop each type of DoS packet respectively. Example 1: When MD = ‘10’, ENABLE = ‘10’, setting the EQ bit to ‘1’ can determine the drop or forward packets with identical source and destination IP addresses in IPv4/IPv6. Example 2: When MD = ‘11’, ENABLE = ‘01’/’10’, setting the EQ bit to ‘1’ can determine the drop or forward packets with identical source and destination TCP/UDP ports in IPv4/IPv6. Example 3: When MD = ‘11’, ENABLE = ‘11’, Sequence Number = ‘0’, FME = ‘1’, FMSK = ‘00101001’, FLAG = ‘xx1x1xx1’, Setting the EQ bit to ‘1’ will drop/forward the all packets with a TCP sequence number equal to ‘0’, and flag bit URG = ‘1’, PSH = ‘1’, and FIN = ‘1’. July 23, 2014 56 Revision 1.0 Micrel, Inc. KSZ8765CLX Example 4: When MD = ‘11’, ENABLE = ‘01’, MAX Port = ‘1024’, MIN Port = ‘0’, FME = ‘1’, FMSK = ‘00010010’, FLAG = ‘xxx0xx1x’, Setting the EQ bit to ‘1’ will drop/forward the all packets with a TCP port number ≤1024, and flag bit URB = ‘0’, SYN = ‘1’. ACL-related registers list as the Register 110 (0x6E), the Register 111 (0x6F), and the ACL rule tables. Device Registers The KSZ8765CLX device has a rich set of registers available to manage the functionality of the device. Access to these registers is via the MIIM or SPI interfaces. The figure below provides a global picture of accessibility via the various interfaces and addressing ranges from the perspective of each interface. Figure 14. Interface and Register Mapping The registers within the linear 0x00-0xFF address space are all accessible via the SPI interface by a CPU attached to that bus. The mapping of the various functions within that linear address space is summarized in the table below. July 23, 2014 57 Revision 1.0 Micrel, Inc. KSZ8765CLX Table 18. Mapping of Functional Areas within the Address Space Register Locations 0x00 – 0xFF Device Area Description Switch Control and Configuration Registers that control the overall functionality of the switch, MAC, and PHYs. Registers used to indirectly address and access distinct areas within the device. 0x6E – 0x6F Management information base (MIB) counters Static MAC address table Dynamic MAC address table VLAN table PME indirect register ACL indirect register EEE indirect Register Indirect Control Registers Registers used to indirectly address and access four distinct areas within the device. 0x70 – 0x78 Management Information Base (MIB) counters Static MAC address table Dynamic MAC address table VLAN table Indirect Access Registers This indirect byte register is used to access: 0xA0 0x17 – 0x4F July 23, 2014 PME indirect registers ACL indirect registers EEE indirect registers Indirect Byte Access Registers PHY1 to PHY4 MIIM Registers Mapping to Those Port Registers’ Address Ranges 58 The same PHY registers as specified in IEEE 802.3. Revision 1.0 Micrel, Inc. KSZ8765CLX Direct Register Description Address Contents 0x00-0x01 Family ID, Chip ID, Revision ID, and start switch Registers 0x02-0x0D Global Control Registers 0 – 11 0x0E-0x0F Global Power Down Management Control Registers 0x10-0x14 Port 1 Control Registers 0 – 4 0x15 Port 1 Authentication Control Register 0x16-0x18 Port 1 Reserved (Factory Test Registers) 0x19-0x1F Port 1 Control/Status Registers 0x20-0x24 Port 2 Control Registers 0 – 4 0x25 Port 2 Authentication Control Register 0x26-0x28 Port 2 Reserved (Factory Test Registers) 0x29-0x2F Port 2 Control/Status Registers 0x30-0x34 Port 3 Control Registers 0 – 4 0x35 Port 3 Authentication Control Register 0x36-0x38 Port 3 Reserved (Factory Test Registers) 0x39-0x3F Port 3 Control/Status Registers 0x40-0x44 Port 4 Control Registers 0 – 4 0x45 Port 4 Authentication Control Register 0x46-0x48 Port 4 Reserved (Factory Test Registers) 0x49-0x4F Port 4 Control/Status Registers 0x50-0x54 Port 5 Control Registers 0 – 4 0x56-0x58 Port 5 Reserved (Factory Test Registers) 0x59-0x5F Port 5 Control/Status Registers 0x60-0x67 Reserved (Factory Testing Registers) 0x68-0x6D MAC Address Registers 0x6E-0x6F Indirect Access Control Registers 0x70-0x78 Indirect Data Registers 0x79-0x7B Reserved (Factory Testing Registers) 0x7C-0x7D Global Interrupt and Mask Registers 0x7E-0x7F ACL Interrupt Status and Control Registers 0x80-0x87 Global Control Registers 12 – 19 0x88 Switch Self Test Control Registers 0x89-0x8F QM Global Control Registers 0x90-0x9F Global TOS Priority Control Registers 0 - 15 0xA0 Global Indirect Byte Register 0xA0-0xAF Reserved (Factory Testing Registers) 0xB0-0xBE Port 1 Control Registers 0xBF Reserved (Factory Testing Register): Transmit Queue Remap Base Register 0xC0-0xCE Port 2 Control Registers July 23, 2014 59 Revision 1.0 Micrel, Inc. KSZ8765CLX Direct Register Description (Continued) Address Contents 0xCF Reserved (Factory Testing Register) 0xD0-0xDE Port 3 Control Registers 0xDF Reserved (Factory Testing Register) 0xE0-0xEE Port 4 Control Registers 0xEF Reserved (Factory Testing Register) 0xF0-0xFE Port 5 Control Registers 0xFF Reserved (Factory Testing Register) July 23, 2014 60 Revision 1.0 Micrel, Inc. KSZ8765CLX Global Registers Address Name Description Mode Default Chip family. RO 0x87 0x9 and Register 24 bit [7]=1 for KSZ8765 RO 0x9 RO 0x0 R/W 1 R/W 0 R/W 0 Register 0 (0x00): Chip ID0 7-0 Family ID Register 1 (0x01): Chip ID1/Start Switch 7-4 Chip ID 3-1 Revision ID 0 Start Switch 1 = Start the switch function of the chip 0 = Stop the switch function of the chip Register 2 (0x02): Global Control 0 7 New back-off enable New back-off algorithm designed for UNH 1 = Enable 0 = Disable Global Software Reset 1 = Enable reset of all FSM and data path (not configuration) 6 Global soft reset enable 0 = Disable reset Note: This reset will stop receiving packets if they are in traffic. All registers keep their configuration values. Flush the entire dynamic MAC table for RSTP. This bit is self-clearing (SC). 1 = Trigger the flush dynamic MAC table operation. 5 Flush dynamic MAC table 0 = Normal operation R/W Note: All the entries associated with a port that has its learning capability turned off (learning disable) will be flushed. If you want to flush the entire table, the learning capability of all ports must be turned off. (SC) 0 Flush the matched entries in static MAC table for RSTP 1 = Trigger the flush static MAC table operation. 0 = Normal operation R/W 4 Flush static MAC table Note: The matched entry is defined as the entry in the Forwarding Ports field that contains a single port and MAC address with unicast. This port, in turn, has its learning capability turned off (learning disable). Per port, multiple entries can be qualified as matched entries. 3 Reserved N/A Don’t change. RO 1 2 Reserved N/A Don’t change. RO 1 R/W 0 R/W 0 1 0 UNH Mode Link Change Age 1 = The switch will drop packets with 0x8808 in the T/L filed or DA = 01-80-C2-00-00-01. 0 = The switch will drop packets qualified as flow control packets. 1 = Changing from link to no link will cause the address table to age faster (