KSZ8851-16MLL/MLLI/MLLU
Single-Port Ethernet MAC Controller with 8-Bit
or 16-Bit Non-PCI Interface
Highlights
Features
• Single-Port Controller Chip with Non-PCI CPU
Interface
• Mixed Analog/Digital Device Offering Wake-OnLAN Technology for Effectively Addressing Fast
Ethernet Applications
• HP Auto-MDIX Support
• Integrated MAC and PHY Ethernet Controller
Fully Compliant with IEEE 802.3/802.3u
Standards
• Designed for High Performance and High
Throughput Applications
• Supports 10BASE-T/100BASE-TX
• Supports IEEE 802.3x Full-Duplex Flow Control
and Half-Duplex Backpressure Collision Flow
Control
• Supports DMA-Slave Burst Data Read and Write
Transfers
• Supports IP Header (IPv4)/TCP/UDP/ICMP
Checksum Generation and Checking
• Supports IPv6 TCP/UDP/ICMP Checksum
Generation and Checking
• Automatic 32-Bit CRC Generation and Checking
• Simple SRAM-like Host Interface Easily Connects
to Most Common Embedded MCUS
• Supports Multiple Data Frames for Receive without Address Bus and Byte-Enable Signals
• Supports Both Big- and Little-Endian Processors
• Larger Internal Memory with 12 kb for RX FIFO
and 6 kb for TX FIFO. Programmable Low, High
and Overrun Watermark for Flow Control in Rx
FIFO
• Shared Data Bus for Data, Address, and Byte
Enable
• Efficient Architecture Design with Configurable
Host Interrupt Schemes to Minimize Host CPU
Overhead and Utilization
• Powerful and Flexible Address Filtering Scheme
• Optional to Use External Serial EEPROM Configuration for MAC Address
• Single 25 MHz Reference Clock for Both PHY
and MAC
• HBM ESD Rating 6 kV
Target Applications
•
•
•
•
•
•
•
•
•
Video/Audio Distribution Systems
High-End Cable, Satellite, and IP Set-Top Boxes
Video over IP and IPTV
Voice over IP (VoIP) and Analog Telephone
Adapters (ATA)
Industrial Control in Latency Critical Applications
Home Base Station with Ethernet Connection
Industrial Control Sensor Devices (Temperature,
Pressure, Levels, and Valves)
Security, Motion Control and Surveillance
Cameras
In-Vehicle Diagnostics (OBD) and Software
Download
2018 Microchip Technology Inc.
DS00002357B-page 1
KSZ8851-16MLL/MLLI/MLLU
Power Modes, Power Supplies, and
Packaging
• Single 3.3V Power Supply with Options for 1.8V,
2.5V and 3.3V VDD I/O
• Built-in Integrated 3.3V or 2.5V to 1.8V Low Noise
Regulator (LDO) for Core and Analog Blocks
• Enhanced Power Management Feature with
Energy Detect Mode to Ensure Low-Power Dissipation During Device Idle Periods
• Comprehensive LED Indicator Support for Link,
Activity and 10/100 Speed (2 LEDs) - User Programmable
• Low-Power CMOS Design
• Commercial Temperature Range: 0°C to +70°C
• Industrial Temperature Range: –40°C to +85°C
• Flexible Package Options Available in 48-Pin
QFP KSZ8851-16MLL or 128-Pin PQFP
KSZ8851-16/32MQL
Markets
•
•
•
•
•
Fast Ethernet
Embedded Ethernet
Industrial Ethernet
Embedded Systems
Automotive Ethernet
Additional Features
In Addition to Offering All the Features of a Layer 2
Controller, the KSZ8851-16MLL Offers:
• Flexible 8-bit and 16-bit Generic Host Processor
Interfaces with Same Access Time and Single
Bus Timing to any I/O Registers and Rx/Tx FIFO
Buffers
• Supports to add Two-Byte Before Frame Header
in Order for IP Frame Content with Double Word
Boundary
• LinkMD® Cable Diagnostic Capabilities to Determine Cable Length, Diagnose Faulty Cables, and
Determine Distance To Fault
• Wake-on-LAN Functionality
- Incorporates Magic Packet™, Wake-up
Frame, Network Link State, and Detection of
Energy Signal Technology
• HP Auto MDI-X™ Crossover with Disable/Enable
Option
• Ability to Transmit and Receive Frames up to
2000 Bytes
Network Features
• 10BASE-T and 100BASE-TX Physical Layer Support
• Auto-Negotiation: 10/100 Mbps Full- and HalfDuplex
• Adaptive Equalizer
• Baseline Wander Correction
DS00002357B-page 2
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU/MLLI/MLLU
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2018 Microchip Technology Inc.
DS00002357B-page 3
KSZ8851-16MLL/MLLI/MLLU
NOTES:
DS00002357B-page 4
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 6
2.0 Pin Description and Configuration .................................................................................................................................................. 9
3.0 Functional Description .................................................................................................................................................................. 14
4.0 CPU Interface I/O Registers ......................................................................................................................................................... 33
5.0 Operational Characteristics ........................................................................................................................................................... 72
6.0 Timing Specifications .................................................................................................................................................................... 74
7.0 Selection of Isolation Transformers .............................................................................................................................................. 78
8.0 Selection of Reference Crystal ..................................................................................................................................................... 79
9.0 Package Outline ............................................................................................................................................................................ 80
Appendix A: Data Sheet Revision History ........................................................................................................................................... 81
The Microchip Web Site ...................................................................................................................................................................... 82
Customer Change Notification Service ............................................................................................................................................... 82
Customer Support ............................................................................................................................................................................... 82
Product Identification System ............................................................................................................................................................. 83
2018 Microchip Technology Inc.
DS00002357B-page 5
KSZ8851-16MLL/MLLI/MLLU
1.0
INTRODUCTION
1.1
General Terms and Conventions
The following is list of the general terms used throughout this document:
BIU
Bus Interface Unit
The host interface function that performs code conversion, buffering, and
the like required for communications to and from a network.
BPDU
Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
CMOS
A common semiconductor manufacturing technique in which positive and
Complementary Metal Oxide negative types of transistors are combined to form a current gate that in
Semiconductor
turn forms an effective means of controlling electrical current through a
chip.
CRC
Cyclic Redundancy Check
A common technique for detecting data transmission errors. CRC for
Ethernet is 32 bits long.
—
Cut-Through Switch
A switch typically processes received packets by reading in the full
packet (storing), then processing the packet to determine where it needs
to go, then forwarding it. A cut-through switch simply reads in the first bit
of an incoming packet and forwards the packet. Cut-through switches do
not store the packet.
DA
Destination Address
The address to send packets.
DMA
Direct Memory Access
A design in which memory on a chip is controlled independently of the
CPU.
EEPROM
Electronically Erasable
Programmable Read-only
Memory
A design in which memory on a chip can be erased by exposing it to an
electrical charge.
EISA
A bus architecture designed for PCs using 80x86 processors, or an Intel
Extended Industry Standard
80386, 80486 or Pentium microprocessor. EISA buses are 32 bits wide
Architecture
and support multiprocessing.
EMI
Electro-Magnetic
Interference
A naturally occurring phenomena when the electromagnetic field of one
device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In computer technology,
computer devices are susceptible to EMI because electromagnetic fields
are a byproduct of passing electricity through a wire. Data lines that have
not been properly shielded are susceptible to data corruption by EMI.
FCS
Frame Check Sequence
See CRC.
FID
Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
IGMP
Internet Group Management
The protocol defined by RFC 1112 for IP multicast transmissions.
Protocol
IPG
Inter-Packet Gap
A time delay between successive data packets mandated by the network
standard for protocol reasons. In Ethernet, the medium has to be "silent"
(i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. IPG is used to correct timing
differences between a transmitter and receiver. During the IPG, no data is
transferred, and information in the gap can be discarded or additions
inserted without impact on data integrity.
ISI
Inter-Symbol Interference
The disruption of transmitted code caused by adjacent pulses affecting or
interfering with each other.
ISA
Industry Standard
Architecture
A bus architecture used in the IBM PC/XT and PC/AT.
—
Jumbo Packet
A packet larger than the standard Ethernet packet (1500 bytes). Large
packet sizes allow for more efficient use of bandwidth, lower overhead,
less processing, etc.
DS00002357B-page 6
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Medium Dependent Interface
An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable.
MDI provides the standard interface to a particular media (copper or
fiber) and is therefore 'media dependent.
MDI-X
Medium Dependent Interface Crossover
An Ethernet port connection that allows networked end stations (i.e., PCs
or workstations) to connect to each other using a null-modem, or crossover, cable. For 10/100 full-duplex networks, an end point (such as a
computer) and a switch are wired so that each transmitter connects to the
far end receiver. When connecting two computers together, a cable that
crosses the TX and RX is required to do this. With auto MDI-X, the PHY
senses the correct TX and RX roles, eliminating any cable confusion.
MIB
Management Information
Base
The MIB comprises the management portion of network devices. This
can include things like monitoring traffic levels and faults (statistical), and
can also change operating parameters in network nodes (static forwarding addresses).
MII
Media Independent Interface
The MII accesses PHY registers as defined in the IEEE 802.3 specification.
NIC
Network Interface Card
An expansion board inserted into a computer to allow it to be connected
to a network. Most NICs are designed for a particular type of network,
protocol, and media, although some can serve multiple networks.
NPVID
Non Port VLAN ID
The Port VLAN ID value is used as a VLAN reference.
PLL
Phase-Locked Loop
—
PME
Power Management Event
An occurrence that affects the directing of power to different components
of a system.
QMU
Queue Management Unit
Manages packet traffic between MAC/PHY interface and the system
host. The QMU has built-in packet memories for receive and transmit
functions called TXQ (Transmit Queue) and RXQ (Receive Queue).
SA
Source Address
The address from which information has been sent.
TDR
TDR is used to pinpoint flaws and problems in underground and aerial
wire, cabling, and fiber optics. They send a signal down the conductor
Time Domain Reflectometry
and measure the time it takes for the signal -- or part of the signal -- to
return.
UTP
Unshielded Twisted Pair
Commonly a cable containing 4 twisted pairs of wires. The wires are
twisted in such a manner as to cancel electrical interference generated in
each wire, therefore shielding is not required.
VLAN
Virtual Local Area Network
A configuration of computers that acts as if all computers are connected
by the same physical network but which may be located virtually anywhere.
MDI
1.2
General Description
The KSZ8851M-series is a single-port controller chip with a non-PCI CPU interface, and is available in 8-bit and 16-bit
bus designs. This data sheet describes the 48-pin LQFP KSZ8851-16MLL functionality for applications requiring highperformance from a single-port Ethernet controller with an 8-bit or 16-bit generic processor interface. The KSZ885116MLL offers the most cost-effective solution for adding high-throughput Ethernet connectivity to traditional embedded
systems.
The KSZ8851-16MLL is a single-chip, mixed analog/digital device offering wake-on-LAN technology for effectively
addressing fast Ethernet applications. It consists of a fast Ethernet MAC controller, an 8-bit or 16-bit generic host processor interface, and incorporates a unique, dynamic memory pointer with 4-byte buffer boundary and can fully utilize
18 KB for both TX (allocated 6 KB) and RX (allocated 12 KB) directions in the host buffer interface.
The KSZ8851-16MLL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851-16MLLI and a qualified AEC-Q100 automotive version of the KSZ8851-16MLLU
are also available.
2018 Microchip Technology Inc.
DS00002357B-page 7
KSZ8851-16MLL/MLLI/MLLU
Physical signal transmission and reception are enhanced through the use of analog circuitry. This makes the design
more efficient and allows lower-power consumption. The KSZ8851-16MLL is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V, or 3.3V VDD I/O. The device includes an extensive feature set that offers management information base (MIB) counters and CPU control/data interfaces with single
shared data bus timing.
The KSZ8851-16MLL includes a unique cable diagnostics feature called LinkMD®. This feature determines the length
of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software
enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851-16MLL supports
Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in
applications.
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
PME
SD [15:0]
CMD
RDN
WRN
CSN
X1
X2
EEPROM
I/F
DS00002357B-page 8
NON-PCI
SHARED
DATA BUS
INTERFACE
UNIT
PLL CLOCK
QMU
DMA
CHANNEL
VDD_IO
1.8V LOW NOISE
REGULATOR
POWER
MANAGEMENT
INTRN
(8- OR 16-BIT)
VDD_CO1.8
RXQ
12KB
TXQ
6KB
HOST MAC
10/100
BASE-T/TX
PHY
RXP1
RXM1
(AUTO MDI/MDI-X)
TXP1
TXM1
CONTROL/STATUS
I/O REGISTERS
MIB
COUNTERS
EEPROM
INTERFACE
LINKMD®
CABLE DIAGNOSTICS
LED DRIVER
P1LED1
P1LED0
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
2.0
PIN DESCRIPTION AND CONFIGURATION
48-LQFP PIN ASSIGNMENT (TOP VIEW)
SD0
SD1
VDD_IO
SD2
SD3
SD4
SD5
SD6
SD7
SD8
VDD_IO
DGND
FIGURE 2-1:
48 47 46 45 44 43 42 41 40 39 38 37
P1LED1
P1LED0
PME
INTRN
RDN
WRN
DGND
VCC_CO1.8
EED_IO
EESK
CMD
CSN
1
2
3
4
5
6
7
8
9
10
11
12
KSZ8851-16MLL
(TOP VIEW)
36
35
34
33
32
31
30
29
28
27
26
25
SD9
SD10
SD11
SD12
SD13
SD14
SD15
VDD_D1.8
DGND
VDD_IO
DGND
X2
AGND
VDD_A1.8
EECS
RXP1
RXM1
AGND
TXP1
TXM1
VDD_A3.3
ISET
RSTN
X1
13 14 15 16 17 18 19 20 21 22 23 24
2018 Microchip Technology Inc.
DS00002357B-page 9
KSZ8851-16MLL/MLLI/MLLU
TABLE 2-1:
Num Pins
SIGNALS
Name
Buffer
Type
(Note 2-1)
Description
Programmable LED output to indicate port activity/status.
LED is ON when output is LOW; LED is OFF when output is HIGH.
Port 1 LED indicators* defined as follows:
1
2
P1LED1
P1LED0
Chip Global Control Register: CGCR bit [9]
IPU/O
0 (Default)
1
P1LED1
100BT
ACT
P1LED0
LINK/ACT
LINK
OPU
* Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;
Speed = LED On (100BASE-T); LED Off (10BASE-T)
Config Mode: The P1LED1 pull-up/pull-down value is latched as 16-/8bit mode during power-up/reset. See the Pin for strap-in options section
for details.
3
PME
OPU
Power Management Event (default active low): It is asserted (low or high
depends on polarity set in PMECR register) when one of the wake-onLAN events is detected by KSZ8851-16MLL. The KSZ8851-16MLL is
requesting the system to wake up from low power mode.
4
INTRN
OPU
Interrupt: An active low signal to host CPU to indicate an interrupt status
bit is set, this pin need an external 4.7 kΩ pull-up resistor.
5
RDN
IPU
Read Strobe Not
Asynchronous read strobe, active low to indicate read cycle.
6
WRN
IPU
Read Strobe Not
Asynchronous read strobe, active low to indicate read cycle.
7
DGND
GND
Digital Ground.
8
9
10
VDD_CO1.8
EED_IO
EESK
DS00002357B-page 10
P
1.8V regulator output. This 1.8V output pin provides power to pins 14
(VDD_A1.8) and 29 (VDD_D1.8) for core VDD supply.
If VDD_IO is set for 1.8V then this pin should be left floating, pins 14
(VDD_A1.8) and 29 (VDD_D1.8) will be sourced by the external 1.8V
supply that is tied to pins 27, 38 and 46 (VDD_IO) with appropriate filtering.
IPD/O
In/Out Data from/to external EEPROM.
Config Mode: The pull-up/pull-down value is latched as with/without
EEPROM during power-up/reset. See the Pin for strap-in options section for details.
IPD/O
EEPROM Serial Clock
A 4 µs (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns
(OBCR[1:0]=00 on-chip bus speed @ 125 MHz) serial output clock
cycle to load configuration data from the serial EEPROM.
Config Mode: The pull-up/pull-down value is latched as big-/little-Endian
mode during power-up/reset. See the Pin for strap-in options section for
details.
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
TABLE 2-1:
Num Pins
SIGNALS (CONTINUED)
Name
Buffer
Type
(Note 2-1)
Description
11
CMD
IPD
Command Type
This command input decides the SD[15:0] shared data bus access information.
When command input is low, the access of shared data bus is for data
access in 16-bit mode shared data bus SD[15:0] or in 8-bit mode shared
data bus SD[7:0].
When command input is high, the access of shared data bus is for
address A[7:2] access at shared data bus SD[7:2], byte enable BE[3:0]
at SD[15:12] and the SD[11:8] is “Do Not Care” in 16-bit mode. It is for
address A[7:0] access at SD[7:0] in 8-bit mode.
12
CSN
IPU
Chip Select Not
Chip select for the shared data bus access enable, active Low.
13
AGND
GND
Analog ground.
14
VDD_A1.8
P
15
EECS
OPD
16
RXP1
I/O
Port 1 physical receive signal (+ differential).
17
RXM1
I/O
Port 1 physical receive signal (– differential).
18
AGND
GND
19
TXP1
I/O
Port 1 physical transmit signal (+ differential).
20
TXM1
I/O
Port 1 physical transmit signal (– differential).
21
VDD_A3.3
P
3.3V analog VDD input power supply with well decoupling capacitors.
22
ISET
O
Set physical transmits output current.
Pull-down this pin with a 3.01 KΩ 1% resistor to ground.
23
RSTN
IPU
24
X1
I
25
X2
O
26
DGND
GND
27
VDD_IO
P
28
DGND
GND
29
VDD_D1.8
P
2018 Microchip Technology Inc.
1.8V analog power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same
source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.
EEPROM Chip Select
This signal is used to select an external EEPROM device.
Analog ground.
Reset Not
Hardware reset pin (active Low). This reset input is required minimum of
10 ms low after stable supply voltage 3.3V.
25 MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to
a 3.3V tolerant oscillator and X2 is a no connect.
Note: Clock requirement is ±50 ppm for either crystal or oscillator.
Digital ground
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
Digital ground
1.8V digital power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same
source as pins 27, 38, and 46 (VDD_IO) with appropriate filtering.
DS00002357B-page 11
KSZ8851-16MLL/MLLI/MLLU
TABLE 2-1:
Num Pins
30
31
32
SIGNALS (CONTINUED)
Name
SD15
SD14
SD13
Buffer
Type
(Note 2-1)
Description
I/O (PD)
Shared Data Bus bit 15. Data D15 access when CMD=0. Byte Enable 3
at double-word boundary access (BE3, 4th byte enable and active high)
in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus
mode.
I/O (PD)
Shared Data Bus bit 14. Data D14 access when CMD=0. Byte Enable 2
at double-word boundary access (BE2, 3rd byte enable and active high)
in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus
mode.
I/O (PD)
Shared Data Bus bit 13. Data D13 access when CMD=0. Byte Enable 1
at double-word boundary access (BE1, 2nd byte enable and active high)
in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus
mode.
33
SD12
I/O (PD)
Shared Data Bus bit 12. Data D12 access when CMD=0. Byte Enable 0
at double-word boundary access (BE0, 1st byte enable and active high)
in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus
mode.
34
SD11
I/O (PD)
Shared Data Bus bit 11. Data D11 access when CMD=0. Do Not Care
when CMD=1. This pin must be tied to GND in 8-bit bus mode.
35
SD10
I/O (PD)
Shared Data Bus bit 10. Data D10 access when CMD=0. Do Not Care
when CMD=1. This pin must be tied to GND in 8-bit bus mode.
36
SD9
I/O (PD)
Shared Data Bus bit 9. Data D9 access when CMD=0. Do Not Care
when CMD=1. This pin must be tied to GND in 8-bit bus mode.
37
DGND
GND
38
VDD_IO
P
39
SD8
I/O (PD)
Shared Data Bus bit 8. Data D8 access when CMD=0. Do Not
Care when CMD=1. This pin must be tied to GND in 8-bit bus
mode.
40
SD7
I/O (PD)
Shared Data Bus bit 7. Data D7 access when CMD=0. Address A7
access when CMD=1.
41
SD6
I/O (PD)
Shared Data Bus bit 6. Data D6 access when CMD=0. Address A6
access when CMD=1.
42
SD5
I/O (PD)
Shared Data Bus bit 5. Data D5 access when CMD=0. Address A5
access when CMD=1.
43
SD4
I/O (PD)
Shared Data Bus bit 4. Data D4 access when CMD=0. Address A4
access when CMD=1.
44
SD3
I/O (PD)
Shared Data Bus bit 3. Data D3 access when CMD=0. Address A3
access when CMD=1.
45
SD2
I/O (PD)
Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2
access when CMD=1.
DS00002357B-page 12
Digital ground.
3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well
decoupling capacitors.
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
TABLE 2-1:
SIGNALS (CONTINUED)
Num Pins
Name
Buffer
Type
(Note 2-1)
46
VDD_IO
P
47
SD1
I/O (PD)
Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode,
this is address A1 access when CMD=1. In 16-bit mode, this is “Do Not
Care” when CMD=1.
48
SD0
I/O (PD)
Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode,
this is address A0 access when CMD=1. In 16-bit mode, this is “Do Not
Care” when CMD=1.
Note 2-1
TABLE 2-2:
Num Pins
1
9
10
Note 2-2
Description
Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2
access when CMD=1.
P = Power supply
GND = Ground
I/O = Bi-directional
I = Input
O = Output
IPD = Input with internal pull-down (58 kΩ ±30%)
IPU = Input with internal pull-up (58 kΩ ±30%)
OPD = Output with internal pull-down (58 kΩ ±30%)
OPU = Output with internal pull-up (58 kΩ ±30%)
IPU/O = Input with internal pull-up (58 kΩ ±30%) during power-up/reset; output pin otherwise
IPD/O = Input with internal pull-down (58 kΩ ±30%) during power-up/reset; output pin otherwise
I/O (PD) = Input/Output with internal pull-down (58 kΩ ±30%)
PIN FOR STRAP-IN OPTIONS
Name
P1LED1
EED_IO
EESK
Buffer
Type
(Note 2-2)
Description
IPU/IO
8- or 16-bit bus mode select during power-up/reset:
NC or Pull-up (default) = 16-bit bus
Pull-down = 8-bit bus
This pin value is also latched into register CCR, bit 6/7.
IPD/O
EEPROM select during power-up/reset:
Pull-up = EEPROM present
NC or Pull-down (default) = EEPROM not present
This pin value is latched into register CCR, bit 9.
IPD/O
Endian mode select during power-up/reset:
Pull-up = Big Endian
NC or Pull-down (default) = Little Endian
This pin value is latched into register CCR, bit 10.
When this pin is no connect or tied to GND, the bit 11 (Endian mode
selection) in RXFDPR register can be used to program either Little
(bit11=0 default) Endian mode or Big (bit11=1) Endian mode.
IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.
IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset.
2018 Microchip Technology Inc.
DS00002357B-page 13
KSZ8851-16MLL/MLLI/MLLU
3.0
FUNCTIONAL DESCRIPTION
The KSZ8851-16MLL is a single-chip fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8851-16MLL via an 8-bit or 16-bit host bus
interface.
The KSZ8851-16MLL is fully compliant with IEEE802.3u standards.
3.1
Functional Overview
3.1.1
POWER MANAGEMENT
The KSZ8851-16MLL supports enhanced power management feature in low power state with energy detection to
ensure low-power dissipation during device idle periods. There are three operation modes under the power management function which is controlled by two bits in PMECR (0xD4) register as shown below:
PMECR[1:0] = 00 Normal Operation Mode
PMECR[1:0] = 01 Energy Detect Mode
PMECR[1:0] = 11 Power-Saving Mode
TABLE 3-1:
INTERNAL FUNCTION BLOCKS STATUSES
Power Management Operation Modes
KSZ8851-16MLL
Function Blocks
Normal Mode
Internal PLL Clock
Enabled
Enabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block disabled
Energy detect at Rx
3.1.2
Power-Saving Mode
Energy Detect Mode
MAC
Enabled
Enabled
Disabled
Host Interface
Enabled
Enabled
Disabled
NORMAL OPERATION MODE
This is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When
KSZ8851-16MLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal
operation mode to any one of the other three power management operation modes.
3.1.3
POWER SAVING MODE
The power-saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting
bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851M is in this mode, all PLL clocks are
enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this
mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains
transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting
by the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from
power-saving mode.
During this power-saving mode, the host CPU can program the bit[1:0] in PMECR register and set bit[10]=0 in
P1SCLMD register to transit the current power-saving mode to any one of the other three power management operation
modes.
3.1.4
ENERGY DETECT MODE
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present or it is connected to a
powered down partner, the KSZ8851-16MLL can automatically enter to the low power state in energy detect mode.
Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can
automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8851-16MLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver.
The energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851-16MLL is in this mode,
DS00002357B-page 14
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0]
Go-Sleep time in GSWUTR register, KSZ8851-16MLL will go into a low power state. When KSZ8851-16MLL is in low
power state, it will keep monitoring the cable energy. Once the energy is detected from the cable and is continuously
presented for a time longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ885116MLL will enter either the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal
operation mode if both auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.
The KSZ8851-16MLL will also assert PME output pin if the corresponding enable bit[8] is set in PMECR (0xD4) register
or generate interrupt to signal an energy detect event occurred if the corresponding enable bit[2] is set in IER (0x90)
register. Once the power management unit detects the PME output asserted or interrupt active, it will power up the host
CPU and issue a wakeup command which is a read cycle to read the Globe Reset Register (GRR at 0x26) to wake up
the KSZ8851-16MLL from the low power state to the normal power state in case the auto-wakeup enable bit[7] is disabled. When KSZ8851-16MLL is at normal power state, it is able to transmit or receive packet from the cable.
3.1.5
WAKE-ON-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device
is pre-programmed by the policy owner or other software with information on how to identify wake frames from other
network traffic. The KSZ8851-16MLL controller can be programmed to notify the host of the wake-up frame detection
with the assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).
A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state (working).
A wake-up signal is caused by:
1.
2.
3.
4.
Detection of energy signal over a pre-configured value (bit 2 in ISR register)
Detection of a linkup in the network link state (bit 3 in ISR register)
Receipt of a Magic Packet (bit 4 in ISR register)
Receipt of a network wake-up frame (bit 5 in ISR register)
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these
in their own ways.
3.1.6
DETECTION OF ENERGY
The energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state.
3.1.7
DETECTION OF LINKUP
Link status wake events are useful to indicate a linkup in the network’s connectivity status.
3.1.8
WAKE-UP PACKET
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a wake-up frame.
The KSZ8851-16MLL supports up to four users defined wake-up frames as below:
• Wake-up frame 0 is defined in wakeup frame registers (0x30 – 0x3B) and is enabled by bit 0 in wakeup frame control register (0x2A).
• Wake-up frame 1 is defined in wakeup frame registers (0x40 – 0x4B) and is enabled by bit 1 in wakeup frame control register (0x2A).
• Wake-up frame 2 is defined in wakeup frame registers (0x50 – 0x5B) and is enabled by bit 2 in wakeup frame control register (0x2A).
• Wake-up frame 3 is defined in wakeup frame registers (0x60 – 0x6B) and is enabled by bit 3 in wakeup frame control register (0x2A).
3.1.9
MAGIC PACKET™
Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by
sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable
of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the
LAN controller receives a Magic Packet frame, it will alert the system to wake up.
2018 Microchip Technology Inc.
DS00002357B-page 15
KSZ8851-16MLL/MLLI/MLLU
Magic Packet is a standard feature integrated into the KSZ8851-16MLL. The controller implements multiple advanced
power-down modes including Magic Packet to conserve power and operate more efficiently.
Once the KSZ8851-16MLL has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames
addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address
(SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address
and CRC.
The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This
sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as 6 bytes
of FFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the
address of the machine to be awakened.
Example:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scanning for the data sequence (assuming an Ethernet frame):
DESTINATION SOURCE – MISC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66
-11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66
- 11 22 33 44 55 66 - MISC - CRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or
an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node
at the frame’s destination.
If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and
takes no further action. If the KSZ8851-16MLL controller detects the data sequence, however, it then alerts the PC’s
power management circuitry (assert the PME pin) to wake up the system.
3.2
3.2.1
Physical Layer Transceiver (PHY)
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 3.01 kΩ
(1%) resistor for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASETX driver.
3.2.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
DS00002357B-page 16
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
3.2.3
PLL CLOCK SYNTHESIZER (RECOVERY)
The internal PLL clock synthesizer can generate either 125 MHz, 62.5 MHz, 41.66 MHz, or 25 MHz clocks by setting
the on-chip bus control register (0x20) for KSZ8851-16MLL system timing. These internal clocks are generated from an
external 25 MHz crystal or oscillator.
3.2.4
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander.
Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler
generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the
same sequence as at the transmitter.
3.2.5
10BASE-T TRANSMIT
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with typical 2.4V amplitude. The harmonic contents
are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
3.2.6
10BASE-T RECEIVE
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function.
The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with
levels less than 400 mV or with short pulse widths to prevent noise at the RXP1 or RXM1 input from falsely triggering
the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8851-16MLL
decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
3.2.7
MDI/MDI-X AUTO CROSSOVER
To eliminate the need for crossover cables between similar devices, the KSZ8851-16MLL supports HP-Auto MDI/MDIX and IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs
for the KSZ8851-16MLL device. This feature is extremely useful when end users are unaware of cable types in addition
to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port
control registers. The IEEE 802.3u standard MDI and MDI-X definitions are shown in Table 3-2.
2018 Microchip Technology Inc.
DS00002357B-page 17
KSZ8851-16MLL/MLLI/MLLU
TABLE 3-2:
MDI/MDI-X PIN DEFINITIONS
MDI
3.2.8
MDI-X
RJ45 Pins
Signals
RJ45 Pins
Signals
1
TD+
1
RD+
2
TD–
2
RD–
3
RD+
3
TD+
6
RD–
6
TD–
STRAIGHT CABLE
A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following diagram shows a typical straight cable connection between a network interface card (NIC) and a switch, or hub (MDI-X).
FIGURE 3-1:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
1
2
2
TRANSMIT PAIR
RECEIVE PAIR
3
STRAIGHT
CABLE
3
4
4
5
5
6
6
7
7
8
8
RECEIVE PAIR
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
NIC
DS00002357B-page 18
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
3.2.9
CROSSOVER TABLE
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The
following diagram shows a typical crossover cable connection between two chips or hubs (two MDI-X devices).
FIGURE 3-2:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
RECEIVE PAIR
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
CROSSOVER
CABLE
1
RECEIVE PAIR
2
2
3
3
4
4
5
5
6
6
7
7
8
8
TRANSMIT PAIR
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
2018 Microchip Technology Inc.
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
DS00002357B-page 19
KSZ8851-16MLL/MLLI/MLLU
3.2.10
AUTO NEGOTIATION
The KSZ8851-16MLL conforms to the auto negotiation protocol as described by the 802.3 committee to allow the port
to operate at either 10BASE-T or 100BASE-TX.
Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In
auto negotiation, the link partners advertise capabilities across the link to each other. If auto negotiation is not supported
or the link partner to the KSZ8851-16MLL is forced to bypass auto negotiation, the mode is set by observing the signal
at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The auto negotiation link setup is shown as
follows:
FIGURE 3-3:
AUTO NEGOTIATION AND PARALLEL OPERATION
START AUTO NEGOTIATION
NO
PARALLEL
OPERATION
FORCE LINK SETTING
YES
BYPASS AUTO NEGOTIATION
AND SET LINK MODE
ATTEMPT AUTO
NEGOTIATION
LISTEN FOR
100BASE-TX
IDLES
LISTEN FOR
10BASE-T
LINK PULSES
JOIN
FLOW
NO
LINK MODE SET?
YES
LINK MODE SET
DS00002357B-page 20
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
3.2.11
LINKMD® CABLE DIAGNOSTICS
The KSZ8851-16MLL LinkMD® uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling
problems such as open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a
maximum distance of 200m and an accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable
digital format in register P1SCLMD[8:0].
Note: cable diagnostics are only valid for copper connections – fiber-optic operation is not supported.
3.2.11.1
Access
LinkMD is initiated by accessing register P1SCLMD, the PHY special control/status and LinkMD register (0xF4).
3.2.11.2
Usage
LinkMD can be run at any time by ensuring that Auto-MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to
P1CR[10] to enable manual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic
test enable bit, P1SCLMD [12], is set to ‘1’ to start the test on this pair.
When bit P1SCLMD[12] returns to ‘0’, the test is complete. The test result is returned in bits P1SCLMD[14:13] and the
distance is returned in bits P1SCLMD[8:0]. The cable diagnostic test results are as follows:
00 = Valid test, normal condition
01 = Valid test, open circuit in cable
10 = Valid test, short circuit in cable
11 = Invalid test, LinkMD failed
If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851-16MLL is unable to shut down the
link partner. In this instance, the test is not run, as it is not possible for the KSZ8851-16MLL to determine if the detected
signal is a reflection of the signal generated or a signal from another source.
Cable distance can be approximated by the following formula:
P1SCLMD[8:0] x 0.4m for port 1 cable distance
This constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.
3.3
Media Access Control (MAC) Operation
The KSZ8851-16MLL strictly abides by IEEE 802.3 standards to maximize compatibility.
3.3.1
INTER PACKET GAP (IPG)
If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive packets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is measured from carrier sense
(CRS) to the next transmit packet.
3.3.2
BACK-OFF ALGORITHM
The KSZ8851-16MLL implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode.
After 16 collisions, the packet is dropped.
3.3.3
LATE COLLISION
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
3.3.4
FLOW CONTROL
The KSZ8851-16MLL supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8851-16MLL receives a pause control frame, the KSZ8851-16MLL will not transmit the
next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before
the current timer expires, the timer will be updated with the new value in the second pause frame. During this period
(while it is flow controlled), only flow control packets from the KSZ8851-16MLL are transmitted.
2018 Microchip Technology Inc.
DS00002357B-page 21
KSZ8851-16MLL/MLLI/MLLU
On the transmit side, the KSZ8851-16MLL has intelligent and efficient ways to determine when to invoke flow control.
The flow control is based on availability of the system resources.
There are three programmable low watermark register FCLWR (0xB0), high watermark register FCHWR (0xB2) and
overrun watermark register FCOWR (0xB4) for flow control in RXQ FIFO. The KSZ8851-16MLL will send PAUSE frame
when the RXQ buffer hit the high watermark level (default 3.072 KB available) and stop PAUSE frame when the RXQ
buffer hit the low watermark level (default 5.12 KB available). The KSZ8851-16MLL will drop packet when the RXQ buffer hit the overrun watermark level (default 256 Bytes available).
The KSZ8851-16MLL issues a flow control frame (Xoff, or transmitter off), containing the maximum pause time defined
in IEEE standard 802.3x. Once the resource is freed up, the KSZ8851-16MLL sends out the another flow control frame
(Xon, or transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis
feature is provided to prevent the flow control mechanism from being constantly activated and deactivated.
3.3.5
HALF-DUPLEX BACKPRESSURE
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8851-16MLL sends preambles to defer
the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851-16MLL
discontinues the carrier sense backpressure and then raises it again quickly. This short silent time (no carrier sense)
prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. The short
silent time is about 4 µs and repeat every 1.64 ms in the backpressure jam patter for 10BASE-T. If the port has packets
to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until chip
resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet reception.
3.3.6
ADDRESS FILTERING FUNCTION
The KSZ8851-16MLL supports 11 different address filtering schemes as shown in Table 3-3. The Ethernet destination
address (DA) field inside the packet is the first 6-byte field which uses to compare with either the host MAC address
registers (0x10 – 0x15) or the MAC address hash table registers (0xA0 – 0xA7) for address filtering operation. The first
bit (bit 40) of the destination address (DA) in the Ethernet packet decides whether this is a physical address if bit 40 is
“0” or a multicast address if bit 40 is “1”.
TABLE 3-3:
ADDRESS FILTERING SCHEME
Receive Control Register (0x74 – 0x75):
RXCR1
Item
Address Filtering
Mode
RX All
(Bit 4)
RX
Inverse
(Bit 1)
RX
RX
Physical Multicast
Address Address
(Bit 11)
(Bit 8)
Description
1
Perfect
0
0
1
1
All Rx frames are passed only if the
DA exactly matches the MAC
address in MARL, MARM and MARH
registers.
2
Inverse perfect
0
1
1
1
All Rx frames are passed if the DA is
not matching the MAC address in
MARL, MARM and MARH registers.
0
All Rx frames with either multicast or
physical destination address are filtering against the MAC address hash
table.
3
Hash only
DS00002357B-page 22
0
0
0
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Receive Control Register (0x74 – 0x75):
RXCR1
Item
4
Address Filtering
Mode
RX All
(Bit 4)
Inverse hash only
0
RX
Inverse
(Bit 1)
1
RX
RX
Physical Multicast
Address Address
(Bit 11)
(Bit 8)
0
Description
0
All Rx frames with either multicast or
physical destination address are filtering not against the MAC address
hash table.
All Rx frames which are filtering out
at item 3 (Hash only) only are passed
in this mode.
5
Hash perfect
(Default)
0
0
1
0
All Rx frames are passed with Physical address (DA) matching the MAC
address and to enable receive multicast frames that pass the hash table
when Multicast address is matching
the MAC address hash table.
6
Inverse hash perfect
0
1
1
0
All Rx frames which are filtering out
at item 5 (Hash perfect) only are
passed in this mode.
7
Promiscuous
1
1
0
0
All Rx frames are passed without any
conditions.
8
Hash only with Multicast address passed
0
All Rx frames are passed with Physical address (DA) matching the MAC
address hash table and with Multicast address without any conditions.
9
Perfect with Multicast address passed
1
All Rx frames are passed with Physical address (DA) matching the MAC
address and with Multicast address
without any conditions.
10
Hash only with Physical address passed
0
All Rx frames are passed with Multicast address matching the MAC
address hash table and with Physical
address without any conditions.
11
Perfect with Physical address passed
1
All Rx frames are passed with Multicast address matching the MAC
address and with Physical address
without any conditions.
1
1
1
1
0
0
0
0
0
1
1
0
Note 1: 3.Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set to 1 in RXCR1
register.
2: 4.The KSZ8851-16MLL will discard frame with the same SA as the MAC address if bit[0] is set in RXCR2
register.
3.3.7
CLOCK GENERATOR
The X1 and X2 pins are connected to a 25 MHz crystal. X1 can also serve as the connector to a 3.3V, 25 MHz oscillator
(as described in the Pin Description and Configuration section).
2018 Microchip Technology Inc.
DS00002357B-page 23
KSZ8851-16MLL/MLLI/MLLU
3.4
Bus Interface Unit (BIU)
The BIU host interface is a generic shared data bus interface, designed to communicate with embedded processors.
No glue logic is required when it talks to various standard asynchronous buses and processors.
3.4.1
SUPPORTED TRANSFERS
In terms of transfer type, the BIU can support asynchronous transfer or SRAM-like slave mode. To support the data
transfers, the BIU provides a group of signals:
Shared Data bus SD[15:0] for Address, Data and Byte Enable, Command (CMD), Chip Select Enable (CSN), Read
(RDN), Write (WRN) and Interrupt (INTRN).
3.4.2
PHYSICAL DATA BUS SIZE
The BIU supports an 8-bit or 16-bit host standard data bus. Depending on the size of the physical data bus, the
KSZ8851-16MLL can support 8-bit or 16-bit data transfers.
For example:
For a 16-bit data bus mode, the KSZ8851-16MLL allows an 8-bit and 16-bit data transfer.
For an 8-bit data bus mode, the KSZ8851-16MLL only allows an 8-bit data transfer.
The KSZ8851-16MLL supports internal data byte-swap. This means that the system/host data bus HD[7:0] just connect
to SD[7:0] for an 8-bit data bus interface. For a 16-bit data bus, the system/host data bus HD[15:8] and HD[7:0] only
need to connect to SD[15:8] and SD[7:0] respectively.
Table 3-4 describes the BIU signal grouping.
TABLE 3-4:
BUS INTERFACE UNIT SIGNAL GROUPING
Signal
Type
Function
Shared Data Bus
Data D[15:0] → SD[15:0] access when CMD=0. Address A[7:2] → SD[7:2]
and Byte Enable BE[3:0] → SD[15:12] access when CMD=1 in 16-bit mode.
Address A[7:0] → SD[7:0] only access when CMD=1 in 8-bit mode (Shared
data bus SD[15:8] must be tied to low in 8-bit bus mode).
SD[15:0]
I/O
CMD
Input
Command Type
This command input decides the SD[15:0] shared data bus access cycle information.
CSN
Input
Chip Select Enable
Chip Enable asserted (low) indicates that the shared data bus access is
enabled.
INTRN
Output
RDN
Input
Asynchronous Read
This pin is asserted to low during read cycle.
WRN
Input
Asynchronous Write
This pin is asserted to low during write cycle.
3.4.3
Interrupt
This pin is asserted to low when interrupt occurred.
LITTLE AND BIG ENDIAN SUPPORT
The KSZ8851-16MLL supports either Little- or Big-Endian microprocessor. The external strap pin 10 (EESK) is used to
select between two modes. The KSZ8851-16MLL operates in Little Endian when this pin is pulled-down or in Big Endian
when this pin is pulled-up.
When this pin 10 is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to
program either Little (bit11=0) Endian mode or Big (bit11=1) Endian mode.
DS00002357B-page 24
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
3.4.4
ASYNCHRONOUS INTERFACE
For asynchronous transfers, the asynchronous interface uses RDN (read) and WRN (write) signal strobes for data latching. The host utilizes the rising edge of RDN to latch READ data when the host read data from KSZ8851-16MLL. The
KSZ8851-16MLL utilizes the internal pulse to latch WRITE data based on the RXFDPR register bit 12 setting.
All asynchronous transfers are either single-data or burst-data transfers. Byte or word data bus access (transfers) is
supported. The BIU, however, provides flexible asynchronous interfacing to communicate with various applications and
architectures. No additional address latch is required. The BIU qualifies both CSN (Chip Select) pin and WRN (Write
Enable) pin to write the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address A[7:0] value (in 8-bit mode) into
KSZ8851-16MLL when CMD (Command type) pin is high. The BIU qualifies both CSN (Chip Select) pin and RDN (Read
Enable) or WRN (Write Enable) pin to read or write the SD[15:0] data value from or to KSZ8851-16MLL when CMD
(Command type) pin is low.
In order for software to read back the previous CMD register write value when CMD is “1”, the BIU qualifies both CSN
(Chip Select) pin and RDN (Read Enable) pin to read the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address
A[7:0] value (in 8-bit mode) back from KSZ8851-16MLL when CMD (Command type) pin is high.
3.4.5
BIU SUMMATION
Figure 3-4 shows the connection for different data bus sizes. Note that in 16-bit bus mode, the SD1 bit must be set to
“1” when CMD = 1 during DMA access. Refer to reference schematics in hardware design package for further details.
All of control and status registers in the KSZ8851-16MLL are accessed indirectly depending on CMD (Command type)
pin. The command sequence to access the specified control or status register is to write the register’s address (when
CMD=1) then read or write this register data (when CMD=0). If both RDN and WRN signals in the system are only used
for KSZ8851-16MLL, the CSN pin can be forced to active low to simplify the system design. The CMD pin can be connected to host address line HA0 for 8-bit bus mode or HA1 for 16-bit bus mode.
FIGURE 3-4:
KSZ8851-16MLL 8-BIT AND 16-BIT DATA BUS CONNECTIONS
KSZ8851-16MLL
HA0
CMD
HD[7:0]
SD[7:0]
SD[15:8]
GND
/CS
/WR
/RD
CSN
WRN
RDN
IRQ
INTRN
8-bit Data Bus
3.5
1K ohm
P1LED1
8-Bit Bus Mode
16-Bit Bus Mode
Pin 1 (P1LED1) = 1K Pull
Down during RESET
Pin 1 (P1LED1) = NC or
Pull Up during RESET
Shared
Data Bus
CMD=0
“Low”
CMD=1
“High”
CMD=0
“Low”
CMD=1
“High”
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
D0
D1
D2
D3
D4
D5
D6
D7
GND
GND
GND
GND
GND
GND
GND
GND
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
GND
GND
GND
GND
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A2
A3
A4
A5
A6
A7
BE0
BE1
BE2
BE3
KSZ8851-16MLL
HA1
HD[7:0]
HD[15:8]
CMD
SD[7:0]
SD[15:8]
P1LED1
/CS
/WR
/RD
CSN
WRN
RDN
IRQ
INTRN
NC
16-bit Data Bus
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It
has built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue).
Each queue contains 12 KB for RXQ and 6 KB for TXQ of memory with back-to-back, non-blocking frame transfer performance. It provides a group of control registers for system control, frame status registers for current packet transmit/
receive status, and interrupts to inform the host of the real time TX/RX status.
3.5.1
TRANSMIT QUEUE (TXQ) FRAME FORMAT
The frame format for the transmit queue is shown in Table 3-5. The first word contains the control information for the
frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data follows.
The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon whether
hardware CRC checksum generation is enabled in TXCR (bit 1) register.
2018 Microchip Technology Inc.
DS00002357B-page 25
KSZ8851-16MLL/MLLI/MLLU
Multiple frames can be pipelined in the receive queue as long as there is enough queue memory, thus avoiding overrun.
For each transmitted frame, the transmit status information for the frame is located in the TXSR (0x72) register.
TABLE 3-5:
FRAME FORMAT FOR TRANSMIT QUEUE
Packet Memory Address Offset
Bit 15
2nd Byte
Bit 0
1st Byte
0
Control Word
(High byte and low byte need to swap in Big Endian mode)
2
Byte Count
(High byte and low byte need to swap in Big Endian mode)
4 - up
Transmit Packet Data
(Maximum size is 2000 bytes)
Because packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of the
packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the
TX queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be
word aligned. Each control word corresponds to one TX packet. Table 3-6 gives the transmit control word bit fields.
TABLE 3-6:
TRANSMIT CONTROL WORD BIT FIELDS
Bit
15
Description
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8851-16MLL sets the transmit interrupt after the
present frame has been transmitted.
14-6
Reserved.
5-0
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status information in the transmit status register.
The transmit byte count specifies the total number of bytes to be transmitted from the TXQ. Its format is provided in
Table 3-7.
TABLE 3-7:
TRANSMIT BYTE COUNT FORMAT
Bit
Description
15-11
Reserved.
10-0
TXBC Transmit Byte Count
Hardware uses the byte count information to conserve the TX buffer memory for
better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is
written to this field. Writing a 0 value to this field is not permitted.
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed
by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851-16MLL does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted
by the KSZ8851-16MLL. It is treated transparently as data both for transmit operations.
3.5.2
FRAME TRANSMITTING PATH OPERATION IN TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851-16MLL with
generic bus interface. User can use the default value for most of the transmit registers. Table 3-8 describes all registers
which need to be set and used for transmitting single frames.
DS00002357B-page 26
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
TABLE 3-8:
REGISTERS SETTING FOR TRANSMIT FUNCTION BLOCK
Register Name
[bit](offset)
Description
TXCR[3:0](0x70)
TXCR[8:5](0x70)
Set transmit control function as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting
padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block
operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
TXMIR[12:0](0x78)
The amount of free transmit memory available is represented in units of byte.
The TXQ memory (6 KB) is used for both frame payload and control word.
TXQCR[0](0x80)
For single frame to transmit, set this bit 0 = 1(manual enqueue). the
KSZ8851-16MLL will enable current TX frame prepared in the TX buffer is
queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to be cleared before setting up another new TX
frame.
TXQCR[1](0x80)
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6
in ISR register) to CPU when TXQ memory is available based upon the total
amount of TXQ space requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to be cleared before set to 1 again.
RXQCR[3](0x82)
Set bit 3 to start DMA access from host CPU either read (receive frame data)
or write (transmit data frame).
TXFDPR[14](0x84)
Set bit 14 to enable TXQ transmit frame data pointer register increments
automatically on accesses to the data register.
IER[14][6](0x90)
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in
Interrupt Status Register.
TXNTFSR[15:0](0x9E)
The host CPU is used to program the total amount of TXQ buffer space which
is required for next total transmit frames size in double-word count.
2018 Microchip Technology Inc.
DS00002357B-page 27
KSZ8851-16MLL/MLLI/MLLU
3.5.3
DRIVER ROUTINE FOR TRANSMIT PACKET FROM HOST PROCESSOR TO KSZ885116MLL
The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller.
It is user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while
transmitting the frame, it’s the user’s choice to decide whether the driver should attempt to retransmit the same frame
or discard the data. Table 3-5 shows the step-by-step for single transmit packets from host processor to KSZ885116MLL.
FIGURE 3-5:
HOST TX SINGLE FRAME IN MANUAL ENQUEUE FLOW DIAGRAM
Host receives an Ethernet pkt from
upper layer and prepares transmit pkt
data (data, data_length, frame ID).
The transmit queue frame format is
shown in Table 5
Check if KSZ8851M TXQ
Memory size is available for this
transmit pkt?
(Read TXMIR Reg)
No
Write the total amount of TXQ buffer
space which is required for next
transmit frame size in double-word
count in TXNTFSR[15:0] register
Set bit 1=1 in TXQCR register to
enable the TXQ memory available
monitor
Yes
Write an “1” to RXQCR[3] reg to enable
TXQ write access, then Host starts
write transmit data (control word, byte
count and pkt data) to TXQ memory.
This is moving transmit data from Host
to KSZ8851M TXQ memory until whole
pkt is finished
Yes
Wait for interrupt
and check if the bit 6=1
(memory space available)
in ISR register
?
No
Write an “0” to RXQCR[3] reg to end
TXQ write access
Write an “1” to TXQCR[0] reg to issue a
transmit command (manual-enqueue)
to the TXQ. The TXQ will transmit this
pkt data to the PHY port
Option to Read ISR[14] reg, it indicates
that the TXQ has completed to transmit
at least one pkt to the PHY port, then
Write “1” to clear this bit
DS00002357B-page 28
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
3.5.4
FRAME QUEUE (RXQ) FRAME FORMAT
The frame format for the receive queue is shown in Table 3-9. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
TABLE 3-9:
FRAME FORMAT FOR RECEIVE QUEUE
Packet Memory Address Offset
Bit 0
1st Byte
0
Status Word
(High byte and low byte need to swap in Big Endian mode. Also see description in RXFHSR register.)
2
Byte Count
(High byte and low byte need to swap in Big Endian mode. Also see description in RXFHSR register.)
4 - up
3.5.5
Bit 15
2nd Byte
Receive Packet Data
(Maximum size is 2000 bytes)
FRAME RECEIVING PATH OPERATION IN RXQ
This section describes the typical register settings for receiving packets from KSZ8851-16MLL to host processor with
generic bus interface. User can use the default value for most of the receive registers. Table 3-10 describes all registers
which need to be set and used for receiving single or multiple frames.
TABLE 3-10:
REGISTERS SETTINGS FOR RECEIVE FUNCTION BLOCK
Register Name[bit](offset)
Description
RXCR1(0x74)
RXCR2(0x76)
Set receive control function as below:
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable
receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in Table 3-3.
RXFHSR[15:0](0x7C)
This register (read only) indicates the current received frame header status
information.
RXFHBCR[11:0](0x7E)
This register (read only) indicates the current received frame header byte
count information.
RXQCR[12:3](0x82)
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data)
or write (transmit data frame). Set bit 4 to automatically enable RXQ frame
buffer dequeue. Set bit 5 to enable RX frame count threshold and read bit 10
for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12
for status. Set bit 9 enable RX IP header two-byte offset.
RXFDPR[14](0x86)
Set bit 14 to enable RXQ address register increments automatically on
accesses to the data register.
RXDTTR[15:0](0x8C)
To program received frame duration timer value. When Rx frame duration in
RXQ exceeds this threshold in 1uS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851-16MLL will generate RX interrupt in ISR[13] and
indicate the status in RXQCR[12].
RXDBCTR[15:0](0x8E)
To program received data byte count value. When the number of received
bytes in RXQ exceeds this threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851-16MLL will generate RX interrupt in ISR[13] and
indicate the status in RXQCR[11].
IER[13](0x90)
Set bit 13 to enable receive interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in
Interrupt Status Register.
2018 Microchip Technology Inc.
DS00002357B-page 29
KSZ8851-16MLL/MLLI/MLLU
Register Name[bit](offset)
Description
RXFCTR[15:8](0x9C)
Rx frame count read only. To indicate the total received frame in RXQ frame
buffer when receive interrupt (bit 13 in ISR) occurred.
RXFCTR[7:0](0x9C)
To program received frame count value. When the number of received frames
in RXQ exceeds or equals to this threshold value and bit 5 of RXQCR register
is set to 1, the KSZ8851-16MLL will generate RX interrupt in ISR[13] and indicate the status in RXQCR[10].
3.5.6
DRIVER ROUTINE FOR RECEIVE PACKET FROM KSZ8851-16MLL TO HOST PROCESSOR
The software driver receives data packet frames from the KSZ8851-16MLL device either as a result of polling or an interrupt based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt
vector table.
If your system has OS support, to minimize interrupt lockout time, the interrupt service routine should handle at interrupt
level only those tasks that require minimum execution time, such as error checking or device status change. The routine
should queue all the time-consuming work to transfer the packet from the KSZ8851-16MLL RXQ into system memory
at task level. The following Figure 3-6 shows the step-by-step for receive packets from KSZ8851-16MLL to host processor.
Note: Each DMA read operation from the host CPU to read RXQ frame buffer, the first read data (byte in 8-bit bus mode,
word in 16-bit bus mode and double word in 32-bit bus mode) is dummy data and must be discarded by host CPU. Afterward, host CPU must read each frame data to align with double word boundary at end. For example, the host CPU has
to read up to 68 bytes if received frame is 65 bytes.
FIGURE 3-6:
HOST RX SINGLE OR MULTIPLE FRAMES IN AUTO-DEQUEUE FLOW DIAGRAM
To program Rx frame count threshold in
RXFCTR, Rx data byte count threshold in
RXDBCTR or Rx frame duration timer
threshold in RXDTTR.
Enable all thresholds bits in RXQCR[5:7].
Set bit 4 in RXQCR to enable RXQ frame
buffer auto-dequeue
Enable Rx interrupt in IER[13]
No
Is Rx interrupt status bit set in
ISR[13] when interrupt asserted?
Yes
Rx interrupt source can be read from
bits in RXQCR[10:12]. Mask out further
Rx interrupt by set bit 13 to 0 in IER
and clear Rx interrupt status by write 1
to bit 13 in ISR.
Read total Rx frame count in RXFCTR
and read Rx frame header status in
RXFHSR and byte count in RXFHBCR.
Write 0x000 to RXFDPR[10:0] to clear
RX frame pointer
Write an “1” to RXQCR[3] reg to enable
RXQ read access, the Host CPU starts
read frame data from RXQ buffer.
Is all Rx frames read?
No
Yes
Write an “0” to RXQCR[3] reg to end
RXQ read access
In order to read received frames from RXQ without error, the software driver must use following steps:
DS00002357B-page 30
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
When receive interrupt occurred and software driver writes “1” to clear the RX interrupt in ISR register; the KSZ8851 will
update Receive Frame Counter (RXFCTR) Register for this interrupt.
When software driver reads back Receive Frame Count (RXFCTR) Register; the KSZ8851 will update both Receive
Frame Header Status and Byte Count Registers (RXFHSR/RXFHBCR).
When software driver reads back both Receive Frame Header Status and Byte Count Registers (RXFHSR/RXFHBCR);
the KSZ8851 will update next receive frame header status and byte count registers (RXFHSR/RXFHBCR).
3.6
EEPROM Interface
It is optional in the KSZ8851-16MLL to use an external EEPROM. The EED_IO (pin 9) must be pulled high to use external EEPROM otherwise this pin pulled low or floating without EEPROM.
An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such
as the host MAC address. The KSZ8851-16MLL can detect if the EEPROM is a 1 Kb (93C46) EEPROM device. The
EEPROM must be organized as 16-bit mode.
If the EED_IO pin is pulled high, then the KSZ8851-16MLL performs an automatic read of the external EEPROM words
0H to 3H after the de-assertion of Reset. The EEPROM values are placed in certain host-accessible registers. EEPROM
read/write functions can also be performed by software read/writes to the EEPCR (0x22) registers.
The KSZ8851-16MLL EEPROM format is given in Table 3-11.
TABLE 3-11:
KSZ8851-16MLL EEPROM FORMAT
Word
15
8
7
0
0H
Reserved
1H
Host MAC Address Byte 2
Host MAC Address Byte 1
2H
Host MAC Address Byte 4
Host MAC Address Byte 3
3H
Host MAC Address Byte 6
Host MAC Address Byte 5
4H - 6H
Reserved
7H - 3FH
Not used for KSZ8851-16MLL (available for user to use)
3.7
Loopback Support
The KSZ8851-16MLL provides two loopback modes, one is near-end (remote) loopback to support for remote diagnostic of failure at line side, and the other is far-end (local) loopback to support for local diagnostic of failure at host side. In
loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode.
3.7.1
NEAR-END (REMOTE) LOOPBACK
Near-end (remote) loopback is conducted at PHY port 1 of the KSZ8851-16MLL. The loopback path starts at the PHY
port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXP1/TXM1).
Bit [9] of register P1SCLMD (0xF4) is used to enable near-end loopback. The ports 1 near-end loopback path is illustrated in Figure 3-7.
3.7.2
FAR-END (LOCAL) LOOPBACK
Far-end (Local) loopback is conducted at Host of the KSZ8851-16MLL. The loopback path starts at the host port’s transmit inputs (Tx data), wraps around at the PHY port’s PMD/PMA, and ends at the host port’s receive outputs (Rx data).
Bit [14] of register P1MBCR (0xE4) is used to enable far-end loopback at host side. The host far-end loopback path is
illustrated in Figure 3-7.
2018 Microchip Technology Inc.
DS00002357B-page 31
KSZ8851-16MLL/MLLI/MLLU
FIGURE 3-7:
PHY PORT 1 NEAR-END (REMOTE) AND HOST FAR-END (LOCAL) LOOPBACK
PATHS
RXP1 /
RXM 1
TXP1 /
TXM 1
(PHY Port 1 Near-end remote Loopback)
PMD1/PMA1
PCS1
MAC1
RXQ/TXQ
QMU/DMA
Bus I/F Unit
(Host Far-end local Loopback)
Host
RX Data
DS00002357B-page 32
Host
TX Data
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.0
CPU INTERFACE I/O REGISTERS
The KSZ8851-16MLL provides an SRAM-like asynchronous bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used
for configuring operational settings, reading or writing control, status information, and transferring packets. The
KSZ8851-16MLL can be programmed to interface with either Big-Endian or Little-Endian processor.
4.0.1
I/O REGISTERS
The following I/O space mapping tables apply to 8- or 16-bit bus interfaces. Depending upon the bus mode selected,
each I/O access can be performed the following operations:
In 8-bit bus mode, there are 256 address locations which is based on SD[7:0] for address when CMD=1. The SD[7:0]
is for data when CMD=0.
In 16-bit bus mode, there are 64 address locations which is based on SD[7:2] ([1:0] is “Do Not Care”) for address and
SD[15:12] for Byte Enable BE[3:0] (either one byte or two bytes) when CMD=1. The SD[15:0] is for data when CMD=0.
TABLE 4-1:
INTERNAL I/O REGISTERS SPACE MAPPING
I/O Register Offset Location
Register Name Default Value
16-Bit
8-Bit
0x00 - 0x01
0x00
0x01
0x02 - 0x03
0x02
0x03
0x04 - 0x05
0x04
0x05
0x06 - 0x07
0x06
0x07
0x08 - 0x09
Description
Reserved
Do Not Care
None
Reserved
Do Not Care
None
0x08
0x09
CCR
Read Only
Chip Configuration Register [7:0]
Chip Configuration Register [15:8]
0x0A - 0x0B
0x0A
0x0B
Reserved
Do Not Care
None
0x0C - 0x0D
0x0C
0x0D
0x0E
0x0F
Reserved
Do Not Care
None
0x0E - 0x0F
0x010 - 0x011
0x10
0x11
MARL
—
MAC Address Register Low [7:0]
MAC Address Register Low [15:8]
0x012 - 0x013
0x12
0x13
MARM
—
MAC Address Register Middle [7:0]
MAC Address Register Middle [15:8]
0x014 - 0x015
0x14
0x15
MARH
—
MAC Address Register High [7:0]
MAC Address Register High [15:8]
0x16 - 0x17
0x16
0x17
Reserved
Do Not Care
None
0x18 - 0x19
0x18
0x19
0x1A
0x1B
Reserved
Do Not Care
None
0x1A - 0x1B
0x1C - 0x1D
0x1C
0x1D
0x1E
0x1F
Reserved
Do Not Care
None
0x1E - 0x1F
0x20 - 0x21
0x20
0x21
OBCR
0x0000
On-Chip Bus Control Register [7:0]
On-Chip Bus Control Register [15:8]
2018 Microchip Technology Inc.
DS00002357B-page 33
KSZ8851-16MLL/MLLI/MLLU
TABLE 4-1:
INTERNAL I/O REGISTERS SPACE MAPPING (CONTINUED)
I/O Register Offset Location
Register Name Default Value
Description
16-Bit
8-Bit
0x22 - 0x23
0x22
0x23
EEPCR
0x0000
EEPROM Control Register [7:0]
EEPROM Control Register [15:8]
0x24 - 0x25
0x24
0x25
MBIR
0x1010
Memory BIST Info Register [7:0]
Memory BIST Info Register [15:8]
0x26 - 0x27
0x26
0x27
GRR
0x000
Global Reset Register [7:0]
Global Reset Register [15:8]
0x28 - 0x29
0x28
0x29
Reserved
Do Not Care
None
0x2A - 0x2B
0x2A
0x2B
WFCR
0x0000
Wakeup Frame Control Register [7:0]
Wakeup Frame Control Register [15:8]
0x2C - 0x2D
0x2C
0x2D
Reserved
Do Not Care
None
0x2E - 0x2F
0x2E
0x2F
0x30 - 0x31
0x30
0x31
WF0CRC0
0x0000
Wakeup Frame 0 CRC0 Register [7:0]
Wakeup Frame 0 CRC0 Register [15:8]
0x32 - 0x33
0x32
0x33
WF0CRC1
0x0000
Wakeup Frame 0 CRC1 Register [7:0]
Wakeup Frame 0 CRC1 Register [15:8]
0x34 - 0x35
0x34
0x35
WF0BM0
0x0000
Wakeup Frame 0 Byte Mask 0 Register [7:0]
Wakeup Frame 0 Byte Mask 0 Register [15:8]
0x36 - 0x37
0x36
0x37
WF0BM1
0x0000
Wakeup Frame 0 Byte Mask 1 Register [7:0]
Wakeup Frame 0 Byte Mask 1 Register [15:8]
0x38 - 0x39
0x38
0x39
WF0BM2
0x0000
Wakeup Frame 0 Byte Mask 2 Register [7:0]
Wakeup Frame 0 Byte Mask 2 Register [15:8]
0x3A - 0x3B
0x3A
0x3B
WF0BM3
0x0000
Wakeup Frame 0 Byte Mask 3 Register [7:0]
Wakeup Frame 0 Byte Mask 3 Register [15:8]
0x3C - 0x3D
0x3C
0x3D
0x3E
0x3F
Reserved
Do Not Care
None
0x3E - 0x3F
0x40 - 0x41
0x40
0x41
WF1CRC0
0x0000
Wakeup Frame 1 CRC0 Register [7:0]
Wakeup Frame 1 CRC0 Register [15:8]
0x42 - 0x43
0x42
0x43
WF1CRC1
0x0000
Wakeup Frame 1 CRC1 Register [7:0]
Wakeup Frame 1 CRC1 Register [15:8]
0x44 - 0x45
0x44
0x45
WF1BM0
0x0000
Wakeup Frame 1 Byte Mask 0 Register [7:0]
Wakeup Frame 1 Byte Mask 0 Register [15:8]
0x46 - 0x47
0x46
0x47
WF1BM1
0x0000
Wakeup Frame 1 Byte Mask 1 Register [7:0]
Wakeup Frame 1 Byte Mask 1 Register [15:8]
0x48 - 0x49
0x48
0x49
WF1BM2
0x0000
Wakeup Frame 1 Byte Mask 2 Register [7:0]
Wakeup Frame 1 Byte Mask 2 Register [15:8]
0x4A - 0x4B
0x4A
0x4B
WF1BM3
0x0000
Wakeup Frame 1 Byte Mask 3 Register [7:0]
Wakeup Frame 1 Byte Mask 3 Register [15:8]
0x4C - 0x4D
0x4C
0x4D
Reserved
Do Not Care
None
0x4E - 0x4F
0x4E
0x4F
Reserved
Do Not Care
None
0x50 - 0x51
0x50
0x51
WF2CRC0
0x0000
Wakeup Frame 2 CRC0 Register [7:0]
Wakeup Frame 2 CRC0 Register [15:8]
DS00002357B-page 34
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
TABLE 4-1:
INTERNAL I/O REGISTERS SPACE MAPPING (CONTINUED)
I/O Register Offset Location
Register Name Default Value
Description
16-Bit
8-Bit
0x52 - 0x53
0x52
0x53
WF2CRC1
0x0000
Wakeup Frame 2 CRC1 Register [7:0]
Wakeup Frame 2 CRC1 Register [15:8]
0x54 - 0x55
0x54
0x55
WF2BM0
0x0000
Wakeup Frame 2 Byte Mask 0 Register [7:0]
Wakeup Frame 2 Byte Mask 0 Register [15:8]
0x56 - 0x57
0x56
0x57
WF2BM1
0x0000
Wakeup Frame 2 Byte Mask 1 Register [7:0]
Wakeup Frame 2 Byte Mask 1 Register [15:8]
0x58 - 0x59
0x58
0x59
WF2BM2
0x0000
Wakeup Frame 2 Byte Mask 2 Register [7:0]
Wakeup Frame 2 Byte Mask 2 Register [15:8]
0x5A - 0x5B
0x5A
0x5B
WF2BM3
0x0000
Wakeup Frame 2 Byte Mask 3 Register [7:0]
Wakeup Frame 2 Byte Mask 3 Register [15:8]
0x5C - 0x5D
0x5C
0x5D
Reserved
Do Not Care
None
0x5E - 0x5F
0x5E
0x5F
0x60 - 0x61
0x60
0x61
WF3CRC0
0x0000
Wakeup Frame 3 CRC0 Register [7:0]
Wakeup Frame 3 CRC0 Register [15:8]
0x62 - 0x63
0x62
0x63
WF3CRC1
0x0000
Wakeup Frame 3 CRC1 Register [7:0]
Wakeup Frame 3 CRC1 Register [15:8]
0x64 - 0x65
0x64
0x65
WF3BM0
0x0000
Wakeup Frame 3 Byte Mask 0 Register [7:0]
Wakeup Frame 3 Byte Mask 0 Register [15:8]
0x66 - 0x67
0x66
0x57
WF3BM1
0x0000
Wakeup Frame 3 Byte Mask 1 Register [7:0]
Wakeup Frame 3 Byte Mask 1 Register [15:8]
0x68 - 0x69
0x68
0x69
WF3BM2
0x0000
Wakeup Frame 3 Byte Mask 2 Register [7:0]
Wakeup Frame 3 Byte Mask 2 Register [15:8]
0x6A - 0x6B
0x6A
0x6B
WF3BM3
0x0000
Wakeup Frame 3 Byte Mask 3 Register [7:0]
Wakeup Frame 3 Byte Mask 3 Register [15:8]
0x6C - 0x6D
0x6C
0x6D
0x6E
0x6F
Reserved
Do Not Care
None
0x6E - 0x6F
0x70 - 0x71
0x70
0x71
TXCR
0x0000
Transmit Control Register [7:0]
Transmit Control Register [15:8]
0x72 - 0x73
0x72
0x73
TXSR
0x0000
Transmit Status Register [7:0]
Transmit Status Register [15:8]
0x74 - 0x75
0x74
0x75
RXCR1
0x0800
Receive Control Register 1 [7:0]
Receive Control Register 1 [15:8]
0x76 - 0x77
0x76
0x77
RXCR2
0x0004
Receive Control Register 2 [7:0]
Receive Control Register 2 [15:8]
0x78 - 0x79
0x78
0x79
TXMIR
0x0000
TXQ Memory Information Register [7:0]
TXQ Memory Information Register [15:8]
0x7A - 0x7B
0x7A
0x7B
Reserved
Do Not Care
None
0x7C - 0x7D
0x7C
0x7D
RXFHSR
0x0000
Receive Frame Header Status Register [7:0]
Receive Frame Header Status Register [15:8]
0x7E - 0x7F
0x7E
0x7F
RXFHBCR
0x0000
Receive Frame Header Byte Count Register [7:0]
Receive Frame Header Byte Count Register [15:8]
0x80 - 0x81
0x80
0x81
TXQCR
0x0000
TXQ Command Register [7:0]
TXQ Command Register [15:8]
2018 Microchip Technology Inc.
DS00002357B-page 35
KSZ8851-16MLL/MLLI/MLLU
TABLE 4-1:
INTERNAL I/O REGISTERS SPACE MAPPING (CONTINUED)
I/O Register Offset Location
Register Name Default Value
Description
16-Bit
8-Bit
0x82 - 0x83
0x82
0x83
RXQCR
0x0000
RXQ Command Register [7:0]
RXQ Command Register [15:8
0x84 - 0x85
0x84
0x85
TXFDPR
0x0000
TX Frame Data Pointer Register [7:0]
TX Frame Data Pointer Register [15:8]
0x86 - 0x87
0x86
0x87
RXFDPR
0x0000
RX Frame Data Pointer Register [7:0]
RX Frame Data Pointer Register [15:8]
0x88 - 0x89
0x88
0x89
0x8A
0x8B
Reserved
Do Not Care
None
0x8A - 0x8B
0x8C - 0x8D
0x8C
0x8D
RXDTTR
0x0000
RX Duration Timer Threshold Register [7:0]
RX Duration Timer Threshold Register [15:8]
0x8E - 0x8F
0x8E
0x8F
RXDBCTR
0x0000
RX Data Byte Count Threshold Register [7:0]
RX Data Byte Count Threshold Register [15:8]
0x90 - 0x91
0x90
0x91
IER
0x0000
Interrupt Enable Register [7:0]
Interrupt Enable Register [15:8]
0x92 - 0x93
0x92
0x93
ISR
0x0300
Interrupt Status Register [7:0]
Interrupt Status Register [15:8]
0x94 - 0x95
0x94
0x95
0x96
0x97
Reserved
Do Not Care
None
0x96 - 0x97
0x98 - 0x99
0x98
0x99
0x9A
0x9B
Reserved
Do Not Care
None
0x9A - 0x9B
0x9C - 0x9D
0x9C
0x9D
RXFCTR
0x0000
RX Frame Count & Threshold Register [7:0]
RX Frame Count & Threshold Register [15:8]
0x9E - 0x9F
0x9E
0x9F
TXNTFSR
0x0000
TX Next Total Frames Size Register [7:0]
TX Next Total Frames Size Register [15:8]
0xA0 - 0xA1
0xA0
0xA1
MAHTR0
0x0000
MAC Address Hash Table Register 0 [7:0]
MAC Address Hash Table Register 0 [15:8]
0xA2 - 0xA3
0xA2
0xA3
MAHTR1
0x0000
MAC Address Hash Table Register 1 [7:0]
MAC Address Hash Table Register 1 [15:8]
0xA4 - 0xA5
0xA4
0xA5
MAHTR2
0x0000
MAC Address Hash Table Register 2 [7:0]
MAC Address Hash Table Register 2 [15:8]
0xA6 - 0xA7
0xA6
0xA7
MAHTR3
0x0000
MAC Address Hash Table Register 3 [7:0]
MAC Address Hash Table Register 3 [15:8]
0xA8 - 0xA9
0xA8
0xA9
0xAA
0xAB
Reserved
Do Not Care
None
0xAA - 0xAB
0xAC - 0xAD
0xAC
0xAD
0xAE
0xAF
Reserved
Do Not Care
None
0xAE - 0xAF
0xB0 - 0xB1
0xB0
0xB1
FCLWR
0x0500
Flow Control Low Watermark Register [7:0]
Flow Control Low Watermark Register [15:8]
DS00002357B-page 36
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
TABLE 4-1:
INTERNAL I/O REGISTERS SPACE MAPPING (CONTINUED)
I/O Register Offset Location
Register Name Default Value
Description
16-Bit
8-Bit
0xB2 - 0xB3
0xB2
0xB3
FCHWR
0x0300
Flow Control High Watermark Register [7:0]
Flow Control High Watermark Register [15:8]
0xB4 - 0xB5
0xB4
0xB5
FCOWR
0x0040
Flow Control Overrun Watermark Register [7:0]
Flow Control Overrun Watermark Register [15:8]
0xB6 - 0xB7
0xB6
0xB7
Reserved
Do Not Care
None
0xB8 - 0xB9
0xB8
0xB9
0xBA
0xB
Reserved
Do Not Care
None
0xBA - 0xBB
0xBC - 0xBD
0xBC
0xBD
Reserved
Do Not Care
None
0xBE - 0xBF
0xBE
0xBF
0xC0 - 0xC1
0xC0
0xC1
CIDER
0x887x
Chip ID and Enable Register [7:0]
Chip ID and Enable Register [15:8]
0xC2 - 0xC3
0xC2
0xC3
Reserved
Do Not Care
None
0xC4 - 0xC5
0xC4
0xC5
Reserved
Do Not Care
None
0xC6 - 0xC7
0xC6
0xC7
CGCR
0x0835
Chip Global Control Register [7:0]
Chip Global Control Register [15:8]
0xC8 - 0xC9
0xC8
0xC9
IACR
0x0000
Indirect Access Control Register [7:0]
Indirect Access Control Register [15:8]
0xCA - 0xCB
0xCA
0xCB
Reserved
Do Not Care
None
0xCC - 0xCD
0xCC
0xCD
0xCE
0xCF
Reserved
Do Not Care
None
0xCE - 0xCF
0xD0 - 0xD1
0xD0
0xD1
IADLR
0x0000
Indirect Access Data Low Register [7:0]
Indirect Access Data Low Register [15:8]
0xD2 - 0xD3
0xD2
0xD3
IADHR
0x0000
Indirect Access Data High Register [7:0]
Indirect Access Data High Register [15:8]
0xD4 - 0xD5
0xD4
0xD5
PMECR
0x0080
Power Management Event Control Register [7:0]
Power Management Event Control Register [15:8]
0xD6 - 0xD7
0xD6
0xD7
GSWUTR
0X080C
Go-Sleep & Wake-Up Time Register [7:0]
Go-Sleep & Wake-Up Time Register [15:8]
0xD8 - 0xD9
0xD8
0xD9
PHYRR
0x0000
PHY Reset Register [7:0]
PHY Reset Register [15:8]
0xDA - 0xDB
0xDA
0xDB
Reserved
Do Not Care
None
0xDC - 0xDD
0xDC
0xDD
0xDE
0xDF
Reserved
Do Not Care
None
0xDE - 0xDF
2018 Microchip Technology Inc.
DS00002357B-page 37
KSZ8851-16MLL/MLLI/MLLU
TABLE 4-1:
INTERNAL I/O REGISTERS SPACE MAPPING (CONTINUED)
I/O Register Offset Location
Register Name Default Value
16-Bit
8-Bit
0xDC - 0xE1
0xE0
0xE1
0xDE - 0xE3
0xE2
0xE3
0xE4 - 0xE5
Description
Reserved
Do Not Care
None
0xE4
0xE5
P1MBCR
0x3120
PHY 1 MII-Register Basic Control Register [7:0]
PHY 1 MII-Register Basic Control Register [15:8]
0xE6 - 0xE7
0xE6
0xE7
P1MBSR
0x7808
PHY 1 MII-Register Basic Status Register [7:0]
PHY 1 MII-Register Basic Status Register [15:8]
0xE8 - 0xE9
0xE8
0xE9
PHY1ILR
0x1430
PHY 1 PHY ID Low Register [7:0]
PHY 1 PHY ID Low Register [15:8]
0xEA - 0xEB
0xEA
0xEB
PHY1IHR
0x0022
PHY 1 PHY ID High Register [7:0]
PHY 1 PHY ID High Register [15:8]
0xEC - 0xED
0xEC
0xED
0xEE - 0xEF
0xEE
0xEF
0xF0 - 0xF1
0xF0
0xF1
0xF2 - 0xF3
0xF2
0xF3
0xF4 - 0xF5
P1ANAR
0x05E1
PHY 1 Auto-Negotiation Advertisement Register
[7:0]
PHY 1 Auto-Negotiation Advertisement Register
[15:8]
PHY 1 Auto-Negotiation Link Partner Ability Register [7:0]
P1ANLPR
0x0001
Reserved
Do Not Care
None
0xF4
0xF5
P1SCLMD
0x0000
Port 1 PHY Special Control/Status, LinkMD® [7:0]
Port 1 PHY Special Control/Status, LinkMD® [15:8]
0xF6 - 0xF7
0xF6
0xF7
P1CR
0x00FF
Port 1 Control Register [7:0]
Port 1 Control Register [15:8]
0xF8 - 0xF9
0xF8
0xF9
P1SR
0x8080
Port 1 Status Register [7:0]
Port 1 Status Register [15:8]
0xFA - 0xFB
0xFA
0xFB
Reserved
Do Not Care
None
0xFC - 0xFD
0xFC
0xFD
0xFE
0xFF
Reserved
Do Not Care
None
0xFE - 0xFF
DS00002357B-page 38
PHY 1 Auto-Negotiation Link Partner Ability Register [15:8]
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.1
Register Nomenclature
Table 4-2 describes the register bit attribute notation used throughout this document.
TABLE 4-2:
REGISTER BIT TYPES
Register Bit Type Notation
Register Bit Description
RO
Read only.
WO
Write only.
R/W
Read/Write.
W1C
Write 1 to clear (writing a “1” to clear this bit).
Many of these register bit notations can be combined. Some examples of this are shown below:
• R/W: Can be written. Will return current setting on a read.
• R/WAC: Will return current setting on a read. Writing anything clears the bit.
4.2
Control and Status Registers
0x00 – 0x07: Reserved.
4.2.1
CHIP CONFIGURATION REGISTER (0X08 – 0X09): CCR
This register indicates the chip configuration mode based on strapping and bonding options.
Bits
Type
Default
Reserved.
RO
—
10
Bus Endian mode
The EESK (pin 10) value is latched into this bit during power-up/reset.
0: Bus in Big Endian mode, 1: Bus in Little Endian mode.
RO
—
9
EEPROM presence
The EED_IO (pin 9) value is latched into this bit during power-up/reset.
0: No external EEPROM, 1: Use external EEPROM.
RO
—
8
Reserved.
RO
0
7
8-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 8-bit bus mode operation, 1: In 8-bit bus mode operation.
RO
—
6
16-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 16-bit bus mode operation, 1: In 16-bit bus mode operation.
RO
—
5
Reserved.
RO
0
4
Shared data bus mode for data and address
0: Data and address bus are separated.
1: Data and address bus are shared.
RO
—
3
Reserved.
RO
0
2
Reserved.
RO
0
1
48-Pin Chip Package
To indicate chip package is 48-pin.
0: No, 1: Yes.
RO
—
0
Reserved.
RO
0
15-11
Description
0x00 – 0x07: Reserved.
2018 Microchip Technology Inc.
DS00002357B-page 39
KSZ8851-16MLL/MLLI/MLLU
4.2.2
HOST MAC ADDRESS REGISTERS: MARL, MARM, AND MARH
These Host MAC address registers are loaded starting at word location 0x1 of the EEPROM upon hardware reset. The
software driver can read or write these registers value, but it will not modify the original Host MAC address value in the
EEPROM. These six bytes of Host MAC address in external EEPROM are loaded to these three registers as mapping
below:
MARL[15:0] = EEPROM 0x1(MAC Byte 2 and 1)
MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3)
MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5)
The Host MAC address is used to define the individual destination address that the KSZ8851-16MLL responds to when
receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are
received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the
actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.
These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below:
MARL[15:0] = 0x89AB
MARM[15:0] = 0x4567
MARH[15:0] = 0x0123
4.2.3
HOST MAC ADDRESS REGISTER LOW (0X10 – 0X11): MARL
The following table shows the register bit fields for Low word of Host MAC address.
Bit
15-0
4.2.4
Description
MARL MAC Address Low
The least significant word of the MAC address.
Type
Default
R/W
—
HOST MAC ADDRESS REGISTER MIDDLE (0X12 – 0X13): MARM
The following table shows the register bit fields for Middle word of Host MAC address.
Bits
15-0
4.2.5
Description
MARM MAC Address Middle
The middle word of the MAC address.
Type
Default
R/W
—
HOST MAC ADDRESS REGISTER HIGH (0X14 – 0X15): MARH
The following table shows the register bit fields for High word of Host MAC address.
Bits
15-0
Description
MARM MAC Address High
The most significant word of the MAC address.
Type
Default
R/W
—
0x16 – 0x1F: Reserved.
DS00002357B-page 40
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.6
ON-CHIP BUS CONTROL REGISTER (0X20 – 0X21): OBCR
This register controls the on-chip bus clock speed for the KSZ8851-16MLL. The default of the on-chip bus clock speed
is 125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the
best performance.
Bits
15-7
6
5-3
2
1-0
4.2.7
Description
Type
Default
Reserved.
R/W
—
Output Pin Drive Strength
Bi-directional or output pad drive strength selection.
0: 8 mA; 1: 16 mA
R/W
0
Reserved.
R/W
—
On-Chip Bus Clock Selection
0: 125 MHz (default setting is divided by 1, Bit[1:0]=00)
1: NA (reserved)
R/W
0
On-Chip Bus Clock Divider Selection
00: Divided by 1; 01: Divided by 2; 10: Divided by 3; 11: NA (reserved).
For example to control the bus clock speed as below:
If Bit 2 = 0 and this value is set 00 to select 125 MHz.
If Bit 2 = 0 and this value is set 01 to select 62.5 MHz.
R/W
0x0
EEPROM CONTROL REGISTER (0X22 – 0X23): EEPCR
To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external
EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design, the chip host
MAC address is loaded from the EEPROM immediately after reset. The KSZ8851-16MLL allows the software to access
(read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the
EEPROM Software Access bit is set.
Bits
Type
Default
Reserved.
RO
—
5
EESRWA EEPROM Software Read or Write Access
0: software read enable to access EEPROM when software access enabled
(bit4=1)
1: software write enable to access EEPROM when software access enabled
(bit4=1).
WO
0
4
EESRWA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
R/W
0
3
EESB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EED_IO pin.
RO
—
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s
EED_IO pin.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS
pin.
R/W
0x0
15-6
2-0
Description
2018 Microchip Technology Inc.
DS00002357B-page 41
KSZ8851-16MLL/MLLI/MLLU
4.2.8
MEMORY BIST INFO REGISTER (0X24 – 0X25): MBIR
This register indicates the built-in self-test result for both TX and RX memories after power-up/reset.
Bits
Type
Default
RESERVED
RO
0x0
12
TXMBF TX Memory BIST Test Finish
When set, it indicates the Memory Built-In Self Test completion for the TX
Memory.
RO
—
11
TXMBFA TX Memory BIST Test Fail
When set, it indicates the TX Memory Built In Self Test has failed.
RO
—
10-8
TXMBFC TX Memory BIST Test Fail Count
To indicate the TX Memory Built In Self Test failed count
RO
—
7-5
Reserved.
RO
—
4
RXMBF RX Memory BIST Finish
When set, it indicates the Memory Built In Self Test completion for the RX
Memory.
RO
—
3
RXMBFA RX Memory BIST Fail
When set, it indicates the RX Memory Built In Self Test has failed.
RO
—
RXMBFC RX Memory BIST Test Fail Count
To indicate the RX Memory Built In Self Test failed count.
RO
—
15:13
2-0
4.2.9
Description
GLOBAL RESET REGISTER (0X26 – 0X27): GRR
This register controls the global and QMU reset functions with information programmed by the CPU.
Bits
Type
Default
Reserved.
RO
0x0000
1
QMU Module Soft Reset
1: Software reset is active to clear both TXQ and RXQ memories.
0: Software reset is inactive.
QMU software reset will flush out all TX/RX packet data inside the TXQ and
RXQ memories and reset all QMU registers to default value.
R/W
0
0
Global Soft Reset
1: Software reset is active.
0: Software reset is inactive.
Global software reset will affect PHY, MAC, QMU, DMA, and the switch core,
all registers value are set to default value.
R/W
0
15-2
Description
0x28 – 0x29: Reserved
4.2.10
WAKEUP FRAME CONTROL REGISTER (0X2A – 0X2B): WFCR
This register holds control information programmed by the CPU to control the wakeup frame function.
Bits
15-8
7
6-4
Description
Type
Default
Reserved.
RO
0x00
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
R/W
0
Reserved.
RO
0x0
DS00002357B-page 42
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Bits
Type
Default
3
WF3E
Wakeup Frame 3 Enable
When set, it enables the wakeup frame 3 pattern detection.
When reset, the wakeup frame 3 pattern detection is disabled.
Description
R/W
0
2
WF2E
Wakeup Frame 2 Enable
When set, it enables the wakeup frame 2 pattern detection.
When reset, the wakeup frame 2 pattern detection is disabled.
R/W
0
1
WF1E
Wakeup Frame 1 Enable
When set, it enables the wakeup frame 1 pattern detection.
When reset, the wakeup frame 1 pattern detection is disabled.
R/W
0
0
WF0E
Wakeup Frame 0 Enable
When set, it enables the wakeup frame 0 pattern detection.
When reset, the wakeup frame 0 pattern detection is disabled.
R/W
0
0x2C – 0x2F: Reserved
4.2.11
WAKEUP FRAME 0 CRC0 REGISTER (0X30 – 0X31): WF0CRC0
This register contains the expected CRC values of the wakeup frame 0 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wakeup byte mask registers.
Bits
15-0
4.2.12
Description
WF0CRC0
Wakeup Frame 0 CRC (lower 16 bits)
The expected CRC value of a wakeup frame 0 pattern.
R/W
Default
R/W
0x0000
WAKEUP FRAME 0 CRC1 REGISTER (0X32 – 0X33): WF0CRC1
This register contains the expected CRC values of the wakeup frame 0 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wakeup byte mask registers.
Bits
15-0
4.2.13
Description
WF0CRC1
Wakeup Frame 0 CRC (lower 16 bits)
The expected CRC value of a wakeup frame 0 pattern.
R/W
Default
R/W
0x0000
WAKEUP FRAME 0 BYTE MASK 0 REGISTER (0X34 – 0X35): WF0BM0
This register contains the first 16 bytes mask values of the wakeup frame 0 pattern. Setting bit 0 selects the first byte of
the wakeup frame 0, setting bit 15 selects the 16th byte of the wakeup frame 0.
Bits
15-0
Description
WF0BM0
Wakeup Frame 0 Byte Mask 0
The first 16 bytes mask of a wakeup frame 0 pattern.
2018 Microchip Technology Inc.
R/W
Default
R/W
0x0000
DS00002357B-page 43
KSZ8851-16MLL/MLLI/MLLU
4.2.14
WAKEUP FRAME 0 BYTE MASK 1 REGISTER (0X36 – 0X37): WF0BM1
This register contains the first 16 bytes mask values of the wakeup frame 0 pattern. Setting bit 0 selects the 17th byte
of the wakeup frame 0, setting bit 15 selects the 32nd byte of the wakeup frame 0.
Bits
Description
R/W
Default
15-0
WF0BM1
Wakeup Frame 0 Byte Mask 1
The next 16 bytes mask covering bytes 17 to 32 of a wakeup frame 0 pattern.
R/W
0x0000
4.2.15
WAKEUP FRAME 0 BYTE MASK 2 REGISTER (0X38 – 0X39): WF0BM2
This register contains the next 16 bytes mask values of the wakeup frame 0 pattern. Setting bit 0 selects the 33rd byte
of the wakeup frame 0. Setting bit 15 selects the 48th byte of the wakeup frame 0.
Bits
Description
R/W
Default
15-0
WF0BM2
Wakeup Frame 0 Byte Mask 2
The next 16 bytes mask covering bytes 33 to 48 of a wakeup frame 0 pattern.
R/W
0x0000
4.2.16
WAKEUP FRAME 0 BYTE MASK 3 REGISTER (0X3A – 0X3B): WF0BM3
This register contains the last 16 bytes mask values of the wakeup frame 0 pattern. Setting bit 0 selects the 49th byte
of the wakeup frame 0. Setting bit 15 selects the 64th byte of the wakeup frame 0.
Bits
Description
R/W
Default
15-0
WF0BM3
Wakeup Frame 0 Byte Mask 3
The next 16 bytes mask covering bytes 49 to 64 of a wakeup frame 0 pattern.
R/W
0x0000
0x3C – 0x3F: Reserved
4.2.17
WAKEUP FRAME 1 CRC0 REGISTER (0X40 – 0X41): WF1CRC0
This register contains the expected CRC values of the wakeup frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wakeup byte mask registers.
Bits
15-0
4.2.18
Description
WF1CRC0
Wakeup frame 1 CRC (lower 16 bits).
The expected CRC value of a wakeup frame 1 pattern.
R/W
Default
RW
0x0000
WAKEUP FRAME 1 CRC1 REGISTER (0X42 – 0X43): WF1CRC1
This register contains the expected CRC values of the wakeup frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wakeup byte mask registers.
Bits
15-0
Description
WF1CRC1
Wakeup frame 1 CRC (upper 16 bits).
The expected CRC value of a wakeup frame 1 pattern.
DS00002357B-page 44
R/W
Default
RW
0x0000
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.19
WAKEUP FRAME 1 BYTE MASK 0 REGISTER (0X44 – 0X45): WF1BM0
This register contains the first 16 bytes mask values of the wakeup frame 1 pattern. Setting bit 0 selects the first byte of
the wakeup frame 1, setting bit 15 selects the 16th byte of the wakeup frame 1.
Bits
Description
WF1BM0
Wakeup frame 1 Byte Mask 0.
The first 16 bytes mask of a wakeup frame 1 pattern.
15-0
4.2.20
R/W
Default
RW
0x0000
WAKEUP FRAME 1 BYTE MASK 1 REGISTER (0X46 – 0X47): WF1BM1
This register contains the next 16 bytes mask values of the wakeup frame 1 pattern. Setting bit 0 selects the 17th byte
of the wakeup frame 1. Setting bit 15 selects the 32nd byte of the wakeup frame 1.
Bits
Description
WF1BM1
Wakeup frame 1 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a wakeup frame 1
pattern.
15-0
4.2.21
R/W
Default
RW
0x0000
WAKEUP FRAME 1 BYTE MASK 2 REGISTER (0X48 – 0X49): WF1BM2
This register contains the next 16 bytes mask values of the wakeup frame 1 pattern. Setting bit 0 selects the 33rd byte
of the wakeup frame 1. Setting bit 15 selects the 48th byte of the wakeup frame 1.
Bits
Description
WF1BM2
Wakeup frame 1 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 32 of a wakeup frame 1
pattern.
15-0
4.2.22
R/W
Default
RW
0x0000
WAKEUP FRAME 1 BYTE MASK 3 REGISTER (0X4A – 0X4B): WF1BM3
This register contains the next 16 bytes mask values of the wakeup frame 1 pattern. Setting bit 0 selects the 49th byte
of the wakeup frame 1. Setting bit 15 selects the 64th byte of the wakeup frame 1.
Bits
Description
WF1BM3
Wakeup frame 1 Byte Mask 3.
The next 16 bytes mask covering bytes 49 to 64 of a wakeup frame 1
pattern.
15-0
R/W
Default
RW
0x0000
0x4C – 0x4F: Reserved
4.2.23
WAKEUP FRAME 2 CRC0 REGISTER (0X50 – 0X51): WF2CRC0
This register contains the expected CRC values of the wakeup frame 2 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wakeup byte mask registers.
Bits
15-0
Description
WF2CRC0
Wakeup frame 2 CRC (lower 16 bits). The expected CRC value of a
wakeup frame 2 pattern
2018 Microchip Technology Inc.
R/W
Default
R/W
0x0000
DS00002357B-page 45
KSZ8851-16MLL/MLLI/MLLU
4.2.24
WAKEUP FRAME 2 CRC1 REGISTER (0X52 – 0X53): WF2CRC1
This register contains the expected CRC values of the wakeup frame 2 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wakeup byte mask registers.
Bits
15-0
4.2.25
Description
WF2CRC1
Wakeup frame 2 CRC (upper 16 bits). The expected CRC value of a
wakeup frame 2 pattern.
R/W
Default
R/W
0x0000
WAKEUP FRAME 2 BYTE MASK 0 REGISTER (0X54 – 0X55): WF2BM0
This register contains the first 16 bytes mask values of the wakeup frame 2 pattern. Setting bit 0 selects the first byte of
the wakeup frame 2, setting bit 15 selects the 16th byte of the wakeup frame 2.
Bits
15-0
4.2.26
Description
WF2BM0
Wakeup frame 2 Byte Mask 0. The first 16 bytes of a wakeup frame 2
pattern.
R/W
Default
R/W
0x0000
WAKEUP FRAME 2 BYTE MASK 1 REGISTER (0X56 – 0X57): WF2BM1
This register contains the next 16 bytes mask values of the wakeup frame 2 pattern. Setting bit 0 selects the 17th byte
of the wakeup frame 2. Setting bit 15 selects the 32nd byte of the wakeup frame 2.
4.2.27
Bits
Description
R/W
Default
15-0
WF2BM1
Wakeup frame 2 Byte Mask 1. The next 16 bytes of a wakeup frame 17
to 32 of a wakeup frame 2 pattern.
R/W
0x0000
WAKEUP FRAME 2 BYTE MASK 2 REGISTER (0X58 – 0X59): WF2BM2
This register contains the next 16 bytes mask values of the wakeup frame 2 pattern. Setting bit 0 selects the 33rd byte
of the wakeup frame 2. Setting bit 15 selects the 48th byte of the wakeup frame 2.
Bits
15-0
4.2.28
Description
R/W
Default
WF2BM2
Wakeup frame 2 Byte Mask 2. The next 16 bytes of a wakeup frame 22
to 48 of a wakeup frame 2 pattern.
R/W
0
WAKEUP FRAME 2 BYTE MASK 1 REGISTER (0X5A – 0X5B): WF2BM3
This register contains the next 16 bytes mask values of the wakeup frame 2 pattern. Setting bit 0 selects the 49th byte
of the wakeup frame 2. Setting bit 15 selects the 64th byte of the wakeup frame 2.
Bits
Description
R/W
Default
15-0
WF2BM3
Wakeup frame 2 Byte Mask 3. The first 16 bytes of a wakeup frame 49
to 64 of a wakeup frame 2 pattern.
R/W
0
0x5C – 0x5F: Reserved
DS00002357B-page 46
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.29
WAKEUP FRAME 3 CRC0 REGISTER (0X60 – 0X61): WF3CRC0
This register contains the expected CRC values of the wakeup frame 3 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wakeup byte mask registers.
Bits
15-0
4.2.30
Description
WF3CRC0
Wakeup frame 3 CRC (lower 16 bits). The expected CRC value of a
wakeup frame 3 pattern.
R/W
Default
R/W
0
WAKEUP FRAME 3 CRC1 REGISTER (0X62 – 0X63): WF3CRC1
This register contains the expected CRC values of the wakeup frame 3 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wakeup byte mask registers.
Bits
15-0
4.2.31
Description
WF3FBM0
Wakeup Frame 3 Byte Mask 0. The first 16 byte mask of a wakeup
frame 3 pattern
R/W
Default
R/W
0
WAKEUP FRAME 3 BYTE MASK 0 REGISTER (0X64 – 0X65): WF3BM0
This register contains the first 16 bytes mask values of the wakeup frame 3 pattern. Setting bit 0 selects the first byte of
the wakeup frame 3, setting bit 15 selects the 16th byte of the wakeup frame 3.
Bits
15-0
4.2.32
Description
WF3BM0
Wakeup Frame 3 Byte Mask 0. The first 16 byte mask of a wakeup
frame 3 pattern.
R/W
Default
R/W
0
WAKEUP FRAME 3 BYTE MASK 1 REGISTER (0X66 – 0X67): WF3BM1
This register contains the next 16 bytes mask values of the wakeup frame 3 pattern. Setting bit 0 selects the 17th byte
of the wakeup frame 3. Setting bit 15 selects the 32nd byte of the wakeup frame 3.
4.2.33
Bits
Description
R/W
Default
15-0
WF3BM1
Wakeup Frame 3 Byte Mask 1. The next 16 bytes mask covering bytes
17 to 32 of a wakeup frame 3 pattern.
R/W
0
WAKEUP FRAME 3 BYTE MASK 2 REGISTER (0X68 – 0X69): WF3BM2
This register contains the next 16 bytes mask values of the wakeup frame 3 pattern. Setting bit 0 selects the 33rd byte
of the wakeup frame 3. Setting bit 15 selects the 48th byte of the wakeup frame 3.
Bits
Description
R/W
Default
15-0
WF3BM2
Wakeup Frame 3 Byte Mask 2. The next 16 bytes mask covering bytes
33 to 48 of a wakeup frame 3 pattern.
R/W
0
2018 Microchip Technology Inc.
DS00002357B-page 47
KSZ8851-16MLL/MLLI/MLLU
4.2.34
WAKEUP FRAME 3 BYTE MASK 3 REGISTER (0X6A – 0X6B): WF3BM3
This register contains the next 16 bytes mask values of the wakeup frame 3 pattern. Setting bit 0 selects the 49th byte
of the wakeup frame 3. Setting bit 15 selects the 64th byte of the wakeup frame 3.
Bits
Description
R/W
Default
15-0
WF3BM3
Wakeup Frame 3 Byte Mask 3. The next 16 bytes mask covering bytes
49 to 64 of a wakeup frame 3 pattern.
R/W
0
0x6C – 0x6F: Reserved
4.2.35
TRANSMIT CONTROL REGISTER (0X70 – 0X71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bits
15-9
Description
R/W
Default
Reserved.
RO
-
8
TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851-16MLL is enabled to transmit ICMP
frame (only for non-fragment frame) checksum generation.
R/W
0x0
7
TCGUDP Transmit Checksum Generation for UDP
When this bit is set, The KSZ8851-16MLL is enabled to transmit UDP
frame checksum generation.
R/W
0x0
6
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851-16MLL is enabled to transmit TCP
frame checksum generation.
R/W
0x0
5
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851-16MLL is enabled to transmit IP
header checksum generation.
R/W
0x0
4
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX
frame pointer is reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit,
then clear this bit to normal operation.
R/W
0x0
3
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851-16MLL is in full-duplex mode,
flow control is enabled. The KSZ8851-16MLL transmits a PAUSE frame
when the Receive Buffer capacity reaches a threshold level that will
cause the buffer to overflow.
When this bit is set and the KSZ8851-16MLL is in half-duplex mode,
back-pressure flow control is enabled. When this bit is cleared, no
transmit flow control is enabled.
R/W
0x0
2
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851-16MLL automatically adds a padding
field to a packet shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to
avoid CRC errors for the transmit packet.
R/W
0x0
1
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851-16MLL automatically adds a 32-bit
CRC checksum field to the end of a transmit frame.
R/W
0x0
0
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a
running state. When reset, the transmit process is placed in the
stopped state after the transmission of the current frame is completed.
R/W
0x0
DS00002357B-page 48
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.36
TRANSMIT STATUS REGISTER (0X72 – 0X73): TXSR
This register keeps the status of the last transmitted frame.
Bits
R/W
Default
Reserved
RO
0x0
13
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
RO
0x0
12
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
RO
0x0
11 - 6
Reserved
RO
-
5-0
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status
information in this register belongs to the frame with this ID.
RO
-
R/W
Default
15
FRXQ Flush Receive Queue
When this bit is set, The receive queue memory is cleared and RX
frame pointer is reset.
Note: Disable the RXE receive enable bit[0] first before set this bit,
then clear this bit to normal operation.
R/W
0x0
14
RXUDPFCC Receive UDP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct UDP checksum for incoming UDP frames. Any received UDP frames with incorrect checksum will be discarded.
R/W
0x0
13
RXTCPFCC Receive TCP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct TCP checksum for incoming TCP frames. Any received TCP frames with incorrect checksum will be discarded.
R/W
0x0
12
RXIPFCC Receive IP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct IP header
checksum for incoming IP frames. Any received IP frames with incorrect checksum will be discarded.
R/W
0x0
11
RXPAFMA Receive Physical Address Filtering with MAC Address
Enable
When this bit is set, this bit enables the RX function to receive physical address that pass the MAC address filtering mechanism (see
Address Filtering Scheme in Table 3-3 for detail).
R/W
0x0
10
RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8851-16MLL is in full-duplex mode,
flow control is enabled, and the KSZ8851-16MLL will acknowledge a
PAUSE frame from the receive interface; i.e., the outgoing packets
are pending in the transmit buffer until the PAUSE frame control timer
expires. This field has no meaning in half-duplex mode and should
be programmed to 0.
When this bit is cleared, flow control is not enabled.
R/W
0x0
9
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into
the RX queue.
When this bit is cleared, all CRC error frames are discarded.
R/W
0x0
15 - 14
4.2.37
Description
RECEIVE CONTROL REGISTER 1 (0X74 – 0X75): RXCR1
This register holds control information programmed by the CPU to control the receive function.
Bits
Description
2018 Microchip Technology Inc.
DS00002357B-page 49
KSZ8851-16MLL/MLLI/MLLU
Bits
4.2.38
R/W
Default
8
XRMAFMA Receive Multicast Address Filtering with MAC Address
Enable
When this bit is set, this bit enables the RX function to receive
multicast address that pass the MAC address filtering mechanism
(see Address Filtering Scheme in Table 3-3 for details).
Description
R/W
0x0
7
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast
frames.
R/W
0x0
6
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames
(including broadcast frames).
R/W
0x0
5
RXUE Receive Unicast Enable
When this bit is set, the RX module receives unicast frames that
match the 48-bit Station MAC address of the module.
R/W
0x0
4
RXAE Receive All Enable
When this bit is set, the KSZ8851-16MLL receives all incoming
frames, regardless of the frame’s destination address (see Address
Filtering Scheme in Table 3-3 for details).
R/W
0x0
3
Reserved
R/W
0x0
2
Reserved
R/W
0x0
1
RXINVF Receive Inverse Filtering
When this bit is set, the KSZ8851-16MLL receives function with
address check operation in inverse filtering mode (see Address
Filtering Scheme in Table 3-3 for details).
R/W
0x0
0
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running
state.
When this bit is cleared, the receive process is placed in the stopped
state upon completing reception of the current frame.
R/W
0x0
RECEIVE CONTROL REGISTER 2 (0X76 – 0X77): RXCR2
This register holds control information programmed by the CPU to control the receive function.
Bits
15-5
4
3
DS00002357B-page 50
Description
R/W
Default
Reserved
RO
—
IUFFP IPV4/IPV6/UDP Fragment Frame Pass
When this bit is set, the KSZ8851-16MLL will pass the checksum
check at receive side for IPv4/IPv6 UDP frame with fragment extension header.
When this bit is cleared, the KSZ8851-16MLL will perform checksum
operation based on configuration and doesn’t care whether it’s a
fragment frame or not.
R/W
0x0
RXIUFCEZ Receive IPV4/IPV6/UDP Frame Checksum Equal Zero
When this bit is set, the KSZ8851-16MLL will pass the filtering for
IPv4/IPv6 UDP frame with UDP checksum equal to zero.
When this bit is cleared, the KSZ8851-16MLL will drop IPv4/IPv6
UDP packet with UDP checksum equal to zero.
R/W
0x0
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.39
Bits
Description
R/W
Default
2
UDPLFE UDP Lite Frame Enable
When this bit is set, the KSZ8851-16MLL will check the checksum at
receive side and generate the checksum at transmit side for UDP
Lite frame.
When this bit is cleared, the KSZ8851-16MLL will pass the checksum
check at receive side and skip the checksum generation at transmit
side for UDP Lite frame.
R/W
0x0
1
RXICMPFCC Receive ICMP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct ICMP checksum for incoming ICMP frames (only for non-fragment frame). Any
received ICMP frames with incorrect checksum will be discarded.
R/W
0x0
0
RXSAF Receive Source Address Filtering
When this bit is set, the KSZ8851-16MLL will drop the frame if the
source address is same as MAC address in MARL, MARM, MARH
registers.
R/W
0x0
R/W
Default
TXQ MEMORY INFORMATION REGISTER (0X78 – 0X79): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bits
Description
15-13
Reserved.
RO
—
12-0
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The
TXQ memory is used for both frame payload, control word.
Note: Software must be written to ensure that there is enough memory for the next transmit frame including control information before
transmit data is written to the TXQ.
RO
—
0X7A – 0x7B: Reserved
4.2.40
RECEIVE FRAME HEADER STATUS REGISTER (0X7C – 0X7D): RXFHSR
This register indicates the received frame header status information, the received frames are reported in RXFCTR register. This register contains the status information for the frame received and the CPU can read so many times same as
the frame count value in the RXFCTR.
Bits
Description
R/W
Default
15
RXFV Receive Frame Valid
When this bit is set, it indicates that the present frame in the receive
packet memory is valid. The status information currently in this location is also valid.
When clear, it indicates that there is either no pending receive frame
or that the current frame is still in the process of receiving.
RO
—
14
Reserved
RO
—
13
RXICMPFCS Receive ICMP Frame Checksum Status
When this bit is set, the KSZ8851 received ICMP frame checksum
field is incorrect.
RO
—
12
RXIPFCS Receive IP Frame Checksum Status
When this bit is set, the KSZ8851 received IP header checksum field
is incorrect.
RO
—
2018 Microchip Technology Inc.
DS00002357B-page 51
KSZ8851-16MLL/MLLI/MLLU
Bits
R/W
Default
11
RXTCPFCS Receive TCP Frame Checksum Status
When this bit is set, the KSZ8851 received TCP frame checksum
field is incorrect.
RO
—
10
RXUDPFCS Receive UDP Frame Checksum Status
When this bit is set, the KSZ8851 received UDP frame checksum
field is incorrect.
RO
—
9-8
4.2.41
Description
Reserved.
RO
—
7
RXBF Receive Broadcast Frame
When this bit is set, it indicates that this frame has a broadcast
address.
RO
—
6
RXMF Receive Multicast Frame
When this bit is set, it indicates that this frame has a multicast
address (including the broadcast address).
RO
—
5
RXUF Receive Unicast Frame
When this bit is set, it indicates that this frame has a unicast address.
RO
—
4
RXMR Receive MII Error
When set, it indicates that there is an MII symbol error on the
received frame.
RO
—
3
RXFT Receive Frame Type
When this bit is set, it indicates that the frame is an Ethernet-type
frame (frame length is greater than 1500 bytes). When clear, it indicates that the frame is an IEEE 802.3 frame. This bit is not valid for
runt frame.
RO
—
2
RXFTL Receive Frame Too Long
When this bit is set, it indicates that the frame length exceeds the
maximum size of 2000 bytes. Frames that are too long are passed to
the host only if the pass bad frame bit is set.
Note: Frame too long is only a frame length indication and does not
cause any frame truncation.
RO
—
1
RXRF Receive Runt Frame
When this bit is set, it indicates that a frame was damaged by a collision or had a premature termination before the collision window
passed.
Runt frames are passed to the host only if the pass bad frame bit is
set.
RO
—
0
RXCE Receive CRC Error
When this bit is set, it indicates that a CRC error has occurred on the
current received frame.
CRC error frames are passed to the host only if the pass bad frame
bit is set.
RO
—
RECEIVE FRAME HEADER BYTE COUNT REGISTER (0X7E – 0X7F): RXFHBCR
This register indicates the received frame header byte count information, the received frames are reported in RXFCTR
register. This register contains the total number of bytes information for the frame received and the CPU can read so
many times same as the frame count value in the RXFCTR.
Bits
15-12
11-0
DS00002357B-page 52
Description
R/W
Default
Reserved
RO
—
RXBC Receive Byte Count
This field indicates the present received frame byte size.
Note: Always read low byte first for 8-bit mode operation.
RO
—
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.42
TXQ COMMAND REGISTER (0X80 – 0X81): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
Bits
Description
R/W
Default
Reserved
R/W
—
1
TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt
(bit 6 in ISR register) to CPU when TXQ memory is available based upon
the total amount of TXQ space requested by CPU at TXNTFSR (0x9E)
register.
Note: This bit is self-clearing after the frame is finished transmitting. The
software should wait for the bit to be cleared before set to 1 again.
R/W
0x0
0
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will enable current TX
frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The
software should wait for the bit to be cleared before setting up another
new TX frame.
R/W
0x0
15-2
4.2.43
RXQ COMMAND REGISTER (0X82 – 0X83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
Bits
R/W
Default
Reserved
R/W
0x0
12
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at
first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
RO
0x0
11
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of
received bytes in RXQ buffer exceeds the threshold set in RX Data Byte
Count Threshold Register (0x8E, RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RO
0x0
10
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of
received frames in RXQ buffer exceeds the threshold set in RX Frame
Count Threshold Register (0x9C, RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RO
0x0
9
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851-16MLL will enable to add two
bytes before frame header in order for IP header inside the frame
contents to be aligned with double word boundary to speed up software
operation.
R/W
0x0
8
Reserved
R/W
-
7
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt
(bit 13 in ISR) when the time start at first received frame in RXQ buffer
exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
R/W
0x0
15-13
Description
2018 Microchip Technology Inc.
DS00002357B-page 53
KSZ8851-16MLL/MLLI/MLLU
Bits
Description
R/W
Default
6
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt
(bit 13 in ISR) when the number of received bytes in RXQ buffer exceeds
the threshold set in RX Data Byte Count Threshold Register (0x8E,
RXDBCT).
R/W
0x0
5
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt
(bit 13 in ISR) when the number of received frames in RXQ buffer
exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
R/W
0x0
4
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will automatically
enable RXQ frame buffer dequeue. The read pointer in RXQ frame buffer
will be automatically adjusted to next received frame location after current
frame is completely read by the host.
R/W
0x0
3
SDA Start DMA Access
When this bit is written as 1, the KSZ8851-16MLL allows a DMA
operation from the host CPU to access either read RXQ frame buffer or
write TXQ frame buffer with CSN and RDN or WRN signals while the
CMD pin is low. All registers access are disabled except this register
during this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to
access the rest of registers. In order to get out of DMA mode the SD1 bit
must set to “1” when CMD = 1.
WO
0x0
Reserved
R/W
—
RRXEF Release RX Error Frame
When this bit is written as 1, the current RX error frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The
software should wait for the bit to be cleared before processing new RX
frame.
R/W
0x0
2-1
0
4.2.44
TX FRAME DATA POINTER REGISTER (0X84 – 0X85): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment is set, It will automatically increment the pointer value on write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
Bits
Description
R/W
Default
15
Reserved.
RO
—
14
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on accesses to the data register. The increment is by one for
every byte access, by two for every word access, and by four for every
doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by
user to access the TX frame location.
RW
0x0
13-11
Reserved.
RO
—
10-0
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame
Data has been enqueued through the TXQ command register.
RW
0x000
DS00002357B-page 54
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.45
RX FRAME DATA POINTER REGISTER (0X86 – 0X87): RXFDPR
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto increment
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
Bits
Description
R/W
Default
15
Reserved
RO
—
14
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automatically on
accesses to the data register. The increment is by one for every byte access,
by two for every word access, and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by
user to access the RX frame location.
RW
0x0
13
Reserved.
RO
—
12
WST Write Sample Time
This bit is used to select the WRN active to write data valid time as shown in
Figure 10.
0: WRN active to write data valid sample time is range of 8 ns (min) to 16 ns
(max).
1: WRN active to write data valid sample time is 4 ns (max).
RW
0x0
11
EMS Endian Mode Selection
This bit is used to select either Big or Little Endian mode when Endian mode
select strapping pin (10) is NC or tied to GND.
0: is set to Little Endian Mode
1: is set to Big Endian Mode
RO (Read
back is
“0”)
0x0
10-0
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This pointer value must reset to 0x000 before each DMA operation from the
host CPU to read RXQ frame buffer.
RO
0x000
0X88 – 0x8B: Reserved
4.2.46
RX DURATION TIMER THRESHOLD REGISTER (0X8C – 0X8D): RXDTTR
This register is used to program the received frame duration timer threshold.
Bit
Description
R/W
Default
15-0
RXDTT Receive Duration Timer Threshold
To program received frame duration timer threshold value in 1 µs interval.
The maximum value is 0xCFFF.
When bit 7 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX
interrupt (bit 13 in ISR) after the time starts at first received frame in RXQ
buffer and exceeds the threshold set in this register.
RW
0x0000
4.2.47
RX DATA BYTE COUNT THRESHOLD REGISTER (0X8E – 0X8F): RXDBCTR
This register is used to program the received data byte count threshold.
Bit
Description
R/W
Default
15-0
RXDBCT Receive Data Byte Count Threshold
To program received data byte threshold value in byte count.
When bit 6 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX
interrupt (bit 13 in ISR) when the number of received bytes in RXQ buffer
exceeds the threshold set in this register.
RW
0x0000
2018 Microchip Technology Inc.
DS00002357B-page 55
KSZ8851-16MLL/MLLI/MLLU
4.2.48
INTERRUPT ENABLE REGISTER (0X90 – 0X91): IER
This register enables the interrupts from the QMU and other sources.
Bit
Description
R/W
Default
15
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
RW
0x0
14
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
RW
0x0
13
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
RW
0x0
12
Reserved
RW
0x0
11
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
RW
0x0
10
Reserved
RW
0x0
9
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
RW
0x0
8
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
RW
0x0
7
Reserved
RW
0x0
6
TXSAIE Transmit Space Available Interrupt Enable
When this bit is set, the Transmit memory space available interrupt is
enabled.
When this bit is reset, the Transmit memory space available interrupt is
disabled.
RW
0x0
5
RXWFDIE Receive Wake-up Frame Detect Interrupt Enable
When this bit is set, the Receive wakeup frame detect interrupt is
enabled.
When this bit is reset, the Receive wakeup frame detect interrupt is disabled.
RW
0x0
4
RXMPDIE Receive Magic Packet Detect Interrupt Enable
When this bit is set, the Receive magic packet detect interrupt is enabled.
When this bit is reset, the Receive magic packet detect interrupt is disabled.
RW
0x0
3
LDIE Linkup Detect Interrupt Enable
When this bit is set, the wake-up from linkup detect interrupt is enabled.
When this bit is reset, the linkup detect interrupt is disabled.
RW
0x0
2
EDIE Energy Detect Interrupt Enable
When this bit is set, the wake-up from energy detect interrupt is enabled.
When this bit is reset, the energy detect interrupt is disabled.
RW
0x0
1
Reserved.
RO
0x0
0
DEDIE Delay Energy Detect Interrupt Enable
When this bit is set, the delay energy detect interrupt is enabled.
When this bit is reset, the delay energy detect interrupt is disabled.
Note: the delay energy detect interrupt till device is ready for host access.
RW
0x0
DS00002357B-page 56
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.49
INTERRUPT STATUS REGISTER (0X92 – 0X93): ISR
This register contains the status bits for all QMU and other interrupt sources. When the corresponding enable bit is set,
it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear.
Bit
Description
R/W
Default
15
LCIS Link Change Interrupt Enable
When this bit is set, it indicates that the link status has changed from link up to
link down, or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RO
(W1C)
0x0
14
TXIS Transmit Interrupt Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a
frame on the MAC interface and the QMU TXQ is ready for new frames from the
host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RO
(W1C)
0x0
13
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received at least a frame
from the MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RO
(W1C)
0x0
RO
0x0
RO
(W1C)
0x0
RO
0x0
12
Reserved
11
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
10
Reserved
9
TXPSIS Transmit Process Stopped Interrupt Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RO
(W1C)
0x0
8
RXPSIS Receive Process Stopped Interrupt Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RO
(W1C)
0x0
7
Reserved
RO
0x0
6
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has
occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
RO
(W1C)
0x0
5
RXWFDIS Receive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has
occurred. Write “1000” to PMECR[5:2] to clear this bit
RO
0x0
4
RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has
occurred. Write “0100” to PMECR[5:2] to clear this bit.
RO
0x0
3
LDIS Linkup Detect Interrupt Status
When this bit is set, it indicates that wake-up from linkup detect status has
occurred. Write “0010” to PMECR[5:2] to clear this bit.
RO
0x0
2
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up
from energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER
register, it indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
RO
0x0
1
Reserved.
RO
0x0
0
Reserved.
RO
0x0
0x94 – 0x9B: Reserved
2018 Microchip Technology Inc.
DS00002357B-page 57
KSZ8851-16MLL/MLLI/MLLU
4.2.50
RX FRAME COUNT AND THRESHOLD REGISTER (0X9C – 0X9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
Bit
Description
R/W
Default
15-8
RXDBCT Receive Data Byte Count Threshold
To program received data byte threshold value in byte count.
When bit 6 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX
interrupt (bit 13 in ISR) when the number of received bytes in RXQ buffer
exceeds the threshold set in this register.
R/W
0x00
7-0
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
Note: When bit 5 set to 1 in RXQCR register, the RXFCT Receive Frame
Threshold can’t set to 0, the KSZ8851-16MLL will set RX interrupt (bit 13
in ISR) when the number of received frames in RXQ buffer exceeds or
equals to the threshold set in this register.
R/W
0x00
4.2.51
TX NEXT TOTAL FRAMES SIZE REGISTER (0X9E – 0X9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
Bit
Description
R/W
Default
15-0
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space
which is required for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR register) to
CPU when TXQ memory is available based upon the total amount of TXQ
space requested by CPU at this register.
R/W
0x0000
4.2.52
MAC ADDRESS HASH TABLE REGISTER 0 (0XA0 – 0XA1): MAHTR0
The 64-bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect”
mode in Table 3-3 (Address Filtering Scheme). This value is defined as the six most significant bits from CRC circuit
calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be
used, while the others determine which bit within the register.
Multicast table register 0.
Bit
15-0
Description
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches
the CRC, the hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
DS00002357B-page 58
R/W
Default
R/W
0x0
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.53
MAC ADDRESS HASH TABLE REGISTER 1 (0XA2 – 0XA3): MAHTR1
Multicast table register 1.
Bit
Description
R/W
Default
15-0
HT1 Hash Table 1
When the appropriate bit is set, if the packet received with DA matches
the CRC, the hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set
in the RXCR1, all multicast addresses are received regardless of the multicast table value.
R/W
0x0
4.2.54
MAC ADDRESS HASH TABLE REGISTER 2 (0XA4 – 0XA5): MAHTR2
Multicast table register 2.
Bit
Description
R/W
Default
15-0
HT2 Hash Table 2
When the appropriate bit is set, if the packet received with DA matches
the CRC, the hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set
in the RXCR1, all multicast addresses are received regardless of the multicast table value.
R/W
0x0
4.2.55
MAC ADDRESS HASH TABLE REGISTER 3 (0XA6 – 0XA7): MAHTR3
Multicast table register 3.
Bit
Description
R/W
Default
15-0
HT3 Hash Table 3
When the appropriate bit is set, if the packet received with DA matches
the CRC, the hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set
in the RXCR1, all multicast addresses are received regardless of the multicast table value.
R/W
0x0
0xA8 – 0xAF: Reserved
4.2.56
FLOW CONTROL LOW WATERMARK REGISTER (0XB0 – 0XB1): FCLWR
This register is used to control the flow control for low watermark in QMU RX queue.
Bit
Description
R/W
Default
15-12
Reserved.
R/W
—
11--0
FCLWC Flow Control Low Watermark Configuration
These bits are used to define the QMU RX queue low watermark configuration. It is in double words count and default is 5.12 KByte available buffer space out of 12 KByte.
R/W
0x0500
2018 Microchip Technology Inc.
DS00002357B-page 59
KSZ8851-16MLL/MLLI/MLLU
4.2.57
FLOW CONTROL HIGH WATERMARK REGISTER (0XB2 – 0XB3): FCHWR
This register is used to control the flow control for high watermark in QMU RX queue.
Bit
Description
R/W
Default
15-12
Reserved.
R/W
—
11--0
FCHWC Flow Control High Watermark Configuration
These bits are used to define the QMU RX queue high watermark configuration. It is in double words count and default is 3.072 KByte available
buffer space out of 12 KByte.
R/W
0x0300
4.2.58
FLOW CONTROL OVERRUN WATERMARK REGISTER (0XB4 – 0XB5): FCOWR
This register is used to control the flow control for high watermark in QMU RX queue.
Bit
Description
R/W
Default
15-12
Reserved.
R/W
—
11--0
FCLWC Flow Control Overrun Watermark Configuration
These bits are used to define the QMU RX queue overrun watermark
configuration. It is in double words count and default is 256 Bytes available buffer space out of 12 Kbyte.
R/W
0x0040
R/W
Default
0xB6 – 0xBF: Reserved
4.2.59
CHIP ID AND ENABLE REGISTER (0XC0 – 0XC1): CIDER
This register contains the chip ID and the chip enable bit.
Bit
Description
15-8
Family ID
Chip family ID
RO
0x88
7-4
Chip ID
0x7 is assigned to KSZ8851-16MLL
RO
0x7
3-1
Revision ID
Note: Bits[3-1]=0 is for rev. A2 part, bits[3-1]=1 is for rev.A3 part.
RO
—
Reserved
R/W
0x0
R/W
Default
0
0xC2 – 0xC5: Reserved
4.2.60
CHIP GLOBAL CONTROL REGISTER (0XC6 – 0XC7): CGCR
This register contains the global control for the chip function.
Bit
Description
15-12
Reserved
R/W
0x0
11-10
Reserved
R/W
0x2
R/W
0x0
LEDSEL0
This bit sets the LEDSEL0 selection for P1LED1 and P1LED0. PHY port
LED indicators, defined as below:
9
—
LEDSEL0 (bit9)
0
1
P1LED1
100BT
ACT
P1LED0
LINK/ACT
LINK
8
Reserved
R/W
0x0
7-0
Reserved
R/W
0x35
DS00002357B-page 60
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.61
INDIRECT ACCESS CONTROL REGISTER (0XC8 – 0XC9): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read access is determined by bit 12).
Bit
Description
R/W
Default
Reserved
R/W
0x0
Read Enable.
1 = Read cycle is enabled (MIB counter will clear after
read).
0 = No operation.
R/W
0x0
Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
R/W
0x0
9-5
Reserved.
R/W
—
4-0
Indirect Address
Bit 4-0 of indirect address for 32 MIB counter locations.
R/W
0x00
15-13
12
11-10
0xCA – 0xCF: Reserved
4.2.62
INDIRECT ACCESS DATA LOW REGISTER (0XD0 – 0XD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Bit
Description
15-0
4.2.63
Indirect Low Word Data
Bit 15-0 of indirect data.
R/W
Default
R/W
0X0000
INDIRECT ACCESS DATA LOW REGISTER (0XD2 – 0XD3): IADHR
This register contains the indirect data (low word) for MIB counter.
Bit
Description
15-0
4.2.64
Indirect High Word Data
Bit 31-16 of indirect data.
R/W
Default
R/W
0X0000
POWER MANAGEMENT EVENT CONTROL REGISTER (0XD4 – 0XD5): PMECR
This register is used to control the KSZ8851-16MLL power management event, capabilities, and status.
Bit
Description
R/W
Default
15
Reserved
RO
—
14
PME Delay Enable
This bit is used to enable the delay of PME output pin
assertion.
When this bit is set to 1, the device will not assert the
PME output until all the clocks in the device are running
and it is ready for host accesses.
When this bit is set to 0, the device will assert the PME
output without delay.
This bit is only valid when Auto Wake-Up Enable (bit7) is
set to 1 in this register.
R/W
0
13
Reserved
R/W
0
2018 Microchip Technology Inc.
DS00002357B-page 61
KSZ8851-16MLL/MLLI/MLLU
Bit
Description
R/W
Default
12
PME Output Polarity
This bit is used to control the PME output pin polarity.
When this bit is set to 1, the PME output pin is active high.
When this bit is set to 0, the PME output pin is active low.
R/W
0
11-8
Wake-on-LAN to PME Output Enable
These four bits are used to enable the PME output pin
asserted when one of these wake-on-LAN events is
detected:
Bit 11: is corresponding to receive wake-up frame.
Bit 10: is corresponding to receive magic packet.
Bit 9: is corresponding to link change from down to up.
Bit 8: is corresponding to signal energy detected.
When the bit is set to 1, the PME pin will be asserted
when a corresponding wake-on-LAN event is occurred.
When this bit is set to 0, the PME pin will be not asserted
when a corresponding wake-on-LAN event is occurred.
R/W
0x0
7
Auto Wake-Up Enable
This bit is used to enable automatically wake-up from low
power state to normal power state in energy detect mode
if carrier (signal energy) is present more than wake-up
time in GSWUTR register. During the normal power state,
the device can receive and transmit packets.
When this bit is set to 1, the auto wake-up is enabled in
energy detect mode.
When this bit is set to 0, the auto wake-up is disabled in
energy detect mode.
R/W
0
6
Wake-Up to Normal Operation Mode
This bit is used to control the device wake-up from low
power state in energy detect mode to normal operation
mode if signal energy is detected longer than the programmed wake-up time in GSWUTR register.
When this bit is set to 1, the device will automatically go to
the normal operation mode from energy detect mode.
When this bit is set to 0, the device will not automatically
go to the normal mode from energy detect mode.
This bit is only valid when Auto Wake-Up Enable (bit7) is
set to 1.
R/W
0
5-2
Wake-Up Event Indication
These four bits are used to indicate the KSZ8851-16MLL
wake-up event status as below:
0000: No wake-up event.
0001: Wake-up from energy event detected. (Bit 2 also
set to 1 in ISR register)
0010: Wake-up from link up event detected. (Bit 3 also set
to 1 in ISR register)
0100: Wake-up from magic packet event detected.
1000: Wake-up from wakeup frame event detected.
If Wake-on-LAN to PME Output Enable bit [11:8] are set,
the KSZ8851-16MLL also asserts the PME pin. These bits
are cleared on power up reset or by writing 1 to bits [5-2]
(W1C). It is not modified by either hardware or software
reset. When these bits are cleared, the KSZ8851-16MLL
deasserts the PME pin.
RO
(W1C)
0x0
DS00002357B-page 62
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Bit
Description
Power Management Mode
These two bits are used to control the KSZ8851-16MLL
power management mode as below:
00: Normal Operation Mode.
01: Energy Detect Mode. (two states in this mode either
low power or normal power)
10: Reserved: Should not be used.
11: Power-saving mode.
In energy detect mode under low power state, it can
wake-up to normal operation mode from line to get the
energy.
1-0
4.2.65
R/W
Default
R/W
0x0
GO-SLEEP AND WAKE-UP TIME REGISTER (0XD6 – 0XD7): GSWUTR
This register contains the value which is used to control minimum Go-Sleep time period when the device from normal
power state to low power state or to control minimum Wake-Up time period when the device from low power state to
normal power state in energy detect mode.
Bit
Description
R/W
Default
15-8
Wake-up Time
This value is used to control the minimum period that the
energy has to be detected consecutively before the
device is waked-up from the low power state. The unit is
16 ms ±80%, the default wake-up time is 128 ms (16 ms
x 8). Zero time (0x00) is not allowed.
R/W
0x08
7-0
Go-sleep Time
This value is used to control the minimum period that the
no energy event has to be detected consecutively before
the device enters the low power state when the energy
detect mode is on. The unit is 1 sec ±80%, the default
go-sleep time is 12 sec (1s x 12). Zero time (0x00) is not
allowed.
R/W
0x0C
R/W
Default
R/W
—
RO
(Self Clear)
0
4.2.66
PHY RESET REGISTER (0XD8 – 0XD9): PHYRR
This register contains a control bit to reset PHY block when write an “1”.
Bit
15-1
0
Description
Reserved.
PHY Reset Bit
This bit is write only and self clear after write an “1”, it is
used to reset PHY block circuitry.
0xDA – 0xDF: Reserved
0xE0 – 0xE3: Reserved
2018 Microchip Technology Inc.
DS00002357B-page 63
KSZ8851-16MLL/MLLI/MLLU
4.2.67
PHY 1 MII-REGISTER BASIC CONTROL REGISTER (0XE4 – 0XE5): P1MBCR
This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.
Bit
Description
R/W
Default
Bit is Same as:
15
Reserved
RO
0
—
14
Local (far-end) loopback (llb)
1 = perform local loopback at host
(host Tx -> PHY -> host Rx, see Figure 3-7)
0 = normal operation
R/W
0
—
13
Force 100
1 = force 100 Mbps if AN is disabled (bit 12)
0 = force 10 Mbps if AN is disabled (bit 12)
R/W
1
Bit 6 in P1CR
12
AN Enable
1 = auto-negotiation enabled.
0 = auto-negotiation disabled.
R/W
1
Bit 7 in P1CR
11-10
Reserved
R/W
0
—
9
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
R/W
0
Bit 13 in P1CR
8
Force Full Duplex
1 = force full duplex
0 = force half duplex.
if AN is disabled (bit 12) or AN is enabled but
failed.
R/W
1
Bit 5 in P1CR
7-6
Reserved
RO
0
—
5
HP_mdix
1 = HP Auto MDI-X mode.
0 = Microchip Auto MDI-X mode.
R/W
1
Bit 15 in P1CR
4
Force MDI-X
1 = if auto MDI/MDI-X is disabled, force PHY
into MDI mode.
0 = if auto MDI/MDI-X is disabled, force PHY
into MDI-X mode..
R/W
0
Bit 9 in P1CR
3
Disable MDI-X
1 = disable auto MDI-X.
0 = normal operation.
R/W
0
Bit 10 in P1CR
2
Reserved.
R/W
0
—
1
Disable Transmit
1 = disable transmit.
0 = normal operation.
R/W
0
Bit 14 in P1CR
0
Disable LED
1 = disable all LEDs.
0 = normal operation.
R/W
0
Bit 15 in P1CR
;
DS00002357B-page 64
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
4.2.68
PHY 1 MII-REGISTER BASIC STATUS REGISTER (0XE6 – 0XE7): P1MBSR
This register contains the MII register status for the chip function.
Bit
Description
R/W
Default
Bit is Same as:
15
T4 Capable
1 = 100 BASE-T4 capable.
0 = not 100 BASE-T4 capable.
RO
0
—
14
100 Full Capable
1 = 100BASE-TX full-duplex capable.
0 = not 100BASE-TX full-duplex capable.
RO
0
—
13
100 Half Capable
1= 100BASE-TX half-duplex capable.
0= not 100BASE-TX half-duplex capable
RO
1
—
12
10 Full Capable
1 = 10BASE-T full-duplex capable.
0 = not 10BASE-T full-duplex capable.
RO
1
—
11
10 Half Capable
1= 10BASE-TX half-duplex capable.
0= not 10BASE-TX half-duplex capable
RO
0
—
10-7
Reserved
RO
0
—
6
Preamble suppressed
Not supported.
RO
1
—
5
AN Complete
1 = auto-negotiation complete.
0 = auto-negotiation not completed.
RO
0
Bit 6 in P1SR
4
Reserved
RO
1
—
3
AN Capable
1 = auto-negotiation capable.
0 = not auto-negotiation capable.
RO
0
—
2
Link Status
1 = link is up; 0 = link is down.
RO
0
Bit 5 in P1SR
1
Jabber test
Not supported.
RO
0
—
0
Extended Capable
1 = extended register capable.
0 = not extended register capable.
RO
0
—
4.2.69
PHY 1 PHY ID LOW REGISTER (0XE8 – 0XE9): PHY1ILR
This register contains the PHY ID (low) for the chip.
Bit
Description
15-0
4.2.70
PHYID Low
Low order PHYID bits.
Default
R/W
0x1430
RO
Default
R/W
0x0022
RO
PHY 1 PHY ID HIGH REGISTER (0XEA – 0XEB): PHY1IHR
This register contains the PHY ID (high) for the chip.
Bit
15-0
Description
PHYID High
High order PHYID bits.
2018 Microchip Technology Inc.
DS00002357B-page 65
KSZ8851-16MLL/MLLI/MLLU
4.2.71
PHY 1 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (0XEC – 0XED): P1ANAR
This register contains the auto-negotiation advertisement for the PHY function.
Bit
Description
Default
R/W
Bit is Same As:
15
Next page
Not supported.
0
RO
—
14
Reserved
0
RO
—
13
Remote fault
Not supported.
0
RO
—
12-11
0x0
RO
—
10
Pause (flow control capability)
1 = advertise pause capability.
0 = do not advertise pause
capability.
1
RW
Bit 4 in P1CR
9
Reserved.
0
RW
—
8
Adv 100 Full
1 = advertise 100 full-duplex
capability.
0 = do not advertise 100 fullduplex capability
1
RW
Bit 3 in P1CR
7
Adv 100 Half
1= advertise 100 half-duplex
capability.
0 = do not advertise 100 halfduplex capability.
1
RW
Bit 2 in P1CR
6
Adv 10 Full
1 = advertise 10 full-duplex
capability.
0 = do not advertise 10 fullduplex capability.
1
RW
Bit 1 in P1CR
5
Adv 10 Half
1 = advertise 10 half-duplex
capability.
0 = do not advertise 10 halfduplex capability.
1
RW
Bit 0 in P1CR
0x01
RO
—
Selector Field
802.3
4-0
4.2.72
Reserved
PHY 1 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (0XEE – 0XEF): P1ANLPR
This register contains the auto-negotiation link partner ability for the chip function.
Bit
Description
Default
R/W
Bit is Same As:
15
Next page
Not supported.
0
RO
14
LP ACK
Not supported.
0
RO
13
Remote fault
Not supported.
0
RO
—
12-11
Reserved
—
—
0x0
RO
—
10
Pause
Link partner pause capability.
0
RO
Bit 4 in P1SR
9
Reserved.
0
RO
—
DS00002357B-page 66
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Bit
Description
Default
R/W
8
Adv 100 Full
Link partner 100 full capability.
0
RO
Bit 3 in P1SR
7
Adv 100 Half
Link partner 100 half capability.
0
RO
Bit 2 in P1SR
6
Adv 10 Full
Link partner 10 full capacity.
0
RO
Bit 1 in P1SR
5
Adv 10 Half
Link partner 10 half capability.
0
RO
Bit 0 in P1SR
0x01
RO
—
4-0
Reserved.
Bit is Same As:
0xF0 – 0xF3: Reserved
4.2.73
PORT 1 PHY SPECIAL CONTROL/STATUS, LINKMD (0XF4 – 0XF5): P1SCLMD
This register contains the special control, status and LinkMD information of PHY1.
Bit
Default
R/W
0
RO
—
0x0
RO
—
12
Vct_en
Vct enable.
1 = the cable diagnostic test is
enabled. It is self-cleared after the
VCT test is done.
0 = it indicates the cable diagnostic
test is completed and the status information is valid for read.
0
RW
(Self-Clear)
—
11
Force_lnk
Force link.
1 = force link pass; 0 = normal operation.
0
RW
—
10
Reserved.
0
RO
—
9
Remote (Near-end) loopback (rlb)
1 = perform remote loopback at PHY
(RXP1/RXM1 -> TXP1/TXM1, see Figure 9)
0 = normal operation
15
14-13
8-0
Description
Reserved
Vct_result
VCT result.
[00] = normal condition.
[01] = open condition has been
detected in cable.
[10] = short condition has been
detected in cable.
[11] = cable diagnostic test is failed.
Vct_fault_count
VCT fault count.
Distance to the fault. It’s approximately
0.4m*vct_fault_count.
2018 Microchip Technology Inc.
Bit is Same As:
—
0
RW
0x000
RO
—
DS00002357B-page 67
KSZ8851-16MLL/MLLI/MLLU
4.2.74
PORT 1 CONTROL REGISTER (0XF6 – 0XF7): P1CR
This register contains the global per port control for the chip function.
Bit
Description
Default
R/W
15
LED Off
1 = Turn off all of the port 1 LEDs (P1LED3,
P1LED2, P1LED1, P1LED0). These pins
are driven high if this bit is set to one.
0 = normal operation.
0
RW
Bit 0 in P1MBCR
14
Txids
1 = disable the port’s transmitter.
0 = normal operation.
0
RW
Bit 1 in P1MBCR
13
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
0
RW
Bit 9 in P1MBCR
12
Reserved
0
RW
—
11
Reserved
0
RW
—
10
Disable auto MDI/MDI-X
1 = disable auto MDI/MDI-X function.
0 = enable auto MDI/MDI-X function.
0
RW
Bit 3 in P1MBCR
9
Force MDI-X
1= if auto MDI/MDI-X is disabled, force PHY
into MDI mode.
0 = if auto MDI/MDI-X is disabled, force PHY
into MDI-X mode.
0
RW
Bit 4 in P1MBCR
8
Reserved
0
RW
—
7
Auto Negotiation Enable
1 = auto negotiation is enabled.
0 = disable auto negotiation, speed, and
duplex are decided by bits 6 and 5 of the
same register.
1
RW
Bit 12 in P1MBCR
6
Force Speed
1 = force 100BT if AN is disabled (bit 7).
0 = force 10BT if AN is disabled (bit 7).
1
RW
Bit 13 in P1MBCR
5
Force Duplex
1 = force full duplex if (1) AN is disabled or
(2) AN is enabled but failed.
0 = force half duplex if (1) AN is disabled or
(2) AN is enabled but failed.
1
RW
Bit 8 in P1MBCR
4
Advertised flow control capability
1 = advertise flow control (pause) capability.
0 = suppress flow control (pause) capability
from transmission to link partner.
1
RW
Bit 10 in P1ANAR
3
Advertised 100BT full-duplex capability
1 = advertise 100BT full-duplex capability.
0 = suppress 100BT full-duplex capability
from transmission to link partner.
1
RW
Bit 8 in P1ANAR
2
Advertised 100BT half-duplex capability
1 = advertise 100BT half-duplex capability.
0 = suppress 100BT half-duplex capability
from transmission to link partner.
1
RW
Bit 7 in P1ANAR
1
Advertised 10BT full-duplex capability
1 = advertise 10BT full-duplex capability.
0 = suppress 10BT full-duplex capability
from transmission to link partner.
1
RW
Bit 6 in P1ANAR
DS00002357B-page 68
Bit is Same As:
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Bit
0
4.2.75
Description
Advertised 10BT half-duplex capability
1 = advertise 10BT half-duplex capability.
0 = suppress 10BT half-duplex capability
from transmission to link partner.
Default
R/W
1
RW
Bit is Same As:
Bit 5 in P1ANAR
PORT 1 STATUS REGISTER (0XF8 – 0XF9): P1SR
This register contains the PHY port status for the chip function.
Bit
Description
Default
R/W
Bit is Same As:
15
HP_mdix
1 = HP Auto MDI-X mode.
0 = Microchip Auto MDI-X mode.
1
RW
Bit 5 in P1MBCR
14
Reserved
0
RO
—
13
Polarity Reverse
1 = polarity is reversed.
0 = polarity is not reversed.
0
RO
—
Reserved
0
RO
—
10
Operation Speed
1 = link speed is 100 Mbps.
0 = link speed is 10 Mbps.
0
RO
—
9
Operation Duplex
1 = link duplex is full.
0 = link duplex is half.
0
RO
—
8
Reserved
0
RO
—
7
MDI-X status
1 = MDI.
0 = MDI-X.
1
RO
—
6
AN Done
1 = AN done.
0 = AN not done.
0
RO
Bit 5 in P1MBSR
5
Link Good
1= link good.0 = link not good.
0
RO
Bit 2 in P1MBSR
4
Partner flow control capability
1 = link partner flow control (pause) capable.
0 = link partner not flow control (pause)
capable.
0
RO
Bit 10 in P1ANLPR
3
Partner 100BT full-duplex capability
1 = link partner 100BT full-duplex capable.
0 = link partner not 100BT full-duplex
capable.
0
RO
Bit 8 in P1ANLPR
2
Partner 100BT half-duplex capability
1 = link partner 100BT half-duplex capable.
0= link partner not 100BT half-duplex
capable.
0
RO
Bit 7 in P1ANLPR
1
Partner 10BT full-duplex capability
1= link partner 10BT full-duplex capable.
0 = link partner not 10BT full-duplex
capable.
0
RO
Bit 6 in P1ANLPR
0
Partner 10BT half-duplex capability
1 = link partner 10BT half-duplex capable.
0 = link partner not 10BT half-duplex
capable.
0
RO
Bit 5 in P1ANLPR
12-11
0xFA – 0xFF: Reserved
2018 Microchip Technology Inc.
DS00002357B-page 69
KSZ8851-16MLL/MLLI/MLLU
4.3
MIB (Management Information Base) Counters
The KSZ8851-16MLL provides 32 MIB counters to monitor the port activity for network management. The MIB counters
are formatted as shown below:
TABLE 4-3:
FORMAT OF MIB COUNTERS
Bit
Name
R/W
31-0
Counter
values
RO
Description
Counter value (read clear)
Default
0x00000000
Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F. Refer to
Table 4-4.
TABLE 4-4:
PORT 1 MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset
Counter Name
0x0
RxByte
Description
Rx octet count including bad packets
0x1
Reserved
0x2
RxUndersizePkt
Reserved
0x3
RxFragments
0x4
RxOversize
Rx oversize packets w/ good CRC (max: 1536 bytes)
0x5
RxJabbers
Rx packets longer than 1536 bytes w/ either CRC errors, alignment
errors, or symbol errors
0x6
RxSymbolError
0x7
RxCRCError
Rx packets within (64,2000) bytes w/ an integral number of bytes and
a bad CRC
0x8
RxAlignmentError
Rx packets within (64,2000) bytes w/ a non-integral number of bytes
and a bad CRC
0x9
RxControl8808Pkts
Number of MAC control frames received by a port with 88-08h in EtherType field
0xA
RxPausePkts
Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-08h), DA, control opcode (00-01), data length
(64B min), and a valid CRC
0xB
RxBroadcast
Rx good broadcast packets (not including error broadcast packets or
valid multicast packets)
0xC
RxMulticast
Rx good multicast packets (not including MAC control frames, error
multicast packets or valid broadcast packets)
Rx undersize packets w/ good CRC
Rx fragment packets w/ bad CRC, symbol errors or alignment errors
Rx packets w/ invalid data symbol and legal packet size
0xD
RxUnicast
0xE
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length
0xF
Rx65to127Octets
Total Rx packets (bad packets included) that are between 65 and 127
octets in length
0x10
Rx128to255Octets
Total Rx packets (bad packets included) that are between 128 and
255 octets in length
0x11
Rx256to511Octets
Total Rx packets (bad packets included) that are between 256 and 511
octets in length
0x12
Rx512to1023Octets
Total Rx packets (bad packets included) that are between 512 and
1023 octets in length
0x13
Rx1024to1521Octets
Total Rx packets (bad packets included) that are between 1024 and
1521 octets in length
0x14
Rx1522to2000Octets
Total Rx packets (bad packets included) that are between 1522 and
2000 octets in length
0x15
TxByte
DS00002357B-page 70
Rx good unicast packets
Tx good octet count, including PAUSE packets
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
TABLE 4-4:
PORT 1 MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset
Counter Name
Description
0x16
TxLateCollision
0x17
TxPausePkts
0x18
TxBroadcastPkts
Tx good broadcast packets (not including error broadcast or valid multicast packets)
0x19
TxMulticastPkts
Tx good multicast packets (not including error multicast packets or
valid broadcast packets)
0x1A
TxUnicastPkts
Tx good unicast packets
0x1B
TxDeferred
0x1C
TxTotalCollision
0x1D
TxExcessiveCollision
0x1E
TxSingleCollision
0x1F
TxMultipleCollision
The number of times a collision is detected later than 512 bit-times
into the Tx of a packet
Number of PAUSE frames transmitted by a port
Tx packets by a port for which the 1st Tx attempt is delayed due to the
busy medium
Tx total collision, half duplex only
A count of frames for which Tx fails due to excessive collisions
Successfully Tx frames on a port for which Tx is inhibited by exactly
one collision
Successfully Tx frames on a port for which Tx is inhibited by more
than one collision
Example:
MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR (0xC8) with 0x1C0E (set indirect address and trigger a read MIB counters operation)
Then:
Read reg. IADHR (MIB counter value 31-16)
Read reg. IADLR (MIB counter value 15-0)
4.4
Additional MIB Information
In the heaviest condition, the byte counter will overflow in two minutes. It is recommended that the software read all the
counters at least every 30 seconds.
MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
2018 Microchip Technology Inc.
DS00002357B-page 71
KSZ8851-16MLL/MLLI/MLLU
5.0
OPERATIONAL CHARACTERISTICS
5.1
Absolute Maximum Ratings*
Supply Voltage (VDD_A3.3, VDD_IO)....................................................................................................... –0.5V to +4.0V
Input Voltage (All Inputs) ........................................................................................................................... –0.5V to +4.0V
Output Voltage (All Outputs) ..................................................................................................................... –0.5V to +4.0V
HBM ESD Rating (Note 5-1) ......................................................................................................................................6 kV
Note 5-1
Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in
series with 100 pF.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Operating Conditions**, Absolute Maximum Ratings*, or any other applicable section of this specification is not implied. Note that device signals are NOT 5V tolerant
unless specified otherwise.
5.2
Operating Conditions**
Supply Voltage
VDD_A3.3 .......................................................................................................................................... +3.1V to +3.5V
VDD_IO (3.3V)................................................................................................................................... +3.1V to +3.5V
VDD_IO (2.5V)............................................................................................................................... +2.35V to +2.65V
VDD_IO (1.8V)................................................................................................................................... +1.7V to +1.9V
**The device is not guaranteed to function outside its operating ratings.
Electrical Characteristics
TA = 25°C, bold values indicate –40°C≤ TA ≤ +85°C, unless noted.
Parameter
Symbol
Min.
Typ.
Max.
Units
Condition
Supply Current for 100BASE-TX Operation (Single Port @ 100% Utilization)
100BASE-TX
(analog core + PLL +
digital core + transceiver
+ digital I/O)
IDD1
—
85
—
mA
VDD_A3.3, VDD_IO = 3.3V;
Chip only (no transformer)
—
85
—
mA
VDD_A3.3 = 3.3V, VDD_IO =
2.5V; Chip only (no transformer)
—
85
—
mA
VDD_A3.3 = 3.3V, VDD_IO =
1.8V; Chip only (no transformer)
Supply Current for 10BASE-T Operation (Single Port @ 100% Utilization)
10BASE-T
(analog core + PLL +
digital core + transceiver
+ digital I/O)
IDD2
—
75
—
mA
VDD_A3.3, VDD_IO = 3.3V;
Chip only (no transformer)
—
75
—
mA
VDD_A3.3 = 3.3V, VDD_IO =
2.5V; Chip only (no transformer)
—
75
—
mA
VDD_A3.3 = 3.3V, VDD_IO =
1.8V; Chip only (no transformer)
Power Management Mode
Power-saving mode
IDD3
—
70
—
mA
Ethernet cable disconnected
and auto-negotiate
Energy-detect mode
IDD5
—
2
—
mA
At low power state
DS00002357B-page 72
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
Parameter
Symbol
Min.
Typ.
Max.
Units
Condition
CMOS Inputs (VDD_IO = 3.3V/2.5V/1.8V)
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
IIN
2.0
—
—
/1.8
—
—
/1.3
—
—
—
—
0.8
—
—
/0.7
—
—
/0.5
–10
—
10
V
—
V
—
µA
VIN = GND ~ VDD_IO
V
IOH = 8 mA
V
IOL = 8 mA
CMOS Outputs (VDD_IO = 3.3V/2.5V/1.8V)
Output High Voltage
Output Low Voltage
VOH
VOL
Output Tri-State Leakage |IOZ|
Power Management Mode
2.4
—
—
/2.0
—
—
/1.5
—
—
—
—
0.4
—
—
/0.4
—
—
/0.4
–10
—
10
µA
—
Power-saving mode
IDD3
—
70
—
mA
Ethernet cable disconnected
and auto-negotiate
Energy-detect mode
IDD5
—
2
—
mA
At low power state
100BASE-TX Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
Voltage
VO
±0.95
—
±1.05
V
100Ω termination on the differential output
Output Voltage
Imbalance
VIMB
—
—
2
%
100Ω termination on the differential output
Rise/Fall Time
tr/tf
3
—
5
ns
—
Rise/Fall Imbalance
—
0
—
0.5
ns
—
Duty Cycle Distortion
—
—
—
±0.25
ns
—
Overshoot
—
—
—
5
%
—
Reference Voltage of ISET VSET
—
0.5
—
V
—
Output Jitter
—
—
0.7
1.4
ns
Peak-to-peak
VSQ
—
400
—
mV
5 MHz square wave
10BASE-T Receive
Squelch Threshold
10BASE-T Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
Voltage
VP
2.2
2.5
2.8
V
100Ω termination on the differential output
Jitter Added
—
—
1.8
3.5
ns
100Ω termination on the differential output
(peak-to-peak)
2018 Microchip Technology Inc.
DS00002357B-page 73
KSZ8851-16MLL/MLLI/MLLU
6.0
TIMING SPECIFICATIONS
6.1
Asynchronous Read and Write Timing (Processor Read and Write)
FIGURE 6-1:
TABLE 6-1:
ASYNCHRONOUS CYCLE
ASYNCHRONOUS CYCLE TIMING PARAMETERS
Symbol
Parameter
Min.
Typ.
Max.
Units
t1
CSN, CMD valid to RDN, WRN active.
0
—
—
ns
t2
RDN active to Read Data SD[15:0] valid
Note: This is KSZ8851 output delay after RDN
active when the processor read data.
24
—
32
ns
t3
RDN inactive to Read data invalid
Note: The processor latch read data at RDN rising
edge.
1
—
2
ns
t4
CSN, CMD hold after RDN, WRN inactive
0
—
—
ns
t5
WRN active to write data valid (bit12 = 0 in
RXFDPR)
8
—
16
ns
—
WRN active to write data valid (bit12 = 1 in RXFDPR)
Note: It is better if the processor can provide data
less than 4 ns after WRN active. If the processor
provides data more than 4 ns after WRN active,
keep the default bit12=0 of the register RXFDPR.
—
—
4
ns
t6
—
RDN Read active time (low)
40
—
—
ns
WRN Write active time (low)
40
—
—
ns
t7
—
RDN Read inactive time (high)
10
—
—
ns
RDN Read inactive time (high)
10
—
—
ns
DS00002357B-page 74
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
6.2
Auto-Negotiation Timing
FIGURE 6-2:
AUTO-NEGOTIATION TIMING
FLP
BURST
TX+/TX–
FLP
BURST
tFLPWW
tBTB
TX+/TX–
CLOCK
PULSE
DATA
PULSE
tPWW
tPWW
CLOCK
PULSE
DATA
PULSE
tCTC
tCTC
TABLE 6-2:
AUTO-NEGOTIATION TIMING PARAMETERS
Timing
Parameter
Description
Min.
Typ.
Max.
Units
tBTB
FLP burst to FLP burst
8
16
24
ms
tFLPW
FLP burst width
—
2
—
ms
tPW
Clock/data pulse width
—
100
—
ns
tCTD
Clock pulse to data pulse
55.5
64
69.5
µs
tCTC
Clock pulse to clock pulse
111
128
139
µs
—
Number of clock/data pulses per burst
17
—
33
—
6.3
Reset Timing
As long as the stable supply voltages to reset High timing (minimum of 10 ms) are met, there is no power-sequencing
requirement when the KSZ8851-16MLL use a single 3.3V power supply with internal 1.8V LDO. It is also requirement
the power-sequencing to power up the 1.8V voltage earlier than VDDIO voltage if the internal 1.8V LDO is not used. At
least, the both 1.8V voltage and VDDIO voltage should come up at the same time when do not using the internal 1.8V
LDO.
The reset timing requirement is summarized in the Figure 6-3 and Table 6-3.
FIGURE 6-3:
RESET TIMING
SUPPLY
VOLTAGE
TSR
RSTN
TABLE 6-3:
RESET TIMING PARAMETERS
Symbol
Parameter
Min
Max
Unit
tsr
Stable supply voltages to reset high
10
—
ms
2018 Microchip Technology Inc.
DS00002357B-page 75
KSZ8851-16MLL/MLLI/MLLU
6.4
EEPROM Timing
FIGURE 6-4:
EEPROM READ CYCLE TIMING DIAGRAM
EECS
*1
1
EESK
tcyc
EED_IO
(OUTPUT)
11
0
AN
A0
ts
th
EED_IO
(INPUT )
HIGH-Z
D15
D14
D1
D13
D0
*1 START BIT
TABLE 6-4:
EEPROM TIMING PARAMETERS
Timing Parameter
Description
Min
Typ
Max
Unit
tcyc
Clock cycle
—
0.8 (OBCR[1:0]=00
on-chip bus speed
@ 125 MHz)
—
µs
ts
Setup time
20
—
—
ns
th
Hold time
20
—
—
ns
DS00002357B-page 76
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
6.5
Reset Circuit Diagram
The following discrete reset circuit shown in Figure 6-5 is recommended for use when powering up the KS8851 device.
For applications where the reset signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset
circuit shown in Figure 6-6.
FIGURE 6-5:
RECOMMENDED RESET CIRCUIT
VC
D1: 1N4148
R
10k
D1
KSZ8851
RST
C
10µF
FIGURE 6-6:
RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
VC
R
10k
D1
KSZ8851
CPU/FPGA
RST
RST_OUT_n
C
10µF
D2
D1, D2: 1N4148
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the device. The reset out RST_OUT_n
from CPU/FPGA provides the warm reset after power up.
2018 Microchip Technology Inc.
DS00002357B-page 77
KSZ8851-16MLL/MLLI/MLLU
7.0
SELECTION OF ISOLATION TRANSFORMERS
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke
is recommended for exceeding FCC requirements.
Table 7-1 gives recommended transformer characteristics.
TABLE 7-1:
TRANSFORMER SELECTION CRITERIA
Parameter
Value
Test Condition
Turns Ratio
1 CT : 1 CT
—
Open-circuit inductance (min)
350 µH
100 mV, 100 kHz, 8 mA
Leakage inductance (max)
0.4 µH
1 MHz (min)
Inter-winding capacitance (max)
12 pF
—
DC resistance (max)
0.9Ω
—
Insertion loss (max)
1.0 dB
0 MHz – 65 MHz
HIPOT (min)
1500 VRMS
—
TABLE 7-2:
QUALIFIED SINGLE-PORT MAGNETICS
Magnetic Manufacturer
Part Number
Auto MDI-X
Number of Port(s)
Pulse
H1102
Yes
1
Pulse (low cost)
H1260
Yes
1
Transpower
HB726
Yes
1
Bel Fuse
S558-5999-U7
Yes
1
Delta
LF8505
Yes
1
LanKom
LF-H41S
Yes
1
TDK (Mag Jack)
TLA-6T718
Yes
1
DS00002357B-page 78
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
8.0
SELECTION OF REFERENCE CRYSTAL
TABLE 8-1:
TYPICAL REFERENCE CRYSTAL CHARACTERISTICS
Characteristics
Value
Units
Frequency
25
MHz
Frequency tolerance (max)
±50
ppm
Load capacitance (max)
20
pF
Series resistance
40
Ω
2018 Microchip Technology Inc.
DS00002357B-page 79
KSZ8851-16MLL/MLLI/MLLU
9.0
PACKAGE OUTLINE
FIGURE 9-1:
48-PIN (7 MM × 7MM) LQFP PACKAGE OUTLINE AND RECOMMENDED LAND
PATTERN
Note:
DS00002357B-page 80
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
APPENDIX A:
DATA SHEET REVISION HISTORY
TABLE A-1:
Revision
Section/Figure/Entry
Correction
DS00002357A (2-14-17)
—
KSZ8851-16MLL/MLLI/MLLU data sheet converted
to Microchip template. Minor grammatical text
updates throughout data sheet.
DS00002357B (6-8-18)
• Power Modes, Power
Supplies, and Packaging
• Section 3.1.1 “Power
Management”
• Table 3-1
• Section 4.2.64 “Power
Management Event
Control Register (0xD4
– 0xD5): PMECR”
• Electrical Characteristics
References to Soft Power Down mode removed and/
or changed to “Reserved.”
2018 Microchip Technology Inc.
DS00002357B-page 81
KSZ8851-16MLL/MLLI/MLLU
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support
DS00002357B-page 82
Advance Information
2018 Microchip Technology Inc.
KSZ8851-16MLL/MLLI/MLLU
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
X
Device
Option
Package
Option
X
Power
Option
X
Temperature
Device:
KSZ8851-16 - Single-Port Ethernet MAC Controller with 8-Bit
or 16-Bit Non-PCI Interface
Option:
M
=
Managed
Package Option:
L
=
48-pin LQFP
Power Option
L
=
Integrated LDO/LDO Controller/Regulator
Temperature:
Blank
I
U
= Commercial
= Industrial
= Automotive AEC-Q100 qualified
Examples:
a)
b)
c)
KSZ8851-16MLL: Single-Port Ethernet
MAC Controller with 8-Bit
or 16-Bit Non-PCI Interface, Managed Option, 48pin LQFP, Integrated LDO/
LDO Controller/Regulator,
Commercial Temperature
KSZ8851-16MLLI: Single-Port Ethernet
MAC Controller with 8-Bit
or 16-Bit Non-PCI Interface, Managed Option, 48pin LQFP, Integrated LDO/
LDO Controller/Regulator,
Industrial Temperature
KSZ8851-16MLLU: Single-Port Ethernet
MAC Controller with 8-Bit
or 16-Bit Non-PCI Interface, Managed Option, 48pin LQFP, Integrated LDO/
LDO Controller/Regulator,
Automotive
AEC-Q100
qualified Temperature
Note 1:
2018 Microchip Technology Inc.
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Reel size is 4,000.
DS00002357B-page 83
KSZ8851-16MLL/MLLI/MLLU
NOTES:
DS00002357B-page 84
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of
Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication,
CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
©2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3195-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00002357B-page 85
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Finland - Espoo
Tel: 358-9-4520-820
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
China - Qingdao
Tel: 86-532-8502-7355
Philippines - Manila
Tel: 63-2-634-9065
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Israel - Ra’anana
Tel: 972-9-744-7705
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS00002357B-page 86
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2018 Microchip Technology Inc.
10/25/17