KSZ8863MLL/FLL/RLL
Integrated 3-Port 10/100 Managed Switch
with PHYs
Features
• Advanced Switch Features
- IEEE 802.1q VLAN Support for Up to 16 Groups
(Full Range of VLAN IDs)
- VLAN ID Tag/Untag Options, Per Port Basis
- IEEE 802.1p/q Tag Insertion or Removal on a
Per Port Basis (Egress)
- Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
- Broadcast Storm Protection with Percent
Control (Global and Per Port Basis)
- IEEE 802.1d Rapid Spanning Tree Protocol
Support
- Tail Tag Mode (1 byte Added before FCS) Support at Port 3 to Inform the Processor which
Ingress Port Receives the Packet and its Priority
- Bypass Feature that Automatically Sustains the
Switch Function between Port 1 and Port 2
when CPU (Port 3 Interface) Goes to the Sleep
Mode
- Self-Address Filtering
- Individual MAC Address for Port 1 and Port 2
- Supports RMII Interface and 50 MHz Reference
Clock Output
- IGMP Snooping (IPv4) Support for Multicast
Packet Filtering
- IPv4/IPv6 QoS Support
- MAC Filtering Function to Forward Unknown
Unicast Packets to Specified Port
• Comprehensive Configuration Register Access
- Serial Management Interface (SMI) to All Internal Registers
- MII Management (MIIM) Interface to PHY Registers
- High Speed SPI and I2C Interface to All Internal
Registers
- I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch
Mode
- Control Registers Configurable on the Fly (PortPriority, 802.1p/d/q, AN…)
• QoS/CoS Packet Prioritization Support
- Per Port, 802.1p and DiffServ-Based
- Re-Mapping of 802.1p Priority Field Per Port
basis, Four Priority Levels
• Proven Integrated 3-Port 10/100 Ethernet Switch
- 3rd Generation Switch with Three MACs and
Two PHYs Fully Compliant with IEEE 802.3u
Standard
2017-2021 Microchip Technology Inc.
•
•
•
•
- Non-Blocking Switch Fabric Ensures Fast
Packet Delivery by Utilizing a 1k MAC Address
Lookup Table and a Store-and-Forward Architecture
- Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
- Half-Duplex Back Pressure Flow Control
- HP Auto MDI-X for Reliable Detection of and
Correction for Straight-Through and Crossover
Cables with Disable and Enable Option
- LinkMD® TDR-Based Cable Diagnostics Permit
Identification of Faulty Copper Cabling
- MII Interface Supports Both MAC Mode and
PHY Mode
- Comprehensive LED Indicator Support for Link,
Activity, Full-/Half-Duplex and 10/100 Speed
- HBM ESD Rating 4 kV
Switch Monitoring Features
- Port Mirroring/Monitoring/Sniffing: Ingress and/
or Egress Traffic to Any Port or MII
- MIB Counters for Fully Compliant Statistics
Gathering 34 MIB Counters Per Port
- Loopback Modes for Remote Diagnostic of Failure
Low Power Dissipation
- Full-Chip Software Power-Down (Register Configuration Not Saved)
- Energy-Detect Mode Support
- Dynamic Clock Tree Shutdown Feature
- Per Port Based Software Power-Save on PHY
(Idle Link Detection, Register Configuration Preserved)
- Voltages: Single 3.3V Supply with Internal 1.8V
LDO for 3.3V VDDIO
- Optional 3.3V, 2.5V, and 1.8V for VDDIO
- Transceiver Power 3.3V for VDDA_3.3
Industrial Temperature Range: –40°C to +85°C
Available in a 48-Pin LQFP, Lead-Free Package
Applications
•
•
•
•
•
•
•
•
•
•
VoIP Phone
Set-Top/Game Box
Automotive
Industrial Control
IPTV POF
SOHO Residential Gateway
Broadband Gateway/Firewall/VPN
Integrated DSL/Cable Modem
Wireless LAN Access Point + Gateway
Standalone 10/100 Switch
DS00002335C-page 1
KSZ8863MLL/FLL/RLL
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00002335C-page 2
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 11
4.0 Register Descriptions .................................................................................................................................................................... 36
5.0 Operational Characteristics ........................................................................................................................................................... 72
6.0 Electrical Characteristics ............................................................................................................................................................... 73
7.0 Timing Specifications .................................................................................................................................................................... 75
8.0 Reset Circuit ................................................................................................................................................................................. 84
9.0 Selection of Isolation Transformers .............................................................................................................................................. 85
10.0 Package Outline .......................................................................................................................................................................... 86
Appendix A: Data Sheet Revision History ........................................................................................................................................... 87
The Microchip Web Site ...................................................................................................................................................................... 88
Customer Change Notification Service ............................................................................................................................................... 88
Customer Support ............................................................................................................................................................................... 88
Product Identification System ............................................................................................................................................................. 89
2017-2021 Microchip Technology Inc.
DS00002335C-page 3
KSZ8863MLL/FLL/RLL
1.0
INTRODUCTION
1.1
General Description
KSZ8863MLL, KSZ8863FLL, and KSZ8863RLL are highly integrated 3-port switch-on-a-chip ICs in the industry’s smallest footprint. They are designed to enable a new generation of low port count, cost-sensitive, and power-efficient 10/
100 Mbps switch systems. Low power consumption, advanced power management, and sophisticated QoS features
(for example, IPv6 priority classification support) make these devices ideal for IPTV, IP-STB, VoIP, automotive, and
industrial applications.
The KSZ8863 family is designed to support the GREEN requirement in today’s switch systems. Advanced power management schemes include software power down, per port power down, and energy detect mode that shuts down the
transceiver when a port is idle.
KSZ8863MLL/FLL/RLL also offers a bypass mode that enables system-level power saving. In this mode, the processor
connected to the switch through the MII interface can be shut down without impacting the normal switch operation.
The configurations provided by the KSZ8863 family enable the flexibility to meet the requirements of different applications:
• KSZ8863MLL: Two 10/100BASE-T/TX transceivers and one MII interface
• KSZ8863RLL: Two 10/100BASE-T/TX transceivers and one RMII interface
• KSZ8863FLL: One 100BASE-FX, one 10/100BASE-T/TX transceivers, and one MII interface
The devices are available in RoHS-compliant 48-pin LQFP packages. Industrial-grade and automotive-grade are also
available.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
HP AUTO
MDIX
10/100
T/TX/FX
PHY 1
10/100
MAC 1
10/100
T/TX
PHY 2
10/100
MAC 2
MII (for MLL, FLL)
RMII (for RLL)
10/100
MAC 3
SPI
SPI
MIIM
CONTROL
REGISTERS
SMI
FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY
HP AUTO
MDIX
1K LOOK-UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
MIB
COUNTERS
EEPROM
INTERFACE
I2C
P1 LED[1:0]
P2 LED[1:0]
DS00002335C-page 4
LED
DRIVERS
STRAP IN
CONFIGURATION
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
2.0
PIN DESCRIPTION AND CONFIGURATION
48-PIN 7 MM X 7 MM LQFP ASSIGNMENT (TOP VIEW)
FXSD1
RSTN
P2LED0
P2LED1
P1LED0
P1LED1
VDDCO
GND
VDDIO
SPISN
SPIQ
SDA_MDIO
FIGURE 2-1:
48 47 46 45 44 43 42 41 40 39 38 37
RXM1
RXP1
TXM1
TXP1
VDDA_3.3
ISET
VDDA_1.8
RXM2
RXP2
AGND
TXM2
TXP2
1
2
3
4
5
6
7
8
9
10
11
12
48-pin
LQFP
36
35
34
33
32
31
30
29
28
27
26
25
SCL_MDC
INTRN
SCRS3
SCOL3
VDDC
GND
SMRXC3
SMRXD30
SMRXD31
SMRXD32
SMRXD33/REFCLKO_3
SMRXDV3
NC
X1
X2
SMTXEN3
SMTXD33/EN_REFCLKO_3
SMTXD32
SMTXD31
SMTXD30
GND
VDDIO
SMTXC3/REFCLKI_3
SMTXER3/MII_LINK_3
13 14 15 16 17 18 19 20 21 22 23 24
2017-2021 Microchip Technology Inc.
DS00002335C-page 5
KSZ8863MLL/FLL/RLL
TABLE 2-1:
SIGNALS
Pin
Number
Pin
Name
Type
Note 2-1
1
RXM1
I/O
Physical receive or transmit signal (– differential)
2
RXP1
I/O
Physical receive or transmit signal (+ differential)
3
TXM1
I/O
Physical transmit or receive signal (– differential)
4
TXP1
I/O
Physical transmit or receive signal (+ differential)
5
VDDA_3.3
P
3.3V analog VDD
6
ISET
O
Set physical transmit output current.
Pull down this pin with an 11.8 kΩ 1% resistor to ground.
7
VDDA_1.8
P
1.8V analog core power input from VDDCO (pin 42).
8
RXM2
I/O
Physical receive or transmit signal (– differential)
9
RXP2
I/O
Physical receive or transmit signal (+ differential)
10
AGND
GND
11
TXM2
I/O
Physical transmit or receive signal (– differential)
12
TXP2
I/O
Physical transmit or receive signal (+ differential)
13
NC
NC
No connection
14
X1
I
15
X2
O
16
SMTXEN3
Ipu
Switch MII transmit enable
17
SMTXD33/
EN_REFCLKO_3
Ipu
MLL/FLL: Switch MII transmit data bit 3
RLL: Strap option: RMII mode Clock selection
PU = Enable REFCLKO_3 output
PD = Disable REFCLKO_3 output
Description
Analog ground
25 MHz or 50 MHz crystal or oscillator clock connections.
Pins (X1 and X2) connect to a crystal. If an oscillator is used, X1 connects
to a 3.3V tolerant oscillator, and X2 is a NC.
Note: The clock is ±50 ppm for both crystal and oscillator. The clock should
be applied to X1 pin before the reset voltage goes high.
18
SMTXD32
Ipu
Switch MII transmit data bit 2
RLL: Strap option: X1 pin Clock selection (for Rev A3 and behind A3)
PU = 25 MHz to X1 pin as clock source (default)
PD = 50 MHz to X1 pin as clock source to provide or receive 50 MHz RMII
reference clock for RLL part
19
SMTXD31
Ipu
Switch MII/RMII transmit data bit 1
20
SMTXD30
Ipu
21
GND
GND
22
VDDIO
P
3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well decoupling capacitors
Switch MII/RMII transmit data bit 0
Digital ground
23
SMTXC3/
REFCLKI_3
I/O
MLL/FLL: Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII and RMII mode
RLL: Reference clock input
Note: Pull-down by resistor is needed if the internal reference clock is used
in RLL by register 198 bit 3.
24
SMTXER3/
MII_LINK_3
Ipd
Switch port 3 MII transmit error in MII mode
0 = MII link indicator from host in MII PHY mode
1 = No link on port 3 MII PHY mode and enable bypass mode
DS00002335C-page 6
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
TABLE 2-1:
Pin
Number
25
26
27
28
SIGNALS (CONTINUED)
Pin
Name
SMRXDV3
SMRXD33/
REFCLKO_3
SMRXD32
SMRXD31
Type
Note 2-1
Description
Ipu/O
Switch MII/RMII receive data valid
Strap option: Force Duplex mode (P1DPX)
PU = Port 1 default to Full-Duplex mode if P1ANEN = 1 and auto-negotiation fails. Force port 1 in Full-Duplex mode if P1ANEN = 0.
PD = Port 1 default to Half-Duplex mode if P1ANEN = 1 and auto-negotiation fails. Force port 1 in Half-Duplex mode if P1ANEN = 0.
Ipu/O
MLL/FLL: Switch MII receive data bit 3
RLL: Output reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = Enable
PD = Disable
Ipu/O
Switch MII receive data bit 2
Strap option: Force the speed on port 2 (P2SPD)
PU = Force port 2 to 100BT if P2ANEN = 0
PD = Force port 2 to 10BT if P2ANEN = 0
Ipu/O
Switch MII/RMII receive data bit 1
Strap option: Force Duplex mode (P2DPX)
PU = Port 2 default to Full-Duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in Full-Duplex mode if P2ANEN = 0.
PD = Port 2 set to Half-Duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in Half-Duplex mode if P2ANEN = 0.
Switch MII/RMII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
PU = Always enable (force) port 2 flow control feature.
PD = Port 2 flow control feature enable is determined by auto-negotiation
result.
29
SMRXD30
Ipu/O
30
SMRXC3
I/O
31
GND
GND
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
Digital ground
32
VDDC
P
33
SCOL3
Ipu/O
Switch MII collision detect
34
SCRS3
Ipu/O
Switch MII carrier sense
35
INTRN
Opu
Interrupt
Active-low signal to host CPU to indicate an interrupt status bit is set when
lost link. Refer to register 187 and 188.
I/O
SPI Client mode/I2C Client mode: clock input
I2C Host mode: clock output
MIIM clock input
36
37
38
SCL_MDC
SDA_MDIO
SPIQ
1.8V digital core power input from VDDCO (pin 42)
Ipu/O
SPI Client mode: serial data input
I2C Host/Client mode: serial data input/output
MIIM: Data input/output
Note: An external pull-up is needed on this pin when it is in use.
Ipd/O
SPI Client mode: serial data output
Note: An external pull-up is needed on this pin when it is in use.
Strap option: Force flow control on port 1 (P1FFC)
PU = Always enable (force) port 1 flow control feature
PD = Port 1 flow control feature enable is determined by auto-negotiation
result.
2017-2021 Microchip Technology Inc.
DS00002335C-page 7
KSZ8863MLL/FLL/RLL
TABLE 2-1:
Pin
Number
39
SIGNALS (CONTINUED)
Pin
Name
SPISN
Type
Note 2-1
Ipd
Description
SPI Client mode: chip select (active-low)
When SPISN is high, KSZ8863MLL/FLL/RLL is deselected and SPIQ is
held in a high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
Note:
40
VDDIO
P
41
GND
GND
42
43
44
VDDCO
P1LED1
P1LED0
DS00002335C-page 8
P
An external pull-up is needed on this pin when using SPI or
MDC/MDIO-MIIM/SMI mode.
3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well decoupling capacitors
Digital ground
1.8V core power voltage output (internal 1.8V LDO regulator output)
This 1.8V output pin provides power to both VDDA_1.8 and VDDC input
pins.
Note:
Internally, 1.8V LDO regulator input comes from VDDIO. Do not
connect an external power supply to VDDCO pin. The ferrite
bead is requested between analog and digital 1.8V core power.
Ipu/O
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit [5:4])
Strap option: Force the speed on port 1 (P1SPD)
PU = Force port 1 to 100BT if P1ANEN = 0
PD = Force port 1 to 10BT if P1ANEN = 0
Ipd/O
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4])
Strap option: Enable auto-negotiation on port 1 (P1ANEN)
PU = Enable (better to pull up in design)
PD = Disable (default)
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
TABLE 2-1:
Pin
Number
SIGNALS (CONTINUED)
Pin
Name
Type
Note 2-1
Description
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit [5:4])
Strap option: Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4])
Strap option: Serial bus configuration
Serial bus configuration pins to select mode of access to KSZ8863MLL/
FLL/RLL internal registers.
45
P2LED1
Ipu/O
[P2LED1, P2LED0] = [0, 0] — I2C Host (EEPROM) mode
(If EEPROM is not detected, the KSZ8863MLL/FLL/RLL is configured with
the default values of its internal registers and the values of its strap-in
pins.)
Interface Signals
Type
Description
SPIQ
O
SCL_MDC
O
Not used (tri-stated)
SDA_MDIO
I/O
I2C data I/O
SPISN
I
Not used
I2C clock
[P2LED1, P2LED0] = [0, 1] — I2C Client mode
The external I2C Host drives the SCL_MDC clock.
The KSZ8863MLL/FLL/RLL device addresses are:
1011_1111
1011_1110
Interface Signals
46
P2LED0
Ipu/O
Type
Description
SPIQ
O
Not used (tri-stated)
SCL_MDC
I
SDA_MDIO
I/O
I2C data I/O
SPISN
I
Not used
I2C clock
[P2LED1, P2LED0] = [1, 0] — SPI Client mode
Interface Signals
Type
Description
SPIQ
O
SPI data out
SCL_MDC
I
SPI clock
SDA_MDIO
I
SPI data in
SPISN
I
SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM mode
In SMI mode, KSZ8863MLL/FLL/RLL provides access to all its internal 8bit registers through its SCL_MDC and SDA_MDIO pins.
In MIIM mode, KSZ8863MLL/FLL/RLL provides access to its 16-bit MIIM
registers through its SDC_MDC and SDA_MDIO pins.
47
48
RSTN
Ipu
FXSD1
2017-2021 Microchip Technology Inc.
I
Hardware reset pin (active-low)
MLL/RLL: No connection or connect to analog ground by 1 kΩ pull-down
resistor.
FLL: Fiber signal detect
DS00002335C-page 9
KSZ8863MLL/FLL/RLL
Note 2-1
P = power supply
GND = Ground
I = Input
O = Output
I/O = Bi-directional
Ipu/O = Input with internal pull-up during reset; output pin otherwise
Ipu = Input with internal pull-up
Ipd = Input with internal pull-down
Opu = Output with internal pull-up
Opd = Output with internal pull-down
Speed: Low (100BASE-TX), High (10BASE-T)
Full-Duplex: Low (full-duplex), High (half-duplex)
Activity: Toggle (transmit/receive activity)
Link: Low (link), High (no link)
DS00002335C-page 10
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
3.0
FUNCTIONAL DESCRIPTION
KSZ8863MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated layer 2
managed switch.
KSZ8863MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the
host processor has complete control of KSZ8863MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or I2C
bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
On the media side, KSZ8863MLL/FLL/RLL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design
more efficient and allow for lower power consumption and smaller chip die size.
3.1
3.1.1
Physical Layer Transceiver
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 1% 11.8 kΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
3.1.3
PLL CLOCK SYNTHESIZER
KSZ8863MLL/FLL/RLL generates 125 MHz, 62.5 MHz, and 31.25 MHz clocks for system timing. Internal clocks are
generated from an external 25 MHz or 50 MHz crystal or oscillator. KSZ8863RLL can generate a 50 MHz reference
clock for the RMII interface.
3.1.4
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
3.1.5
100BASE-FX OPERATION
The 100BASE-FX operation is similar to the 100BASE-TX operation with the differences being that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is
bypassed and auto MDI/MDI-X is disabled.
2017-2021 Microchip Technology Inc.
DS00002335C-page 11
KSZ8863MLL/FLL/RLL
3.1.6
100BASE-FX SIGNAL DETECTION
In 100BASE-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (signal detect) output pin. The fiber signal threshold can be selected by register 192 bit 6 for port 1. When FXSD is less than
the threshold, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the
fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD input pin is tied high
to force 100BASE-FX mode.
100BASE-FX signal detection is summarized in Table 3-1:
TABLE 3-1:
FX SIGNAL THRESHOLD
Register 192 Bit 7, Bit 6 (Port 1)
Fiber Signal Threshold at FXSD
1
2.0V
0
1.2V
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage
swing to match the FXSD pin’s input voltage threshold.
3.1.7
100BASE-FX FAR-END FAULT
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8863FLL detects a FEF when its FXSD input is below the Fiber Signal Threshold. When a FEF is detected,
KSZ8863FLL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period
between frames. By default, FEF is enabled.
3.1.8
10BASE-T TRANSMIT
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents
are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
3.1.9
10BASE-T RECEIVE
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into
clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to
prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit,
the PLL locks onto the incoming signal and KSZ8863MLL/FLL/RLL decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
3.1.10
MDI/MDI-X AUTO CROSSOVER
To eliminate the need for crossover cables between similar devices, KSZ8863MLL/FLL/RLL supports HP Auto MDI/
MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for
the KSZ8863MLL/FLL/RLL device. This feature is extremely useful when end users are unaware of cable types, and
also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the
port control registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are illustrated in Table 3-2.
TABLE 3-2:
MDI/MDI-X PIN DEFINITIONS
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
TD+
1
RD+
2
TD–
2
RD–
3
RD+
3
TD+
6
RD–
6
TD–
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KSZ8863MLL/FLL/RLL
3.1.10.1
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-1 depicts
a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
FIGURE 3-1:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Transmit Pair
Receive Pair
3
Straight
Cable
3
4
4
5
5
6
6
7
7
8
8
Receive Pair
Modular Connector
(RJ-45)
NIC
2017-2021 Microchip Technology Inc.
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
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KSZ8863MLL/FLL/RLL
3.1.10.2
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-2 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-2:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
3.1.11
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
AUTO-NEGOTIATION
KSZ8863MLL/FLL/RLL conforms to the auto-negotiation protocol defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In
auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not supported or the KSZ8863MLL/FLL/RLL link partner is forced to bypass auto-negotiation, KSZ8863MLL/FLL/RLL sets its
operating mode by observing the signal at its receiver. This is known as parallel detection, and allows KSZ8863MLL/
FLL/RLL to establish a link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol.
The link up process is shown in Figure 3-3.
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KSZ8863MLL/FLL/RLL
FIGURE 3-3:
AUTO-NEGOTIATION AND PARALLEL OPERATION
START AUTO-NEGOTIATION
FORCE LINK SETTING
NO
PARALLEL
OPERATION
YES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
ATTEMPT AUTONEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
3.1.12
LINKMD® CABLE DIAGNOSTICS
KSZ8863MLL/FLL/RLL supports LinkMD. The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the
cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault. Internal circuitry displays the TDR information in a user-readable digital format.
Cable diagnostics are only valid for copper connections and do not support fiber optic operation.
3.1.12.1
Access
LinkMD is initiated through accessing the PHY special control/status registers {26, 42} and the LinkMD result registers
{27, 43} for ports 1 and 2 respectively; and in conjunction with the port registers control 13 for ports 1 and 2 respectively
to disable Auto MDI/MDIX.
Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access.
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KSZ8863MLL/FLL/RLL
3.1.12.2
Usage
The following is a sample procedure for using LinkMD with registers {42, 43, 45} on port 2:
1.
Disable auto MDI/MDI-X by writing a ‘1’ to register 45, bit [2] to enable manual control over the differential pair
used to transmit the LinkMD pulse.
Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing.
Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is complete.
Read cable diagnostic test results in register 42, bits [6:5]. The results are as follows:
2.
3.
4.
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when KSZ8863MLL/FLL/RLL is unable to shut down the link partner. In this instance,
the test is not run because it is impossible for KSZ8863MLL/FLL/RLL to determine if the detected signal is a reflection
of the signal generated or a signal from another source.
5.
Get the distance to fault by concatenating register 42, bit [0] and register 43, bits [7:0]; and multiplying the result
by a constant of 0.4. The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
·
D Dis tan ce to cable fault in meters = 0.4 Register 26 bit [0] Register 27 bits [7:0]
Concatenated values of registers 42 and 43 are converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that
varies significantly from the norm.
3.2
Power Management
KSZ8863MLL/FLL/RLL supports enhanced power management feature in low power state with energy detection to
ensure low-power dissipation during device idle periods. There are five operation modes under the power management
function, which is controlled by two bits in register 195 (0xC3) and one bit in register 29 (0x1D), 45(0x2D) as shown
below:
•
•
•
•
•
Register 195 bit [1:0] = 00 Normal Operation mode
Register 195 bit [1:0] = 01 Energy Detect mode
Register 195 bit [1:0] = 10 Soft Power Down mode
Register 195 bit [1:0] = 11 Power Saving mode
Register 29, 45 bit 3 = 1 Port Based Power Down mode
Table 3-3 indicates all internal function blocks status under four different power management operation modes.
TABLE 3-3:
INTERNAL FUNCTION BLOCK STATUS
Power Management Operation Modes
KSZ8863MLL/FLL/RLL
Function Blocks
Normal Mode
Power Saving
Mode
Energy Detect
Mode
Soft Power Down
Mode
Internal PLL Clock
Enabled
Enabled
Disabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block
disabled
Energy detect at Rx
Disabled
MAC
Enabled
Enabled
Disabled
Disabled
Host Interface
Enabled
Enabled
Disabled
Disabled
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KSZ8863MLL/FLL/RLL
3.2.1
NORMAL OPERATION MODE
This is the default setting bit [1:0] = 00 in register 195 after the chip power-up or hardware reset. When KSZ8863MLL/
FLL/RLL is in this Normal Operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is
ready for CPU read or write.
During the Normal Operation mode, the host CPU can set the bit [1:0] in register 195 to transit the current Normal Operation mode to any one of the other three power management operation modes.
3.2.2
POWER SAVING MODE
The Power Saving mode is entered when Auto-Negotiation mode is enabled, cable is disconnected, and bit [1:0] = 11
in register 195 is set. When KSZ8863MLL/FLL/RLL is in this mode, all PLL clocks are enabled, MAC is on, all internal
register values are not changed, and the host interface is ready for CPU read or write. In this mode, it mainly controls
the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only
turns off the unused receiver block. Once the activity resumes due to plugging a cable or attempting by the far end to
establish a link, KSZ8863MLL/FLL/RLL can automatically enable the PHY power-up to normal power state from Power
Saving mode.
During the Power Saving mode, the host CPU can set bit [1:0] = 0 in register 195 to transit the current Power Saving
mode to any one of the other three power management operation modes.
3.2.3
ENERGY DETECT MODE
The Energy Detect mode provides a mechanism to save more power than in the Normal Operation mode when
KSZ8863MLL/FLL/RLL is not connected to an active link partner. In this mode, the device saves up to 87% of the power.
If the cable is not plugged, KSZ8863MLL/FLL/RLL can automatically enter a low-power state, that is, the Energy Detect
mode. In this mode, KSZ8863MLL/FLL/RLL keeps transmitting 120 ns width pulses at a rate of 1 pulse/second. Once
the activity resumes due to plugging a cable or attempting by the far end to establish a link, KSZ8863MLL/FLL/RLL can
automatically power up to normal power state in Energy Detect mode.
Energy Detect mode consists of two states: normal power state and low power state. In low power state, KSZ8863MLL/
FLL/RLL reduces the power consumption by disabling all circuitries except the energy detect circuitry of the receiver.
The Energy Detect mode is entered by setting bit [1:0] = 01 in register 195. When KSZ8863MLL/FLL/RLL is in this mode,
it monitors the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bit [7:0]
Go-Sleep time in register 196, KSZ8863MLL/FLL/RLL goes into a low power state. When KSZ8863MLL/FLL/RLL is in
low power state, it keeps monitoring the cable energy. Once the energy is detected from the cable, KSZ8863MLL/FLL/
RLL enters the normal power state. When KSZ8863MLL/FLL/RLL is in the normal power state, it can transmit or receive
packet from the cable.
It saves about 87% of the power when the MII interface is in PHY mode (register 53 bit 7 = 0), pin SMTXER3/MII_LINK_3
is connected to High, register 195 bit [1:0] = 01, bit 2 = 1(Disable PLL), and no cables are connected.
3.2.4
SOFT POWER DOWN MODE
The Soft Power Down mode is entered by setting bit [1:0] = 10 in register 195. When KSZ8863MLL/FLL/RLL is in this
mode, all PLL clocks are disabled, PHY and MAC are off, and all internal register values are not changed. When the
host set bit [1:0] = 00 in register 195, this device reverts from current Soft Power Down mode to Normal Operation mode.
3.2.5
PORT-BASED POWER DOWN MODE
In addition, KSZ8863MLL/FLL/RLL features a per-port power down mode. To save power, a PHY port that is not in use
can be powered down via the port control register 29 or 45 bit 3, or the MIIM PHY register. It saves about 15 mA per port.
3.3
3.3.1
MAC and Switch
ADDRESS LOOKUP
The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table
plus switching information.
KSZ8863MLL/FLL/RLL is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables,
which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses
it can learn.
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KSZ8863MLL/FLL/RLL
3.3.2
LEARNING
The internal lookup engine updates its table with a new entry if the following conditions are met:
• The received packet's Source Address (SA) does not exist in the lookup table.
• The received packet is good; the packet has no receiving errors and is of legal length.
The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
the last entry of the table is deleted to make room for the new entry.
3.3.3
MIGRATION
The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the table
accordingly. Migration happens when the following conditions are met:
• The received packet’s SA is in the table, but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length.
The lookup engine updates the existing record in the table with the new source port information.
3.3.4
AGING
The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record
from the table. The lookup engine constantly performs the aging process and continuously removes aging records. The
aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit [2].
3.3.5
FORWARDING
KSZ8863MLL/FLL/RLL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 3-4
shows stage one of the forwarding algorithm, where the search engine looks up the VLAN ID, static table, and dynamic
table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as
shown in Figure 3-5. The packet is sent to PTF2.
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KSZ8863MLL/FLL/RLL
FIGURE 3-4:
DESTINATION ADDRESS LOOKUP FLOW CHART, STAGE 1
Start
PTF1= NULL
NO
VLAN ID
Valid?
- Search VLAN table
- Ingress VLAN filtering
- Discard NPVID check
YES
Search complete.
Get PTF1 from
Static MAC Table
FOUND
Search Static
Table
This search is based on
DA or DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
Dynamic MAC
Table
FOUND
Dynamic Table
Search
This search is based on
DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
VLAN Table
PTF1
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DS00002335C-page 19
KSZ8863MLL/FLL/RLL
FIGURE 3-5:
DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2
PTF1
Spanning Tree
Process
- Check receiving port's receive enable bit
- Check destination port's transmit enable bit
- Check whether packets are special (BPDU
or specified)
IGMP Process
- Applied to MAC #1 and MAC #2
- MAC #3 is reserved for
microprocessor
- IGMP will be forwarded to port 3
Port Mirror
Process
- RX Mirror
- TX Mirror
- RX or TX Mirror
- RX and TX Mirror
Port VLAN
Membership
Check
PTF2
KSZ8863MLL/FLL/RLL does not forward the following packets:
1.
2.
3.
Error packets: These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal
size packet errors.
IEEE802.3x PAUSE frames: KSZ8863MLL/FLL/RLL intercepts these packets and performs full duplex flow control accordingly.
“Local” packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches
the port from which the packet originated, the packet is defined as local.
3.3.6
SWITCHING ENGINE
KSZ8863MLL/FLL/RLL features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32-kb internal frame buffer. This buffer pool is shared among all three ports. There are a
total of 256 buffers available. Each buffer is sized at 128 bytes.
3.3.7
MAC OPERATION
KSZ8863MLL/FLL/RLL strictly abides by IEEE 802.3 standards to maximize compatibility.
3.3.7.1
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
3.3.7.2
Back-Off Algorithm
KSZ8863MLL/FLL/RLL implements the IEEE 802.3 standard for the binary exponential back-off algorithm and the
optional “aggressive mode” back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration for register 4 (0x04) bit [3].
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KSZ8863MLL/FLL/RLL
3.3.7.3
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
3.3.7.4
Illegal Frames
KSZ8863MLL/FLL/RLL discards frames less than 64 bytes and can be programmed to accept frames up to 1518 bytes,
1536 bytes, or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since
KSZ8863MLL/FLL/RLL supports VLAN tags, the maximum sizing is adjusted when these tags are present.
3.3.7.5
Full-Duplex Flow Control
KSZ8863MLL/FLL/RLL supports the standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if KSZ8863MLL/FLL/RLL receives a pause control frame, KSZ8863MLL/FLL/RLL does not transmit
the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received
before the current timer expires, the timer is updated with the new value in the second pause frame. During this period
(while it is flow controlled), only flow control packets from KSZ8863MLL/FLL/RLL are transmitted.
On the transmit side, KSZ8863MLL/FLL/RLL has intelligent and efficient ways to determine when to invoke flow control.
The flow control is based on availability of the system resources, including available buffers, available transmit queues
and available receive queues.
KSZ8863MLL/FLL/RLL will flow control a port that has just received a packet if the destination port resource is busy.
KSZ8863MLL/FLL/RLL issues a flow control frame (XOFF) containing the maximum pause time defined by the IEEE
802.3x standard. Once the resource is freed up, KSZ8863MLL/FLL/RLL sends out the other flow control frame (XON)
with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to
prevent the flow control mechanism from being constantly activated and deactivated.
KSZ8863MLL/FLL/RLL flow controls all ports if the receive queue becomes full.
3.3.7.6
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as a full-duplex flow control. If backpressure is required, KSZ8863MLL/FLL/RLL sends preambles
to defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the IEEE 802.3 standard), after a certain time, KSZ8863MLL/
FLL/RLL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents
other stations from sending out packets, thus keeping other stations in a carrier sense deferred state. If the port has
packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets
are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is activated again
until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense
is generated immediately, thus reducing the chance of further collisions and maintaining carrier sense to prevent packet
reception.
To ensure that no packet is lost in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:
• Aggressive back-off (register 3 (0x03), bit [0])
• No excessive collision drop (register 4 (0x04), bit [3])
Note:
3.3.7.7
These bits are not set as defaults because it is not the IEEE standard.
Broadcast Storm Protection
KSZ8863MLL/FLL/RLL has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch
resources (bandwidth and available space in transmit queues) may be utilized. KSZ8863MLL/FLL/RLL can opt to
include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally and can
be enabled or disabled on a per-port basis. The rate is based on a 67 ms interval for 100BT and a 500 ms interval for
10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the
number of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting
is 0x63 (99 decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec × 67 ms/interval × 1% = 99 frames/interval (approx.) = 0x63
Note:
The 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8
bytes of preamble between two packets.
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KSZ8863MLL/FLL/RLL
3.3.7.8
Port Individual MAC Address and Source Port Filtering
KSZ8863MLL/FLL/RLL provides individual MAC address for port 1 and port 2. They can be set at registers 142-147 and
148-153. The packet is filtered if its source address matches the MAC address of port 1 or port 2 when register 21 and
37 bit 6 is set to 1, respectively. For example, the packet is dropped after it completes the loop of a ring network.
3.3.8
MII INTERFACE OPERATION
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by KSZ8863MLL/FLL is connected to the
device’s third MAC; the MII default is PHY mode and can be set to MAC mode with the register 53 bit 7. The interface
contains two distinct groups of signals: one for transmission and the other for reception. Table 3-4 describes the signals
used by the MII bus.
TABLE 3-4:
MII SIGNALS
PHY Mode Connections
MAC Mode Connections
KSZ8863MLL/FLL
PHY Signals
Pin Description
MTXEN
SMTXEN3
Transmit Enable
MTXEN
SMRXDV3
MTXER
SMTXER3
Transmit Error
MTXER
(NOT USED)
External MAC
Controller Signals
External PHY
Signals
KSZ8863MLL/FLL
MAC Signals
MTXD3
SMTXD33
Transmit Data Bit 3
MTXD3
SMRXD33
MTXD2
SMTXD32
Transmit Data Bit 2
MTXD2
SMRXD32
MTXD1
SMTXD31
Transmit Data Bit 1
MTXD1
SMRXD31
MTXD0
SMTXD30
Transmit Data Bit 0
MTXD0
SMRXD30
MTXC
SMTXC3
Transmit Clock
MTXC
SMRXC3
MCOL
SCOL3
Collision Detection
MCOL
SCOL3
MCRS
SCRS3
Carrier Sense
MCRS
SCRS3
MRXDV
SMRXDV3
Receive Data Valid
MRXDV
SMTXEN3
MRXER
(NOT USED)
Receive Error
MRXER
SMTXER3
MRXD3
SMRXD33
Receive Data Bit 3
MRXD3
SMTXD33
MRXD2
SMRXD32
Receive Data Bit 2
MRXD2
SMTXD32
MRXD1
SMRXD31
Receive Data Bit 1
MRXD1
SMTXD31
MRXD0
SMRXD30
Receive Data Bit 0
MRXD0
SMTXD30
MRXC
SMRXC3
Receive Clock
MRXC
SMTXC3
The MII operates in either PHY mode or MAC mode. The data interface is nibble-wide and runs at ¼ the network bit rate
(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For
half-duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
KSZ8863MLL/FLL does not provide the MRXER signal for PHY mode operation, and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Because the switch filters error frames, these MII error signals are not used by
KSZ8863MLL/FLL. So, for PHY mode operation, if the device interfacing with KSZ8863MLL/FLL has an MRXER input
pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with KSZ8863MLL/FLL has an
MTXER input pin, it also needs to be tied low.
KSZ8863MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status.
If the host is powered down, pin MII_LINK goes to high. In this case, no new ingress frames from port 1 or port 2 are
sent out through port 3, and the frames for port 3 already in packet memory are flushed out.
3.3.9
RMII INTERFACE OPERATION
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Ports 10 Mbps and 100 Mbps data rates
• Uses a single 50 MHz clock reference (provided internally or externally)
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KSZ8863MLL/FLL/RLL
• Provides independent 2-bit wide (di-bit) transmit and receive data paths
• Contains two distinct groups of signals: one for transmission and the other for reception
When EN_REFCLKO_3 is high, KSZ8863RLL outputs a 50 MHz in REFCLKO_3. Register 198 bit [3] is used to select
the internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8863RLL is
provided by KSZ8863RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the clock
provides to KSZ8863RLL via REFCLKI_3.
If KSZ8863RLL does not provide the reference clock, this 50 MHz reference clock with divide-by-2 (25 MHz) has to be
used in X1 pin instead of the 25 MHz crystal, since the clock skew of these two clock sources impacts the RMII timing
before Rev A3 part. The Rev A3 part can connect the external 50 MHz reference clock to X1 pin and SMTXC3/REFCLKI_3 pins directly with strap pins of pin 17 SMTXD33/EN_REFCLKO_3 and pin 18 SMTXD32 to be pulled down.
TABLE 3-5:
RMII CLOCK SETTING
Reg.
198
Bit [3]
Pin 17 SMTXD33/
EN_REFCLKO_3
Internal pull-up
Pin 18 SMTXD32
Internal pull-up
(For Rev A3)
0
0
(pull down by 1k)
0
(pull down by 1k)
External 50 MHz OSC input to EN_REFCLKO_3 = 0 to
SMTXC3 /REFCLKI_3 and X1 disable REFCLKO_3 for
pin directly
better EMI
1
0
(pull down by 1k)
50 MHz on X1 pin is as clock
source. REFCLKO_3 Output
is Feedback to REFCLKI_3
externally
EN_REFCLKO_3 = 1 to
enable REFCLKO_3
1
25 MHz on X1 pin is as clock
source.
REFCLKO_3 Output is
connected to REFCLKI_3
externally
EN_REFCLKO_3 = 1 to
enable REFCLKO_3
0
EN_REFCLKO_3 = 1 to
50 MHz on X1 pin, 50 MHz
RMII Clock goes to SMTXC3/ enable REFCLKO_3 and no
feedback to REFCLKI_3
REFCLKI_3 internally.
REFCLKI_3 can be pulled
down by a resistor.
1
EN_REFCLKO_3 = 1 to
25 MHz on X1 pin, 50 MHz
RMII Clock goes to SMTXC3/ enable REFCLKO_3 and no
feedback to REFCLKI_3
REFCLKI_3 internally.
REFCLKI_3 can be pulled
down by a resistor.
0
0
1
1
1
1
1
Clock Source
Note
The RMII provided by KSZ8863RLL is connected to the device’s third MAC and complies with the RMII Specification.
Table 3-6 describes the signals that the RMII bus is using. Refer to RMII Specification for full detail on the signal description.
TABLE 3-6:
RMII SIGNAL DESCRIPTION
RMII Signal Name
Direction (with
respect to PHY)
Direction (with
respect to MAC)
RMII Signal
Description
KSZ8863RLL RMII
Signal Direction
REFCLKI_3 (input)
REF_CLK
Input
Input or Output
Synchronous 50 MHz
clock reference for
receive, transmit, and
control interface
CRS_DV
Output
Input
Carrier sense/
Receive data valid
SMRXDV3 (output)
RXD1
Output
Input
Receive data bit 1
SMRXD31 (output)
RXD0
Output
Input
Receive data bit 0
SMRXD30 (output)
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TABLE 3-6:
RMII SIGNAL DESCRIPTION (CONTINUED)
RMII Signal Name
Direction (with
respect to PHY)
Direction (with
respect to MAC)
RMII Signal
Description
KSZ8863RLL RMII
Signal Direction
TX_EN
Input
TXD1
Input
Output
Transmit enable
SMTXEN3 (input)
Output
Transmit data bit 1
SMTXD31 (input)
TXD0
Input
Output
Transmit data bit 0
SMTXD30 (input)
RX_ER
Output
Input (not required)
Receive error
(not used)
—
SMTXER3 (input)
Connects to RX_ER
signal of RMII PHY
device
—
—
—
KSZ8863RLL filters error frames and, thus, does not implement the RX_ER output signal. To detect error frames from
RMII PHY devices, the SMTXER3 input signal of KSZ8863RLL is connected to the RXER output signal of the RMII PHY
device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, the MII signals (SMTXD3 [3:2] and SMTXER3) can be floating if they are used as default strap options.
The KSZ8863RLL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8863RLL
devices to be connected back-to-back. Table 3-7 shows the KSZ8863RLL RMII pin connections with an external RMII
PHY and an external RMII MAC, such as another KSZ8863RLL device.
TABLE 3-7:
RMII SIGNAL CONNECTIONS
KSZ8863RLL
PHY-MAC Connections
External PHY
Signals
KSZ8863RLL MAC
Signals
REF_CLK
REFCLKI_3
TX_EN
3.3.10
Pin Descriptions
KSZ8863RLL
MAC-MAC Connections
KSZ8863RLL MAC
Signals
External MAC
Signals
Reference Clock
REFCLKI_3
REF_CLK
SMRXDV3
Carrier sense/
Receive data valid
SMRXDV3
CRS_DV
TXD1
SMRXD31
Receive data bit 1
SMRXD31
RXD1
TXD0
SMRXD30
Receive data bit 0
SMRXD30
RXD0
CRS_DV
SMTXEN3
Transmit enable
SMTXEN3
TX_EN
RXD1
SMTXD31
Transmit data bit 1
SMTXD31
TXD1
RXD0
SMTXD30
Transmit data bit 0
SMTXD30
TXD0
RX_ER
SMTXER3
Receive error
(not used)
(not used)
MII MANAGEMENT (MIIM) INTERFACE
KSZ8863MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of
KSZ8863MLL/FLL/RLL. An external device with MDC/MDIO capability is used to read the PHY status or configure the
PHY settings. For further detail on the MIIM interface, see Clause 22.2.4.5 of the IEEE 802.3u Specification, and refer
to 802.3 section 22.3.4 for the timing.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC)
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8863MLL/FLL/RLL device
• Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM registers [29, 31]
The MIIM interface can operate up to a maximum clock speed of 5 MHz.
Table 3-8 depicts the MII Management Interface frame format.
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KSZ8863MLL/FLL/RLL
TABLE 3-8:
MII MANAGEMENT FRAME FORMAT
Preamble
Start of
Frame
Read/
Write OP
Code
Read
32 1’s
01
10
AAAAA
Write
32 1’s
01
01
AAAAA
3.3.11
PHY
REG
Address Address
Bits [4:0] Bits [4:0]
TA
Data Bits[15:0]
Idle
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
SERIAL MANAGEMENT INTERFACE (SMI)
The SMI is the KSZ8863MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8863MLL/FLL/RLL
configuration registers. This interface allows an external device to completely monitor and control the states of
KSZ8863MLL/FLL/RLL.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC)
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8863MLL/FLL/RLL device
• Access to all KSZ8863MLL/FLL/RLL configuration registers. Register access includes the Global, Port, and
Advanced Control Registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and
custom MIIM registers [29, 31]
Table 3-9 depicts the SMI frame format.
TABLE 3-9:
SERIAL MANAGEMENT INTERFACE (SMI) FRAME FORMAT
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
REG
Address Address
Bits [4:0] Bits [4:0]
Read
32 1’s
01
00
1xRRR
Write
32 1’s
01
00
0xRRR
TA
Data Bits [15:0]
Idle
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
RRRRR
10
xxxx_xxxx_DDDD_DDDD
Z
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit [3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read or write operations.
To access the KSZ8873MLL/FLL/RLL registers 0-196 (0x00 – 0xC6), the following applies:
• PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
• TA bits [1:0] are ‘Z0’ that means the processor MDIO pin is changed to input Hi-Z from Output mode and the following ‘0’ is the read response from the device.
• TA bits [1:0] are set to ‘10’ when write registers.
• Registers are 8 data bits wide.
- For read operation, data bits [15:8] are read back as 0’s.
- For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
The SMI register access is the same as the MIIM register access, except for the register access requirements presented
in this section.
3.4
3.4.1
Advanced Switch Functions
BYPASS MODE
KSZ8863MLL/FLL/RLL also offers a Bypass mode that enables system-level power saving. When the CPU (connected
to port 3) enters a Power Saving mode of power down or Sleeping mode, the CPU can control pin 24 SMTXER3/
MII_LINK_3, which can be tied high so that KSZ8863MLL/FLL/RLL detects this change and automatically switches to
the Bypass mode. In this mode, the switch function between port 1 and port 2 is sustained. The packets with DA to port
3 are dropped and bypass the internal buffer memory, making the buffer memory more efficient for data transfer between
port 1 and port 2.
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KSZ8863MLL/FLL/RLL
3.4.2
IEEE 802.1Q VLAN SUPPORT
KSZ8863MLL/FLL/RLL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8863MLL/FLL/RLL provides a 16-entries VLAN table that converts the 12-bits VLAN ID (VID) to the 4-bits
Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is
used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is valid.
If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for
further lookup. The FID and Destination Address (FID+DA) are used to determine the destination port. The FID and
Source Address (FID+SA) are used for address learning.
TABLE 3-10:
FID+DA LOOKUP IN VLAN MODE
DA Found in
Static MAC
Table?
Use FID Flag?
FID Match?
FID+DA Found
in Dynamic
MAC Table?
Action
No
Don’t care
Don’t care
No
Broadcast to the membership ports defined
in the VLAN Table bits [18:16]
No
Don’t care
Don’t care
Yes
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Yes
0
Don’t care
Don’t care
Send to the destination port(s) defined in
the Static MAC Address Table bits [50:48]
Yes
1
No
No
Broadcast to the membership ports defined
in the VLAN Table bits [18:16]
Yes
1
No
Yes
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Yes
1
Yes
Don’t care
Send to the destination port(s) defined in
the Static MAC Address Table bits [50:48]
TABLE 3-11:
FID+SA LOOKUP IN VLAN MODE
FID+SA Found in Dynamic MAC Table?
Action
No
Learn and add FID+SA to the Dynamic MAC Address Table
Yes
Update time stamp
Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets,” are also supported by
KSZ8863MLL/FLL/RLL. These features can be set on a per-port basis and are defined in register 18, 34, and 50 for
ports 1, 2, and 3, respectively.
3.4.3
QOS PRIORITY SUPPORT
KSZ8863MLL/FLL/RLL provides Quality of Service (QoS) for applications such as VoIP and video conferencing. Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest
priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32, and 48 is used to enable split transmit
queues for ports 1, 2, and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets have
equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four
priority queues. This global option is set and explained in bit [3] of register 5.
3.4.4
PORT-BASED PRIORITY
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received
at the high-priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. Bits [4:3] of registers 16, 32, and 48 are used to enable port-based priority for ports
1, 2, and 3, respectively.
3.4.5
802.1P-BASED PRIORITY
For 802.1p-based priority, KSZ8863MLL/FLL/RLL examines the ingress (incoming) packets to determine whether they
are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping”
value, as specified by the registers 12 and 13. The “priority mapping” value is programmable.
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Figure 3-6 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
FIGURE 3-6:
8
6
6
2
2
2
Preamble
DA
SA
VPID
TCI
length
Bits
802.1q VLAN Tag
16
Tagged Packet Type
(8100 for Ethernet)
3
1
802.1p
CFI
Bytes
802.1P PRIORITY FIELD FORMAT
46-1500
LLC
Data
4
FCS
12
VLAN ID
The 802.1p-based priority is enabled with bit [5] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively.
KSZ8863MLL/FLL/RLL provides the option to insert or remove the header of the priority tagged frame at each individual
egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field
(TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of the port registers control 0 and the register 194 to select which source port (ingress
port) PVID can be inserted on the egress port for ports 1, 2, and 3, respectively. At the egress port, untagged packets
are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36}, and
{51,52} for ports 1, 2, and 3, respectively; and the source port VID has to be inserted at selected egress ports by bit [5:0]
of register 194. KSZ8863MLL/FLL/RLL does not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively. At the egress port, tagged
packets will have their 802.1Q VLAN Tags removed. KSZ8863MLL/FLL/RLL does not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
The 802.1p Priority Field Re-mapping is a QoS feature that allows KSZ8863MLL/FLL/RLL to set the “User Priority Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field
of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
3.4.6
DIFFSERV-BASED PRIORITY
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully
decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine
priority.
3.5
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable,” “receive
enable,” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. Table 3-12 shows
the port setting and software actions taken for each of the five spanning tree states.
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KSZ8863MLL/FLL/RLL
TABLE 3-12:
SPANNING TREE STATES
State
Port Setting
Software Action
Disable State
The port should not forward or receive any packets. Learning is disabled.
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The processor should not send any packets to the port. The
switch may still send specific packets to the processor (packets that match some entries in the “static MAC table” with
“overriding bit” set) and the processor should discard those
packets. Address learning is disabled on the port in this state.
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The processor should not send any packets to the port(s) in
this state. The processor should program the “Static MAC
table” with the entries that it needs to receive (for example,
BPDU packets). The “overriding” bit should also be set so that
the switch will forward those specific packets to the processor.
Address learning is disabled on the port in this state.
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets).
The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor
may send packets to the port(s) in this state. See Section 3.7,
"Tail Tagging Mode" for details. Address learning is disabled
on the port in this state.
“transmit enable = 0,
receive enable = 0,
learning disable = 0”
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets).
The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor
may send packets to the port(s) in this state. See Section 3.7,
"Tail Tagging Mode" for details. Address learning is enabled
on the port in this state.
“transmit enable = 1,
receive enable = 1,
learning disable = 0”
The processor programs the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets).
The “overriding” bit is set so that the switch forwards those
specific packets to the processor. The processor can send
packets to the port(s) in this state. See Section 3.7, "Tail Tagging Mode" for details. Address learning is enabled on the port
in this state.
Blocking State
Only packets to the processor are forwarded.
Learning is disabled.
Listening State
Only packets to and from
the processor are forwarded. Learning is disabled.
Learning State
Only packets to and from
the processor are forwarded. Learning is
enabled.
Forwarding State
Packets are forwarded
and received normally.
Learning is enabled.
3.6
Rapid Spanning Tree Support
There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP:
• Discarding ports do not participate in the active topology and do not learn MAC addresses.
- Discarding state: The state includes three states of the disable, blocking, and listening of STP.
- Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1"
- Software action: The processor should not send any packets to the port. The switch may still send specific
packets to the processor (packets that match some entries in the static table with “overriding bit” set), and the
processor should discard those packets. When disabling the port’s learning capability (learning disable=’1’),
set the register 2 bit 5 and bit 4 flushes rapidly the port related entries in the dynamic MAC table and static
MAC table.
Note:
The processor is connected to port 3 via the MII interface. Address learning is disabled on the port in this
state.
• Ports in Learning states learn MAC addresses, but do not forward user traffic.
- Learning state: Only packets to and from the processor are forwarded. Learning is enabled.
- Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0”
- Software action: The processor should program the static MAC table with the entries that it needs to receive
(for example, BPDU packets). The “overriding” bit should be set so that the switch forwards those specific
packets to the processor. The processor may send packets to the port(s) in this state, see Section 3.7, "Tail
Tagging Mode" for details. Address learning is enabled on the port in this state.
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• Ports in Forwarding states fully participate in both data forwarding and MAC learning.
- Forwarding state: Packets are forwarded and received normally. Learning is enabled.
- Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0”
- Software action: The processor should program the static MAC table with the entries that it needs to receive
(for example, BPDU packets). The “overriding” bit should be set so that the switch forwards those specific
packets to the processor. The processor may send packets to the port(s) in this state, see Section 3.7, "Tail
Tagging Mode" for details. Address learning is enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs, which are similar to STP Configuration BPDUs with the exception of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.
3.7
Tail Tagging Mode
The Tail Tag is only seen and used by the port 3 interface, which should be connected to a processor. It is an effective
way to retrieve the ingress port information for spanning tree protocol IGMP snooping and other applications. Bit 1 and
bit 0 in the one byte tail tagging is used to indicate the source or destination port in port 3. Bit 3 and bit 2 are used for
the priority setting of the ingress frame in port 3. Other bits are not used. The Tail Tag feature is enabled by setting register 3 bit 6.
FIGURE 3-7:
Bytes
TABLE 3-13:
TAIL TAG FRAME FORMAT
8
6
6
2
2
2
Preamble
DA
SA
VPID
TCI
length
46-1500
LLC
Data
1
4
Tail Tag
FCS
TAIL TAG RULES
Ingress to Port 3 (Host to KSZ8863)
Bit [1,0]
Destination Port
0,0
Normal (address lookup)
0,1
Port 1
1,0
Port 2
1,1
Port 1 and 2
Bit [3,2]
Frame Priority
0,0
Priority 0
0,1
Priority 1
1,0
Priority 2
1,1
Priority 3
Egress from Port 3 (KSZ8863 to Host)
Bit [0]
Source Port
0
Port 1
1
Port 2
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3.8
IGMP Support
For Internet Group Management Protocol (IGMP) support in layer 2, KSZ8863MLL/FLL/RLL provides two components:
3.8.1
IGMP SNOOPING
KSZ8863MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are
identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol
version number = 0x2.
3.8.2
IGMP SEND BACK TO THE SUBSCRIBED PORT
Once the host responds to the received IGMP packet, the host should knows the original IGMP ingress port and send
back the IGMP packet to this port only. Otherwise this IGMP packet is broadcasted to all ports to downgrade the performance.
Enabling the Tail Tag mode, the host will know the IGMP packet received port from tail tag bits [0] and can send back
the response IGMP packet to this subscribed port by setting the bits [1,0] in the tail tag. Enable “Tail Tag mode” by setting
register 3 bit 6. The tail tag is removed automatically when the IGMP packet is sent out from the subscribed port.
3.9
Port Mirroring Support
KSZ8863MLL/FLL/RLL supports “Port Mirroring” as follows:
• “Receive only” mirror on a port
- All packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed as the
“receive sniff” and port 3 is programmed as the “sniffer port.” A packet received on port 1 is destined to port 2
after the internal lookup. KSZ8863MLL/FLL/RLL forwards the packet to both port 2 and port 3. KSZ8863MLL/
FLL/RLL can also optionally forward “bad” received packets to the “sniffer port.”
• “Transmit only” mirror on a port
- All packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed as the
“transmit sniff” and port 3 is programmed as the “sniffer port.” A packet received on port 2 is destined to port 1
after the internal lookup. KSZ8863MLL/FLL/RLL forwards the packet to both port 1 and port 3.
• “Receive and transmit” mirror on two ports
- All packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND”
feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed as the “receive sniff,” port 2 is programmed as the “transmit sniff,” and port 3 is programmed as the “sniffer port.” A packet received on port 1 is
destined to port 2 after the internal lookup. KSZ8863MLL/FLL/RLL forwards the packet to both port 2 and port
3.
Multiple ports can be selected as the “receive sniff” or the “transmit sniff.” In addition, any port can be selected as the
“sniffer port.” All these per-port features can be selected through registers 17, 33, and 49 for ports 1, 2, and 3, respectively.
3.10
Rate Limiting Support
KSZ8863MLL/FLL/RLL provides a fine resolution hardware rate limiting from 64 kbps to 99 Mbps. The rate step is
64 kbps when the rate range is from 64 kbps to 960 kbps, and 1 Mbps for 1 Mbps to 100 Mbps (100BT) or to 10 Mbps
(10BT) (refer to Data Rate Limit Table). The rate limit is independent on the “receive side” and on the “transmit side” on
a per-port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the
data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control
Registers. The size of each frame has options to include a minimum IFG (Inter Frame Gap) or a Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8863MLL/FLL/RLL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. KSZ8863MLL/FLL/RLL counts the data rate from those selected type of frames.
Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per-frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
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If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
is triggered. As a result of congestion, the actual egress rate may be dominated by flow control or dropping at the ingress
end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
3.11
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded
in the static table, it is also not learned in the dynamic MAC table. KSZ8863MLL/FLL/RLL is then configured with the
option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in
register 14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP).
3.12
Configuration Interface
KSZ8863MLL/FLL/RLL can operate as both a managed switch and an unmanaged switch.
In Unmanaged mode, KSZ8863MLL/FLL/RLL is typically programmed using an EEPROM. If no EEPROM is present,
KSZ8863MLL/FLL/RLL is configured using its default register settings. Some default settings are configured via strapin pin options. The strap-in pins are indicated in the “Pin Description and I/O Assignment” table.
3.12.1
I2C HOST SERIAL BUS CONFIGURATION
With an additional I2C (“2-wire”) EEPROM, KSZ8863MLL/FLL/RLL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For the KSZ8863MLL/FLL/RLL I2C Host configuration, the EEPROM stores the configuration data for register 0 to register 198 (as defined in the KSZ8863MLL/FLL/RLL register map) with the exception of the “Read Only” status registers.
After the deassertion of reset, KSZ8863MLL/FLL/RLL sequentially reads in the configuration data for all 199 registers,
starting from register 0.
FIGURE 3-8:
EEPROM CONFIGURATION TIMING DIAGRAM
RST_N
....
SCL
....
SDA
....
tprgm
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