KSZ8893FQL
Single-Chip 3-Port Switch with Fiber Support
Features
• Integrated 3-Port 10/100 Ethernet Switch
- Three MACs and Two PHYs Fully Compliant
with IEEE 802.3u Standard
- Non-Blocking Switch Fabric Ensures Fast
Packet Delivery by Utilizing an 1K MAC
Address Lookup Table and a Store-and-Forward
Architecture
- Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
- Half-Duplex Back Pressure Flow Control
- HP Auto MDI-X for Reliable Detection of and
Correction for Straight-Through and Crossover
Cables with Disable and Enable Option
- Microchip LINKMD® TDR-Based Cable Diagnostics Permit Identification of Faulty Copper
Cabling
- 100BASE-FX, 100BASE-SX, and 10BASE-FL
Fiber Support on Port 1
- MII Interface Supports Both MAC Mode and
PHY Mode
- RMII Interface Support with External 50 MHz
System Clock
- 7-Wire Serial Network Interface (SNI) Support
for Legacy MAC
- Comprehensive LED Indicator Support for Link,
Activity, Full-/Half-Duplex and 10/100 Speed
• Fiber Support
- Integrated LED Driver and Post Amplifier for
10BASE-FL and 100BASE-SX Optical Modules
• TTC TS-1000 OAM
- Supports OAM Sub-Layer which Conforms to
TS-1000 V2 Specification from Telecommunication Technology Committee (TTC)
- Sends and Receives OAM Frames to Center or
Terminal Side
- Loopback Mode to Support Loopback Packet
from Center Side to Terminal Side
- Far-End Fault Detection with Disable and
Enable
- Link Transparency to Indicate Link Down from
Link Partner
- Unique User Defined Register (UDR) Feature
Brings OAM to Low Cost/Complexity Nodes
• Comprehensive Configuration Register Access
- SMI, SPI, and I2C Management Interfaces to All
8-bit Internal Registers
- MII Management (MIIM) Interface to PHY Registers
- I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch
Mode
2019 - 2021 Microchip Technology Inc. and its subsidiaries
•
•
•
•
•
•
- Control Registers Configurable on the Fly (PortPriority, 802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
- Per Port, 802.1p, and DiffServ-Based
- Re-Mapping of 802.1p Priority Field Per Port
Basis
- Four Priority Levels
Advanced Switch Features
- IEEE 802.1q VLAN Support for Up to 16 Groups
(Full Range of VLAN IDs)
- VLAN ID Tag/Untag Options, Per Port Basis
- IEEE 802.1p/q Tag Insertion or Removal on a
Per Port Basis (Egress)
- Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
- Broadcast Storm Protection with Percent Control (Global and Per Port Basis)
- IEEE 802.1d Spanning Tree Protocol Support
- Special Tagging Mode to Inform the Processor
which Ingress Port Receives the Packet
- IGMP Snooping (IPv4) and MLD Snooping
(IPv6) Support for Multicast Packet Filtering
- MAC Filtering Function to Forward Unknown
Unicast Packets to Specified Port
- Double-Tagging Support
Low Latency Support
- Repeater Mode
Switch Monitoring Features
- Port Mirroring/Monitoring/Sniffing: Ingress and/
or Egress Traffic to Any Port or MII
- MIB Counters for Fully Compliant Statistics
Gathering, 34 MIB Counters Per Port
- Loopback Modes for Remote Diagnostic of Failure
Low Power Dissipation
- Full-Chip Hardware Power-Down (Register
Configuration Not Saved)
- Per Port Based Software Power-Save on PHY
(Idle Link Detection, Register Configuration Preserved)
- Voltages: Core 1.2V, I/O and Transceiver 3.3V
Available in a 128-Pin PQFP, Lead-Free Package
Applications
• Media Conversion Modules
- 10BASE-FL to/from 10BASE-T
- 100BASE-SX to/from 100BASE-TX
- 100BASE-FX to/from 100BASE-TX
• FTTx Managed/Unmanaged Media Converters
• Fiber Broadband Gateways
DS00003038C-page 1
KSZ8893FQL
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00003038C-page 2
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 17
4.0 Register Descriptions .................................................................................................................................................................... 46
5.0 Operational Characteristics ........................................................................................................................................................... 90
6.0 Electrical Characteristics ............................................................................................................................................................... 91
7.0 Timing Specifications .................................................................................................................................................................... 93
8.0 Reset Circuit ............................................................................................................................................................................... 101
9.0 Selection of Isolation Transformers ............................................................................................................................................ 102
10.0 Package Outline ........................................................................................................................................................................ 103
Appendix A: Data Sheet Revision History ......................................................................................................................................... 105
The Microchip Web Site .................................................................................................................................................................... 106
Customer Change Notification Service ............................................................................................................................................. 106
Customer Support ............................................................................................................................................................................. 106
Product Identification System ........................................................................................................................................................... 107
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 3
KSZ8893FQL
1.0
INTRODUCTION
1.1
General Description
The KSZ8893FQL, a highly integrated single-chip 3-port Fast Ethernet switch is designed for applications with fiber support such as media converter. It provides two 10/100 transceivers with patented mixed-signal low-power technology,
three media access control (MAC) units, a high-speed non-blocking switch fabric, a Layer-2 managed switch and TS1000 OAM (Operations, Administration and Management) V2 in a compact solution. Backwards compatible to the TS1000 (2002) specification, TS-1000 V2 is an OAM sub-layer that provides communication between CO (central office)
and CPE (customer premises equipment).
In fiber mode, one PHY unit can be configurable to 100BASE-FX, 100BASE-SX, or 10BASE-FL fiber for conversion to
10BASE-T and 100BASE-TX copper. A fiber LED driver and post amplifier are also included for 10BASE-FL and
100BASE-SX applications.
In copper mode, both PHY units support 10BASE-T and 100BASE-TX with HP Auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables, and LINKMD® TDR-based cable diagnostics for identification
of faulty cabling.
The high-performance switching engine features an extensive feature set that includes programmable rate limiting, tag/
port-based VLAN, 4 priority class, RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and
emerging Fast Ethernet applications.
The KSZ8893FQL comes in a lead-free package.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
TO CONTROL
REGISTERS
HP AUTO
MDIX
10/100
T/TX
PHY 2
RMII/MII/
SNI
O
A
M
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
SNI
SPI
SPI
MIIM
CONTROL
REGISTERS
SMI
FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY
HP AUTO
MDIX
10/100
FL/FX/SX
PHY 1
1K LOOK-UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
MIB
COUNTERS
EEPROM
INTERFACE
I2C
P1 LED[3:0]
P2 LED[3:0]
DS00003038C-page 4
LED
DRIVERS
STRAP IN
CONFIGURATION
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
2.0
PIN DESCRIPTION AND CONFIGURATION
128-PIN PQFP ASSIGNMENT, (TOP VIEW)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
UNUSED
PS0
PS1
SPIS_N
SDA
SCL
SPIQ
MDIO
MDC
UNUSED
UNUSED
VDDC
DGND
SCONF0
SCONF1
SCRS
SCOL
SMRXD0
SMRXD1
SMRXD2
SMRXD3
SMRXDV
SMRXC
VDDIO
DGND
SMTXC / REFCLK
SMTXER
SMTXD0
SMTXD1
SMTXD2
SMTXD3
SMTXEN
LEDSEL0
UNUSED
UNUSED
RST_N
X2
X1
FIGURE 2-1:
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
AGND
VDDAP
AGND
ISET
TEST2
TEST1
AGND
VDDA
TXP2
TXM2
AGND
RXP2
RXM2
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
FXSD1
VDDA
AGND
MUX2
MUX1
AGND
P1LED2
P1LED1
P1LED0
P2LED2
P2LED1
P2LED0
DGND
VDDIO
MCHS
MCCs
PDD#
ADVFC
P2ANEN
P2SPD
P2DPX
P2FFC
P1FST
P1CRCD
P1LPBM
P2LED3
DGND
VDDC
LEDSEL1
NC
P1LED3
RMII_EN
HWPOVR
P2MDIXDIS
P2MDIX
P1ANEN
P1SPD
P1DPX
P1FFC
ML_EN
DIAGF
PWRDN
AGND
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
UNUSED
UNUSED
UNUSED
DGND
VDDIO
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
DGND
VDDC
UNUSED
UNUSED
UNUSED
TESTEN
SCANEN
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 5
KSZ8893FQL
TABLE 2-1:
Pin
Number
SIGNALS
Pin
Name
Type
Note
2-1
Description
Port 1 LED indicators (active-low)
(applies to all modes of operation, except Repeater Mode)
—
1
P1LED2
IPU/O
[LEDSEL1, LEDSEL0]
[0,0] Default
[0,1]
P1LED3
—
—
P1LED2
Link/Activity
100Link/Activity
P1LED1
Full-Duplex/Col
10Link/Activity
P1LED0
Speed
Full-Duplex
—
—
2
P1LED1
IPU/O
[LEDSEL1, LEDSEL0]
[1,0]
[1,1]
P1LED3
Activity
—
P1LED2
Link
—
P1LED1
Full-Duplex/Col
—
P1LED0
Speed
—
Link/Act, 100Link/Activity, 10Link/Activity:
Low (link), High (no link), Toggle (transmit/receive activity)
Full-Duplex/Col:
Low (full-duplex), High (half-duplex), Toggles (collision)
Speed:
Low (100BASE-TX), High (10BASE-T)
Full-Duplex:
Low (full-duplex), High (half-duplex)
Activity:
Toggles (transmit/receive activity)
Link:
Low (link), High (no link)
Repeater Mode (only)
DS00003038C-page 6
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
TABLE 2-1:
Pin
Number
SIGNALS (CONTINUED)
Pin
Name
Type
Note
2-1
Description
—
3
P1LED0
IPU/O
[LEDSEL1, LEDSEL0]
[0,0]
P1LED3
RPT_COL
P1LED2
RPT_LINK3/RX
P1LED1
RPT_LINK2/RX
P1LED0
RPT_LINK1/RX
RPT_COL:
Low (collision)
RPT_LINK#/RX (# = port):
Low (link), High (no link), Toggles (receive activity)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P1LED3 is pin 25.
During reset, P1LED[2:0] are inputs for internal testing.
Port 2 LED indicators (active-low)
(applies to all modes of operation, except Repeater Mode)
—
4
P2LED2
IPU/O
[LEDSEL1, LEDSEL0]
[0,0] Default
[0,1]
P2LED3
—
—
P2LED2
Link/Activity
100Link/Activity
P2LED1
Full-Duplex/Col
10Link/Activity
P2LED0
Speed
Full-Duplex
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 7
KSZ8893FQL
TABLE 2-1:
Pin
Number
SIGNALS (CONTINUED)
Pin
Name
Type
Note
2-1
Description
—
—
5
P2LED1
IPU/O
[LEDSEL1, LEDSEL0]
[1,0]
[1,1]
P2LED3
Activity
—
P2LED2
Link
—
P2LED1
Full-Duplex/Col
—
P2LED0
Speed
—
Link/Act, 100Link/Activity, 10Link/Activity:
Low (link), High (no link), Toggle (transmit/receive activity)
Full-Duplex/Col:
Low (full-duplex), High (half-duplex), Toggles (collision)
Speed:
Low (100BASE-TX), High (10BASE-T)
Full-Duplex:
Low (full-duplex), High (half-duplex)
Activity:
Toggles (transmit/receive activity)
Link:
Low (link), High (no link)
Repeater Mode (only)
—
6
P2LED0
IPU/O
[LEDSEL1, LEDSEL0]
[0,0]
P2LED3
RPT_COL
P2LED2
RPT_LINK3/RX
P2LED1
RPT_LINK2/RX
P2LED0
RPT_LINK1/RX
RPT_COL:
Low (collision)
RPT_LINK#/RX (# = port):
Low (link), High (no link), Toggles (receive activity)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P2LED3 is pin 25.
During reset, P2LED[2:0] are inputs for internal testing.
7
DGND
GND
Digital ground.
8
VDDIO
P
3.3V digital VDD
DS00003038C-page 8
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
TABLE 2-1:
Pin
Number
SIGNALS (CONTINUED)
Pin
Name
Type
Note
2-1
Description
KSZ8893FQL operating modes (defined below):
(MCHS, MCCS)
9
10
MCHS
MCCS
IPD
Description
(0, 0)
Normal 3 port switch mode (3 MAC + 2 PHY)
MC mode is disabled.
Port 1 is either Fiber or UTP.
Port 2 is UTP.
Port 3 (MII) is enabled.
(0, 1)
Center MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber and has Center MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
(1, 0)
Terminal MC mode (2 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber and has Terminal MC enabled.
Port 2 is UTP.
Port 3 (MII) is disabled.
(1, 1)
Terminal MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 Fiber and has Terminal MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
IPD
Power Down Detect
1 = Normal operation.
0 = Power down detected.
11
PDD#
IPU
12
ADVFC
IPU
1 = Advertise the switch’s flow control capability via auto-negotiation.
0 = Will not advertise the switch’s flow control capability via auto-negotiation.
13
P2ANEN
IPU
1 = Enable auto-negotiation on port 2.
0 = Disable auto-negotiation on port 2.
14
P2SPD
IPD
1 = Force port 2 to 100BT if P2ANEN = 0.
0 = Force port 2 to 10BT if P2ANEN = 0.
In Terminal MC mode (pin MCHS is ‘1’), a high to low transition to this pin will
cause port 1 (fiber) to generate and send out an “Indicate Terminal MC Condition” OAM frame with the S0 status bit set to ‘1’.
15
P2DPX
IPD
1 = Port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in full duplex mode if P2ANEN = 0.
0 = Port 2 default to half duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in half duplex mode if P2ANEN = 0.
16
P2FFC
IPD
1 = Always enable (force) port 2 flow control feature.
0 = Port 2 flow control feature enable is determine by the auto-negotiation
result.
17
P1FST
OPU
1 = Normal function.
0 = MC in loopback mode or MC abnormal conditions occur.
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 9
KSZ8893FQL
TABLE 2-1:
Pin
Number
SIGNALS (CONTINUED)
Pin
Name
Type
Note
2-1
Description
18
P1LCRCD
IPD
In MC loopback mode,
1 = Drop OAM frames and Ethernet frames with the following errors – CRS,
undersize, oversize. Loopback Ethernet frames with only good CRC and valid
length.
0 = Drop OAM frames only. Loopback all Ethernet frames including those with
errors.
19
P1LPBM
IPD
1 = Perform MC loopback at PHY of port 1.
0 = Perform MC loopback at MAC of port 2
20
P2LED3
OPD
Port 2 LED indicator
Note: An external 1 kΩ pull-down is needed on this pin if it is connected to an
LED. The 1 kΩ resistor will not turn ON the LED.
See description in pin 4.
21
DGND
GND
Digital ground.
22
VDDC/
VOUT_1V2
P
23
LEDSEL1
IPD
24
NC
O
25
26
P1LED3
RMII_EN
1.2V digital VDD
Provides VOUT_1V2 to KSZ8893FQL’s input power pins: VDDAP (pin 63),
VDDC (pins 91 and 123), and VDDA (pins 38, 43, and 57). It is recommended
the pin should be connected to 3.3V power rail by a 100Ω resistor for the
internal LDO application.
LED display mode select.
See description in pins 1 and 4.
No connect
OPD
Port 1 LED indicator
Note: An external 1 kΩ pull-down is needed on this pin if it is connected to an
LED. The 1 kΩ resistor will not turn ON the LED.
See description in pin 1.
OPD
Strap pin for RMII Mode
1 = Enable
0 = Disable
After reset, this pin has no meaning and is a no connect.
27
HWPOVR
IPD
Hardware pin overwrite
1 = Enable: All strap-in pin configurations are overwritten by the EEPROM
configuration data, except for P2ANEN (pin 13), P2SPD (pin 14), P2DPX (pin
15) and ML_EN (pin 34). After reset, the pin state for P2ANEN, P2SPD and
P2DPX is polled by the KSZ8893FQL.
0 = Disable: All strap-in pin configurations are overwritten by the EEPROM
configuration data.
28
P2MDIXDIS
IPD
Port 2 Auto MDI/MDI-X
PD (default) = enable
PU = disable
29
P2MDIX
IPD
Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled.
PD (default) = MDI-X (transmit on TXP2/TXM2 pins)
PU = MDI, (transmit on RXP2/RXM2 pins)
30
P1ANEN
IPU
1 = Enable auto-negotiation on port 1
0 = Disable auto-negotiation on port 1
DS00003038C-page 10
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
31
P1SPD
IPD
1 = Force port 1 to 100BT if P1ANEN = 0
0 = Force port 1 to 10BT if P1ANEN = 0
Description
32
P1DPX
IPD
1 = Port 1 default to full-duplex mode if P1ANEN = 1 and auto-negotiation
fails. Force port 1 in full-duplex mode if P1ANEN = 0.
0 = Port 1 default to half-duplex mode if P1ANEN = 1 and auto-negotiation
fails. Force port 1 in half-duplex mode if P1ANEN = 0.
33
P1FFC
IPD
1 = Always enable (force) port 1 flow control feature
0 = Port 1 flow control feature enable is determined by auto-negotiation result.
34
ML_EN
IPD
1 = Enable missing link
0 = Disable missing link
35
DIAGF
IPD
1 = Diagnostic fail
0 = Diagnostic normal
36
PWRDN
IPU
Chip power down input (active-low)
1 = Normal operation
0 = The chip is powered down
37
AGND
GND
Analog ground
38
VDDA
P
39
AGND
GND
40
MUX1
I
No connect
41
MUX2
I
10BASE-FL/100BASE-SX Enable. Active-low.
42
AGND
GND
43
VDDA
P
1.2V analog VDD
44
FXSD1
I
Fiber signal detect/factory test pin
45
RXP1
I/O
Physical receive or transmit signal (+ differential)
46
RXM1
I/O
Physical receive or transmit signal (– differential)
47
AGND
GND
48
TXP1
I/O
Physical transmit or receive signal (+ differential)
49
TXM1
I/O
Physical transmit or receive signal (– differential)
50
VDDATX
P
3.3V analog VDD
51
VDDARX
P
3.3V analog VDD
52
RXM2
I/O
Physical receive or transmit signal (– differential)
53
RXP2
I/O
Physical receive or transmit signal (+ differential)
54
AGND
GND
55
TXM2
I/O
Physical transmit or receive signal (– differential)
56
TXP2
I/O
Physical transmit or receive signal (+ differential)
1.2V analog VDD
Analog ground
Analog ground
Analog ground
Analog ground
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 11
KSZ8893FQL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
57
VDDA
P
1.2 analog VDD
58
AGND
GND
Analog ground
59
TEST1
I
Factory test pin – float for normal operation
60
TEST2
I
Factory test pin – float for normal operation
61
ISET
O
Set physical transmit output current
Pull-down this pin with a 3.01 kΩ 1% resistor to ground.
62
AGND
GND
63
VDDAP
P
64
AGND
GND
65
X1
I
66
X2
O
67
RST_N
IPU
68
UNUSED
I
Unused pin – externally pull down for normal operation
69
UNUSED
I
Unused pin – externally pull down for normal operation
70
LEDSEL0
I
LED display mode select
See description in pins 1 and 4.
71
SMTXEN
I
Switch MII transmit enable
72
SMTXD3
I
Switch MII transmit data bit 3
73
SMTXD2
I
Switch MII transmit data bit 2
74
SMTXD1
I
Switch MII transmit data bit 1
75
SMTXD0
I
Switch MII transmit data bit 0
76
SMTXER
I
Switch MII transmit error
77
SMTXC/
REFCLK
I/O
78
DGND
GND
79
VDDIO
P
80
SMRXC
I/O
DS00003038C-page 12
Description
Analog ground
1.2V analog VDD for PLL
Analog ground
25 MHz crystal/oscillator clock connections
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a
3.3V tolerant oscillator and X2 is no connected.
Note: Clock is ±50 ppm for both crystal and oscillator.
Hardware Reset (active-low)
Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII mode
Reference Clock (RMII mode only)
Input for 50 MHz ±50 ppm system clock
Note: In RMII mode, pin X1 is pulled up to VDDIO supply with a 10 kΩ resistor
and pin X2 is a no connect.
Digital ground
3.3V digital VDD
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
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KSZ8893FQL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
81
SMRXDV
O
82
83
84
SMRXD3
SMRXD2
SMRXD1
Description
Switch MII receive data valid I/O
IPD/O
Switch MII receive data bit 3
Strap option: switch MII full-duplex flow control
PD (default) = disable
PU = enable
IPD/O
Switch MII receive data bit 2
Strap option: switch MII is in
PD (default) = full-duplex mode
PU = half-duplex mode
IPD/O
Switch MII receive data bit 1
Strap option: Switch MII is in
PD (default) = 100 Mbps mode
PU = 10 Mbps mode
85
SMRXD0
I/O
Switch MII receive data bit 0
Strap option: switch will accept packet size up to
PD = 1536 bytes (inclusive)
PU = 1522 bytes (tagged), 1518 bytes (untagged)
86
SCOL
I/O
Switch MII collision detect
87
SCRS
I/O
Switch MII carrier sense
Switch MII interface configuration
88
SCONF1
I
89
SCONF0
(SCONF1, SCONF0)
Description
(0,0)
Disable, outputs tri-stated
(0,1)
PHY mode MII
(1,0)
MAC mode MII
(1,1)
PHY mode SNI
90
DGND
GND
91
VDDC
P
1.2V digital VDD
92
UNUSED
I
Unused pin - externally pull down for normal operation
93
UNUSED
I
Unused pin - externally pull down for normal operation
94
MDC
I
MII management interface: clock input
95
MDIO
I/O
MII management interface: data input/output
Note: an external pull-up is needed on this pin when it is in use
96
SPIQ
O
SPI slave mode: serial data output
See description in pins 100 and 101
Note: an external pull-up is needed on this pin when it is in use
I/O
SPI slave mode/ I2C slave mode: clock input
I2C master/slave mode: clock output
See description in pins 100 and 101
97
SCL
Digital core ground
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DS00003038C-page 13
KSZ8893FQL
TABLE 2-1:
Pin
Number
98
99
SIGNALS (CONTINUED)
Pin
Name
SDA
SPIS_N
Type
Note
2-1
I/O
I
Description
SPI slave mode: serial data input
I2C master/slave mode: serial data input/output
See description in pins 100 and 101
Note: an external pull-up is needed on this pin when it is in use
SPI slave mode: chip select (active low)
When SPIS _N is high, the KSZ8893FQL is deselected and SPIQ is held in
high impedance state
A high-to-low transition is used to initiate SPI data transfer
See description in pins 100 and 101
Note: an external pull-up is needed on this pin when it is in use
Serial bus configuration pins to select mode of access to KSZ8893FQL internal registers.
[PS1, PS0] = [0, 0] — I2C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8893FQL will be configured with the
default values of its internal registers and the values of its strap-in pins.)
Interface Signals
100
PS1
I
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
O
I2C clock
SDA
I/O
I2C data I/O
SPIS_N
I
Not used
[PS1, PS0] = [0, 1] — I2C slave mode
The external I2C master will drive the SCL clock.
The KSZ8893FQL device addresses are:
1011_1111
1011_1110
Interface Signals
SPIQ
DS00003038C-page 14
Type
O
Description
Not used (tri-stated)
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
TABLE 2-1:
Pin
Number
SIGNALS (CONTINUED)
Pin
Name
Type
Note
2-1
Description
SCL
I
SDA
I/O
SPIS_N
I
I2C clock
I2C data I/O
Not used
[PS1, PS0] = [1, 0] — SPI slave mode
Interface Signals
101
PS0
I
Type
Description
SPIQ
O
SPI data out
SCL
I
SPI clock
SDA
I
SPI data in
SPIS_N
I
SPI chip select
[PS1, PS0] = [1, 1] – SMI-mode
In this mode, the KSZ8893FQL provides access to all its internal 8-bit registers through its MDC and MDIO pins.
Note:
When (PS1, PS0) does not equal (1,1), the KSZ8893FQL provides access to
its 16-bit MIIM registers through its MDC and MDIO pins.
102
UNUSED
I
Unused pin – externally pull up for normal operation
103
UNUSED
I
Unused pin – externally pull up for normal operation
104
UNUSED
I
Unused pin – externally pull up for normal operation
105
UNUSED
I
Unused pin – externally pull up for normal operation
106
DGND
GND
107
VDDIO
P
3.3V digital VDD
108
UNUSED
I
Unused pin – externally pull up for normal operation
109
UNUSED
I
Unused pin – externally pull up for normal operation
110
UNUSED
I
Unused pin – externally pull down for normal operation
111
UNUSED
I
Unused pin – externally pull down for normal operation
112
UNUSED
I
Unused pin – externally pull down for normal operation
113
UNUSED
I
Unused pin – externally pull down for normal operation
114
UNUSED
I
Unused pin – externally pull down for normal operation
115
UNUSED
I
Unused pin – externally pull down for normal operation
116
UNUSED
I
Unused pin – externally pull down for normal operation
117
UNUSED
I
Unused pin – externally pull down for normal operation
118
UNUSED
I
Unused pin – externally pull down for normal operation
119
UNUSED
I
Unused pin – externally pull down for normal operation
Digital ground
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 15
KSZ8893FQL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
120
UNUSED
I
Unused pin – externally pull down for normal operation
121
UNUSED
I
Unused pin – externally pull up for normal operation
122
DGND
GND
123
VDDC
P
1.2V digital VDD
124
UNUSED
I
Unused pin – externally pull down for normal operation
125
UNUSED
I
Unused pin – externally pull down for normal operation
126
UNUSED
I
Unused pin – externally pull down for normal operation
127
TESTEN
IPD
Scan Test Enable
For normal operation, pull down this pin to ground.
128
SCANEN
IPD
Scan Test Scan Mux Enable
For normal operation, pull down this pin to ground.
Note 2-1
Description
Digital ground
P = power supply; GND = ground; I = input; O = output
I/O = bi-directional
Ipu/O = Input with internal pull-up during reset; output pin otherwise.
Ipu = Input with internal pull-up.
Ipd = Input with internal pull-down.
Opu = Output with internal pull-up.
Opd = Output with internal pull-down.
Speed: Low (100BASE-TX), High (10BASE-T)
Full-Duplex: Low (full-duplex), High (half-duplex)
Activity: Toggle (transmit/receive activity)
Link: Low (link), High (no link)
DS00003038C-page 16
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
3.0
FUNCTIONAL DESCRIPTION
The KSZ8893FQL is a single-chip Fast Ethernet media converter. It contains two 10/100 physical layer transceivers and
three Media Access Control (MAC) units with an integrated Layer 2 managed switch.
On the media side, the KSZ8893FQL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports. In Media
Converter (MC) applications, PHY port 1 is the fiber port and supports 100BASE-FX, 100BASE-SX, and 10BASE-FL.
The KSZ8893FQL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host
processor has complete control of the KSZ8893FQL via the SMI interface, MIIM interface, SPI bus, or I2C bus. An
unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
3.1
3.1.1
Media Conversion
TS-1000 OAM OPERATION
The KSZ8893FQL implements Japan’s TTC (Telecommunication Technology Committee) TS-1000 version 2, OAM sublayer, which resides between RS and PCS layer in the IEEE 802.3 Standard. The OAM sub-layer is provided in
100BASE-FX mode and is used by the KSZ8893FQL to send and receive OAM frames. These special frames are used
for the transmission of OAM (Operations, Administration, Management) information between center MC and terminal
MC. Key TS-1000 OAM features include:
•
•
•
•
•
Private point-to-point communication between two TS-1000 compliant devices
96 bits (12 bytes) frames for the transmission of OAM information between center MC and terminal MC
Transmission of MC status between center MC and terminal MC
Automatic generation of OAM frame to inform MC link partner of local MC’s status change
Transmission of vendor code and model number information between center MC and terminal MC for device identification
• Inquisition of terminal MC status by center MC
• Remote loop back for diagnostic by center MC
3.1.1.1
OAM Frame Format
The TS-1000 OAM (Operations, Administration, and Management) Frame Format is shown in Table 3-1.
TABLE 3-1:
TS-1000 OAM FRAME FORMAT
Bit
F0 - F7
Command
Description
Preamble
1010 1010
C0
Conservation Delimiter
0
C1
Direction Delimiter
0 = Upstream (from terminal MC to center MC)
1 = Downstream (from center MC to terminal
MC)
C2 - C3
Configuration Delimiter
10 = Request
11 = Response
01 = Indication
00 = Reserved
C4 - C7
Version
0000
C8 - C15
Control Signal
1000 0000 = Start loopback test
0000 0000 = Stop loopback test
0100 0000 = Notify status
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 17
KSZ8893FQL
TABLE 3-1:
TS-1000 OAM FRAME FORMAT (CONTINUED)
Bit
Command
Description
S0
Power
0 = Normal operation
1 = Power down
S1
Optical
0 = Normal
1 = Abnormal
S2
UTP Link
0 = Link up
1 = Link down
S3
MC
0 = Normal
1 = Brake
S4
Way for Information
0 = Use conservation frame
1 = Use FEFI
S5
Loop Mode
0 = Normal operation
1 = In loop mode
S6
Terminal MC Link Option
0 = Center side MC have to set always “0”
1 = Terminal side MC have to set always “1”
Terminal MC Link Speed 1
This bit must be set “0”
Terminal MC Link Speed 2
0 = 10 Mbps
1 = 100 Mbps
These bits have to be set “0”, if S2 is “1”
(Center side MC have to set always “0”)
S9
Terminal MC Link Duplex
0 = Half-Duplex
1 = Full-Duplex
This bit have to be set “0”, if S2 is “1”
(Center side MC have to set always “0”)
S10
0 = Not Support Auto-Negotiation
Terminal MC Auto-Negotiation Capa1 = Support Auto-Negotiation
bility
(Center side MC have to set always “0”)
S11
Multiple Link Partner
0 = One link partner on UTP side
1 = Multiple link partner on UTP side
Reserved
All bits must be set “0”
M0 - M23
Vendor Code
—
M24 - M47
Model Number
—
FCS
Create FCS at this sub-layer (C0 - M47)
Status
S7
S8
S12 - S15
E0 - E7
3.1.1.2
Media Converter Modes
TS-1000 Media Converter (MC) modes are selected and configured using hardware pins: MCHS and MCCS. The MC
modes are summarized in Table 3-2 and are also shown in the Pin Description and Configuration section.
TABLE 3-2:
TS-1000 MEDIA CONVERTER MODE SELECTION
(MCHS, MCCS)
Description
(0, 0)
Normal 3 port switch mode (3 MAC + 2 PHY)
MC mode is disabled.
Port 1 is either Fiber or UTP.
Port 2 is UTP.
Port 3 (MII) is enabled.
(0, 1)
Center MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber & has Center MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
DS00003038C-page 18
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
TABLE 3-2:
TS-1000 MEDIA CONVERTER MODE SELECTION (CONTINUED)
(MCHS, MCCS)
Description
(1, 0)
Terminal MC mode (2 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber & has Terminal MC enabled.
Port 2 is UTP.
Port 3 (MII) is disabled.
(1, 1)
Terminal MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber & has Terminal MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
Figure 3-1 shows two KSZ8893FQLs connected in a typical center MC to terminal MC application.
FIGURE 3-1:
TYPICAL TS-1000 MEDIA CONVERTER APPLICATION
CO
CPE
Center MC
UTP
Terminal MC
FIBER
KSZ8893FQL
KSZ8893FQL
DATA
OAM
IFG
Fault
LED
option
DATA
CPU
IFG
UTP
EEPROM
or CPU
option
KSZ8893FQL CONFIGURATION:
CPU via SMI, SPI, or I2C bus
EEPROM via I2C
3.1.1.3
MC Loopback Operation
TS-1000 MC loopback operation is initiated and enabled by the center MC. The terminal MC provides the loopback path
to return the loopback packet back to the center MC. The KSZ8893FQL in terminal MC mode provides three loopback
path options:
Port 1 OPT
• Receive loopback packet from center MC at RXP1/RXM1 input pins of port 1 (fiber).
• Turn around loopback packet at PMD/PMA of port 1 (fiber).
• Transmit loopback packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber).
Port 2 MAC
• Receive loopback packet from center MC at RXP1/RXM1 input pins of port 1 (fiber).
• Turn around loopback packet at MAC of port 2 (copper).
• Transmit loopback packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber).
Port 2 UTP
• Receive loopback packet from center MC at RXP1/RXM1 input pins of port 1 (fiber).
• Turn around loopback packet at PMD/PMA of port 2 (copper).
• Transmit loopback packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber).
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DS00003038C-page 19
KSZ8893FQL
FIGURE 3-2:
KSZ8893FQL MC LOOPBACK PATHS
RX+/RX-
Fiber
Port
TX+/TX-
PMD/PMA
PCS
OAM MC
MAC
SWITCH
MAC
PCS
UTP
Port
3.1.1.4
PMD/PMA
Dedicated TS-1000 Registers and Pins
The KSZ8893FQL provides 32 dedicated registers to support TS-1000 OAM communication in center MC and terminal
MC modes. The TS-1000 MC registers are located at 64 to 95 (0x40 to 0x5F), and provide the following functions:
•
•
•
•
•
•
•
•
•
PHY address configuration
Center MC and Terminal MC configuration
OAM frame selection and execution
MC loopback setup
MC loopback counters for CRC error, timeout, good packet
Remote command access
Counters for valid MC packet transmitted and received
MC (local) - status, vendor code, and model number
Link Partner (remote) - status, vendor code, and model number
Table 3-3 lists the dedicated KSZ8893FQL pins used in center MC and terminal MC modes.
TABLE 3-3:
DEDICATED TS-1000 PINS
Pin
Signal Name
Type
9
MCHS
IPD
10
MCCS
IPD
DS00003038C-page 20
Description
Selects center MC and terminal MC modes. See “Media Converter
Modes” section for details.
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
TABLE 3-3:
Pin
DEDICATED TS-1000 PINS (CONTINUED)
Signal Name
Type
Description
11
PDD#
IPU
Power-Down Detect: Used by terminal MC to detect a power-down condition or indicate a failure has occurred.
1 = Normal operation
0 = Power down detected
After detecting a high-to-low transition on this pin, the KSZ8893FQL
then sends out an “Indicate Terminal MC Condition” OAM frame with
the S0 status bit set to ‘1’ to inform the center MC that a power down
condition or failure has occurred on the terminal MC side.
If this pin is implemented, PWRDN (pin 36) needs to be deasserted
(pulled up).
17
P1FST
OPU
Drives low to indicate fault conditions (far-end fault detected, link partner’s fiber or UTP port down), or MC loopback mode. This pin has 8 mA
drive and can directly drive a LED.
IPD
Used by terminal MC for MC loopback – strap-in pin to select:
1 = Drop OAM frames and Ethernet frames with the following errors:
CRC, undersize, oversize. Loopback Ethernet frames with only good
CRC and valid length.
0 = Drop OAM frames only. Loopback all Ethernet frames including
those with errors.
18
P1CRCD
19
P1LPBM
IPD
Used by terminal MC for MC loopback – strap-in pin to select:
1 = Perform MC loopback at PHY of port 1
0 = Perform MC loopback at MAC of port 2
See also register 11 (0x0B) bits[3:2].
34
ML_EN
IPD
Used by terminal MC for Missing Link Indication – strap-in pin to select:
1 = Enable Missing Link feature
0 = Disable Missing Link feature
IPD
Used by terminal MC for Diagnostic status:
1 = Diagnostic fail
0 = Diagnostic normal
After detecting a change of state on this pin, the KSZ8893FQL sends
out an “Indicate Terminal MC Condition” OAM frame with the S3 status
bit set to the state of this pin to inform the center MC that a diagnostic
status change has occurred on the terminal MC side.
35
3.1.2
DIAGF
10BASE-FL OPERATION
10BASE-FL operation is supported on port 1 of the KSZ8893FQL. It conforms to clause 15 and 18 of the IEEE802.3
Standard for 10BASe-FL fiber operation. Refer to the Standard for details.
In a typical application, the KSZ8893FQL provides media conversion from 10BASE-FL fiber on port 1 to 10BASE-T copper on port 2. Alternatively, port 2 can be substituted with port 3 to directly connect to an external MAC.
3.1.2.1
Physical Interface
For 10BASE-FL operation, port 1 interfaces with an external fiber module to drive 850 nm fiber optic links. The interface
connections between the KSZ8893FQL and fiber module are single-ended (common mode). 10BASE-FL signal transmission and reception are done on TXM1 (pin 49) and RXM1 (pin 46), respectively. Refer to Microchip’s reference schematic for recommended interface circuit and termination.
3.1.2.2
Enabling 10BASE-FL Mode
To enable 10BASE-FL mode, tie FXSD1 (pin 44) high to +3.3V and MUX2 (pin 41) low-to-ground. Port 1 should also be
configured with auto-negotiation disabled, forced to 10 Mbps for the speed, and set to either half- or full-duplex. Optionally, flow control can be enabled to send out PAUSE frames in full-duplex mode.
The 10BASE-FL settings use the same strapping pins, MIIM registers and port registers as 10BASE-T copper. These
settings are summarized in Table 3-4.
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DS00003038C-page 21
KSZ8893FQL
TABLE 3-4:
10BASE-FL CONFIGURATION
10BASE-FL Setting
Strapping Pin
MIIM Register
Port Register
Auto-Negotiation
(disable only)
P1ANEN (30)
Reg. 0, Bit[12]
Reg. 28, Bit[7]
Speed (10 Mbps only)
P1SPD (31)
Reg. 0, Bit[13]
Reg. 28, Bit[6]
Duplex (half or full)
P1DPX (32)
Reg. 0, Bit[8]
Reg. 28, Bit[5]
Forced Flow Control
(option)
P1FFC (33)
—
Reg. 18, Bit[4]
3.1.3
100BASE-SX OPERATION
100BASE-SX operation is supported on port 1 of the KSZ8893FQL. It conforms to the TIA/EIA-785 Standard for
100BASE-SX fiber operation. Refer to the Standard for details.
In a typical application, the KSZ8893FQL provides media conversion from 100BASE-SX fiber on port 1 to 100BASE-TX
copper on port 2. Alternatively, port 2 can be substituted with port 3 to directly connect to an external MAC.
3.1.3.1
Physical Interface
For 100BASE-SX operation, port 1 interfaces with an external fiber module to drive 850 nm fiber optic links. The interface connections between the KSZ8893FQL and fiber module are single-ended (common mode). 100BASE-SX signal
transmission and reception are done on TXM1 (pin 49) and RXM1 (pin 46), respectively. Refer to Microchip’s reference
schematic for recommended interface circuit and termination.
3.1.3.2
Enabling 100BASE-SX Mode
To enable 100BASE-SX mode, tie FXSD1 (pin 44) high to +3.3V and MUX2 (pin 41) low-to-ground. Port 1 should also
be configured with auto-negotiation disabled, forced to 100 Mbps for the speed, and set to either half- or full-duplex.
Optionally, flow control can be enabled to send out PAUSE frames in full-duplex mode.
The 100BASE-SX settings use the same strapping pins, MIIM registers and port registers as 100BASE-TX copper.
These settings are summarized in Table 3-5.
TABLE 3-5:
100BASE-SX CONFIGURATION
100BASE-SX Settings
Strapping Pin
MIIM Register
Port Register
Auto-Negotiation
(disable only)
P1ANEN (30)
Reg. 0, Bit[12]
Reg. 28, Bit[7]
Speed (100 Mbps only)
P1SPD (31)
Reg. 0, Bit[13]
Reg. 28, Bit[6]
Duplex (half or full)
P1DPX (32)
Reg. 0, Bit[8]
Reg. 28, Bit[5]
Forced Flow Control
(option)
P1FFC (33)
—
Reg. 18, Bit[4]
3.2
3.2.1
Physical Layer Transceiver
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 1% 3.01 kΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.2.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
DS00003038C-page 22
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
3.2.3
PLL CLOCK SYNTHESIZER
The KSZ8893FQL generates 125 MHz, 31.25 MHz, 25 MHz, and 10 MHz clocks for system timing. Internal clocks are
generated from an external 25 MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an
external 50 MHz oscillator or system clock.
3.2.4
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
3.2.5
100BASE-FX OPERATION
100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/de-scrambler
and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed and
auto MDI/MDI-X is disabled.
3.2.6
100BASE-FX SIGNAL DETECTION
In 100BASE-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver SD
(signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V. When FXSD1
is between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD1 is over 2.2V,
the fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied high
to force 100BASE-FX mode.
100BASE-FX signal detection is summarized in Table 3-6.
TABLE 3-6:
FX AND TX MODE SELECTION
FXSD1 Input Voltage
Mode
Less than 0.2V
TX mode
Greater than 1V, but less than 1.8V
FX mode
No signal detected
Far-end fault generated
FX mode
Signal detected
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage
swing to match the FXSD1 pin’s input voltage threshold.
Greater than 2.2V
3.2.7
100BASE-FX FAR-END FAULT
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8893FQL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the KSZ8893FQL
signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between
frames.
By default, FEF is enabled. FEF can be disabled through register setting.
2019 - 2021 Microchip Technology Inc. and its subsidiaries
DS00003038C-page 23
KSZ8893FQL
3.2.8
10BASE-T TRANSMIT
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents
are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
3.2.9
10BASE-T RECEIVE
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into
clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to
prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit,
the PLL locks onto the incoming signal and the KSZ8893FQL decodes a data frame. The receiver clock is maintained
active during idle periods in between data reception.
3.2.10
FIBER LED DRIVER
The device provides a current mode fiber LED driver. The edge enhanced current mode does not require any output
wave shaping. The drive current of the fiber LED driver is programmable through register 138 (0x8A) bit[7:6]. The programmable current values are as follows:
TABLE 3-7:
3.2.11
PROGRAMMABLE CURRENT VALUES FOR FIBER LED DRIVER
Reg. 138 (0x8A) bit[7:6]
Current Value
00
60 mA
01
80 mA
10
90 mA
11
40 mA
POST AMPLIFIER
The KSZ8893FQL also includes a post amplifier. The post amplifier is intended for interfacing the output of the preamplifier of the PIN diode module. The minimum sensitivity of the post amplifier is 2.5 mVRMS.
3.2.12
POWER MANAGEMENT
The KSZ8893FQL features a per-port power down mode. To save power, a PHY port that is not in use can be powered
down via port control register or via MIIM PHY register.
In addition, there is a full chip power down mode. When activated, the entire chip is powered down.
3.2.13
MDI/MDI-X AUTO CROSSOVER
To eliminate the need for crossover cables between similar devices, the KSZ8893FQL offers HP Auto MDI/MDI-X and
Microchip Auto MDI/MDI-X crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for
the KSZ8893FQL device. This feature is extremely useful when end users are unaware of cable types, and also, saves
on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control
registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are illustrated in Table 3-8.
TABLE 3-8:
MDI/MDI-X PIN DEFINITIONS
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
TD+
1
RD+
2
TD–
2
RD–
3
RD+
3
TD+
6
RD–
6
TD–
DS00003038C-page 24
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
3.2.13.1
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-3 depicts
a typical straight cable connection between a NIC card (MDI) and a switch or hub (MDI-X).
FIGURE 3-3:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Transmit Pair
Receive Pair
3
Straight
Cable
3
4
4
5
5
6
6
7
7
8
8
Receive Pair
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
3.2.13.2
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-4 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-4:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
2019 - 2021 Microchip Technology Inc. and its subsidiaries
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
DS00003038C-page 25
KSZ8893FQL
3.2.14
AUTO-NEGOTIATION
The KSZ8893FQL conforms to the auto-negotiation protocol, as defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In
auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not supported or the KSZ8893FQL link partner is forced to bypass auto-negotiation, then the KSZ8893FQL sets its operating
mode by observing the signal at its receiver. This is known as parallel detection and allows the KSZ8893FQL to establish
link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol.
The link up process is shown in Figure 3-5.
FIGURE 3-5:
AUTO-NEGOTIATION AND PARALLEL OPERATION
START AUTO-NEGOTIATION
FORCE LINK SETTING
NO
PARALLEL
OPERATION
YES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
ATTEMPT AUTONEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
3.2.15
LINKMD® CABLE DIAGNOSTICS
The LINKMD® feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches.
LINKMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with
maximum distance of 200m and accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable digital format.
Note that cable diagnostics are only valid for copper connections and do not support fiber optic operation.
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KSZ8893FQL
3.2.15.1
Access
LINKMD is initiated by accessing registers {26,27} and {42,43}, the LINKMD Control/Status registers, for ports 1 and 2,
respectively; and in conjunction with registers 29 and 45, Port Control Register 13, for ports 1 and 2, respectively.
Alternatively, the MIIM PHY registers 0 and 29 can be used for LINKMD access.
3.2.15.2
Usage
The following is a sample procedure for using LINKMD with registers {26,27,29} on port 1.
1.
2.
3.
4.
Disable auto MDI/MDI-X by writing a ‘1’ to register 29, bit [2] to enable manual control over the differential pair
used to transmit the LINKMD pulse.
Start cable diagnostic test by writing a ‘1’ to register 26, bit [4]. This enable bit is self-clearing.
Wait (poll) for register 26, bit [4] to return a ‘0’, indicating cable diagnostic test is complete.
Read cable diagnostic test results in register 26, bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the KSZ8893FQL is unable to shut down the link partner. In this instance, the
test is not run, because it would be impossible for the KSZ8893FQL to determine if the detected signal is a reflection of
the signal generated or a signal from another source.
5.
Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0]; and multiplying the result by
a constant of 0.4. The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
·
D Dis tan ce to cable fault in meters = 0.4 Register 26 Bit [0], Register 27 Bits [7:0]
Concatenated values of registers 26 and 27 are converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that
varies significantly from the norm.
For port 2 and for the MIIM PHY registers, LINKMD usage is similar.
3.3
3.3.1
MAC and Switch
ADDRESS LOOKUP
The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table
plus switching information.
The KSZ8893FQL is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables, which
depending upon the operating environment and probabilities, may not guarantee the absolute number of addresses it
can learn.
3.3.2
LEARNING
The internal lookup engine updates its table with a new entry if the following conditions are met:
• The received packet's source address (SA) does not exist in the lookup table.
• The received packet is good; the packet has no receiving errors and is of legal length.
The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
the last entry of the table is deleted to make room for the new entry.
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KSZ8893FQL
3.3.3
MIGRATION
The internal lookup engine also monitors whether a station has moved. If a station has moved, it will update the table
accordingly. Migration happens when the following conditions are met:
• The received packet’s SA is in the table, but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length.
The lookup engine will update the existing record in the table with the new source port information.
3.3.4
AGING
The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record
from the table. The lookup engine constantly performs the aging process and will continuously remove aging records.
The aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit [2].
3.3.5
FORWARDING
The KSZ8893FQL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 3-6 shows
stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table
for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning
tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in
Figure 3-7. The packet is sent to PTF2.
FIGURE 3-6:
DESTINATION ADDRESS LOOKUP FLOW CHART, STAGE 1
Start
PTF1= NULL
NO
- Search VLAN table
- Ingress VLAN filtering
- Discard NPVID check
VLAN ID
Valid?
YES
Search complete.
Get PTF1 from
Static MAC Table
FOUND
Search Static
Table
This search is based on
DA or DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
Dynamic MAC
Table
FOUND
Dynamic Table
Search
This search is based on
DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
VLAN Table
PTF1
DS00003038C-page 28
2019 - 2021 Microchip Technology Inc. and its subsidiaries
KSZ8893FQL
FIGURE 3-7:
DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2
PTF1
Spanning Tree
Process
- Check receiving port's receive enable bit
- Check destination port's transmit enable bit
- Check whether packets are special (BPDU
or specified)
IGMP Process
- Applied to MAC #1 and MAC #2
- MAC #3 is reserved for
microprocessor
- IGMP will be forwarded to port 3
Port Mirror
Process
- RX Mirror
- TX Mirror
- RX or TX Mirror
- RX and TX Mirror
Port VLAN
Membership
Check
PTF2
The KSZ8893FQL will not forward the following packets:
1.
2.
3.
Error packets: These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal
size packet errors.
IEEE802.3x PAUSE frames: KSZ8893FQL intercepts these packets and performs full-duplex flow control accordingly.
"Local" packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches
the port from which the packet originated, the packet is defined as local.
3.3.6
SWITCHING ENGINE
The KSZ8893FQL features a high-performance switching engine to move data to and from the MAC’s packet buffers.
It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32 kB internal frame buffer. This buffer pool is shared between all three ports. There are a
total of 256 buffers available. Each buffer is sized at 128 bytes.
3.3.7
MAC OPERATION
The KSZ8893FQL strictly abides by IEEE 802.3 standards to maximize compatibility.
3.3.7.1
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
3.3.7.2
Back-Off Algorithm
The KSZ8893FQL implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional
"aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration
for register 4 (0x04) bit [3].
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DS00003038C-page 29
KSZ8893FQL
3.3.7.3
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
3.3.7.4
Illegal Frames
The KSZ8893FQL discards frames less than 64 bytes and can be programmed to accept frames up to 1518 bytes, 1536
bytes, or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Because the
KSZ8893FQL supports VLAN tags, the maximum sizing is adjusted when these tags are present.
3.3.7.5
Full-Duplex Flow Control
The KSZ8893FQL supports standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8893FQL receives a pause control frame, the KSZ8893FQL will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the
current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while
it is flow controlled), only flow control packets from the KSZ8893FQL are transmitted.
On the transmit side, the KSZ8893FQL has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources, including available buffers, available transmit queues, and
available receive queues.
The KSZ8893FQL will flow control a port that has just received a packet if the destination port resource is busy. The
KSZ8893FQL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802.3x
standard. Once the resource is freed up, the KSZ8893FQL sends out the other flow control frame (XON) with zero pause
time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow
control mechanism from being constantly activated and deactivated.
The KSZ8893FQL flow controls all ports if the receive queue becomes full.
3.3.7.6
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as full-duplex flow control. If backpressure is required, the KSZ8893FQL sends preambles to defer
the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8893FQL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to prevent packet
reception.
To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:
• Aggressive back-off (register 3 (0x03), bit [0])
• No excessive collision drop (register 4 (0x04), bit [3])
Note that these bits are not set as defaults because this is not the IEEE standard.
3.3.7.7
Broadcast Storm Protection
The KSZ8893FQL has an intelligent option to protect the switch system from receiving too many broadcast packets. As
the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893FQL has the option to include “multicast
packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67 ms interval for 100BT and a 500 ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes
during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting is 0x63 (99 decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec × 67 ms/interval × 1% = 99 frames/interval (approx.) = 0x63
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes of
preamble between two packets.
DS00003038C-page 30
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KSZ8893FQL
3.3.8
MII INTERFACE OPERATION
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by the KSZ8893FQL is connected to device’s
third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception.
Table 3-9 describes the signals used by the MII bus.
TABLE 3-9:
MII SIGNALS
PHY Mode Connections
MAC Mode Connections
External MAC
Controller Signals
KSZ8893FQL
PHY Signals
Pin Description
External PHY
Signals
KSZ8893FQL
MAC Signals
MTXEN
SMTXEN
Transmit Enable
MTXEN
SMRXDV
MTXER
SMTXER
Transmit Error
MTXER
(NOT USED)
MTXD3
SMTXD[3]
Transmit Data Bit 3
MTXD3
SMRXD[3]
MTXD2
SMTXD[2]
Transmit Data Bit 2
MTXD2
SMRXD[2]
MTXD1
SMTXD[1]
Transmit Data Bit 1
MTXD1
SMRXD[1]
MTXD0
SMTXD[0]
Transmit Data Bit 0
MTXD0
SMRXD[0]
MTXC
SMTXC
Transmit Clock
MTXC
SMRXC
MCOL
SCOL
Collision Detection
MCOL
SCOL
MCRS
SCRS
Carrier Sense
MCRS
SCRS
MRXDV
SMRXDV
Receive Data Valid
MRXDV
SMTXEN
MRXER
(NOT USED)
Receive Error
MRXER
SMTXER
MRXD3
SMRXD[3]
Receive Data Bit 3
MRXD3
SMTXD[3]
MRXD2
SMRXD[2]
Receive Data Bit 2
MRXD2
SMTXD[2]
MRXD1
SMRXD[1]
Receive Data Bit 1
MRXD1
SMTXD[1]
MRXD0
SMRXD[0]
Receive Data Bit 0
MRXD0
SMTXD[0]
MRXC
SMRXC
Receive Clock
MRXC
SMTXC
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at one-quarter the
network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error has
occurred during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For half-duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
The KSZ8893FQL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Because the switch filters error frames, these MII error signals are not used by the
KSZ8893FQL. So, for PHY mode operation, if the device interfacing with the KSZ8893FQL has an MRXER input pin, it
needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8893FQL has an MTXER input
pin, it also needs to be tied low.
3.3.9
RMII INTERFACE OPERATION
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
•
•
•
•
Supports 10 Mbps and 100 Mbps data rates.
Uses a single 50 MHz clock reference (provided externally).
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception
The RMII provided by the KSZ8893FQL is connected to the device’s third MAC. It complies with the RMII Specification.
The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal
description.
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DS00003038C-page 31
KSZ8893FQL
TABLE 3-10:
RMII SIGNAL DESCRIPTION
RMII Signal
Name
Direction with
Respect to PHY
Direction with
Respect to MAC
REF_CLK
Input
Input or Output
CRS_DV
Output
Input
Carrier sense/Receive data
SMRXDV (output)
valid
RXD1
Output
Input
Receive data bit 1
RMII Signal Description
Device RMII Signal
Direction
Synchronous 50 MHz clock
reference for receive, trans- REFCLK (input)
mit, and control interface
SMRXD[1] (output)
RXD0
Output
Input
Receive data bit 0
SMRXD[0] (output)
TX_EN
Input
Output
Transmit enable
SMTXEN (input)
TXD1
Input
Output
Transmit data bit 1
SMTXD[1] (input)
TXD0
Input
Output
Transmit data bit 0
SMTXD[0] (input)
RX_ER
Output
Input (not req’d)
Receive error
(Not used)
SMTXER* (input)
* Connects to RX_ER
—
—
—
—
signal of RMII PHY
device
The KSZ8893FQL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames
from RMII PHY devices, the SMTXER input signal of the KSZ8893FQL is connected to the RXER output signal of the
RMII PHY device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, tie MII signals, SMTXD[3:2] and SMTXER, to ground if they are not used.
The KSZ8893FQL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8893FQL
devices to be connected back-to-back. The following table shows the KSZ8893FQL RMII pin connections with an external RMII PHY and an external RMII MAC, such as another KSZ8893FQL device.
TABLE 3-11:
RMII SIGNAL CONNECTIONS
PHY-to-MAC Connections
MAC-to-MAC Connections
External PHY
Signals
KSZ8893FQL MAC
Signals
Pin Descriptions
REF_CLK
REFCLK
Reference Clock
REFCLK
REF_CLK
CRS_DV
SMRXDV
Carrier Sense/
Receive Data Valid
SMRXDV
CRS_DV
RXD1
SMRXD[1]
Receive Data Bit 1
SMRXD[1]
RXD1
RXD0
SMRXD[0]
Receive Data Bit 0
SMRXD[0]
RXD0
KSZ8893FQL MAC
Signals
External MAC
Signals
TX_EN
SMTXEN
Transmit Enable
SMTXEN
TX_EN
TXD1
SMTXD[1]
Transmit Data Bit 1
SMTXD[1]
TXD1
TXD0
SMTXD[0]
Transmit Data Bit 0
SMTXD[0]
TXD0
RX_ER
SMTXER
Receive Error
(Not used)
(Not used)
DS00003038C-page 32
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KSZ8893FQL
3.3.10
SNI (7-WIRE) OPERATION
The serial network interface (SNI), or 7-wire, is compatible with some controllers used for network layer protocol processing. In SNI mode, the KSZ8893FQL acts like a PHY and the external controller functions as the MAC. The
KSZ8893FQL can interface directly with external controllers using the 7-wire interface. These signals are divided into
two groups, one for transmission and the other for reception. The signals involved are described in the following table.
TABLE 3-12:
SNI SIGNALS
Pin Description
External MAC Controller Signal
KSZ8893FQL PHY Signal
Transmit enable
TXEN
SMTXEN
Serial transmit data
TXD
SMTXD[0]
Transmit clock
TXC
SMTXC
Collision detection
COL
SCOL
Carrier sense
CRS
SMRXDV
Serial receive data
RXD
SMRXD[0]
Receive clock
RXC
SMRXC
The SNI interface is a bit wide data interface and, therefore, runs at the network bit rate (not encoded). An additional
signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when
the data is valid.
For half-duplex operation, the SCOL signal is used to indicate that a collision has occurred during transmission.
3.3.11
MII MANAGEMENT (MIIM) INTERFACE
The KSZ8893FQL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8893FQL.
An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further
details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8893FQL device.
• Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM registers [29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5 MHz.
Table 3-13 depicts the MII Management Interface frame format.
TABLE 3-13:
MII MANAGEMENT INTERFACE FRAME FORMAT
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA
Data Bits[15:0]
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
3.3.12
SERIAL MANAGEMENT INTERFACE (SMI)
The SMI is the KSZ8893FQL non-standard MIIM interface that provides access to all KSZ8893FQL configuration registers. This interface allows an external device to completely monitor and control the states of the KSZ8893FQL.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8893FQL device.
• Access to all KSZ8893FQL configuration registers. Register access includes the Global, Port, and Advanced Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers [29, 31].
Table 3-14 depicts the SMI frame format.
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KSZ8893FQL
TABLE 3-14:
SERIAL MANAGEMENT INTERFACE (SMI) FRAME FORMAT
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA
Data Bits[15:0]
Idle
32 1’s
01
00
1xRRR
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
Read
Write
32 1’s
01
00
0xRRR
RRRRR 10
xxxx_xxxx_DDDD_DDDD
Z
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8893FQL registers 0-141 (0x00 – 0x8D), the following applies:
• PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
• Registers are 8 data bits wide.
- For read operation, data bits [15:8] are read back as 0’s.
- For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
3.3.13
REPEATER MODE
The KSZ8893FQL supports repeater mode in 100BASE-TX half-duplex mode. In repeater mode, all ingress packets are
broadcast to the other two ports. MAC address checking and learning are disabled.
Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured
to 100BASE-TX half-duplex mode. Additionally, both PHY ports need to have auto-negotiation disabled.
The latency between the two PHY ports is 270 ns (minimum) and 310 ns (maximum). The 40 ns difference is one clock
skew (one 25 MHz clock period) between reception and transmission. Latency is defined as the time from the first bit of
the Destination Address (DA) entering the ingress port to the first bit of the DA exiting the egress port.
3.4
3.4.1
Advanced Switch Functions
SPANNING TREE SUPPORT
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive
enable”, and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. Table 3-15 shows
the port setting and software actions taken for each of the five spanning tree states.
TABLE 3-15:
SPANNING TREE STATES
Disable State
Port Setting
Software Action
The port should not
forward or receive
any packets. Learning is disabled.
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The processor should not send any packets to the port. The switch
may still send specific packets to the processor (packets that match
some entries in the “Static MAC table” with “overriding bit” set) and
the processor should discard those packets. Address learning is disabled on the port in this state.
Blocking State
Port Setting
Software Action
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The processor should not send any packets to the port(s) in this
state. The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets). The
“overriding” bit should also be set so that the switch will forward
those specific packets to the processor. Address learning is disabled
on the port in this state.
Only packets to the
processor are forwarded. Learning is
disabled.
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TABLE 3-15:
SPANNING TREE STATES (CONTINUED)
Listening State
Port Setting
Software Action
Only packets to and
“transmit enable = 0,
from the processor
receive enable = 0,
are forwarded.
learning disable =1”
Learning is disabled.
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets). The
“overriding” bit should be set so that the switch will forward those
specific packets to the processor. The processor may send packets
to the port(s) in this state. See Special Tagging Mode for details.
Address learning is disabled on the port in this state.
Learning State
Software Action
Port Setting
Only packets to and
“transmit enable = 0,
from the processor
receive enable = 0,
are forwarded.
learning disable = 0”
Learning is enabled.
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets). The
“overriding” bit should be set so that the switch will forward those
specific packets to the processor. The processor may send packets
to the port(s) in this state. See Special Tagging Mode for details.
Address learning is enabled on the port in this state.
Forwarding State
Software Action
Port Setting
The processor programs the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit is
set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. See
Special Tagging Mode for details. Address learning is enabled on the
port in this state.
Packets are for“transmit enable = 1,
warded and
receive enable = 1,
received normally.
learning disable = 0”
Learning is enabled.
3.4.2
SPECIAL TAGGING MODE
Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications.
Special Tagging, similar to 802.1Q Tagging, requires software to change network drivers to insert/modify/strip/interpret
the special tag. This mode is enabled by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.
TABLE 3-16:
SPECIAL TAGGING MODE FORMAT
802.1Q Tag Format
Special Tag Format
TPID (tag protocol identifier, 0x8100) + TCI
STPID (special tag identifier, 0x810 + 4 bit for “port mask”) +
TCI
The STPID is only seen and used by the port 3 interface, which should be connected to a processor. Packets from the
processor to the switch’s port 3 should be tagged with the STPID and the port mask, defined as follows:
• “0001”, forward packet to port 1 only
• “0010”, forward packet to port 2 only
• “0011”, broadcast packet to port 1 and port 2
Packets with normal tags (“0000” port masks) will use KSZ8893FQL internal MAC table look-up to determine the forwarding port(s). Also, if packets from the processor are not tagged, the KSZ8893FQL will treat them as normal packets
and use internal MAC table lookup to determine the forwarding port(s).
The KSZ8893FQL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port
setting, regardless of port states (disable, blocking, listening, and learning). Table 3-17 below shows the processor to
switch egress rules when dealing with STPID.
TABLE 3-17:
STPID EGRESS RULES (PROCESSOR TO SWITCH PORT 3)
Ingress Tag Field
TX Port “Tag
Insertion”
TX Port “Tag
Removal”
Egress Action to Tag Field
(0x810 + port mask)
0
0
- Modify tag field to 0x8100
- Recalculate CRC
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port VID if null VID
(0x810 + port mask)
0
1
- (STPID + TCI) will be removed
- Padding to 64 bytes if necessary
- Recalculate CRC
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TABLE 3-17:
STPID EGRESS RULES (PROCESSOR TO SWITCH PORT 3) (CONTINUED)
Ingress Tag Field
TX Port “Tag
Insertion”
(0x810 + port mask)
1
TX Port “Tag
Removal”
Egress Action to Tag Field
0
- Modify tag field to 0x8100
- Recalculate CRC
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port VID if null VID
- Modify tag field to 0x8100
- Recalculate CRC
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port VID if null VID
(0x810 + port mask)
1
1
Not Tagged
Don’t Care
Don’t Care
- Determined by the Dynamic MAC Address Table
For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the packets were received on, defined as follows:
• “0001”, packet from port 1
• “0010”, packet from port 2
No port mask values, other than the previous two defined ones, should be received in this direction in Special Tagging
Mode. The switch to processor egress rules are defined as follows:
TABLE 3-18:
STPID EGRESS RULES (SWITCH PORT 3 TO PROCESSOR)
Ingress Packets
Egress Action to Tag Field
Tagged with 0x8100 + TCI
- Modify TPID to 0x810 + “port mask”, which indicates source port
- No change to TCI if VID is not null
- Replace null VID with ingress port VID
- Recalculate CRC
Not tagged
- Insert TPID to 0x810 + “port mask”, which indicates source port
- Insert TCI with ingress port VID
- Recalculate CRC
3.4.3
IGMP SUPPORT
For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8893FQL provides two components:
3.4.3.1
IGMP Snooping
The KSZ8893FQL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2.
3.4.3.2
Multicast Address Insertion in the Static MAC Table
Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the subscribed
ports, instead of broadcasting to all ports.
To enable IGMP support, set register 5 bit [6] to ‘1’. Also, Special Tagging Mode needs to be enabled, so that the processor knows which port the IGMP packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.
3.4.4
IPV6 MLD SNOOPING
The KSZ8893FQL traps IPv6 Multicast Listener Discovery (MLD) packets and forwards them only to processor (port 3).
MLD snooping is controlled by register 5 bit 5 (MLD snooping enable) and register 5 bit 4 (MLD option).
With MLD snooping enabled, the KSZ8893FQL traps packets that meet all of the following conditions:
• IPv6 multicast packets
• Hop count limit = 1
• IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58)
If the MLD option bit is set to “1”, the KSZ8893FQL traps packets with the following additional condition:
• IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60)
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For MLD snooping, Special Tagging Mode also needs to be enabled, so that the processor knows which port the MLD
packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.
3.4.5
PORT MIRRORING SUPPORT
KSZ8893FQL supports port mirroring comprehensively as:
• “Receive Only” mirror on a port: All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received
on port 1 is destined to port 2 after the internal lookup. The KSZ8893FQL forwards the packet to both port 2 and
port 3. The KSZ8893FQL can optionally even forward “bad” received packets to the “sniffer port”.
• “Transmit Only” mirror on a port: All the packets transmitted on the port are mirrored on the sniffer port. For
example, port 1 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet
received on port 2 is destined to port 1 after the internal lookup. The KSZ8893FQL forwards the packet to both
port 1 and port 3.
• “Receive and Transmit” mirror on two ports: All the packets received on port A and transmitted on port B are
mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff”, and port 3 is programmed to be the
“sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8893FQL forwards
the packet to both port 2 and port 3.
Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer
port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively.
3.4.6
IEEE 802.1Q VLAN SUPPORT
The KSZ8893FQL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8893FQL provides a 16-entry VLAN Table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID)
for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the look-up process starts with VLAN Table lookup to determine whether the VID is valid. If the VID
is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for further lookup.
The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source Address
(FID+SA) are used for address learning.
TABLE 3-19:
FID+DA LOOKUP IN VLAN MODE
DA Found in
Static MAC
Table?
Use FID
Flag?
FID Match?
FID+DA Found in
Dynamic MAC
Table?
Action
No
Don’t care
Don’t care
No
Broadcast to the membership ports
defined in the VLAN Table bits [18:16]
No
Don’t care
Don’t care
Yes
Send to the destination port defined in
the Dynamic MAC Address Table bits
[53:52]
Yes
0
Don’t care
Don’t care
Send to the destination port(s) defined
in the Static MAC Address Table bits
[50:48]
Yes
1
No
No
Broadcast to the membership ports
defined in the VLAN Table bits [18:16]
Yes
1
No
Yes
Send to the destination port defined in
the Dynamic MAC Address Table bits
[53:52]
Yes
1
Yes
Don’t care
Send to the destination port(s) defined
in the Static MAC Address Table bits
[50:48]
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KSZ8893FQL
TABLE 3-20:
FID+SA LOOKUP IN VLAN MODE
FID+SA Found in Dynamic MAC Table?
Action
No
Learn and add FID+SA to the Dynamic MAC Address Table
Yes
Update time stamp
Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the
KSZ8893FQL. These features can be set on a per port basis, and are defined in register 18, 34, and 50 for ports 1, 2,
and 3, respectively.
3.4.7
QOS PRIORITY SUPPORT
The KSZ8893FQL provides Quality of Service (QoS) for applications such as VoIP and video conferencing. Offering four
priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest priority
queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32, and 48 is used to enable split transmit queues
for ports 1, 2, and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets have equal
priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four
priority queues. This global option is set and explained in bit [3] of register 5.
3.4.8
PORT-BASED PRIORITY
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received
at the high priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. Bits [4:3] of registers 16, 32, and 48 are used to enable port-based priority for ports
1, 2, and 3, respectively.
3.4.9
802.1P-BASED PRIORITY
For 802.1p-based priority, the KSZ8893FQL examines the ingress (incoming) packets to determine whether they are
tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value,
as specified by the registers 12 and 13. The “priority mapping” value is programmable.
Figure 3-8 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
FIGURE 3-8:
8
6
6
2
2
2
Preamble
DA
SA
VPID
TCI
length
Bits
802.1q VLAN Tag
16
Tagged Packet Type
(8100 for Ethernet)
3
1
802.1p
CFI
Bytes
802.1P PRIORITY FIELD FORMAT
46-1500
LLC
Data
4
FCS
12
VLAN ID
802.1p-based priority is enabled by bit [5] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively.
The KSZ8893FQL provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI),
is also referred to as the IEEE 802.1Q VLAN tag.
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Tag Insertion is enabled by bit [2] of the port registers control 0 and the register 194 to select which source port (ingress
port) PVID can be inserted on the egress port for ports 1, 2, and 3, respectively. At the egress port, untagged packets
are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36}, and
{51,52} for ports 1, 2, and 3, respectively, and the source port VID has to be inserted at selected egress ports by bit[5:0]
of register 194. The KSZ8893FQL will not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively. At the egress port, tagged
packets will have their 802.1Q VLAN Tags removed. The KSZ8893FQL will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8893FQL to set the “User Priority Ceiling” at any
ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the
ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority Ceiling” is enabled
by bit [3] of registers 17, 33, and 49 for ports 1, 2, and 3, respectively.
3.4.10
DIFFSERV-BASED PRIORITY
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully
decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine
priority.
3.4.11
RATE LIMITING SUPPORT
The KSZ8893FQL supports hardware rate limiting from 64 kbps to 88 Mbps, independently on the “receive side” and on
the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On
the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control
Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up
Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8893FQL provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The KSZ8893FQL counts the data rate from those selected type of frames. Packets
are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore, slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
3.5
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded
in the static table, it is also not learned in the dynamic MAC table. The KSZ8893FQL is then configured with the option
to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register
14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP).
3.6
Configuration Interface
The KSZ8893FQL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8893FQL is typically programmed using an EEPROM. If no EEPROM is present, the
KSZ8893FQL is configured using its default register settings. Some default settings are configured via strap-in pin
options. The strap-in pins are indicated in Table 2-1.
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KSZ8893FQL
3.6.1
I2C MASTER SERIAL BUS CONFIGURATION
With an additional I2C (“2-wire”) EEPROM, the KSZ8893FQL can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor.
For KSZ8893FQL I2C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as
defined in the KSZ8893FQL register map) with the exception of the “Read Only” status registers. After the de-assertion
of reset, the KSZ8893FQL sequentially reads in the configuration data for all 121 registers, starting from register 0. The
configuration access time (tprgm) is less than 15 ms, as depicted in Figure 3-9.
FIGURE 3-9:
EEPROM CONFIGURATION TIMING DIAGRAM
RST_N
....
SCL
....
SDA
....
tprgm
