KSZ8893FQL/FQLI
Single-Chip 3-Port Switch
with Fiber Support
Rev. 1.0
General Description
The KSZ8893FQL, a highly integrated single-chip 3 port
Fast Ethernet switch is designed for applications with
fiber support such as media converter. It provides two
10/100 transceivers with patented mixed-signal lowpower technology, three media access control (MAC)
units, a high-speed non-blocking switch fabric, a Layer-2
managed switch and TS-1000 OAM (Operations,
Administration and Management) V2 in a compact
solution. Backwards compatible to the TS-1000 (2002)
specification, TS-1000 V2 is an OAM sub-layer that
provides communication between CO (central office) and
CPE (customer premises equipment).
In fiber mode, one PHY unit can be configurable to
100Base-FX, 100Base-SX, or 10Base-FL fiber for
conversion to 10Base-T and 100Base-TX copper. A fiber
LED driver and post amplifier are also included for
10Base-FL and 100Base-SX applications.
LinkMD®
In copper mode, both PHY units support 10Base-T and
100Base-TX with HP Auto MDI/MDI-X for reliable
detection of and correction for straight-through and
crossover cables, and LinkMD® TDR-based cable
diagnostics for identification of faulty cabling.
The high performance switching engine features an
extensive feature set that includes programmable rate
limiting, tag/port-based VLAN, 4 priority class,
RMII/MII/SNI and CPU control/data interfaces to
effectively address both current and emerging Fast
Ethernet applications.
The KSZ8893FQL comes in a lead-free package, and is
also available in industrial temperature-grade. (see
Ordering Information).
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
KSZ8893FQL/FQLI
LinkMD is a registered trademark of Micrel, Inc
Product/Application names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 2006
M9999-070506-1.0
Micrel, Inc.
Features
Integrated 3-Port 10/100 Ethernet Switch
• Three MACs and two PHYs fully compliant with IEEE
802.3u standard
• Non-blocking switch fabric assures fast packet
delivery by utilizing an 1K MAC address lookup table
and a store-and-forward architecture
• Full duplex IEEE 802.3x flow control (PAUSE) with
force mode option
• Half-duplex back pressure flow control
• HP Auto MDI-X for reliable detection of and correction
for straight-through and crossover cables with disable
and enable option
• Micrel LinkMD® TDR-based cable diagnostics permit
identification of faulty copper cabling
• 100Base-FX, 100Base-SX and 10Base-FL fiber
support on port 1
• MII interface supports both MAC mode and PHY mode
• RMII interface support with external 50MHz system
clock
• 7-wire serial network interface (SNI) support for legacy
MAC
• Comprehensive LED Indicator support for link, activity,
full/half duplex and 10/100 speed
Fiber Support
KSZ8893FQL/FQLI
• Control registers configurable on the fly (port-priority,
802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
• Per port, 802.1p and DiffServ-based
• Re-mapping of 802.1p priority field per port basis
• Four priority levels
Advanced Switch Features
• IEEE 802.1q VLAN support for up to 16 groups (fullrange of VLAN IDs)
• VLAN ID tag/untag options, per port basis
• IEEE 802.1p/q tag insertion or removal on a per port
basis (egress)
• Programmable rate limiting at the ingress and egress
on a per port basis
• Broadcast storm protection with % control (global and
per port basis)
• IEEE 802.1d spanning tree protocol support
• Special tagging mode to inform the processor which
ingress port receives the packet
• IGMP snooping (Ipv4) and MLD snooping (Ipv6)
support for multicast packet filtering
• MAC filtering function to forward unknown unicast
packets to specified port
• Double-tagging support
• Integrated LED driver and post amplifier for 10BaseFL and 100Base-SX optical modules
Low Latency Support
TTC TS-1000 OAM
Switch Monitoring Features
• Supports OAM sub-layer which conforms to TS-1000
V2 specification from TTC (Telecommunication
Technology Committee)
• Sends and receives OAM frames to Center or
Terminal side
• Loop back mode to support loop back packet from
Center side to Terminal side
• Far-end fault detection with disable and enable
• Link Transparency to indicate link down from link
partner
• Unique User Defined Register (UDR) feature brings
OAM to low cost/complexity nodes
Comprehensive Configuration Register Access
• SMI, SPI and I2C management interfaces to all 8-bit
internal registers
• MII management (MIIM) interface to PHY registers
• I/O pins strapping and EEPROM to program selective
registers in unmanaged switch mode
July 2006
• Repeater mode
• Port mirroring/monitoring/sniffing: ingress and/or
egress traffic to any port or MII
• MIB counters for fully compliant statistics gathering, 34
MIB counters per port
• Loopback modes for remote diagnostic of failure
Low Power Dissipation
• Full-chip hardware power-down (register configuration
not saved)
• Per port based software power-save on PHY (idle link
detection, register configuration preserved)
• Voltages:
– Core 1.2V
– I/O and Transceiver 3.3V
Industrial Temperature Range: –40°C to +85°C
Available in 128-Pin PQFP, Lead-free package
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Applications
KSZ8893FQL/FQLI
Ordering Information
• Media Conversion Modules:
– 10Base-FL 10Base-T
– 100Base-SX 100Base-TX
– 100Base-FX 100Base-TX
• FTTx Managed/Unmanaged Media Converters
• Fiber Broadband Gateways
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3
Part Number
Temp. Range
Package
Lead Finish
KSZ8893FQL
0°C to 70°C
128-Pin PQFP
Pb-Free
KSZ8893FQLI
–40°C to +85°C
128-Pin PQFP
Pb-Free
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Revision History
Revision
Date
1.0
07/05/06
July 2006
Summary of Changes
Data sheet created.
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KSZ8893FQL/FQLI
Contents
Pin Configuration ............................................................................................................................................................ 12
Pin Description ................................................................................................................................................................ 13
Functional Description ................................................................................................................................................... 22
Functional Overview: Media Conversion...................................................................................................................... 22
TS-1000 OAM Operation .............................................................................................................................................. 22
OAM Frame Format ............................................................................................................................................. 22
Media Converter Modes....................................................................................................................................... 24
MC Loop Back Operation..................................................................................................................................... 25
Dedicated TS-1000 Registers & Pins................................................................................................................... 26
10Base-FL Operation.................................................................................................................................................... 27
Physical Interface ................................................................................................................................................. 27
Enabling 10Base-FL Mode................................................................................................................................... 27
100Base-SX Operation ................................................................................................................................................. 27
Physical Interface ................................................................................................................................................. 27
Enabling 100Base-SX Mode ................................................................................................................................ 27
Functional Overview: Physical Layer Transceiver ...................................................................................................... 28
100Base-TX Transmit ................................................................................................................................................... 28
100Base-TX Receive .................................................................................................................................................... 28
PLL Clock Synthesizer.................................................................................................................................................. 28
Scrambler/De-scrambler (100Base-TX Only) ............................................................................................................... 28
100Base-FX Operation ................................................................................................................................................. 29
100Base-FX Signal Detection....................................................................................................................................... 29
100Base-FX Far-End Fault ........................................................................................................................................... 29
10Base-T Transmit ....................................................................................................................................................... 29
10Base-T Receive ........................................................................................................................................................ 29
Fiber LED Driver ........................................................................................................................................................... 29
Post Amplifier................................................................................................................................................................ 30
Power Management...................................................................................................................................................... 30
MDI/MDI-X Auto Crossover .......................................................................................................................................... 30
Straight Cable....................................................................................................................................................... 30
Crossover Cable................................................................................................................................................... 31
Auto-Negotiation ........................................................................................................................................................... 32
LinkMD Cable Diagnostics............................................................................................................................................ 33
Access.................................................................................................................................................................. 33
Usage ................................................................................................................................................................... 33
Functional Overview: MAC and Switch......................................................................................................................... 34
Address Lookup ............................................................................................................................................................ 34
Learning ........................................................................................................................................................................ 34
Migration ....................................................................................................................................................................... 34
Aging ............................................................................................................................................................................. 34
Forwarding .................................................................................................................................................................... 34
Switching Engine .......................................................................................................................................................... 37
MAC Operation ............................................................................................................................................................. 37
Inter Packet Gap (IPG)......................................................................................................................................... 37
Back-Off Algorithm ............................................................................................................................................... 37
Late Collision........................................................................................................................................................ 37
Illegal Frames....................................................................................................................................................... 37
Full Duplex Flow Control ...................................................................................................................................... 37
Half-Duplex Backpressure ................................................................................................................................... 37
Broadcast Storm Protection ................................................................................................................................. 38
MII Interface Operation ................................................................................................................................................. 38
RMII Interface Operation............................................................................................................................................... 39
SNI (7-Wire) Operation ................................................................................................................................................. 40
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MII Management (MIIM) Interface ................................................................................................................................ 41
Serial Management Interface (SMI).............................................................................................................................. 41
Repeater Mode ............................................................................................................................................................. 42
Advanced Switch Functions .......................................................................................................................................... 42
Spanning Tree Support................................................................................................................................................. 42
Special Tagging Mode .................................................................................................................................................. 43
IGMP Support ............................................................................................................................................................... 44
IGMP Snooping .................................................................................................................................................... 44
Multicast Address Insertion in the Static MAC Table ........................................................................................... 44
IPv6 MLD Snooping ...................................................................................................................................................... 44
Port Mirroring Support................................................................................................................................................... 44
IEEE 802.1Q VLAN Support ......................................................................................................................................... 45
QoS Priority Support ..................................................................................................................................................... 46
Port-Based Priority........................................................................................................................................................ 46
802.1p-Based Priority ................................................................................................................................................... 46
DiffServ-Based Priority.................................................................................................................................................. 47
Rate Limiting Support ................................................................................................................................................... 47
Unicast MAC Address Filtering..................................................................................................................................... 47
Configuration Interface.................................................................................................................................................. 47
I2C Master Serial Bus Configuration .................................................................................................................... 47
I2C Slave Serial Bus Configuration ...................................................................................................................... 48
SPI Slave Serial Bus Configuration...................................................................................................................... 49
Loopback Support......................................................................................................................................................... 52
Far-end Loopback ................................................................................................................................................ 52
Near-end (Remote) Loopback.............................................................................................................................. 53
MII Management (MIIM) Registers ................................................................................................................................. 54
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control ........................................................................... 55
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control ........................................................................... 55
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status ............................................................................ 56
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status ............................................................................ 56
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High ................................................................................... 56
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High ................................................................................... 56
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low.................................................................................... 56
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low.................................................................................... 56
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability......................................... 57
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability......................................... 57
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability ............................................ 57
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability ............................................ 57
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status.............................................................. 58
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status.............................................................. 58
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status ...................................................... 58
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status ...................................................... 58
Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers).................................................................... 59
Global Registers ........................................................................................................................................................... 60
Register 0 (0x00): Chip ID0.................................................................................................................................. 60
Register 1 (0x01): Chip ID1 / Start Switch ........................................................................................................... 60
Register 2 (0x02): Global Control 0...................................................................................................................... 61
Register 3 (0x03): Global Control 1...................................................................................................................... 61
Register 4 (0x04): Global Control 2...................................................................................................................... 62
Register 5 (0x05): Global Control 3...................................................................................................................... 63
Register 6 (0x06): Global Control 4...................................................................................................................... 63
Register 7 (0x07): Global Control 5...................................................................................................................... 64
Register 8 (0x08): Global Control 6...................................................................................................................... 64
Register 9 (0x09): Global Control 7...................................................................................................................... 64
Register 10 (0x0A): Global Control 8 ................................................................................................................... 65
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Register 11 (0x0B): Global Control 9 ................................................................................................................... 65
Register 12 (0x0C): Global Control 10 ................................................................................................................. 65
Register 13 (0x0D): Global Control 11 ................................................................................................................. 66
Register 14 (0x0E): Global Control 12 ................................................................................................................. 66
Register 15 (0x0F): Global Control 13 ................................................................................................................. 66
Port Registers ............................................................................................................................................................... 67
Register 16 (0x10): Port 1 Control 0 .................................................................................................................... 67
Register 32 (0x20): Port 2 Control 0 .................................................................................................................... 67
Register 48 (0x30): Port 3 Control 0 .................................................................................................................... 67
Register 17 (0x11): Port 1 Control 1 .................................................................................................................... 68
Register 33 (0x21): Port 2 Control 1 .................................................................................................................... 68
Register 49 (0x31): Port 3 Control 1 .................................................................................................................... 68
Register 18 (0x12): Port 1 Control 2 .................................................................................................................... 69
Register 34 (0x22): Port 2 Control 2 .................................................................................................................... 69
Register 50 (0x32): Port 3 Control 2 .................................................................................................................... 69
Register 19 (0x13): Port 1 Control 3 .................................................................................................................... 69
Register 35 (0x23): Port 2 Control 3 .................................................................................................................... 69
Register 51 (0x33): Port 3 Control 3 .................................................................................................................... 69
Register 20 (0x14): Port 1 Control 4 .................................................................................................................... 70
Register 36 (0x24): Port 2 Control 4 .................................................................................................................... 70
Register 52 (0x34): Port 3 Control 4 .................................................................................................................... 70
Register 21 (0x15): Port 1 Control 5 .................................................................................................................... 70
Register 37 (0x25): Port 2 Control 5 .................................................................................................................... 70
Register 53 (0x35): Port 3 Control 5 .................................................................................................................... 70
Register 22 (0x16): Port 1 Control 6 .................................................................................................................... 71
Register 38 (0x26): Port 2 Control 6 .................................................................................................................... 71
Register 54 (0x36): Port 3 Control 6 .................................................................................................................... 71
Register 23 (0x17): Port 1 Control 7 .................................................................................................................... 72
Register 39 (0x27): Port 2 Control 7 .................................................................................................................... 72
Register 55 (0x37): Port 3 Control 7 .................................................................................................................... 72
Register 24 (0x18): Port 1 Control 8 .................................................................................................................... 73
Register 40 (0x28): Port 2 Control 8 .................................................................................................................... 73
Register 56 (0x38): Port 3 Control 8 .................................................................................................................... 73
Register 25 (0x19): Port 1 Control 9 .................................................................................................................... 74
Register 41 (0x29): Port 2 Control 9 .................................................................................................................... 74
Register 57 (0x39): Port 3 Control 9 .................................................................................................................... 74
Register 26 (0x1A): Port 1 PHY Special Control/Status ...................................................................................... 75
Register 42 (0x2A): Port 2 PHY Special Control/Status ...................................................................................... 75
Register 58 (0x3A): Reserved, not applied to port 3............................................................................................ 75
Register 27 (0x1B): Port 1 LinkMD Result ........................................................................................................... 75
Register 43 (0x2B): Port 2 LinkMD Result ........................................................................................................... 75
Register 59 (0x3B): Reserved, not applied to port 3............................................................................................ 75
Register 28 (0x1C): Port 1 Control 12.................................................................................................................. 76
Register 44 (0x2C): Port 2 Control 12.................................................................................................................. 76
Register 60 (0x3C): Reserved, not applied to port 3............................................................................................ 76
Register 29 (0x1D): Port 1 Control 13.................................................................................................................. 77
Register 45 (0x2D): Port 2 Control 13.................................................................................................................. 77
Register 61 (0x3D): Reserved, not applied to port 3............................................................................................ 77
Register 30 (0x1E): Port 1 Status 0 ..................................................................................................................... 77
Register 46 (0x2E): Port 2 Status 0 ..................................................................................................................... 77
Register 62 (0x3E): Reserved, not applied to port 3............................................................................................ 77
Register 31 (0x1F): Port 1 Status 1...................................................................................................................... 78
Register 47 (0x2F): Port 2 Status 1...................................................................................................................... 78
Register 63 (0x3F): Port 3 Status 1...................................................................................................................... 78
TS-1000 Media Converter Registers ............................................................................................................................ 79
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Register 64 (0x40): PHY Address ........................................................................................................................ 79
Register 65 (0x41): Center Side Status ............................................................................................................... 79
Register 66 (0x42): Center Side Command......................................................................................................... 80
Register 67 (0x43): PHY-SW Initialize ................................................................................................................. 80
Register 68 (0x44): Loop Back Setup1 ................................................................................................................ 81
Register 69 (0x45): Loop Back Setup2 ................................................................................................................ 82
Register 70 (0x46): Loop Back Result Counter for CRC Error ............................................................................ 82
Register 71 (0x47): Loop Back Result Counter for Timeout ................................................................................ 82
Register 72 (0x48): Loop Back Result Counter for Good Packet ........................................................................ 83
Register 73 (0x49): Additional Status (Center and Terminal side) ...................................................................... 83
Register 74 (0x4A): Remote Command 1............................................................................................................ 83
Register 75 (0x4B): Remote Command 2............................................................................................................ 84
Register 76 (0x4C): Remote Command 3............................................................................................................ 84
Register 77 (0x4D): Valid MC Packet Transmitted Counter ................................................................................ 85
Register 78 (0x4E): Valid MC Packet Received Counter..................................................................................... 85
Register 79 (0x4F): Shadow of 0x58h Register ................................................................................................... 85
Register 80 (0x50): My Status 1 (Terminal and Center side) .............................................................................. 86
Register 81 (0x51): My Status 2........................................................................................................................... 87
Register 82 (0x52): My Vendor Info (1)................................................................................................................ 87
Register 83 (0x53): My Vendor Info (2)................................................................................................................ 87
Register 84 (0x54): My Vendor Info (3)................................................................................................................ 87
Register 85 (0x55): My Model Info (1).................................................................................................................. 87
Register 86 (0x56): My Model Info (2).................................................................................................................. 87
Register 87 (0x57): My Model Info (3).................................................................................................................. 88
Register 88 (0x58): LNK Partner Status (1) ......................................................................................................... 88
Register 89 (0x59): LNK Partner Status (2) ......................................................................................................... 88
Register 90 (0x5A): LNK Partner Vendor Info (1) ................................................................................................ 88
Register 91 (0x5B): LNK Partner Vendor Info (2) ................................................................................................ 88
Register 92 (0x5C): LNK Partner Vendor Info (3) ................................................................................................ 88
Register 93 (0x5D): LNK Partner Model Info (1).................................................................................................. 88
Register 94 (0x5E): LNK Partner Model Info (2) .................................................................................................. 88
Register 95 (0x5F): LNK Partner Model Info (3) .................................................................................................. 88
Advanced Control Registers ......................................................................................................................................... 89
Register 96 (0x60): TOS Priority Control Register 0............................................................................................ 89
Register 97 (0x61): TOS Priority Control Register 1............................................................................................ 89
Register 98 (0x62): TOS Priority Control Register 2............................................................................................ 89
Register 99 (0x63): TOS Priority Control Register 3............................................................................................ 89
Register 100 (0x64): TOS Priority Control Register 4.......................................................................................... 90
Register 101 (0x65): TOS Priority Control Register 5.......................................................................................... 90
Register 102 (0x66): TOS Priority Control Register 6.......................................................................................... 90
Register 103 (0x67): TOS Priority Control Register 7.......................................................................................... 90
Register 104 (0x68): TOS Priority Control Register 8.......................................................................................... 91
Register 105 (0x69): TOS Priority Control Register 9.......................................................................................... 91
Register 106 (0x6A): TOS Priority Control Register 10 ....................................................................................... 91
Register 107 (0x6B): TOS Priority Control Register 11 ....................................................................................... 91
Register 108 (0x6C): TOS Priority Control Register 12 ....................................................................................... 92
Register 109 (0x6D): TOS Priority Control Register 13 ....................................................................................... 92
Register 110 (0x6E): TOS Priority Control Register 14 ....................................................................................... 92
Register 111 (0x6F): TOS Priority Control Register 15........................................................................................ 92
Switch MAC Address Registers.................................................................................................................................... 93
Register 112 (0x70): MAC Address Register 0.................................................................................................... 93
Register 113 (0x71): MAC Address Register 1.................................................................................................... 93
Register 114 (0x72): MAC Address Register 2.................................................................................................... 93
Register 115 (0x73): MAC Address Register 3.................................................................................................... 93
Register 116 (0x74): MAC Address Register 4.................................................................................................... 93
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Register 117 (0x75): MAC Address Register 5.................................................................................................... 93
User Defined Registers................................................................................................................................................. 93
Register 118 (0x76): User Defined Register 1 ..................................................................................................... 93
Register 119 (0x77): User Defined Register 2 ..................................................................................................... 93
Register 120 (0x78): User Defined Register 3 ..................................................................................................... 93
Indirect Access Registers ............................................................................................................................................. 94
Register 121 (0x79): Indirect Access Control 0 ................................................................................................... 94
Register 122 (0x7A): Indirect Access Control 1 ................................................................................................... 94
Register 123 (0x7B): Indirect Data Register 8 ..................................................................................................... 94
Register 124 (0x7C): Indirect Data Register 7 ..................................................................................................... 94
Register 125 (0x7D): Indirect Data Register 6 ..................................................................................................... 94
Register 126 (0x7E): Indirect Data Register 5 ..................................................................................................... 94
Register 127 (0x7F): Indirect Data Register 4 ..................................................................................................... 94
Register 128 (0x80): Indirect Data Register 3...................................................................................................... 94
Register 129 (0x81): Indirect Data Register 2...................................................................................................... 95
Register 130 (0x82): Indirect Data Register 1...................................................................................................... 95
Register 131 (0x83): Indirect Data Register 0...................................................................................................... 95
Reserved Registers ...................................................................................................................................................... 95
Register 132 (0x84): Digital Testing Status 0 ...................................................................................................... 95
Register 133 (0x85): Digital Testing Control 0 ..................................................................................................... 95
Register 134 (0x86): Analog Testing Control 0.................................................................................................... 95
Register 135 (0x87): Analog Testing Control 1.................................................................................................... 95
Register 136 (0x88): Analog Testing Control 2.................................................................................................... 95
Register 137 (0x89): Analog Testing Control 3.................................................................................................... 95
Register 138 (0x8A): Analog Testing Status........................................................................................................ 96
Register 139 (0x8B): Analog Testing Control 4 ................................................................................................... 96
Register 140 (0x8C): QM Debug 1....................................................................................................................... 96
Register 141 (0x8D): QM Debug 2....................................................................................................................... 96
Static MAC Address Table............................................................................................................................................ 97
VLAN Table................................................................................................................................................................... 99
Dynamic MAC Address Table..................................................................................................................................... 100
MIB (Management Information Base) Counters ......................................................................................................... 101
Additional MIB Counter Information ................................................................................................................... 103
Absolute Maximum Ratings(1) ...................................................................................................................................... 104
Operating Ratings(2) ...................................................................................................................................................... 104
Electrical Characteristics(4) .......................................................................................................................................... 104
Timing Diagrams ........................................................................................................................................................... 106
EEPROM Timing......................................................................................................................................................... 106
SNI Timing .................................................................................................................................................................. 107
MII Timing ................................................................................................................................................................... 108
RMII Timing................................................................................................................................................................. 109
SPI Input Timing ......................................................................................................................................................... 110
SPI Output Timing....................................................................................................................................................... 111
Auto-Negotiation Timing ............................................................................................................................................. 112
Reset Timing.................................................................................................................................................................. 113
Reset Circuit .................................................................................................................................................................. 114
Selection of Isolation Transformers............................................................................................................................ 115
Selection of Reference Crystal .................................................................................................................................... 115
Package Information ..................................................................................................................................................... 116
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List of Figures
Figure 1. TS-1000 OAM Frame Format ........................................................................................................................... 23
Figure 2. Typical TS-1000 Media Converter Application ................................................................................................. 24
Figure 3. KSZ8893FQL MC Loop Back Paths ................................................................................................................. 25
Figure 4. Typical Straight Cable Connection ................................................................................................................... 31
Figure 5. Typical Crossover Cable Connection ............................................................................................................... 31
Figure 6. Auto-Negotiation and Parallel Operation. ......................................................................................................... 32
Figure 7. Destination Address Lookup Flow Chart, Stage 1 ............................................................................................ 35
Figure 8. Destination Address Resolution Flow Chart, Stage 2....................................................................................... 36
Figure 9. 802.1p Priority Field Format.............................................................................................................................. 46
Figure 10. KSZ8893FQL EEPROM Configuration Timing Diagram. ............................................................................... 48
Figure 11. SPI Write Data Cycle. ..................................................................................................................................... 50
Figure 12. SPI Read Data Cycle. ..................................................................................................................................... 50
Figure 13. SPI Multiple Write. .......................................................................................................................................... 51
Figure 14. SPI Multiple Read. .......................................................................................................................................... 51
Figure 15. Far-End Loopback Path. ................................................................................................................................. 52
Figure 16. Near-end (Remote) Loopback Path................................................................................................................ 53
Figure 17. EEPROM Interface Input Timing Diagram.................................................................................................... 106
Figure 18. EEPROM Interface Output Timing Diagram ................................................................................................. 106
Figure 19. SNI Timing – Data Received from SNI ......................................................................................................... 107
Figure 20. SNI Timing – Data Input-to-SNI .................................................................................................................... 107
Figure 21. MII Timing – Data Received from MII ........................................................................................................... 108
Figure 22. MII Timing – Data Input-to-MII ...................................................................................................................... 108
Figure 23. RMII Timing – Data Received from RMII ...................................................................................................... 109
Figure 24. RMII Timing – Data Input-to-RMII................................................................................................................. 109
Figure 25. SPI Input Timing ........................................................................................................................................... 110
Figure 26. SPI Output Timing......................................................................................................................................... 111
Figure 27. Auto-Negotiation Timing ............................................................................................................................... 112
Figure 28. Reset Timing ................................................................................................................................................. 113
Figure 29. Recommended Reset Circuit ........................................................................................................................ 114
Figure 30. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output................................................ 114
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List of Tables
Table 1. TS-1000 Media Converter Mode Selection........................................................................................................ 24
Table 2. Dedicated TS-1000 Pins .................................................................................................................................... 26
Table 3. 10Base-FL Configuration ................................................................................................................................... 27
Table 4. 100Base-SX Configuration................................................................................................................................. 28
Table 5. FX and TX Mode Selection ................................................................................................................................ 29
Table 6. Programmable Current Values for Fiber LED Driver ......................................................................................... 30
Table 7. MDI/MDI-X Pin Definitions ................................................................................................................................. 30
Table 8. MII Signals.......................................................................................................................................................... 38
Table 9. RMII Signal Description...................................................................................................................................... 39
Table 10. RMII Signal Connections.................................................................................................................................. 40
Table 11. SNI Signals....................................................................................................................................................... 40
Table 12. MII Management Interface Frame Format ....................................................................................................... 41
Table 13. Serial Management Interface (SMI) Frame Format ......................................................................................... 41
Table 14. Spanning Tree States ...................................................................................................................................... 42
Table 15. Special Tagging Mode Format ......................................................................................................................... 43
Table 16. STPID Egress Rules (Processor to Switch Port 3) .......................................................................................... 43
Table 17. STPID Egress Rules (Switch Port 3 to Processor) .......................................................................................... 44
Table 18. FID+DA Lookup in VLAN Mode ....................................................................................................................... 45
Table 19. FID+SA Lookup in VLAN Mode ....................................................................................................................... 45
Table 20. KSZ8893FQL SPI Connections ....................................................................................................................... 49
Table 21. Format of Static MAC Table (8 Entries) ........................................................................................................... 97
Table 22. Format of Static VLAN Table (16 Entries)........................................................................................................ 99
Table 23. Format of Dynamic MAC Address Table (1K Entries) ................................................................................... 100
Table 24. Format of “Per Port” MIB Counters ................................................................................................................ 101
Table 25. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets............................................................................ 102
Table 26. Format of “All Port Dropped Packet” MIB Counters....................................................................................... 102
Table 27. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets................................................................ 102
Table 28. EEPROM Timing Parameters ........................................................................................................................ 106
Table 29. SNI Timing Parameters.................................................................................................................................. 107
Table 30. MII Timing Parameters................................................................................................................................... 108
Table 31. RMII Timing Parameters ................................................................................................................................ 109
Table 32. SPI Input Timing Parameters ......................................................................................................................... 110
Table 33. SPI Output Timing Parameters ...................................................................................................................... 111
Table 34. Auto-Negotiation Timing Parameters............................................................................................................. 112
Table 35. Reset Timing Parameters .............................................................................................................................. 113
Table 36. Transformer Selection Criteria ....................................................................................................................... 115
Table 37. Qualified Single Port Magnetics..................................................................................................................... 115
Table 38. Typical Reference Crystal Characteristics ...................................................................................................... 115
July 2006
11
M9999-070506-1.0
P1LED2
P1LED1
P1LED0
P2LED2
P2LED1
P2LED0
DGND
VDDIO
MCHS
MCCs
PDD#
ADVFC
P2ANEN
P2SPD
P2DPX
P2FFC
P1FST
P1CRCD
P1LPBM
P2LED3
DGND
VDDC
LEDSEL1
NC
P1LED3
RMII_EN
HWPOVR
P2MDIXDIS
P2MDIX
P1ANEN
P1SPD
P1DPX
P1FFC
ML_EN
DIAGF
PWRDN
AGND
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
UNUSED
PS0
PS1
SPIS_N
SDA
SCL
SPIQ
MDIO
MDC
UNUSED
UNUSED
VDDC
DGND
SCONF0
SCONF1
SCRS
SCOL
SMRXD0
SMRXD1
SMRXD2
SMRXD3
SMRXDV
SMRXC
VDDIO
DGND
SMTXC / REFCLK
SMTXER
SMTXD0
SMTXD1
SMTXD2
SMTXD3
SMTXEN
LEDSEL0
UNUSED
UNUSED
RST_N
X2
X1
Micrel, Inc.
July 2006
KSZ8893FQL/FQLI
Pin Configuration
UNUSED
UNUSED
UNUSED
DGND
VDDIO
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
DGND
VDDC
UNUSED
UNUSED
UNUSED
TESTEN
SCANEN
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
12
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AGND
VDDAP
AGND
ISET
TEST2
TEST1
AGND
VDDA
TXP2
TXM2
AGND
RXP2
RXM2
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
FXSD1
VDDA
AGND
MUX2
MUX1
AGND
128-Pin PQFP (PQ)
(Top View)
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin Description
Pin
Number
Pin Name
Type(1)
1
P1LED2
Ipu/O
2
P1LED1
Ipu/O
3
P1LED0
Ipu/O
Pin Function
Port 1LED indicators (active low)
(apply to all modes of operation, except Repeater Mode)
[LEDSEL1, LEDSEL0]
[0,0] Default
[0,1]
—
—
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
P1LED3
[LEDSEL1, LEDSEL0]
[1,0]
[1,1]
Act
—
P1LED2
Link
—
P1LED1
Full duplex/Col
—
P1LED0
Speed
—
P1LED3
Link/Act, 100Link/Act, 10Link/Act:
Low (link), High (no link), Toggle (transmit / receive activity)
Full duplex/Col:
Low (full duplex), High (half duplex), Toggles (collision)
Speed:
Low (100Base-TX), High (10Base-T)
Full duplex:
Low (full duplex), High (half duplex)
Act:
Toggles (transmit / receive activity)
Link:
Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0,0]
P1LED3
RPT_COL
P1LED2
RPT_LINK3/RX
P1LED1
RPT_LINK2/RX
P1LED0
RPT_LINK1/RX
RPT_COL:
Low (collision)
RPT_LINK#/RX (# = port):
Low (link), High (no link), Toggles (receive activity)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P1LED3 is pin 25.
During reset, P1LED[2:0] are inputs for internal testing.
July 2006
13
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
4
P2LED2
Ipu/O
5
P2LED1
Ipu/O
6
P2LED0
Ipu/O
Pin Function
Port 2 LED indicators (active low)
(apply to all modes of operation, except Repeater Mode)
[LEDSEL1, LEDSEL0]
[0,0] Default
[0,1]
—
—
P2LED2
Link/Act
100Link/Act
P2LED1
Full duplex/Col
10Link/Act
P2LED0
Speed
Full duplex
P2LED3
[LEDSEL1, LEDSEL0]
[1,0]
[1,1]
Act
—
P2LED2
Link
—
P2LED1
Full duplex/Col
—
P2LED0
Speed
—
P2LED3
Link/Act, 100Link/Act, 10Link/Act:
Low (link), High (no link), Toggles (transmit / receive activity)
Full duplex/Col:
Low (full duplex), High (half duplex), Toggles (collision)
Speed:
Low (100Base-TX), High (10Base-T)
Full duplex:
Low (full duplex), High (half duplex)
Act:
Toggles (transmit / receive activity)
Link:
Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0,0]
P2LED3
RPT_ACT
P2LED2
RPT_ERR3
P2LED1
RPT_ERR2
P2LED0
RPT_ERR1
RPT_ACT:
Low (activity)
RPT_ERR# (# = port):
Low (error status due to either isolation, partition, jabber, or JK error)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P2LED3 is pin 20.
During reset, P2LED[2:0] are inputs for internal testing.
7
DGND
Gnd
8
VDDIO
P
July 2006
Digital ground
3.3V digital VDD
14
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
9
MCHS
Ipd
10
MCCS
Ipd
Pin Function
KSZ8893FQL operating modes (defined below):
(MCHS, MCCS)
Description
Normal 3 port switch mode (3 MAC + 2 PHY)
MC mode is disabled.
Port 1 is either Fiber or UTP.
Port 2 is UTP.
Port 3 (MII) is enabled.
(0, 0)
Center MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber and has Center MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
(0, 1)
Terminal MC mode (2 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber and has Terminal MC
enabled.
Port 2 is UTP.
Port 3 (MII) is disabled.
(1, 0)
Terminal MC mode (3 MAC + 2 PHY)
(1, 1)
11
PDD#
Ipu
MC mode is enabled.
Port 1 Fiber and has Terminal MC
enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
Power Down Detect
1 = Normal operation.
0 = Power down detected.
In Terminal MC mode (pin MCHS is ‘1’), a high to low transition to this pin will cause
port 1 (fiber) to generate and send out an “Indicate Terminal MC Condition” OAM
frame with the S0 status bit set to ‘1’.
12
ADVFC
Ipu
1 = Advertise the switch’s flow control capability via auto-negotiation.
0 = Will not advertise the switch’s flow control capability via auto-negotiation.
13
P2ANEN
Ipu
1 = Enable auto-negotiation on port 2.
0 = Disable auto-negotiation on port 2.
14
P2SPD
Ipd
1 = Force port 2 to 100BT if P2ANEN = 0.
0 = Force port 2 to 10BT if P2ANEN = 0.
15
P2DPX
Ipd
1 = Port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails. Force
port 2 in full duplex mode if P2ANEN = 0.
0 = Port 2 default to half duplex mode if P2ANEN = 1 and auto-negotiation fails. Force
port 2 in half duplex mode if P2ANEN = 0.
16
P2FFC
Ipd
1 = Always enable (force) port 2 flow control feature.
0 = Port 2 flow control feature enable is determine by the auto-negotiation result.
July 2006
15
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
17
P1FST
Opu
Pin Function
1 = Normal function.
0 = MC in loopback mode, or MC abnormal conditions occur.
18
P1LCRCD
Ipd
In MC loopback mode,
1 = Drop OAM frames and Ethernet frames with the following errors – CRS, undersize,
oversize. Loopback Ethernet frames with only good CRC and valid length.
0 = Drop OAM frames only. Loopback all Ethernet frames including those with errors.
19
P1LPBM
Ipd
20
P2LED3
Opd
1 = Perform MC loopback at PHY of port 1.
0 = Perform MC loopback at MAC of port 2
Port 2 LED indicator
Note: An external 1K pull-down is needed on this pin if it is connected to an LED. The
1K resistor will not turn ON the LED.
See description in pin 4.
21
DGND
Gnd
22
VDDC /
VOUT_1V2
P
23
LEDSEL1
Ipd
24
NC
O
25
P1LED3
Opd
Digital ground
1.2V digital VDD
Provides VOUT_1V2 to KSZ8893FQL’s input power pins: VDDAP (pin 63), VDDC (pins 91
and 123), and VDDA (pins 38, 43, and 57).
LED display mode select.
See description in pins 1 and 4.
No connect
Port 1 LED indicator
Note: An external 1K pull-down is needed on this pin if it is connected to an LED. The
1K resistor will not turn ON the LED.
See description in pin 1.
26
RMII_EN
Opd
Strap pin for RMII Mode
1 = Enable
0 = Disable
After reset, this pin has no meaning and is a no connect.
27
HWPOVR
Ipd
Hardware pin overwrite
1 = Enable: All strap-in pin configurations are overwritten by the EEPROM
configuration data, except for P2ANEN (pin 13), P2SPD (pin 14), P2DPX (pin 15) and
ML_EN (pin 34). After reset, the pin state for P2ANEN, P2SPD and P2DPX is polled by
the KSZ8893FQL.
0 = Disable: All strap-in pin configurations are overwritten by the EEPROM
configuration data.
28
P2MDIXDIS
Ipd
Port 2 Auto MDI/MDI-X
PD (default) = enable
PU = disable
29
P2MDIX
Ipd
Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled.
PD (default) = MDI-X (transmit on TXP2 / TXM2 pins)
PU = MDI, (transmit on RXP2 / RXM2 pins)
30
P1ANEN
Ipu
1 = Enable auto-negotiation on port 1
0 = Disable auto-negotiation on port 1
31
P1SPD
Ipd
1 = Force port 1 to 100BT if P1ANEN = 0
0 = Force port 1 to 10BT if P1ANEN = 0
July 2006
16
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
32
P1DPX
Ipd
1 = Port 1 default to full duplex mode if P1ANEN = 1 and auto-negotiation fails. Force
port 1 in full-duplex mode if P1ANEN = 0.
0 = Port 1 default to half duplex mode if P1ANEN = 1 and auto-negotiation fails. Force
port 1 in half duplex mode if P1ANEN = 0.
33
P1FFC
Ipd
1 = Always enable (force) port 1 flow control feature
0 = Port 1 flow control feature enable is determined by auto-negotiation result.
34
ML_EN
Ipd
1 = Enable missing link
0 = Disable missing link
35
DIAGF
Ipd
1 = Diagnostic fail
0 = Diagnostic normal
36
PWRDN
Ipu
Chip power down input (active low)
Pin Function
1 = Normal operation
0 = The chip is powered down
37
AGND
Gnd
38
VDDA
P
Analog ground
39
AGND
Gnd
40
MUX1
I
No connect
10Base-FL/100Base-SX Enable. Active low.
1.2V analog VDD
Analog ground
41
MUX2
I
42
AGND
Gnd
43
VDDA
P
1.2V analog VDD
44
FXSD1
I
Fiber signal detect / factory test pin
45
RXP1
I/O
Analog ground
Physical receive or transmit signal (+ differential)
46
RXM1
I/O
Physical receive or transmit signal (– differential)
47
AGND
Gnd
Analog ground
48
TXP1
I/O
Physical transmit or receive signal (+ differential)
49
TXM1
I/O
Physical transmit or receive signal (– differential)
50
VDDATX
P
3.3V analog VDD
51
VDDARX
P
3.3V analog VDD
52
RXM2
I/O
Physical receive or transmit signal (– differential)
53
RXP2
I/O
Physical receive or transmit signal (+ differential)
54
AGND
Gnd
Analog ground
55
TXM2
I/O
Physical transmit or receive signal (– differential)
56
TXP2
I/O
Physical transmit or receive signal (+ differential)
57
VDDA
P
1.2 analog VDD
58
AGND
Gnd
Analog ground
59
TEST1
I
Factory test pin – float for normal operation
60
TEST2
I
Factory test pin – float for normal operation
61
ISET
O
Set physical transmit output current
Pull-down this pin with a 3.01K 1% resistor to ground.
62
AGND
63
VDDAP
P
64
AGND
Gnd
July 2006
Gnd
Analog ground
1.2V analog VDD for PLL
Analog ground
17
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
65
X1
I
25MHz crystal/oscillator clock connections
66
X2
O
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is no connected.
67
RST_N
Ipu
68
UNUSED
I
Unused pin – externally pull down for normal operation
69
UNUSED
I
Unused pin – externally pull down for normal operation
70
LEDSEL0
I
LED display mode select
See description in pins 1 and 4.
71
SMTXEN
I
Switch MII transmit enable
72
SMTXD3
I
Switch MII transmit data bit 3
73
SMTXD2
I
Switch MII transmit data bit 2
74
SMTXD1
I
Switch MII transmit data bit 1
75
SMTXD0
I
Switch MII transmit data bit 0
76
SMTXER
I
Switch MII transmit error
77
SMTXC /
REFCLK
I/O
Pin Function
Note: Clock is ±50ppm for both crystal and oscillator.
Hardware Reset (active low)
Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII mode
Reference Clock (RMII mode only)
Input for 50MHz ±50ppm system clock
Note: In RMII mode, pin X1 is pulled up to VDDIO supply with a 10K resistor and pin
X2 is a no connect.
78
DGND
Gnd
79
VDDIO
P
80
SMRXC
I/O
Digital ground
3.3V digital VDD
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
81
SMRXDV
O
Switch MII receive data valid
82
SMRXD3
Ipd/O
Switch MII receive data bit 3
Strap option: switch MII full-duplex flow control
PD (default) = disable
PU = enable
83
SMRXD2
Ipd/O
Switch MII receive data bit 2
Strap option: switch MII is in
PD (default) = full-duplex mode
PU = half-duplex mode
84
SMRXD1
Ipd/O
Switch MII receive data bit 1
Strap option: Switch MII is in
PD (default) = 100Mbps mode
PU = 10Mbps mode
85
SMRXD0
I/O
Switch MII receive data bit 0
Strap option: switch will accept packet size up to
PD = 1536 bytes (inclusive)
PU = 1522 bytes (tagged), 1518 bytes (untagged)
86
July 2006
SCOL
I/O
Switch MII collision detect
18
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
87
SCRS
I/O
88
SCONF1
I
89
SCONF0
I
90
Pin Function
Switch MII carrier sense
Switch MII interface configuration
(SCONF1,
SCONF0)
Description
(0,0)
disable, outputs tri-stated
(0,1)
PHY mode MII
(1,0)
MAC mode MII
(1,1)
PHY mode SNI
DGND
Gnd
Digital core ground
91
VDDC
P
1.2V digital VDD
92
UNUSED
I
Unused pin – externally pull down for normal operation
93
UNUSED
I
Unused pin – externally pull down for normal operation
94
MDC
I
MII management interface: clock input
95
MDIO
I/O
MII management interface: data input/output
Note: an external pull-up is needed on this pin when it is in use.
96
SPIQ
O
SPI slave mode: serial data output
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in use.
97
SCL
I/O
SPI slave mode / I2C slave mode: clock input
I2C master mode: clock output
See description in pins 100 and 101.
98
SDA
I/O
SPI slave mode: serial data input
I2C master/slave mode: serial data input/output
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in use.
99
SPIS_N
I
SPI slave mode: chip select (active low)
When SPIS_N is high, the KSZ8893FQL is deselected and SPIQ is held in high
impedance state.
A high-to-low transition is used to initiate SPI data transfer.
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in use.
100
PS1
I
101
PS0
I
Serial bus configuration pins to select mode of access to KSZ8893FQL internal
registers.
[PS1, PS0] = [0, 0] — I2C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8893FQL will be configured with the default
values of its internal registers and the values of its strap-in pins.)
Interface
Signals
Description
SPIQ
O
Not used (tri-stated)
SCL
O
I2C clock
SDA
I/O
I2C data I/O
SPIS_N
July 2006
Type
I
19
Not used
M9999-070506-1.0
Micrel, Inc.
Pin
Number
KSZ8893FQL/FQLI
Pin Name
Type(1)
Pin Function
[PS1, PS0] = [0, 1] — I2C slave mode
The external I2C master will drive the SCL clock.
The KSZ8893FQL device addresses are:
1011_1111
1011_1110
Interface
Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
I
I2C clock
SDA
I/O
SPIS_N
I
I2C data I/O
Not used
[PS1, PS0] = [1, 0] — SPI slave mode
Interface
Signals
SPIQ
Type
Description
O
SPI data out
SCL
I
SPI clock
SDA
I
SPI data In
SPIS_N
I
SPI chip select
[PS1, PS0] = [1, 1] – SMI-mode
In this mode, the KSZ8893FQL provides access to all its internal 8-bit registers through
its MDC and MDIO pins.
Note:
When (PS1, PS0) ≠ (1,1), the KSZ8893FQL provides access to its 16-bit MIIM
registers through its MDC and MDIO pins.
102
UNUSED
I
Unused pin – externally pull up for normal operation
103
UNUSED
I
Unused pin – externally pull up for normal operation
104
UNUSED
I
Unused pin – externally pull up for normal operation
105
UNUSED
I
Unused pin – externally pull up for normal operation
106
DGND
Gnd
107
VDDIO
P
3.3V digital VDD
108
UNUSED
I
Unused pin – externally pull up for normal operation
109
UNUSED
I
Unused pin – externally pull up for normal operation
110
UNUSED
I
Unused pin – externally pull down for normal operation
111
UNUSED
I
Unused pin – externally pull down for normal operation
112
UNUSED
I
Unused pin – externally pull down for normal operation
113
UNUSED
I
Unused pin – externally pull down for normal operation
114
UNUSED
I
Unused pin – externally pull down for normal operation
115
UNUSED
I
Unused pin – externally pull down for normal operation
116
UNUSED
I
Unused pin – externally pull down for normal operation
117
UNUSED
I
Unused pin – externally pull down for normal operation
118
UNUSED
I
Unused pin – externally pull down for normal operation
119
UNUSED
I
Unused pin – externally pull down for normal operation
July 2006
Digital ground
20
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Pin
Number
Pin Name
Type(1)
120
UNUSED
I
Unused pin – externally pull down for normal operation
121
UNUSED
I
Unused pin – externally pull down for normal operation
122
DGND
Gnd
123
VDDC
P
1.2V digital VDD
124
UNUSED
I
Unused pin – externally pull down for normal operation
125
UNUSED
I
Unused pin – externally pull down for normal operation
126
UNUSED
I
Unused pin – externally pull down for normal operation
127
TESTEN
Ipd
Scan Test Enable
For normal operation, pull-down this pin to ground.
128
SCANEN
Ipd
Scan Test Scan Mux Enable
For normal operation, pull-down this pin to ground.
Pin Function
Digital ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down.
Ipu = Input with internal pull-up.
Opd = Output with internal pull-down.
Opu = Output with internal pull-up.
Ipd/O = Input with internal pull-down during reset; output pin otherwise.
Ipu/O = Input with internal pull-up during reset; output pin otherwise.
July 2006
21
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Functional Description
The KSZ8893FQL is a single-chip Fast Ethernet media converter. It contains two 10/100 physical layer transceivers
and three Media Access Control (MAC) units with an integrated Layer 2 managed switch.
On the media side, the KSZ8893FQL supports IEEE 802.3 10Base-T and 100Base-TX on both PHY ports. In Media
Converter (MC) applications, PHY port 1 is the fiber port and supports 100Base-FX, 100Base-SX and 10Base-FL.
The KSZ8893FQL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the
host processor has complete control of the KSZ8893FQL via the SMI interface, MIIM interface, SPI bus, or I2C bus. An
unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Media Conversion
TS-1000 OAM Operation
The KSZ8893FQL implements Japan’s TTC (TELECOMMUNICATION TECHNOLOGY COMMITTEE) TS-1000 version
2, OAM sub-layer, which resides between RS and PCS layer in the IEEE 802.3 Standard. The OAM sub-layer is
provided in 100Base-FX mode, and is used by the KSZ8893FQL to send and receive OAM frames. These special
frames are used for the transmission of OAM (Operations, Administration, Management) information between center
MC and terminal MC. Key TS-1000 OAM features include:
•
•
•
•
•
•
•
Private point-to-point communication between two TS-1000 compliant devices
96 bits (12 bytes) frames for the transmission of OAM information between center MC and terminal MC
Transmission of MC status between center MC and terminal MC
Automatic generation of OAM frame to inform MC link partner of local MC’s status change
Transmission of vendor code and model number information between center MC and terminal MC for device
identification
Inquisition of terminal MC status by center MC
Remote loop back for diagnostic by center MC
OAM Frame Format
The TS-1000 OAM (Operations, Administration, and Management) Frame Format is shown on the following page.
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Command
Preamble
Conservation Delimiter
Direction Delimiter
C2–C3
Configuration Delimiter
C4–C7
C8–C15
Version
Control signal
S0
S1
S2
S3
S4
S5
S6
Power
Optical
UTP link
MC
Way for information
Loop mode
Terminal MC Link option
S7
S8
Terminal MC Link Speed1
Terminal MC Link Speed2
Status
Bit
F0–F7
C0
C1
S9
Terminal MC Link Duplex
S10
Terminal MC Auto-Negotiation
capability
S11
Multiple link partner
S12–S15
M0–M23
M24–M47
E0–E7
Reserve
Vendor code
Model number
FCS
Description
1010 1010
0
0: Upstream (from terminal MC to center MC)
1: Downstream (from center MC to terminal MC)
10: request 11:reponse
01: indication 00:reserved
0000
1000 0000: Start loop back test
0000 0000: Stop loop back test
0100 0000: Notify status
0: normal operation 1: power down
0: normal 1:abnormal
0: link up 1: link down
0: normal 1:brake
0: use conservation frame 1: use FEFI
0: normal operation 1: in loop mode
0: Center side MC have to set always “0”
1: Terminal side MC have to set always “1”
This bit must be set “0”
0: 10Mbps
1: 100Mbps
These bits have to be set “0”, if S2 is “1”
(Center side MC have to set always “0”)
0: Half Duplex
1: Full Duplex
This bit have to be set “0”, if S2 is “1”
(Center side MC have to set always “0”)
0: Not Support Auto-Negotiation
1: Support Auto-Negotiation
(Center side MC have to set always “0”)
0: one link partner on UTP side
1: multiple link partner on UTP side
All bits must be set “0”
Create FCS at this sub-layer (C0-M47)
Figure 1. TS-1000 OAM Frame Format
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KSZ8893FQL/FQLI
Media Converter Modes
TS-1000 Media Converter (MC) modes are selected and configured using hardware pins: MCHS and MCCS. The MC
modes are summarized in the following table and are also shown in the Pin Description and I/O Assignment section.
(MCHS, MCCS)
(0, 0)
(0, 1)
(1, 0)
(1, 1)
Description
Normal 3 port switch mode (3 MAC + 2 PHY)
MC mode is disabled.
Port 1 is either Fiber or UTP.
Port 2 is UTP.
Port 3 (MII) is enabled.
Center MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber & has Center MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
Terminal MC mode (2 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber & has Terminal MC enabled.
Port 2 is UTP.
Port 3 (MII) is disabled.
Terminal MC mode (3 MAC + 2 PHY)
MC mode is enabled.
Port 1 is Fiber & has Terminal MC enabled.
Port 2 is UTP.
Port 3 (MII) is enabled.
Table 1. TS-1000 Media Converter Mode Selection
The following figure shows two KSZ8893FQLs connected in a typical center MC to terminal MC application.
Figure 2. Typical TS-1000 Media Converter Application
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KSZ8893FQL/FQLI
MC Loop Back Operation
TS-1000 MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back
path to return the loop back packet back to the center MC. The KSZ8893FQL in terminal MC mode provides three loop
back path options:
Port 1 OPT
•
Receive loop back packet from center MC at RXP1/RXM1 input pins of port 1 (fiber).
•
Turn around loop back packet at PMD/PMA of port 1 (fiber).
•
Transmit loop back packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber).
Port 2 MAC
•
Receive loop back packet from center MC at RXP1/RXM1 input pins of port 1 (fiber).
•
Turn around loop back packet at MAC of port 2 (copper).
•
Transmit loop back packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber).
Port 2 UTP
•
Receive loop back packet from center MC at RXP1/RXM1 input pins of port 1 (fiber).
•
Turn around loop back packet at PMD/PMA of port 2 (copper).
•
Transmit loop back packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber).
Figure 3. KSZ8893FQL MC Loop Back Paths
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Dedicated TS-1000 Registers & Pins
The KSZ8893FQL provides 32 dedicated registers to support TS-1000 OAM communication in center MC and terminal
MC modes. The TS-1000 MC registers are located at 64 to 95 (0x40 to 0x5F), and provide the following functions:
•
•
•
•
•
•
•
•
•
PHY address configuration
Center MC and Terminal MC configuration
OAM frame selection and execution
MC loop back setup
MC loop back counters for CRC error, timeout, good packet
Remote command access
Counters for valid MC packet transmitted and received
MC (local) - status, vendor code, and model number
Link Partner (remote) - status, vendor code, and model number
The following table lists the dedicated KSZ8893FQL pins used in center MC and terminal MC modes.
Pin
Signal Name
Type
9
10
MCHS
MCCS
Ipd
Ipd
11
PDD#
Ipu
17
P1FST
Opu
18
P1CRCD
Ipd
19
P1LPBM
Ipd
34
ML_EN
Ipd
35
DIAGF
Ipd
Description
Selects center MC and terminal MC modes. See “Media Converter
Modes” subsection for details.
Power Down Detect – Use by terminal MC to detect a power-down
condition or indicate a failure has occurred.
1 = Normal operation
0 = Power down detected
After detecting a high-to-low transition on this pin, the KSZ8893FQL then
sends out an “Indicate Terminal MC Condition” OAM frame with the S0
status bit set to ‘1’ to inform the center MC that a power down condition
or failure has occurred on the terminal MC side.
If this pin is implemented, PWRDN (pin 36) needs to be de-asserted
(pulled up).
Drives low to indicate fault conditions (far-end fault detected, link
partner’s fiber or UTP port down), or MC loop back mode. This pin has
8mA drive and can directly drive a LED.
Used by terminal MC for MC loop back – strap-in pin to select:
1 = Drop OAM frames and Ethernet frames with the following errors –
CRC, undersize, oversize. Loop back Ethernet frames with only good
CRC and valid length.
0 = Drop OAM frames only. Loop back all Ethernet frames including
those with errors.
Used by terminal MC for MC loop back – strap-in pin to select:
1 = Perform MC loop back at PHY of port 1
0 = Perform MC loop back at MAC of port 2
See also register 11 (0x0B) bits[3:2].
Used by terminal MC for Missing Link Indication – strap-in pin to select:
1 = Enable Missing Link feature
0 = Disable Missing Link feature
Used by terminal MC for Diagnostic status
1 = Diagnostic fail
0 = Diagnostic normal
After detecting a change of state on this pin, the KSZ8893FQL sends out
an “Indicate Terminal MC Condition” OAM frame with the S3 status bit
set to the state of this pin to inform the center MC that a diagnostic status
change has occurred on the terminal MC side.
Table 2. Dedicated TS-1000 Pins
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10Base-FL Operation
10Base-FL operation is supported on port 1 of the KSZ8893FQL. It conforms to clause 15 and 18 of the IEEE802.3
Standard for 10Base-FL fiber operation. Refer to the Standard for details.
In a typical application, the KSZ8893FQL provides media conversion from 10Base-FL fiber on port 1 to 10Base-T
copper on port 2. Alternatively, port 2 can be substituted with port 3 to directly connect to an external MAC.
Physical Interface
For 10Base-FL operation, port 1 interfaces with an external fiber module to drive 850nm fiber optic links. The interface
connections between the KSZ8893FQL and fiber module are single-ended (common mode). 10Base-FL signal
transmission and reception are done on TXM1 (pin 49) and RXM1 (pin 46), respectively. Refer to Micrel reference
schematic for recommended interface circuit and termination.
Enabling 10Base-FL Mode
To enable 10Base-FL mode, tie FXSD1 (pin 44) high to +3.3V and MUX2 (pin 41) low-to-ground. Port 1 should also be
configured with auto-negotiation disabled, forced to 10Mbps for the speed, and set to either half or full duplex.
Optionally, flow control can be enabled to send out PAUSE frames in full duplex mode.
The 10Base-FL settings use the same strapping pins, MIIM registers and port registers as 10Base-T copper. These
settings are summarized in the following table.
10Base-FL Settings
Auto-Negotiation (disable only)
Speed (10Mbps only)
Duplex (half or full)
Forced Flow Control (option)
Strapping Pin (#)
MIIM Register #, Bit[#]
Port Register #, Bit[#]
P1ANEN (30)
P1SPD (31)
P1DPX (32)
P1FFC (33)
Reg. 0, Bit[12]
Reg. 0, Bit[13]
Reg. 0, Bit[8]
---
Reg. 28, Bit[7]
Reg. 28, Bit[6]
Reg. 28, Bit[5]
Reg. 18, Bit[4]
Table 3. 10Base-FL Configuration
100Base-SX Operation
100Base-SX operation is supported on port 1 of the KSZ8893FQL. It conforms to the TIA/EIA-785 Standard for
100Base-SX fiber operation. Refer to the Standard for details.
In a typical application, the KSZ8893FQL provides media conversion from 100Base-SX fiber on port 1 to 100Base-TX
copper on port 2. Alternatively, port 2 can be substituted with port 3 to directly connect to an external MAC.
Physical Interface
For 100Base-SX operation, port 1 interfaces with an external fiber module to drive 850nm fiber optic links. The interface
connections between the KSZ8893FQL and fiber module are single-ended (common mode). 100Base-SX signal
transmission and reception are done on TXM1 (pin 49) and RXM1 (pin 46), respectively. Refer to Micrel’s reference
schematic for recommended interface circuit and termination.
Enabling 100Base-SX Mode
To enable 100Base-SX mode, tie FXSD1 (pin 44) high to +3.3V and MUX2 (pin 41) low-to-ground. Port 1 should also
be configured with auto-negotiation disabled, forced to 100Mbps for the speed, and set to either half or full duplex.
Optionally, flow control can be enabled to send out PAUSE frames in full duplex mode.
The 100Base-SX settings use the same strapping pins, MIIM registers and port registers as 100Base-TX copper. These
settings are summarized in the following table.
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100Base-SX Settings
Auto-Negotiation (disable only)
Speed (100Mbps only)
Duplex (half or full)
Forced Flow Control (option)
KSZ8893FQL/FQLI
Strapping Pin (#)
MIIM Register #, Bit[#]
Port Register #, Bit[#]
P1ANEN (30)
P1SPD (31)
P1DPX (32)
P1FFC (33)
Reg. 0, Bit[12]
Reg. 0, Bit[13]
Reg. 0, Bit[8]
---
Reg. 28, Bit[7]
Reg. 28, Bit[6]
Reg. 28, Bit[5]
Reg. 18, Bit[4]
Table 4. 100Base-SX Configuration
Functional Overview: Physical Layer Transceiver
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 1% 3.01KΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for
optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature
variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8893FQL generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are
generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an
external 50MHz oscillator or system clock.
Scrambler/De-scrambler (100Base-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference
(EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift
register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the
incoming data stream using the same sequence as at the transmitter.
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100Base-FX Operation
100Base-FX operation is similar to 100Base-TX operation with the differences being that the scrambler/de-scrambler
and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed and
auto MDI/MDI-X is disabled.
100Base-FX Signal Detection
In 100Base-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver SD
(signal detect) output pin. 100Base-FX mode is activated when the FXSD1 input pin is greater than 1V. When FXSD1 is
between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD1 is over 2.2V, the
fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied high
to force 100Base-FX mode.
100Base-FX signal detection is summarized in the following table:
FXSD1 Input Voltage
Less than 0.2V
Greater than 1V, but less than 1.8V
Greater than 2.2V
Mode
TX mode
FX mode
No signal detected
Far-end fault generated
FX mode
Signal detected
Table 5. FX and TX Mode Selection
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage
swing to match the FXSD1 pin’s input voltage threshold.
100Base-FX Far-End Fault
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8893FQL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the
KSZ8893FQL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle
period between frames.
By default, FEF is enabled. FEF can be disabled through register setting.
10Base-T Transmit
The 10Base-T driver is incorporated with the 100Base-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with typical 2.3V amplitude. The harmonic contents
are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into
clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to
prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit,
the PLL locks onto the incoming signal and the KSZ8893FQL decodes a data frame. The receiver clock is maintained
active during idle periods in between data reception.
Fiber LED Driver
The device provides a current mode fiber LED driver. The edge enhanced current mode does not require any output
wave shaping. The drive current of the fiber LED driver is programmable thru register 138 (0x8A) bit[7:6]. The
programmable current values are as follow:
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Reg. 138 (0x8A) bit[7:6]
Current Value
00
60mA
01
80mA
10
90mA
11
40mA
Table 6. Programmable Current Values for Fiber LED Driver
Post Amplifier
The KSZ8893FQL also includes a post amplifier. The post amplifier is intended for interfacing the output of the preamplifier of the PIN diode module. The minimum sensitivity of the post amplifier is 2.5mVrms.
Power Management
The KSZ8893FQL features a per-port power down mode. To save power, a PHY port that is not in use can be powered
down via port control register, or via MIIM PHY register.
In addition, there is a full chip power down mode. When activated, the entire chip is powered down.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8893FQL offers HP Auto MDI/MDI-X and
Micrel Auto MDI/MDI-X crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for
the KSZ8893FQL device. This feature is extremely useful when end users are unaware of cable types, and also, saves
on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control
registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are:
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
2
TD+
1
RD+
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
Table 7. MDI/MDI-X Pin Definitions
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following
diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
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10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Transmit Pair
Receive Pair
3
Straight
Cable
3
4
4
5
5
6
6
7
7
8
8
Receive Pair
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
Figure 4. Typical Straight Cable Connection
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The
following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Figure 5. Typical Crossover Cable Connection
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Auto-Negotiation
The KSZ8893FQL conforms to the auto-negotiation protocol, as defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In
auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not
supported or the KSZ8893FQL link partner is forced to bypass auto-negotiation, then the KSZ8893FQL sets its
operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8893FQL
to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol.
The link up process is shown in the following flow diagram.
Figure 6. Auto-Negotiation and Parallel Operation
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LinkMD Cable Diagnostics
The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems
such as open circuits, short circuits and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with
maximum distance of 200m and accuracy of +/- 2m. Internal circuitry displays the TDR information in a user-readable
digital format.
Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation.
Access
LinkMD is initiated by accessing registers {26,27} and {42,43}, the LinkMD Control/Status registers, for ports 1 and 2,
respectively; and in conjunction with registers 29 and 45, Port Control Register 13, for ports 1 and 2, respectively.
Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access.
Usage
The following is a sample procedure for using LinkMD with registers {26,27,29} on port 1.
1. Disable auto MDI/MDI-X by writing a ‘1’ to register 29, bit [2] to enable manual control over the differential pair
used to transmit the LinkMD pulse.
2. Start cable diagnostic test by writing a ‘1’ to register 26, bit [4]. This enable bit is self-clearing.
3. Wait (poll) for register 26, bit [4] to return a ‘0’; indicating cable diagnostic test is completed.
4. Read cable diagnostic test results in register 26, bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the KSZ8893FQL is unable to shut down the link partner. In this
instance, the test is not run, since it would be impossible for the KSZ8893FQL to determine if the detected
signal is a reflection of the signal generated or a signal from another source.
5. Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0], and multiplying the result by
a constant of 0.4. The distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.4 x {(register 26, bit [0]),(register 27, bits [7:0])}
D (distance to cable fault) is expressed in meters.
Concatenated value of registers 26 and 27 is converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of
propagation that varies significantly from the norm.
For port 2 and for the MIIM PHY registers, LinkMD usage is similar.
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Functional Overview: MAC and Switch
Address Lookup
The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address
table plus switching information.
The KSZ8893FQL is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables, which
depending upon the operating environment and probabilities, may not guarantee the absolute number of addresses it
can learn.
Learning
The internal look-up engine updates its table with a new entry if the following conditions are met:
1. The received packet's Source Address (SA) does not exist in the lookup table.
2. The received packet is good; the packet has no receiving errors, and is of legal length.
The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
then the last entry of the table is deleted to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station has moved. If a station has moved, it will update the table
accordingly. Migration occurs when the following conditions are met:
1. The received packet's SA is in the table but the associated source port information is different.
2. The received packet is good; the packet has no receiving errors, and is of legal length.
The lookup engine will update the existing record in the table with the new source port information.
Aging
The look-up engine updates the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine removes the
record from the table. The look-up engine constantly performs the aging process and will continuously remove aging
records. The aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit
[2].
Forwarding
The KSZ8893FQL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 7 shows
stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table
for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning
tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port-to-forward 2” (PTF2), as shown in
Figure 8. The packet is sent to PTF2.
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Figure 7. Destination Address Lookup Flow Chart, Stage 1
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Figure 8. Destination Address Resolution Flow Chart, Stage 2
The KSZ8893FQL will not forward the following packets:
1. Error packets
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegally sized packet
errors.
2. IEEE802.3x PAUSE frames
KSZ8893FQL intercepts these packets and performs full duplex flow control accordingly.
3. "Local" packets
Based on destination address (DA) lookup. If the destination port from the look-up table matches the port from
which the packet originated, the packet is defined as "local."
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Switching Engine
The KSZ8893FQL features a high-performance switching engine that moves data to and from the MACs’ packet
buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32kB internal frame buffer. This buffer pool is shared between all three ports. There are a
total of 256 buffers available. Each buffer is sized at 128 bytes.
MAC Operation
The KSZ8893FQL strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
Back-Off Algorithm
The KSZ8893FQL implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional
"aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending upon the switch
configuration for register 4 (0x04) bit [3].
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
Illegal Frames
The KSZ8893FQL discards frames less than 64 bytes, and can be programmed to accept frames up to 1518 bytes,
1536 bytes or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since the
KSZ8893FQL supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Full Duplex Flow Control
The KSZ8893FQL supports standard IEEE 802.3x flow control frames on both the transmit and the receive sides.
On the receive side, if the KSZ8893FQL receives a pause control frame, then the KSZ8893FQL will not transmit the
next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received
before the current timer expires, then the timer will be updated with the new value in the second pause frame. During
this period (while it is flow controlled), only flow control packets from the KSZ8893FQL are transmitted.
On the transmit side, the KSZ8893FQL has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based upon availability of the system resources, including available buffers, available transmit queues
and available receive queues.
The KSZ8893FQL will flow control a port that has just received a packet if the destination port resource is busy. The
KSZ8893FQL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802.3x
standard. Once the resource is freed up, the KSZ8893FQL then sends out the other flow control frame (XON) with zero
pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the
flow control mechanism from being constantly activated and deactivated.
The KSZ8893FQL flow controls all ports if the receive queue becomes full.
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as full duplex flow control. If backpressure is required, then the KSZ8893FQL sends preambles
to defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8893FQL
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thereby keeping other stations in a ‘carrier sense’ deferred state. If the port has
packets to send during a backpressure situation, then the carrier sense type backpressure is interrupted and those
packets are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is
reactivated again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is
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skipped and carrier sense is generated immediately, thereby reducing the chance of further collisions and carrier sense
is maintained to prevent packet reception.
To ensure no packet loss in 10 Base-T or 100 Base-TX half duplex modes, the user must enable the following:
1. Aggressive back-off (register 3 (0x03), bit [0])
2. No excessive collision drop (register 4 (0x04), bit [3])
Note: These bits are not set as defaults, as this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8893FQL has an intelligent option to protect the switch system from receiving too many broadcast packets. As
the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources
(bandwidth and available space in transmit queues) may be utilized. The KSZ8893FQL has the option to include
“multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be
enabled or disabled on a per port basis. The rate is based upon a 67ms interval for 100BT and a 500ms interval for
10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the
number of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting
is 0x63 (99 decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Note: 148,800 frames/sec is based on 64-byte block of packets in 100Base-TX with 12 bytes of IPG and 8 bytes of
preamble between two packets.
MII Interface Operation
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by the KSZ8893FQL is connected to the
device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for
reception. The following table describes the signals used by the MII bus.
PHY-Mode Connections
MAC-Mode Connections
External MAC
Controller Signals
KSZ8893FQL
PHY Signals
Pin
Descriptions
External
PHY Signals
KSZ8893FQL
MAC Signals
MTXEN
SMTXEN
Transmit enable
MTXEN
SMRXDV
MTXER
SMTXER
Transmit error
MTXER
(not used)
MTXD3
SMTXD[3]
Transmit data bit 3
MTXD3
SMRXD[3]
MTXD2
SMTXD[2]
Transmit data bit 2
MTXD2
SMRXD[2]
MTXD1
SMTXD[1]
Transmit data bit 1
MTXD1
SMRXD[1]
MTXD0
SMTXD[0]
Transmit data bit 0
MTXD0
SMRXD[0]
MTXC
SMTXC
Transmit clock
MTXC
SMRXC
MCOL
SCOL
Collision detection
MCOL
SCOL
MCRS
SCRS
Carrier sense
MCRS
SCRS
MRXDV
SMRXDV
Receive data valid
MRXDV
SMTXEN
MRXER
(not used)
Receive error
MRXER
SMTXER
MRXD3
SMRXD[3]
Receive data bit 3
MRXD3
SMTXD[3]
MRXD2
SMRXD[2]
Receive data bit 2
MRXD2
SMTXD[2]
MRXD1
SMRXD[1]
Receive data bit 1
MRXD1
SMTXD[1]
MRXD0
SMRXD[0]
Receive data bit 0
MRXD0
SMTXD[0]
MRXC
SMRXC
Receive clock
MRXC
SMTXC
Table 8. MII Signals
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The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at one-quarter the
network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error has
occurred during transmission. Similarly, the receive side has signals that convey when the data is valid and without
physical layer errors. For half-duplex operation, the SCOL signal indicates if a collision has occurred during
transmission.
The KSZ8893FQL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the
KSZ8893FQL. So, for PHY mode operation, if the device interfacing with the KSZ8893FQL has an MRXER input pin, it
needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8893FQL has an MTXER
input pin, it also needs to be tied low.
RMII Interface Operation
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
1. Supports 10Mbps and 100Mbps data rates.
2. Uses a single 50 MHz clock reference (provided externally).
3. Provides independent 2-bit wide (di-bit) transmit and receive data paths.
4. Contains two distinct groups of signals: one for transmission and the other for reception
The RMII provided by the KSZ8893FQL is connected to the device’s third MAC. It complies with the RMII Specification.
The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal
description.
RMII
Signal Name
Direction
(with respect
to the PHY)
Direction
(with respect
to the MAC)
REF_CLK
Input
Input or
Output
CRS_DV
Output
Input
RXD1
Output
Input
Receive data bit 1
SMRXD[1] (output)
RXD0
Output
Input
Receive data bit 0
SMRXD[0] (output)
TX_EN
Input
Output
Transmit enable
SMTXEN (input)
TXD1
Input
Output
Transmit data bit 1
SMTXD[1] (input)
TXD0
Input
Output
Transmit data bit 0
SMTXD[0] (input)
RX_ER
Output
Input
(not required)
Receive error
(not used)
RMII
Signal Description
Synchronous 50 MHz clock
reference for receive, transmit
and control interface
Carrier sense/
Receive data valid
KSZ8893FQL RMII
Signal (direction)
REFCLK (input)
SMRXDV (output)
SMTXER* (input)
---
---
---
---
* Connects to RX_ER
signal of RMII PHY device
Table 9. RMII Signal Description
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The KSZ8893FQL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames
from RMII PHY devices, the SMTXER input signal of the KSZ8893FQL is connected to the RXER output signal of the
RMII PHY device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, tie MII signals, SMTXD[3:2] and SMTXER, to ground if they are not used.
The KSZ8893FQL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8893FQL
devices to be connected back-to-back. The following table shows the KSZ8893FQL RMII pin connections with an
external RMII PHY and an external RMII MAC, such as another KSZ8893FQL device.
KSZ8893FQL
PHY-MAC Connections
External
KSZ8893FQL
MAC Signals
PHY Signals
Pin
Descriptions
KSZ8893FQL
MAC-MAC Connections
External
KSZ8893FQL
MAC Signals
MAC Signals
REF_CLK
REFCLK
Reference Clock
REFCLK
REF_CLK
TX_EN
SMRXDV
SMRXDV
CRS_DV
TXD1
SMRXD[1]
Carrier sense/
Receive data valid
Receive data bit 1
SMRXD[1]
RXD1
TXD0
SMRXD[0]
Receive data bit 0
SMRXD[0]
RXD0
CRS_DV
SMTXEN
Transmit enable
SMTXEN
TX_EN
RXD1
SMTXD[1]
Transmit data bit 1
SMTXD[1]
TXD1
RXD0
SMTXD[0]
Transmit data bit 0
SMTXD[0]
TXD0
RX_ER
SMTXER
Receive error
(not used)
(not used)
Table 10. RMII Signal Connections
SNI (7-Wire) Operation
The serial network interface (SNI) or 7-wire is compatible with some controllers used for network layer protocol
processing. In SNI mode, the KSZ8893FQL acts like a PHY and the external controller functions as the MAC. The
KSZ8893FQL can interface directly with external controllers using the 7-wire interface. These signals are divided into
two groups, one for transmission and the other for reception. The signals involved are described in the following table.
Pin Descriptions
External MAC
KSZ8893FQL
Controller Signals
PHY Signals
Transmit enable
TXEN
SMTXEN
Serial transmit data
TXD
SMTXD[0]
Transmit clock
TXC
SMTXC
Collision detection
COL
SCOL
Carrier sense
CRS
SMRXDV
Serial receive data
RXD
SMRXD[0]
Receive clock
RXC
SMRXC
Table 11. SNI Signals
The SNI interface is a bit wide data interface and therefore, runs at the network bit rate (not encoded). An additional
signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when
the data is valid.
For half duplex operation, the SCOL signal is used to indicate that a collision has occurred during transmission.
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MII Management (MIIM) Interface
The KSZ8893FQL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8893FQL. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
•
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
•
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893FQL device.
•
Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM
registers [29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5 MHz.
The following table depicts the MII Management Interface frame format.
Read
Write
Preamble
Start of
Frame
Read/Write
OP Code
32 1’s
32 1’s
01
01
10
01
PHY
Address
Bits [4:0]
AAAAA
AAAAA
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Data
Bits [15:0]
Idle
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Z
Z
Table 12. MII Management Interface Frame Format
Serial Management Interface (SMI)
The SMI is the KSZ8893FQL non-standard MIIM interface that provides access to all KSZ8893FQL configuration
registers. This interface allows an external device to completely monitor and control the states of the KSZ8893FQL.
The SMI interface consists of the following:
•
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
•
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893FQL device.
•
Access to all KSZ8893FQL configuration registers. Register access includes the Global, Port and Advanced
Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers [0:5] and custom
MIIM registers [29, 31].
The following table depicts the SMI frame format.
Read
Write
Preamble
Start of
Frame
Read/Write
OP Code
32 1’s
32 1’s
01
01
00
00
PHY
Address
Bits [4:0]
1xRRR
0xRRR
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Data
Bits [15:0]
Idle
Z0
10
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Z
Z
Table 13. Serial Management Interface (SMI) Frame Format
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence, can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8893FQL registers 0-141 (0x00 – 0x8D), the following applies:
•
PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
•
Registers are 8 data bits wide.
– For read operation, data bits [15:8] are read back as 0’s.
– For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
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SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
Repeater Mode
The KSZ8893FQL supports repeater mode in 100Base-TX Half Duplex mode. In repeater mode, all ingress packets are
broadcast to the other two ports. MAC address checking and learning are disabled.
Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured
to 100Base-TX Half Duplex mode. Additionally, both PHY ports need to have auto-negotiation disabled.
The latency between the two PHY ports is 270 ns (minimum) and 310 ns (maximum). The 40 ns difference is one clock
skew (one 25 MHz clock period) between reception and transmission. Latency is defined as the time from the first bit of
the Destination Address (DA) entering the ingress port to the first bit of the DA exiting the egress port.
Advanced Switch Functions
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2), can be configured in one of the five spanning tree states via “transmit enable”,
“receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The
following table shows the port setting and software actions taken for each of the five spanning tree states.
Disable State
The port should not
forward or receive
any packets.
Learning is
disabled.
Blocking State
Only packets to the
processor are
forwarded.
Learning is
disabled.
Listening State
Only packets to
and from the
processor are
forwarded.
Learning is
disabled.
Learning State
Only packets to
and from the
processor are
forwarded.
Learning is
enabled.
Forwarding State
Packets are
forwarded and
received normally.
Learning is
enabled.
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable = 0”
Port Setting
“transmit
enable = 1,
receive
enable = 1,
learning
disable = 0”
Software Action
The processor should not send any packets to the port. The switch may still send
specific packets to the processor (packets that match some entries in the “static
MAC table” with “overriding bit” set) and the processor should discard those
packets. Address learning is disabled on the port in this state.
Software Action
The processor should not send any packets to the port(s) in this state. The
processor should program the “Static MAC table” with the entries that it needs to
receive (for example, BPDU packets). The “overriding” bit should also be set so that
the switch will forward those specific packets to the processor. Address learning is
disabled on the port in this state.
Software Action
The processor should program the “Static MAC table” with the entries that it needs
to receive (for example, BPDU packets). The “overriding” bit should be set so that
the switch will forward those specific packets to the processor. The processor may
send packets to the port(s) in this state. See “Special Tagging Mode” for details.
Address learning is disabled on the port in this state.
Software Action
The processor should program the “Static MAC table” with the entries that it needs
to receive (for example, BPDU packets). The “overriding” bit should be set so that
the switch will forward those specific packets to the processor. The processor may
send packets to the port(s) in this state. See “Special Tagging Mode” for details.
Address learning is enabled on the port in this state.
Software Action
The processor programs the “Static MAC table” with the entries that it needs to
receive (for example, BPDU packets). The “overriding” bit is set so that the switch
forwards those specific packets to the processor. The processor can send packets
to the port(s) in this state. See “Special Tagging Mode” for details. Address learning
is enabled on the port in this state.
Table 14. Spanning Tree States
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Special Tagging Mode
Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other
applications. Special Tagging, similar to 802.1Q Tagging, requires software to change network drivers to
insert/modify/strip/interpret the special tag. This mode is enabled by setting both register 11 bit [0] and register 48 bit [2]
to ‘1’.
802.1Q Tag Format
TPID (tag protocol identifier, 0x8100) + TCI
Special Tag Format
STPID (special tag identifier, 0x810 +
4 bit for “port mask”) + TCI
Table 15. Special Tagging Mode Format
The STPID is only seen and used by the port 3 interface, which should be connected to a processor. Packets from the
processor to the switch’s port 3 should be tagged with the STPID and the port mask, defined as follows:
“0001”, forward packet to port 1 only
“0010”, forward packet to port 2 only
“0011”, broadcast packet to port 1 and port 2
Packets with normal tags (“0000” port masks) will use KSZ8893FQL internal MAC table look-up to determine the
forwarding port(s). Also, if packets from the processor are not tagged, the KSZ8893FQL will treat them as normal
packets and use internal MAC table lookup to determine the forwarding port(s).
The KSZ8893FQL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port
setting, regardless of port states (disable, blocking, listening, and learning). The table below shows the processor to
switch egress rules when dealing with STPID.
Ingress Tag Field
TX port “tag
insertion”
TX port “tag
removal”
(0x810 + port mask)
0
0
(0x810 + port mask)
0
1
(0x810 + port mask)
1
0
(0x810 + port mask)
1
1
Not Tagged
Don’t care
Don’t care
Egress Action to Tag Field
- Modify tag field to 0x8100
- Recalculate CRC
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port VID if null VID
- (STPID + TCI) will be removed
- Padding to 64 bytes if necessary
- Recalculate CRC
- Modify tag field to 0x8100
- Recalculate CRC
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port VID if null VID
- Modify tag field to 0x8100
- Recalculate CRC
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port VID if null VID
- Determined by the Dynamic MAC Address Table
Table 16. STPID Egress Rules (Processor to Switch Port 3)
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For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the
packets were received on, defined as follows:
“0001”, packet from port 1
“0010”, packet from port 2
No port mask values, other than the previous two defined ones, should be received in this direction in Special Tagging
Mode. The switch to processor egress rules are defined as follows:
Ingress Packets
Tagged with 0x8100 + TCI
Not tagged
Egress Action to Tag Field
- Modify TPID to 0x810 + “port mask”, which indicates source port
- No change to TCI if VID is not null
- Replace null VID with ingress port VID
- Recalculate CRC
- Insert TPID to 0x810 + “port mask”, which indicates source port
- Insert TCI with ingress port VID
- Recalculate CRC
Table 17. STPID Egress Rules (Switch Port 3 to Processor)
IGMP Support
For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8893FQL provides two components:
IGMP Snooping
The KSZ8893FQL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are
identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol
version number = 0x2.
Multicast Address Insertion in the Static MAC Table
Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the subscribed
ports, instead of broadcasting to all ports.
To enable IGMP support, set register 5 bit [6] to ‘1’. Also, Special Tagging Mode needs to be enabled, so that the
processor knows which port the IGMP packet was received on. This is achieved by setting both register 11 bit [0] and
register 48 bit [2] to ‘1’.
IPv6 MLD Snooping
The KSZ8893FQL traps IPv6 Multicast Listener Discovery (MLD) packets and forwards them only to processor (port 3).
MLD snooping is controlled by register 5 bit 5 (MLD snooping enable) and register 5 bit 4 (MLD option).
With MLD snooping enabled, the KSZ8893FQL traps packets that meet all of the following conditions:
•
IPv6 multicast packets
•
Hop count limit = 1
• IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58)
If the MLD option bit is set to “1”, the KSZ8893FQL traps packets with the following additional condition:
• IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60)
For MLD snooping, Special Tagging Mode also needs to be enabled, so that the processor knows which port the MLD
packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.
Port Mirroring Support
KSZ8893FQL supports “Port Mirroring” comprehensively as:
“receive only” mirror on a port
All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be
“receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2
after the internal lookup. The KSZ8893FQL forwards the packet to both port 2 and port 3. The KSZ8893FQL
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can optionally even forward “bad” received packets to the “sniffer port”.
“transmit only” mirror on a port
All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to be
“transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port
1 after the internal lookup. The KSZ8893FQL forwards the packet to both port 1 and port 3.
“receive and transmit” mirror on two ports
All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the
“AND” feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is
programmed to be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port
1 is destined to port 2 after the internal lookup. The KSZ8893FQL forwards the packet to both port 2 and port 3.
Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer
port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively.
IEEE 802.1Q VLAN Support
The KSZ8893FQL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q
specification. KSZ8893FQL provides a 16-entry VLAN Table, which converts the 12-bits VLAN ID (VID) to the 4-bits
Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is
used for look-up. In VLAN mode, the look-up process starts with VLAN Table lookup to determine whether the VID is
valid. If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved
for further lookup. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID +
Source Address (FID+SA) are used for address learning.
DA found in
Static MAC
Table?
Use FID flag?
FID match?
DA+FID found
in Dynamic
MAC Table?
No
Don’t care
Don’t care
No
No
Don’t care
Don’t care
Yes
Yes
0
Don’t care
Don’t care
Yes
1
No
No
Yes
1
No
Yes
Yes
1
Yes
Don’t care
Action
Broadcast to the membership ports defined
in the VLAN Table bits [18:16]
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Send to the destination port(s) defined in the
Static MAC Address Table bits [50:48]
Broadcast to the membership ports defined
in the VLAN Table bits [18:16]
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Send to the destination port(s) defined in the
Static MAC Address Table bits [50:48]
Table 18. FID+DA Lookup in VLAN Mode
FID+SA found in
Dynamic MAC Table?
No
Yes
Action
Learn and add FID+SA to the Dynamic MAC Address Table
Update time stamp
Table 19. FID+SA Lookup in VLAN Mode
Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the
KSZ8893FQL. These features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports 1, 2
and 3, respectively.
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QoS Priority Support
The KSZ8893FQL provides Quality of Service (QoS) for applications such as VoIP and video conferencing. Offering
four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest
priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32 and 48 is used to enable split transmit
queues for ports 1, 2 and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets
have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four
priority queues. This global option is set and explained in bit [3] of register 5.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received
at the high priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the
corresponding transmit queue is split. Bits [4:3] of registers 16, 32 and 48 are used to enable port-based priority for
ports 1, 2 and 3, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8893FQL examines the ingress (incoming) packets to determine whether they are
tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value,
as specified by the registers 12 and 13. The “priority mapping” value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Figure 9. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively.
The KSZ8893FQL provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI),
is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets
{19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KSZ8893FQL will not add tags to already tagged
packets.
Tag Removal is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port,
tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8893FQL will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8893FQL to set the “User Priority Ceiling” at
any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the
ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority Ceiling” is
enabled by bit [3] of registers 17, 33 and 49 for ports 1, 2 and 3, respectively.
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DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to
determine priority.
Rate Limiting Support
The KSZ8893FQL supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and
on the “transmit side” on a per port basis. For 10Base-T, a rate setting above 10 Mbps means the rate is not limited. On
the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control
Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up
Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or
Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8893FQL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. The KSZ8893FQL counts the data rate from those selected type of frames.
Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore, slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in
the static table, it is also not learned in the dynamic MAC table. The KSZ8893FQL is then configured with the option to
either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register
14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8893FQL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8893FQL is typically programmed using an EEPROM. If no EEPROM is present, the
KSZ8893FQL is configured using its default register settings. Some default settings are configured via strap-in pin
options. The strap-in pins are indicated in the “KSZ8893FQL Pin Description and I/O Assignment” table.
I2C Master Serial Bus Configuration
With an additional I2C (“2-wire”) EEPROM, the KSZ8893FQL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For KSZ8893FQL I2C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as
defined in the KSZ8893FQL register map) with the exception of the “Read Only” status registers. After the de-assertion
of reset, the KSZ8893FQL sequentially reads in the configuration data for all 121 registers, starting from register 0. The
configuration access time (tprgm) is less than 15 ms, as depicted in the following figure.
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Figure 10. KSZ8893FQL EEPROM Configuration Timing Diagram.
The following is a sample procedure for programming the KSZ8893FQL with a pre-configured EEPROM:
1. Connect the KSZ8893FQL to the EEPROM by joining the SCL and SDA signals of the respective devices. For
the KSZ8893FQL, SCL is pin 97 and SDA is pin 98.
2. Enable I2C master mode by setting the KSZ8893FQL strap-in pins, PS[1:0] (pins 100 and 101, respectively) to
“00”.
3. Check to ensure that the KSZ8893FQL reset signal input, RST_N (pin 67), is properly connected to the external
reset source at the board level.
4. Program the desired configuration data into the EEPROM.
5. Place the EEPROM on the board and power up the board.
6. Assert an active-low reset to the RST_N pin of the KSZ8893FQL. After reset is de-asserted, the KSZ8893FQL
begins reading the configuration data from the EEPROM. The KSZ8893FQL checks that the first byte read from
the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not, EEPROM configuration
access is denied and all other data sent from the EEPROM is ignored by the KSZ8893FQL. The configuration
access time (tprgm) is less than 15ms.
Note: For proper operation, check to ensure that the KSZ8893FQL PWRDN input signal (pin 36) is not asserted during
the reset operation. The PWRDN input is active low.
I2C Slave Serial Bus Configuration
In managed mode, the KSZ8893FQL can be configured as an I2C slave device. In this mode, an I2C master device
(external controller/CPU) has complete programming access to the KSZ8893FQL’s 142 registers. Programming access
includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC
Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly accessed via
registers 121 to 131.
In I2C slave mode, the KSZ8893FQL operates like other I2C slave devices. Addressing the KSZ8893FQL’s 8-bit
registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of I2C read/write operations
and related timing information can be found in the AT24C02 Datasheet.
Two fixed 8-bit device addresses are used to address the KSZ8893FQL in I2C slave mode. One is for read; the other is
for write. The addresses are as follow:
1011_1111
1011_1110
The following is a sample procedure for programming the KSZ8893FQL using the I2C slave serial bus:
1. Enable I2C slave mode by setting the KSZ8893FQL strap-in pins PS[1:0] (pins 100 and 101, respectively) to
“01”.
2. Power up the board and assert reset to the KSZ8893FQL. After reset, the “Start Switch” bit (register 1 bit [0]) is
set to ‘0’.
3. Configure the desired register settings in the KSZ8893FQL, using the I2C write operation.
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4. Read back and verify the register settings in the KSZ8893FQL, using the I2C read operation.
5. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893FQL with the programmed settings.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after a ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8893FQL can be configured as a SPI slave device. In this mode, a SPI master device
(external controller/CPU) has complete programming access to the KSZ8893FQL’s 142 registers. Programming access
includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC
Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly accessed via
registers 121 to 131.
The KSZ8893FQL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write.
SPI multiple read and multiple write are also supported by the KSZ8893FQL to expedite register read back and register
configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8893FQL SPIS_N input pin (SPI Slave
Select signal) low after a byte (a register) is read. After the read, the KSZ8893FQL’s internal address counter
increments automatically to the next byte (next register). The next byte at the next register address is shifted out onto
the KSZ8893FQL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-asserting
the SPIS_N signal to the KSZ8893FQL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8893FQL SPIS_N input pin
low after a byte (a register) is written. The KSZ8893FQL internal address counter increments automatically to the next
byte (next register) after the write. The next byte that is sent from the master device to the KSZ8893FQL SDA input pin
is written to the next register address. SPI multiple write continues until the SPI master device terminates it by deasserting the SPIS_N signal to the KSZ8893FQL.
For both SPI multiple read and multiple write, the KSZ8893FQL internal address counter wraps back to register address
zero once the highest register address is reached. This feature allows all 142 KSZ8893FQL registers to be read, or
written with a single SPI command from any initial register address.
The KSZ8893FQL is capable of supporting a 5MHz SPI bus.
The following is a sample procedure for programming the KSZ8893FQL using the SPI bus:
1. At the board level, connect the KSZ8893FQL pins as follows:
KSZ8893FQL Pin #
99
97
98
96
KSZ8893FQL Signal Name
SPIS_N
SCL
(SPIC)
SDA
(SPID)
SPIQ
External Processor Signal Description
SPI Slave Select
SPI Clock
SPI Data
(Master output; Slave input)
SPI Data
(Master input; Slave output)
Table 20. KSZ8893FQL SPI Connections
2. Enable SPI slave mode by setting the KSZ8893FQL strap-in pins PS[1:0] (pins 100 and 101, respectively) to
“10”.
3. Power up the board and assert reset to the KSZ8893FQL.
After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’.
4. Configure the desired register settings in the KSZ8893FQL, using the SPI write or multiple write command.
5. Read back and verify the register settings in the KSZ8893FQL, using the SPI read or multiple read command.
6. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893FQL with the programmed settings.
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Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after a ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The
read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising
edge of SPIC.
Figure 11. SPI Write Data Cycle
Figure 12. SPI Read Data Cycle
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Figure 13. SPI Multiple Write
Figure 14. SPI Multiple Read
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KSZ8893FQL/FQLI
Loopback Support
The KSZ8893FQL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY
ports needs to be set to 100Base-TX. Two types of loopback are supported: Far-end Loopback and Near-end
(Remote) Loopback.
Far-end Loopback
Far-end loopback is conducted between the KSZ8893FQL’s two PHY ports. The loopback path starts at the
“Originating.” PHY port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at
the “Originating” PHY port’s transmit outputs (TXP/TXM).
Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 0, bit [14] can be used to enable far-end loopback.
The far-end loopback path is illustrated in the following figure.
Figure 15. Far-End Loopback Path
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KSZ8893FQL/FQLI
Near-end (Remote) Loopback
Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8893FQL. The loopback path
starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the
PHY port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers 26 and 42 is used to enable near-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 31, bit [1] can be used to enable near-end loopback.
The near-end loopback paths are illustrated in the following figure.
Figure 16. Near-end (Remote) Loopback Path.
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KSZ8893FQL/FQLI
MII Management (MIIM) Registers
The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C, and SMI interfaces can
also be used to access some of these registers. The latter three interfaces use a different mapping mechanism than the
MIIM interface.
The “PHYADs” by defaults are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2). Additionally, these
“PHYADs” can be programmed to the PHY addresses specified in bits[7:3] of Register 15 (0x0F): Global Control 13.
The “REGAD” supported are 0x0-0x5, 0x1D and 0x1F.
Register Name
PHYAD = 0x1, REGAD = 0x0
PHYAD = 0x1, REGAD = 0x1
PHYAD = 0x1, REGAD = 0x2
PHYAD = 0x1, REGAD = 0x3
PHYAD = 0x1, REGAD = 0x4
PHYAD = 0x1, REGAD = 0x5
PHYAD = 0x1, 0x6 – 0x1C
PHYAD = 0x1, 0x1D
PHYAD = 0x1, 0x1E
PHYAD = 0x1, 0x1F
PHYAD = 0x2, REGAD = 0x0
PHYAD = 0x2, REGAD = 0x1
PHYAD = 0x2, REGAD = 0x2
PHYAD = 0x2, REGAD = 0x3
PHYAD = 0x2, REGAD = 0x4
PHYAD = 0x2, REGAD = 0x5
PHYAD = 0x2, 0x6 – 0x1C
PHYAD = 0x2, 0x1D
PHYAD = 0x2, 0x1E
PHYAD = 0x2, 0x1F
July 2006
Description
PHY1 Basic Control Register
PHY1 Basic Status Register
PHY1 Physical Identifier I
PHY1 Physical Identifier II
PHY1 Auto-Negotiation Advertisement Register
PHY1 Auto-Negotiation Link Partner Ability Register
PHY1 Not supported
PHY1 LinkMD Control/Status
PHY1 Not supported
PHY1 Special Control/Status
PHY2 Basic Control Register
PHY2 Basic Status Register
PHY2 Physical Identifier I
PHY2 Physical Identifier II
PHY2 Auto-Negotiation Advertisement Register
PHY2 Auto-Negotiation Link Partner Ability Register
PHY2 Not supported
PHY2 LinkMD Control/Status
PHY2 Not supported
PHY2 Special Control/Status
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PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control
Bit
15
14
Name
Soft reset
Loopback
R/W
RO
R/W
13
Force 100
R/W
12
AN enable
R/W
11
Power down
R/W
10
9
Isolate
Restart AN
RO
R/W
8
Force full duplex
R/W
7
6
5
Collision test
Reserved
Hp_mdix
RO
RO
R/W
4
Force MDI
R/W
3
Disable MDIX
R/W
2
Disable far-end fault
R/W
1
Disable transmit
R/W
0
Disable LED
R/W
July 2006
Description
NOT SUPPORTED
1 = Perform loopback, as indicated:
Port 1 Loopback (reg. 29, bit 0 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
Port 2 Loopback (reg. 45, bit 0 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Auto-negotiation enabled
0 = Auto-negotiation disabled
1 = Power down
0 = Normal operation
NOT SUPPORTED
1 = Restart auto-negotiation
0 = Normal operation
1 = Full duplex
0 = Half duplex
NOT SUPPORTED
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
1 = Force MDI (transmit on RXP / RXM pins)
0 = Normal operation (transmit on TXP / TXM pins)
1 = Disable auto MDI-X
0 = Enable auto MDI-X
1 = Disable far-end fault detection
0 = Normal operation
1 = Disable transmit
0 = Normal operation
1 = Disable LED
0 = Normal operation
55
Default
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Reference
Reg. 29, bit 0
Reg. 45, bit 0
Reg. 28, bit 6
Reg. 44, bit 6
Reg. 28, bit 7
Reg. 44, bit 7
Reg. 29, bit 3
Reg. 45, bit 3
Reg. 29, bit 5
Reg. 45, bit 5
Reg. 28, bit 5
Reg. 44, bit 5
Reg. 31, bit 7
Reg. 47, bit 7
Reg. 29, bit 1
Reg. 45, bit 1
Reg. 29, bit 2
Reg. 45, bit 2
Reg. 29, bit 4
Reg. 29, bit 6
Reg. 45, bit 6
Reg. 29, bit 7
Reg. 45, bit 7
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KSZ8893FQL/FQLI
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status
Bit
15
14
Name
T4 capable
100 Full capable
R/W
RO
RO
13
100 Half capable
RO
12
10 Full capable
RO
11
10 Half capable
RO
RO
RO
5
Reserved
Preamble
suppressed
AN complete
4
Far-end fault
RO
3
AN capable
RO
2
Link status
RO
1
0
Jabber test
Extended capable
RO
RO
10-7
6
RO
Description
0 = Not 100 Base-T4 capable
1 = 100Base-TX full duplex capable
0 = Not capable of 100Base-TX full duplex
1 = 100Base-TX half duplex capable
0 = Not 100Base-TX half duplex capable
1 = 10Base-T full duplex capable
0 = Not 10Base-T full duplex capable
1 = 10Base-T half duplex capable
0 = Not 10Base-T half duplex capable
Default
0
1
Reference
1
Always 1
1
Always 1
1
Always 1
Always 1
0000
0
NOT SUPPORTED
1 = Auto-negotiation complete
0 = Auto-negotiation not completed
1 = Far-end fault detected
0 = No far-end fault detected
1 = Auto-negotiation capable
0 = Not auto-negotiation capable
1 = Link is up
0 = Link is down
NOT SUPPORTED
0 = Not extended register capable
0
0
1
0
Reg. 30, bit 6
Reg. 46, bit 6
Reg. 31, bit 0
Reg. 28, bit 7
Reg. 44, bit 7
Reg. 30, bit 5
Reg. 46, bit 5
0
0
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High
Bit
15-0
Name
PHYID high
R/W
RO
Description
High order PHYID bits
Default
0x0022
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low
Bit
15-0
July 2006
Name
PHYID low
R/W
RO
Description
Low order PHYID bits
56
Default
0x1430
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KSZ8893FQL/FQLI
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability
Bit
15
14
13
12-11
10
Name
Next page
Reserved
Remote fault
Reserved
Pause
R/W
RO
RO
RO
RO
R/W
9
8
Reserved
Adv 100 Full
R/W
R/W
7
Adv 100 Half
R/W
6
Adv 10 Full
R/W
5
Adv 10 Half
R/W
Selector field
RO
4-0
Description
NOT SUPPORTED
NOT SUPPORTED
1 = Advertise pause ability
0 = Do not advertise pause ability
1 = Advertise 100 full duplex ability
0 = Do not advertise 100 full duplex ability
1 = Advertise 100 half duplex ability
0 = Do not advertise 100 half duplex ability
1 = Advertise 10 full duplex ability
0 = Do not advertise 10 full duplex ability
1 = Advertise 10 half duplex ability
0 = Do not advertise 10 half duplex ability
802.3
Default
0
0
0
00
1
0
1
1
1
1
Reference
Reg. 28, bit 4
Reg. 44, bit 4
Reg. 28, bit 3
Reg. 44, bit 3
Reg. 28, bit 2
Reg. 44, bit 2
Reg. 28, bit 1
Reg. 44, bit 1
Reg. 28, bit 0
Reg. 44, bit 0
00001
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability
Bit
15
14
13
12-11
10
Name
Next page
LP ACK
Remote fault
Reserved
Pause
R/W
RO
RO
RO
RO
RO
Link partner pause capability
Default
0
0
0
00
0
9
8
Reserved
Adv 100 Full
RO
RO
Link partner 100 full capability
0
0
7
Adv 100 Half
RO
Link partner 100 half capability
0
6
Adv 10 Full
RO
Link partner 10 full capability
0
5
Adv 10 Half
RO
Link partner 10 half capability
0
Reserved
RO
4-0
July 2006
Description
NOT SUPPORTED
NOT SUPPORTED
NOT SUPPORTED
Reference
Reg. 30, bit 4
Reg. 46, bit 4
Reg. 30, bit 3
Reg. 46, bit 3
Reg. 30, bit 2
Reg. 46, bit 2
Reg. 30, bit 1
Reg. 46, bit 1
Reg. 30, bit 0
Reg. 46, bit 0
00000
57
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status
Bit
15
Name
Vct_enable
R/W
R/W
(SC)
14-13
Vct_result
RO
12
Vct 10M Short
RO
11-9
8-0
Reserved
Vct_fault_count
RO
RO
Description
1 = Enable cable diagnostic. After VCT test has
completed, this bit will be self-cleared.
0 = Indicate cable diagnostic test (if enabled) has
completed and the status information is valid for read.
00 = Normal condition
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failed
1 = Less than 10 meter short
Default
0
Reference
Reg. 26, bit 4
Reg. 42, bit 4
00
Reg 26, bit[6:5]
Reg 42, bit[6:5]
0
Reg. 26, bit 7
Reg. 42, bit 7
Reserved
Distance to the fault.
It’s approximately 0.4m*vct_fault_count[8:0]
000
{0,
(0x00)}
{(Reg. 26, bit
0), (Reg. 27,
bit[7:0])}
{(Reg. 42, bit
0), (Reg. 43,
bit[7:0])}
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status
Bit
15-6
Name
Reserved
R/W
RO
Description
Reserved
5
Polrvs
RO
4
MDI-X status
RO
3
Force_lnk
R/W
2
Pwrsave
R/W
1
Remote Loopback
R/W
0
Reserved
R/W
1 = Polarity is reversed
0 = Polarity is not reversed
1 = MDI-X
0 = MDI
1 = Force link pass
0 = Normal Operation
0 = Enable power saving
1 = Disable power saving
1 = Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
0 = Normal Operation
Reserved
Do not change the default value.
July 2006
58
Default
{(0x00),
00}
0
0
0
1
0
Reference
Reg. 31, bit 5
Reg. 47, bit 5
Reg. 30, bit 7
Reg. 46, bit 7
Reg. 26, bit 3
Reg. 42, bit 3
Reg. 26, bit 2
Reg. 42, bit 2
Reg. 26, bit 1
Reg. 42, bit 1
0
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers)
Global Registers
Register (Decimal)
0-1
2-15
Register (Hex)
0x00-0x01
0x02-0x0F
Description
Chip ID Registers
Global Control Registers
Register (Hex)
0x10-0x1D
0x1E-0x1F
0x20-0x2D
0x2E-0x2F
0x30-0x39
0x3A-0x3E
0x3F
Description
Port 1 Control Registers, including MII PHY Registers
Port 1 Status Registers, including MII PHY Registers
Port 2 Control Registers, including MII PHY Registers
Port 2 Status Registers, including MII PHY Registers
Port 3 Control Registers
Reserved
Port 3 Status Register
Port Registers
Register (Decimal)
16-29
30-31
32-45
46-47
48-57
58-62
63
TS-1000 Media Converter Registers
Register (Decimal)
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
July 2006
Register (Hex)
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
Description
PHY Address
Center Side Status
Center Side Command
PHY-SW Initialize
Loop Back Setup1
Loop Back Setup2
Loop Back Result Counter for CRC Error
Loop Back Result Counter for Timeout
Loop Back Result Counter for Good Packet
Additional Status
Remote Command1
Remote Command2
Remote Command3
Valid MC Packet Transmitted Counter
Valid MC Packet Received Counter
Shadow of Register 0x58h
My Status 1
My Status 2
My Vendor Info (1)
My Vendor Info (2)
My Vendor Info (3)
My Model Info (1)
My Model Info (2)
My Model Info (3)
LNK Partner Status (1)
LNK Partner Status (2)
LNK Partner Vendor Info (1)
LNK Partner Vendor Info (2)
LNK Partner Vendor Info (3)
LNK Partner Model Info (1)
59
M9999-070506-1.0
Micrel, Inc.
Register (Decimal)
94
95
KSZ8893FQL/FQLI
Register (Hex)
0x5E
0x5F
Description
LNK Partner Model Info (2)
LNK Partner Model Info (3)
Advanced Control Registers
Register (Decimal)
96-111
112-117
118-120
121-122
123-131
132
133
134-137
138
139
140-141
Register (Hex)
0x60-0x6F
0x70-0x75
0x76-0x78
0x79-0x7A
0x7B-0x83
0x84
0x85
0x86-0x89
0x8A
0x8B
0x8C-0x8D
Description
TOS Priority Control Registers
Switch Engine’s MAC Address Registers
User Defined Registers
Indirect Access Control Registers
Indirect Data Registers
Digital Testing Status Register
Digital Testing Control Register
Analog Testing Control Registers
Analog Testing Status Register
Analog Testing Control Register
QM Debug Registers
Global Registers
Register 0 (0x00): Chip ID0
Bit
7-0
Name
Family ID
R/W
RO
Description
Chip family
Default
0x88
Description
Chip ID
Revision ID
1 = Start the chip when external pins (PS1, PS0) = (0,1) or (1,0)
or (1,1).
Default
0xA
-
Register 1 (0x01): Chip ID1 / Start Switch
Bit
7-4
3-1
0
Name
Chip ID
Revision ID
Start Switch
R/W
RO
RO
RW
Note: In (PS1, PS0) = (0, 0) mode, the chip will start
automatically after trying to read the external EEPROM. If
EEPROM does not exist, the chip will use pin strapping and
default values for all internal registers. If EEPROM is present, the
contents in the EEPROM will be checked. The switch will check:
(1) Register 0 = 0x88, (2) Register 1 bits [7:4] = 0xA. If this check
is OK, the contents in the EEPROM will override chip registers’
default values.
0 = Chip will not start when external pins (PS1, PS0) = (0,1) or
(1,0) or (1,1).
July 2006
60
M9999-070506-1.0
Micrel, Inc.
KSZ8893FQL/FQLI
Register 2 (0x02): Global Control 0
Bit
7
Name
New Back-off
Enable
R/W
R/W
6-4
Reserved
R/W
3
Pass Flow Control
Packet
R/W
2
Reserved
R/W
1
Reserved
R/W
0
Link Change Age
R/W
Description
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
Reserved
Do not change the default value.
1 = Switch will not filter 802.1x “flow control” packets
0 = Switch will filter 802.1x “flow control” packets
Reserved
Do not change the default value.
Reserved
Do not change the default value.
Link change from “link” to “no link” will cause fast aging (
