KSZ8893MQL/MBL
Integrated 3-Port 10/100 Managed
Switch with PHYs
Rev. 1.6
with patented mixed-signal low-power technology,
three media access control (MAC) units, a highspeed non-blocking switch fabric, a dedicated
address lookup engine, and an on-chip frame buffer
memory.
Both PHY units support 10BASE-T and 100BASETX. In addition, one PHY unit supports 100BASE-FX.
The KSZ8893MQL/MBL comes in a lead-free
package, and is also available in industrial
temperature-grade
KS8893MQLI/MBLI
and
Automotive-grade KSZ8893 MQL AM. (See Ordering
Information).
General Description
The KSZ8893MQL/MBL, a highly integrated layer 2
managed switch, is designed for low port count,
cost-sensitive 10/100 Mbps switch systems. It offers
an extensive feature set that includes rate limiting,
tag/port-based VLAN, QoS priority, management,
management information base (MIB) counters,
RMII/MII/SNI, and CPU control/data interfaces to
effectively address both current and emerging Fast
Ethernet applications.
The KSZ8893MQL/MBL contains two 10/100
transceivers
___________________________________________________________________________________________________
Functional Diagram
HP AUTO
MDIX
10/100
T/TX/FX
PHY 1
10/100
MAC 1
10/100
T/TX
PHY 2
10/100
MAC 2
RMII/MII/
SNI
10/100
MAC 3
SNI
SPI
SPI
MIIM
CONTROL
REGISTERS
SMI
FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY
HP AUTO
MDIX
1K LOOK-UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
MIB
COUNTERS
EEPROM
INTERFACE
I2C
P1 LED[3:0]
P2 LED[3:0]
LED
DRIVERS
STRAP IN
CONFIGURATION
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
February 2010
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KSZ8893MQL/MBL
Features
• Proven Integrated 3-Port 10/100 Ethernet Switch
– 3rd generation switch with three MACs and two
PHYs fully compliant with IEEE 802.3u standard
– Non-blocking switch fabric assures fast packet
delivery by utilizing an 1K MAC address lookup table
and a store-and-forward architecture
– Full duplex IEEE 802.3x flow control (PAUSE) with
force mode option
– Half-duplex back pressure flow control
– HP Auto MDI-X for reliable detection of and correction
for straight-through and crossover cables with disable
and enable option
TM
– Micrel LinkMD TDR-based cable diagnostics permit
identification of faulty copper cabling
– 100BASE-FX support on port 1
– MII interface supports both MAC mode and PHY
mode
– RMII interface support with external 50MHz system
clock
– 7-wire serial network interface (SNI) support for
legacy MAC
– Comprehensive LED Indicator support for link,
activity, full/half duplex and 10/100 speed
• Switch Monitoring Features
– Port mirroring/monitoring/sniffing: ingress and/or
egress traffic to any port or MII
– MIB counters for fully compliant statistics gathering,
34 MIB counters per port
– Loopback modes for remote diagnostic of failure
• Low Power Dissipation:
– Full-chip hardware power-down (register configuration
not saved)
– Per port based software power-save on PHY (idle link
detection, register configuration preserved)
– Voltages: Single power supply: 3.3V
o
o
• Industrial Temperature Range: –40 C to +85 C
• Available in 128-Pin PQFP and 100-ball LFBGA,
Lead- free package
Applications
• Typical
– Media Converter
– FTTx customer premises equipment
– VoIP Phone
– SOHO Residential Gateway
– Broadband Gateway / Firewall / VPN
– Integrated DSL/Cable Modem
– Wireless LAN access point + gateway
– Set-top/Game Box
– Standalone 10/100 switch
• Comprehensive Configuration Register Access
– Serial management interface (SMI) to all internal
registers
– MII management (MIIM) interface to PHY registers
2
– SPI and I C Interface to all internal registers
– I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode
– Control registers configurable on the fly (port-priority,
802.1p/d/q, AN…)
• Upgradeable(1)
– Unmanaged switch with future option to migrate to a
managed solution
– Single PHY alternative with future expansion option
for two ports
• QoS/CoS Packet Prioritization Support
– Per port, 802.1p and DiffServ-based
– Re-mapping of 802.1p priority field per port basis
– Four priority levels
• Industrial
• Advanced Switch Features
– Applications requiring port redundancy and port
monitoring
– Sensor devices in redundant ring topology
– IEEE 802.1q VLAN support for up to 16 groups (fullrange of VLAN IDs)
– VLAN ID tag/untag options, per port basis
– IEEE 802.1p/q tag insertion or removal on a per port
basis (egress)
– Programmable rate limiting at the ingress and egress
on a per port basis
– Broadcast storm protection with % control (global and
per port basis)
– IEEE 802.1d spanning tree protocol support
– Special tagging mode to inform the processor which
ingress port receives the packet
– IGMP snooping (Ipv4) and MLD snooping (Ipv6)
support for multicast packet filtering
– MAC filtering function to forward unknown unicast
packets to specified port
– Double-tagging support
– Support IEEE 802.1w, 802.1t spanning tree
Note:
1. Reduces cost and time of PCB re-spin.
• Low Latency Support
– Repeater mode
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KSZ8893MQL/MBL
Ordering Information
Part Number
Operation
Package
Grade
128-Pin PQFP,
Lead-free
Commercial
Temp. Range
o
o
KSZ8893MQL
0 C to 70 C
KSZ8893MQLI
–40 C to +85 C
KSZ8893MQL AM
-40 C to +85 C
o
o
128-Pin PQFP,
Lead-free
Industrial
o
o
128-Pin PQFP,
Lead-free
Automotive grade
100-Ball LFBGA
Commercial
100-Ball LFBGA
Industrial
o
KSZ8893MBL
o
0 C to 70 C
KSZ8893MBLI
o
o
–40 C to +85 C
Revision History
Revision
Date
Summary of Changes
1.0
6/30/05
Initial release
1.1
11/17/05
Updated ordering information
Updated package information
Updated default register values
Updated current consumption description
Changed device reference in datasheet from KS8893M to KSZ8893MQL
Added repeater mode description
1.2
02/08/07
Modify Table 5. RMII Signal Connections
Add TLA-6T718 to Table 16. Qualified Single Port Magnetics
1.3
06/19/07
Add Thermal Resistance (θJC) to Operating Rating
1.4
10/16/07
Recommend connecting a 100ohm resistor between VDDC and 3.3V
power rail.
1.5
11/05/07
Add the KSZ8893MBL BGA device information.
11/26/07
Modify the Hold time, Output valid in table 25, 26 and Figure 25,26 of MII
interface timing.
12/10/07
07/30/08
09/16/08
02/12/09
February 2010
Add the I2C timing diagram and parameters in Figure 24 to 27 and Table
28.
Add MBLI to order information
Modify the paragraph “Unicast MAC Address Filtering”
Modify the Table 5 (RMII Signal Connections)
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KSZ8893MQL/MBL
Contents
List of Figures...................................................................................................................................... 8
List of Tables ....................................................................................................................................... 9
Pin Description and I/O Assignment of KSZ8893MQL .................................................................... 10
Ball Description and I/O Assignment of KSZ8893MBL ................................................................... 19
Pin Configuration............................................................................................................................... 26
Functional Overview: Physical Layer Transceiver .......................................................................... 28
100BASE-TX Transmit.........................................................................................................................................................28
100BASE-TX Receive ..........................................................................................................................................................28
PLL Clock Synthesizer........................................................................................................................................................28
Scrambler/De-scrambler (100BASE-TX Only) ...................................................................................................................29
100BASE-FX Operation.......................................................................................................................................................29
100BASE-FX Signal Detection............................................................................................................................................29
100BASE-FX Far-End Fault.................................................................................................................................................29
10BASE-T Transmit.............................................................................................................................................................29
10BASE-T Receive ..............................................................................................................................................................30
Power Management.............................................................................................................................................................30
MDI/MDI-X Auto Crossover.................................................................................................................................................30
Straight Cable ................................................................................................................................................................31
Crossover Cable ............................................................................................................................................................32
Auto-Negotiation .................................................................................................................................................................32
LinkMD Cable Diagnostics .................................................................................................................................................34
Access ...........................................................................................................................................................................34
Usage ............................................................................................................................................................................34
Functional Overview: MAC and Switch ............................................................................................ 35
Address Lookup ..................................................................................................................................................................35
Learning ...............................................................................................................................................................................35
Migration ..............................................................................................................................................................................35
Aging ....................................................................................................................................................................................35
Forwarding...........................................................................................................................................................................35
Switching Engine ................................................................................................................................................................38
MAC Operation ....................................................................................................................................................................38
Inter Packet Gap (IPG) ..................................................................................................................................................38
Back-Off Algorithm.........................................................................................................................................................38
Late Collision .................................................................................................................................................................38
Illegal Frames ................................................................................................................................................................38
Full Duplex Flow Control................................................................................................................................................38
Half-Duplex Backpressure .............................................................................................................................................38
Broadcast Storm Protection...........................................................................................................................................39
MII Interface Operation........................................................................................................................................................39
RMII Interface Operation .....................................................................................................................................................40
SNI (7-Wire) Operation ........................................................................................................................................................41
MII Management (MIIM) Interface .......................................................................................................................................42
Serial Management Interface (SMI) ....................................................................................................................................43
Repeater Mode.....................................................................................................................................................................43
Advanced Switch Functions ............................................................................................................. 44
Spanning Tree Support.......................................................................................................................................................44
Special Tagging Mode.........................................................................................................................................................45
IGMP Support ......................................................................................................................................................................46
IGMP Snooping .............................................................................................................................................................46
Multicast Address Insertion in the Static MAC Table .....................................................................................................46
IPv6 MLD Snooping.............................................................................................................................................................46
Port Mirroring Support........................................................................................................................................................47
IEEE 802.1Q VLAN Support ................................................................................................................................................47
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KSZ8893MQL/MBL
QoS Priority Support...........................................................................................................................................................48
Port-Based Priority..............................................................................................................................................................48
802.1p-Based Priority..........................................................................................................................................................48
DiffServ-Based Priority .......................................................................................................................................................49
Rate Limiting Support .........................................................................................................................................................49
Unicast MAC Address Filtering..........................................................................................................................................49
Configuration Interface .......................................................................................................................................................50
2
I C Master Serial Bus Configuration ..............................................................................................................................50
2
I C Slave Serial Bus Configuration ................................................................................................................................51
SPI Slave Serial Bus Configuration ...............................................................................................................................51
Loopback Support...............................................................................................................................................................54
Far-end Loopback..........................................................................................................................................................54
Near-end (Remote) Loopback .......................................................................................................................................55
MII Management (MIIM) Registers..................................................................................................... 56
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control.........................................................................57
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control.........................................................................57
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status...........................................................................58
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status...........................................................................58
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High ..................................................................................58
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High ..................................................................................58
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low ...................................................................................58
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low ...................................................................................58
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................59
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................59
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................59
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................59
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status...........................................................60
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status...........................................................60
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status ...................................................60
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status ...................................................60
Register Map: Switch & PHY (8-bit registers) .................................................................................. 61
Global Registers ............................................................................................................................................................61
Port Registers ................................................................................................................................................................61
Advanced Control Registers ..........................................................................................................................................61
Global Registers..................................................................................................................................................................61
Register 0 (0x00): Chip ID0 ...........................................................................................................................................61
Register 1 (0x01): Chip ID1 / Start Switch .....................................................................................................................62
Register 2 (0x02): Global Control 0 ...............................................................................................................................62
Register 3 (0x03): Global Control 1 ...............................................................................................................................63
Register 4 (0x04): Global Control 2 ...............................................................................................................................63
Register 4 (0x04): Global Control 2 (continued).............................................................................................................64
Register 5 (0x05): Global Control 3 ...............................................................................................................................64
Register 5 (0x05): Global Control 3 (continued).............................................................................................................65
Register 6 (0x06): Global Control 4 ...............................................................................................................................65
Register 6 (0x06): Global Control 4 (continued).............................................................................................................66
Register 7 (0x07): Global Control 5 ...............................................................................................................................66
Register 8 (0x08): Global Control 6 ...............................................................................................................................66
Register 9 (0x09): Global Control 7 ...............................................................................................................................66
Register 10 (0x0A): Global Control 8 .............................................................................................................................66
Register 11 (0x0B): Global Control 9 .............................................................................................................................67
Register 12 (0x0C): Global Control 10...........................................................................................................................67
Register 13 (0x0D): Global Control 11...........................................................................................................................68
Register 14 (0x0E): Global Control 12 ...........................................................................................................................68
Register 15 (0x0F): Global Control 13 ...........................................................................................................................68
Port Registers......................................................................................................................................................................68
Register 16 (0x10): Port 1 Control 0 ..............................................................................................................................69
Register 32 (0x20): Port 2 Control 0 ..............................................................................................................................69
Register 48 (0x30): Port 3 Control 0 ..............................................................................................................................69
Register 17 (0x11): Port 1 Control 1 ..............................................................................................................................70
Register 33 (0x21): Port 2 Control 1 ..............................................................................................................................70
Register 49 (0x31): Port 3 Control 1 ..............................................................................................................................70
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KSZ8893MQL/MBL
Register 18 (0x12): Port 1 Control 2 ..............................................................................................................................71
Register 34 (0x22): Port 2 Control 2 ..............................................................................................................................71
Register 50 (0x32): Port 3 Control 2 ..............................................................................................................................71
Register 19 (0x13): Port 1 Control 3 ..............................................................................................................................72
Register 35 (0x23): Port 2 Control 3 ..............................................................................................................................72
Register 51 (0x33): Port 3 Control 3 ..............................................................................................................................72
Register 20 (0x14): Port 1 Control 4 ..............................................................................................................................72
Register 36 (0x24): Port 2 Control 4 ..............................................................................................................................72
Register 52 (0x34): Port 3 Control 4 ..............................................................................................................................72
Register 21 (0x15): Port 1 Control 5 ..............................................................................................................................72
Register 37 (0x25): Port 2 Control 5 ..............................................................................................................................72
Register 53 (0x35): Port 3 Control 5 ..............................................................................................................................72
Register 22 (0x16): Port 1 Control 6 ..............................................................................................................................73
Register 38 (0x26): Port 2 Control 6 ..............................................................................................................................73
Register 54 (0x36): Port 3 Control 6 ..............................................................................................................................73
Register 23 (0x17): Port 1 Control 7 ..............................................................................................................................74
Register 39 (0x27): Port 2 Control 7 ..............................................................................................................................74
Register 55 (0x37): Port 3 Control 7 ..............................................................................................................................74
Register 24 (0x18): Port 1 Control 8 ..............................................................................................................................75
Register 40 (0x28): Port 2 Control 8 ..............................................................................................................................75
Register 56 (0x38): Port 3 Control 8 ..............................................................................................................................75
Register 25 (0x19): Port 1 Control 9 ..............................................................................................................................76
Register 41 (0x29): Port 2 Control 9 ..............................................................................................................................76
Register 57 (0x39): Port 3 Control 9 ..............................................................................................................................76
Register 26 (0x1A): Port 1 PHY Special Control/Status.................................................................................................77
Register 42 (0x2A): Port 2 PHY Special Control/Status.................................................................................................77
Register 58 (0x3A): Reserved, not applied to port 3 ......................................................................................................77
Register 27 (0x1B): Port 1 LinkMD Result .....................................................................................................................77
Register 43 (0x2B): Port 2 LinkMD Result .....................................................................................................................77
Register 59 (0x3B): Reserved, not applied to port 3 ......................................................................................................77
Register 28 (0x1C): Port 1 Control 12............................................................................................................................78
Register 44 (0x2C): Port 2 Control 12............................................................................................................................78
Register 60 (0x3C): Reserved, not applied to port 3......................................................................................................78
Register 29 (0x1D): Port 1 Control 13............................................................................................................................79
Register 45 (0x2D): Port 2 Control 13............................................................................................................................79
Register 61 (0x3D): Reserved, not applied to port 3......................................................................................................79
Register 30 (0x1E): Port 1 Status 0 ...............................................................................................................................80
Register 46 (0x2E): Port 2 Status 0 ...............................................................................................................................80
Register 62 (0x3E): Reserved, not applied to port 3 ......................................................................................................80
Register 31 (0x1F): Port 1 Status 1 ...............................................................................................................................80
Register 47 (0x2F): Port 2 Status 1 ...............................................................................................................................80
Register 63 (0x3F): Port 3 Status 1 ...............................................................................................................................80
Register 31 (0x1F): Port 1 Status 1 (continued).............................................................................................................81
Register 47 (0x2F): Port 2 Status 1 (continued).............................................................................................................81
Register 63 (0x3F): Port 3 Status 1 (continued).............................................................................................................81
Register 96 (0x60): TOS Priority Control Register 0 ......................................................................................................81
Register 97 (0x61): TOS Priority Control Register 1 ......................................................................................................82
Register 98 (0x62): TOS Priority Control Register 2 ......................................................................................................82
Register 99 (0x63): TOS Priority Control Register 3 ......................................................................................................83
Register 100 (0x64): TOS Priority Control Register 4 ....................................................................................................83
Register 101 (0x65): TOS Priority Control Register 5 ....................................................................................................84
Register 102 (0x66): TOS Priority Control Register 6 ....................................................................................................84
Register 103 (0x67): TOS Priority Control Register 7 ....................................................................................................85
Register 104 (0x68): TOS Priority Control Register 8 ....................................................................................................85
Register 105 (0x69): TOS Priority Control Register 9 ....................................................................................................86
Register 106 (0x6A): TOS Priority Control Register 10..................................................................................................86
Register 107 (0x6B): TOS Priority Control Register 11..................................................................................................87
Register 108 (0x6C): TOS Priority Control Register 12 .................................................................................................87
Register 109 (0x6D): TOS Priority Control Register 13 .................................................................................................88
Register 110 (0x6E): TOS Priority Control Register 14..................................................................................................88
Register 111 (0x6F): TOS Priority Control Register 15..................................................................................................89
Register 112 (0x70): MAC Address Register 0 ..............................................................................................................89
Register 113 (0x71): MAC Address Register 1 ..............................................................................................................89
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KSZ8893MQL/MBL
Register 114 (0x72): MAC Address Register 2 ..............................................................................................................89
Register 115 (0x73): MAC Address Register 3 ..............................................................................................................89
Register 116 (0x74): MAC Address Register 4 ..............................................................................................................89
Register 117 (0x75): MAC Address Register 5 ..............................................................................................................89
Register 118 (0x76): User Defined Register 1 ...............................................................................................................90
Register 119 (0x77): User Defined Register 2 ...............................................................................................................90
Register 120 (0x78): User Defined Register 3 ...............................................................................................................90
Register 121 (0x79): Indirect Access Control 0..............................................................................................................90
Register 122 (0x7A): Indirect Access Control 1 .............................................................................................................90
Register 123 (0x7B): Indirect Data Register 8 ...............................................................................................................90
Register 124 (0x7C): Indirect Data Register 7 ...............................................................................................................91
Register 125 (0x7D): Indirect Data Register 6 ...............................................................................................................91
Register 126 (0x7E): Indirect Data Register 5 ...............................................................................................................91
Register 127 (0x7F): Indirect Data Register 4................................................................................................................91
Register 128 (0x80): Indirect Data Register 3................................................................................................................91
Register 129 (0x81): Indirect Data Register 2................................................................................................................91
Register 130 (0x82): Indirect Data Register 1................................................................................................................91
Register 131 (0x83): Indirect Data Register 0................................................................................................................91
Register 132 (0x84): Digital Testing Status 0.................................................................................................................91
Register 133 (0x85): Digital Testing Control 0 ...............................................................................................................92
Register 134 (0x86): Analog Testing Control 0 ..............................................................................................................92
Register 135 (0x87): Analog Testing Control 1 ..............................................................................................................92
Register 136 (0x88): Analog Testing Control 2 ..............................................................................................................92
Register 137 (0x89): Analog Testing Control 3 ..............................................................................................................92
Register 138 (0x8A): Analog Testing Status..................................................................................................................92
Register 139 (0x8B): Analog Testing Control 4..............................................................................................................92
Register 140 (0x8C): QM Debug 1 ................................................................................................................................92
Register 141 (0x8D): QM Debug 2 ................................................................................................................................92
Static MAC Address Table.............................................................................................................................................93
VLAN Table ...................................................................................................................................................................94
Dynamic MAC Address Table........................................................................................................................................95
MIB (Management Information Base) Counters.............................................................................................................96
Additional MIB Counter Information ...............................................................................................................................98
Absolute Maximum Ratings(1) ........................................................................................................... 99
Operating Ratings(2) ........................................................................................................................... 99
Electrical Characteristics(1) ............................................................................................................. 100
EEPROM Timing ................................................................................................................................................................102
SNI Timing..........................................................................................................................................................................103
MII Timing...........................................................................................................................................................................104
MAC Mode MII Timing .................................................................................................................................................104
PHY Mode MII Timing..................................................................................................................................................105
RMII Timing ........................................................................................................................................................................106
I2C Slave Mode Timing .....................................................................................................................................................107
SPI Timing..........................................................................................................................................................................108
Input Timing.................................................................................................................................................................108
Output Timing ..............................................................................................................................................................109
Auto-Negotiation Timing...................................................................................................................................................110
Reset Timing .................................................................................................................................... 111
Reset Circuit .................................................................................................................................... 112
Selection of Isolation Transformers ............................................................................................... 113
Selection of Reference Crystal ....................................................................................................... 113
Package Information........................................................................................................................ 114
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KSZ8893MQL/MBL
List of Figures
Figure 1. Typical Straight Cable Connection................................................................................................................................... 31
Figure 2. Typical Crossover Cable Connection .............................................................................................................................. 32
Figure 3. Auto-Negotiation and Parallel Operation ......................................................................................................................... 33
Figure 4. Destination Address Lookup Flow Chart, Stage 1 .......................................................................................................... 36
Figure 5. Destination Address Resolution Flow Chart, Stage 2..................................................................................................... 37
Figure 6. 802.1p Priority Field Format.............................................................................................................................................. 48
Figure 7. KSZ8893MQL/MBL EEPROM Configuration Timing Diagram......................................................................................... 50
Figure 8. SPI Write Data Cycle.......................................................................................................................................................... 52
Figure 9. SPI Read Data Cycle.......................................................................................................................................................... 53
Figure 10. SPI Multiple Write ............................................................................................................................................................ 53
Figure 11. SPI Multiple Read............................................................................................................................................................. 53
Figure 12: Far-End Loopback Path .................................................................................................................................................. 54
Figure 13. Near-end (Remote) Loopback Path ................................................................................................................................ 55
Figure 14. EEPROM Interface Input Timing Diagram.................................................................................................................... 102
Figure 15. EEPROM Interface Output Timing Diagram................................................................................................................. 102
Figure 16. SNI Input Timing Diagram .............................................................................................................................................. 103
Figure 17. SNI Output Timing Diagram .......................................................................................................................................... 103
Figure 18. MAC Mode MII Timing – Data Received from MII......................................................................................................... 104
Figure 19. MAC Mode MII Timing – Data Transmitted to MII ........................................................................................................ 104
Figure 20. PHY Mode MII Timing – Data Received from MII ......................................................................................................... 105
Figure 21. PHY Mode MII Timing – Data Transmitted to MII ......................................................................................................... 105
Figure 22: RMII Timing – Data Received from RMII....................................................................................................................... 106
Figure 23: RMII Timing – Data Input to RMII .................................................................................................................................. 106
Figure 24. I2C Input Timing.............................................................................................................................................................. 107
Figure 25. I2C Start Bit Timing ........................................................................................................................................................ 107
Figure 26. I2C Stop Bit Timing......................................................................................................................................................... 107
Figure 27. I2C Input Timing.............................................................................................................................................................. 107
Figure 28. SPI Input Timing ............................................................................................................................................................ 108
Figure 29. SPI Output Timing ......................................................................................................................................................... 109
Figure 30: Auto-Negotiation Timing............................................................................................................................................... 110
Figure 31. Reset Timing .................................................................................................................................................................. 111
Figure 32. Recommended Reset Circuit ........................................................................................................................................ 112
Figure 33. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output............................................................. 112
Figure 34. 128-Pin PQFP Package.................................................................................................................................................. 114
Figure 35. 100_Ball LFBGA Package .............................................................................................................................................. 115
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KSZ8893MQL/MBL
List of Tables
Table 1. FX and TX Mode Selection.................................................................................................................................................. 29
Table 2. MDI/MDI-X Pin Definitions................................................................................................................................................... 30
Table 3. MII Signals ........................................................................................................................................................................... 39
Table 4: RMII Signal Description ...................................................................................................................................................... 40
Table 5: RMII Signal Connections .................................................................................................................................................... 41
Table 6. SNI Signals .......................................................................................................................................................................... 41
Table 7. MII Management Interface Frame Format .......................................................................................................................... 42
Table 8. Serial Management Interface (SMI) Frame Format............................................................................................................ 43
Table 9: Spanning Tree States ......................................................................................................................................................... 44
Table 10. Special Tagging Mode Format.......................................................................................................................................... 45
Table 11. STPID Egress Rules (Processor to Switch Port 3).......................................................................................................... 45
Table 12. STPID Egress Rules (Switch Port 3 to Processor).......................................................................................................... 46
Table 13. FID+DA Lookup in VLAN Mode ........................................................................................................................................ 47
Table 14. FID+SA Lookup in VLAN Mode ........................................................................................................................................ 48
Table 15. KSZ8893MQL/MBL SPI Connections ............................................................................................................................... 52
Table 16. Format of Static MAC Table (8 Entries) ........................................................................................................................... 93
Table 17. Format of Static VLAN Table (16 Entries)........................................................................................................................ 94
Table 18. Format of Dynamic MAC Address Table (1K Entries)..................................................................................................... 95
Table 19. Format of “Per Port” MIB Counters ................................................................................................................................. 96
Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets ........................................................................................... 97
Table 21. Format of “All Port Dropped Packet” MIB Counters....................................................................................................... 97
Table 22. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets .............................................................................. 97
Table 23. EEPROM Timing Parameters.......................................................................................................................................... 102
Table 24. SNI Timing Parameters ................................................................................................................................................... 103
Table 25. MAC Mode MII Timing Parameters................................................................................................................................. 104
Table 26. PHY Mode MII Timing Parameters.................................................................................................................................. 105
Table 27: RMII Timing Parameters ................................................................................................................................................. 106
Table 28. I2C Timing Parameters..................................................................................................................................................... 107
Table 29. SPI Input Timing Parameters.......................................................................................................................................... 108
Table 30. SPI Output Timing Parameters....................................................................................................................................... 109
Table 31: Auto-Negotiation Timing Parameters ............................................................................................................................ 110
Table 32. Reset Timing Parameters ............................................................................................................................................... 111
Table 33. Transformer Selection Criteria....................................................................................................................................... 113
Table 34. Qualified Single Port Magnetics..................................................................................................................................... 113
Table 35. Typical Reference Crystal Characteristics .................................................................................................................... 113
February 2010
9
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Pin Description and I/O Assignment of KSZ8893MQL
Pin Number
Pin Name
Type
1
P1LED2
Ipu/O
2
P1LED1
Ipu/O
3
P1LED0
Ipu/O
(1)
Description
Port 1 LED Indicators
(apply to all modes of operation, except Repeater Mode)
[LEDSEL1, LEDSEL0]
[0, 0]
[0, 1]
P1LED3
—
—
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
[LEDSEL1, LEDSEL0]
[1, 0]
[1, 1]
P1LED3
Act
—
P1LED2
Link
—
P1LED1
Full duplex/Col
—
P1LED0
Speed
—
Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link),
Toggle (transmit / receive activity)
Full duplex/Col : Low (full duplex), High (half duplex), Toggles
(collision)
Speed : Low (100BASE-TX), High (10BASE-T)
Full duplex : Low (full duplex), High (half duplex)
Act : Toggle (transmit / receive activity)
Link : Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0, 0]
P1LED3
RPT_COL
P1LED2
RPT_LINK3/RX
P1LED1
RPT_LINK2/RX
P1LED0
RPT_LINK1/RX
RPT_COL : Low (collision)
RPT_LINK#/RX (# = port) : Low (link), High (no link), Toggles
(receive activity)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P1LED3 is pin 25.
During reset, P1LED[2:0] are inputs for internal testing.
Note:
1. Ipu/O = Input with internal pull-up during reset, output pin otherwise.
February 2010
10
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Pin Number
Pin Name
Type
4
P2LED2
Ipu/O
5
P2LED1
Ipu/O
6
P2LED0
Ipu/O
(1)
Description
Port 2 LED Indicators
(apply to all modes of operation, except Repeater Mode)
[LEDSEL1, LEDSEL0]
[0, 0]
[0, 1]
P2LED3
—
—
P2LED2
Link/Act
100Link/Act
P2LED1
Full duplex/Col
10Link/Act
P2LED0
Speed
Full duplex
[LEDSEL1, LEDSEL0]
[1, 0]
[1, 1]
P2LED3
Act
—
P2LED2
Link
—
P2LED1
Full duplex/Col
—
P2LED0
Speed
—
Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link),
Toggle (transmit / receive activity)
Full duplex/Col : Low (full duplex), High (half duplex), Toggles
(collision)
Speed : Low (100BASE-TX), High (10BASE-T)
Full duplex : Low (full duplex), High (half duplex)
Act : Toggle (transmit / receive activity)
Link : Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0, 0]
P2LED3
RPT_ACT
P2LED2
RPT_ERR3
P2LED1
RPT_ERR2
P2LED0
RPT_ERR1
RPT_ACT : Low (activity)
RPT_ERR# (# = port) : Low (error status due to either
isolation, partition, jabber, or JK error)
7
DGND
Gnd
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P2LED3 is pin 20.
During reset, P2LED[2:0] are inputs for internal testing.
Digital ground
8
VDDIO
P
3.3V digital VDD
Note:
1. P = Power supply.
Gnd = Ground.
Ipu/O = Input with internal pull-up during reset, output pin otherwise.
February 2010
11
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
(1)
Pin Number
Pin Name
Type
9
NC
Ipd
Description
No connect
10
NC
Ipd
No connect
11
NC
Ipu
No connect
12
ADVFC
Ipu
1 = advertise the switch’s flow control capability via autonegotiation.
0 = will not advertise the switch’s flow control capability via
auto-negotiation.
13
P2ANEN
Ipu
1 = enable auto-negotiation on port 2
0 = disable auto-negotiation on port 2
14
P2SPD
Ipd
1 = force port 2 to 100BT if P2ANEN = 0
0 = force port 2 to 10BT if P2ANEN = 0
15
P2DPX
Ipd
1 = port 2 default to full duplex mode if P2ANEN = 1 and
auto-negotiation fails. Force port 2 in full duplex mode if
P2ANEN = 0.
0 = port 2 default to half duplex mode if P2ANEN = 1 and
auto-negotiation fails. Force port 2 in half duplex mode if
P2ANEN = 0.
16
P2FFC
Ipd
1 = always enable (force) port 2 flow control feature
0 = port 2 flow control feature enable is determined by autonegotiation result.
17
NC
Opu
No connect
18
NC
Ipd
No connect
19
NC
Ipd
No connect
20
P2LED3
Opd
Port 2 LED indicator
Note: Internal pull-down is weak; it will not turn ON the LED.
See description in pin 4.
21
DGND
Gnd
22
VDDCO
P
Digital ground
1.2V digital VDD
Provides VOUT_1V2 to KSZ8893MQL’s input power pins: VDDAP
(pin 63), VDDC (pins 91 and 123), and VDDA (pins 38, 43, and
57). It is recommended the pin should be connected to 3.3V
power rail by a 100ohm resistor for the internal LDO
application.
23
LEDSEL1
Ipd
LED display mode select
See description in pins 1 and 4.
24
NC
O
No connect
25
P1LED3
Opd
Port 1 LED indicator
Note: An external 1K pull-down is needed on this pin if it is
connected to a LED. The 1K resistor will not turn ON the
LED.
See description in pin 1.
Note:
1. P = Power supply.
Gnd = Ground.
O = Output.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Opu = Output w/ internal pull-up.
Opd = Output w/ internal pull-down.
February 2010
12
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Pin Number
Pin Name
Type
26
RMII_EN
Opd
(1)
Description
Strap pin for RMII Mode
0 = Disable
1 = Enable
After reset, this pin has no meaning and is a no connect.
27
HWPOVR
Ipd
Hardware pin overwrite
0 = Disable. All strap-in pins configurations are overwritten by
the EEPROM configuration data
1 = Enable. All strap-in pins configurations are overwritten by
the EEPROM configuration data, except for register 0x2C bits
[7:5], (port 2: auto-negotiation enable, force speed, force
duplex).
28
P2MDIXDIS
Ipd
Port 2 Auto MDI/MDI-X
PD (default) = enable
PU = disable
29
P2MDIX
Ipd
Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled.
PD (default) = MDI-X (transmit on TXP2 / TXM2 pins)
PU = MDI, (transmit on RXP2 / RXM2 pins)
30
P1ANEN
Ipu
1 = enable auto-negotiation on port 1
31
P1SPD
Ipd
1 = force port 1 to 100BT if P1ANEN = 0
0 = disable auto-negotiation on port 1
0 = force port 1 to 10BT if P1ANEN = 0
32
P1DPX
Ipd
1 = port 1 default to full duplex mode if P1ANEN = 1 and autonegotiation fails. Force port 1 in full-duplex mode if P1ANEN
= 0.
0 = port 1 default to half duplex mode if P1ANEN = 1 and
auto- negotiation fails. Force port 1 in half duplex mode if
P1ANEN = 0.
33
P1FFC
Ipd
1 = always enable (force) port 1 flow control feature
0 = port 1 flow control feature enable is determined by auto
negotiation result.
34
NC
Ipd
No connect
35
NC
Ipd
No connect
36
PWRDN
Ipu
Chip power down input (active low)
37
AGND
Gnd
Analog ground
38
VDDA
P
1.2V analog VDD
39
AGND
Gnd
Analog ground
40
MUX1
I
Factory test pin - float for normal operation
41
MUX2
I
Factory test pin - float for normal operation
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Opd = Output w/ internal pull-down.
February 2010
13
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
(1)
Pin Number
Pin Name
Type
Description
42
AGND
Gnd
Analog ground
43
VDDA
P
1.2V analog VDD
44
FXSD1
I
Fiber signal detect / factory test pin
45
RXP1
I/O
Physical receive or transmit signal (+ differential)
46
RXM1
I/O
Physical receive or transmit signal (– differential)
47
AGND
Gnd
Analog ground
48
TXP1
I/O
Physical transmit or receive signal (+ differential)
49
TXM1
I/O
Physical transmit or receive signal (– differential)
50
VDDATX
P
3.3V analog VDD
51
VDDARX
P
3.3V analog VDD
52
RXM2
I/O
Physical receive or transmit signal (– differential)
53
RXP2
I/O
Physical receive or transmit signal (+ differential)
54
AGND
Gnd
Analog ground.
55
TXM2
I/O
Physical transmit or receive signal (– differential)
56
TXP2
I/O
Physical transmit or receive signal (+ differential)
57
VDDA
P
1.2V analog VDD
58
AGND
Gnd
Analog ground
59
TEST1
I
Factory test pin - float for normal operation
60
TEST2
I
Factory test pin - float for normal operation
61
ISET
O
Set physical transmit output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
62
AGND
Gnd
Analog ground
63
VDDAP
P
1.2V analog VDD for PLL
64
AGND
Gnd
Analog ground.
65
X1
I
25MHz crystal/oscillator clock connections
66
X2
O
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1
connects to a 3.3V tolerant oscillator and X2 is a no connect.
67
RST_N
Ipu
Hardware reset pin (active low)
68
UNUSED
I
Unused pin – externally pull down for normal operation
69
UNUSED
I
Unused pin – externally pull down for normal operation
Note: Clock is +/- 50ppm for both crystal and oscillator.
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input w/ internal pull-up.
February 2010
14
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
(1)
Pin Number
Pin Name
Type
Description
70
LEDSEL0
I
71
SMTXEN
I
Switch MII transmit enable
72
SMTXD3
I
Switch MII transmit data bit 3
73
SMTXD2
I
Switch MII transmit data bit 2
74
SMTXD1
I
Switch MII transmit data bit 1
75
SMTXD0
I
Switch MII transmit data bit 0
76
SMTXER
I
Switch MII transmit error
77
SMTXC /
REFCLK
I/O
Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII mode
LED display mode select
See description in pins 1 and 4.
Reference Clock (RMII mode only)
Input for 50MHz +/- 50ppm system clock
Note: In RMII mode, pin X1 is pulled up to VDDIO supply with
a 10K resistor and pin X2 is a no connect.
78
DGND
Gnd
Digital ground
79
VDDIO
P
3.3V digital VDD
80
SMRXC
I/O
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
81
SMRXDV
O
Switch MII receive data valid
82
SMRXD3
Ipd/O
Switch MII receive data bit 3
Strap option: switch MII full-duplex flow control
PD (default) = disable
PU = enable
83
SMRXD2
Ipd/O
Switch MII receive data bit 2
Strap option: switch MII is in
PD (default) = full-duplex mode
PU = half-duplex mode
84
SMRXD1
Ipd/O
Switch MII receive data bit 1
Strap option: Switch MII is in
PD (default) = 100Mbps mode
PU = 10Mbps mode
85
SMRXD0
I/O
Switch MII receive data bit 0
Strap option: switch will accept packet size up to
PD = 1536 bytes (inclusive)
PU = 1522 bytes (tagged), 1518 bytes (untagged)
86
SCOL
I/O
Switch MII collision detect
87
SCRS
I/O
Switch MII carrier sense
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
I/O = Bi-directional.
February 2010
15
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Pin Number
Pin Name
Type
88
SCONF1
I
89
SCONF0
I
Gnd
(1)
Description
Switch MII interface configuration
(SCONF1, SCONF0)
Description
(0,0)
disable, outputs tri-stated
(0,1)
PHY mode MII
(1,0)
MAC mode MII
(1,1)
PHY mode SNI
90
DGND
Digital ground
91
VDDC
P
1.2V digital VDD
92
UNUSED
I
Unused pins – externally pull down for normal operation
93
UNUSED
I
94
MDC
I
MII management interface: clock input
95
MDIO
I/O
MII management interface: data input/output
Note: an external pull-up is needed on this pin when it is in
use.
96
SPIQ
O
SPI slave mode: serial data output
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in
use.
97
SCL
I/O
2
SPI slave mode / I C slave mode: clock input
2
I C master mode: clock output
See description in pins 100 and 101.
98
SDA
I/O
SPI slave mode: serial data input
2
I C master/slave mode: serial data input/output
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in
use.
99
SPIS_N
I
SPI slave mode: chip select (active low)
When SPIS_N is high, the KSZ8893MQL is deselected and
SPIQ is held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in
use.
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
February 2010
16
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Pin Number
Pin Name
Type
100
PS1
I
101
PS0
I
(1)
Description
Serial bus configuration pins to select mode of access to
KSZ8893MQL internal registers.
2
[PS1, PS0] = [0, 0] — I C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8893MQL will be
configured with the default values of its internal registers and
the values of its strap-in pins.)
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
O
I2C clock
SDA
I/O
I2C data I/O
SPIS_N
I
Not used
2
[PS1, PS0] = [0, 1] — I C slave mode
2
The external I C master will drive the SCL clock.
The KSZ8893MQL device addresses are:
1011_1111
1011_1110
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
I
I2C clock
SDA
I/O
I2C data I/O
SPIS_N
I
Not used
[PS1, PS0] = [1, 0] — SPI slave mode
Interface Signals
Type
Description
SPIQ
O
SPI data out
SCL
I
SPI clock
SDA
I
SPI data In
SPIS_N
I
SPI chip select
[PS1, PS0] = [1, 1] – SMI-mode
In this mode, the KSZ8893MQL provides access to all its
internal 8-bit registers through its MDC and MDIO pins.
Note:
When (PS1, PS0) ≠ (1,1), the KSZ8893MQL provides access
to its 16-bit MIIM registers through its MDC and MDIO pins.
102
UNUSED
I
103
UNUSED
I
Unused pins – externally pull up for normal operation
Note:
1. I = Input.
February 2010
17
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Pin Number
Pin Name
Type
104
UNUSED
I
(1)
Description
Unused pins – externally pull up for normal operation
105
UNUSED
I
106
DGND
Gnd
Digital ground
107
VDDIO
P
3.3V digital VDD
108
UNUSED
I
Unused pins – externally pull up for normal operation
109
UNUSED
I
110
UNUSED
I
Unused pin – externally pull down for normal operation
111
UNUSED
I
Unused pin – externally pull down for normal operation
112
UNUSED
I
Unused pin – externally pull down for normal operation
113
UNUSED
I
Unused pin – externally pull down for normal operation
114
UNUSED
I
Unused pin – externally pull down for normal operation
115
UNUSED
I
Unused pin – externally pull down for normal operation
116
UNUSED
I
Unused pin – externally pull down for normal operation
117
UNUSED
I
Unused pin – externally pull down for normal operation
118
UNUSED
I
Unused pin – externally pull down for normal operation
119
UNUSED
I
Unused pin – externally pull down for normal operation
120
UNUSED
I
Unused pin – externally pull down for normal operation
121
UNUSED
I
Unused pin – externally pull down for normal operation
122
DGND
Gnd
Digital ground
123
VDDC
P
1.2V digital VDD
124
UNUSED
I
Unused pin – externally pull down for normal operation
125
UNUSED
I
Unused pin – externally pull down for normal operation
126
UNUSED
I
Unused pin – externally pull down for normal operation
127
TESTEN
Ipd
Scan Test Enable
For normal operation, pull-down this pin to ground.
128
SCANEN
Ipd
Scan Test Scan Mux Enable
For normal operation, pull-down this pin to ground.
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
Ipd = Input w/ internal pull-down.
February 2010
18
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Ball Description and I/O Assignment of KSZ8893MBL
Ball Number
Ball Name
Type
C10
P1LED2
Ipu/O
B10
P1LED1
Ipu/O
A10
P1LED0
Ipu/O
(1)
Ball Function Description
Port 1 LED Indicators
(apply to all modes of operation, except Repeater Mode)
[LEDSEL1, LEDSEL0]
[0, 0]
[0, 1]
P1LED3
—
—
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
[LEDSEL1, LEDSEL0]
[1, 0]
[1, 1]
P1LED3
Act
—
P1LED2
Link
—
P1LED1
Full duplex/Col
—
P1LED0
Speed
—
Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link),
Toggle (transmit / receive activity)
Full duplex/Col : Low (full duplex), High (half duplex), Toggles
(collision)
Speed : Low (100BASE-TX), High (10BASE-T)
Full duplex : Low (full duplex), High (half duplex)
Act : Toggle (transmit / receive activity)
Link : Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0, 0]
P1LED3
RPT_COL
P1LED2
RPT_LINK3/RX
P1LED1
RPT_LINK2/RX
P1LED0
RPT_LINK1/RX
RPT_COL : Low (collision)
RPT_LINK#/RX (# = port) : Low (link), High (no link), Toggles
(receive activity)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P1LED3 is pin 25.
During reset, P1LED[2:0] are inputs for internal testing.
Note:
1.
Ipu/O = Input with internal pull-up during reset, output pin otherwise.
February 2010
19
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Ball Number
Ball Name
Type
C9
P2LED2
Ipu/O
B9
P2LED1
Ipu/O
A9
P2LED0
Ipu/O
(1)
Ball Function Description
Port 2 LED Indicators
(apply to all modes of operation, except Repeater Mode)
[LEDSEL1, LEDSEL0]
[0, 0]
[0, 1]
P2LED3
—
—
P2LED2
Link/Act
100Link/Act
P2LED1
Full duplex/Col
10Link/Act
P2LED0
Speed
Full duplex
[LEDSEL1, LEDSEL0]
[1, 0]
[1, 1]
P2LED3
Act
—
P2LED2
Link
—
P2LED1
Full duplex/Col
—
P2LED0
Speed
—
Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link),
Toggle (transmit / receive activity)
Full duplex/Col : Low (full duplex), High (half duplex), Toggles
(collision)
Speed : Low (100BASE-TX), High (10BASE-T)
Full duplex : Low (full duplex), High (half duplex)
Act : Toggle (transmit / receive activity)
Link : Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0, 0]
P2LED3
RPT_ACT
P2LED2
RPT_ERR3
P2LED1
RPT_ERR2
P2LED0
RPT_ERR1
RPT_ACT : Low (activity)
RPT_ERR# (# = port) : Low (error status due to either
isolation, partition, jabber, or JK error)
C8
ADVFC
Ipu
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P2LED3 is pin 20.
During reset, P2LED[2:0] are inputs for internal testing.
1 = advertise the switch’s flow control capability via autonegotiation.
0 = will not advertise the switch’s flow control capability via
auto-negotiation.
B8
P2ANEN
Ipu
1 = enable auto-negotiation on port 2
0 = disable auto-negotiation on port 2
February 2010
20
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Ball Number
Ball Name
Type
A8
P2SPD
Ipd
B7
P2DPX
Ipd
(1)
Ball Function Description
1 = force port 2 to 100BT if P2ANEN = 0
0 = force port 2 to 10BT if P2ANEN = 0
1 = port 2 default to full duplex mode if P2ANEN = 1 and
auto-negotiation fails. Force port 2 in full duplex mode if
P2ANEN = 0.
0 = port 2 default to half duplex mode if P2ANEN = 1 and
auto-negotiation fails. Force port 2 in half duplex mode if
P2ANEN = 0.
A7
P2FFC
Ipd
1 = always enable (force) port 2 flow control feature
0 = port 2 flow control feature enable is determined by autonegotiation result.
B6
P2LED3
Opd
Port 2 LED indicator
Note: Internal pull-down is weak; it will not turn ON the LED.
See description in pin 4.
A6
LEDSEL1
Ipd
LED display mode select
See description in pins 1 and 4.
B5
P1LED3
Opd
Port 1 LED indicator
Note: An external 1K pull-down is needed on this pin if it is
connected to a LED. The 1K resistor will not turn ON the
LED.
See description in pin 1.
A5
RMII_EN
Opd
Strap pin for RMII Mode
0 = Disable
1 = Enable
After reset, this pin has no meaning and is a no connect.
B4
HWPOVR
Ipd
Hardware pin overwrite
0 = Disable. All strap-in pins configurations are overwritten by
the EEPROM configuration data
1 = Enable. All strap-in pins configurations are overwritten by
the EEPROM configuration data, except for register 0x2C bits
[7:5], (port 2: auto-negotiation enable, force speed, force
duplex).
A4
P2MDIXDIS
Ipd
Port 2 Auto MDI/MDI-X
PD (default) = enable
PU = disable
B3
P2MDIX
Ipd
Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled.
PD (default) = MDI-X (transmit on TXP2 / TXM2 pins)
PU = MDI, (transmit on RXP2 / RXM2 pins)
A3
P1ANEN
Ipu
1 = enable auto-negotiation on port 1
0 = disable auto-negotiation on port 1
B2
P1SPD
Ipd
1 = force port 1 to 100BT if P1ANEN = 0
0 = force port 1 to 10BT if P1ANEN = 0
A2
P1DPX
Ipd
1 = port 1 default to full duplex mode if P1ANEN = 1 and
auto- negotiation fails. Force port 1 in full-duplex mode if
P1ANEN = 0.
0 = port 1 default to half duplex mode if P1ANEN = 1 and
auto- negotiation fails. Force port 1 in half duplex mode if
P1ANEN = 0.
February 2010
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Micrel, Inc.
KSZ8893MQL/MBL
Ball Number
Ball Name
Type
A1
P1FFC
Ipd
(1)
Ball Function Description
1 = always enable (force) port 1 flow control feature
0 = port 1 flow control feature enable is determined by auto
negotiation result.
B1
PWRDN
Ipu
Chip power down input (active low)
C3
FXSD1
I
Fiber signal detect / factory test pin
C1
RXP1
I/O
Physical receive or transmit signal (+ differential)
C2
RXM1
I/O
Physical receive or transmit signal (– differential)
D1
TXP1
I/O
Physical transmit or receive signal (+ differential)
D2
TXM1
I/O
Physical transmit or receive signal (– differential)
F2
RXM2
I/O
Physical receive or transmit signal (– differential)
F1
RXP2
I/O
Physical receive or transmit signal (+ differential)
G2
TXM2
I/O
Physical transmit or receive signal (– differential)
G1
TXP2
I/O
Physical transmit or receive signal (+ differential)
H2
ISET
O
Set physical transmit output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
H1
X1
I
25MHz crystal/oscillator clock connections
J1
X2
O
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1
connects to a 3.3V tolerant oscillator and X2 is a no connect.
Note: Clock is +/- 50ppm for both crystal and oscillator.
K1
RST_N
Ipu
Hardware reset pin (active low)
J2
LEDSEL0
I
LED display mode select
See description in pins 1 and 4.
K2
SMTXEN
I
Switch MII transmit enable
J3
SMTXD3
I
Switch MII transmit data bit 3
K3
SMTXD2
I
Switch MII transmit data bit 2
J4
SMTXD1
I
Switch MII transmit data bit 1
K4
SMTXD0
I
Switch MII transmit data bit 0
J5
SMTXER
I
Switch MII transmit error
K5
SMTXC /
REFCLK
I/O
Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII mode
Reference Clock (RMII mode only)
Input for 50MHz +/- 50ppm system clock
Note: In RMII mode, pin X1 is pulled up to VDDIO supply with
a 10K resistor and pin X2 is a no connect.
K6
SMRXC
I/O
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
J6
SMRXDV
O
Switch MII receive data valid
J7
SMRXD3
Ipd/O
Switch MII receive data bit 3
Strap option: switch MII full-duplex flow control
PD (default) = disable
PU = enable
February 2010
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Micrel, Inc.
KSZ8893MQL/MBL
Ball Number
Ball Name
Type
K7
SMRXD2
Ipd/O
(1)
Ball Function Description
Switch MII receive data bit 2
Strap option: switch MII is in
PD (default) = full-duplex mode
PU = half-duplex mode
J8
SMRXD1
Ipd/O
Switch MII receive data bit 1
Strap option: Switch MII is in
PD (default) = 100Mbps mode
PU = 10Mbps mode
K8
SMRXD0
I/O
Switch MII receive data bit 0
Strap option: switch will accept packet size up to
PD = 1536 bytes (inclusive)
PU = 1522 bytes (tagged), 1518 bytes (untagged)
J9
SCOL
I/O
Switch MII collision detect
K9
SCRS
I/O
Switch MII carrier sense
J10
SCONF1
I
Switch MII interface configuration
K10
SCONF0
I
(SCONF1, SCONF0)
Description
(0,0)
disable, outputs tri-stated
(0,1)
PHY mode MII
(1,0)
MAC mode MII
(1,1)
PHY mode SNI
H10
MDC
I
MII management interface: clock input
H9
MDIO
I/O
MII management interface: data input/output
Note: an external pull-up is needed on this pin when it is in
use.
G9
SPIQ
O
SPI slave mode: serial data output
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in
use.
G10
SCL
I/O
2
SPI slave mode / I C slave mode: clock input
2
I C master mode: clock output
See description in pins 100 and 101.
F9
SDA
I/O
SPI slave mode: serial data input
2
I C master/slave mode: serial data input/output
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in
use.
F10
SPIS_N
I
SPI slave mode: chip select (active low)
When SPIS_N is high, the KSZ8893MBL is deselected and
SPIQ is held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
See description in pins 100 and 101.
Note: an external pull-up is needed on this pin when it is in
use.
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KSZ8893MQL/MBL
Ball Number
Ball Name
Type
E9
PS1
I
E10
PS0
I
(1)
Ball Function Description
Serial bus configuration pins to select mode of access to
KSZ8893MBL internal registers.
2
[PS1, PS0] = [0, 0] — I C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8893MBL will be
configured with the default values of its internal registers and
the values of its strap-in pins.)
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
O
I2C clock
SDA
I/O
I2C data I/O
SPIS_N
I
Not used
2
[PS1, PS0] = [0, 1] — I C slave mode
2
The external I C master will drive the SCL clock.
The KSZ8893MBL device addresses are:
1011_1111
1011_1110
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
I
I2C clock
SDA
I/O
I2C data I/O
SPIS_N
I
Not used
[PS1, PS0] = [1, 0] — SPI slave mode
Interface Signals
Type
Description
SPIQ
O
SPI data out
SCL
I
SPI clock
SDA
I
SPI data In
SPIS_N
I
SPI chip select
[PS1, PS0] = [1, 1] – SMI-mode
In this mode, the KSZ8893MBL provides access to all its
internal 8-bit registers through its MDC and MDIO pins.
Note:
When (PS1, PS0) ≠ (1,1), the KSZ8893MBL provides access
to its 16-bit MIIM registers through its MDC and MDIO pins.
D9
TESTEN
Ipd
Scan Test Enable
For normal operation, pull-down this pin to ground.
D10
SCANEN
Ipd
Scan Test Scan Mux Enable
C5, D8, E8, H6,
VDDC
P
1.2V digital VDD
VDDCO
P
1.2V digital VDD
For normal operation, pull-down this pin to ground.
H7
C4
Provides VOUT_1V2 to KSZ8893MBL’s input power pins: VDDA
(pin E3, F3 and G3), VDDC (pins C5, D8, E8, H6 and H7). It is
recommended the pin should be connected to 3.3V power rail
by a 100ohm resistor for the internal LDO application.
Ball Number
February 2010
Ball Name
Type
(1)
Ball Function Description
24
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
E3, F3, G3
VDDA
P
1.2V analog VDD
C6, C7, F8, G8,
VDDIO
P
3.3V digital VDD
H4, H5
E1
VDDATX
P
3.3V analog VDD
E2
VDDARX
P
3.3V analog VDD
D4, D5, D6, D7,
GND
Gnd
Ground
NC
NC
No connect
E4, E5, E6, E7,
F4, F5, F6, F7,
G4, G5, G6, G7
D3, H3, H8
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input w/ internal pull-up.
February 2010
25
M9999-021110-1.6
P1LED2
P1LED1
P1LED0
P2LED2
P2LED1
P2LED0
DGND
VDDIO
NC
NC
NC
ADVFC
P2ANEN
P2SPD
P2DPX
P2FFC
NC
NC
NC
P2LED3
DGND
VDDC
LEDSEL1
NC
P1LED3
RMII_EN
HWPOVR
P2MDIXDIS
P2MDIX
P1ANEN
P1SPD
P1DPX
P1FFC
NC
NC
PWRDN
AGND
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
UNUSED
UNUSED
UNUSED
DGND
VDDIO
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
DGND
VDDC
UNUSED
UNUSED
UNUSED
TESTEN
SCANEN
February 2010
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
UNUSED
PS0
PS1
SPIS_N
SDA
SCL
SPIQ
MDIO
MDC
UNUSED
UNUSED
VDDC
DGND
SCONF0
SCONF1
SCRS
SCOL
SMRXD0
SMRXD1
SMRXD2
SMRXD3
SMRXDV
SMRXC
VDDIO
DGND
SMTXC / REFCLK
SMTXER
SMTXD0
SMTXD1
SMTXD2
SMTXD3
SMTXEN
LEDSEL0
UNUSED
UNUSED
RST_N
X2
X1
Micrel, Inc.
KSZ8893MQL/MBL
Pin Configuration
26
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AGND
VDDAP
AGND
ISET
TEST2
TEST1
AGND
VDDA
TXP2
TXM2
AGND
RXP2
RXM2
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
FXSD1
VDDA
AGND
MUX2
MUX1
AGND
KSZ8893 128-Pin PQFP (Top View)
M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Ball Configuration
1
2
3
4
5
6
7
8
9
10
A
P1
FFC
P1
DPX
P1AN
EN
P2MD
IXDIX
RMII
EN
LED
SEL1
P2
FFC
P2
SPD
P2
LED0
P1
LED0
B
PWR
DN
P1
SPD
P2
MDIX
HW
POVR
P1
LED3
P2
LED3
P2
DPX
P2AN
EN
P2
LED1
P1
LED1
C
RXP1
RXM1
FXSD
1
VDD
CO
VDDC
VDD
IO
VDD
IO
ADV
FC
P2
LED2
P1
LED2
D
TXP1
TXM1
NC
GND
GND
GND
GND
VDDC
TEST
EN
SCAN
EN
E
VDDA
TX
VDDA
RX
VDDA
GND
GND
GND
GND
VDDC
PS1
PS0
F
RXP2
RXM2
VDDA
GND
GND
GND
GND
VDD
IO
SDA
SPIS
N
G
TXP2
TXM2
VDDA
GND
GND
GND
GND
VDD
IO
SPIQ
SCL
H
X1
ISET
NC
VDD
IO
VDD
IO
VDDC
VDDC
NC
MDIO
MDC
J
X2
LED
SEL0
SM
TXD3
SM
TXD1
SM
TXER
SM
RXDV
SM
RXD3
SM
RXD1
SCOL
SCON
F1
K
RSTN
SM
TXEN
SM
TXD2
SM
TXD0
SM
TXC
SM
RXC
SM
RXD2
SM
RXD0
SCRS
SCON
F0
KSZ8893MBL 100-Ball LFBGA (Top View)
February 2010
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M9999-021110-1.6
Micrel, Inc.
KSZ8893MQL/MBL
Functional Description
The KSZ8893MQL/MBL contains two 10/100 physical layer transceivers and three MAC units with an integrated
Layer 2 managed switch.
The KSZ8893MQL/MBL has the flexibility to reside in either a managed or unmanaged design. In a managed
design, the host processor has complete control of the KSZ8893MQL/MBL via the SMI interface, MIIM interface,
2
SPI bus, or I C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at
system reset time.
On the media side, the KSZ8893MQL/MBL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports,
and also 100BASE-FX on PHY port 1, which allows the KSZ8893MQL/MBL to be used as a media converter.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make
the design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-toNRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz
serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The
serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The
output current is set by an external1% 3.01KΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion,
data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel
conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the
twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer
must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial
estimation based on comparisons of incoming signal strength against some known cable characteristics, and then
tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as
temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is
then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed
by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to
the MAC.
PLL Clock Synthesizer
The KSZ8893MQL/MBL generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal
clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are
generated from an external 50MHz oscillator or system clock.
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KSZ8893MQL/MBL
Scrambler/De-scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic
interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear
feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver
then de-scrambles the incoming data stream using the same sequence as at the transmitter.
100BASE-FX Operation
100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation
is bypassed and auto MDI/MDI-X is disabled.
100BASE-FX Signal Detection
In 100BASE-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver
SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V.
When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When
FXSD1 is over 2.2V, the fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied
high to force 100BASE-FX mode.
100BASE-FX signal detection is summarized in the following table:
FXSD1 Input Voltage
Mode
Less than 0.2V
TX mode
Greater than 1V, but less than 1.8V
FX mode
No signal detected.
Far-end fault generated
Greater than 2.2V
FX mode
Signal detected
Table 1. FX and TX Mode Selection
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output
voltage swing to match the FXSD1 pin’s input voltage threshold.
100BASE-FX Far-End Fault
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver.
The KSZ8893MQL/MBL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected,
the KSZ8893MQL/MBL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero
in the idle period between frames.
By default, FEF is enabled. FEF can be disabled through register setting.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same
magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The
harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchesterencoded signal.
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Micrel, Inc.
KSZ8893MQL/MBL
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver
circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is
separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with
short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input
exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8893MQL/MBL decodes a data
frame. The receiver clock is maintained active during idle periods in between data reception.
Power Management
The KSZ8893MQL/MBL features a per-port power down mode. To save power, a PHY port that is not in use can
be powered down via port control register, or MIIM PHY register.
In addition, there is a full chip power down mode. When activated, the entire chip is powered down.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8893MQL/MBL supports HP Auto
MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive
pairs for the KSZ8893MQL/MBL device. This feature is extremely useful when end users are unaware of cable
types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be
disabled through the port control registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are:
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
TD+
1
RD+
2
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
Table 2. MDI/MDI-X Pin Definitions
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Micrel, Inc.
KSZ8893MQL/MBL
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following
diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
2
2
Transmit Pair
Receive Pair
3
Straight
Cable
3
4
4
5
5
6
6
7
7
8
8
Receive Pair
Transmit Pair
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Modular Connector
(RJ-45)
NIC
Figure 1. Typical Straight Cable Connection
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Micrel, Inc.
KSZ8893MQL/MBL
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X
devices).
10/100 Ethernet
Media Dependent Interface
1
Receive Pair
10/100 Ethernet
Media Dependent Interface
Crossover
Cable
1
Receive Pair
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Transmit Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Figure 2. Typical Crossover Cable Connection
Auto-Negotiation
The KSZ8893MQL/MBL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u
specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation.
In auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not
supported or the KSZ8893MQL/MBL link partner is forced to bypass auto-negotiation, the KSZ8893MQL/MBL
sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the
KSZ8893MQL/MBL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
The link up process is shown in the following flow diagram.
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Micrel, Inc.
KSZ8893MQL/MBL
Start Auto Negotiation
Force Link Setting
N
o
Parallel
Operation
Yes
Bypass Auto Negotiation
and Set Link Mode
Attempt Auto
Negotiation
Listen for 100BASE-TX
Idles
Listen for 10BASE-T
Link Pulses
No
Join
Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 3. Auto-Negotiation and Parallel Operation
February 2010
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Micrel, Inc.
KSZ8893MQL/MBL
LinkMD Cable Diagnostics
The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling
problems such as open circuits, short circuits and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then
analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the
cabling fault with maximum distance of 200m and accuracy of +/- 2m. Internal circuitry displays the TDR
information in a user-readable digital format.
Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation.
Access
LinkMD is initiated by accessing registers {26,27} and {42,43}, the LinkMD Control/Status registers, for ports 1
and 2, respectively; and in conjunction with registers 29 and 45, Port Control Register 13, for ports 1 and 2,
respectively.
Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access.
Usage
The following is a sample procedure for using LinkMD with registers {26,27,29} on port 1.
1. Disable auto MDI/MDI-X by writing a ‘1’ to register 29, bit [2] to enable manual control over the differential pair
used to transmit the LinkMD pulse.
2. Start cable diagnostic test by writing a ‘1’ to register 26, bit [4]. This enable bit is self-clearing.
3. Wait (poll) for register 26, bit [4] to return a ‘0’, indicating cable diagnostic test is completed.
4. Read cable diagnostic test results in register 26, bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the KSZ8893MQL/MBL is unable to shut down the link partner. In this
instance, the test is not run, since it would be impossible for the KSZ8893MQL/MBL to determine if the
detected signal is a reflection of the signal generated or a signal from another source.
5. Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0]; and multiplying the result
by a constant of 0.4. The distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.4 x {(register 26, bit [0]),(register 27, bits [7:0])}
D (distance to cable fault) is expressed in meters.
Concatenated value of registers 26 and 27 is converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of
propagation that varies significantly from the norm.
For port 2 and for the MIIM PHY registers, LinkMD usage is similar.
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Functional Overview: MAC and Switch
Address Lookup
The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast
address table plus switching information.
The KSZ8893MQL/MBL is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup
tables, which depending on the operating environment and probabilities, may not guarantee the absolute number
of addresses it can learn.
Learning
The internal lookup engine updates its table with a new entry if the following conditions are met:
1. The received packet's Source Address (SA) does not exist in the lookup table.
2. The received packet is good; the packet has no receiving errors, and is of legal length.
The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table
is full, the last entry of the table is deleted to make room for the new entry.
Migration
The internal lookup engine also monitors whether a station has moved. If a station has moved, it will update the
table accordingly. Migration happens when the following conditions are met:
1. The received packet's SA is in the table but the associated source port information is different.
2. The received packet is good; the packet has no receiving errors, and is of legal length.
The lookup engine will update the existing record in the table with the new source port information.
Aging
The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The
time stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes
the record from the table. The lookup engine constantly performs the aging process and will continuously remove
aging records. The aging period is about 200 seconds. This feature can be enabled or disabled through register 3
(0x03) bit [2].
Forwarding
The KSZ8893MQL/MBL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 4
shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and
dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further
modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to
forward 2” (PTF2), as shown in Figure 5. The packet is sent to PTF2.
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Start
PTF1= NULL
NO
VLAN ID
Valid?
- Search VLAN table
- Ingress VLAN filtering
- Discard NPVID check
YES
Search complete.
Get PTF1 from
Static MAC Table
FOUND
Search Static
Table
This search is based on
DA or DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
Dynamic MAC
Table
FOUND
Dynamic Table
Search
This search is based on
DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
VLAN Table
PTF1
Figure 4. Destination Address Lookup Flow Chart, Stage 1
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PTF1
Spanning Tree
Process
- Check receiving port's receive enable bit
- Check destination port's transmit enable bit
- Check whether packets are special (BPDU
or specified)
IGMP Process
- Applied to MAC #1 and MAC #2
- MAC #3 is reserved for
microprocessor
- IGMP will be forwarded to port 3
Port Mirror
Process
-
RX Mirror
TX Mirror
RX or TX Mirror
RX and TX Mirror
Port VLAN
Membership
Check
PTF2
Figure 5. Destination Address Resolution Flow Chart, Stage 2
The KSZ8893MQL/MBL will not forward the following packets:
1. Error packets
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size
packet errors.
2. IEEE802.3x PAUSE frames
KSZ8893MQL/MBL intercepts these packets and performs full duplex flow control accordingly.
3. "Local" packets
Based on destination address (DA) lookup. If the destination port from the lookup table matches the port
from which the packet originated, the packet is defined as "local."
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Switching Engine
The KSZ8893MQL/MBL features a high-performance switching engine to move data to and from the MACs’
packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall
latency.
The switching engine has a 32kB internal frame buffer. This buffer pool is shared between all three ports. There
are a total of 256 buffers available. Each buffer is sized at 128 bytes.
MAC Operation
The KSZ8893MQL/MBL strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If
the current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
Back-Off Algorithm
The KSZ8893MQL/MBL implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and
optional "aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch
configuration for register 4 (0x04) bit [3].
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
Illegal Frames
The KSZ8893MQL/MBL discards frames less than 64 bytes, and can be programmed to accept frames up to1518
bytes, 1536 bytes or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since
the KSZ8893MQL/MBL supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Full Duplex Flow Control
The KSZ8893MQL/MBL supports standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8893MQL/MBL receives a pause control frame, the KSZ8893MQL/MBL will not
transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause
frame is received before the current timer expires, the timer will be updated with the new value in the second
pause frame. During this period (while it is flow controlled), only flow control packets from the KSZ8893MQL/MBL
are transmitted.
On the transmit side, the KSZ8893MQL/MBL has intelligent and efficient ways to determine when to invoke flow
control. The flow control is based on availability of the system resources, including available buffers, available
transmit queues and available receive queues.
The KSZ8893MQL/MBL will flow control a port that has just received a packet if the destination port resource is
busy. The KSZ8893MQL/MBL issues a flow control frame (XOFF), containing the maximum pause time defined
by the IEEE 802.3x standard. Once the resource is freed up, the KSZ8893MQL/MBL sends out the other flow
control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A
hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and
deactivated.
The KSZ8893MQL/MBL flow controls all ports if the receive queue becomes full.
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as full duplex flow control. If backpressure is required, the KSZ8893MQL/MBL sends
preambles to defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the
KSZ8893MQL/MBL discontinues the carrier sense and then raises it again quickly. This short silent time (no
carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense
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deferred state. If the port has packets to send during a backpressure situation, the carrier sense type
backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send,
carrier sense type backpressure is reactivated again until switch resources free up. If a collision occurs, the binary
exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of
further collisions and carrier sense is maintained to prevent packet reception.
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:
1. Aggressive back-off (register 3 (0x03), bit [0])
2. No excessive collision drop (register 4 (0x04), bit [3])
Note: These bits are not set as defaults, as this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8893MQL/MBL has an intelligent option to protect the switch system from receiving too many broadcast
packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of
switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893MQL/MBL
has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are
programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval
for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the
rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in
register 6 (0x06) and 7 (0x07). The default setting is 0x63 (99 decimal). This is equal to a rate of 1%, calculated
as follows:
148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes
of preamble between two packets.
MII Interface Operation
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a
common interface between physical layer and MAC layer devices. The MII provided by the KSZ8893MQL/MBL is
connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission
and the other for reception. The following table describes the signals used by the MII bus.
PHY-Mode Connections
MAC-Mode Connections
External
PHY Signals
KSZ8893MQL/MBL
MAC Signals
Transmit enable
MTXEN
SMRXDV
Transmit error
MTXER
(not used)
Transmit data bit 3
MTXD3
SMRXD[3]
SMTXD[2]
Transmit data bit 2
MTXD2
SMRXD[2]
SMTXD[1]
Transmit data bit 1
MTXD1
SMRXD[1]
SMTXD[0]
Transmit data bit 0
MTXD0
SMRXD[0]
SMTXC
Transmit clock
MTXC
SMRXC
MCOL
SCOL
Collision detection
MCOL
SCOL
MCRS
SCRS
Carrier sense
MCRS
SCRS
MRXDV
SMRXDV
Receive data valid
MRXDV
SMTXEN
MRXER
(not used)
Receive error
MRXER
SMTXER
MRXD3
SMRXD[3]
Receive data bit 3
MRXD3
SMTXD[3]
MRXD2
SMRXD[2]
Receive data bit 2
MRXD2
SMTXD[2]
MRXD1
SMRXD[1]
Receive data bit 1
MRXD1
SMTXD[1]
MRXD0
SMRXD[0]
Receive data bit 0
MRXD0
SMTXD[0]
MRXC
SMRXC
Receive clock
MRXC
SMTXC
External MAC
Controller Signals
KSZ8893MQL/MBL
PHY Signals
MTXEN
SMTXEN
MTXER
SMTXER
MTXD3
SMTXD[3]
MTXD2
MTXD1
MTXD0
MTXC
Pin
Descriptions
Table 3. MII Signals
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The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the
network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error
occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without
physical layer errors. For half duplex operation, the SCOL signal indicates if a collision has occurred during
transmission.
The KSZ8893MBL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC
mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER
indicates a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are
not used by the KSZ8893MBL. So, for PHY mode operation, if the device interfacing with the KSZ8893MBL has
an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the
KSZ8893MQL/MBL has an MTXER input pin, it also needs to be tied low.
RMII Interface Operation
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII).
RMII provides a common interface between physical layer and MAC layer devices, and has the following key
characteristics:
1.
2.
3.
4.
Supports 10Mbps and 100Mbps data rates.
Uses a single 50 MHz clock reference (provided externally).
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception
The RMII provided by the KSZ8893MQL/MBL is connected to the device’s third MAC. It complies with the RMII
Specification. The following table describes the signals used by the RMII bus. Refer to RMII Specification for full
detail on the signal description.
RMII
Signal Name
Direction
(with respect
to the PHY)
Direction
(with respect
to the MAC)
REF_CLK
Input
Input or
Output
CRS_DV
Output
Input
RXD1
Output
Input
Synchronous 50 MHz clock
reference for receive, transmit
and control interface
Carrier sense/
Receive data valid
Receive data bit 1
RXD0
Output
Input
Receive data bit 0
SMRXD[0] (output)
TX_EN
Input
Output
Transmit enable
SMTXEN (input)
TXD1
Input
Output
Transmit data bit 1
SMTXD[1] (input)
TXD0
Input
Output
Transmit data bit 0
SMTXD[0] (input)
RX_ER
Output
Input
(not required)
Receive error
(not used)
RMII
Signal Description
KSZ8893MQL/MBL RMII
Signal (direction)
REFCLK (input)
SMRXDV (output)
SMRXD[1] (output)
SMTXER* (input)
---
---
---
---
* Connects to RX_ER signal
of RMII PHY device
Table 4: RMII Signal Description
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The KSZ8893MQL/MBL filters error frames, and thus does not implement the RX_ER output signal. To detect
error frames from RMII PHY devices, the SMTXER input signal of the KSZ8893MQL/MBL is connected to the
RXER output signal of the RMII PHY device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, tie MII signals, SMTXD[3:2] and SMTXER, to ground if they are not used.
The KSZ8893MQL/MBL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two
KSZ8893MQL/MBL devices to be connected back-to-back. The following table shows the KSZ8893MQL/MBL
RMII pin connections with an external RMII PHY and an external RMII MAC, such as another KSZ8893MQL/MBL
device.
KSZ8893MQL/MBL
KSZ8893MQL/MBL
PHY-MAC Connections
KSZ8893MQL/M
External
BL
PHY Signals
MAC Signals
MAC-MAC Connections
KSZ8893MQL/M
External
BL
MAC Signals
MAC Signals
REF_CLK
REFCLK
TX_EN
SMRXDV
TXD1
Pin
Descriptions
REFCLK
REF_CLK
SMRXDV
CRS_DV
SMRXD[1]
Reference Clock
Carrier sense/
Receive data valid
Receive data bit 1
SMRXD[1]
RXD1
TXD0
SMRXD[0]
Receive data bit 0
SMRXD[0]
RXD0
CRS_DV
SMTXEN
Transmit enable
SMTXEN
TX_EN
RXD1
SMTXD[1]
Transmit data bit 1
SMTXD[1]
TXD1
RXD0
SMTXD[0]
Transmit data bit 0
SMTXD[0]
TXD0
RX_ER
SMTXER
Receive error
(not used)
(not used)
Table 5: RMII Signal Connections
SNI (7-Wire) Operation
The serial network interface (SNI) or 7-wire is compatible with some controllers used for network layer protocol
processing. In SNI mode, the KSZ8893MQL/MBL acts like a PHY and the external controller functions as the
MAC. The KSZ8893MQL/MBL can interface directly with external controllers using the 7-wire interface. These
signals are divided into two groups, one for transmission and the other for reception. The signals involved are
described in the following table.
Pin Descriptions
External MAC
Controller Signals
KSZ8893MQL/MBL
PHY Signals
Transmit enable
TXEN
SMTXEN
Serial transmit data
TXD
SMTXD[0]
Transmit clock
TXC
SMTXC
Collision detection
COL
SCOL
Carrier sense
CRS
SMRXDV
Serial receive data
RXD
SMRXD[0]
Receive clock
RXC
SMRXC
Table 6. SNI Signals
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The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An
additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that
conveys when the data is valid.
For half duplex operation, the SCOL signal is used to indicate that a collision has occurred during transmission.
MII Management (MIIM) Interface
The KSZ8893MQL/MBL supports the IEEE 802.3 MII Management Interface, also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of
the KSZ8893MQL/MBL. An external device with MDC/MDIO capability is used to read the PHY status or
configure the PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u
Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893MQL/MBL device.
Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom
MIIM registers [29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5 MHz.
The following table depicts the MII Management Interface frame format.
Preamble
Start of
Frame
Read/Write
PHY
REG
OP Code
Address
Address
TA
Data
Idle
Bits [15:0]
Bits [4:0]
Bits [4:0]
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 7. MII Management Interface Frame Format
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Serial Management Interface (SMI)
The SMI is the KSZ8893MQL/MBL non-standard MIIM interface that provides access to all KSZ8893MQL/MBL
configuration registers. This interface allows an external device to completely monitor and control the states of the
KSZ8893MQL/MBL.
The SMI interface consists of the following:
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893MQL/MBL device.
Access to all KSZ8893MQL/MBL configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers
[0:5] and custom MIIM registers [29, 31].
The following table depicts the SMI frame format.
Preamble
Start of
Frame
Read/Write
PHY
REG
OP Code
Address
Address
TA
Data
Idle
Bits [15:0]
Bits [4:0]
Bits [4:0]
Read
32 1’s
01
00
1xRRR
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
Write
32 1’s
01
00
0xRRR
RRRRR
10
xxxx_xxxx_DDDD_DDDD
Z
Table 8. Serial Management Interface (SMI) Frame Format
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI
register write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY
address bit[3] is undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write
operations.
To access the KSZ8893MQL/MBL registers 0-141 (0x00 – 0x8D), the following applies:
PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address;
that is, {PHYAD[2:0], REGAD[4:0]} = bits [7:0] of the 8-bit address.
Registers are 8 data bits wide.
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
SMI register access is the same as the MIIM register access, except for the register access requirements
presented in this section.
Repeater Mode
The KSZ8893MQL/MBL supports repeater mode in 100BASE-TX Half Duplex mode. In repeater mode, all ingress
packets are broadcast to the other two ports. MAC address checking and learning are disabled.
Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be
configured to 100BASE-TX Half Duplex mode. Additionally, both PHY ports need to have auto-negotiation
disabled.
The latency between the two PHY ports is 270 ns (minimum) and 310 ns (maximum). The 40 ns difference is one
clock skew (one 25 MHz clock period) between reception and transmission. Latency is defined as the time from
the first bit of the Destination Address (DA) entering the ingress port to the first bit of the DA exiting the egress
port.
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Advanced Switch Functions
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”,
“receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The
following table shows the port setting and software actions taken for each of the five spanning tree states.
Disable State
Port Setting
Software Action
The port should
not forward or
receive any
packets. Learning
is disabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
The processor should not send any packets to the port. The switch may still
send specific packets to the processor (packets that match some entries in
the “static MAC table” with “overriding bit” set) and the processor should
discard those packets. Address learning is disabled on the port in this
state.
Blocking State
Port Setting
Software Action
Only packets to
the processor are
forwarded.
Learning is
disabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
The processor should not send any packets to the port(s) in this state. The
processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
also be set so that the switch will forward those specific packets to the
processor. Address learning is disabled on the port in this state.
Listening State
Port Setting
Software Action
Only packets to
and from the
processor are
forwarded.
Learning is
disabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
The processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state. See
“Special Tagging Mode” for details. Address learning is disabled on the port
in this state.
Learning State
Port Setting
Software Action
Only packets to
and from the
processor are
forwarded.
Learning is
enabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable = 0”
The processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state. See
“Special Tagging Mode” for details. Address learning is enabled on the port
in this state.
Forwarding
State
Port Setting
Software Action
Packets are
forwarded and
received normally.
Learning is
enabled.
“transmit
enable = 1,
receive
enable = 1,
learning
disable = 0”
The processor programs the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit is set so
that the switch forwards those specific packets to the processor. The
processor can send packets to the port(s) in this state. See “Special
Tagging Mode” for details. Address learning is enabled on the port in this
state.
Table 9: Spanning Tree States
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Special Tagging Mode
Special Tagging Mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other
applications. Special Tagging, similar to 802.1Q Tagging, requires software to change network drivers to
insert/modify/strip/interpret the special tag. This mode is enabled by setting both register 11 bit [0] and register 48
bit [2] to ‘1’.
802.1Q Tag Format
TPID (tag protocol identifier, 0x8100) + TCI.
Special Tag Format
STPID (special tag identifier, 0x810 +
4 bit for “port mask”) + TCI
Table 10. Special Tagging Mode Format
The STPID is only seen and used by the port 3 interface, which should be connected to a processor. Packets
from the processor to the switch’s port 3 should be tagged with the STPID and the port mask, defined as follows:
“0001”, forward packet to port 1 only
“0010”, forward packet to port 2 only
“0011”, broadcast packet to port 1 and port 2
Packets with normal tags (“0000” port masks) will use KSZ8893MQL/MBL internal MAC table lookup to determine
the forwarding port(s). Also, if packets from the processor are not tagged, the KSZ8893MQL/MBL will treat them
as normal packets and use internal MAC table lookup to determine the forwarding port(s).
The KSZ8893MQL/MBL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override
any port setting, regardless of port states (disable, blocking, listening, learning). The table below shows the
processor to switch egress rules when dealing with STPID.
Ingress Tag Field
TX port “tag
insertion”
TX port “tag
removal”
Egress Action to Tag Field
- Modify tag field to 0x8100
(0x810+ port mask)
0
- Recalculate CRC
0
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port
VID if null VID
- (STPID + TCI) will be removed
(0x810+ port mask)
0
1
- Padding to 64 bytes if necessary
- Recalculate CRC
- Modify tag field to 0x8100
(0x810+ port mask)
1
- Recalculate CRC
0
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port
VID if null VID
- Modify tag field to 0x8100
(0x810+ port mask)
1
- Recalculate CRC
1
- No change to TCI if not null VID
- Replace VID with ingress (port 3) port
VID if null VID
Not Tagged
Don’t care
Don’t care
- Determined by the Dynamic MAC
Address Table
Table 11. STPID Egress Rules (Processor to Switch Port 3)
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For packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the
packets were received on, defined as follows:
“0001”, packet from port 1
“0010”, packet from port 2
No port mask values, other than the previous two defined ones, should be received in this direction in Special
Tagging Mode. The switch to processor egress rules are defined as follows:
Ingress Packets
Egress Action to Tag Field
- Modify TPID to 0x810 + “port mask”, which indicates source port.
Tagged with 0x8100 + TCI
- No change to TCI if VID is not null
- Replace null VID with ingress port VID
- Recalculate CRC
- Insert TPID to 0x810 + “port mask”, which indicates source port
Not tagged.
- Insert TCI with ingress port VID
- Recalculate CRC
Table 12. STPID Egress Rules (Switch Port 3 to Processor)
IGMP Support
For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8893MQL/MBL provides two
components:
IGMP Snooping
The KSZ8893MQL/MBL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets
are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4
and protocol version number = 0x2.
Multicast Address Insertion in the Static MAC Table
Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the
subscribed ports, instead of broadcasting to all ports.
To enable IGMP support, set register 5 bit [6] to ‘1’. Also, Special Tagging Mode needs to be enabled, so that the
processor knows which port the IGMP packet was received on. This is achieved by setting both register 11 bit [0]
and register 48 bit [2] to ‘1’.
IPv6 MLD Snooping
The KSZ8893MQL/MBL traps IPv6 Multicast Listener Discovery (MLD) packets and forwards them only to
processor (port 3). MLD snooping is controlled by register 5 bit 5 (MLD snooping enable) and register 5 bit 4
(MLD option).
With MLD snooping enabled, the KSZ8893MQL/MBL traps packets that meet all of the following conditions:
•
•
•
IPv6 multicast packets
Hop count limit = 1
IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58)
If the MLD option bit is set to “1”, the KSZ8893MQL/MBL traps packets with the following additional condition:
•
IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or
60)
For MLD snooping, Special Tagging Mode also needs to be enabled, so that the processor knows which port the
MLD packet was received on. This is achieved by setting both register 11 bit [0] and register 48 bit [2] to ‘1’.
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Port Mirroring Support
KSZ8893MQL/MBL supports “Port Mirroring” comprehensively as:
“receive only” mirror on a port
All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to
be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined
to port 2 after the internal lookup. The KSZ8893MQL/MBL forwards the packet to both port 2 and port 3.
The KSZ8893MQL/MBL can optionally even forward “bad” received packets to the “sniffer port”.
“transmit only” mirror on a port
All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to
be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined
to port 1 after the internal lookup. The KSZ8893MQL/MBL forwards the packet to both port 1 and port 3.
“receive and transmit” mirror on two ports
All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on
the “AND” feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port
2 is programmed to be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet
received on port 1 is destined to port 2 after the internal lookup. The KSZ8893MQL/MBL forwards the
packet to both port 2 and port 3.
Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the
“sniffer port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3,
respectively.
IEEE 802.1Q VLAN Support
The KSZ8893MQL/MBL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q
specification. KSZ8893MQL/MBL provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to
the 4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port
default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine
whether the VID is valid. If the VID is not valid, the packet is dropped and its address is not learned. If the VID is
valid, the FID is retrieved for further lookup. The FID + Destination Address (FID+DA) are used to determine the
destination port. The FID + Source Address (FID+SA) are used for address learning.
DA found in
Static MAC
Table?
Use FID flag?
FID match?
DA+FID
found in
Dynamic
MAC Table?
Action
No
Don’t care
Don’t care
No
Broadcast to the membership ports
defined in the VLAN Table bits [18:16]
No
Don’t care
Don’t care
Yes
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Yes
0
Don’t care
Don’t care
Send to the destination port(s) defined in
the Static MAC Address Table bits [50:48]
Yes
1
No
No
Broadcast to the membership ports
defined in the VLAN Table bits [18:16]
Yes
1
No
Yes
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Yes
1
Yes
Don’t care
Send to the destination port(s) defined in
the Static MAC Address Table bits [50:48]
Table 13. FID+DA Lookup in VLAN Mode
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FID+SA found in Dynamic
MAC Table?
Action
No
Learn and add FID+SA to the Dynamic MAC Address Table
Yes
Update time stamp
Table 14. FID+SA Lookup in VLAN Mode
Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported
by the KSZ8893MQL/MBL. These features can be set on a per port basis, and are defined in register 18, 34 and
50 for ports 1, 2 and 3, respectively.
QoS Priority Support
The KSZ8893MQL/MBL provides Quality of Service (QoS) for applications such as VoIP and video conferencing.
Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is
the highest priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32 and 48 is used to
enable split transmit queues for ports 1, 2 and 3, respectively. If a port's transmit queue is not split, high priority
and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the
four priority queues. This global option is set and explained in bit [3] of register 5.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets
received at the high priority receiving port are marked as high priority and are sent to the high-priority transmit
queue if the corresponding transmit queue is split. Bits [4:3] of registers 16, 32 and 48 are used to enable portbased priority for ports 1, 2 and 3, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8893MQL/MBL examines the ingress (incoming) packets to determine whether
they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority
mapping” value, as specified by the registers 12 and 13. The “priority mapping” value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
8
6
6
2
2
2
Preamble
DA
SA
VPID
TCI
length
Bits
802.1q VLAN Tag
16
Tagged Packet Type
(8100 for Ethernet)
3
1
802.1p
CFI
Bytes
46-1500
LLC
Data
4
FCS
12
VLAN ID
Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively.
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The KSZ8893MQL/MBL provides the option to insert or remove the priority tagged frame's header at each
individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control
Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets
{19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KSZ8893MQL/MBL will not add tags to already
tagged packets.
Tag Removal is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port,
tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8893MQL/MBL will not modify untagged
packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8893MQL/MBL to set the “User Priority
Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s
priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User
Priority Ceiling” is enabled by bit [3] of registers 17, 33 and 49 for ports 1, 2 and 3, respectively.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section.
The ToS priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP)
register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of
the ToS field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the
DSCP register to determine priority.
Rate Limiting Support
The KSZ8893MQL/MBL supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive
side” and on the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate
is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up
Ingress Rate Control Registers. On the transmit side, the data transmit rate for each priority queue at each port
can be limited by setting up Egress Rate Control Registers. The size of each frame has options to include
minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8893MQL/MBL provides options to selectively choose frames from all types,
multicast, broadcast, and flooded unicast frames. The KSZ8893MQL/MBL counts the data rate from those
selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate
limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output
traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The
throughput of each output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated
in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or
flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow
control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unknown Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the
static MAC address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address
is not recorded in the static table, and also not learned in the dynamic MAC table, KSZ8893MQL/MBL is then
configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is
enabled and configured in register 14.
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This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8893MQL/MBL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8893MQL/MBL is typically programmed using an EEPROM. If no EEPROM is
present, the KSZ8893MQL/MBL is configured using its default register settings. Some default settings are
configured via strap-in pin options. The strap-in pins are indicated in the “KSZ8893MQL/MBL Pin Description and
I/O Assignment” table.
2
I C Master Serial Bus Configuration
2
With an additional I C (“2-wire”) EEPROM, the KSZ8893MQL/MBL can perform more advanced switch features
like “broadcast storm protection” and “rate control” without the need of an external processor.
2
For KSZ8893MQL/MBL I C Master configuration, the EEPROM stores the configuration data for register 0 to
register 120 (as defined in the KSZ8893MQL/MBL register map) with the exception of the “Read Only” status
registers. After the de-assertion of reset, the KSZ8893MQL/MBL sequentially reads in the configuration data for
all 121 registers, starting from register 0. The configuration access time (tprgm) is less than 15 ms, as depicted in
the following figure.
RST_N
....
SCL
....
SDA
....
tprgm
