KSZ8895MLU-EVAL

KSZ8895MLU Integrated 5-Port 10/100 Managed Switch Revision 1.2 General Description The KSZ8895MLU is a highly-integrated Layer 2managed 5-port switch with an optimized design and plentiful features, qualified to meet AEC-Q100 standard for automotive applications. It is designed for costsensitive 10/100Mbps 5-port switch systems with on-chip termination, lowest power consumption and internal core power controller. These features will save more system cost. It has 1.4Gbps high-performance memory bandwidth, shared memory based switch fabric with full non-blocking configuration. It also provides an extensive feature set such as power management, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, quality-of-service (QoS) four-queue prioritization, management interface, and MIB counters. Port 5 is a MAC 5 MII interface with PHY mode as default at switch side. The SW5-MII interface can be connected to a processor with a MAC MII interface. The KSZ8895MLU consists of 10/100 PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8895MLU contains five MACs and four integrated PHYs. All PHYs support 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the SPI interface or the SMI interface. MIIM registers of the PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode. The KSZ8895MLU provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. Datasheets and support documentation are available on Micrel’s web site at: www.micrel.com. Functional Diagram KSZ8895MLU 10/100 T/Tx 1 PHY1 10/100 MAC 1 Auto MDI/MDIX 10/100 T/Tx 2 PHY2 10/100 MAC 2 Auto MDI/MDIX 10/100 T/Tx 3 PHY3 10/100 MAC 3 Auto MDI/MDIX 10/100 T/Tx 4 PHY4 10/100 MAC 4 MDC,MDI/O for MIIM and SMI SNI SNI SPI Control Reg SPI I/F LED0[5:1] LED1[5:1] LED2[5:1] LED I/F Control Registers Tagging, Priority 10/100 MAC 5 SW5-MII FIFO, Flow Control, VLAN Auto MDI/MDIX 1K Look Up Engine Queue Mgmnt Buffer Mgmnt Frame Buf fers MIB Counters EEPROM I/F Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com April 28, 2014 Revision 1.2 Micrel, Inc. KSZ8895MLU Features Advanced Switch Features                 IEEE 802.1q VLAN support for up to 128 VLAN groups (full-range 4096 of VLAN IDs). Static MAC table supports up to 32 entries. VLAN ID tag/untag options, per port basis. IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). Programmable rate limiting at the ingress and egress on a per port basis. Jitter-free per packet based rate-limiting support. Broadcast storm protection with percentage control (global and per port basis). IEEE 802.1d rapid spanning tree protocol RSTP support. Tail tag mode (1byte added before FCS) support at Port 5 to inform the processor which ingress port receives the packet. 1.4Gbps high-performance memory bandwidth and shared memory-based switch fabric with fully nonblocking configuration. MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII interface. Enable/Disable option for huge frame size up to 2000 bytes per frame. IGMP v1/v2 snooping (Ipv4) support for multicast packet filtering. IPv4/IPv6 QoS support. Support unknown unicast/multicast address and unknown VID packet filtering. Self-address filtering. Comprehensive Configuration Register Access     Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers. 2 High-speed SPI (up to 25MHz) and I C master Interface to all internal registers. I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode. Control registers configurable on the fly (port-priority, 802.1p/d/q, AN…). QoS/CoS Packet Prioritization Support     Per port, 802.1p and DiffServ-based. 1/2/4-queue QoS prioritization selection. Programmable weighted fair queuing for ratio control. Re-mapping of 802.1p priority field per port basis. Integrated 5-Port 10/100 Ethernet Switch    New generation switch with five MACs and five PHYs fully compliant with IEEE 802.3u standard. Non-blocking switch fabric assures fast packet delivery by utilizing a 1K MAC address lookup table and a storeand-forward architecture. New generation switch with five MACs and five PHYs fully compliant with IEEE 802.3u standard. April 28, 2014           Non-blocking switch fabric assures fast packet delivery by utilizing a 1K MAC address lookup table and a store-andforward architecture. On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table). Full duplex IEEE 802.3x flow control (PAUSE) with force mode option. Half-duplex back pressure flow control. HP Auto MDI/MDI-X and IEEE Auto crossover support. Port 5 MAC5 SW5-MII interface supports PHY mode and MAC mode. 7-wire serial network interface (SNI) support for legacy MAC. Per port LED Indicators for link, activity, and 10/100 speed. Register port status support for link, activity, full/half duplex and 10/100 speed. On-chip terminations and internal biasing technology for cost down and lowest power consumption. Switch Monitoring Features     Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII. MIB counters for fully-compliant statistics gathering 34 MIB counters per port. Loop-back support for MAC, PHY, and remote diagnostic of failure. Interrupt for the link change on any ports. Low Power Dissipation          Full-chip hardware power-down. Full-chip software power-down/per port software power down. Energy-detect mode support