KSZ9031MNX
Gigabit Ethernet Transceiver with GMII/MII
Support
Features
Target Applications
• Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications
• GMII/MII Standard Interface with 3.3V/2.5V/1.8V
Tolerant I/Os
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100/1000 Mbps) and
Duplex (Half/Full)
• On-Chip Termination Resistors for the Differential
Pairs
• On-Chip LDO Controller to Support Single 3.3V
Supply Operation
• Jumbo Frame Support Up to 16 KB
• 125 MHz Reference Clock Output
• Energy-Detect Power-Down Mode for Reduced
Power Consumption When the Cable is Not
Attached
• Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection
• Programmable LED Outputs for Link, Activity, and
Speed
• Baseline Wander Correction
• LinkMD TDR-based Cable Diagnostic to Identify
Faulty Copper Cabling
• Parametric NAND Tree Support to Detect Faults
Between Chip I/Os and Board
• Loopback Modes for Diagnostics
• Automatic MDI/MDI-X Crossover to Detect and
Correct Pair Swap at All Speeds of Operation
• Automatic Detection and Correction of Pair
Swaps, Pair Skew, and Pair Polarity
• MDC/MDIO Management Interface for PHY Register Configuration
• Interrupt Pin Option
• Power-Down and Power-Saving Modes
• Operating Voltages
- Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V
(External FET or Regulator)
- VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
- Transceiver (AVDDH): 3.3V or 2.5V
(Commercial Temp.)
• 64-pin QFN (8 mm × 8 mm) Package
•
•
•
•
•
•
•
•
•
•
•
DS00002096F-page 1
Laser/Network Printer
Network Attached Storage (NAS)
Network Server
Broadband Gateway
Gigabit SOHO/SMB Router
IPTV
IP Set-Top Box
Game Console
IP Camera
Triple-Play (Data, Voice, Video) Media Center
Media Converter
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
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DS00002096F-page 2
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 13
4.0 Register Descriptions .................................................................................................................................................................... 29
5.0 Operational Characteristics ........................................................................................................................................................... 49
6.0 Electrical Characteristics ............................................................................................................................................................... 50
7.0 Timing Diagrams ........................................................................................................................................................................... 54
8.0 Reset Circuit ................................................................................................................................................................................. 61
9.0 Reference Circuits — LED Strap-In Pins ...................................................................................................................................... 63
10.0 Reference Clock - Connection and Selection ............................................................................................................................. 64
11.0 On-Chip LDO Controller - MOSFET Selection ............................................................................................................................ 64
12.0 Magnetic - Connection and Selection ......................................................................................................................................... 65
13.0 Package Outlines ........................................................................................................................................................................ 67
Appendix A: Data Sheet Revision History ........................................................................................................................................... 69
The Microchip Web Site ...................................................................................................................................................................... 70
Customer Change Notification Service ............................................................................................................................................... 70
Customer Support ............................................................................................................................................................................... 70
Product Identification System ............................................................................................................................................................. 71
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 3
KSZ9031MNX
1.0
INTRODUCTION
1.1
General Description
The KSZ9031MNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physicallayer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9031MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent
Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000 Mbps
or 10/100 Mbps.
The KSZ9031MNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four
differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.
The KSZ9031MNX offers diagnostic features to facilitate system bring-up and debugging in production testing and in
product deployment. Parametric NAND tree support enables fault detection between KSZ9031MNX I/Os and the board.
The LinkMD® TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify
analog and digital data paths.
The KSZ9031MNX is available in a 64-pin, lead-free QFN package.
GMII/MII
10/100/1000Mbps
GMII/MII
ETHERNET MAC
MDC/MDIO
MANAGEMENT
KSZ9031MNX
DS00002096F-page 4
RJ-45
CONNECTOR
MEDIA TYPES
10Base-T
100Base-TX
1000Base-T
LDO
CONTROLLER
PME_N
(SYSTEM POWER CIRCUIT)
MAGNETICS
SYSTEM BLOCK DIAGRAM
ON-CHIP TERMINATION
RESISTORS
FIGURE 1-1:
VIN
3.3VA
VOUT
1.2V (FOR CORE VOLTAGES)
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
PIN DESCRIPTION AND CONFIGURATION
ISET
NC
XI
XO
AVDDL_PLL
LDO_O
TX_CLK
RESET_N
CLK125_NDO /
LED_MODE
DVDDL
INT_N /
PME_N2
COL
MDIO
MDC
CRS
64-QFN PIN ASSIGNMENT (TOP VIEW)
AGNDH
FIGURE 2-1:
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDDH
1
48
RX_CLK /
PHYAD2
TXRXP_A
2
47
RX_ER
TXRXM_A
3
46
DVDDH
AVDDL
4
45
RX_DV /
CLK125_EN
AVDDL
5
44
RXD0/
MODE0
NC
6
43
RXD1/
MODE1
TXRXP_B
7
42
DVDDL
TXRXM_B
8
KSZ9031MNX
41
RXD2/
MODE2
AGNDH
9
PADDLE GROUND
40
DVDDH
39
RXD3/
MODE3
(ON BOTTOM OF CHIP)
TXRXP_C
10
TXRXM_C
11
38
RXD4
AVDDL 12
37
RXD5
AVDDL 13
36
DVDDL
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TXD6
TXD7
DVDDH
TX_ER
GTX_CLK
TX_EN
TXD5
33
TXD4
AVDDH 16
DVDDL
RXD7
TXD3
34
TXD2
15
TXD1
TXRXM_D
TXD0
RXD6
DVDDL
35
LED1 /
PME_N1 /
PHYAD0
14
DVDDH
TXRXP_D
LED2 /
PHYAD1
2.0
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 5
KSZ9031MNX
TABLE 2-1:
SIGNALS - KSZ9031MNX
Pin
Number
Pin
Name
Type
Note
2-1
1
AVDDH
P
2
Description
3.3V/2.5V (commercial temperature only) analog VDD
I/O
Media Dependent Interface[0], positive signal of differential pair
1000BASE-T mode: TXRXP_A corresponds to BI_DA+ for MDI configuration
and BI_DB+ for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXP_A is the positive transmit signal
(TX+) for MDI configuration and the positive receive signal (RX+) for MDI-X
configuration, respectively.
TXRXM_A
I/O
Media Dependent Interface[0], negative signal of differential pair
1000BASE-T mode: TXRXM_A corresponds to BI_DA– for MDI configuration
and BI_DB– for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXM_A is the negative transmit signal
(TX–) for MDI configuration and the negative receive signal (RX–) for MDI-X
configuration, respectively.
4
AVDDL
P
1.2V analog VDD
5
AVDDL
P
1.2V analog VDD
6
NC
—
No connect
I/O
Media Dependent Interface[1], positive signal of differential pair
1000BASE-T mode: TXRXP_B corresponds to BI_DB+ for MDI configuration
and BI_DA+ for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXP_B is the positive receive signal
(RX+) for MDI configuration and the positive transmit signal (TX+) for MDI-X
configuration, respectively.
TXRXM_B
I/O
Media Dependent Interface[1], negative signal of differential pair
1000BASE-T mode: TXRXM_B corresponds to BI_DB– for MDI configuration
and BI_DA– for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXM_B is the negative receive signal
(RX–) for MDI configuration and the negative transmit signal
(TX–) for MDI-X configuration, respectively.
AGNDH
GND
TXRXP_A
3
7
TXRXP_B
8
9
10
TXRXP_C
Analog ground
I/O
Media Dependent Interface[2], positive signal of differential pair
1000BASE-T mode: TXRXP_C corresponds to BI_DC+ for MDI configuration
and BI_DD+ for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXP_C is not used.
Media Dependent Interface[2], negative signal of differential pair
1000BASE-T mode: TXRXM_C corresponds to BI_DC– for MDI configuration
and BI_DD– for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXM_C is not used.
11
TXRXM_C
I/O
12
AVDDL
P
1.2V analog VDD
13
AVDDL
P
1.2V analog VDD
DS00002096F-page 6
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 2-1:
Pin
Number
14
SIGNALS - KSZ9031MNX (CONTINUED)
Pin
Name
TXRXP_D
Type
Note
2-1
Description
I/O
Media Dependent Interface[3], positive signal of differential pair
1000BASE-T mode: TXRXP_D corresponds to BI_DD+ for MDI configuration
and BI_DC+ for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXP_D is not used.
Media Dependent Interface[3], negative signal of differential pair
1000BASE-T mode: TXRXM_D corresponds to BI_DD– for MDI configuration
and BI_DC– for MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode: TXRXM_D is not used.
15
TXRXM_D
I/O
16
AVDDH
P
3.3V/2.5V (commercial temperature only) analog VDD
LED2 output: Programmable LED2 output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of PHYAD[1]. See the Strapping Options - KSZ9031MNX section for details.
The LED2 pin is programmed by the LED_MODE strapping option (Pin 55),
and is defined as follows:
Single-LED Mode
Link
Pin State
LED Definition
Link Off
H
OFF
Link On (any speed)
L
ON
Pin State
LED Definition
Tri-Color Dual-LED Mode
Link/Activity
17
LED2/
PHYAD1
LED2
LED1
LED2
LED1
Link Off
H
H
OFF
OFF
1000 Link/No Activity
L
H
ON
OFF
Toggle
H
Blinking
OFF
100 Link/No Activity
H
L
OFF
ON
100 Link/Activity
(RX, TX)
H
Toggle
OFF
Blinking
10 Link/No Activity
L
L
ON
ON
Toggle
Toggle
Blinking
Blinking
I/O
1000 Link/Activity
(RX, TX)
10 Link/Activity
(RX, TX)
For tri-color dual-LED mode, LED2 works in conjunction with LED1 (Pin 19) to
indicate 10 Mbps link and activity.
18
DVDDH
P
3.3V, 2.5V, or 1.8V digital VDD_IO
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 7
KSZ9031MNX
TABLE 2-1:
Pin
Number
SIGNALS - KSZ9031MNX (CONTINUED)
Pin
Name
Type
Note
2-1
Description
LED1 output: Programmable LED1 output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of PHYAD[0]. See the Strapping Options - KSZ9031MNX section for details.
PME_N output: Programmable PME_N output (pin option 1). This pin function
requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range
from 1.0 kΩ to 4.7 kΩ. When asserted low, this pin signals that a WOL event
has occurred.
This pin is not an open-drain for all operating modes.
The LED1 pin is programmed by the LED_MODE strapping option (Pin 55),
and is defined as follows:
Single-LED Mode
Activity
Pin State
LED Definition
H
OFF
Toggle
Blinking
Pin State
LED Definition
No Activity
Activity (RX, TX)
19
LED1/
PHYAD0/
PME_N1
Tri-Color Dual-LED Mode
I/O
Link/Activity
LED2
LED1
LED2
LED1
Link Off
H
H
OFF
OFF
1000 Link/No Activity
L
H
ON
OFF
Toggle
H
Blinking
OFF
100 Link/No Activity
H
L
OFF
ON
100 Link/Activity
(RX, TX)
H
Toggle
OFF
Blinking
10 Link/No Activity
L
L
ON
ON
Toggle
Toggle
Blinking
Blinking
1000 Link/Activity
(RX, TX)
10 Link/Activity
(RX, TX)
For tri-color dual-LED mode, LED1 works in conjunction with LED2 (Pin 17) to
indicate 10 Mbps link and activity.
20
21
22
23
DVDDL
P
1.2V digital VDD
TXD0
I
GMII mode: GMII TXD0 (Transmit Data 0) input
MII mode: MII TXD0 (Transmit Data 0) input
TXD1
I
GMII mode: GMII TXD1 (Transmit Data 1) input
MII mode: MII TXD1 (Transmit Data 1) input
TXD2
I
GMII mode: GMII TXD2 (Transmit Data 2) input
MII mode: MII TXD2 (Transmit Data 2) Input
DS00002096F-page 8
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 2-1:
Pin
Number
24
25
26
27
28
29
30
SIGNALS - KSZ9031MNX (CONTINUED)
Pin
Name
Type
Note
2-1
TXD3
I
GMII mode: GMII TXD3 (Transmit Data 3) input
MII mode: MII TXD3 (Transmit Data 3) input
DVDDL
P
1.2V digital VDD
TXD4
I
GMII mode: GMII TXD4 (Transmit Data 4) input
MII mode: This pin is not used and can be driven high or low.
TXD5
I
GMII mode: GMII TXD5 (Transmit Data 5) input
MII mode: This pin is not used and can be driven high or low.
TXD6
I
GMII mode: GMII TXD6 (Transmit Data 6) input
MII Mode: This pin is not used and can be driven high or low.
TXD7
I
GMII mode: GMII TXD7 (Transmit Data 7) input
MII mode: This pin is not used and can be driven high or low.
DVDDH
P
3.3V, 2.5V, or 1.8V digital VDD_IO
I
GMII mode: GMII TX_ER (Transmit Error) input
MII mode: MII TX_ER (Transmit Error) input
If the GMII/MII MAC does not provide the TX_ER output signal, this pin
should be tied low.
Description
31
TX_ER
32
GTX_CLK
I
GMII mode: GMII GTX_CLK (Transmit Reference Clock) input
TX_EN
I
GMII mode: GMII TX_EN (Transmit Enable) input
MII mode: MII TX_EN (Transmit Enable) input
RXD7
O
GMII mode: GMII RXD7 (Receive Data 7) output
MII mode: This pin is not used and is driven low.
RXD6
O
GMII mode: GMII RXD6 (Receive Data 6) output
MII mode: This pin is not used and is driven low.
DVDDL
P
1.2V digital VDD
RXD5
O
GMII mode: GMII RXD5 (Receive Data 5) output
MII mode: This pin is not used and is driven low.
RXD4
O
GMII mode: GMII RXD4 (Receive Data 4) output
MII mode: This pin is not used and is driven low.
I/O
GMII mode: GMII RXD3 (Receive Data 3) output
MII mode: MII RXD3 (Receive Data 3) output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of MODE3. See the Strapping
Options - KSZ9031MNX section for details.
33
34
35
36
37
38
39
RXD3/
MODE3
40
DVDDH
P
I/O
41
RXD2/
MODE2
42
DVDDL
P
3.3V, 2.5V, or 1.8V digital VDD_IO
GMII mode: GMII RXD2 (Receive Data 2) output
MII mode: MII RXD2 (Receive Data 2) output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of MODE2. See the Strapping
Options - KSZ9031MNX section for details.
1.2V digital VDD
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 9
KSZ9031MNX
TABLE 2-1:
Pin
Number
43
44
SIGNALS - KSZ9031MNX (CONTINUED)
Pin
Name
RXD1/
MODE1
RXD0/
MODE0
Type
Note
2-1
Description
I/O
GMII mode: GMII RXD1 (Receive Data 1) output
MII mode: MII RXD1 (Receive Data 1) output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of MODE1. See the Strapping
Options - KSZ9031MNX section for details.
I/O
GMII mode: GMII RXD0 (Receive Data 0) output
MII mode: MII RXD0 (Receive Data 0) output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of MODE0. See the Strapping
Options - KSZ9031MNX section for details.
GMII mode: GMII RX_DV (Receive Data Valid) output
MII mode: MII RX_DV (Receive Data Valid) output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of CLK125_EN. See the
Strapping Options - KSZ9031MNX section for details.
45
RX_DV/
CLK125_EN
I/O
46
DVDDH
P
3.3V, 2.5V, or 1.8V digital VDD_IO
RX_ER
O
GMII mode: GMII RX_ER (Receive Error) output
MII mode: MII RX_ER (Receive Error) output
47
48
49
50
RX_CLK/
PHYAD2
I/O
CRS
O
MDC
Ipu
MDIO
Ipu/O
COL
O
51
52
GMII mode: GMII RX_CLK (Receive Reference Clock) output
MII mode: MII RX_CLK (Receive Reference Clock) output
Config mode: The voltage on this pin is sampled and latched during the
power up/reset process to determine the value of PHYAD[2]. See the Strapping Options - KSZ9031MNX section for details.
GMII mode: GMII CRS (Carrier Sense) output
MII mode: MII CRS (Carrier Sense) output
Management data clock input
This pin is the input reference clock for MDIO (Pin 51).
Management data input/output
This pin is synchronous to MDC (Pin 50) and requires an external pull-up
resistor to DVDDH (digital VDD_IO) in a range from 1.0 kΩ to 4.7 kΩ.
GMII mode: GMII COL (Collision Detected) output
MII mode: MII COL (Collision Detected) output
53
INT_N/
PME_N2
O
Interrupt output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status Register, for programming the interrupt conditions
and reading the interrupt status. Register 1Fh, Bit [14] sets the interrupt output to active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
For Interrupt (when active low) and PME functions, this pin requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0 kΩ to
4.7 kΩ.
This pin is not an open-drain for all operating modes.
54
DVDDL
P
1.2V digital VDD
DS00002096F-page 10
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 2-1:
Pin
Number
55
SIGNALS - KSZ9031MNX (CONTINUED)
Pin
Name
CLK125_NDO/
LED_MODE
Type
Note
2-1
I/O
125 MHz clock output
This pin provides a 125 MHz reference clock output option for use by the
MAC.
Config mode: The voltage on this pin is sampled during the power-up/reset
process to determine the value of LED_MODE. See the Strapping Options KSZ9031MNX section for details.
Chip reset (active low)
Hardware pin configurations are strapped-in (sampled and latched) at the deassertion (rising edge) of RESET_N. See the Strapping Options KSZ9031MNX section for details.
56
RESET_N
Ipu
57
TX_CLK
O
58
LDO_O
Description
O
MII mode: MII TX_CLK (Transmit Reference Clock) output
On-chip 1.2V LDO controller output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for
the chip’s core voltages. If the system provides 1.2V and this pin is not used,
it can be left floating.
Note:
59
60
AVDDL_PLL
XO
This pin should never be driven externally.
P
1.2V analog VDD for PLL
O
25 MHz crystal feedback
This pin connects to one end of an external 25 MHz crystal.
This pin is a no connect if an oscillator or other external (non-crystal) clock
source is used.
Crystal/Oscillator/External Clock input
This pin connects to one end of an external 25 MHz crystal or to the output of
an oscillator or other external (non-crystal) clock source.
25 MHz ±50 ppm tolerance
61
XI
I
62
NC
—
No connect
This pin is not bonded and can be connected to AVDDH power for footprint
compatibility with the KSZ9021GN Gigabit PHY.
63
ISET
I/O
Set the transmit output level.
Connect a 12.1 kΩ 1% resistor to ground on this pin.
64
AGNDH
GND
Analog ground.
P_GND
GND
Exposed paddle on bottom of chip.
Connect P_GND to ground.
Paddle
Note 2-1
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 11
KSZ9031MNX
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
the power-up or reset process, and consequently cause the PHY strap-in pins on the GMII/MII signals to be latched to
the incorrect configuration. In this case, external pull-up or pull-down resistors should be added on the PHY strap-in pins
to ensure the PHY is configured to the correct pin strap-in mode.
TABLE 2-2:
Pin Number
48
17
19
STRAPPING OPTIONS - KSZ9031MNX
Pin Name
PHYAD2
PHYAD1
PHYAD0
Type
Note 2-1
Description
I/O
I/O
I/O
The PHY address, PHYAD[2:0], is sampled and latched at power-up/
reset and is configurable to any value from 0 to 7. Each PHY address
bit is configured as follows:
Pull-up = 1
Pull-down = 0
PHY Address Bits [4:3] are always set to ‘00’.
The MODE[3:0] strap-in pins are sampled and latched at power-up/
reset and are defined as follows:
39
41
43
44
45
55
Note 2-1
MODE3
MODE2
MODE1
MODE0
CLK125_EN
LED_MODE
I/O
I/O
I/O
I/O
MODE[3:0]
Mode
0000
Reserved - not used
0001
GMII/MII mode
0010
Reserved - not used
0011
Reserved - not used
0100
NAND tree mode
0101
Reserved - not used
0110
Reserved - not used
0111
Chip power-down mode
1000
Reserved - not used
1001
Reserved - not used
1010
Reserved - not used
1011
Reserved - not used
1100
Reserved - not used
1101
Reserved - not used
1110
Reserved - not used
1111
Reserved - not used
I/O
CLK125_EN is sampled and latched at power-up/reset and is
defined as follows:
Pull-up (1) = Enable 125 MHz clock output
Pull-down (0) = Disable 125 MHz clock output
Pin 55 (CLK125_NDO) provides the 125 MHz reference clock output
option for use by the MAC.
I/O
LED_MODE is sampled and latched at power-up/reset and is
defined as follows:
Pull-up (1) = Single-LED mode
Pull-down (0) = Tri-color dual-LED mode
I/O = Bi-directional.
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KSZ9031MNX
3.0
FUNCTIONAL DESCRIPTION
The KSZ9031MNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical
layer transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP)
cable.
The KSZ9031MNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four
differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.
On the copper media interface, the KSZ9031MNX can automatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as
specified in the IEEE 802.3 standard for 1000BASE-T operation.
The KSZ9031MNX provides the GMII/MII interface for connection to GMACs in Gigabit Ethernet processors and
switches for data transfer at 10/100/1000Mbps.
Figure 3-1 shows a high-level block diagram of the KSZ9031MNX.
FIGURE 3-1:
KSZ9031MNX BLOCK DIAGRAM
PMA
TX10/100/1000
CLOCK
RESET
CONFIGURATIONS
PMA
RX1000
PCS1000
MEDIA
INTERFACE
PMA
RX100
PCS100
PMA
RX10
PCS10
AUTONEGOTIATION
3.1
3.1.1
GMII/MII
INTERFACE
LED
DRIVERS
10BASE-T/100BASE-TX Transceiver
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is
set by an external 12.1 kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, and overshoot. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion are a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
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KSZ9031MNX
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data conversion circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to the GMII/MII format and provided as the input data to the MAC.
3.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The
scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream
using the same sequence as at the transmitter.
3.1.4
10BASE-T TRANSMIT
The 10BASE-T output drivers are incorporated into the 100BASE-TX drivers to allow for transmission with the same
magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with typical amplitude of
2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASE-T/
10BASE-Te signals have harmonic contents that are at least 31 dB below the fundamental frequency when driven by
an all-ones Manchester-encoded signal.
3.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths to prevent
noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks
onto the incoming signal and the KSZ9031MNX decodes a data frame. The receiver clock is maintained active during
idle periods between receiving data frames.
The KSZ9031MNX removes all 7 bytes of the preamble and presents the received frame starting with the SFD (start of
frame delimiter) to the MAC.
Auto-polarity correction is provided for the receiving differential pair to automatically swap and fix the incorrect +/– polarity wiring in the cabling.
3.2
1000BASE-T Transceiver
The 1000BASE-T transceiver is based-on a mixed-signal/digital-signal processing (DSP) architecture, which includes
the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, precision clock recovery scheme, and power-efficient line drivers.
Figure 3-2 shows a high-level block diagram of a single channel of the 1000BASE-T transceiver for one of the four differential pairs.
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KSZ9031MNX
FIGURE 3-2:
KSZ9031MNX 1000BASE-T BLOCK DIAGRAM - SINGLE CHANNEL
XTAL
OTHER
CHANNELS
CLOCK
GENERATION
TX
SIGNAL
SIDE -STREAM
SCRAMBLER
&
SYMBOL ENCODER
TRANSMIT
BLOCK
PCS STATE
MACHINES
LED DRIVER
NEXT
CANCELLER
NEXT
Canceller
NEXT Canceller
ECHO
CANCELLER
ANALOG
HYBRID
PAIR SWAP
&
ALIGN UNIT
BASELINE
WANDER
COMPENSATION
RXADC
AGC
RX
SIGNAL
FFE
+
CLOCK & PHASE
RECOVERY
AUTO NEGOTIATION
DESCRAMBLER
+
DECODER
SLICER
DFE
MII
REGISTERS
MII
MANAGEMENT
CONTROL
PMA STATE
MACHINES
3.2.1
ANALOG ECHO-CANCELLATION CIRCUIT
In 1000BASE-T mode, the analog echo-cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit
relieves the burden of the ADC and the adaptive equalizer.
This circuit is disabled in 10BASE-T/100BASE-TX mode.
3.2.2
AUTOMATIC GAIN CONTROL (AGC)
In 1000BASE-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal
level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.
3.2.3
ANALOG-TO-DIGITAL CONVERTER (ADC)
In 1000BASE-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential to the overall performance of the transceiver.
This circuit is disabled in 10BASE-T/100BASE-TX mode.
3.2.4
TIMING RECOVERY CIRCUIT
In 1000BASE-T mode, the mixed-signal clock recovery circuit together with the digital phase-locked loop is used to
recover and track the incoming timing information from the received data. The digital phase-locked loop has very low
long-term jitter to maximize the signal-to-noise ratio of the receive signal.
The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to
the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This
also helps to facilitate echo cancellation and NEXT removal.
3.2.5
ADAPTIVE EQUALIZER
In 1000BASE-T mode, the adaptive equalizer provides the following functions:
• Detection for partial response signaling
• Removal of NEXT and ECHO noise
• Channel equalization
Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch.
The KSZ9031MNX uses a digital echo canceler to further reduce echo components on the receive signal.
In 1000BASE-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels).
This results in high-frequency cross-talk coming from adjacent wires. The KSZ9031MNX uses three NEXT cancelers
on each receive channel to minimize the cross-talk induced by the other three channels.
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DS00002096F-page 15
KSZ9031MNX
In 10BASE-T/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and
recover the channel loss from the incoming data.
3.2.6
TRELLIS ENCODER AND DECODER
In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5
symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one
KSZ9031MNX is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed,
pair skew, pair order, and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted
into 9-bit symbols and de-scrambled into 8-bit data.
3.3
Auto MDI/MDI-X
The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable
between the KSZ9031MNX and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the
link partner, and assigns the MDI/MDI-X pair mapping of the KSZ9031MNX accordingly.
Table 3-1 shows the KSZ9031MNX 10/100/1000 pin configuration assignments for MDI/MDI-X pin mapping.
TABLE 3-1:
Pin
(RJ-45 Pair)
MDI/MDI-X PIN MAPPING
MDI
MDI-X
1000BASE-T
100BASE-T
10BASE-T
1000BASE-T
100BASE-T
10BASE-T
TXRXP/M_A
(1, 2)
A+/–
TX+/–
TX+/–
B+/–
RX+/–
RX+/–
TXRXP/M_B
(3, 6)
B+/–
RX+/–
RX+/–
A+/–
TX+/–
TX+/–
TXRXP/M_C
(4, 5)
C+/–
Not Used
Not Used
D+/–
Not Used
Not Used
TXRXP/M_D
(7, 8)
D+/–
Not Used
Not Used
C+/–
Not Used
Not Used
Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to Register 1Ch, Bit [6]. MDI and MDI-X mode is
set by Register 1Ch, Bit [7] if Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
3.4
Pair-Swap, Alignment, and Polarity Check
In 1000BASE-T mode, the KSZ9031MNX
• Detects incorrect channel order and automatically restores the pair order for the A, B, C, D pairs (four channels).
• Supports 50 ns ±10 ns difference in propagation delay between pairs of channels in accordance with the IEEE
802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchronized.
Incorrect pair polarities of the differential signals are automatically corrected for all speeds.
3.5
Wave Shaping, Slew-Rate Control, and Partial Response
In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and
to minimize distortion and error in the transmission channel.
• For 1000BASE-T, a special partial-response signaling method is used to provide the band-limiting feature for the
transmission path.
• For 100BASE-TX, a simple slew-rate control method is used to minimize EMI.
• For 10BASE-T, pre-emphasis is used to extend the signal quality through the cable.
3.6
PLL Clock Synthesizer
The KSZ9031MNX generates 125 MHz, 25 MHz, and 10 MHz clocks for system timing. Internal clocks are generated
from the external 25 MHz crystal or reference clock.
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KSZ9031MNX
3.7
Auto-Negotiation
The KSZ9031MNX conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows UTP (unshielded twisted pair) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the operating mode.
The following list shows the speed and duplex operation mode from highest-to-lowest:
•
•
•
•
•
•
Priority 1: 1000BASE-T, full-duplex
Priority 2: 1000BASE-T, half-duplex
Priority 3: 100BASE-TX, full-duplex
Priority 4: 100BASE-TX, half-duplex
Priority 5: 10BASE-T, full-duplex
Priority 6: 10BASE-T, half-duplex
If auto-negotiation is not supported or the KSZ9031MNX link partner is forced to bypass auto-negotiation for 10BASET and 100BASE-TX modes, the KSZ9031MNX sets its operating mode by observing the input signal at its receiver. This
is known as parallel detection, and allows the KSZ9031MNX to establish a link by listening for a fixed signal protocol in
the absence of the auto-negotiation advertisement protocol.
The auto-negotiation link-up process is shown in Figure 3-3.
FIGURE 3-3:
AUTO-NEGOTIATION FLOW CHART
START AUTO-NEGOTIATION
FORCE LINK SETTING
NO
PARALLEL
OPERATION
YES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
ATTEMPT AUTONEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
For 1000BASE-T mode, auto-negotiation is required and always used to establish a link. During 1000BASE-T autonegotiation, the master and slave configuration is first resolved between link partners. Then the link is established with
the highest common capabilities between link partners.
Auto-negotiation is enabled by default after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled through Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bits [6, 13] and
the duplex is set by Register 0h, Bit [8].
If the speed is changed on the fly, the link goes down and either auto-negotiation or parallel detection initiates until a
common speed between KSZ9031MNX and its link partner is re-established for a link.
If the link is already established and there is no change of speed on the fly, the changes (for example, duplex and pause
capabilities) will not take effect unless either auto-negotiation is restarted through Register 0h, Bit [9], or a link-down to
link-up transition occurs (that is, disconnecting and reconnecting the cable).
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DS00002096F-page 17
KSZ9031MNX
After auto-negotiation is completed, the link status is updated in Register 1h, Bit [2], and the link partner capabilities are
updated in Registers 5h, 6h, and Ah.
The auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. The duration of
these timers under normal operating conditions is summarized in Table 3-2.
TABLE 3-2:
AUTO-NEGOTIATION TIMERS
Auto-Negotiation Interval Timers
Time Duration
Transmit Burst Interval
16 ms
Transmit Pulse Interval
68 µs
FLP Detect Minimum Time
17.2 µs
FLP Detect Maximum Time
185 µs
Receive Minimum Burst Interval
6.8 ms
Receive Maximum Burst Interval
112 ms
Data Detect Minimum Interval
35.4 µs
Data Detect Maximum Interval
95 µs
NLP Test Minimum Interval
4.5 ms
NLP Test Maximum Interval
30 ms
Link Loss Time
52 ms
Break Link Time
1480 ms
Parallel Detection Wait Time
830 ms
Link Enable Wait Time
1000 ms
3.8
10/100 Mbps Speeds Only
Some applications require link-up to be limited to 10/100 Mbps speeds only.
After power-up/reset, the KSZ9031MNX can be restricted to auto-negotiate and link-up to 10/100 Mbps speeds only by
programming the following register settings:
1.
2.
3.
Set Register 0h, Bit [6] = ‘0’ to remove 1000 Mbps speed.
Set Register 9h, Bits [9:8] = ‘00’ to remove Auto-Negotiation advertisements for 1000 Mbps full/half duplex.
Write a ‘1’ to Register 0h, Bit [9], a self-clearing bit, to force a restart of Auto-Negotiation.
Auto-Negotiation and 10BASE-T/100BASE-TX speeds use only differential pairs A (pins 2, 3) and B (pins 7, 8). Differential pairs C (pins 10, 11) and D (pins 14, 15) can be left as no connects.
3.9
GMII Interface
The Gigabit Media Independent Interface (GMII) is compliant to the IEEE 802.3 Specification. It provides a common
interface between GMII PHYs and MACs, and has the following key characteristics:
• Pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision
indication).
• 1000 Mbps is supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 8 bits wide, a byte.
In GMII operation, the GMII pins function as follows:
•
•
•
•
•
The MAC sources the transmit reference clock, GTX_CLK, at 125 MHz for 1000 Mbps.
The PHY recovers and sources the receive reference clock, RX_CLK, at 125 MHz for 1000 Mbps.
TX_EN, TXD[7:0], and TX_ER are sampled by the KSZ9031MNX on the rising edge of GTX_CLK.
RX_DV, RXD[7:0], and RX_ER are sampled by the MAC on the rising edge of RX_CLK.
CRS and COL are driven by the KSZ9031MNX and do not have to transition synchronously with respect to either
GTX_CLK or RX_CLK.
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KSZ9031MNX
The KSZ9031MNX combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/
1000 Mbps. After power-up or reset, the KSZ9031MNX is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to ‘0001’. See the Strapping Options - KSZ9031MNX section.
The KSZ9031MNX has the option to output a 125 MHz reference clock on CLK125_NDO (Pin 55). This clock provides
a lower-cost reference clock alternative for GMII/MII MACs that require a 125 MHz crystal or oscillator. The 125 MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9031MNX provides a dedicated transmit clock input pin (GTX_CLK, Pin 32) for GMII mode, which is sourced
by the MAC for 1000 Mbps speed.
3.9.1
GMII SIGNAL DEFINITION
Table 3-3 describes the GMII signals. Refer to Clause 35 of the IEEE 802.3 Specification for more detailed information.
TABLE 3-3:
GMII SIGNAL DEFINITION
GMII Signal Name GMII Signal Name Pin Type (with
Pin Type (with
Description
(per spec)
(per KSZ9031MNX) respect to PHY) respect to MAC)
GTX_CLK
GTX_CLK
Input
Output
Transmit Reference Clock
(125 MHz for 1000 Mbps)
TX_EN
TX_EN
Input
Output
Transmit Enable
TXD[7:0]
TXD[7:0]
Input
Output
Transmit Data[7:0]
TX_ER
TX_ER
Input
Output
Transmit Error
RX_CLK
RX_CLK
Output
Input
3.9.2
Receive Reference Clock
(125 MHz for 1000 Mbps)
RX_DV
RX_DV
Output
Input
Receive Data Valid
RXD[7:0]
RXD[7:0]
Output
Input
Receive Data[7:0]
RX_ER
RX_ER
Output
Input
Receive Error
CRS
CRS
Output
Input
Carrier Sense
COL
COL
Output
Input
Collision Detected
GMII SIGNAL DIAGRAM
The KSZ9031MNX GMII pin connections to the MAC are shown in Figure 3-4.
FIGURE 3-4:
KSZ9031MNX GMII INTERFACE
KSZ9031MNX
GTX _CLK
GMII
ETHERNET MAC
GTX _CLK
TX _EN
TX _EN
TXD[7:0]
TXD[7:0]
TX_ER
RX_CLK
TX_ER
RX_CLK
RX _DV
RX _DV
RXD[7:0]
RXD[7:0]
RX _ER
RX _ER
CRS
CRS
COL
COL
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 19
KSZ9031MNX
3.10
MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication).
• 10 Mbps and 100 Mbps are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
In MII operation, the MII pins function as follows:
• The PHY sources the transmit reference clock, TX_CLK, at 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.
• The PHY recovers and sources the receive reference clock, RX_CLK, at 25 MHz for 100 Mbps and 2.5 MHz for
10 Mbps.
• TX_EN, TXD[3:0], and TX_ER are driven by the MAC and transition synchronously with respect to TX_CLK.
• RX_DV, RXD[3:0], and RX_ER are driven by the KSZ9031MNX and transition synchronously with respect to
RX_CLK.
• CRS and COL are driven by the KSZ9031MNX and do not have to transition synchronously with respect to either
TX_CLK or RX_CLK.
The KSZ9031MNX combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/
1000 Mbps. After power-up or reset, the KSZ9031MNX is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to ‘0001’. See the Strapping Options - KSZ9031MNX section.
The KSZ9031MNX has the option to output a 125 MHz reference clock on CLK125_NDO (Pin 55). This clock provides
a lower-cost reference clock alternative for GMII/MII MACs that require a 125 MHz crystal or oscillator. The 125 MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9031MNX provides a dedicated transmit clock output pin (TX_CLK, Pin 57) for MII mode, which is sourced by
the KSZ9031MNX for 10/100 Mbps speed.
3.10.1
MII SIGNAL DEFINITION
Table 3-4 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-4:
MII SIGNAL DEFINITION
MII Signal Name
MII Signal Name
Pin Type (with
Pin Type (with
Description
(per spec)
(per KSZ9031MNX) respect to PHY) respect to MAC)
Transmit Reference Clock
(25 MHz for 100 Mbps, 2.5 MHz for
10 Mbps)
TX_CLK
TX_CLK
Output
Input
TX_EN
TX_EN
Input
Output
TXD[3:0]
TXD[3:0]
Input
Output
Transmit Data[3:0]
TX_ER
TX_ER
Input
Output
Transmit Error
RX_CLK
RX_CLK
Output
Input
Transmit Enable
Receive Reference Clock
(25 MHz for 100 Mbps, 2.5 MHz for
10 Mbps)
RX_DV
RX_DV
Output
Input
Receive Data Valid
RXD[3:0]
RXD[3:0]
Output
Input
Receive Data[3:0]
RX_ER
RX_ER
Output
Input
Receive Error
CRS
CRS
Output
Input
Carrier Sense
COL
COL
Output
Input
Collision Detection
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KSZ9031MNX
3.10.2
MII SIGNAL DIAGRAM
The KSZ9031MNX MII pin connections to the MAC are shown in Figure 3-5.
FIGURE 3-5:
KSZ9031MNX MII INTERFACE
MII
ETHERNET MAC
KSZ9031MNX
TX _CLK
TX _CLK
TX _EN
TX _EN
TXD[3:0]
TXD[3:0]
TX_ER
3.11
TX_ER
RX_CLK
RX_CLK
RX _DV
RX _DV
RXD[3:0]
RXD[3:0]
RX _ER
RX _ER
CRS
CRS
COL
COL
MII Management (MIIM) Interface
The KSZ9031MNX supports the IEEE 802.3 MII management interface, also known as the Management Data Input/
Output (MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9031MNX.
An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details
about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows an external controller to communicate with one or more KSZ9031MNX devices. Each KSZ9031MNX device is assigned a unique
PHY address between 0h and 7h by the PHYAD[2:0] strapping pins.
• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indirect access to MMD addresses and registers. See the Register Map section.
PHY Address 0h is supported as the unique PHY address only; it is not supported as the broadcast PHY address, which
allows for a single write command to simultaneously program an identical PHY register for two or more PHY devices
(for example, using PHY Address 0h to set Register 0h to a value of 0x1940 to set Bit [11] to a value of one to enable
software power-down). Instead, separate write commands are used to program each PHY device.
Table 3-5 shows the MII management frame format for the KSZ9031MNX.
TABLE 3-5:
MII MANAGEMENT FRAME FORMAT FOR THE KSZ9031MNX
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Read
32 1’s
01
10
00AAA
RRRRR
Write
32 1’s
01
01
00AAA
RRRRR
2022 Microchip Technology Inc. and its subsidiaries
Data Bits [15:0]
Idle
Z0
DDDDDDDD_DDDDDDDD
Z
10
DDDDDDDD_DDDDDDDD
Z
DS00002096F-page 21
KSZ9031MNX
3.12
Interrupt (INT_N)
The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9031MNX PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits that enable and disable the conditions for asserting the INT_N signal. Bits [7:0] of Register 1Bh are the interrupt status bits that indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [14] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ9031MNX control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
3.13
LED Mode
The KSZ9031MNX provides two programmable LED output pins, LED2 and LED1, which are configurable to support
two LED modes. The LED mode is configured by the LED_MODE strap-in (Pin 55). It is latched at power-up/reset and
is defined as follows:
• Pull-Up: Single-LED Mode
• Pull-Down: Tri-Color Dual-LED Mode
Each LED output pin can directly drive an LED with a series resistor (typically 220Ω to 470Ω).
3.13.1
SINGLE-LED MODE
In single-LED mode, the LED2 pin indicates the link status while the LED1 pin indicates the activity status, as shown in
Table 3-6.
TABLE 3-6:
SINGLE-LED MODE - PIN DEFINITION
LED Pin
Pin State
LED Definition
LED2
H
OFF
Link Off
L
ON
Link On (any speed)
LED1
3.13.2
Link/Activity
H
OFF
No Activity
Toggle
Blinking
Activity (RX, TX)
TRI-COLOR DUAL-LED MODE
In tri-color dual-LED mode, the link and activity status are indicated by the LED2 pin for 1000BASE-T; by the LED1 pin
for 100BASE-TX; and by both LED2 and LED1 pins, working in conjunction, for 10BASE-T. This is summarized in
Table 3-7.
TABLE 3-7:
TRI-COLOR DUAL-LED MODE - PIN DEFINITION
LED Pin (State)
LED Pin (Definition)
LED1
LED2
H
H
OFF
OFF
Link Off
L
H
ON
OFF
1000 Link/No Activity
Toggle
H
Blinking
OFF
1000 Link/Activity (RX, TX)
H
L
OFF
ON
100 Link/No Activity
H
Toggle
OFF
Blinking
L
L
ON
ON
Toggle
Toggle
Blinking
Blinking
DS00002096F-page 22
LED1
Link/Activity
LED2
100 Link/Activity (RX, TX)
10 Link/No Activity
10 Link/Activity (RX, TX)
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
3.14
Loopback Mode
The KSZ9031MNX supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
3.14.1
LOCAL (DIGITAL) LOOPBACK
This loopback mode checks the GMII/MII transmit and receive data paths between KSZ9031MNX and external MAC,
and is supported for all three speeds (10/100/1000 Mbps) at full-duplex.
The loopback data path is shown in Figure 3-6.
1.
2.
3.
GMII/MII MAC transmits frames to KSZ9031MNX.
Frames are wrapped around inside KSZ9031MNX.
KSZ9031MNX transmits frames back to GMII/MII MAC.
FIGURE 3-6:
LOCAL (DIGITAL) LOOPBACK
KSZ9031MNX
AFE
PCS
(ANALOG)
(DIGITAL)
GMII /
MII
GMII / MII
MAC
The following programming steps and register settings are used for local loopback mode.
For 1000 Mbps loopback,
1.
Set Register 0h,
Bit [14] = 1
Bits [6, 13] = 10
Bit [12] = 0
Bit [8] = 1
2. Set Register 9h,
- Bit [12] = 1
- Bit [11] = 0
-
// Enable local loopback mode
// Select 1000 Mbps speed
// Disable auto-negotiation
// Select full-duplex mode
// Enable master-slave manual configuration
// Select slave configuration (required for loopback mode)
For 10/100 Mbps loopback,
1.
-
Set Register 0h,
Bit [14] = 1
Bits [6, 13] = 00 / 01
Bit [12] = 0
Bit [8] = 1
3.14.2
// Enable local loopback mode
// Select 10 Mbps/100 Mbps speed
// Disable auto-negotiation
// Select full-duplex mode
REMOTE (ANALOG) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between KSZ9031MNX and its link partner, and is supported for 1000BASE-T full-duplex mode only.
The loopback data path is shown in Figure 3-7.
1.
2.
3.
The Gigabit PHY link partner transmits frames to KSZ9031MNX.
Frames are wrapped around inside KSZ9031MNX.
KSZ9031MNX transmits frames back to the Gigabit PHY link partner.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 23
KSZ9031MNX
FIGURE 3-7:
REMOTE (ANALOG) LOOPBACK
KSZ9031MNX
RJ-45
AFE
(ANALOG)
PCS
(DIGITAL)
GMII /
MII
CAT-5
(UTP)
RJ-45
1000BASE-T
LINK PARTNER
The following programming steps and register settings are used for remote loopback mode.
1.
Set Register 0h,
- Bits [6, 13] = 10 // Select 1000 Mbps speed
- Bit [12] = 0
// Disable auto-negotiation
- Bit [8] = 1
// Select full-duplex mode
Or just auto-negotiate and link up at 1000BASE-T full-duplex mode with the link partner.
2.
Set Register 11h,
- Bit [8] = 1
// Enable remote loopback mode
3.15
LinkMD® Cable Diagnostic
The LinkMD function uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems,
such as open circuits, short circuits, and impedance mismatches.
LinkMD operates by sending a pulse of known amplitude and duration down the selected differential pair, then analyzing
the polarity and shape of the reflected signal to determine the type of fault: open circuit for a positive/non-inverted amplitude reflection and short circuit for a negative/inverted amplitude reflection. The time duration for the reflected signal to
return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and
presents it as a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing Register 12h, the LinkMD – Cable Diagnostic register, in conjunction with Register 1Ch,
the Auto MDI/MDI-X register. The latter register is needed to disable the Auto MDI/MDI-X function before running the
LinkMD test. Additionally, a software reset (Reg. 0h, Bit [15] = 1) should be performed before and after running the
LinkMD test. The reset helps to ensure the KSZ9031MNX is in the normal operating state before and after the test.
3.16
NAND Tree Support
The KSZ9031MNX provides parametric NAND tree support for fault detection between chip I/Os and board. NAND tree
mode is enabled at power-up/reset with the MODE[3:0] strap-in pins set to ‘0100’. Table 3-8 lists the NAND tree pin
order.
TABLE 3-8:
NAND TREE TEST PIN ORDER FOR KSZ9031MNX
Pin
Description
LED2
Input
LED1/PME_N1
Input
TXD0
Input
TXD1
Input
TXD2
Input
TXD3
Input
DS00002096F-page 24
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 3-8:
3.17
NAND TREE TEST PIN ORDER FOR KSZ9031MNX (CONTINUED)
Pin
Description
TX_ER
Input
GTX_CLK
Input
TX_EN
Input
RX_DV
Input
RX_ER
Input
RX_CLK
Input
CRS
Input
COL
Input
INT_/PME_N2
Input
MDC
Input
MDIO
Input
CLK125_NDO
Output
Power Management
The KSZ9031MNX incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections.
3.17.1
ENERGY-DETECT POWER-DOWN MODE
Energy-detect power-down (EDPD) mode is used to further reduce the transceiver power consumption when the cable
is unplugged. It is enabled by writing a one to MMD Address 1Ch, Register 23h, Bit [0], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link).
In EDPD Mode, the KSZ9031MNX shuts down all transceiver blocks, except for the transmitter and energy detect circuits. Power can be reduced further by extending the time interval between the transmissions of link pulses to check for
the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ9031MNX and its
link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the
cable is connected between them. By default, EDPD mode is disabled after power-up.
3.17.2
SOFTWARE POWER-DOWN MODE
This mode is used to power down the KSZ9031MNX device when it is not in use after power-up. Software power-down
(SPD) mode is enabled by writing a one to Register 0h, Bit [11]. In the SPD state, the KSZ9031MNX disables all internal
functions, except for the MII management interface. The KSZ9031MNX exits the SPD state after a zero is written to
Register 0h, Bit [11].
3.17.3
CHIP POWER-DOWN MODE
This mode provides the lowest power state for the KSZ9031MNX device when it is mounted on the board but not in use.
Chip power-down (CPD) mode is enabled after power-up/reset with the MODE[3:0] strap-in pins set to ‘0111’. The
KSZ9031MNX exits CPD mode after a hardware reset is applied to the RESET_N pin (Pin 56) with the MODE[3:0] strapin pins set to an operating mode other than CPD.
3.18
Wake-On-LAN
Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end
device, such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet
(commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ9031MNX can perform the
same WOL function if the MAC address of its associated MAC device is entered into the KSZ9031MNX PHY registers
for magic-packet detection. When the KSZ9031MNX detects the magic packet, it wakes up the host by driving its power
management event (PME) output pin low.
By default, the WOL function is disabled. It is enabled by setting the enabling bit and configuring the associated registers
for the selected PME wake-up detection method.
The KSZ9031MNX provides three methods to trigger a PME wake-up:
• Magic-packet detection
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 25
KSZ9031MNX
• Customized-packet detection
• Link status change detection
3.18.1
MAGIC-PACKET DETECTION
The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of
its associated MAC device (local MAC device).
When the magic packet is detected from its link partner, the KSZ9031MNX asserts its PME output pin low.
The following MMD Address 2h registers are provided for magic-packet detection:
• Magic-packet detection is enabled by writing a ‘1’ to MMD Address 2h, Register 10h, Bit [6]
• The MAC address (for the local MAC device) is written to and stored in MMD Address 2h, Registers 11h – 13h
The KSZ9031MNX does not generate the magic packet. The magic packet must be provided by the external system.
3.18.2
CUSTOMIZED-PACKET DETECTION
The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet
to use in the CRC calculation. After the KSZ9031MNX receives the packet from its link partner, the selected bytes for
the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that
was previously written to and stored in the KSZ9031MNX PHY registers. If there is a match, the KSZ9031MNX asserts
its PME output pin low.
Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used
to configure and enable each customized packet.
The following MMD registers are provided for customized-packet detection:
• Each of the four customized packets is enabled via MMD Address 2h, Register 10h,
- Bit [2] // For customized packets, type 0
- Bit [3] // For customized packets, type 1
- Bit [4] // For customized packets, type 2
- Bit [5] // For customized packets, type 3
• 32-bit expected CRCs are written to and stored in:
- MMD Address 2h, Registers 14h – 15h // For customized packets, type 0
- MMD Address 2h, Registers 16h – 17h // For customized packets, type 1
- MMD Address 2h, Registers 18h – 19h // For customized packets, type 2
- MMD Address 2h, Registers 1Ah – 1Bh // For customized packets, type 3
• Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
- MMD Address 2h, Registers 1Ch – 1Fh // For customized packets, type 0
- MMD Address 2h, Registers 20h – 23h // For customized packets, type 1
- MMD Address 2h, Registers 24h – 27h // For customized packets, type 2
- MMD Address 2h, Registers 28h – 2Bh // For customized packets, type 3
3.18.3
LINK STATUS CHANGE DETECTION
If link status change detection is enabled, the KSZ9031MNX asserts its PME output pin low whenever there is a link
status change using the following MMD Address 2h registers bits and their enabled (1) or disabled (0) settings:
• MMD Address 2h, Register 10h, Bit [0]
• MMD Address 2h, Register 10h, Bit [1]
// For link-up detection
// For link-down detection
The PME output signal is available on either LED1/PME_N1 (Pin 19) or INT_N/PME_N2 (Pin 53), and is selected and
enabled using MMD Address 2h, Register 2h, Bits [8] and [10], respectively. Additionally, MMD Address 2h, Register
10h, Bits [15:14] defines the output functions for Pins 19 and 53.
The PME output is active low and requires a 1 kΩ pull-up to the VDDIO supply. When asserted, the PME output is
cleared by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status
change).
DS00002096F-page 26
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
3.19
Typical Current/Power Consumption
Table 3-9, Table 3-10, Table 3-11, and Table 3-12 show the typical current consumption by the core (DVDDL, AVDDL,
AVDDL_PLL), transceiver (AVDDH) and digital I/O (DVDDH) supply pins, and the total typical power for the entire
KSZ9031MNX device for various nominal operating voltage combinations.
TABLE 3-9:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (3.3V), DIGITAL I/O (3.3V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
3.3V Transceiver
(AVDDH)
1000BASE-T Link-Up (no traffic)
211 mA
1000BASE-T Full-Duplex at
100% Utilization
221 mA
100BASE-TX Link-Up (no traffic)
60.6 mA
28.7 mA
13.3 mA
211 mW
100BASE-TX Full-Duplex at
100% Utilization
61.2 mA
28.7 mA
18.0 mA
228 mW
10BASE-T Link-Up (no traffic)
7.0 mA
17.0 mA
5.7 mA
83 mW
10BASE-T Full-Duplex at
100% Utilization
7.7 mA
29.3 mA
11.1 mA
143 mW
Software Power-Down Mode
(Reg. 0h.11 = 1)
0.9 mA
4.1 mA
7.1 mA
38 mW
Condition
TABLE 3-10:
3.3V Digital I/O
(DVDDH)
Total
Chip Power
66.6 mA
26.0 mA
560 mW
65.6 mA
53.8 mA
660 mW
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (3.3V), DIGITAL I/O (1.8V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
3.3V Transceiver
(AVDDH)
1.8V Digital I/O
(DVDDH)
Total
Chip Power
1000BASE-T Link-Up (no traffic)
211 mA
66.6 mA
14.2 mA
498 mW
1000BASE-T Full-Duplex at
100% Utilization
221 mA
65.6 mA
29.3 mA
534 mW
100BASE-TX Link-Up (no traffic)
60.6 mA
28.7 mA
7.3 mA
181 mW
100BASE-TX Full-Duplex at
100% Utilization
61.2 mA
28.7 mA
10.0 mA
186 mW
10BASE-T Link-Up (no traffic)
7.0 mA
17.0 mA
3.1 mA
70 mW
10BASE-T Full-Duplex at
100% Utilization
7.7 mA
29.3 mA
6.0 mA
117 mW
Software Power-Down Mode
(Reg. 0h.11 = 1)
0.9 mA
4.1 mA
3.7 mA
21 mW
Condition
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DS00002096F-page 27
KSZ9031MNX
TABLE 3-11:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (2.5V; Note 1), DIGITAL I/O (2.5V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
2.5V Transceiver
(AVDDH)
1000BASE-T Link-Up (no traffic)
211 mA
1000BASE-T Full-Duplex at
100% Utilization
221 mA
100BASE-TX Link-Up (no traffic)
2.5V Digital I/O
(DVDDH)
Total
Chip Power
58.6 mA
19.3 mA
448 mW
57.6 mA
40.5 mA
510 mW
60.6 mA
24.8 mA
10.0 mA
160 mW
100BASE-TX Full-Duplex at
100% Utilization
61.2 mA
24.8 mA
13.7 mA
170 mW
10BASE-T Link-Up (no traffic)
7.0 mA
12.5 mA
4.3 mA
50 mW
10BASE-T Full-Duplex at
100% Utilization
7.7 mA
25.8 mA
8.3 mA
94 mW
Software Power-Down Mode
(Reg. 0h.11 = 1)
0.9 mA
3.0 mA
5.3 mA
22 mW
Condition
Note 1:
2.5V AVDDH is recommended for commercial temperature range (0°C to +70°C) operation only.
TABLE 3-12:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (2.5V; Note 1), DIGITAL I/O (1.8V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
2.5V Transceiver
(AVDDH)
1000BASE-T Link-Up (no traffic)
211 mA
1000BASE-T Full-Duplex at
100% Utilization
221 mA
100BASE-TX Link-Up (no traffic)
60.6 mA
24.8 mA
7.3 mA
148 mW
100BASE-TX Full-Duplex at
100% Utilization
61.2 mA
24.8 mA
10.0 mA
153 mW
10BASE-T Link-Up (no traffic)
7.0 mA
12.5 mA
3.1 mA
45 mW
10BASE-T Full-Duplex at
100% Utilization
7.7 mA
25.8 mA
6.0 mA
85 mW
Software Power-Down Mode
(Reg. 0h.11 = 1)
0.9 mA
3.0 mA
3.7 mA
15 mW
Condition
Note 1:
1.8V Digital I/O
(DVDDH)
Total
Chip Power
58.6 mA
14.2 mA
425 mW
57.6 mA
29.3 mA
462 mW
2.5V AVDDH is recommended for commercial temperature range (0°C to +70°C) operation only.
DS00002096F-page 28
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
4.0
REGISTER DESCRIPTIONS
This chapter describes the various control and status registers (CSRs).
4.1
Register Map
The register space within the KSZ9031MNX consists of two distinct areas.
• Standard registers
// Direct register access
• MDIO Manageable device (MMD) registers // Indirect register access
The KSZ9031MNX supports the following standard registers.
TABLE 4-1:
STANDARD REGISTERS SUPPORTED BY KSZ9031MNX
Register Number (hex)
Description
IEEE-Defined Registers
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Auto-Negotiation Link Partner Next Page Ability
9h
1000BASE-T Control
Ah
Bh - Ch
1000BASE-T Status
Reserved
Dh
MMD Access – Control
Eh
MMD Access – Register/Data
Fh
Extended Status
Vendor-Specific Registers
10h
Reserved
11h
Remote Loopback
12h
LinkMD Cable Diagnostic
13h
Digital PMA/PCS Status
14h
Reserved
15h
RXER Counter
16h - 1Ah
1Bh
1Ch
1Dh - 1Eh
1Fh
Reserved
Interrupt Control/Status
Auto MDI/MDI-X
Reserved
PHY Control
The KSZ9031MNX supports the following MMD device addresses and their associated register addresses, which make
up the indirect MMD registers. These can be seen in Table 4-2.
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DS00002096F-page 29
KSZ9031MNX
TABLE 4-2:
MMD REGISTERS SUPPORTED BY KSZ9031MNX
Device Address (hex)
0h
1h
2h
DS00002096F-page 30
Register Address (hex)
3h
4h
5Ah
Description
AN FLP Burst Transmit – LO
AN FLP Burst Transmit – HI
1000BASE-T Link-Up Time Control
0h
Common Control
1h
Strap Status
2h
Operation Mode Strap Override
3h
Operation Mode Strap Status
4h
GMII Control Signal Pad Skew
8h
GMII Clock Pad Skew
10h
Wake-On-LAN – Control
11h
Wake-On-LAN – Magic Packet, MAC-DA-0
12h
Wake-On-LAN – Magic Packet, MAC-DA-1
13h
Wake-On-LAN – Magic Packet, MAC-DA-2
14h
Wake-On-LAN – Customized Packet, Type 0,
Expected CRC 0
15h
Wake-On-LAN – Customized Packet, Type 0,
Expected CRC 1
16h
Wake-On-LAN – Customized Packet, Type 1,
Expected CRC 0
17h
Wake-On-LAN – Customized Packet, Type 1,
Expected CRC 1
18h
Wake-On-LAN – Customized Packet, Type 2,
Expected CRC 0
19h
Wake-On-LAN – Customized Packet, Type 2,
Expected CRC 1
1Ah
Wake-On-LAN – Customized Packet, Type 3,
Expected CRC 0
1Bh
Wake-On-LAN – Customized Packet, Type 3,
Expected CRC 1
1Ch
Wake-On-LAN – Customized Packet, Type 0,
Mask 0
1Dh
Wake-On-LAN – Customized Packet, Type 0,
Mask 1
1Eh
Wake-On-LAN – Customized Packet, Type 0,
Mask 2
1Fh
Wake-On-LAN – Customized Packet, Type 0,
Mask 3
20h
Wake-On-LAN – Customized Packet, Type 1,
Mask 0
21h
Wake-On-LAN – Customized Packet, Type 1,
Mask 1
22h
Wake-On-LAN – Customized Packet, Type 1,
Mask 2
23h
Wake-On-LAN – Customized Packet, Type 1,
Mask 3
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KSZ9031MNX
TABLE 4-2:
MMD REGISTERS SUPPORTED BY KSZ9031MNX (CONTINUED)
Device Address (hex)
Register Address (hex)
24h
Wake-On-LAN – Customized Packet, Type 2,
Mask 0
25h
Wake-On-LAN – Customized Packet, Type 2,
Mask 1
26h
Wake-On-LAN – Customized Packet, Type 2,
Mask 2
27h
Wake-On-LAN – Customized Packet, Type 2,
Mask 3
28h
Wake-On-LAN – Customized Packet, Type 3,
Mask 0
29h
Wake-On-LAN – Customized Packet, Type 3,
Mask 1
2Ah
Wake-On-LAN – Customized Packet, Type 3,
Mask 2
2Bh
Wake-On-LAN – Customized Packet, Type 3,
Mask 3
2h
1Ch
4.2
Description
4h
Analog Control 4
23h
EDPD Control
Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the
IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.
TABLE 4-3:
Address
IEEE-DEFINED REGISTER DESCRIPTIONS
Name
Description
Mode
(Note 4-1)
Default
Register 0h – Basic Control
0.15
Reset
1 = Software PHY reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC
0
0.14
Loopback
1 = Loopback mode
0 = Normal operation
RW
0
0.13
[0.6, 0.13]
[1,1] = Reserved
[1,0] = 1000 Mbps
Speed Select
[0,1] = 100 Mbps
(LSB)
[0,0] = 10 Mbps
This bit is ignored if auto-negotiation is enabled
(Reg. 0.12 = 1).
RW
0
RW
1
0.12
Auto-Negotiation Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides settings in Reg. 0.13, 0.8 and 0.6.
If disabled, Auto MDI-X is also automatically disabled. Use Register 1Ch to set MDI/MDI-X.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 31
KSZ9031MNX
TABLE 4-3:
Address
IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Name
Mode
(Note 4-1)
Description
0.11
1 = Power-down mode
0 = Normal operation
When this bit is set to ‘1’, the link-down status
might not get updated in the PHY register. Software
should note link is down and should not rely on the
Power-Down
RW
PHY register link status.
After this bit is changed from ‘1’ to ‘0’, an internal
global reset is automatically generated. Wait a minimum of 1 ms before read/write access to the PHY
registers.
0.10
Isolate
0.9
1 = Restart auto-negotiation process
Restart Auto0 = Normal operation
Negotiation
This bit is self-cleared after a ‘1’ is written to it.
0.8
Duplex Mode
0.7
Collision Test
1 = Electrical isolation of PHY from GMII/MII
0 = Normal operation
Default
0
RW
0
RW/SC
0
1 = Full-duplex
0 = Half-duplex
RW
1
1 = Enable COL test
0 = Disable COL test
RW
0
0.6
[0.6, 0.13]
[1,1] = Reserved
[1,0] = 1000 Mbps
Speed Select
[0,1] = 100 Mbps
(MSB)
[0,0] = 10 Mbps
This bit is ignored if auto-negotiation is enabled
(Reg. 0.12 = 1).
RW
Set by MODE[3:0]
strapping pins.
See the Strapping
Options KSZ9031MNX
section for details.
0.5:0
Reserved
Reserved
RO
00_0000
1 = T4 capable
0 = Not T4 capable
RO
0
Register 1h - Basic Status
1.15
100BASE-T4
1.14
100BASE-TX 1 = Capable of 100 Mbps full-duplex
Full-Duplex
0 = Not capable of 100 Mbps full-duplex
RO
1
1.13
100BASE-TX 1 = Capable of 100 Mbps half-duplex
Half-Duplex 0 = Not capable of 100 Mbps half-duplex
RO
1
1.12
10BASE-T
Full-Duplex
1 = Capable of 10 Mbps full-duplex
0 = Not capable of 10 Mbps full-duplex
RO
1
1.11
10BASE-T
Half-Duplex
1 = Capable of 10 Mbps half-duplex
0 = Not capable of 10 Mbps half-duplex
RO
1
1.10:9
Reserved
Reserved
RO
00
1.8
Extended
Status
1 = Extended status info in Reg. 15h.
0 = No extended status info in Reg. 15h.
RO
1
1.7
Reserved
Reserved
RO
0
1.6
1 = Preamble suppression
No Preamble
0 = Normal preamble
RO
1
1.5
Auto-Negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
RO
0
1.4
Remote Fault
1 = Remote fault
0 = No remote fault
RO/LH
0
DS00002096F-page 32
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-3:
IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
1.3
Auto-Negotiation Ability
1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber
Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
RO/LH
0
1.0
Extended
Capability
1 = Supports extended capability registers
RO
1
Address
Default
Register 2h - PHY Identifier 1
2.15:0
Assigned to the 3rd through 18th bits of the organiPHY ID Numzationally unique identifier (OUI). KENDIN Commu- RO
ber
nication’s OUI is 0010A1h.
0022h
Register 3h - PHY Identifier 2
3.15:10
Assigned to the 19th through 24th bits of the orgaPHY ID Numnizationally unique identifier (OUI). KENDIN Comber
munication’s OUI is 0010A1h.
RO
0001_01
3.9:4
Model Number
Six-bit manufacturer’s model number
RO
10_0010
3.3:0
Revision
Number
Four-bit manufacturer’s revision number
RO
Indicates silicon
revision
Register 4h - Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
0 = No next page capability
RW
0
4.14
Reserved
Reserved
RO
0
4.13
Remote Fault
1 = Remote fault supported
0 = No remote fault
RW
0
4.12
Reserved
Reserved
RO
0
4.11:10
Pause
[4.11, 4.10]
[0,0] = No pause
[1,0] = Asymmetric pause (link partner)
[0,1] = Symmetric pause
[1,1] = Symmetric and asymmetric pause (local
device)
RW
00
4.9
100BASE-T4
1 = T4 capable
0 = No T4 capability
RO
0
4.8
100BASE-TX 1 = 100 Mbps full-duplex capable
Full-Duplex
0 = No 100 Mbps full-duplex capability
RW
1
4.7
100BASE-TX 1 = 100 Mbps half-duplex capable
Half-Duplex 0 = No 100 Mbps half-duplex capability
RW
1
4.6
10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability
RW
1
4.5
10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability
RW
1
4.4:0
Selector
Field
[00001] = IEEE 802.3
RW
0_0001
RO
0
Register 5h - Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 33
KSZ9031MNX
TABLE 4-3:
IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
5.14
Acknowledge
1 = Link code word received from partner
0 = Link code word not yet received
RO
0
5.13
Remote Fault
1 = Remote fault detected
0 = No remote fault
RO
0
5.12
Reserved
Reserved
RO
0
5.11:10
Pause
[5.11, 5.10]
[0,0] = No pause
[1,0] = Asymmetric Pause (link partner)
[0,1] = Symmetric pause
[1,1] = Symmetric and asymmetric pause (local
device)
RW
00
5.9
100BASE-T4
1 = T4 capable
0 = No T4 capability
RO
0
5.8
100BASE-TX 1 = 100 Mbps full-duplex capable
Full-Duplex
0 = No 100 Mbps full-duplex capability
RO
0
5.7
100BASE-TX 1 = 100 Mbps half-duplex capable
Half-Duplex 0 = No 100 Mbps half-duplex capability
RO
0
5.6
10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability
RO
0
5.5
10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability
RO
0
5.4:0
Selector
Field
[00001] = IEEE 802.3
RO
0_0000
Address
Default
Register 6h - Auto-Negotiation Expansion
6.15:5
Reserved
Reserved
RO
0000_0000_000
6.4
Parallel
Detection
Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection
RO/LH
0
6.3
Link Partner
Next Page
Able
1 = Link partner has next page capability
RO
0 = Link partner does not have next page capability
0
6.2
Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page capabil- RO
ity
1
6.1
Page
Received
1 = New page received
0 = New page not received
RO/LH
0
6.0
Link Partner
Auto-Negotiation Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
RO
0
Register 7h - Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next pages will follow
0 = Last page
RW
0
7.14
Reserved
Reserved
RO
0
7.13
Message
Page
1 = Message page
0 = Unformatted page
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
DS00002096F-page 34
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-3:
IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
7.11
Toggle
1 = Previous value of the transmitted link code
word equal to logic one
0 = Previous value of the transmitted link code
word equal to logic zero
RO
0
7.10:0
Message
Field
11-bit wide field to encode 2048 messages
RW
000_0000_0001
Address
Default
Register 8h - Link Partner Next Page Ability
8.15
Next Page
1 = Additional next pages will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message
Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link code word
equal to logic zero
0 = Previous value of transmitted link code word
equal to logic one
RO
0
8.10:0
Message
Field
—
RO
000_0000_0000
Register 9h – 1000BASE-T Control
9.15:13
Test Mode
Bits
Transmitter test mode operations
[9.15:13] Mode
[000] Normal operation
[001] Test mode 1 –Transmit waveform test
[010] Test mode 2 –Transmit jitter test in master
mode
[011] Test mode 3 –Transmit jitter test in slave
mode
[100] Test mode 4 –Transmitter distortion test
[101] Reserved, operations not identified
RW
[110] Reserved, operations not identified
[111] Reserved, operations not identified
To enable 1000BASE-T Test Mode:
1) Set Register 0h = 0x0140 to disable auto-negotiation and select 1000Mbps speed.
2) Set Register 9h, bits [15:13] = 001, 010, 011, or
100 to select one of the 1000BASE-T Test Modes.
After the above settings, the test waveform for the
selected test mode is transmitted onto each of the
4 differential pairs. No link partner is needed.
9.12
Master-Slave
Manual Configuration
Enable
1 = Enable master-slave manual configuration
value
0 = Disable master-slave manual configuration
value
RW
0
9.11
Master-Slave
Manual Configuration
Value
1 = Configure PHY as master during master-slave
negotiation
0 = Configure PHY as slave during master-slave
negotiation
This bit is ignored if master-slave manual configuration is disabled (Reg. 9.12 = 0).
RW
0
2022 Microchip Technology Inc. and its subsidiaries
000
DS00002096F-page 35
KSZ9031MNX
TABLE 4-3:
Address
IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Mode
(Note 4-1)
Name
Description
9.10
Port Type
1 = Indicate the preference to operate as multi-port
device (master)
0 = Indicate the preference to operate as singleRW
port device (slave)
This bit is valid only if master-slave manual configuration is disabled (Reg. 9.12 = 0).
9.9
1 = Advertise PHY is 1000BASE-T full-duplex
1000BASE-T capable
Full-Duplex
0 = Advertise PHY is not 1000BASE-T full-duplex
capable
RW
1
9.8
1 = Advertise PHY is 1000BASE-T half-duplex
1000BASE-T capable
Half-Duplex 0 = Advertise PHY is not 1000BASE-T half-duplex
capable
RW
1
9.7:0
Reserved
RO
Write as 0, ignore on read
Default
0
Register Ah – 1000BASE-T Status
A.15
Master-Slave
1 = Master-slave configuration fault detected
Configura0 = No master-slave configuration fault detected
tion Fault
RO/LH/SC 0
A.14
Master-Slave
Configura1 = Local PHY configuration resolved to master
tion Resolu- 0 = Local PHY configuration resolved to slave
tion
RO
0
A.13
Local
1 = Local receiver OK (loc_rcvr_status = 1)
Receiver Sta0 = Local receiver not OK (loc_rcvr_status = 0)
tus
RO
0
A.12
Remote
1 = Remote receiver OK (rem_rcvr_status = 1)
Receiver Sta0 = Remote receiver not OK (rem_rcvr_status = 0)
tus
RO
0
A.11
Link Partner
1000BASE-T
Full-Duplex
Capability
1 = Link partner is capable of 1000BASE-T fullduplex
0 = Link partner is not capable of 1000BASE-T
full-duplex
RO
0
A.10
Link Partner
1000BASE-T
Half-Duplex
Capability
1 = Link partner is capable of 1000BASE-T halfduplex
0 = Link Partner is not capable of 1000BASE-T
half-duplex
RO
0
A.9:8
Reserved
Reserved
RO
00
Idle Error
Count
Cumulative count of errors detected when receiver
is receiving idles and PMA_TXMODE.indicate =
SEND_N.
RO/SC
The counter is incremented every symbol period
that rxerror_status = ERROR.
A.7:0
0000_0000
Register Dh - MMD Access – Control
D.15:14
MMD –
Operation
Mode
DS00002096F-page 36
For the selected MMD device address (Bits [4:0] of
this register), these two bits select one of the following register or data operations and the usage
for MMD Access – Register/Data (Reg. Eh).
RW
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
00
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-3:
IEEE-DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
D.13:5
Reserved
Reserved
RW
00_0000_000
D.4:0
MMD –
Device
Address
These five bits set the MMD device address.
RW
0_0000
RW
0000_0000_0000_00
00
Address
Default
Register Eh - MMD Access – Register/Data
E.15:0
MMD –
Register/
Data
For the selected MMD device address (Reg. Dh,
Bits [4:0]),
When Reg. Dh, Bits [15:14] = 00, this register
contains the read/write register address for the
MMD device address.
Otherwise, this register contains the read/write
data value for the MMD device address and its
selected register address.
See also Reg. Dh, Bits [15:14], for descriptions of
post increment reads and writes of this register for
data operation.
Register Fh – Extended Status
F.15
1000BASE-X 1 = PHY can perform 1000BASE-X full-duplex
Full-Duplex
0 = PHY cannot perform 1000BASE-X full-duplex
RO
0
F.14
1000BASE-X 1 = PHY can perform 1000BASE-X half-duplex
Half-Duplex 0 = PHY cannot perform 1000BASE-X half-duplex
RO
0
F.13
1000BASE-T 1 = PHY can perform 1000BASE-T full-duplex
Full-Duplex
0 = PHY cannot perform 1000BASE-T full-duplex
RO
1
F.12
1000BASE-T 1 = PHY can perform 1000BASE-T half-duplex
Half-Duplex 0 = PHY cannot perform 1000BASE-T half-duplex
RO
1
F.11:0
Reserved
RO
—
Note 4-1
TABLE 4-4:
Address
Ignore when read
RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low.
VENDOR-SPECIFIC REGISTER DESCRIPTIONS
Name
Description
Mode
(Note 4-1)
Default
Register 11h – Remote Loopback
11.15:9
Reserved
Reserved
RW
0000_000
11.8
Remote
Loopback
1 = Enable remote loopback
0 = Disable remote loopback
RW
0
11.7:1
Reserved
Reserved
RW
1111_010
11.0
Reserved
Reserved
RO
0
RW/SC
0
RW
0
Register 12h – LinkMD – Cable Diagnostic
12.15
Cable Diagnostic Test
Enable
Write value:
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Disable cable diagnostic test.
Read value:
1 = Cable diagnostic test is in progress.
0 = Indicates cable diagnostic test (if enabled) has
completed and the status information is valid for
read.
12.14
Reserved
This bit should always be set to ‘0’.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 37
KSZ9031MNX
TABLE 4-4:
Address
VENDOR-SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Name
Mode
(Note 4-1)
Description
Default
12.13:12
Cable Diagnostic Test
Pair
These two bits select the differential pair for testing:
00 = Differential pair A (Pins 2, 3)
01 = Differential pair B (Pins 7, 8)
RW
10 = Differential pair C (Pins 10, 11)
11 = Differential pair D (Pins 14, 15)
00
12.11:10
Reserved
These two bits should always be set to ‘00’.
RW
00
12.9:8
These two bits represent the test result for the
selected differential pair in Bits [13:12] of this register.
Cable Diag00 = Normal cable condition (no fault detected)
RO
nostic Status
01 = Open cable fault detected
10 = Short cable fault detected
11 = Reserved
00
12.7:0
Cable Diagnostic Fault
Data
RO
0000_0000
RO/LH
0000_0000_0000_0
For the open or short cable fault detected in Bits
[9:8] of this register, this 8-bit value represents the
distance to the cable fault.
Register 13h – Digital PMA/PCS Status
13.15:3
Reserved
Reserved
13.2
1000BASE-T link status
1000BASE-T
1 = Link status is OK
Link Status
0 = Link status is not OK
RO
0
13.1
100BASE-TX link status
100BASE-TX
1 = Link status is OK
Link Status
0 = Link status is not OK
RO
0
13.0
Reserved
RO
0
RO/RC
0000_0000_0000_00
00
Reserved
Register 15h – RXER Counter
15.15:0
RXER
Counter
Receive error counter for symbol error frames
Register 1Bh – Interrupt Control/Status
1B.15
Jabber Interrupt Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
RW
0
1B.14
Receive
Error Interrupt Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt
RW
0
1B.13
Page
Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
RW
0
1B.12
Parallel
Detect Fault
Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt
RW
0
1B.11
Link Partner
Acknowledge Interrupt Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt
RW
0
1B.10
Link-Down
Interrupt
Enable
1 = Enable link-down interrupt
0 = Disable link-down interrupt
RW
0
DS00002096F-page 38
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-4:
Address
VENDOR-SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
1B.9
Remote Fault
1 = Enable remote fault interrupt
Interrupt
0 = Disable remote fault interrupt
Enable
RW
0
1B.8
Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt
RW
0
1B.7
Jabber Interrupt
1 = Jabber occurred
0 = Jabber did not occur
RO/RC
0
1B.6
Receive
Error Interrupt
1 = Receive error occurred
0 = Receive error did not occur
RO/RC
0
1B.5
Page
Receive
Interrupt
1 = Page receive occurred
0 = Page receive did not occur
RO/RC
0
1B.4
Parallel
Detect Fault
Interrupt
1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur
RO/RC
0
1B.3
Link Partner
Acknowledge Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur
RO/RC
0
1B.2
Link-Down
Interrupt
1 = Link-down occurred
0 = Link-down did not occur
RO/RC
0
1B.1
Remote Fault 1 = Remote fault occurred
Interrupt
0 = Remote fault did not occur
RO/RC
0
1B.0
Link-Up
Interrupt
RO/RC
0
1 = Link-up occurred
0 = Link-up did not occur
Register 1Ch – Auto MDI/MDI-X
1C.15:8
Reserved
Reserved
RW
0000_0000
1C.7
MDI Set
When Swap-Off (Bit [6] of this register) is asserted
(1),
1 = PHY is set to operate as MDI mode
0 = PHY is set to operate as MDI-X mode
This bit has no function when Swap-Off is deasserted (0).
RW
0
1C.6
Swap-Off
1 = Disable Auto MDI/MDI-X function
0 = Enable Auto MDI/MDI-X function
RW
0
1C.5:0
Reserved
Reserved
RW
00_0000
Register 1Fh – PHY Control
1F.15
Reserved
Reserved
RW
0
1F.14
Interrupt
Level
1 = Interrupt pin active high
0 = Interrupt pin active low
RW
0
1F.13:12
Reserved
Reserved
RW
00
1F.11:10
Reserved
Reserved
RO/LH/RC 00
1F.9
Enable
Jabber
1 = Enable jabber counter
0 = Disable jabber counter
RW
1
1F.8:7
Reserved
Reserved
RW
00
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 39
KSZ9031MNX
TABLE 4-4:
Address
VENDOR-SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Name
Mode
(Note 4-1)
Description
Default
1F.6
Speed
Status
1 = Indicate chip final speed status at 1000BASE-T RO
1000BASE-T
0
1F.5
Speed
Status
1 = Indicate chip final speed status at 100BASE-TX RO
100BASE-TX
0
1F.4
Speed
Status
10BASE-T
1 = Indicate chip final speed status at 10BASE-T
RO
0
1F.3
Duplex
Status
Indicate chip duplex status
1 = Full-duplex
0 = Half-duplex
RO
0
1F.2
1000BASE-T Indicate chip master/slave status
Master/Slave 1 = 1000BASE-T master mode
Status
0 = 1000BASE-T slave mode
RO
0
1F.1
Reserved
Reserved
RW
0
1F.0
Link Status
Check Fail
1 = Fail
0 = Not failing
RO
0
Note 4-1
RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low.
DS00002096F-page 40
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
4.3
MMD Registers
MMD registers provide indirect read/write access to up to 32 MMD device addresses with each device supporting up to
65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ9031MNX, however, uses only
a small fraction of the available registers. See the Register Map section for a list of supported MMD device addresses
and their associated register addresses.
The following two standard registers serve as the portal registers to access the indirect MMD registers.
• Standard register Dh – MMD Access – Control
• Standard register Eh – MMD Access – Register/Data
TABLE 4-5:
Address
MMD PORTAL REGISTERS
Name
Description
Mode
(Note 4-1)
Default
Register Dh - MMD Access – Control
D.15:14
MMD Operation
Mode
For the selected MMD device address (Bits [4:0] of
this register), these two bits select one of the following register or data operations and the usage
for MMD Access – Register/Data (Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW
00
D.13:5
Reserved
Reserved
RW
00_0000_000
D.4:0
MMD –
Device
Address
These five bits set the MMD device address
RW
0_0000
RW
0000_0000_
0000_0000
Register Eh - MMD Access – Register/Data
E.15:0
Note 4-1
MMD –
Register/
Data
For the selected MMD device address (Reg. Dh,
Bits [4:0]),
When Reg. Dh, Bits [15:14] = 00, this register contains the read/write register address for the MMD
device address.
Otherwise, this register contains the read/write
data value for the MMD device address and its
selected register address.
See also Register Dh, Bits [15:14] descriptions for
post increment reads and writes of this register for
data operation.
RW = Read/Write
Example: MMD Register Write
Write MMD - Device Address 2h, Register 10h = 0001h to enable link-up detection to trigger PME for WOL.
1.
2.
3.
4.
Write Register Dh with 0002h
Write Register Eh with 0010h
Write Register Dh with 4002h
Write Register Eh with 0001h
// Set up register address for MMD – Device Address 2h.
// Select Register 10h of MMD – Device Address 2h.
// Select register data for MMD – Device Address 2h, Register 10h.
// Write value 0001h to MMD – Device Address 2h, Register 10h.
Example: MMD Register Read
Read MMD - Device Address 2h, Register 11h – 13h for the magic packet’s MAC address.
1.
2.
3.
4.
5.
6.
Write Register Dh with 0002h // Set up register address for MMD – Device Address 2h.
Write Register Eh with 0011h // Select Register 11h of MMD – Device Address 2h.
Write Register Dh with 8002h // Select register data for MMD – Device Address 2h, Register 11h.
Read Register Eh
// Read data in MMD – Device Address 2h, Register 11h.
Read Register Eh
// Read data in MMD – Device Address 2h, Register 12h.
Read Register Eh
// Read data in MMD – Device Address 2h, Register 13h.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 41
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS
Name
Mode
(Note 4-1)
Description
Default
MMD Address 0h, Register 3h – AN FLP Burst Transmit – LO
0.3.15:0
AN FLP
Burst
Transmit –
LO
This register and the following register set the
Auto-Negotiation FLP burst transmit timing. The
same timing must be set for both registers.
0x4000 = Select 8 ms interval timing (default)
0x1A80 = Select 16 ms interval timing
All other values are reserved.
RW
0x4000
This register and the previous register set the AutoNegotiation FLP burst transmit timing. The same
AN FLP
timing must be set for both registers.
Burst
RW
0x0003 = Select 8 ms interval timing (default)
Transmit – HI
0x0006 = Select 16 ms interval timing
All other values are reserved.
0x0003
MMD Address 0h, Register 4h – AN FLP Burst Transmit – HI
0.4.15:0
MMD Address 1h, Register 5Ah – 1000BASE-T Link-Up Time Control
1.5A.15:9
Reserved
Reserved
RO
0000_000
1.5A.8:4
Reserved
Reserved
RW
1_0000
1.5A.3:1
When the link partner is another KSZ9031 device,
the 1000BASE-T link-up time can be long. These
three bits provide an optional setting to reduce the
1000BASE-T link-up time.
100 = Default power-up setting
011 = Optional setting to reduce link-up time when
1000BASE-T the link partner is a KSZ9031 device.
RW
Link-Up Time All other settings are reserved and should not be
used.
The optional setting is safe to use with any link
partner.
Note: Read/Write access to this register bit is available only when Reg. 0h is set to 0x2100 to disable
auto-negotiation and force 100BASE-TX mode.
100
1.5A.0
Reserved
RW
0
RW
0000_0000_000
Reserved
MMD Address 2h, Register 0h – Common Control
2.0.15:5
2.0.4
Reserved
Reserved
LED Mode
Override
Override strap-in for LED_MODE
1 = Single-LED mode
0 = Tri-color dual-LED mode
WO
This bit is write-only and always reads back a value
of ‘0’. The updated value is reflected in Bit [3] of
this register.
0
2.0.3
LED Mode
LED_MODE Status
1 = Single-LED mode
0 = Tri-color dual-LED mode
RO
Set by LED_MODE
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
Can be updated by
Bit [4] of this register
after reset.
2.0.2
Reserved
Reserved
RW
0
DS00002096F-page 42
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
2.0.1
CLK125_EN
Status
Override strap-in for CLK125_EN
1 = CLK125_EN strap-in is enabled
0 = CLK125_EN strap-in is disabled
RW
Set by CLK125_EN
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.0.0
Reserved
Reserved
RW
0
RO
0000_0000
MMD Address 2h, Register 1h – Strap Status
2.1.15:8
Reserved
Reserved
2.1.7
LED_MODE
Strap-In
Status
Strap to
1 = Single-LED mode
0 = Tri-color dual-LED mode
RO
Set by LED_MODE
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.1.6
Reserved
Reserved
RO
0
2.1.5
CLK125_EN
Strap-In
Status
Strap to
1 = CLK125_EN strap-in is enabled
0 = CLK125_EN strap-in is disabled
RO
Set by CLK125_EN
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.1.4:3
Reserved
Reserved
RO
00
RO
Set by PHYAD[2:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.1.2:0
PHYAD[2:0]
Strap-In
Value
Strap-in value for PHY address
Bits [4:3] of PHY address are always set to ‘00’.
MMD Address 2h, Register 2h – Operation Mode Strap Override
2.2.15:11
Reserved
Reserved
RW
0000_0
2.2.10
PME_N2
Output
Enable
For INT_N/PME_N2 (Pin 53),
1 = Enable PME output
0 = Disable PME output
This bit works in conjunction with MMD Address
2h, Reg. 10h, Bits [15:14] to define the output for
Pin 53.
RW
0
2.2.9
Reserved
Reserved
RW
0
PME_N1
Output
Enable
For LED1/PME_N1 (Pin 19),
1 = Enable PME output
0 = Disable PME output
This bit works in conjunction with MMD Address
2h, Reg. 10h, Bits [15:14] to define the output for
Pin 19.
RW
0
2.2.8
2.2.7
Chip PowerDown Override
1 = Override strap-in for chip power-down mode
RW
Set by MODE[3:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.2.6:5
Reserved
Reserved
RW
00
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 43
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS (CONTINUED)
Name
Mode
(Note 4-1)
Description
Default
2.2.4
NAND Tree
Override
1 = Override strap-in for NAND Tree mode
RW
Set by MODE[3:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.2.3:2
Reserved
Reserved
RW
00
2.2.1
GMII/MII
override
1 = Override strap-in for GMII/MII mode
RW
Set by MODE[3:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.2.0
Reserved
Reserved
RW
0
RO
0000_0000
MMD Address 2h, Register 3h – Operation Mode Strap Status
2.3.15:8
Reserved
Reserved
2.3.7
Chip PowerDown StrapIn Status
1 = Strap to chip power-down mode
RO
Set by MODE[3:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.3.6:5
Reserved
Reserved
RO
00
2.3.4
NAND Tree
Strap-In
Status
1 = Strap to NAND Tree mode
RO
Set by MODE[3:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.3.3:2
Reserved
Reserved
RO
00
2.3.1
GMII/MII
Strap-In
Status
1 = Strap to GMII/MII mode
RO
Set by MODE[3:0]
strapping pin.
See the Strapping
Options KSZ9031MNX
section for details.
2.3.0
Reserved
Reserved
RO
0
MMD Address 2h, Register 4h – GMII Control Signal Pad Skew
2.4.15:8
Reserved
Reserved
RW
0000_0000
2.4.7:4
RX_DV Pad
Skew
GMII RX_DV output pad skew control (0.06 ns/
step)
RW
0111
2.4.3:0
TX_EN Pad
Skew
GMII TX_EN input pad skew control (0.06 ns/step) RW
0111
MMD Address 2h, Register 8h – GMII Clock Pad Skew
2.8.15:10
Reserved
Reserved
RW
0000_00
2.8.9:5
GTX_CLK
Pad Skew
GMII GTX_CLK input pad skew control (0.06 ns/
step)
RW
01_111
2.8.4:0
RX_CLK
Pad Skew
GMII RX_CLK output pad skew control (0.06 ns/
step)
RW
0_1111
DS00002096F-page 44
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
MMD Address 2h, Register 10h – Wake-On-LAN – Control
2.10.15:14
PME Output
Select
These two bits work in conjunction with MMD
Address 2h, Reg. 2h, Bits [8] and [10] for PME_N1
and PME_N2 enable, to define the output for Pins
19 and 53, respectively.
LED1/PME_N1 (Pin 19)
00 = PME_N1 output only
01 = LED1 output only
RW
10 = LED1 and PME_N1 output
11 = Reserved
INT_N/PME_N2 (Pin 53)
00 = PME_N2 output only
01 = INT_N output only
10 = INT_N and PME_N2 output
11 = Reserved
2.10.13:7
Reserved
Reserved
RW
00_0000_0
2.10.6
Magic Packet
1 = Enable magic-packet detection
Detect
0 = Disable magic-packet detection
Enable
RW
0
2.10.5
CustomPacket Type
3 Detect
Enable
1 = Enable custom-packet, Type 3 detection
0 = Disable custom-packet, Type 3 detection
RW
0
2.10.4
CustomPacket Type
2 Detect
Enable
1 = Enable custom-packet, Type 2 detection
0 = Disable custom-packet, Type 2 detection
RW
0
2.10.3
CustomPacket Type
1 Detect
Enable
1 = Enable custom-packet, Type 1 detection
0 = Disable custom-packet, Type 1 detection
RW
0
2.10.2
CustomPacket Type
0 Detect
Enable
1 = Enable custom-packet, Type 0 detection
0 = Disable custom-packet, Type 0 detection
RW
0
2.10.1
Link-Down
Detect
Enable
1 = Enable link-down detection
0 = Disable link-down detection
RW
0
2.10.0
Link-Up
Detect
Enable
1 = Enable link-up detection
0 = Disable link-up detection
RW
0
00
MMD Address 2h, Register 11h – Wake-On-LAN – Magic Packet, MAC-DA-0
2.11.15:0
This register stores the lower two bytes of the destination MAC address for the magic packet.
Magic Packet Bit [15:8] = Byte 2 (MAC Address [15:8])
RW
MAC-DA-0
Bit [7:0] = Byte 1 (MAC Address [7:0])
The upper four bytes of the destination MAC
address are stored in the following two registers.
2022 Microchip Technology Inc. and its subsidiaries
0000_0000_0000_00
00
DS00002096F-page 45
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS (CONTINUED)
Name
Mode
(Note 4-1)
Description
Default
MMD Address 2h, Register 12h – Wake-On-LAN – Magic Packet, MAC-DA-1
2.12.15:0
This register stores the middle two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 4 (MAC Address [31:24])
Magic Packet
Bit [7:0] = Byte 3 (MAC Address [23:16])
RW
MAC-DA-1
The lower two bytes and upper two bytes of the
destination MAC address are stored in the previous
and following registers, respectively.
0000_0000_0000_00
00
MMD Address 2h, Register 13h – Wake-On-LAN – Magic Packet, MAC-DA-2
2.13.15:0
This register stores the upper two bytes of the destination MAC address for the magic packet.
Magic Packet Bit [15:8] = Byte 6 (MAC Address [47:40])
RW
MAC-DA-2
Bit [7:0] = Byte 5 (MAC Address [39:32])
The lower four bytes of the destination MAC
address are stored in the previous two registers.
0000_0000_0000_00
00
MMD Address 2h, Register 14h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
MMD Address 2h, Register 16h – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
MMD Address 2h, Register 18h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
MMD Address 2h, Register 1Ah – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
2.14.15:0
2.16.15:0
2.18.15:0
2.1A.15:0
Custom
Packet Type
X CRC 0
This register stores the upper two bytes for the
expected CRC.
Bit [15:8] = Byte 2 (CRC [15:8])
Bit [7:0] = Byte 1 (CRC [7:0])
The lower two bytes for the expected CRC are
stored in the following register.
RW
0000_0000_0000_00
00
MMD Address 2h, Register 15h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
MMD Address 2h, Register 17h – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
MMD Address 2h, Register 19h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
MMD Address 2h, Register 1Bh – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
2.15.15:0
2.17.15:0
2.19.15:0
2.1B.15:0
Custom
Packet Type
X CRC 1
This register stores the lower two bytes for the
expected CRC.
Bit [15:8] = Byte 4 (CRC [31:24])
Bit [7:0] = Byte 3 (CRC [23:16])
The upper two bytes for the expected CRC are
stored in the previous register.
RW
0000_0000_0000_00
00
MMD Address 2h, Register 1Ch – Wake-On-LAN – Customized Packet, Type 0, Mask 0
MMD Address 2h, Register 20h – Wake-On-LAN – Customized Packet, Type 1, Mask 0
MMD Address 2h, Register 24h – Wake-On-LAN – Customized Packet, Type 2, Mask 0
MMD Address 2h, Register 28h – Wake-On-LAN – Customized Packet, Type 3, Mask 0
2.1C.15:0
2.20.15:0
2.24.15:0
2.28.15:0
Custom
Packet Type
X Mask 0
DS00002096F-page 46
This register selects the bytes in the first 16 bytes
of the packet (bytes 1 through 16) that will be used
for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
RW
The register-bit to packet-byte mapping is as follows:
Bit [15]: Byte 16
……
Bit [2]: Byte 2
Bit [0]: Byte 1
0000_0000_0000_00
00
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
MMD Address 2h, Register 1Dh – Wake-On-LAN – Customized Packet, Type 0, Mask 1
MMD Address 2h, Register 21h – Wake-On-LAN – Customized Packet, Type 1, Mask 1
MMD Address 2h, Register 25h – Wake-On-LAN – Customized Packet, Type 2, Mask 1
MMD Address 2h, Register 29h – Wake-On-LAN – Customized Packet, Type 3, Mask 1
2.1D.15:0
2.21.15:0
2.25.15:0
2.29.15:0
Custom
Packet Type
X Mask 1
This register selects the bytes in the second 16
bytes of the packet (bytes 17 thru 32) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as follows:
Bit [15]: Byte 32
……
Bit [2]: Byte 18
Bit [0]: Byte 17
RW
0000_0000_0000_00
00
MMD Address 2h, Register 1Eh – Wake-On-LAN – Customized Packet, Type 0, Mask 2
MMD Address 2h, Register 22h – Wake-On-LAN – Customized Packet, Type 1, Mask 2
MMD Address 2h, Register 26h – Wake-On-LAN – Customized Packet, Type 2, Mask 2
MMD Address 2h, Register 2Ah – Wake-On-LAN – Customized Packet, Type 3, Mask 2
2.1E.15:0
2.22.15:0
2.26.15:0
2.2A.15:0
Custom
Packet Type
X Mask 2
This register selects the bytes in the third 16 bytes
of the packet (bytes 33 through 48) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as follows:
Bit [15]: Byte 48
……
Bit [2]: Byte 34
Bit [0]: Byte 33
RW
0000_0000_0000_00
00
MMD Address 2h, Register 1Fh – Wake-On-LAN – Customized Packet, Type 0, Mask 3
MMD Address 2h, Register 23h – Wake-On-LAN – Customized Packet, Type 1, Mask 3
MMD Address 2h, Register 27h – Wake-On-LAN – Customized Packet, Type 2, Mask 3
MMD Address 2h, Register 2Bh – Wake-On-LAN – Customized Packet, Type 3, Mask 3
2.1F.15:0
2.23.15:0
2.27.15:0
2.2B.15:0
Custom
Packet Type
X Mask 3
This register selects the bytes in the fourth 16 bytes
of the packet (bytes 49 through 64) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
RW
The register-bit to packet-byte mapping is as follows:
Bit [15]: Byte 64
……
Bit [2]: Byte 50
Bit [0]: Byte 49
0000_0000_0000_00
00
MMD Address 1Ch, Register 4h – Analog Control 4
1C.4.15:11
Reserved
Reserved
RW
0000_0
1C.4.10
10BASE-Te
Mode
1 = 10BASE-Te (1.75V TX amplitude)
0 = Standard 10BASE-T (2.5V TX amplitude)
RW
0
1C.4.9:0
Reserved
Reserved
RW
00_1111_1111
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 47
KSZ9031MNX
TABLE 4-6:
Address
MMD REGISTER DESCRIPTIONS (CONTINUED)
Name
Description
Mode
(Note 4-1)
Default
MMD Address 1Ch, Register 23h – EDPD Control
1C.23.15:1
Reserved
Reserved
RW
0000_0000_0000_00
0
1C.23.0
EDPD Mode
Enable
Energy-detect power-down mode
1 = Enable
0 = Disable
RW
0
Note 4-1
RW = Read/Write;
RO = Read Only;
WO = Write Only;
LH = Latch High.
DS00002096F-page 48
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
5.0
OPERATIONAL CHARACTERISTICS
5.1
Absolute Maximum Ratings*
Supply Voltage (VIN)
(DVDDL, AVDDL, AVDDL_PLL) ................................................................................................................ –0.5V to +1.8V
(AVDDH) ................................................................................................................................................... –0.5V to +5.0V
(DVDDH) ................................................................................................................................................... –0.5V to +5.0V
Input Voltage (all inputs) ........................................................................................................................... –0.5V to +5.0V
Output Voltage (all outputs) ...................................................................................................................... –0.5V to +5.0V
Lead Temperature (soldering, 10s) ....................................................................................................................... +260°C
Storage Temperature (TS)...................................................................................................................... –55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating
may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect
reliability.
5.2
Operating Ratings**
Supply Voltage
(DVDDL, AVDDL, AVDDL_PLL) ........................................................................................................ +1.140V to +1.380V
(AVDDH @ 3.3V) .............................................................................................................................. +3.135V to +3.465V
(AVDDH @ 2.5V; Commercial temp. only)........................................................................................ +2.375V to +2.625V
(DVDDH @ 3.3V).............................................................................................................................. +3.135V to +3.465V
(DVDDH @ 2.5V).............................................................................................................................. +2.375V to +2.625V
(DVDDH @ 1.8V).............................................................................................................................. +1.710V to +1.890V
Ambient Temperature
(TA Commercial: KSZ9031MNXC)............................................................................................................... 0°C to +70°C
(TA Industrial: KSZ9031MNXI) ................................................................................................................. –40°C to +85°C
Maximum Junction Temperature (TJ max.) ........................................................................................................... +125°C
Thermal Resistance (ΘJA)..............................................................................................................................+32.27°C/W
Thermal Resistance (ΘJC) ...............................................................................................................................+6.76°C/W
**The device is not guaranteed to function outside its operating ratings.
Note:
Do not drive input signals without power supplied to the device.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 49
KSZ9031MNX
6.0
ELECTRICAL CHARACTERISTICS
TA = 25°C. Specification is for packaged product only.
TABLE 6-1:
SUPPLY CURRENT - CORE/DIGITAL I/O
Parameters
1.2V Total of:
DVDDL (digital core) +
AVDDL (analog core) +
AVDDL_PLL (PLL)
1.8V for Digital I/O
(GMII/MII operating @
1.8V)
2.5V for Digital I/O
(GMII/MII operating @
2.5V)
DS00002096F-page 50
Symbol
ICORE
IDVDDH_1.8
IDVDDH_2.5
Min.
Typ.
Max.
Units
—
211
—
1000Base-T link-up (no traffic)
—
221
—
1000Base-T full-duplex @
100% utilization
—
60.6
—
100Base-TX link-up (no traffic)
—
61.2
—
100Base-TX full-duplex @
100% utilization
—
7.0
—
—
7.7
—
10Base-T full-duplex @
100% utilization
—
0.9
—
Software power-down mode
(Reg. 0.11 = 1)
—
0.8
—
Chip power-down mode
(strap-in pins MODE[3:0] = 0111)
—
14.2
—
1000Base-T link-up (no traffic)
—
29.3
—
1000Base-T full-duplex @
100% utilization
—
7.3
—
100Base-TX link-up (no traffic)
—
10.0
—
100Base-TX full-duplex @
100% utilization
—
3.1
—
—
6.0
—
10Base-T full-duplex @
100% utilization
—
3.7
—
Software power-down mode
(Reg. 0.11 = 1)
—
0.2
—
Chip power-down mode
(strap-in pins MODE[3:0] = 0111)
—
19.3
—
1000Base-T link-up (no traffic)
—
40.5
—
1000Base-T full-duplex @
100% utilization
—
10.0
—
100Base-TX link-up (no traffic)
—
13.7
—
100Base-TX full-duplex @
100% utilization
—
4.3
—
—
8.3
—
10Base-T full-duplex @
100% utilization
—
5.3
—
Software power-down mode
(Reg. 0.11 = 1)
—
0.9
—
Chip power-down mode
(strap-in pins MODE[3:0] = 0111)
mA
mA
mA
Note
10Base-T link-up (no traffic)
10Base-T link-up (no traffic)
10Base-T link-up (no traffic)
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 6-1:
SUPPLY CURRENT - CORE/DIGITAL I/O (CONTINUED)
Parameters
3.3V for Digital I/O
(GMII/MII operating @
3.3V)
TABLE 6-2:
IDVDDH_3.3
Min.
Typ.
Max.
Units
—
26.0
—
1000Base-T link-up (no traffic)
—
53.8
—
1000Base-T full-duplex @
100% utilization
—
13.3
—
100Base-TX link-up (no traffic)
—
18.0
—
100Base-TX full-duplex @
100% utilization
—
5.7
—
—
11.1
—
10Base-T full-duplex @
100% utilization
—
7.1
—
Software power-down mode
(Reg. 0.11 = 1)
—
2.1
—
Chip power-down mode
(strap-in pins MODE[3:0] = 0111)
mA
Note
10Base-T link-up (no traffic)
SUPPLY CURRENT - TRANSCEIVER (Note 6-1)
Parameters
2.5V for Transceiver
(Recommended for
commercial temperature
range operation only)
3.3V for Transceiver
Parameter
Note 6-1
Symbol
Symbol
IAVDDH_2.5
IAVDDH_3.3
Min.
Typ.
Max.
Units
—
58.6
—
1000Base-T link-up (no traffic)
—
57.6
—
1000Base-T full-duplex @
100% utilization
—
24.8
—
100Base-TX link-up (no traffic)
—
24.8
—
100Base-TX full-duplex @
100% utilization
—
12.5
—
—
25.8
—
10Base-T full-duplex @
100% utilization
—
3.0
—
Software power-down mode
(Reg. 0.11 = 1)
—
0.02
—
Chip power-down mode
(strap-in pins MODE[3:0] = 0111)
—
66.6
—
1000Base-T link-up (no traffic)
—
65.6
—
1000Base-T full-duplex @
100% utilization
—
28.7
—
100Base-TX link-up (no traffic)
—
28.7
—
100Base-TX full-duplex @
100% utilization
—
17.0
—
—
29.3
—
10Base-T full-duplex @
100% utilization
—
4.1
—
Software power-down mode
(Reg. 0.11 = 1)
—
0.02
—
Chip power-down mode
(strap-in pins MODE[3:0] = 0111)
mA
mA
Note
10Base-T link-up (no traffic)
10Base-T link-up (no traffic)
Equivalent to current draw through external transformer center taps for PHY transceivers with currentmode transmit drivers.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 51
KSZ9031MNX
TABLE 6-3:
CMOS INPUTS
Parameters
Input High Voltage
Input Low Voltage
Input High
Leakage Current
Input Low Leakage Current
TABLE 6-4:
VIH
VIL
IIHL
Min.
Typ.
Max.
2.0
—
—
1.5
—
—
1.1
—
—
—
—
1.3
—
—
1.0
—
—
Units
Note
DVDDH (digital I/O) = 3.3V
V
DVDDH (digital I/O) = 2.5V
DVDDH (digital I/O) = 1.8V
DVDDH (digital I/O) = 3.3V
V
DVDDH (digital I/O) = 2.5V
0.7
DVDDH (digital I/O) = 1.8V
µA
DVDDH = 3.3V and VIH = 3.3V
All digital input pins
–2.0
—
2.0
–2.0
—
2.0
IILL
µA
DVDDH = 3.3V and VIL = 0.0V
All digital input pins, except MDC,
MDIO, RESET_N.
DVDDH = 3.3V and VIL = 0.0V
MDC, MDIO, RESET_N pins with
internal pull-ups
–120
—
–40
Min.
Typ.
Max.
2.7
—
—
DVDDH (digital I/O) = 3.3V,
IOH (min) = 10mA
All digital output pins
2.0
—
—
DVDDH (digital I/O) = 2.5V,
IOH (min) = 10mA
All digital output pins
CMOS OUTPUTS
Parameter
Output High Voltage
Output Low Voltage
Output Tri-State Leakage
TABLE 6-5:
Symbol
Symbol
VOH
VOL
|Ioz|
Units
V
Note
1.5
—
—
DVDDH (digital I/O) = 1.8V,
IOH (min) = 13mA
All digital output pins, except LED1,
LED2
—
—
0.3
DVDDH (digital I/O) = 3.3V,
IOL (min) = 10mA
All digital output pins
—
—
0.3
DVDDH (digital I/O) = 2.5V,
IOL (min) = 10mA
All digital output pins
V
DVDDH (digital I/O) = 1.8V,
IOL (min) = 13mA
All digital output pins, except LED1,
LED2
—
—
0.3
—
—
10
µA
—
LED OUTPUTS
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
Output Drive Current
ILED
10
—
—
mA
DVDDH (digital I/O) = 3.3V or 2.5V,
and VOL at 0.3V
Each LED pin (LED1, LED2)
DS00002096F-page 52
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
TABLE 6-6:
PULL-UP PINS
Parameters
Internal Pull-Up Resistance
(MDC, MDIO,
RESET_N pins)
TABLE 6-7:
Symbol
pu
Min.
Typ.
Max.
13
22
31
16
28
39
26
44
62
Units
Note
DVDDH (digital I/O) = 3.3V
kΩ
DVDDH (digital I/O) = 2.5V
DVDDH (digital I/O) = 1.8V
100BASE-TX TRANSMIT (Note 6-1)
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
Peak Differential Output
Voltage
VO
0.95
—
1.05
V
100Ω termination across differential
output
Output Voltage Imbalance
VIMB
—
—
2
%
100Ω termination across differential
output
Rise/Fall Time
t r, t f
3
—
5
ns
—
Rise/Fall Time Imbalance
—
0
—
0.5
ns
—
Duty Cycle Distortion
—
—
—
±0.25
ns
—
Overshoot
—
—
—
5
%
—
Output Jitter
—
—
0.7
—
Note 6-1
Measured differentially after 1:1 transformer.
ns
Peak-to-peak
TABLE 6-8:
10BASE-T TRANSMIT (Note 6-1)
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
V
100Ω termination across differential
output
Peak Differential Output
Voltage
VP
2.2
—
2.8
Jitter Added
—
—
—
3.5
ns
Peak-to-peak
Harmonic Rejection
—
—
–31
—
Note 6-1
Measured differentially after 1:1 transformer.
dB
Transmit all-one signal sequence
TABLE 6-9:
10BASE-T RECEIVE
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
Squelch Threshold
VSQ
300
400
—
mV
5 MHz square wave
TABLE 6-10:
TRANSMITTER - DRIVE SETTING
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
Reference Voltage of ISET
VSET
—
1.2
—
V
R(ISET) = 12.1 kΩ
Units
Note
TABLE 6-11:
LDO CONTROLLER - DRIVE RANGE
Parameters
Output drive range for
LDO_O (Pin 58) to gate
input of P-channel
MOSFET
Symbol
Min.
Typ.
Max.
0.85
—
2.8
0.85
—
2.0
AVDDH = 3.3V for MOSFET source
voltage
V
VLDO_O
2022 Microchip Technology Inc. and its subsidiaries
AVDDH = 2.5V for MOSFET source
voltage (recommended for commercial temperature range operation only)
DS00002096F-page 53
KSZ9031MNX
7.0
TIMING DIAGRAMS
FIGURE 7-1:
GMII TRANSMIT TIMING - DATA INPUT TO PHY
tCYC
tLO
GTX_CLK
tHI
tR
tSU
tF
tHD
TX_EN
TXD[7:0]
TX_ER
TABLE 7-1:
Timing
Parameter
GMII TRANSMIT TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
1000BASE-T
tCYC
GTX_CLK period
7.5
8.0
8.5
tSU
TX_EN, TXD[7:0], TX_ER setup time to rising edge of
GTX_CLK
2.0
—
—
tHD
TX_EN, TXD[7:0], TX_ER hold time from rising edge of
GTX_CLK
0
—
—
tHI
GTX_CLK high pulse width
2.5
—
—
tLO
GTX_CLK low pulse width
2.5
—
—
tR
GTX_CLK rise time
—
—
1.0
tF
GTX_CLK fall time
—
—
1.0
DS00002096F-page 54
ns
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
FIGURE 7-2:
GMII RECEIVE TIMING - DATA INPUT TO MAC
tCYC
tLO
RX_CLK
tHI
tR
tSU
tF
tHD
RX_DV
RXD[7:0]
RX_ER
TABLE 7-2:
Timing
Parameter
GMII RECEIVE TIMING PARAMETERS
Description
Min.
Typ.
Max.
tCYC
RX_CLK period
7.5
8.0
8.5
tSU
RX_EN, RXD[7:0], RX_ER setup time to rising edge of
RX_CLK
2.5
—
—
tHD
RX_EN, RXD[7:0], RX_ER hold time from rising edge of
RX_CLK
0.5
—
—
tHI
RX_CLK high pulse width
2.5
—
—
tLO
RX_CLK low pulse width
2.5
—
—
tR
RX_CLK rise time
—
—
1.0
tF
RX_CLK fall time
—
—
1.0
Units
1000BASE-T
2022 Microchip Technology Inc. and its subsidiaries
ns
DS00002096F-page 55
KSZ9031MNX
FIGURE 7-3:
MII TRANSMIT TIMING - DATA INPUT TO PHY
tCYC
tLO
TX_CLK
tHI
tSU
tHD
TX_EN
TXD[3:0]
TX_ER
TABLE 7-3:
Timing
Parameter
MII TRANSMIT TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
10BASE-T
tCYC
TX_CLK period
—
400
—
tSU
TX_EN, TXD[3:0], TX_ER setup time to rising edge of
TX_CLK
15
—
—
tHD
TX_EN, TXD[3:0], TX_ER hold time from rising edge of
TX_CLK
0
—
—
tHI
TX_CLK high pulse width
140
—
260
tLO
TX_CLK low pulse width
140
—
260
ns
100BASE-TX
tCYC
TX_CLK period
—
40
—
tSU
TX_EN, TXD[3:0], TX_ER setup time to rising edge of
TX_CLK
15
—
—
tHD
TX_EN, TXD[3:0], TX_ER hold time from rising edge of
TX_CLK
0
—
—
tHI
TX_CLK high pulse width
14
—
26
tLO
TX_CLK low pulse width
14
—
26
DS00002096F-page 56
ns
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
FIGURE 7-4:
MII RECEIVE TIMING - DATA INPUT TO MAC
tCYC
RX _CLK
RX _DV
RXD[3:0]
RX _ER
TABLE 7-4:
Timing
Parameter
tHI
tSU
tLO
tHD
MII RECEIVE TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
10BASE-T
tCYC
RX_CLK period
—
400
—
tSU
RX_DV, RXD[3:0], RX_ER setup time to rising edge of
RX_CLK
10
—
—
tHD
RX_DV, RXD[3:0], RX_ER hold time from rising edge of
RX_CLK
10
—
—
tHI
RX_CLK high pulse width
140
—
260
tLO
RX_CLK low pulse width
140
—
260
ns
100BASE-TX
tCYC
RX_CLK period
—
40
—
tSU
RX_DV, RXD[3:0], RX_ER setup time to rising edge of
RX_CLK
10
—
—
tHD
RX_DV, RXD[3:0], RX_ER hold time from rising edge of
RX_CLK
10
—
—
tHI
RX_CLK high pulse width
14
—
26
tLO
RX_CLK low pulse width
14
—
26
2022 Microchip Technology Inc. and its subsidiaries
ns
DS00002096F-page 57
KSZ9031MNX
FIGURE 7-5:
TABLE 7-5:
Timing
Parameter
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS
Min.
Typ.
Max.
FLP burst to FLP burst
8
16
24
FLP burst width
—
2
—
tPW
Clock/Data pulse width
—
100
—
tCTD
Clock pulse to data pulse
55.5
64
69.5
tCTC
Clock pulse to clock pulse
111
128
139
Number of clock/data pulses per FLP burst
17
—
33
tBTB
tFLPW
—
Description
Units
ms
ns
µs
—
The KSZ9031MNX Fast Link Pulse (FLP) burst-to-burst transmit timing for Auto-Negotiation defaults to 8 ms. IEEE
802.3 Standard specifies this timing to be 16 ms ±8 ms. Some PHY link partners need to receive the FLP with 16 ms
centered timing; otherwise, there can be intermittent link failures and long link-up times.
After KSZ9031MNX power-up/reset, program the following register sequence to set the FLP timing to 16 ms:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Write Register Dh = 0x0000
Write Register Eh = 0x0004
Write Register Dh = 0x4000
Write Register Eh = 0x0006
Write Register Dh = 0x0000
Write Register Eh = 0x0003
Write Register Dh = 0x4000
Write Register Eh = 0x1A80
Write Register 0h, Bit [9] = 1
// Set up register address for MMD – Device Address 0h
// Select Register 4h of MMD – Device Address 0h
// Select register data for MMD – Device Address 0h, Register 4h
// Write value 0x0006 to MMD – Device Address 0h, Register 4h
// Set up register address for MMD – Device Address 0h
// Select Register 3h of MMD – Device Address 0h
// Select register data for MMD – Device Address 0h, Register 3h
// Write value 0x1A80 to MMD – Device Address 0h, Register 3h
// Restart Auto-Negotiation
The above setting for 16 ms FLP transmit timing is compatible with all PHY link partners.
DS00002096F-page 58
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
FIGURE 7-6:
TABLE 7-6:
MDC/MDIO TIMING
MDC/MDIO TIMING PARAMETERS
Timing
Parameter
Description
Min.
Typ.
tP
Max.
MDC period
120
400
—
tMD1
MDIO (PHY input) setup to rising edge of MDC
10
—
—
tMD2
MDIO (PHY input) hold from rising edge of MDC
10
—
—
tMD3
MDIO (PHY output) delay from rising edge of MDC
0
—
—
Units
ns
The typical MDC clock frequency is 2.5 MHz (400 ns clock period).
The KSZ9031MNX can operate with MDC clock frequencies generated from bit banging with GPIO pin in the 10s/100s
of Hertz and have been tested up to a MDC clock frequency of 8.33 MHz (120 ns clock period). Test condition for
8.33 MHz is for one KSZ9031MNX PHY on the MDIO line with a 1.0 kΩ pull-up to the DVDDH supply rail.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 59
KSZ9031MNX
FIGURE 7-7:
POWER-UP/POWER-DOWN/RESET TIMING
NOTE
1
TRANSCEIVER (AVDDH), DIGITAL I/Os (DVDDH)
NOTE
3
CORE (DVDDL, AVDDL, AVDDL_PLL)
NOTE
2
SUPPLY
VOLTAGES
tVR
tPC
tSR
RESET_N
tCS
tCH
STRAP-IN
VALUE
tRC
STRAP-IN /
OUTPUT PIN
Note 1: The recommended power-up sequence is to have the transceiver (AVDDH) and digital I/O (DVDDH) voltages
power up before the 1.2V core (DVDDL, AVDDL, AVDDL_PLL) voltage. If the 1.2V core must power up first, the maximum lead time for the 1.2V core voltage with respect to the transceiver and digital I/O voltages should be 200 µs.
There is no power sequence requirement between transceiver (AVDDH) and digital I/O (DVDDH) power rails.
The power-up waveforms should be monotonic for all supply voltages to the KSZ9031MNX.
Note 2: After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO)
interface.
Note 3: The recommended power-down sequence is to have the 1.2V core voltage power-down before powering down
the transceiver and digital I/O voltages.
Before the next power-up cycle, all supply voltages to the KSZ9031MNX should reach less than 0.4V and there should
be a minimum wait time of 150 ms from power-off to power-on.
TABLE 7-7:
Timing
Parameter
POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
tVR
Supply voltages rise time (must be monotonic)
200
—
—
µs
tSR
Stable supply voltages to de-assertion of reset
10
—
—
ms
tCS
Strap-in pin configuration setup time
5
—
—
tCH
Strap-in pin configuration hold time
5
—
—
tRC
De-assertion of reset to strap-in pin output
6
—
—
tPC
Supply voltages cycle off-to-on time
150
—
—
DS00002096F-page 60
ns
ms
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
8.0
RESET CIRCUIT
The following are some reset circuit suggestions.
Figure 8-1 illustrates the reset circuit for powering up the KSZ9031MNX if reset is triggered by the power supply.
FIGURE 8-1:
RESET CIRCUIT IF TRIGGERED BY THE POWER SUPPLY
DVDDH
D1: 1N4148
D1
KSZ9031MNX
R 10K
RESET_N
C 10μF
Figure 8-2 illustrates the reset circuit for applications where reset is driven by another device (for example, the CPU or
an FPGA). At power-on-reset, R, C, and D1 provide the monotonic rise time to reset the KSZ9031MNX device. The
RST_OUT_N from the CPU/FPGA provides the warm reset after power-up.
The KSZ9031MNX and CPU/FPGA references the same digital I/O voltage (DVDDH).
FIGURE 8-2:
RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT
DVDDH
KSZ9031MNX
R 10K
D1
CPU/FPGA
RESET_N
RST_OUT_N
C 10μF
D2
D1, D2: 1N4148
Figure 8-3 illustrates the reset circuit with an MIC826 voltage supervisor driving the KSZ9031MNX reset input.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 61
KSZ9031MNX
FIGURE 8-3:
RESET CIRCUIT WITH MIC826 VOLTAGE SUPERVISOR
DVDDH
KSZ9031MNX
RESET_N
DVDDH
MIC826
RESET#
Part
Number
Reset
Threshold
MIC826TYMT / 3.075V
MIC826ZYMT / 2.315V
MIC826WYMT / 1.665V
DVDDH = 3.3V, 2.5V, or 1.8V
DS00002096F-page 62
2022 Microchip Technology Inc. and its subsidiaries
KSZ9031MNX
9.0
REFERENCE CIRCUITS — LED STRAP-IN PINS
The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in
Figure 9-1 for 3.3V and 2.5V DVDDH.
FIGURE 9-1:
REFERENCE CIRCUITS FOR LED STRAPPING PINS
DVDDH = 3.3V, 2.5V
PULL-UP
10kΩ
220Ω
KSZ9031MNX
LED PIN
DVDDH = 3.3V, 2.5V
PULL-DOWN
220Ω
KSZ9031MNX
LED PIN
1k Ω
For 1.8V DVDDH, LED indication support requires voltage level shifters between LED[2:1] pins and LED indicator
diodes to ensure the multiplexed PHYAD[1:0] strapping pins are latched in high/low correctly. If LED indicator diodes
are not implemented, the PHYAD[1:0] strapping pins just need 10 kΩ pull-up to 1.8V DVDDH for a value of 1, and 1.0 kΩ
pull-down to ground for a value of 0.
2022 Microchip Technology Inc. and its subsidiaries
DS00002096F-page 63
KSZ9031MNX
10.0
REFERENCE CLOCK - CONNECTION AND SELECTION
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9031MNX.
The reference clock is 25 MHz for all operating modes of the KSZ9031MNX.
The KSZ9031MNX uses the AVDDH supply, analog 3.3V (or analog 2.5V option for commercial temperature only), for
the crystal/ clock pins (XI, XO). If the 25 MHz reference clock is provided externally, the XI input pin should have a minimum clock voltage peak-to-peak (VPP) swing of 2.5V reference to ground. If VPP is less than 2.5V, series capacitive
coupling is recommended. With capacitive coupling, the VPP swing can be down to 1.5V. Maximum VPP swing is 3.3V
+5%.
Figure 10-1 and Table 10-1 show the reference clock connection to XI (Pin 61) and XO (Pin 60) of the KSZ9031MNX,
and the reference clock selection criteria.
FIGURE 10-1:
25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION
22pF
XI
22pF
XO
XI
25 MHz OSC
±50PPM
NC
XO
25 MHz XTAL
±50PPM
TABLE 10-1:
11.0
25 MHZ CRYSTAL/REFERENCE CLOCK SELECTION CRITERIA
Characteristics
Value
Frequency
25 MHz
Frequency Tolerance (max.)
±50 ppm
Crystal Series Resistance (typ.)
40Ω
Total Period Jitter (peak-to-peak)
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