KSZ9477STXI

KSZ9477S 7-Port Gigabit Ethernet Switch with Ring Redundancy, SGMII and RGMII/MII/RMII Interfaces Highlights • One port with 10/100/1000 Ethernet MAC and SGMII interface • One port with 10/100/1000 Ethernet MAC and configurable RGMII/MII/RMII interface • EtherSynch® with full support for IEEE 1588v2 Precision Time Protocol (PTP) • IEEE 802.1AS/Qav Audio Video Bridging (AVB) • IEEE 802.1X access control support • Five ports with integrated 10/100/1000BASE-T PHY transceivers w/ optional Quiet-WIRE® EMC filtering • Non-blocking wire-speed Ethernet switching fabric • Full-featured forwarding and filtering control, including Access Control List (ACL) filtering • Full VLAN and QoS support • EtherGreen™ power management features, including low power standby • Flexible management interface options: SPI, I2C, MIIM, and in-band management via any port • Industrial temperature range support • 128-pin TQFP-EP (14 x 14mm) RoHS compliant pkg Target Applications • • • • • • Industrial Ethernet (Profinet, MODBUS, Ethernet/IP) Real-time Ethernet networks IEC 61850 networks w/ power substation automation Industrial control/automation switches Networked measurement and control systems Test and measurement equipment Features • Switch Management Capabilities - 10/100/1000Mbps Ethernet switch basic functions: frame buffer management, address look-up table, queue management, MIB counters - Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 4096 entry forwarding table with 256kByte frame buffer - Jumbo packet support up to 9000 bytes - Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port - Rapid spanning tree protocol (RSTP) support for topology management and ring/linear recovery - Multiple spanning tree protocol (MSTP) support • One External MAC Port with SGMII • One External MAC Port with RGMII/MII/RMII • Five Integrated PHY Ports - 1000BASE-T/100BASE-TX/10BASE-Te IEEE 802.3 Fast Link-up option significantly reduces link-up time Auto-negotiation and Auto-MDI/MDI-X support On-chip termination resistors and internal biasing for differential pairs to reduce power - LinkMD® cable diagnostic capabilities • Advanced Switch Capabilities - IEEE 802.1Q VLAN support for 128 active VLAN groups and the full range of 4096 VLAN IDs - IEEE 802.1p/Q tag insertion/removal on per port basis - VLAN ID on per port or VLAN basis - IEEE 802.3x full-duplex flow control and half-duplex back pressure collision control - IEEE 802.1X access control (Port and MAC address) - IGMP v1/v2/v3 snooping for multicast packet filtering - IPv6 multicast listener discovery (MLD) snooping - IPv4/IPv6 QoS support, QoS/CoS packet prioritization - 802.1p QoS packet classification with 4 priority queues - Programmable rate limiting at ingress/egress ports • Ring Redundancy - DLR (EtherNet/IP) support - HSR (IEC 62439-3) support • IEEE 1588v2 PTP and Clock Synchronization - Transparent Clock (TC) with auto correction update Master and slave Ordinary Clock (OC) support End-to-end (E2E) or peer-to-peer (P2P) PTP multicast and unicast message support PTP message transport over IPv4/v6 and IEEE 802.3 IEEE 1588v2 PTP packet filtering Synchronous Ethernet support via recovered clock • Audio Video Bridging (AVB) - Compliant with IEEE 802.1BA/AS/Qat/Qav standards Priority queuing, Low latency cut-through mode gPTP time synchronization, credit-based traffic shaper Time aware traffic scheduler per port • Comprehensive Configuration Registers Access - High-speed 4-wire SPI (up to 50MHz), I2C interfaces provide access to all internal registers - MII Management (MIIM, MDC/MDIO 2-wire) Interface provides access to all PHY registers - In-band management via any of the data ports - I/O pin strapping facility to set register bits at reset • Power Management - Energy detect power-down mode on cable disconnect Dynamic clock tree control Unused ports can be individually powered down Full-chip software power-down Wake-on-LAN (WoL) standby power mode - RGMII v2.0, RMII v1.2 with 50MHz reference clock input/output option, MII in PHY/MAC mode  2017-2019 Microchip Technology Inc. DS00002392C-page 1 KSZ9477S TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). 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DS00002392C-page 2  2017-2019 Microchip Technology Inc. KSZ9477S Table of Contents 1.0 Preface ............................................................................................................................................................................................ 4 2.0 Introduction ..................................................................................................................................................................................... 8 3.0 Pin Descriptions and Configuration ............................................................................................................................................... 10 4.0 Functional Description .................................................................................................................................................................. 20 5.0 Device Registers ........................................................................................................................................................................... 72 6.0 Operational Characteristics ......................................................................................................................................................... 235 7.0 Design Guidelines ....................................................................................................................................................................... 252 8.0 Package Information ................................................................................................................................................................... 255 Appendix A: Data Sheet Revision History ......................................................................................................................................... 259 The Microchip Web Site .................................................................................................................................................................... 263 Customer Change Notification Service ............................................................................................................................................. 263 Customer Support ............................................................................................................................................................................. 263 Product Identification System ........................................................................................................................................................... 264  2017-2019 Microchip Technology Inc. DS00002392C-page 3 KSZ9477S 1.0 PREFACE 1.1 Glossary of Terms TABLE 1-1: GENERAL TERMS Term Description 10BASE-Te 10 Mbps Ethernet, 2.5V signaling, IEEE 802.3 compliant 100BASE-TX 100 Mbps Fast Ethernet, IEEE 802.3u compliant 1000BASE-T 1000 Mbps Gigabit Ethernet, IEEE 802.3ab compliant ADC Analog-to-Digital Converter AN Auto-Negotiation AVB Audio Video Bridging (IEEE 802.1BA, 802.1AS, 802.1Qat, 802.1Qav) BLW Baseline Wander BPDU Bridge Protocol Data Unit. Messages which carry the Spanning Tree Protocol information. Byte 8 bits CRC Cyclic Redundancy Check. A common technique for detection data transmission errors. CRC for Ethernet is 32 bits long. CSR Control and Status Registers DA Destination Address DWORD 32 bits FCS Frame Check Sequence. The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction. FID Frame or Filter ID. Specifies the frame identifier. Alternately is the filter identifier. FIFO First In First Out buffer FSM Finite State Machine GPIO General Purpose I/O Host External system (Includes processor, application software, etc.) IGMP Internet Group Management Protocol. Defined by RFC 1112, RFC 2236, and RFC 4604 to establish multicast group membership in IPv4 networks. IPG Inter-Packet Gap. A time delay between successive data packets mandated by the network standard for protocol reasons. Jumbo Packet A packet larger than the standard Ethernet packet (1518 bytes). Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. lsb Least Significant Bit LSB Least Significant Byte MAC Media Access Controller. A functional block responsible for implementing the media access control layer, which is a sublayer of the data link layer. MDI Medium Dependent Interface. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDIX Media Independent Interface with Crossover. An Ethernet port connection that allows networked end stations (i.e., PCs or workstations) to connect to each other using a null-modem, or crossover, cable. MIB Management Information Base. The MIB comprises the management portion of network devices. This can include monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). MII Media Independent Interface. The MII accesses PHY registers as defined in the IEEE 802.3 specification. DS00002392C-page 4  2017-2019 Microchip Technology Inc. KSZ9477S TABLE 1-1: GENERAL TERMS (CONTINUED) Term Description MIIM Media Independent Interface Management MLD Multicast Listening Discovery. This protocol is defined by RFC 3810 and RFC 4604 to establish multicast group membership in IPv6 networks. MLT-3 Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. msb Most Significant Bit MSB Most Significant Byte NRZ Non Return to Zero. A type of signal data encoding whereby the signal does not return to a zero state in between bits. NRZI Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and leaves the signal unchanged for a “0” N/A Not Applicable NC No Connect OUI Organizationally Unique Identifier PHY A device or function block which performs the physical layer interface function in a network. PLL Phase Locked Loop. A electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. PTP Precision Time Protocol RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. RTC Real-Time Clock SA Source Address SFD Start of Frame Delimiter. The 8-bit value indicating the end of the preamble of an Ethernet frame. SQE Signal Quality Error (also known as “heartbeat”) SSD Start of Stream Delimiter TCP Transmission Control Protocol UDP User Datagram Protocol - A connectionless protocol run on top of IP networks UTP Unshielded Twisted Pair. Commonly a cable containing 4 twisted pairs of wire. UUID Universally Unique IDentifier VLAN Virtual Local Area Network WORD 16 bits  2017-2019 Microchip Technology Inc. DS00002392C-page 5 KSZ9477S 1.2 Buffer Types TABLE 1-2: BUFFER TYPES Buffer Type I Description Input IPU IPU/O IPD IPD/O O8 Input with internal pull-up (58 k ±30%) Input with internal pull-up (58 k ±30%) during power-up/reset; output pin during normal operation Input with internal pull-down (58 k ±30%) Input with internal pull-down (58 k ±30%) during power-up/reset; output pin during normal operation Output with 8 mA sink and 8 mA source O24 Output with 24 mA sink and 24 mA source OPU Output (8mA) with internal pull-up (58 k ±30%) OPD Output (8mA) with internal pull-down (58 k ±30%) SGMII-I SGMII Input SGMII-O SGMII Output AIO Analog bidirectional ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin P Power GND Ground Note: Refer to Section 6.3, "Electrical Characteristics," on page 236 for the electrical characteristics of the various buffers. DS00002392C-page 6  2017-2019 Microchip Technology Inc. KSZ9477S 1.3 Register Nomenclature TABLE 1-3: REGISTER NOMENCLATURE Register Bit Type Notation R Read: A register or bit with this attribute can be read. W Write: A register or bit with this attribute can be written. RO Read only: Read only. Writes have no effect. RC Read to Clear: Contents is cleared after the read. Writes have no effect. WO Write only: If a register or bit is write-only, reads will return unspecified data. WC Write One to Clear: Writing a one clears the value. Writing a zero has no effect. W0C Write Zero to Clear: Writing a zero clears the value. Writing a one has no effect. LL Latch Low: Applies to certain RO status bits. If a status condition causes this bit to go low, it will maintain the low state until read, even if the status condition changes. A read clears the latch, allowing the bit to go high if dictated by the status condition. LH Latch High: Applies to certain RO status bits. If a status condition causes this bit to go high, it will maintain the high state until read, even if the status condition changes. A read clears the latch, allowing the bit to go low if dictated by the status condition. SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no effect. Contents can be read. RESERVED 1.4 • NXP Register Bit Description Reserved Field: Reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. The value of reserved bits is not guaranteed on a read. References I2C-Bus Specification (UM10204, April 4, 2014): www.nxp.com/documents/user_manual/UM10204.pdf  2017-2019 Microchip Technology Inc. DS00002392C-page 7 KSZ9477S 2.0 INTRODUCTION 2.1 General Description The KSZ9477S is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2 managed Gigabit Ethernet switch, five 10BASE-Te/100BASE-TX/1000BASE-T physical layer transceivers (PHYs) and associated MAC units, and two individually configurable MAC ports (one SGMII interface, one RGMII/MII/RMII interface) for direct connection to a host processor/controller, another Ethernet switch, or an Ethernet PHY transceiver. The SGMII port has two modes of operation: SerDes mode (which supports 1000BASE-X fiber) and SGMII mode. The KSZ9477S is built upon industry-leading Ethernet technology, with features designed to offload host processing and streamline the overall design: • • • • • • Non-blocking wire-speed Ethernet switch fabric supports 1 Gbps on RGMII Full-featured forwarding and filtering control, including port-based Access Control List (ACL) filtering Full VLAN and QoS support Traffic prioritization with per-port ingress/egress queues and by traffic classification Spanning Tree support IEEE 802.1X access control support As a member of the EtherSynch product family, the KSZ9477S incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hardware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware “PTP clock”. IEEE 1588 provides sub-microsecond synchronization for a range of industrial Ethernet applications. The KSZ9477S fully supports the IEEE family of Audio Video Bridging (AVB) standards, which provides high Quality of Service (QoS) for latency sensitive traffic streams over Ethernet. Time-stamping and time-keeping features support IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav, and a time aware scheduler as proposed for IEEE 802.1Qbv. The KSZ9477S also incorporates features that simplify the implementation of DLR and HSR redundancy protocols by offloading tasks from the host processor. For DLR networks, these features include Beacon frame generation, Beacon timeout detection, and MAC table flushing. HSR networks are supported with automatic duplicate frame discard and self-address filtering. The 100Mbps PHYs feature Quiet-WIRE internal filtering to reduce line emissions and enhance immunity to environmental noise. It is ideal for automotive or industrial applications where stringent radiated emission limits must be met. A host processor can access all KSZ9477S registers for control over all PHY, MAC, and switch functions. Full register access is available via the integrated SPI or I2C interfaces, and by in-band management via any one of the data ports. PHY register access is provided by a MIIM interface. Flexible digital I/O voltage allows the MAC port to interface directly with a 1.8/2.5/3.3V host processor/controller/FPGA. Additionally, a robust assortment of power-management features including Wake-on-LAN (WoL) for low power standby operation, have been designed to satisfy energy-efficient system requirements. The KSZ9477S is available in an industrial (-40°C to +85°C) temperature range. An internal block diagram of the KSZ9477S is shown in Figure 2-1. DS00002392C-page 8  2017-2019 Microchip Technology Inc. KSZ9477S Port 2 10/100/1000 PHY 2 Port 3 10/100/1000 PHY 3 Port 4 10/100/1000 PHY 4 Port 5 10/100/1000 PHY 5 Precision  GPIO GPIO IEEE 1588 /  802.1AS Clock KSZ9477S  2017-2019 Microchip Technology Inc. GMAC 1 GMAC 6 GMAC 2 GMAC 7 GMAC 3 GMAC 4 GMAC 5 Control Registers Switch Engine 10/100/1000 PHY 1 1588 & AVB Processing,  Queue Management, QOS, Etc. Port 1 Address Lookup IEEE 1588 / 802.1AS  Time Stamp INTERNAL BLOCK DIAGRAM IEEE 1588 / 802.1AS Time Stamp FIGURE 2-1: RGMII/MII/RMII SGMII MIB Counters Frame Buffers Queue Mgmt. SPI/I2C/MIIM DS00002392C-page 9 KSZ9477S 3.0 PIN DESCRIPTIONS AND CONFIGURATION 3.1 Pin Assignments The device pin diagram for the KSZ9477S can be seen in Figure 3-1. Table 3-1 provides a KSZ9477S pin assignment table. Pin descriptions are provided in Section 3.2, "Pin Descriptions". PIN ASSIGNMENTS (TOP VIEW) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RESET_N SYNCLKO INTRP_N PME_N LED2_1 LED2_0 GPIO_1 LED3_1 LED3_0 DVDDL LED4_1 LED4_0 VDDLS VDDHS S_OUT7M S_OUT7P GND S_IN7P S_IN7M GND S_REXT GND NC NC VDDHS VDDLS DVDDL GND VDDIO IBA DVDDL RXD6_0 FIGURE 3-1: 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 KSZ9477S 128-TQFP-EP (Top View) GND (Connect exposed pad to ground with a via field) RXD6_1 RXD6_2 RXD6_3 VDDIO CRS6 RX_ER6 RX_DV6/CRS_DV6/RX_CTL6 RX_CLK6/REFCLKO6 DVDDL TXD6_0 TXD6_1 TXD6_2 TXD6_3 COL6 TX_ER6 TX_EN6/TX_CTL6 TX_CLK6/REFCLKI6 GND GND DVDDL AVDDH TXRX4M_D TXRX4P_D AVDDL TXRX4M_C TXRX4P_C TXRX4M_B TXRX4P_B AVDDL TXRX4M_A TXRX4P_A AVDDH TXRX1P_A TXRX1M_A AVDDL TXRX1P_B TXRX1M_B TXRX1P_C TXRX1M_C TXRX1P_D TXRX1M_D AVDDH DVDDL TXRX2P_A TXRX2M_A AVDDL TXRX2P_B TXRX2M_B TXRX2P_C TXRX2M_C AVDDL TXRX2P_D TXRX2M_D AVDDH DVDDL TXRX3P_A TXRX3M_A TXRX3P_B TXRX3M_B TXRX3P_C TXRX3M_C AVDDL TXRX3P_D TXRX3M_D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SDO SDI/SDA/MDIO VDDIO SCS_N SCL/MDC LED5_0 LED5_1 DVDDL LED1_0 LED1_1 GND NC GND DVDDL AVDDH TXRX5P_A TXRX5M_A AVDDL TXRX5P_B TXRX5M_B TXRX5P_C TXRX5M_C AVDDL TXRX5P_D TXRX5M_D AVDDH GND AVDDL XO XI ISET AVDDH Note: When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example, RESET_N indicates that the reset signal is active low. The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Section 3.2, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types". DS00002392C-page 10  2017-2019 Microchip Technology Inc. KSZ9477S TABLE 3-1: PIN ASSIGNMENTS Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name 1 TXRX1P_A 33 AVDDH 65 RXD6_0 (Note 3-1) 97 SDO 2 TXRX1M_A 34 TXRX4P_A 66 DVDDL 98 SDI/SDA/MDIO 3 AVDDL 35 TXRX4M_A 67 IBA (Note 3-1) 99 VDDIO 4 TXRX1P_B 36 AVDDL 68 VDDIO 100 SCS_N 5 TXRX1M_B 37 TXRX4P_B 69 GND 101 SCL/MDC 6 TXRX1P_C 38 TXRX4M_B 70 DVDDL 102 LED5_0 7 TXRX1M_C 39 TXRX4P_C 71 VDDLS 103 LED5_1 (Note 3-1) 8 TXRX1P_D 40 TXRX4M_C 72 VDDHS 104 DVDDL 9 TXRX1M_D 41 AVDDL 73 NC 105 LED1_0 (Note 3-1) 10 AVDDH 42 TXRX4P_D 74 NC 106 LED1_1 (Note 3-1) 11 DVDDL 43 TXRX4M_D 75 GND 107 GND 12 TXRX2P_A 44 AVDDH 76 S_REXT 108 NC 13 TXRX2M_A 45 DVDDL 77 GND 109 GND 14 AVDDL 46 GND 78 S_IN7M 110 DVDDL 15 TXRX2P_B 47 GND 79 S_IN7P 111 AVDDH 16 TXRX2M_B 48 TX_CLK6/REFCLKI6 80 GND 112 TXRX5P_A 17 TXRX2P_C 49 TX_EN6/TX_CTL6 81 S_OUT7P 113 TXRX5M_A 18 TXRX2M_C 50 TX_ER6 82 S_OUT7M 114 AVDDL 19 AVDDL 51 COL6 83 VDDHS 115 TXRX5P_B 20 TXRX2P_D 52 TXD6_3 84 VDDLS 116 TXRX5M_B 21 TXRX2M_D 53 TXD6_2 85 LED4_0 (Note 3-1) 117 TXRX5P_C 22 AVDDH 54 TXD6_1 86 LED4_1 (Note 3-1) 118 TXRX5M_C 23 DVDDL 55 TXD6_0 87 DVDDL 119 AVDDL 24 TXRX3P_A 56 DVDDL 88 LED3_0 120 TXRX5P_D 25 TXRX3M_A 57 RX_CLK6/REFCLKO6 89 LED3_1 (Note 3-1) 121 TXRX5M_D 26 TXRX3P_B 58 RX_DV6/CRS_DV6/ RX_CTL6 90 GPIO_1 122 AVDDH 27 TXRX3M_B 59 RX_ER6 91 LED2_0 (Note 3-1) 123 GND 28 TXRX3P_C 60 CRS6 92 LED2_1 (Note 3-1) 124 AVDDL 29 TXRX3M_C 61 VDDIO 93 PME_N 125 XO 30 AVDDL 62 RXD6_3 (Note 3-1) 94 INTRP_N (Note 3-1) 126 XI 31 TXRX3P_D 63 RXD6_2 (Note 3-1) 95 SYNCLKO (Note 3-1) 127 ISET 32 TXRX3M_D 64 RXD6_1 (Note 3-1) 96 RESET_N 128 AVDDH Exposed Pad Must be Connected to GND Note 3-1 This pin provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information.  2017-2019 Microchip Technology Inc. DS00002392C-page 11 KSZ9477S 3.2 Pin Descriptions This sections details the functions of the various device signals. TABLE 3-2: PIN DESCRIPTIONS Buffer Type Name Symbol Port 5-1 Ethernet TX/RX Pair A + TXRX[5:1]P_A Port 5-1 Ethernet TX/RX Pair A - TXRX[5:1]M_A Port 5-1 Ethernet TX/RX Pair B + TXRX[5:1]P_B Port 5-1 Ethernet TX/RX Pair B - TXRX[5:1]M_B Port 5-1 Ethernet TX/RX Pair C + TXRX[5:1]P_C AIO Port 5-1 1000BASE-T Differential Data Pair C (+) Port 5-1 Ethernet TX/RX Pair C - TXRX[5:1]M_C AIO Port 5-1 1000BASE-T Differential Data Pair C (-) Port 5-1 Ethernet TX/RX Pair D + TXRX[5:1]P_D AIO Port 5-1 1000BASE-T Differential Data Pair D (+) Port 5-1 Ethernet TX/RX Pair D - TXRX[5:1]M_D AIO Port 5-1 1000BASE-T Differential Data Pair D (-) Description Ports 5-1 Gigabit Ethernet Pins AIO Port 5-1 1000BASE-T Differential Data Pair A (+) Note: AIO Port 5-1 1000BASE-T Differential Data Pair A (-) Note: AIO 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. Port 5-1 1000BASE-T Differential Data Pair B (+) Note: AIO 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. Port 5-1 1000BASE-T Differential Data Pair B (-) Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. Port 6 RGMII/MII/RMII Pins Port 6 Transmit/ Reference Clock TX_CLK6/ REFCLKI6 I/O8 MII Mode: TX_CLK6 is the Port 6 25/2.5MHz Transmit Clock. In PHY mode this pin is an output, in MAC mode it is an input. RMII Mode: REFCLKI6 is the Port 6 50MHz Reference Clock input when in RMII Normal mode. This pin is unused when in RMII Clock mode. RGMII Mode: TX_CLK6 is the Port 6 125/25/2.5MHz Transmit Clock input. Port 6 Transmit Enable/Control TX_EN6/ TX_CTL6 IPD MII/RMII Modes: TX_EN6 is the Port 6 Transmit Enable. Port 6 Transmit Error TX_ER6 IPD MII Mode: Port 6 Transmit Error input. RGMII Mode: TX_CTL6 is the Port 6 Transmit Control. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. DS00002392C-page 12  2017-2019 Microchip Technology Inc. KSZ9477S TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Port 6 Collision Detect COL6 IPD/O8 Description MII Mode: Port 6 Collision Detect. In PHY mode this pin is an output, in MAC mode it is an input. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. Port 6 Transmit Data 3 TXD6_3 IPD MII/RGMII Modes: Port 6 Transmit Data bus bit 3. RMII Mode: Not used. Do not connect this pin in this mode of operation. Port 6 Transmit Data 2 TXD6_2 IPD MII/RGMII Modes: Port 6 Transmit Data bus bit 2. RMII Mode: Not used. Do not connect this pin in this mode of operation. Port 6 Transmit Data 1 TXD6_1 IPD MII/RMII/RGMII Modes: Port 6 Transmit Data bus bit 1. Port 6 Transmit Data 0 TXD6_0 IPD MII/RMII/RGMII Modes: Port 6 Transmit Data bus bit 0. Port 6 Receive/ Reference Clock RX_CLK6/ REFCLKO6 I/O24 MII Mode: RX_CLK6 is the Port 6 25/2.5MHz Receive Clock. In PHY mode this pin is an output, in MAC mode it is an input. RMII Mode: REFCLKO6 is the Port 6 50MHz Reference Clock output when in RMII Clock mode. This pin is unused when in RMII Normal mode. RGMII Mode: RX_CLK6 is the Port 6 125/25/2.5MHz Receive Clock output. Port 6 Receive Data Valid / Carrier Sense / Control RX_DV6/ CRS_DV6/ RX_CTL6 IPD/O24 MII Mode: RX_DV6 is the Port 6 Received Data Valid output. RMII Mode: CRS_DV6 is the Carrier Sense / Receive Data Valid output. RGMII Mode: RX_CTL6 is the Receive Control output. Port 6 Receive Error RX_ER6 IPD/O24 MII Mode: Port 6 Receive Error output. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. Port 6 Carrier Sense CRS6 IPD/O8 MII Mode: Port 6 Carrier Sense. In PHY mode this pin is an output, in MAC mode it is an input. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation.  2017-2019 Microchip Technology Inc. DS00002392C-page 13 KSZ9477S TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Port 6 Receive Data 3 RXD6_3 IPD/O24 Description MII/RGMII Modes: Port 6 Receive Data bus bit 3. RMII Mode: Not used. Do not connect this pin in this mode of operation. Note: Port 6 Receive Data 2 RXD6_2 IPD/O24 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. MII/RGMII Modes: Port 6 Receive Data bus bit 2. RMII Mode: Not used. Do not connect this pin in this mode of operation. Note: IPD/O24 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 6 Receive Data 1 RXD6_1 MII/RMII/RGMII Modes: Port 6 Receive Data bus bit 1. Port 6 Receive Data 0 RXD6_0 Port 7 SGMII Differential Input Data + S_IN7P SGMII-I Port 7 SGMII Differential Input Data + Port 7 SGMII Differential Input Data - S_IN7M SGMII-I Port 7 SGMII Differential Input Data - Port 7 SGMII Differential Output Data + S_OUT7P SGMII-O Port 7 SGMII Differential Output Data + Port 7 SGMII Differential Output Data - S_OUT7M SGMII-O Port 7 SGMII Differential Output Data - Port 7 SGMII Reference Resistor S_REXT A Note: IPD/O24 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. MII/RMII/RGMII Modes: Port 6 Receive Data bus bit 0. Note: This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 7 SGMII Pins SGMII reference resistor. Connect a 191Ω 1% resistor between this pin and GND using a short trace to avoid noise coupling. SPI/I2C/MIIM Interface Pins SPI/I2C/MIIM Serial Clock SCL/MDC IPU SPI/I2C Modes: SCL serial clock. MIIM Mode: MDC serial clock. SPI Data Out SDO O8 SPI Mode: Data out (also known as MISO). I2C/MIIM Modes: Not used. DS00002392C-page 14  2017-2019 Microchip Technology Inc. KSZ9477S TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type SPI Data In / I2C/MIIM Data In/Out SDI/SDA/MDIO IPU/O8 Description SPI Mode: SDI Data In (also known as MOSI). I2C Mode: SDA Data In/Out. MIIM Mode: MDIO Data In/Out. SDI and MDIO are open-drain signals when in the output state. An external pull-up resistor to VDDIO (1.0kΩ to 4.7kΩ) is required. SPI Chip Select SCS_N IPU SPI Mode: Chip Select (active low). I2C/MIIM Modes: Not used. LED Pins Port 1 LED Indicator 0 LED1_0 IPU/O8 Port 1 LED Indicator 0. Active low output sinks current to light an external LED. Note: Port 1 LED Indicator 1 LED1_1 IPU/O8 Port 1 LED Indicator 1. Active low output sinks current to light an external LED. Note: Port 2 LED Indicator 0 LED2_0 IPU/O8 LED2_1 IPU/O8 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 2 LED Indicator 0. Active low output sinks current to light an external LED. Note: Port 2 LED Indicator 1 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 2 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 3 LED Indicator 0 LED3_0 IPU/O8 Port 3 LED Indicator 0. Active low output sinks current to light an external LED. Port 3 LED Indicator 1 LED3_1 IPU/O8 Port 3 LED Indicator 1. Active low output sinks current to light an external LED. Note:  2017-2019 Microchip Technology Inc. This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. DS00002392C-page 15 KSZ9477S TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Port 4 LED Indicator 0 LED4_0 IPU/O8 Description Port 4 LED Indicator 0. Active low output sinks current to light an external LED. Note: Port 4 LED Indicator 1 LED4_1 IPU/O8 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 4 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 5 LED Indicator 0 LED5_0 IPU/O8 Port 5 LED Indicator 0. Active low output sinks current to light an external LED. Port 5 LED Indicator 1 LED5_1 IPU/O8 Port 5 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Miscellaneous Pins Interrupt INTRP_N OPU Active low, open-drain interrupt. This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Note: Power Management Event PME_N O8 This pin requires an external pull-up resistor. Power Management Event. This output signal indicates that an energy detect event has occurred. It is intended to wake up the system from a low power mode. Note: The assertion polarity is programmable (default active low). An external pull-up resistor is required for active-low operation; an external pull-down resistor is required for active-high operation. System Reset RESET_N IPU Active low system reset. The device must be reset either during or after power-on. An RC circuit is suggested for power-on reset. Crystal Clock / Oscillator Input XI ICLK Crystal clock / oscillator input. When using a 25MHz crystal, this input is connected to one lead of the crystal. When using an oscillator, this pin is the input from the oscillator. The crystal oscillator should have a tolerance of ±50ppm. Crystal Clock Output XO OCLK Crystal clock / oscillator output. When using a 25MHz crystal, this output is connected to one lead of the crystal. When using an oscillator, this pin is left unconnected. DS00002392C-page 16  2017-2019 Microchip Technology Inc. KSZ9477S TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type 25/125MHz Reference Clock Output SYNCLKO IPU/O24 25/125MHz reference clock output, derived from the crystal input or the recovered clock of any PHY. This signal may be used for Synchronous Ethernet. This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. General Purpose Input/Output 1 GPIO_1 IPU/O8 This signal can be used as an input or output for use by the IEEE 1588 event trigger or timestamp capture units. It will be synchronized to the internal IEEE 1588 clock. This pin can also be controlled (as an output) or sampled (as an input) via device registers. Transmit Output Current Set Resistor ISET A Transmit output current set resistor. This pin configures the physical transmit output current. It must be connected to GND through a 6.04kΩ 1% resistor. In-Band Management Configuration Strap IBA IPD In-Band Management Configuration strap. This pin provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. No Connect NC - +3.3/2.5/1.8V I/O Power VDDIO P +3.3V / +2.5V / +1.8V I/O Power +2.5V Analog Power AVDDH P +2.5V Analog Power +1.2V Analog Power AVDDL P +1.2V Analog Power +1.2V Digital Power DVDDL P +1.2V Digital Power +1.2V SGMII Core Power VDDLS P +1.2V SGMII Core Power +2.5V SGMII I/O Power VDDHS P +2.5V SGMII I/O Power Ground GND GND Ground (pins and pad) Description No Connect. For proper operation, this pin must be left unconnected. Power/Ground Pins  2017-2019 Microchip Technology Inc. DS00002392C-page 17 KSZ9477S 3.2.1 CONFIGURATION STRAPS The KSZ9477S utilizes configuration strap pins to configure the device for different modes. While RESET_N is low, these pins are hi-Z. Pull-up/down resistors are used to create high or low states on these pins, which are internally sampled at the rising edge of RESET_N. All of these pins have a weak internal pull-up or pull-down resistor which provides a default level for strapping. To strap an LED pin low, use a 750Ω to 1kΩ external pull-down resistor. To strap a non-LED pin high, use an external 1kΩ to 10kΩ pull-up resistor to VDDIO. Once RESET_N is high, all of these pins become driven outputs. Because the internal pull-up/down resistors are not strong, consideration must be given to any other pull-up/down resistors which may reside on the board or inside a device connected to these pins. When an LED pin is directly driving an LED, the effect of the LED and LED load resistor on the strapping level must be considered. This is the reason for using a small value resistor to pull an LED pin low. This is especially true when an LED is powered from a voltage that is higher than VDDIO. The configuration strap pins and their associated functions are detailed in Table 3-3. TABLE 3-3: CONFIGURATION STRAP DESCRIPTIONS Configuration Strap Pin Description LED1_0 Quiet-WIRE Filtering Enable 0: Quiet-WIRE filtering enabled 1: Quiet-WIRE filtering disabled (Default) LED1_1 Flow Control (All Ports) 0: Flow control disabled 1: Flow control enabled (Default) LED2_1 Link-up Mode (All PHYs) 0: Fast Link-up: Auto-negotiation and auto MDI/MDI-X are disabled 1: Normal Link-up: Auto-negotiation and auto MDI/MDI-X are enabled (Default) Note: Since Fast Link-up disables auto-negotiation and auto-crossover, it is suitable only for specialized applications. LED4_0, LED2_0 When LED2_1 = 1 at strap-in (Normal Link-up): [LED4_0, LED2_0]: Auto-Negotiation Enable (All PHYs) / NAND Tree Test Mode 00: Reserved 01: Auto-negotiation disabled, forced as 100 Mbps and half duplex. Auto-MDI-X is on. 10: NAND Tree test mode 11: Auto-negotiation enabled (Default) When LED2_1 = 0 at strap-in (Fast Link-up; All PHYs Full-Duplex; Auto-negotiation and Auto-MDI-X are off): LED2_0: 1000BASE-T Master/Slave Mode, 100BASE-T MDI/MDI-X Mode (All PHYs) 0: 1000BASE-T: Slave Mode 100BASE-T: MDI-X 1: 1000BASE-T: Master Mode (Default) 100BASE-T: MDI (Default) LED4_0: PHY Speed Select (All PHYs) 0: 1000BASE-T 1: 100BASE-TX (Default) LED4_1, LED3_1 [LED4_1, LED3_1]: Management Interface Mode 00: MIIM (MDIO) 01: I2C 1x: SPI (Default) LED5_1 DS00002392C-page 18 Switch Enable at Startup 0: Start Switch is disabled. The switch will not forward packets until the Start Switch bit is set in the Switch Operation Register. 1: Start Switch is enabled. The switch will forward packets immediately after reset. (Default)  2017-2019 Microchip Technology Inc. KSZ9477S TABLE 3-3: CONFIGURATION STRAP DESCRIPTIONS (CONTINUED) Configuration Strap Pin RXD6_3, RXD6_2 Description [RXD6_3, RXD6_2]: Port 6 Mode 00: RGMII (Default) 01: RMII 10: Reserved 11: MII RXD6_1 Port 6 MII/RMII Mode 0: MII: PHY Mode (Default) RMII: Clock Mode. RMII 50MHz reference clock is output on REFCLKO6. (Default) RGMII: No effect 1: MII: MAC Mode RMII: Normal Mode. RMII 50MHz reference clock is input on REFCLKI6. RGMII: No effect RXD6_0 Port 6 Speed Select 0: 1000Mbps Mode (Default) 1: 100Mbps Mode Note: IBA If Port 6 is configured for MII or RMII, set the speed to 100Mbps. In-Band Management 0: Disable In-Band Management (Default) 1: Enable In-Band Management SYNCLKO SGMII Mode C 0: Invalid 1: Normal SGMII operation. This pin must be strapped high for proper operation. (Default) INTRP_N SGMII Mode J 0: Invalid 1: Normal SGMII operation. This pin must be strapped high for proper operation. (Default)  2017-2019 Microchip Technology Inc. DS00002392C-page 19 KSZ9477S 4.0 FUNCTIONAL DESCRIPTION This section provides functional descriptions for the following: • • • • • • • • • • • • • • Physical Layer Transceiver (PHY) LEDs Media Access Controller (MAC) Switch Ring Redundancy IEEE 1588 Precision Time Protocol Audio Video Bridging and Time Sensitive Networks NAND Tree Support Clocking Power Power Management Management Interface In-Band Management MAC Interface (Ports 6 and 7) 4.1 Physical Layer Transceiver (PHY) Ports 1 through 5 include completely integrated triple-speed (10BASE-Te, 100BASE-TX, 1000BASE-T) Ethernet physical layer transceivers for transmission and reception of data over standard four-pair unshielded twisted pair (UTP), CAT5 or better Ethernet cable. The device reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs, eliminating the need for external termination resistors. The internal chip termination and biasing provides significant power savings when compared with using external biasing and termination resistors. The device can automatically detect and correct for differential pair misplacements and polarity reversals, and correct for propagation delay differences between the four differential pairs, as specified in the IEEE 802.3 standard for 1000BASE-T operation. 4.1.1 1000BASE-T TRANSCEIVER The 1000BASE-T transceiver is based on a mixed-signal/digital signal processing (DSP) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, a precision clock recovery scheme, and power-efficient line drivers. 4.1.1.1 Analog Echo Cancellation Circuit In 1000BASE-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit relieves the burden of the ADC and the adaptive equalizer. This circuit is disabled in 10BASE-Te/100BASE-TX mode. 4.1.1.2 Automatic Gain Control (AGC) In 1000BASE-T mode, the automatic gain control circuit provides initial gain adjustment to boost up the signal level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal. 4.1.1.3 Analog-to-Digital Converter (ADC) In 1000BASE-T mode, the analog-to-digital converter digitizes the incoming signal. ADC performance is essential to the overall performance of the transceiver. This circuit is disabled in 10BASE-Te/100BASE-TX mode. 4.1.1.4 Timing Recovery Circuit In 1000BASE-T mode, the mixed signal clock recovery circuit, together with the digital phase locked loop (PLL), is used to recover and track the incoming timing information from the received data. The digital PLL has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal. The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This also helps to facilitate echo cancellation and NEXT removal. DS00002392C-page 20  2017-2019 Microchip Technology Inc. KSZ9477S 4.1.1.5 Adaptive Equalizer In 1000BASE-T mode, the adaptive equalizer provides the following functions: • Detection for partial response signaling • Removal of NEXT and ECHO noise • Channel equalization Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch. The device uses a digital echo canceler to further reduce echo components on the receive signal. In 1000BASE-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels). This results in high-frequency cross-talk coming from adjacent wires. The device uses three NEXT cancelers on each receive channel to minimize the cross-talk induced by the other three channels. In 10BASE-Te/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. 4.1.1.6 Trellis Encoder and Decoder In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. On the receiving side, the idle stream is examined first. The scrambler seed, pair skew, pair order and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-bit symbols and de-scrambled into 8-bit data. 4.1.2 4.1.2.1 100BASE-TX TRANSCEIVER 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external ISET resistor sets the output current for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-Te output driver is also incorporated into the 100BASETX driver. 4.1.2.2 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/ 5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC. 4.1.2.3 Scrambler/De-Scrambler The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. The scrambler is used only for 100BASE-TX. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter.  2017-2019 Microchip Technology Inc. DS00002392C-page 21 KSZ9477S 4.1.3 10BASE-Te TRANSCEIVER 10BASE-Te is an energy-efficient version of 10BASE-T which is powered from a 2.5V supply. It has a reduced transmit signal amplitude and requires Cat5 cable. It is inter-operable to 100m with 10BASE-T when Cat5 cable is used. 4.1.3.1 10BASE-Te Transmit The 10BASE-Te driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with typical 1.75V amplitude (compared to the typical transmit amplitude of 2.5V for 10BASE-T). The harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 4.1.3.2 10BASE-Te Receive On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RXP1 or RXM1 input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the device decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. 4.1.4 AUTO MDI/MDI-X The automatic MDI/MDI-X feature, also known as auto crossover, eliminates the need to determine whether to use a straight cable or a crossover cable between the device and its link partner. The auto-sense function detects the MDI/ MDI-X pair mapping from the link partner, and assigns the MDI/MDI-X pair mapping of the device accordingly. Table 41 shows the device’s 10/100/1000 Mbps pin configuration assignments for MDI and MDI-X pin mapping. TABLE 4-1: MDI/MDI-X PIN DEFINITIONS Pin (RJ45 pair) MDI 1000BASE-T 100BASE-TX MDI-X 10BASE-Te 1000BASE-T 100BASE-TX 10BASE-Te TXRXxP/M_A (1,2) A+/- TX+/- TX+/- B+/- RX+/- RX+/- TXRXxP/M_B (3,6) B+/- RX+/- RX+/- A+/- TX+/- TX+/- TXRXxP/M_C (4,5) C+/- Not used Not used D+/- Not used Not used TXRXxP/M_D (7,8) D+/- Not used Not used C+/- Not used Not used Auto MDI/MDI-X is enabled by default. It can be disabled through the port control registers. If Auto MDI/MDI-X is disabled, the port control register can also be used to select between MDI and MDI-X settings. An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X. 4.1.5 PAIR-SWAP, ALIGNMENT, AND POLARITY CHECK In 1000BASE-T mode, the device: • Detects incorrect channel order and automatically restores the pair order for the A and B pairs. This is also done separately for the C and D pairs. Crossing of A or B pairs to C or D pairs is not corrected. • Supports 50±10ns difference in propagation delay between pairs of channels in accordance with the IEEE 802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchronized. Incorrect pair polarities of the differential signals are automatically corrected for all speeds. 4.1.6 WAVE SHAPING, SLEW-RATE CONTROL, AND PARTIAL RESPONSE In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. • For 1000BASE-T, a special partial-response signaling method is used to provide the bandwidth-limiting feature for the transmission path. • For 100BASE-TX, a simple slew-rate control method is used to minimize EMI. • For 10BASE-Te, pre-emphasis is used to extend the signal quality through the cable. DS00002392C-page 22  2017-2019 Microchip Technology Inc. KSZ9477S 4.1.7 AUTO-NEGOTIATION The device conforms to the auto-negotiation protocol as described by IEEE 802.3. Auto-negotiation allows each port to operate at either 10BASE-Te, 100BASE-TX or 1000BASE-T by allowing link partners to select the best common mode of operation. During auto-negotiation, the link partners advertise capabilities across the link to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest priority. • • • • • • Priority 1: 1000BASE-T, full-duplex Priority 2: 1000BASE-T, half-duplex Priority 3: 100BASE-TX, full-duplex Priority 4: 100BASE-TX, half-duplex Priority 5: 10BASE-Te, full-duplex Priority 6: 10BASE-Te, half-duplex If the KSZ9477S link partner doesn’t support auto-negotiation or is forced to bypass auto-negotiation for 10BASE-Te and 100BASE-TX modes, the KSZ9477S port sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ9477S to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation advertisement protocol. The auto-negotiation link-up process is shown in Figure 4-1. FIGURE 4-1: AUTO-NEGOTIATION AND PARALLEL OPERATION For 1000BASE-T mode, auto-negotiation is always required to establish a link. During 1000BASE-T auto-negotiation, the master and slave configuration is first resolved between link partners. Then the link is established with the highest common capabilities between link partners.  2017-2019 Microchip Technology Inc. DS00002392C-page 23 KSZ9477S Auto-negotiation is enabled by default after power-up or hardware reset. Afterwards, auto-negotiation can be enabled or disabled via bit 12 of the PHY Basic Control Register. If auto-negotiation is disabled, the speed is set by bits 6 and 13 of the PHY Basic Control Register, and the duplex is set by bit 8. If the speed is changed on the fly, the link goes down and either auto-negotiation or parallel detection initiate until a common speed between the KSZ9477S and its link partner is re-established for a link. If link is already established and there is no change of speed on the fly, the changes (for example, duplex and pause capabilities) will not take effect unless either auto-negotiation is restarted through bit 9 of the PHY Basic Control Register, or a link-down to link-up transition occurs (i.e. disconnecting and reconnecting the cable). After auto-negotiation is completed, the link status is updated in the PHY Basic Status Register, and the link partner capabilities are updated in the PHY Auto-Negotiation Link Partner Ability Register, PHY Auto-Negotiation Expansion Status Register, and PHY 1000BASE-T Status Register. 4.1.8 QUIET-WIRE FILTERING Quiet-WIRE is a feature to enhance 100BASE-TX EMC performance by reducing both conducted and radiated emissions from the TXP/M signal pair. It can be used either to reduce absolute emissions, or to enable replacement of shielded cable with unshielded cable, all while maintaining interoperability with standard 100BASE-TX devices. Quiet-WIRE filtering is implemented internally, with no additional external components required. It is enabled or disabled for all PHYs at power-up and reset by a strapping option on the LED1_0 pin. The default setting for Quiet-WIRE reduces emissions primarily above 60MHz, with less reduction at lower frequencies. Several dB of reduction is possible. Signal attenuation is approximately equivalent to increasing the cable length by 10 to 20 meters, thus reducing cable reach by that amount. For applications needing more modest improvement in emissions, the level of filtering can be reduced by writing to certain registers. Each PHY port has a set of MMD registers for configuring Quiet-WIRE. Table 4-2 provide the register settings for disabling Quiet-WIRE, and for enabling it in the default setting as can be enabled by the strapping option. TABLE 4-2: 4.1.9 ENABLING AND DISABLING QUIET-WIRE MMD Register Disable Quiet-WIRE Enable Quiet-WIRE default MMD Quiet-WIRE Configuration 0 Register 0x0000 0x0001 MMD Quiet-WIRE Configuration 1 Register 0x1F0F 0x0E03 MMD Quiet-WIRE Configuration 2 Register 0x1F1F 0x3020 MMD Quiet-WIRE Configuration 3 Register 0x0010 0x2E36 MMD Quiet-WIRE Configuration 4 Register 0x0000 0x0B1C MMD Quiet-WIRE Configuration 5 Register 0x0000 0x7E01 MMD Quiet-WIRE Configuration 6 Register 0x0000 0x7F7E MMD Quiet-WIRE Configuration 7 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 8 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 9 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 10 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 11 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 12 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 13 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 14 Register 0x0000 0x0000 MMD Quiet-WIRE Configuration 15 Register 0x0000 0x0000 FAST LINK-UP Link up time is normally determined by the time it takes to complete auto-negotiation. Additional time may be added by the auto MDI/MDI-X feature. The total link up time from power-up or cable connect is typically a second or more. DS00002392C-page 24  2017-2019 Microchip Technology Inc. KSZ9477S Fast Link-up mode significantly reduces 100BASE-TX link-up time by disabling both auto-negotiation and auto MDI/ MDI-X, and fixing the TX and RX channels. This mode is enabled or disabled by the LED2_1 strapping option. It is not set by registers, so fast link-up is available immediately upon power-up. Fast Link-up is available at power-up only for 100BASE-TX link speed, which is selected by strapping the LED4_0 pin high. Fast Link-up is also available for 10BASETe, but this link speed must first be selected via a register write. Fast Link-up is intended for specialized applications where both link partners are known in advance. The link must also be known so that the fixed transmit channel of one device connects to the fixed receive channel of the other device, and vice versa. The TX and RX channel assignments are determined by the MDI/MDI-X strapping option on LED2_0. If a device in Fast Link-up mode is connected to a normal device (auto-negotiate and auto-MDI/MDI-X), there will be no problems linking, but the speed advantage of Fast Link-up will not be realized. For more information on configuration straps, refer to Section 3.2.1, "Configuration Straps," on page 18. 4.1.10 LinkMD® CABLE DIAGNOSTICS The LinkMD® function utilizes Time Domain Reflectometry (TDR) to analyze the cabling for common cabling problems, such as open circuits, short circuits and impedance mismatches. LinkMD® works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, and then analyzing the shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD® function processes this TDR information and presents it as a numerical value that can be translated to a cable distance. A LinkMD test is initiated individually for each PHY and for a specific PHY differential pair. 4.1.10.1 Usage To run a LinkMD test on all four pairs of one PHY, follow this flow. 1. Disable auto-negotiation: Write 0 to of register 0xN100-0xN101 bit 12. 2. Configure register 0xN112-0xN113 to enable master-slave manual configuration mode. 3. Start cable diagnostic by writing 1 to register 0xN124-0xN125 bit 15. This enable bit is self-clearing. 4. Wait (poll) for register 0xN124-0xN125 bit 15 to return 0, which indicates that the cable diagnostic test is completed. Alternatively, wait 250ms. 5. Read cable diagnostic test status in register 0xN124-0xN125 bits [9-8]. The results are: a) 00 = normal operation b) 01 = open condition detected in cable (valid result) c) 10 = short condition detected in cable (valid result) d) 11 = cable diagnostic test invalid (test failed) The ‘11’ case occurs when the PHY is unable to shut down the link partner. In this instance, the test is not run because it would be impossible for the PHY to determine if the detected signal is a reflection of the signal generated or a signal from another source. 6. For status 01 or 10, read the Cable Diagnostic Result in register 0xN124-0xN125 bits [7:0]. Get distance to fault by the following formula: Distance to fault (meters) = 0.8 * (Cable Diagnostic Result – 22). 7. To test another differential pair on this PHY, change the value of register 0xN124-0xN125 bits [13:12] when initiating the test.  2017-2019 Microchip Technology Inc. DS00002392C-page 25 KSZ9477S 8. Return the registers to their original values and restart auto-negotiation. The following script will test the four pairs of port 1. For other ports, change the register addresses accordingly. “ww” = write word (16-bits) [register] [data] “rw” = read word (16-bits) [register] Values are hexadecimal. ww 1100 0140 ww 1112 1000 # initialization # initialization ww 1124 8000 # initiate test for pair A sleep 250 msec rw 1124 # read result for pair A ww 1124 9000 # initiate test for pair B sleep 250 msec rw 1124 # read result for pair B ww 1124 a000 # initiate test for pair C sleep 250 msec rw 1124 # read result for pair C ww 1124 b000 # initiate test for pair D sleep 250 msec rw 1124 # read result for pair D ww 1112 0700 # return register to default setting ww 0 1340 # return register to default setting (may vary by application) 4.1.11 LinkMD®+ ENHANCED DIAGNOSTICS: RECEIVE SIGNAL QUALITY INDICATOR A receive Signal Quality Indicator (SQI) feature can be used to determine the relative quality of the 100BASE-TX receive signal. It approximates a signal-to-noise ratio, and is affected by cable length, cable quality, and coupling of environmental noise. The raw SQI values are available for reading at any time from the SQI registers. These four registers are located in the MMD register space and begin with MMD Signal Quality Channel A Register. There is one register for each of the four differential pairs (channels) of the 1000BASE-T interface, allowing separate calculation of SQI for each twisted pair of the interface. When a port is operated in 100BASE-TX mode, only the channel A register is used for determining SQI. Use bits [14:8] from the register. A lower value indicates better signal quality, while a higher value indicates worse signal quality. Even for a stable configuration in a low-noise environment, the value read from this register will vary, often significantly. It is necessary to average many readings to come up with a reasonably useful result. The update interval of the SQI register is 2µs, so measurements taken more frequently than 2µs will be redundant. In a quiet environment, It is suggested to average a minimum of 10 to 20 readings. In a noisy environment, individual readings are even more unreliable, so a minimum of 30 to 50 readings are suggested for averaging. The SQI circuit does not include any hysteresis. The Linux driver provided by Microchip includes SQI support. It does the averaging and provides a single number to represent the SQI. DS00002392C-page 26  2017-2019 Microchip Technology Inc. KSZ9477S 4.1.12 REMOTE PHY LOOPBACK This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between the KSZ9477S and its Ethernet PHY link partner, and is supported for 10/100/1000 Mbps at full-duplex. The loopback data path is shown in Figure 4-2 and functions as follows: • The Ethernet PHY link partner transmits data to the KSZ9477S PHY port. • Data received at the external pins of the PHY port is looped back without passing through the MAC and internal switch fabric. • The same KSZ9477S PHY port transmits data back to the Ethernet PHY link partner. FIGURE 4-2: REMOTE PHY LOOPBACK Device PHY Port N (1-5) RJ-45 10/100/1000 PHY MAC Switch Fabric CAT-5 (UTP) RJ-45 Ethernet PHY Link Partner The following programming steps and register settings are for remote PHY loopback mode for 1000BASE-T Master Mode, 1000BASE-T Slave Mode, 100BASE-TX Mode, and 10BASE-T Mode. • 1000BASE-T Master Mode - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x1F00 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x1340 • 1000BASE-T Slave Mode - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x1300 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x1340 • 100BASE-TX Mode - Set Port N (1-5), PHY Auto-Negotiation Advertisement Register = 0x0181 - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x0C00  2017-2019 Microchip Technology Inc. DS00002392C-page 27 KSZ9477S - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x3300 • 10BASE-T Mode - Set Port N (1-5), PHY Auto-Negotiation Advertisement Register = 0x0061 - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x0C00 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x3300 4.2 LEDs Each PHY port has two programmable LED output pins, LEDx_0 and LEDx_1, to indicate the PHY link and activity status. Two different LED modes are available. The LED mode can be changed individually for each PHY port by writing to the PHY Mode bit in the PHY indirect register: MMD 2, address 0, bit 4: • 1 = Single-LED Mode • 0 = Tri-Color Dual-LED Mode (Default) Each LED output pin can directly drive an LED with a series resistor (typically 220Ω to 470Ω). LED outputs are activelow. 4.2.1 SINGLE-LED MODE In single-LED mode, the LEDx_1 pin indicates the link status while the LEDx_0 pin indicates the activity status, as shown in Figure 4-3. TABLE 4-3: SINGLE-LED MODE PIN DEFINITION LED Pin Pin State Pin LED Definition Link/Activity H OFF Link Off LEDx_1 LEDx_0 4.2.2 L ON Link On (any speed) H OFF No Activity Toggle Blinking Activity (RX,TX) TRI-COLOR DUAL-LED MODE In tri-color dual-LED mode, the link and activity status are indicated by the LEDx_1 pin for 1000BASE-T; by the LEDx_0 pin for 100BASE-TX; and by both LEDx_1 and LEDx_0 pins, working in conjunction, for 10BASE-T. This behavior is summarized in Figure 4-4. TABLE 4-4: TRI-COLOR DUAL-LED MODE PIN DEFINITION LED Pin (State) LED Pin (Definition) Link/Activity LEDx_1 LEDx_0 LEDx_1 LEDx_0 H H OFF OFF Link off L H ON OFF 1000Mbps Link / No Activity Toggle H Blinking OFF 1000Mbps Link / Activity (RX,TX) H L OFF ON 100Mbps Link / No Activity H Toggle OFF Blinking L L ON ON Toggle Toggle Blinking Blinking DS00002392C-page 28 100Mbps Link / Activity (RX,TX) 10Mbps Link / No Activity 10Mbps Link / Activity (RX,TX)  2017-2019 Microchip Technology Inc. KSZ9477S 4.3 4.3.1 Media Access Controller (MAC) MAC OPERATION The device strictly abides by IEEE 802.3 standards to maximize compatibility. Additionally, there is an added MAC filtering function to filter unicast packets. The MAC filtering function is useful in applications, such as VoIP, where restricting certain packets reduces congestion and thus improves performance. The transmit MAC takes data from the egress buffer and creates full Ethernet frames by adding the preamble and the start-of-frame delimiter ahead of the data, and generates the FCS that is appended to the end of the frame. It also sends flow control packets as needed. The receive MAC accepts data via the integrated PHY or via the SGMII/MII/RMII/RGMII interface. It decodes the data bytes, strips off the preamble and SFD of each frame. The destination and source addresses and VLAN tag are extracted for use in filtering and address/ID lookup, and the MAC also calculates the CRC of the received frame, which is compared to the FCS field. The MAC can discard frames that are the wrong size, that have an FCS error, or when the source MAC address matches the Switch MAC address. The receive MAC also implements the Wake on LAN (WoL) feature. This system power saving feature is described in detail in the Section 4.11, "Power Management". MIB statistics are collected in both receive and transmit directions. 4.3.2 INTER-PACKET GAP (IPG) If a frame is successfully transmitted, then the minimum 96-bit time for IPG is specified as being between two consecutive packets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is specified as being from carrier sense (CRS) to the next transmit packet. 4.3.3 BACK-OFF ALGORITHM The device implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After 16 consecutive collisions, the packet is dropped. 4.3.4 LATE COLLISION If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. 4.3.5 LEGAL PACKET SIZE On all ports, the device discards received packets smaller than 64 bytes (excluding VLAN tag, including FCS) or larger than the maximum size. The default maximum size is the IEEE standard of 1518 bytes, but the device can be configured to accept jumbo packets up to 9000 bytes. Jumbo packet traffic on multiple ports can stress switch resources and cause activation of flow control. 4.3.6 FLOW CONTROL The device supports standard MAC Control PAUSE (802.3x flow control) frames in both the transmit and receive directions for full-duplex connections. In the receive direction, if a PAUSE control frame is received on any port, the device will not transmit the next normal frame on that port until the timer, specified in the PAUSE control frame, expires. If another PAUSE frame is received before the current timer expires, the timer will then update with the new value in the second PAUSE frame. During this period (while it is flow controlled), only flow control packets from the device are transmitted. In the transmit direction, the device has intelligent and efficient ways to determine when to invoke flow control and send PAUSE frames. The flow control is based on availability of the system resources, including available buffers and available transmit queues. The device issues a PAUSE frame containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the device sends out another flow control frame with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. 4.3.7 HALF-DUPLEX BACK PRESSURE A half-duplex back pressure option (non-IEEE 802.3 standard) is also provided. The activation and deactivation conditions are the same as in full-duplex mode. If back pressure is required, the device sends preambles to defer the other stations' transmission (carrier sense deference).  2017-2019 Microchip Technology Inc. DS00002392C-page 29 KSZ9477S To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the device discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier sense type back pressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type back pressure is reactivated again until chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet reception. To ensure no packet loss in 10BASE-Te or 100BASE-TX half-duplex modes, the user must enable the following: • No excessive collision drop (Switch MAC Control 1 Register) • Back pressure (Port MAC Control 1 Register) 4.3.8 FLOW CONTROL AND BACK PRESSURE REGISTERS Table 4-5 provides a list of flow control and back pressure related registers. TABLE 4-5: FLOW CONTROL AND BACK PRESSURE REGISTERS Registers Description LED Configuration Strap Register LED configuration strap settings. (LED1_1 enables flow control and back pressure) Switch MAC Address 0 Register through Switch MAC Address 5 Register Switch's MAC address, used as source address of PAUSE control frames Switch MAC Control 0 Register “Aggressive back-off” enable Switch MAC Control 1 Register BP mode, “Fair mode” enable, “no excessive collision drop” enable Switch MAC Control 4 Register Pass PAUSE control frames Port Status Register Flow control enable (per port) PHY Auto-Negotiation Advertisement Register PHY - flow control advertisement (per port) Port MAC Control 1 Register Half-duplex back pressure enable (per port) Port Ingress Rate Limit Control Register Ingress rate limit flow control enable (per port) Port Control 0 Register Drop mode (per port) 4.3.9 BROADCAST STORM PROTECTION The device has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The device has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 5ms interval for 1000BASE-T, a 50ms interval for 100BASE-TX and a 500ms interval for 10BASE-Te. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in control registers. The default setting equates to a rate of 1%. 4.3.10 SELF-ADDRESS FILTERING Received packets can be filtered (dropped) if their source address matches the device's MAC address. This feature is useful for automatically terminating packets once they have traversed a ring network and returned to their source. It can be enabled on a per-port basis via the Switch Lookup Engine Control 1 Register and Port Control 2 Register. 4.4 4.4.1 Switch SWITCHING ENGINE A high-performance switching engine is used to move data to and from the MAC's packet buffers. It operates in store and forward mode, while an efficient switching mechanism reduces overall latency. The switching engine has a 256KByte internal frame buffer that is shared between all the ports. DS00002392C-page 30  2017-2019 Microchip Technology Inc. KSZ9477S For the majority of switch functions, all of the data ports are treated equally. However, a few functions such as IGMP snooping, 802.1X, forwarding invalid VLAN packets, etc., give special recognition to the host port. Any port (but most commonly port 6 or port 7) may be assigned as the host port by enabling tail tagging mode for that port. Only one port may be a host port. When a switch receives a non-error packet, it checks the packet's destination MAC address. If the address is known, the packet is forwarded to the output port that is associated with the destination MAC address. The following paragraphs describe the key functions of destination address lookup and source address learning. These processes may be combined with VLAN support and other features, which are described in the subsequent sub-sections. 4.4.2 ADDRESS LOOKUP Destination address lookup is performed in three separate internal address tables in the device: 1. 2. 3. Address Lookup (ALU) Table: 4K dynamic + static entries Static Address Table: 16 static entries Reserved Multicast Address Table: 8 pre-configured static entries 4.4.2.1 Address Lookup (ALU) Table The Address Lookup (ALU) Table stores MAC addresses and their associated information. This table holds both dynamic and static entries. Dynamic entries are created automatically in hardware, as described in Section 4.4.2.4, "Learning". Static entries are created by management software. This table is a 4-way associative memory, with 1K buckets, for a total of 4K entries. A hash function translates the received packet's MAC address (and optionally the FID) into a 10-bit index for accessing the table. At each bucket are four fully-associative address entries. All four entries are simultaneously compared to the MAC address (plus optional FID) for a possible match. Three options are available for the hashing function, as described in Table 4-6. If VLAN is enabled (802.1Q VLAN Enable bit in the Switch Lookup Engine Control 0 Register), the VLAN group (FID) is included in the hashing function along with the MAC address. If VLAN is not enabled the hashing function is applied to MAC address and the FID in the default VLAN (VID=1) which is 0. TABLE 4-6: ADDRESS LOOKUP TABLE HASHING OPTIONS HASH_OPTION (Switch Lookup Engine Control 0 Register) Description 01b (Default) A hash algorithm based on the CRC of the MAC address plus FID. The hash algorithm uses the CRC-CCITT polynomial. The input to the hash is reduced to a 16-bit CRC hash value. Bits [9:0] of the hash value plus (binary addition) 7-bit FID (zero extended on the left) are used as an index to the table. The CRC-CCITT polynomial is: X16+X12+X5+1. 10b An XOR algorithm based on 16 bits of the XOR of the triple-folded MAC address. Bits [9:0] of the XOR value plus 7-bit FID (left-extended) are used to index the table. 00b or 11b A direct algorithm. The 10 least significant bits of the MAC address plus 7 bit FID are used to index the table. 4.4.2.2 Static Address Table The 16-entry Static Address Table is typically used to hold multicast addresses, but is not limited to this. As with static entries in the ALU table, entries in the Static Address Table are created by management software. It serves the same function as static entries that are created in the ALU table, so its use is optional. 4.4.2.3 Reserved Multicast Address Table The Reserved Multicast Address Table holds 8 pre-configured address entries, as defined in Table 4-7. This table is an optional feature that is disabled at power-on. If desired, the forwarding ports may be modified.  2017-2019 Microchip Technology Inc. DS00002392C-page 31 KSZ9477S TABLE 4-7: Group RESERVED MULTICAST ADDRESS TABLE Address MAC Group Address Function Default PORT FORWARD Value Default Forwarding Action (defines forwarding port: P7...P1) 0 (01-80-C2-00)-00-00 Bridge Group Data 100_0000 Forward only to the highest numbered port (default host port) 1 (01-80-C2-00)-00-01 MAC Control Frame 000_0000 (typically flow control) Drop MAC flow control 2 (01-80-C2-00)-00-03 802.1X Access Control 100_0000 Forward to highest numbered port 3 (01-80-C2-00)-00-10 Bridge Management 111_1111 Flood to all ports 4 (01-80-C2-00)-00-20 GMRP 011_1111 Flood to all ports except highest numbered port 5 (01-80-C2-00)-00-21 GVRP 011_1111 Flood to all ports except highest numbered port 6 (01-80-C2-00)-00-02, (01-80-C2-00)-00-04 – (01-80-C2-00)-00-0F 100_0000 Forward to highest numbered port 7 (01-80-C2-00)-00-11 (01-80-C2-00)-00-1F, (01-80-C2-00)-00-22 (01-80-C2-00)-00-2F 011_1111 Flood to all ports except highest numbered port If a match is found in one of the tables, then the destination port is read from that table entry. If a match is found in more than one table, static entries will take priority over dynamic entries. 4.4.2.4 Learning The internal lookup engine updates the ALU table with a new dynamic entry if the following conditions are met: • The received packet's source address (SA) does not exist in the lookup table. • The received packet has no errors, and the packet size is of legal length. • The received packet has a unicast SA. The lookup engine inserts the qualified SA into the table, along with the port number and age count. If all four table entries are valid, the oldest of the (up to four) dynamic entries may be deleted to make room for the new entry. Static entries are never deleted by the learning process. If all four entries are static entries, the address is not learned but an interrupt is generated and the table index number is made available to the interrupt service routine. 4.4.2.5 Migration The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the ALU table accordingly. Migration happens when the following conditions are met: • The received packet's SA is in the table but the associated source port information is different. • The received packet has no receiving errors, and the packet size is of legal length. The lookup engine updates the existing record in the table with the new source port information. 4.4.2.6 Aging The lookup engine updates the age count information of a dynamic record in the ALU table whenever the corresponding SA appears. The age count is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record from the table. The lookup engine constantly performs the aging process and continuously removes aging records. The aging period is about 300 seconds (±75 seconds) and can be configured longer or shorter (1 second to 30 minutes). This feature can be enabled or disabled. Static entries are exempt from the aging process. DS00002392C-page 32  2017-2019 Microchip Technology Inc. KSZ9477S 4.4.2.7 Forwarding The device forwards packets using the algorithm that is depicted in Figure 4-3. Figure 4-3 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1" (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes. The ACL process works in parallel with the flow outlined above. The authentication and ACL processes have the highest priority in the forwarding process, and the ACL result may override the result of the above flow. The output of the ACL process is the final “port-to-forward 2" (PTF2) destination port(s). The device will not forward the following packets: • Error packets: These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal size packet errors. • MAC Control PAUSE frames: The device intercepts these packets and performs full duplex flow control accordingly. • “Local” packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as “local”. • In-Band Management packets. FIGURE 4-3: PACKET FORWARDING PROCESS FLOWCHART Start PTF1 no PTF1=NULL VLAN ID Valid? - Search VLAN table - Ingress VLAN filtering -Discard NPVID check Spanning Tree Process - Check receiving port s receive enable bit - Check destination port s transmit enable bit - Check whether packets are special (BPDU) yes Get PTF1 from Static Array found Search Static Array Search based on DA or DA+FID IGMP / MLD Process - IGMP / MLD packets are forwarded to Host port - Process does not apply to packets received at Host port Port Mirror Process - not found Get PTF1 from Address Table found Search Address Look-up Table Search based on DA+FID RX Mirror TX Mirror RX or TX Mirror RX and TX Mirror not found Get PTF1 from VLAN Table Port Authentication & ACL PTF1 PTF2  2017-2019 Microchip Technology Inc. DS00002392C-page 33 KSZ9477S 4.4.2.8 Lookup Engine Registers Table 4-8 provides a list of lookup engine related registers. TABLE 4-8: LOOKUP ENGINE REGISTERS Registers Description Global Interrupt Status Register, Global Interrupt Mask Register Top level LUE interrupt Switch Lookup Engine Control 0 Register, Switch Lookup Engine Control 1 Register, Switch Lookup Engine Control 2 Register, Switch Lookup Engine Control 3 Register Misc. Address Lookup Table Interrupt Register, Address Lookup Table Mask Register Low level LUE interrupts Address Lookup Table Entry Index 0 Register, Address Lookup Table Entry Index 1 Register Access failure address/index ALU Table Index 0 Register, ALU Table Index 1 Register, ALU Table Access Control Register, Static Address and Reserved Multicast Table Control Register, ALU / Static Address Table Entry 1 Register, ALU / Static Address / Reserved Multicast Table Entry 2 Register, ALU / Static Address Table Entry 3 Register, ALU / Static Address Table Entry 4 Register Address table access registers 4.4.3 IEEE 802.1Q VLAN Virtual LAN is a means of segregating a physical network into multiple virtual networks whereby traffic may be confined to specific subsets of the greater network. IEEE 802.1Q defines a VLAN protocol using a 4-byte tag that is added to the Ethernet frame header. The device supports port-based and tag-based VLANs, including tagging, un-tagging, forwarding and filtering. 4.4.3.1 Non-Tag Port-Based VLAN The simplest VLAN method establishes forwarding restrictions on a port-by-port basis without using VLAN tags. There is a register for each ingress port that is used to specify the allowed forwarding ports. An incoming packet is restricted from being forwarded to any egress port that is disallowed for that ingress port. The settings are made in the Port Control 1 Register. This function is always enabled; it is not enabled and disabled by the 802.1Q VLAN Enable bit in the Switch Lookup Engine Control 0 Register. The default setting is to allow all ingress-to-egress port paths. 4.4.3.2 Tag-Based VLAN When 802.1Q VLAN is enabled, an internal VLAN Table with 4k entries is used to a store port membership list, VLAN group ID (FID) and additional information relating to each VLAN. This table must be set up by an administrator prior to enabling 802.1Q VLAN. Enabling is done by setting the 802.1Q VLAN Enable bit in the Switch Lookup Engine Control 0 Register. In 802.1Q VLAN mode, the lookup process starts with VLAN Table lookup, using the tag's VID as the address. The first step is to determine whether the VID is valid. If the VID is not valid, the packet is dropped and its address is not learned. Alternatively, unknown VID packets may be forwarded to pre-defined ports or to the host port. If the VID is valid, the FID is retrieved for further lookup. The FID + Destination Address (hashed(DA) + FID) are used to determine the destination port. The FID + Source Address (hashed(SA) + FID) are used for address learning (see Table 4-10 and Table 4-11). DS00002392C-page 34  2017-2019 Microchip Technology Inc. KSZ9477S The hashed(DA) + FID are hashed and used for forwarding lookup in the Address Lookup and Static Address Tables. For a successful address table lookup, the FID fields must also match. If the match fails, the packet is broadcast to all the VLAN port members defined in the VLAN Table entry. If there is a match and egress VLAN filtering is enabled, the packet is forwarded to those ports that are in both the address table port forwarding list and the VLAN table port membership list. A similar address table lookup is performed using the hashed(SA) + FID. If the lookup fails, the FID and SA are learned. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID (Port Default Tag 0 Register and Port Default Tag 1 Register) is used for lookup. Table 4-9 details the forwarding and discarding actions that are taken for the various VLAN scenarios. The first entry in the table is explained by the fact that VLAN Table lookup is enabled even when 802.1Q VLAN is not enabled. Notice that in the Port Default Tag 0 Register and Port Default Tag 1 Register, the port default VID is 1 for each port. Correspondingly, the VLAN port membership list in the VLAN Table entry for VID=1 is pre-configured at power-on to all ones. This provides the standard Ethernet switch behavior of broadcasting all packets with unknown destination address. If the VLAN table entry # 1 is changed, or if the port default VID is changed, this may affect the forwarding action for “unknown packets” even when VLAN is not enabled. It should also be noted that the default values of the Egress VLAN Filtering bits are zero. These bits are zero only for backwards compatibility with previous “KSZ” switches. The resulting switch behavior, in the event of a successful VLAN and ALU lookups, is to forward the packet to the ports in the address table port forwarding list, without regard to the VLAN port membership list. It is suggested that the Egress VLAN Filtering bits be set to one so that the VLAN port membership list from the VLAN Table will be used to qualify the forwarding determined from the address lookup. TABLE 4-9: VLAN Enable (Note 4-1) VLAN FORWARDING VLAN Match/ Valid (Note 4-2) Forward Option (Note 4-3) Egress VLAN Filtering Unknown VID Forward Drop Invalid VID ALU Match/ Valid (Note 4-4) (Note 4-5) (Note 4-6) (Note 4-7) Action 0 X X X X X No Forward to port membership list of default VID in LAN table 0 X X X X X Yes Forward to Address Lookup port forwarding list 1 No X X 0 0 X Forward to host port 1 No X X 0 (def) 1 (def) X Discard 1 No X X 1 X X Forward to Unknown VID packet forward port list 1 Yes 0 X X X No Broadcast: Forward to VLAN table port membership list (PORT FORWARD) Multicast: Forward to Unknown Multicast ports if UM is enabled. Else, forward to VLAN table port membership list. Unicast: Forward to Unknown Unicast ports if UU is enabled. Else forward to VLAN table port membership list. 1 Yes 0 0 (def) X X Yes Forward to address table lookup port forwarding list 1 Yes 0 1 X X Yes Forward to address table lookup port forwarding list & VLAN table port membership list (bitwise AND) 1 Yes 1 X X X Yes Forward to VLAN table port membership list  2017-2019 Microchip Technology Inc. DS00002392C-page 35 KSZ9477S Note: “(def)” indicates the default power-up value. Note 4-1 VLAN Enable is bit 7 in the Switch Lookup Engine Control 0 Register Note 4-2 VLAN Match/Valid indicates when the VLAN Table entry is valid Note 4-3 Forward Option is a bit in the VLAN Table Entry 0 Register Note 4-4 Egress VLAN Filtering are bits 5 and 4 in the Switch Lookup Engine Control 2 Register Note 4-5 Unknown VID Forwarding is in the Unknown VLAN ID Control Register Note 4-6 Drop Invalid VID is bit 6 in the Switch Lookup Engine Control 0 Register Note 4-7 ALU Match/Valid indicates when the Address Lookup is a success Table 4-10 describes in more detail the address lookup process that follows the VLAN Table lookup. Lookup occurs in both the Address Lookup Table and the Static Address Table simultaneously, and the resulting action depends on the results of the two lookups. TABLE 4-10: HASHED(DA) + FID LOOKUP IN VLAN MODE DA Found Use FID Flag? in Static (Static MAC Table) MAC Table? FID Match? DA+FID Found in ALU Table? Action No Don’t Care Don’t Care No Lookup has failed. Broadcast to the membership ports defined in the VLAN Table No Don’t Care Don’t Care Yes Send to the destination port defined in the Address Lookup (ALU) Table Yes 0 Don’t Care Don’t Care Yes 1 No No Lookup has failed. Broadcast to the membership ports defined in the VLAN Table. Yes 1 No Yes Send to the destination port defined in the Address Lookup (ALU) Table Yes 1 Yes Don’t Care Send to the destination port(s) defined in the Static Address Table Send to the destination port(s) defined in the Static Address Table A source address (SA) lookup is also performed in the Address Lookup Table. SA lookup also performs SA filtering and MAC priority when the address is hit. Table 4-11 describes how learning is performed in the Address Lookup Table when a successful VLAN table lookup has been done and the no matching static entry is found in the Address Lookup Table or the Static Address Table. TABLE 4-11: HASHED(SA) + FID LOOKUP IN VLAN MODE FID + SA Found in Address Lookup (ALU) Table? DS00002392C-page 36 Action No Learn and add FID + SA to the Address Lookup (ALU) Table Yes If the static bit is 0, the time stamp and the egress port map is updated. If the static bit is 1, then nothing is done.  2017-2019 Microchip Technology Inc. KSZ9477S 4.4.3.2.1 Tag Insertion and Removal Tag insertion is enabled on all ports when the VLAN feature is enabled. At the ingress port, untagged packets are tagged with the ingress port's default tag. The default tag is separately programmable for each port. The switch does not add tags to already tagged packets unless double tagging is enabled. At the egress port, tagged packets will have their 802.1Q VLAN tags removed if un-tagging is enabled in the VLAN table entry. Untagged packets will not be modified if 802.1Q is enabled. 4.4.3.2.2 Double Tagging The switch supports double tagging, also known as Q-in-Q or VLAN stacking. This feature can be used for service providers to append a second VLAN tag in addition to a first VLAN tag applied by the customer. VLAN support can be enabled either with or without double tagging. When double tagging is enabled, the outer tag is recognized and is used for VLAN and address lookup instead of the inner tag. The outer tag precedes the inner tag in the frame header: the outer tag is located immediately after the source address, and contains a different Tag Protocol Identifier (TPID) value than the inner tag. Additional controls are available for full control of the VLAN function. Some of these features can be enabled on a perport basis, while others are global: • • • • • • • • • Ingress VLAN Filtering: Discard packet if VID port membership in VLAN table does not include the ingress port. Discard non PVID Packet: Discard packet if VID does not match the ingress port default VID. Discard un-tagged Packet: Discard any received packet without a tag. Drop tag: Drops the packet if it is VLAN tagged. Unknown VID Forward: Forward to a fixed set of ports if VLAN lookup fails. Drop unknown VID: Additional options for unknown VID packets: discard or forward to the host port. Null VID Replacement: Replace a null VID with the ingress port default VID. PVID Replacement: Replace a non-null VID with the ingress port default VID. Double Tag Mcast Trap: In double tag mode, trap all reserved multicast packets and forward to the host port. 4.4.3.3 VLAN Registers Table 4-12 provides a list of VLAN related registers. TABLE 4-12: VLAN REGISTERS Registers Description Switch Operation Register Double tag enable Switch Lookup Engine Control 0 Register VLAN enable; Drop invalid VID frames Switch Lookup Engine Control 2 Register Trap double tagged MC frames; Dynamic & status egress VLAN filtering Unknown VLAN ID Control Register Forward unknown VID Switch MAC Control 2 Register Null VID replacement with PVID at egress VLAN Table Entry 0 Register, VLAN Table Entry 1 Register, VLAN Table Entry 2 Register, VLAN Table Index Register, VLAN Table Access Control Register Read/write access to the VLAN table Port Default Tag 0 Register, Port Default Tag 1 Register Port default tag Port Ingress MAC Control Register Drop non-VLAN frames; Tag drop Port Transmit Queue PVID Register PVID replacement at egress Port Control 2 Register VLAN table lookup for VID=0; Ingress VLAN filtering; PVID mismatch discard  2017-2019 Microchip Technology Inc. DS00002392C-page 37 KSZ9477S 4.4.4 QUALITY-OF-SERVICE (QOS) PRIORITY SUPPORT The device provides quality-of-service (QoS) for applications such as VoIP. There are multiple methods for assigning priority to ingress packets. Depending on the packet prioritization method, the packet priority levels are mapped to the egress queues for each port. Each port can be configured for 1, 2, and 4 egress queues, which are prioritized. The default is 1 queue per port. When configured for 4 priority queues, Queue 3 is the highest priority queue and Queue 0 is the lowest priority. Likewise, for a 2-queue configuration, Queue 1 is the highest priority queue. If a port is not configured as 2 or 4 queues, then high priority and low priority packets have equal priority in the single transmit queue. There is an additional option for every port to select either to always deliver packets from the highest priority queue first, or use weighted round robin queuing amongst the multiple queues. This is described later in Section 4.4.13, "Scheduling and Rate Limiting". 4.4.4.1 Port-Based Priority With port-based priority, each ingress port is individually classified as a specific priority level. All packets received at the high-priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split into 2 or 4 queues. 4.4.4.2 IEEE 802.1p-Based Priority For IEEE 802.1p-based priority, the device examines the ingress packets to determine whether they are tagged. If tagged, the 3-bit PCP priority field in the VLAN tag is retrieved and used to look up the “priority mapping” value. The “priority mapping” value is programmable. Figure 4-4 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. FIGURE 4-4: 4.4.4.3 802.P PRIORITY FIELD FORMAT IEEE 802.1p Priority Field Re-Mapping This is a QoS feature that allows the device to set the “User Priority Ceiling” at any ingress port. If the ingress packet's priority field has a higher priority value than the default tag's priority field of the ingress port, the packet's priority field is replaced with the default tag's priority field. 4.4.4.4 DiffServ (DSCP) Priority (IP) DiffServ-based priority from the DSCP field in the IP header can be used to determine packet priority. The 6-bit DSCP value is used as an index to a set of registers which translate the 6-bit DSCP value to a 2-bit value that specifies one of the 4 (or 2) queues. These registers are fully programmable. 4.4.4.5 ACL Priority The Access Control List (ACL) Filtering feature can also be used to assign priority to received packets. This is discussed in Section 4.4.18, "Access Control List (ACL) Filtering". DS00002392C-page 38  2017-2019 Microchip Technology Inc. KSZ9477S 4.4.5 4.4.5.1 TRAFFIC CONDITIONING & POLICING Two Rate Three Color Marker The Two Rate Three Color Marker meters an IP packet stream and marks its packets green, yellow, or red. A packet is marked red if it exceeds the Peak Information Rate (PIR). Otherwise, it is marked either yellow or green depending on whether it exceeds or doesn't exceed the Committed Information Rate (CIR). The Meter operates in one of two modes. In the Color-Blind mode, the Meter assumes that the packet stream is uncolored. In the Color-Aware mode, the Meter assumes that some preceding entity has pre-colored the incoming packet stream so that each packet is green, yellow, or red. The Marker (re)colors an IP packet according to the results of the Meter. 4.4.5.2 Weighted Random Early Detection (WRED) The WRED feature monitors the average queue size of packet memory and ingress queue size of each traffic class, and drops packets based on memory and queue utilization. If the buffers are almost empty, all incoming traffic is accepted. As the buffer utilization increases, the probability for dropping an incoming packet also increases. WRED is intended to avoid the problem of global synchronization. Global synchronization can occur when a switch becomes congested and begins dropping incoming packets all at once. For TCP streams, packet drops invoke the TCP congestion control mechanism, which reduce the transmission rate until there are no more packet drops. If there are many TCP streams and their congestion control mechanisms act in unison, this can cause an undesirable oscillation in traffic rates. By selectively dropping some packets early rather than waiting until the buffer is full, WRED avoids dropping large numbers of packets at once and minimizes the chances of global synchronization. The packet drop probability is based on the minimum threshold, maximum threshold, and a probability multiplier. When the average queue depth is above the minimum threshold, packets start getting dropped. The rate of packet drop increases linearly as the average queue size increases until the average queue size reaches the maximum threshold. The probability multiplier is the fraction of packets dropped when the average queue depth is at the maximum threshold. When the average queue size is above the maximum threshold, all packets are dropped. AVB traffic streams (SR streams) can be exempted from WRED policing. 4.4.6 SPANNING TREE SUPPORT To support spanning tree, one port is the designated port for the host processor, which is defined as the port for which tail tagging is enabled. Each of the other ports can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register bits. Table 4-13 shows the setting and software actions taken for each of the five spanning tree states. TABLE 4-13: Disable State SPANNING TREE STATES Port Setting The port should not forward or transmit enable = 0 receive any packets. receive enable = 0 Learning is disabled. learning disable = 1 Blocking State Port Setting Only packets to the processor transmit enable = 0 are forwarded. receive enable = 0 Learning is disabled. learning disable = 1  2017-2019 Microchip Technology Inc. Software Action The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the “Static MAC Table” with “overriding bit” set) and the processor should discard those packets. Address learning is disabled on the port in this state. Software Action The processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. DS00002392C-page 39 KSZ9477S TABLE 4-13: SPANNING TREE STATES (CONTINUED) Listening State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is disabled. transmit enable = 0 receive enable = 0 learning disable = 1 The processor should program the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. Address learning is disabled on the port in this state. Learning State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is enabled. transmit enable = 0 receive enable = 0 learning disable = 0 The processor should program the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. Address learning is enabled on the port in this state. Forwarding State Port Setting Software Action Packets are forwarded and received normally. Learning is enabled. transmit enable = 1 receive enable = 1 learning disable = 0 The processor programs the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. Address learning is enabled on the port in this state. 4.4.7 RAPID SPANNING TREE SUPPORT There are three operational states assigned to each port for the Rapid Spanning Tree Protocol (RSTP): 1. 2. 3. Discarding State Learning State Forwarding State 4.4.7.1 Discarding State Discarding ports do not participate in the active topology and do not learn MAC addresses. • Discarding state: the state includes three states of the disable, blocking and listening of STP. • Port setting: transmit enable = “0”, receive enable = “0”, learning disable = “1”. • Software action: The host processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those packets. When the port's learning capability (learning disable = '1') is disabled, port related entries in the ALU table and static MAC table can be rapidly flushed. 4.4.7.2 Learning State Ports in “learning state” learn MAC addresses, but do not forward user traffic. • Learning State: Only packets to and from the host processor are forwarded. Learning is enabled. • Port setting for Learning State: transmit enable = “0”, receive enable = “0”, learning disable = “0”. • Software action: The processor should program the Static Address Table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state (see Section 4.4.9, "Tail Tagging Mode" for details). Address learning is enabled on the port in this state. 4.4.7.3 Forwarding State Ports in “forwarding states” fully participate in both data forwarding and MAC learning. • Forwarding state: Packets are forwarded and received normally. Learning is enabled. • Port setting: transmit enable = “1”, receive enable = “1”, learning disable = “0”. DS00002392C-page 40  2017-2019 Microchip Technology Inc. KSZ9477S • Software action: The host processor should program the Static Address Table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state (see Section 4.4.9, "Tail Tagging Mode" for details). Address learning is enabled on the port in this state. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP configuration BPDUs with the exception of a type field set to “version 2" for RSTP and “version 0" for STP, and a flag field carrying additional information. 4.4.8 MULTIPLE SPANNING TREE SUPPORT Multiple Spanning Tree Protocol (MSTP) is an extension of RSTP that allows different VLANs to have different spanning tree configurations. The VLAN Table, Address Lookup Table and Static Address Table all contain a 3-bit field which can be used to specify one of eight spanning trees. Each port contains state registers for specifying unique states for each of the spanning trees. 4.4.9 TAIL TAGGING MODE Tail tagging is a method to communicate ingress and egress port information between the host processor and the switch. It is useful for spanning tree protocol, IGMP/MLD snooping, IEEE 1588, and other applications. As shown in Figure 45, the tail tag is inserted at the end of the packet, between the payload and the 4-byte CRC / FCS.. FIGURE 4-5: B Y TE S TAIL TAG FRAME FORMAT 6 6 (4 ) 2 DEST ADDRESS SOURCE ADDRESS 8 0 2 .1 Q TA G E TY P E or LE NGTH 4 6 (4 2 ) - 1 5 0 0 PAYLOAD 2 (F ro m H o s t) 1 (T o H o s t) T A IL TAG 4 FC S When the switch forwards a received packet to the host port, one tail tagging byte is added to the packet by the switch to indicate to the host processor the port that the packet was received on. The format is shown in Table 4-14. TABLE 4-14: RECEIVE TAIL TAG FORMAT (FROM SWITCH TO HOST) Bits Description 7 PTP Message Indication 0 = Is not a PTP message. A 4-byte receive timestamp has not been added. 1 = Is a PTP message. A 4-byte timestamp has been added before the tail tag. 6:3 Reserved 2:0 Received Port 000 = Packet received at Port 1 001 = Packet received at Port 2 010 = Packet received at Port 3 011 = Packet received at Port 4 100 = Packet received at Port 5 101 = Packet received at Port 6 110 = Packet received at Port 7 In the opposite direction, the host processor must add two tail tag bytes to each packet that it sends to the switch to indicate the intended egress ports. When multiple priority queues are enabled, the tail tag is also used to indicate the priority queue. The format is shown in Table 4-15. This tail tag is removed by the switch before the packet leaves the switch. If the Lookup bit (bit 10) is set, packet forwarding follows the standard forwarding process, and bits [9:0] are ignored. When the Lookup bit is not set, bits [8:0] determine the forwarding ports and priority queue, while the Override bit (bit 9) determines whether port blocking is overridden. Tail tagging applies only to the host port, never to any other ports of the switch.  2017-2019 Microchip Technology Inc. DS00002392C-page 41 KSZ9477S TABLE 4-15: TRANSMIT TAIL TAG FORMAT (FROM HOST TO SWITCH) Bits Description 15:11 Reserved 10 Lookup 0 = Port forwarding is determined by tail tag bits [9:0] below. 1 = Tail tag bits [9:0] are ignored and port forwarding is determined by the standard switch forwarding process (address lookup, VLAN, etc.) 9 Port Blocking Override When set, packets will be sent from the specified port(s) regardless, and any port blocking (see Port Transmit Enable in Port MSTP State Register) is ignored. 8:7 Egress priority (0 to 3) 6 Forward to Port 7 5 Forward to Port 6 4 Forward to Port 5 3 Forward to Port 4 2 Forward to Port 3 1 Forward to Port 2 0 Forward to Port 1 By default, tail tagging is disabled. To enable it, set the Tail Tag Enable bit in one of the Port Operation Control 0 Register at address 0xN020 for port “N”. When this bit is set for one port, that port is referred to as the “host” port. Do not set the Tail Tag Enable bit for more than one port. When IEEE 1588 Precision Time Protocol (PTP) Mode is enabled, the format of the tail tag changes. Specifically, a four byte timestamp field is added between the payload and the tail tag as shown in Figure 4-6. PTP mode is enabled by setting bit 6 in Global PTP Message Config 1 Register. Note that the KSZ8441/62/63 use a different method for passing the timestamp between the switch and host.. FIGURE 4-6: BYTES PTP MODE TAIL TAG FRAME FORMAT 6 6 (4) 2 46 (42) - 1500 4 2 (From Host) 1 (To Host) DEST ADDRESS SOURCE ADDRESS 802.1Q TAG ETYPE or LENGTH PAYLOAD TIME STAMP TAIL TAG 4 FCS In the switch-to-host direction, the switch sets the PTP Message Indication bit in the tail tag to indicate when the fourbyte receive timestamp is present. When PTP Message Indication is not set, the four-byte timestamp field is not present. It is therefore essential for the host processor to read bit 7 of each tail tag in order to know the packet format. The 32-bit timestamp consists of 2 bits for “seconds” and 30 bits for “nanoseconds”. The timestamp format is (((second & 3)