KSZ9692PB/KSZ9692XPB
Integrated Gigabit Networking and Communications Controller
Highlights
• ARM® 922T High-Performance Processor Core
- 250 MHz ARM 922T RISC processor core
- 8KB I-cache and 8KB D-cache
- Configurable Memory Management Unit
(MMU) for Linux and WinCE
• Memory Controller
- 8/16-bit external bus interface for FLASH,
ROM, SRAM, and external I/O
- NAND FLASH controller with boot option
- 200MHz
- 32-bit DDR controller
- Two JEDEC Specification JESD82-1-compliant differential clock drivers for a glueless
DDR interface solution
• Ethernet Interfaces
- Two Gb (10/100/1000 Mbps) MACs
- MII or RGMII interface
- Fully compliant with IEEE 802.3 Ethernet
standards
• PCI Interface
- Version PCI 2.3
- 32-bit 33/66 MHz
- Integrated PCI Arbiter supports three external
masters for KSZ9692PB and one external
master for KSZ9692XPB
- Configurable as Host bridge or Guest device
- Glueless Support for mini-PCI or CardBus
devices
• Dual High-Speed USB 2.0 Interfaces
- Two USB2.0 ports with integrated PHY
- Can be configured as 2-port host, or host +
device
• SDIO/SD Host Controller (for KSZ9692PB only)
- Meets SD Host Controller Standard Specification Version 1.0
- Meets SDIO card specification Version 1.0
• DMA Controllers
- Dedicated DMA channels for PCI, USB,
SDIO and Ethernet ports.
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• Peripherals
- Four high-speed UART ports up to 5 Mbps
- Two programmable 32-bit timers with watchdog timer capability
- Interrupt Controller
- Twenty GPIO ports
- One shared SPI/I2C interface
- One I2S port
• Debugging
- ARM9 JTAG debug interface
- JTAG Boundary Scan Support
• Power Management
- CPU and system clock speed step-down
options
- Ethernet port Wake-on-LAN
- DDR and PCI power down
• Operating Voltage
- 1.3V power for core
- 3.3V power for I/O
- 2.5V or 2.6V power for DDR memory interface
• Reference Hardware and Software Evaluation Kit
- Hardware Evaluation Kit
- Software Evaluation Kit includes WinCE BSP,
Open WRT BSP, Linux based SOHO Router
packages
Applications
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Enhanced residential gateways
High-end printer servers
USB device servers
IP-based multimedia systems
Voice-over-Internet Protocol (VoIP) systems
Set-top box
Industrial control
Wireless Access Points or Mesh Nodes
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TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
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1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Functional Overview ....................................................................................................................................................................... 6
3.0 Pin Description and Configuration ................................................................................................................................................ 24
4.0 Operational Characteristics ........................................................................................................................................................... 37
5.0 Timing specifications ..................................................................................................................................................................... 39
6.0 Package Information ..................................................................................................................................................................... 43
Appendix A: Data Sheet Revision History ........................................................................................................................................... 44
The Microchip Web Site ...................................................................................................................................................................... 45
Customer Change Notification Service ............................................................................................................................................... 45
Customer Support ............................................................................................................................................................................... 45
Product Identification System ............................................................................................................................................................. 46
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1.0
INTRODUCTION
1.1
General Description
The KSZ9692PB/KSZ9692XPB is a highly-integrated System-on-Chip (SoC) containing an ARM® 922T 32-bit processor and a rich set of peripherals to address the cost-sensitive, high-performance needs of a wide variety of high-bandwidth networking and communications applications.
1.2
Block Diagram
FIGURE 1-1:
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KSZ9692PB/KSZ9692XPB BLOCK DIAGRAM
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KSZ9692PB/KSZ9692XPB
1.3
System Level Applications
FIGURE 1-2:
PERIPHERAL OPTIONS AND EXAMPLES
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2.0
FUNCTIONAL OVERVIEW
The KSZ9692PB/KSZ9692XPB is a highly-integrated embedded application controller that is designed to provide a single-chip solution for a wide range of applications that require high-speed networking, multiple I/O controllers and interface to standard peripherals. It features a powerful 32-bit ARM® RISC processor, DDR memory controller, FLASH/
ROM/SRAM/External I/O interface, NAND memory controller, two Gb Ethernet MACs, two USB 2.0 ports, PCI 2.3 bus
interface, SDIO interface (for KSZ9692PB only), and a large number of standard peripherals including UARTs, I2C, I2S,
SPI, MIB counters, Station Manager, timers, interrupt controller and GPIOs.
FIGURE 2-1:
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KSZ9692PB FUNCTIONAL BLOCK DIAGRAM
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KSZ9692PB/KSZ9692XPB
FIGURE 2-2:
KSZ9692XPB FUNCTIONAL BLOCK DIAGRAM
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2.1
ARM® High-Performance Processor
The KSZ9692PB/KSZ9692XPB is built around the 16/32-bit ARM922T RISC processor designed by Advanced RISC
Machines. The ARM922T is a scalable, high-performance processor that was developed for highly integrated SoC applications. Its simple, elegant, and fully static design is particularly suited to cost-effective and power-sensitive embedded
systems. It also offers a separate 8KB D-cache and 8KB I-cache that reduces memory access latency.16-bit thumb
instruction sets are supported to minimize memory footprint. The ARM processor core can be programmed to maximum
of 250 MHz for highest possible performance.
The Advanced Microprocessor Bus Architecture/Advanced High Performance Bus (AMBA AHB) is a 32-bit wide ARM
system bus to which is connected the processor, the register ports of the DDR memory controller, the FLASH/ROM/
SRAM/External I/O controller, the NAND memory controller, the Ethernet MACs, the PCI bridge, the USB ports and the
SDIO controller (for KSZ9692PB only). The ARM processor is the master of AHB and responsible for configuring the
operational characteristics of each AHB device via their individual register port. The AHB is programmable up to
166MHz for maximum system bus performance. AHB interfaces to devices are shown in functional block diagram.
Also connected to AHB is ARM Advanced Peripheral Bus or APB bridge which is attached the standard peripherals.
The APB Bridge transparently converts the AHB accesses into slower APB accesses. The ARM processor is the master
of APB bridge and responsible for configuring the operational characteristics and transfer of data for each APB attached
peripheral. APB interfaces to standard peripherals are shown in the functional block diagrams on page 8 and 9.
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250MHz ARM922T RISC processor core
166MHz AMBA Bus 2.0
16-bit thumb instruction sets
8KB D-cache and 8KB I-cache
Supports Little-Endian mode
Configurable MMU
Power saving options include clock down of both processor core and AMBA AHB
2.2
FLASH/ROM/SRAM Memory and External I/O Interface
The KSZ9692PB/KSZ9692XPB memory controller provides glueless interface for static memory, i.e., ROM, SRAM, and
NOR Flash and three banks of external I/O. NOR Flash bank0 can be configured by power-up strap option to operate
as boot bank from a 8 or 16 bit device.
• Glueless connection to two banks of FLASH/ROM/SRAM memory with programmable 8 or 16 bit data width and
programmable access timing
• Support for AMD/Intel like Flash
• Automatic address line mapping for 8 or 16-bit accesses on Flash, ROM, and SRAM interfaces
• Supports three external I/O banks with programmable 8 or 16 bit data width and programmable access timing
• Total 64MB address space for two banks of
• FLASH/ROM/SRAM and three banks of external I/O
The memory interface for the static memory has a special automatic address mapping feature. This allows the designer
to connect address bit 0 on the memory to ADDR[0] on the KSZ9692PB/KSZ9692XPB and address bit 1 on the memory
to ADDR[1] on the KSZ9692PB/KSZ9692XPB, regardless of whether the designer is trying to achieve half word or byte
addressing. The KSZ9692PB/KSZ9692XPB memory controller performs the address mapping internally. This gives the
designer the flexibility to use 8 or 16 bit data width devices interchangeably on the same PCB (see FIGURE 2-2:
KSZ9692XPB Functional Block Diagram on page 7). For external I/O, however, the designer still needs to resolve the
address mapping (see FIGURE 2-4: External I/O Interface Examples on page 10).
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FIGURE 2-3:
STATIC MEMORY INTERFACE EXAMPLES
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FIGURE 2-4:
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EXTERNAL I/O INTERFACE EXAMPLES
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KSZ9692PB/KSZ9692XPB
2.3
NAND Flash Memory Interface
The KSZ9692PB/KSZ9692XPB NAND controller provides interface to external NAND Flash memory. A total of two
banks are supported. NAND Flash bank0 can be configured by power-up strap option to operate as boot bank. Both
NAND Flash banks share data bus with FLASH/ROM/SRAM memory banks.
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Glueless connection to two banks with programmable 8 or 16 bit data width and programmable access timing
Hardware ECC not supported
Small page size 512 + 16 bytes
Large page size 2048 + 64 bytes
Large and small block size
Boot option with automatic page crossing where pages are automatically opened sequentially by hardware
Boot option with two 8-bit device in parallel to form a 16-bit bank
Boot option with bank0 and bank1 as active banks in cascade
Support for following device densities:
- 64Mbit
- 128Mbit
- 256Mbit
- 512Mbit
- 1Gbit
- 2Gbit
- 4Gbit
- 8Gbit
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The following figures illustrate examples of NAND Flash bank configuration:
FIGURE 2-5:
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8-BIT NAND INTERFACE EXAMPLES
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KSZ9692PB/KSZ9692XPB
FIGURE 2-6:
2.4
16-BIT NAND INTERFACE EXAMPLES
DDR Controller
The KSZ9692PB/KSZ9692XPB DDR memory controller provides interface for accessing external Double Data Rate
Synchronous DRAM. In addition, the KSZ9692PB/KSZ9692XPB provides two integrated DDR differential clock drivers
for a complete glueless DDR interface solution.
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Up to 200 MHz clock frequency (400 MHz data rate)
Supports one 32-bit data width bank (16-bit optional)
Up to 128 MB of addressable space is available with 12 columns and 14 row address lines
Supports all DDR device densities up to 1Gb
Supports all DDR device data width x8 and x16
Configurable DDR RAS and CAS timing parameters
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• Two integrated JEDEC Specification JESD82-1 compliant differential clock drivers for a glueless DDR interface
solution
• JEDEC Specification SSTL_2 I/Os
A dedicated internal PLL provides clocking to the DDR memory controller and the two differential clock drivers. This PLL
is programmable up to 200 MHz and independent of AHB and ARM® processor core clocks.
Figure 2-7 and Figure 2-8 illustrate examples of bank configurations.
FIGURE 2-7:
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TWO 16-BIT DDR MEMORY DEVICE INTERFACE EXAMPLE
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KSZ9692PB/KSZ9692XPB
FIGURE 2-8:
FOUR 8-BIT DDR MEMORY DEVICES INTERFACE EXAMPLE
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DDR memory controller access to memory bank is typically of the burst type. Figure 2-9 and Figure 2-10 are examples
of burst read and write cycles.
FIGURE 2-9:
BURST DDR READ TIMING
FIGURE 2-10:
BURST DDR WRITE TIMING
2.5
SDIO/SD Host Controller (for KSZ9692PB only)
Integrated SDIO/SD host controller provides interface for removable mass storage memory card and I/O devices.
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Meets SD Host Controller Standard Specification Version 1.0
Meets SD memory card spec 1.01. MMC spec 3.31
Meets SDIO card specification version 1.0
1or 4 bit mode supported
Card detection-insertion/removal
Line Status LED driver
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Password protection of cards
Supports read wait control, suspend/resume operation
Support multi block read and write
Up to 12.5 Mbytes per second read and write rates using 4 parallel line for full speed card.
Dedicated DMA or programmed I/O data transfer
2.6
USB 2.0 Interface
Integrated dual USB 2.0 interface can be configured as 2-port host, or host + device. Figure 2-11 and Figure 2-12 illustrate examples of USB 2.0 interface applications.
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Compliant with USB Specification Revision 2.0
Compliant with Open Host Controller Interface (OHCI) Specification Rev 1.0a
Compliant with Enhanced Host Controller Interface (EHCI) Specification Rev 1.0
Root hub with 2 (max) downstream facing ports which are shared by OHCI and EHCI host controller cores
All downstream facing ports can handle High-Speed (480Mbps), Full-Speed (12Mbps), and Low-Speed (1.5Mbps)
transaction
OTG not supported
Integrated 45-ohm termination, 1.5K pull-up and 15K pull-down resistors
Support endpoint zero, and up to 6 configurable endpoints (IN/OUT, isochronous/ control/ interrupt/ bulk)
One isochronous endpoint (IN or OUT)
Dedicated DMA Channel for each port
FIGURE 2-11:
USB 2.0 CONFIGURATION AS TWO-PORT HOST
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FIGURE 2-12:
2.7
USB 2.0 CONFIGURATION AS HOST + DEVICE
PCI Interface
The KSZ9692PB/KSZ9692XPB integrates a PCI-to-AHB bridge solution for interfacing with 32-bit PCI, including
miniPCI, and cardbus devices where it is common for 802.11x-based Wireless products. The PCI-AHB bridge supports
two modes of operation in the PCI bus environment: host bridge mode and guest bridge mode. In the host bridge mode,
the ARM® processor acts as the host of the entire system. It configures other PCI devices and coordinates their transactions, including initiating transactions between the PCI devices and AHB bus subsystem. An on-chip PCI arbiter is
included to determine the PCI bus ownership among up to three PCI master devices.
In guest bridge mode, all of the I/O registers are programmed by either the external host CPU on the PCI bus or the
local ARM host processor through the AHB bus and the KSZ9692PB/KSZ9692XPB can be configured by either the
ARM or the PCI host CPU. In guest bridge mode, the on-chip PCI arbiter is disabled. In both cases, the KSZ9692PB/
KSZ9692XPB memory subsystem is accessible from either the PCI host or the ARM processor. Communications
between the external host CPU and the ARM processor is accomplished through message passing or through shared
memory.
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Compliant to PCI revision 2.3
Support 33 and 66MHz, 32-bit data PCI bus
Support 32-bit miniPCI or cardbus devices
Supports both regular and memory-mapped I/O on the PCI interface
AHB bus and PCI bus operate at independent clock domains
Supports big endian and little endian on AHB
PCI bus Round Robin arbiter for three external masters (for KSZ9692PB only)
PCI bus arbiter for one external master (for KSZ9692XPB only)
Supports high speed bus request and bus parking
Dedicated DMA channel for bulk data transfer to/from DDR memory
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2.8
Ethernet MAC Ports (Port 0 = WAN, Port 1 = LAN)
The KSZ9692PB/KSZ9692XPB integrates two Gigabit Ethernet controllers that operate at 10, 100, and 1000 Mbps.
Each controller has an interface that can operate as MII or RGMII to an external 10/100 or 10/100/1000 PHY to complete
Ethernet network connectivity. An integrated 25 MHz clock eliminates external crystal or oscillator requirement for PHY
to reduce cost. Integrated 2-pin (MDC & MDIO) Station Manager allows ARM® processor to access PHY registers and
pass control and status parameters. Wake-on-LAN is supported as part of the power management mechanism. Each
port has a dedicated MIB counter to accumulate statistics for received and transmitted traffic.
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IEEE 802.3 compliant MAC layer function
Configurable as MII or RGMII interface
RGMII interface compliant to Reduced Gigabit Media Independent Interface (RGMII)
Version 1.3
MII interface compliant to
Clause 22.2.4.5 of the IEEE 802.3u Specification
10/100/1000 Mbps half and full-duplex operation
Automatic CRC generation and checking
Automatic error packet discard
Supports IPv4 Header and IPv4/IPv6 TCP/UDP checksum generation to offload host CPU
Supports IPv4 Header and IPv4/IPv6 TCP/UDP checksum error detection
Supports 32 rules ACL filtering
Maximum frame length support is 2000 Byte at WAN port and 9K-byte at LAN port
Contains large independent receive and transmit FIFOs (8KB receive / 8KB transmit at WAN and 24KB receive /
22KB transmit at LAN) for back-to-back packet receive, and ensured no-under run packet transmit
• Data alignment logic and scatter gather capability
• Configurable as MAC or PHY mode
• Separate transmit and receive DMA channels for each port
2.8.1
WAKE-ON-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device
is pre-programmed by the policy owner or other software with information on how to identify wake frames from other
network traffic.
A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state.
A wake-up signal is caused by:
1.
2.
3.
Detection of a change in the network link state
Receipt of a network wake-up frame
Receipt of a Magic Packet
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these
in their own way.
2.8.2
LINK CHANGE
Link status wake events are useful to indicate a change in the network’s availability, especially when this change may
impact the level at which the system should re-enter the sleeping state. For example, a change from link off to link on
may trigger the system to re-enter sleep at a higher level (D2 versus D31) so that wake frames can be detected. Conversely, a transition from link on to link off may trigger the system to re-enter sleep at a deeper level (D3 versus D2)
since the network is not currently available.
1. References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI.
For more information, refer to the PCI specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf.
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2.8.3
WAKE-UP PACKET
Wake-up packets are certain types of packets with specific CRC values that a system recognizes to as a ‘wake up’
frame. The KSZ9692PB/KSZ9692XPB supports up to four user defined wake-up frame on each network control port:
2.8.4
MAGIC PACKET
Magic Packet technology is used to remotely wake up a sleeping or powered off PC or device on a network. This is
accomplished by sending a specific packet of information, called a Magic Packet frame, to a node on the network. When
a PC or device capable of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the network controller, and when the network controller receives a Magic Packet frame, it will alerts the system to wake up.
Magic Packet is a standard feature integrated into the KSZ9692PB/KSZ9692XPB. The controller implements multiple
advanced power-down modes including Magic Packet to conserve power and operate more efficiently.
Once the KSZ9692PB/KSZ9692XPB has been put into Magic Packet Enable mode, it scans all incoming frames
addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.
A Magic Packet frame must also meet the basic requirements for the network technology chosen, such as Source
Address (SA), or Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address and CRC.
The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This
sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as 6 bytes
of XoffFFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match
the address of the machine to be awakened.
Example:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the network controller would be
scanning for the data sequence (assuming an Ethernet frame):
DESTINATION SOURCE – MISC – : FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - MISC - CIRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or
an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node
at the frame’s destination.
If the network controller scans a frame and does not find the specific sequence shown above, it discards the frame and
takes no further action. If the KSZ9692PB/KSZ9692XPB controller detects the data sequence, however, it then alerts
the device’s power management circuitry to wake up the system.
2.8.5
IPV6 SUPPORT
The KSZ9692PB/KSZ9692XPB provides the following IPv6 support in the hardware:
• Generates the checksum for IPv6 TCP/UDP packets based on register configuration (LAN MAC DMA Transmit
Control Register and WAN MAC DMA Transmit Control Register) or Transmit Descriptor 1 (TDES1). The register
setting is static configuration and the TDES1 setting is packet-based configuration.
• Filters IPv6 packets with TCP/UDP errors (LAN MAC DMA Receive Control Register and WAN MAC DMA
Receive Control Register).
• Supports up to 8 Source IP or Destination IP based-filtering (LAN/WAN Access Control List)
Refer to the Register Description Document for more details.
2.9
DMA Controller
Integrated DMA controller connects data port of two Gb Ethernet MACs, two USB 2.0 ports, PCI 2.3 bus interface, and
SDIO interface (for KSZ9692PB only) via dedicated channels to DDR memory controller for moving large amounts of
data without significant ARM® processor intervention. A typical DMA channel usage is to move data from these interfaces into DDR memory. The data in the memory is processed by the ARM processor and driven back by the DMA chan-
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nel to the external interface. Additionally, the ARM® processor itself has a dedicated DMA channel to access the DDR
memory controller. Flash/ROM/SRAM, NAND controller, and peripherals do not have dedicated DMA channel and
therefore depend on the ARM processor for transfer of data to DDR memory. DMA channel interfaces are shown in functional block diagrams on page 8 and 9.
The arbitration of all requests from DMA channels are handled by the DDR memory controller and pipelined for best
performance. The memory controller supports programmable bandwidth allocation for each DMA channel, thus
enabling the designer to optimize I/O resource utilization of memory.
2.10
UART Interface
The KSZ9692PB/KSZ9692XPB support four independent high-speed UARTs; UART1, UART2, UART3 and UART4.
The UART ports enhance the system availability for legacy serial communication application and console port display.
UART1, UART2, UART3 and UART4 support maximum baud rate of 5 Mbps including standard rates. The higher rates
allow for Bluetooth and GSM applications.
UART1 supports CTSN, DSRN, DCDN modem control pins in addition to RXD and TXD data pins. For UART2, UART3,
UART4 only CTSN and RTSN control pins in addition to RXD and TXD data pins are supported.
2.11
Timers and Watchdog
Two programmable 32-bit timers with one capable of watchdog timer function. These timers can operate in a very flexible way. The host can control the timeout period as well as the pulse duration. Both timers can be enabled with interrupt
capability. When the watchdog timer is programmed and the timer setting expires, the KSZ9692PB/KSZ9692XPB resets
itself and also asserts WRSTO to reset other devices in the system.
2.12
GPIO
Twenty general purpose I/O (GPIO) are individually programmable as input or output. Some GPIO ports are programmable for alternate function as listed below:
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Four GPIO programmable as inputs for external interrupts
Two GPIO programmable as 32-bit timers output
Six GPIO programmable as CTSN and RTSN control pins for UART2, UART3, UART4
One GPIO programmable as SDIO Line Status LED driver (for KSZ9692PB only)
One GPIO programmable as ARM CPU interrupt line activity.
See Signal Description list for detailed GPIO map.
2.13
I2C
The I2C interface is a 2-pin (SCL & SDA) generic serial bus interface for both control and data. The KSZ9692PB/
KSZ9692XPB supports master mode I2C interface. To increase the firmware efficiency, KSZ9692PB/KSZ9692XPB is
equipped with hardware assisted logic to take care I2C bus sequence and protocol.
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Supports one master (KSZ9692PB/KSZ9692XPB) in the system
8-bit or 10-bit addressing
Up to 8 byte burst for read and write
Programmable SCL clock rate
for up to 400kHz
The I2C interface shares the same pins with the SPI interface.
2.14
SPI
The Serial Peripheral Interface (SPI) is a synchronous serial data link that provides communication with external
devices.
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8- to 16-bit Programmable Data Length
Programmable Serial Clock Phase and Polarity
Programmable Active Level of Chip Select (CS)
Programmable Delays between Two Active CS
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• Programmable Delays between Consecutive Transfers without Removing CS
• Programmable Delays between Assertion CS and 1 st SPCK
• Programmable SPI clock (SPCK) rate in the range of AMBA System Clock (SYSCLK) divided by a value between
16 and 65536
The SPI interface shares the same pins with the I2C interface.
2.14.1
I2S
I2S provides programmable 16-, 18-, 20-, 24-bit resolution audio for two (stereo) channels playback and recording.
2.14.2
INTERRUPT CONTROLLER
Interrupt controller handles external and internal interrupt sources.
• Normal or fast interrupt mode (IRQ, FIQ) supported
• Prioritized interrupt handling
2.15
System Level Interfaces
The following figures illustrate the high-level system connections to the KSZ9692PB/KSZ9692XPB. Note that these figures are for illustration purpose only. The system designer must refer to Evaluation Design Kit for actual circuit implementation.
FIGURE 2-13:
DS00003073A-page 22
RESET CIRCUIT
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
FIGURE 2-14:
POWER AND CLOCKS
According to some DDR device manufacturer’s electrical specification, DDR400 devices operating at 200 MHz require
a 2.6V power supply. DDR333 and DDR266 devices require 2.5V power supply. Power to the SoC DDR Memory Controller must be based on DDR device power requirement specification.
2008-2019 Microchip Technology Inc.
DS00003073A-page 23
KSZ9692PB/KSZ9692XPB
3.0
PIN DESCRIPTION AND CONFIGURATION
3.1
Signal Descriptions by Group
Pin Number
Pin Name
Pin Type
Pin Description
R5
RESETN
I
Reset, asserted Low.
RESETN will force the KSZ9692PB/KSZ9692XPB to reset ARM® 9
CPU and all functional blocks. Once asserted, RESETN must
remain asserted for a minimum duration of 256 system clock cycles.
When in the reset state, all the output pins are put into Tri-state and
all open drain signals are floated.
N5
WRSTO
O
Watchdog Timer Reset Output
When the Watchdog Timer expires, this signal will be asserted for at
least 200 msec.
W1
XCLK2
I
System Clock Input 2.
External crystal or clock input 2. The clock frequency should be
25MHz 100ppm.
Y1
XCLK1
I
System Clock Input 1.
Used with XCLK1 pin when other polarity of crystal is needed. This
is unused for a normal clock input.
H19
CLK25MHz
O
25MHz output to external PHY
Y15, Y14
DDCLKO[1:0]
O
DDR Clock Out [1:0].
Output of the internal system clock, it is also used as the clock signal
for DDR interface.
W15, W14
DDCLKON[1:0]
O
The negative of differential pair of DDR Clock Out [1:0].
Output of the internal system clock, it is also used as the clock signal
for DDR interface.
System Interface
U13
SDCLKEO
O
Clock Enable output for SDRAM (for Power Down Mode)
T7, U7
VREF
I
Reference Voltage for SSTL interface.
Must be half of the voltage for the DDR VDD supply. See EIA/
JEDEC standard EIA/JESD8-9 (Stub series terminated logic for
2.5V, SSTL_2)
W3
SDOCLK
O
DDR Clock Out for loopback from De-skew PLL
Y3
SDICLK
I
DDR Clock In from loopback to De-skew PLL. This pin must connect
to SDOCLK with appropriate de-skew length. See Engineering
Evaluation Design Kit for detailed implementation.
Y17, Y16
DDCLKO[3:2]
O
Factory Reserved
W17, W16
DDCLKON[3:2]
NAND/SRAM/ROM/EXIO Interface
O
Factory Reserved
L2, K1, K2,
J3, H5, H4,
J2, H3, J1,
H2, G5, H1,
G3, G4, G2,
F1, G1, F2,
F3, F5, F4,
E1, E2, E3
O
SADDR[23..0]
DS00003073A-page 24
SRAM Address Bus.
The 24-bit address bus covers 16M word memory space of ROM/
SRAM/FLASH, and 16M byte external I/O banks.
This address bus is shared between ROM/SRAM/FLASH/EXTIO
devices.
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
T2, U1, L5,
N4, P3, R2,
T1, M4, K5,
N3, P2, R1,
L4, M3, P1,
K4
SDATA[15..0]
Ipu/O
SRAM DATA Bus.
Bidirectional Bus for 16-bit DATA In and DATA Out. The KSZ9692PB/
KSZ9692XPB also supports 8-bit data bus for ROM/SRAM/FLASH/
EXTIO cycles.
This data bus is shared between NAND, ROM/SRAM/FLASH/EXTIO
devices.
L3
ECS2
O
External I/O Chip Select 2, asserted Low.
Three External I/O banks are provided for external memory-mapped I/
O operations. Each I/O bank stores up to 16Kbytes. ECSN signals
indicate which of the three I/O banks is selected.
N1
ECS1
O
External I/O Chip Select 1, asserted Low.
Three External I/O banks are provided for external memory-mapped I/
O operations. Each I/O bank stores up to 16Kbytes. ECSN signals
indicate which of the three I/O banks is selected.
M2
ECS0
O
External I/O Chip Select 0, asserted Low.
Three External I/O banks are provided for external memory-mapped I/
O operations. Each I/O bank stores up to 16Kbytes. ECSN signals
indicate which of the three I/O banks is selected.
K3
RCSN1
O
ROM/SRAM/FLASH(NOR) Chip select 1, asserted Low.
The KSZ9692PB/KSZ9692XPB can access up to two external ROM/
SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
L1
RCSN0
O
ROM/SRAM/FLASH(NOR) Chip select 0, asserted Low.
The KSZ9692PB/KSZ9692XPB can access up to two external ROM/
SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
This bank is configurable as boot option
N2
EWAITN
I
External Wait asserted Low.
This signal is asserted when an external I/O device or ROM/SRAM/
FLASH(NOR) bank needs more access cycles than those defined in
the corresponding control register.
M1
EROEN
(WRSTPLS)
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
When asserted, this signal controls the output enable port of the specified ROM/SRAM/FLASH memory and EXTIO device.
J5
ERWEN1
O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted
Low.
When asserted, this signal controls the byte write enable of the memory device SDATA[15..8] for ROM/SRAM/FLASH and EXTIO access.
J4
ERWEN0
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted
Low.
When asserted, this signal controls the byte write enable of the memory device SDATA[7..0 or 15..0] for ROM/SRAM/FLASH and EXTIO
access.
R3
NCLE
Ipd/O
NAND command Latch Enable
NCLE controls the activating path for command sent to NAND flash.
U2
NALE
Ipd/O
NAND Address Latch Enable
NALE controls the activating path for address sent to NAND flash.
T3
NCEN1
O
NAND Bank Chip Enable 1, asserted low
NAND device bank 1 selection control.
V3
NCEN0
O
NAND Bank Chip Enable 0, asserted low
NAND device bank 0 selection control.
This bank is configurable as boot option
R4
NREN
Ipu/O
2008-2019 Microchip Technology Inc.
NAND Read Enable, asserted low.
DS00003073A-page 25
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
T4
NWEN
Ipu/O
NAND Write Enable, asserted low.
Pin Description
U3
NWPN
Ipu/O
NAND Write Protection, asserted low.
P4, U4
NRBN[1:0]
I
NAND Ready/Busy, asserted low for busy.
T17, V18,
U17, T16,
W20, W19,
Y20, Y19,
W18, V17,
U16, T15,
Y18, V16
DADD[13..0]
O
DDR Address Bus.
V13, U11,
V12, W13,
Y13, W12,
V11, U10,
V10, Y11,
W10, U9,
Y10, V9, W9,
Y9, W8, Y8,
Y7, W7, V7,
Y6, W6, V6,
Y5, V5, W5,
U5, T5, Y4,
V4, W4
DDATA[31..0]
I/O
DDR Data Bus.
T13, V14
BA[1:0]
O
DDR Bank Address.
U14
CSN
O
DDR Chip Select, asserted Low.
Chip select pins for DDR, the KSZ9692PB/KSZ9692XPB supports
only one DDR bank.
T14
RASN
O
DDR Row Address Strobe, asserted Low.
The Row Address Strobe pin for DDR.
U15
CASN
O
DDR Column Address Strobe, asserted Low.
The Column Address Strobe pin for DDR.
V15
WEN
O
DDR Write Enable, asserted Low.
The write enable signal for DDR.
U8, T6
DM[1:0]
O
DDR Data Input/Output Mask
Data Input/Output mask signals for DDR. DM is sampled High and is
an output mask signal for write accesses and an output enable signal
for read accesses. Input data is masked during a Write cycle. DM0
corresponds to DDATA[7:0], DM1 corresponds to DDATA[15:8].
V8, U6
DQS[1:0]
I/O
DDR only Data Strobe
Input with read data, output with write data. DQS0 corresponds to
DDATA[7:0], DQS1 corresponds to DDATA[15:8].
M16
P0_RXC
Ipd/O
MAC mode MII: input RX clock / PHY mode MII: output RX clock
RGMII mode: input RX clock
P18, N17,
P17, N16
P0_RXD[3:0]
I
RX data[3:0]
N18
P0_RXDV
I
MII mode: RX data valid
RGMII mode: as RX_CTL. RXDV on rising edge of RXC, logic derivative of RXDV and RXER on falling edge of RXC
P19
P0_RXER
I
MII mode: RX error
RGMII mode: input SEL
DDR Interface
Ethernet Port 0
DS00003073A-page 26
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
M17
P0_CRS
I
MAC mode MII: input carrier sense
RGMII mode: not used
P20
P0_COL
I
MAC mode MII: input collision
RGMII mode: not used
M18
P0_TXC
Ipd/O
L17, M19,
N20, N19
P0_TXD[3:0]
O
TX data[3:0]
L16
P0_TXEN
O
MII: TX enable
RGMII: as TX_CTL input. TXEN on rising edge of TXC, logic derivative of TXEN and TXER on falling edge of TXC.
K19
P1_RXC
Ipd/O
L20, L19,
L18, M20
P1_RXD[3:0]
I
RX data[3:0]
K16
P1_RXDV
I
MII mode: RX data valid
RGMII mode: as RX_CTL. RXDV on rising edge of RXC, logic derivative of RXDV and RXER on falling edge of RXC
K17
P1_RXER
I
MII mode: RX error
RGMII mode: input SEL
K18
P1_CRS
I
MAC mode MII: input carrier sense
RGMII mode: not used
K20
P1_COL
I
MAC mode MII: input collision
RGMII mode: not used
J17
P1_TXC
Ipd/O
H20, J19,
J18, J20
P1_TXD[3:0]
O
TX data[3:0] output.
J16
P1_TXEN
O
MII: TX enable
RGMII: as TX_CTL input. TXEN on rising edge of TXC, logic derivative of TXEN and TXER on falling edge of TXC.
G19
U1P
I/O (analog)
USB port 1 differential + signal
G20
U1M
I/O (analog)
USB port 1 differential - signal
F19
U2P
I/O (analog)
USB port 2 differential + signal
F20
U2M
I/O (analog)
USB port 2 differential - signal
G17
USBXI
I (analog)
Crystal in for USB PLL
G18
USBXO
O (analog) Crystal out for USB PLL
H16
USBREXT
G16
USBTEST
G15
USBCFG
I
USB port 2 configuration
“1” = port 2 is host
“0” = port 2 is device
(port 1 is always host)
F18
USBHOVC0
I
Over current sensing input for Host Controller downstream port 1
MAC mode MII: input TX clock / PHY mode MII: output TX clock
RGMII mode: output TX clock
Ethernet Port 1
MAC mode MII: input RX clock / PHY mode MII: output RX clock
RGMII mode: input RX clock
MAC mode MII: input TX clock / PHY mode MII: output TX clock
RGMII mode: output TX clock
USB Interface
I (analog)
Connect to an external resistor 3.4K ohm to GND
O (Analog) USB analog test output (factory reserved)
2008-2019 Microchip Technology Inc.
DS00003073A-page 27
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
F15
USBHOVC1
I
F17
USBHPWR0
Ipu/O
(open
drain)
Power switching control output for downstream port 1; open drain output
F16
USBHPWR1
Ipu/O
(open
drain)
Power switching control output for downstream port 2; open drain output
SDIO Interface (for KSZ9692PB only)
D14
KCMD
Ipd/O
Pin Description
Over current sensing input for Host Controller downstream port 2
SD 4-bit mode: Command line
SD 1-bit mode: Command line
C18
KCLK
Ipd/O
C15
KDATA3
I/O
SD 4-bit mode: data line 3
SD 1-bit mode: not used
C16
KDATA2
I/O
SD 4-bit mode: data line 2 or read wait (optional)
SD 1-bit mode: read wait (optional)
E13
KDATA1
I/O
SD 4-bit mode: data line 1 or interrupt (optional)
SD 1-bit mode: interrupt
C17
KDATA0
I/O
SD 4-bit mode: data line 0
SD 1-bit mode: data line
C14
KSDCDN
I
Active low used for Card Detection
D13
KSDWP
I
Active high used for Card write protection
General Purpose I/O
B14
SLED/GPIO[19]
SDIO/SD Clock
I/O
SDIO Line Status LED output (for KSZ9692PB only) or General Purpose I/O Pin[19]
B15
CPUINTN/
GPIO[18]
I/O
Internal CPU interrupt request or General Purpose I/O Pin[18]
As CPUINTN, any interrupt generated to ARM® CPU asserts logic
low on this pin. Useful for software development.
B16, B17,
B18, D18,
E15, D19
GPIO[17:12]
I/O
General Purpose I/O Pin[17:12]
F14
UART 4 RTSN /
GPIO[11]
I/O
UART 4 RTS or general purpose I/O Pin[11]
E16
UART 4 CTSN /
GPIO[10]
I/O
UART 4 CTS or general purpose I/O Pin[10]
E17
UART 3 RTSN /
GPIO[9]
I/O
UART 3 RTS or general purpose I/O Pin[9]
E19
UART 3 CTSN /
GPIO[8]
I/O
UART 3 CTS or general purpose I/O Pin[8]
E20
UART 2 RTSN /
GPIO[7]
I/O
UART 2 RTS or general purpose I/O Pin[7]
E18
UART 2 CTSN /
GPIO[6]
I/O
UART 2 CTS or general purpose I/O Pin[6]
U20, U19
TOUT[1:0]/
GPIO[5:4]
I/O
Timer 1/0 out or General Purpose I/O Pin[5:4]
V20, T18,
V19, U18
EINT[3:0]/
GPIO[3:0]
I/O
External Interrupt Request or General Purpose I/O Pin[3:0]
C20
SCKIN
I
External crystal or clock input for I2S clock
The maximum supported frequency is 49.2 MHz
D20
SCKOUT
O
External Crystal out for I2S clock
I2S Interface
DS00003073A-page 28
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
C19
I2S_MCLK
O
I2S master clock out
This clock is of same frequency as SCKIN
B20
I2S_BCLK
O
I2S bit clock out
B19
I2S_LRCLK
O
Left/right select
A19
I2S_SDO
O
Serial data out
A20
I2S_SDI
I
Serial data in
MDIO/MDC Interface
H18
MDC
Ipu/O
Clock for station management
H17
MDIO
Ipu/O
Serial data for station management
E14
SPCK_SCL
Ipu/O
SPI mode: master clock output
I2C mode: serial clock output
D17
SPMOSI_SDA
Ipu/O
SPI mode: master data out,slave data in
I2C mode: serial data
D16
SPMISO
I
D15
SPICS
Ipu/O
F13
SPI_RDY
I
Microchip SPI mode ready signal
I2C/SPI Interface
SPI master data in, slave data out
SPI chip select
PCI Interface Signals
C3
PRSTN
I
PCI Reset, asserted Low
In Host Bridge Mode, the PCI Reset pin is an input. This pin as well as
the reset pin of all the devices on the PCI bus could be driven by
WRSTO.
In Guest Bridge Mode, this pin is input. The system reset to drive this
pin.
B2
PCLK
I
PCI Bus Clock input.
This signal provides the timing for the PCI bus transactions. This signal is
used to drive the PCI bus interface and the internal PCI logic. All PCI bus
signals are sampled on the rising edges of the PCLK. PCLK can operate
from 20MHz to 33MHz, or 66MHz.
E4
GNT3N
O
PCI Bus Grant 3
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI
arbiter to grant PCI bus access to the master driving REQ3N.
In Guest Bridge Mode, this is unused.
(No connect for KSZ9692XPB)
D4
GNT2N
O
PCI Bus Grant 2
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI
arbiter to grant PCI bus access to the master driving REQ2N.
In Guest Bridge Mode, this is unused.
(No connect for KSZ9692XPB)
B1
GNT1N
O
PCI Bus Grant 1
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI
arbiter to grant PCI bus access to the master driving REQ1N.
In Guest Bridge Mode, this is an output signal to indicate to the external PCI bus arbiter that KSZ9692PB/KSZ9692XPB is requesting
access to the PCI bus.
2008-2019 Microchip Technology Inc.
DS00003073A-page 29
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
D3
REQ3N
I
PCI Bus Request 3
Assert Low.
In Host Bridge Mode, this is an input signal from the external PCI
device to request for PCI bus access
In Guest Bridge Mode, this is unused.
(No connect for KSZ9692XPB)
E6
REQ2N
I
PCI Bus Request 2
Assert Low.
In Host Bridge Mode, this is an input signal from the external PCI
device to request for PCI bus access
In Guest Bridge Mode, this is unused.
(No connect for KSZ9692XPB)
C1
REQ1N
I
PCI Bus Request 1
Assert Low.
In Host Bridge Mode, this is an input signal from the external PCI
device to request for PCI bus access
In Guest Bridge Mode, this signal comes from the external arbiter to
indicate that the bus is granted to KSZ9692PB/KSZ9692XPB.
B3, E7, D6,
A2, B4, A3,
D7, C5, C6,
B5, A4, A5,
B6, E8, C7,
D8, D10,
B10, A11,
B11, C11,
A12, E11,
D11, B12,
A13, C12,
B13, F12,
C13, D12,
E12
PAD[31..0]
I/O
32-bit PCI address and data lines
Addresses and data bits are multiplexed on the same pins. During the
first clock cycle of a PCI transaction, the PAD bus contains the first
clock cycle of a PCI transaction, the PAD bus contains the physical
address. During subsequent clock cycles, these lines contain the 32bit data to be transferred. Depending on the type of the transaction,
the source of the data will be the KSZ9692PB/KSZ9692XPB if it initiates a PCI write transaction, or the data source will be the target if it is
a PCI Read transaction. The KSZ9692PB/KSZ9692XPB bus transaction consists of an address phase followed by one or more data
phases. The KSZ9692PB/KSZ9692XPB supports both Read and
Write burst transactions. In case of a Read transaction, a special data
turn around cycle is needed between the address phase and the data
phase.
A6, A7, E10,
C10
CBEN[3..0]
I/O
PCI Commands and Byte Enable, asserted Low.
The PCI command and byte enable signals are multiplexed on the
same pins. During the first clock cycle of a PCI transaction, the CBEN
bus contains the command for the transaction. The PCI transaction
consists of the address phases and one or more data phases. During
the data phases of the transaction, the bus carries the byte enable for
the current data phases.
C8
PAR
I/O
Parity
PCI Bus parity is even across PAD[31:0] and CBEN[3:0].
The KSZ9692PB/KSZ9692XPB generates PAR during the address
phase and write data phases as a bus master, and during read data
phases as a target. It checks for correct PAR during read data phase
as a bus master, during every address phase as a bus slave, and
during write data phases as a target.
D9
FRAMEN
I/O
PCI Bus Frame signal, asserted Low.
FRAMEN is an indication of an active PCI bus cycle. It is asserted at
the beginning of a PCI transaction, i.e. the address phase, and deasserted before the final transfer of the data phase of the transaction.
DS00003073A-page 30
Pin Description
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
B8
IRDYN
I/O
PCI Initiator Ready signal, asserted Low.
This signal is asserted by a PCI master to indicate a valid data phase
on the PAD bus during data phases of a write transaction. In a read
transaction, it indicates that the master is ready to accept data from
the target. A target will monitor the IRDYN signal when a data phase
is completed on any rising edge of the PCI clock when both IRDYN
and TRDYN are asserted. Wait cycles are inserted until both IRDYN
and TRDYN are asserted together.
E9
TRDYN
I/O
PCI Target Ready signal, asserted Low.
This signal is asserted by a PCI slave to indicate a valid data phase
on the PAD bus during data phases of a read transaction. In a write
transaction, it indicates that the slave is ready to accept data from the
target. A PCI initiator will monitor the TRDYN signal when a data
phase is completed on any rising edge of the PCI clock when both
IRDYN and TRDYN are asserted. Wait cycles are inserted until both
IRDYN and TRDYN are asserted together.
A9
DEVSELN
I/O
PCI Device Select signal, asserted Low.
This signal is asserted when the KSZ9692PB/KSZ9692XPB is
selected as a target during a bus transaction. When the KSZ9692PB/
KSZ9692XPB is the initiator of the current bus access, it expects the
target to assert DEVSELN within 5 PCI bus cycles, confirming the
access. If the target does not assert DEVSELN within the required
bus cycles, the KSZ9692PB/KSZ9692XPB aborts the bus cycle. As a
target, the KSZ9692PB/KSZ9692XPB asserts this signal in a medium
speed decode timing. (2 bus cycle)
B7
IDSEL
I
Initialization Device Select. It is used as a chip select during configuration read and write transactions.
B9
STOPN
I/O
PCI Stop signal, asserted Low.
This signal is asserted by the PCI target to indicate to the bus master
that it is terminating the current transaction. The KSZ9692PB/
KSZ9692XPB responds to the assertion of STOPN when it is the bus
master, either to disconnect, retry, or abort.
A10
PERRN
I/O
PCI Parity Error signal, asserted Low.
The KSZ9692PB/KSZ9692XPB asserts PERRN when it checks and
detects a bus parity error. When it generates the PAR output, the
KSZ9692PB/KSZ9692XPB monitors for any reported parity error on
PERRN.
When the KSZ9692PB/KSZ9692XPB is the bus master and a parity
error is detected, the KSZ9692PB/KSZ9692XPB sets error bits on the
control status registers. It completes the current data burst transaction, then stop the operation. After the Host clears the system error,
the KSZ9692PB/KSZ9692XPB continues its operation.
C9
SERRN
O (open
drain)
PCI System Error signal, asserted Low.
If an address parity error is detected, the KSZ9692PB/KSZ9692XPB
asserts the SERRN signal two clocks after the failing address.
C4
M66EN
I
PCI 66MHz Enable
When asserted, this signal indicates the PCI Bus segment is operating at 66 MHz.
This pin is mainly used in Guest bridge mode when the PCLK is
driven by the Host bridge.
F6
PCLKOUT3
O
PCI Clock output 3
(No connect for KSZ9692XPB)
D1
PCLKOUT2
O
PCI Clock output 2
(No connect for KSZ9692XPB)
D2
PCLKOUT1
O
PCI Clock output 1
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DS00003073A-page 31
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
E5
PCLKOUT0
O
PCI Clock output 0.
This signal provides the timing for the PCI bus transactions. This signal is used to drive the PCI bus interface and the internal PCI logic. All
PCI bus signals are sampled on the rising edges of the PCLK. PCLK
can operate from 20MHz to 33MHz, or 66MHz.
In Host Bridge Mode, this is an output signal for all the devices on the
PCI bus to sample data and control signals. Connect this clock to
drive PCLK input.
In Guest Bridge Mode, this is not used.
A8
CLKRUNN
I/O
This is a CardBus only signal. The CLKRUNN signal is used by portable CardBus devices to request the system to turn on the bus clock.
Output is not generated.
C2
MPCIACTN
I/O
Mini-PCI active. This signal is asserted by the PCI device to indicate
that its current function requires full system performance. MPCIACTN
is an open drain output signal.
D5
PBMS
I
PCI Bridge Mode Select
Select the operating mode of the PCI Bridge.
When PBMS is High, the Host Bridge Mode is selected and on chip
PCI bus arbiter is enabled.
When PBMS is Low, the Guest Bridge Mode is selected and the onchip arbiter is disabled.
A1
PMEN
O (open
drain)
PCI Power Management Enable (active low)
This pin is to inform the external PCI host that KSZ9692PB/
KSZ9692XPB has detected a wake-up event.
UART Signals
P16
U1RXD
Ipd
R16
U1TXD
O (TriState)
UART 1 Receive Data
R19
U1CTSN
Ipd
R20
U1DCDN
Ipd
UART 1 Data Carrier Detect
P15
U1DSRN
Ipd
UART 1 Data Set Ready
R15
U2RXD
Ipd
R17
U2TXD
O (TriState)
R18
U3RXD
Ipd
N15
U3TXD
O (TriState)
T19
U4RXD
Ipd
T20
U4TXD
O (TriState)
UART 1Transmit Data
Must be enabled as output by software, otherwise tri-stated upon
power-up. External pull-up recommended.
UART 1Clear to Send
UART 2 Receive Data
UART 2 Transmit Data
Must be enabled as output by software, otherwise tri-stated upon
power-up. External pull-up recommended.
UART 3 Receive Data
UART 3 Transmit Data
Must be enabled as output by software, otherwise tri-stated upon
power-up. External pull-up recommended.
UART 4 Receive Data
UART 4 Transmit Data
Must be enabled as output by software, otherwise tri-stated upon
power-up. External pull-up recommended.
TAP Control Signals
A18
TCK
I
JTAG Test Clock
A17
TMS
I
JTAG Test Mode Select
A16
TDI
I
JTAG Test Data In
A15
TDO
O
JTAG Test Data Out
A14
TRSTN
I
JTAG Test Reset, asserted Low
DS00003073A-page 32
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
P5
SCANEN
Ipd
1 = Scan Enable (Factory reserved)
0 = Normal Operation
V2
TESTEN
Ipd
1 = Test Enable (Factory reserved)
0 = Normal Operation
V1
TESTEN1
Ipd
1 = Test Enable1 (Factory reserved)
0 = Normal Operation
Y2
TEST1
O (analog) Factory reserved
W2
TEST2
O (analog) Factory reserved
Test Signals
Power and Ground (96)
N6, M6,
M7, G7,
G8, G9,
M14,
M15, N14,
P11, P12,
P13, P14
VDD1.2
P
Digital power supply 1.3V (13)
G6, H6,
J6, K6,
F7, F8,
F9, F10,
F11, G10,
G11, H14,
J14, K14,
K15, L15
VDD3.3
P
Digital power supply 3.3V (16)
R6, R7, R8,
R9, R10,
R11, R12,
R13, R14,
T8, T9, T10,
T11
VDD2.5
P
DDR Pad Driver 2.5V or 2.6V Power Supply. (13)
H7, H8, H9,
H10, H11,
J7, J8, J9,
J10, J11, K7,
K8, K9, K10,
K11, K12, L7,
L9, L10, L11,
L12, L13,
L14, M9,
M10, M11,
M12, M13,
N9, N10,
N11, N12,
N13, P7, P8,
P9, P10
GND
GROUND
L6
PLLVDDA3.3
P
M8
PLLVSSA3.3
GROUND
P6
PLLDVDD1.2
P
M5
PLLSVDD1.2
P
System PLL Analog and Digital Power. (1)
N7, N8
PLLVSS1.2
GROUND
De-skew PLL and System PLL Ground. (2)
L8
PLLVSSISO
GROUND
Ground Isolation PLL and other circuit. (1)
G12
USB1VDDA3.3
P
2008-2019 Microchip Technology Inc.
Digital Ground. (37)
Band Gap Reference Analog Power. (1)
Band Gap Reference Analog Ground. (1)
De-skew PLL Analog and Digital Power. (1)
Analog Power for USB Channel 1. (1)
DS00003073A-page 33
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
G13
USBCVDDA3.3
P
G14
USB2VDDA3.3
P
H13, J13,
K13
USBVSSA3.3
GROUND
Pin Description
Analog Power for Common Circuit of USB Channel 1 and 2. (1)
Analog Power for USB Channel 2. (1)
Analog Ground for both USB Channels Analog Circuit. (3)
J15
USB1VDD1.2
P
Digital Power for USB Channel 1 Controller. (1)
H15
USB2VDD1.2
P
Digital Power for USB Channel 2 Controller. (1)
J12
USBVSS1
GROUND
Digital Ground for USB Channel 1 Controller. (1)
H12
USBVSS2
GROUND
Digital Ground for USB Channel 2 Controller. (1)
Note 1: P = Power supply.
I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
Ipu = Internal 55kΩ pull-up resistor.
Ipd = Internal 55kΩ pull-down resistor.
3.2
Power-up Strapping Options
Certain pins are sampled upon power up or reset to initialize KSZ9692PB/KSZ9692XPB system registers per system
configuration requirements.
Pin Number
Pin Name
Pin Type
E3
SADDR[0]
Ipd/O
During reset, this pin is the input strap option for NAND Boot small page
size
0 = 512 Bytes (default)
1 = 528 Bytes
E1, E2
SADDR[2:1]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [7:6]. These pins are used to specify number of active
banks (CE#) in cascade.
00 = 1 bank (default)
01 = 2 banks
F4
SADDR[3]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [8], NAND Flash type. This pin is used to specify using
large or small block NAND Flash as a boot bank as follows:
“0” = small block (default)
“1” = large block
F5
SADDR[4]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [4], NAND Flash type. This pin is used to specify number of NAND Flash in parallel for combined data width as follows:
“0” = 1 NAND Flash (default)
“1” = 2 NAND Flash
F3
SADDR[5]
Ipu/O
During reset, this is the input strap option to enter ARM® 9 tic test mode
0: ARM tic test mode (factory reserved)
1: Normal mode (default)
F2
SADDR[6]
Ipd/O
During reset, this pin is the input strap option for NAND FLASH device support automatic page crossing
0: NAND FLASH device does not support automatic page crossing (default)
1: NAND FLASH device supports automatic page crossing
DS00003073A-page 34
Pin Description
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
G1
SADDR[7]
Ipd/O
During reset, this pin is a strapping option for B0SIZE, Bank 0 Data Access
Size. This is applicable to ROM/SRAM/FLASH and NAND boot bank.
Bank 0 is used for boot program. This pin is used to specify the size of the
bank 0 data bus width as follow:
“0” = one byte (default)
“1” = half word
F1
SADDR[8]
Ipd/O
During reset, this pin is a strapping option for BTSEL:
“0” = Boot select from NOR flash (default)
“1” = Boot select from NAND flash
G2
SADDR[9]
Ipd/O
During reset this pin is a strapping option for BYP_SYSPLL:
“0” = Use systems PLL (default)
“1” = Bypass systems PLL, use external clock (factory reserved)
G4
SADDR[10]
Ipd/O
During reset this pin is a strapping option for BYP_CLKSEL:
“0” = Select 200MHz external clock (default)
“1” = Select 250MHz external clock (factory reserved)
G3
SADDR[11]
Ipd/O
During reset, this pin is the input strap option to enable either MII or RGMII
mode at port1 (LAN port)
0: MII mode (default)
1: RGMII mode
M1
EROEN
(WRSTPLS)
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
When asserted, this signal controls the output enable port of the specified
ROM/SRAM/FLASH memory and EXTIO device.
During reset, this pin is used for Watchdog Timer Reset Polarity Select.
This is a power strapping option pin for watchdog reset output polarity.
“0” = WRSTO is selected as active high (default)
“1” = WRSTO is selected as active low.
This pin is shared with the EROEN pin.
J4
ERWEN0
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, these signals control the byte write enable of the memory
device for ROM/SRAM/FLASH and EXTIO access.
During ARM® tic test mode, this pin is TESTACK.
During reset, this pin is the input strap option to enable either MII or RGMII
mode at port0 (WAN port)
0: MII mode (default)
1: RGMII mode
R3
NCLE
Ipd/O
NAND command Latch Enable
NCLE controls the activating path for command sent to NAND flash.
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [2]. This bit along with configuration register bits [1:0] is
used for boot program. This pin along with NALE and NWEN is used to
specify NAND Flash size.
[NCLE, NALE, NWEN]
000 = 64Mbit
001 = 128Mbit (default)
010 = 256Mbit
011 = 512Mbit
100 = 1Gbit
101 = 2Gbit
110 = 4Gbit
111 = 8Gbit
2008-2019 Microchip Technology Inc.
DS00003073A-page 35
KSZ9692PB/KSZ9692XPB
Pin Number
Pin Name
Pin Type
Pin Description
U2
NALE
Ipd/O
NAND Address Latch Enable
NALE controls the activating path for address sent to NAND flash.
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [1]. This bit along with configuration register bits [2], [0]
is used for boot program. This pin along with NCLE and NWEN is used to
specify NAND Flash size.
[NCLE, NALE, NWEN]
000 = 64Mbit
001 = 128Mbit (default)
010 = 256Mbit
011 = 512Mbit
100 = 1Gbit
101 = 2Gbit
110 = 4Gbit
111 = 8Gbit
T4
NWEN
Ipu/O
NAND Write Enable, asserted low
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [0]. This bit along with configuration register bits [2:1] is
used for boot program. This pin along with NCLE and NALE is used to
specify NAND Flash size.
[NCLE, NALE, NWEN]
000 = 64Mbit
001 = 128Mbit (default)
010 = 256Mbit
011 = 512Mbit
100 = 1Gbit
101 = 2Gbit
110 = 4Gbit
111 = 8Gbit
U3
NWPN
Ipu/O
NAND Write Protection, asserted low
During reset, this pin is the input strap option to enable test modes. This pin
along with TESTEN, TESTEN1 form different test modes.
{TESTEN, TESTEN1, NWPN} =
011: ARM® Scan test mode
010: USB Analog Bits test mode
others: refer to TESTEN and TESTEN1 pin description
(factory reserved)
G15
USBCFG
I
USB port 2 configuration
“1” = port 2 is host
“0” = port 2 is device
(port 1 is always host)
Test Pins Strapping Options
P5
SCANEN
Ipd
1 = Scan Enable (Factory reserved)
0 = Normal Operation
V2
TESTEN
Ipd
1 = Test Enable (Factory reserved)
0 = Normal Operation
V1
TESTEN1
Ipd
1 = Test Enable1 (Factory reserved)
0 = Normal Operation
Note 1: P = Power supply.
I = Input. O = Output.
O/I = Output in normal mode; input pin during reset.
Ipu = Internal 55kΩ pull-up resistor.
Ipd = Internal 55kΩ pull-down resistor.
DS00003073A-page 36
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
4.0
OPERATIONAL CHARACTERISTICS
4.1
Absolute Maximum Ratings (Note 1)
Supply Voltage
(VDD1.2, PLLDVDD1.2, PLLSVDD1.2, ................................................................................................................
USB1VDD1.2, USB2VDD1.2)....................................................................................................... –0.5V to +1.6V
VDD2.5…… .......................................................................................... ……… …………………..–0.5V to +3.0V
(VDD3.3, PLLVDDA3.3, PLLDVDD3.3,
USB1VDDA3.3, USB2VDDA3.3,
USBCVDDA3.3)........................................................................................................................... –0.5V to +4.0V
Input Voltage (all inputs) ........................................................................................................................... –0.5V to +4.0V
Output Voltage (all outputs) ...................................................................................................................... –0.5V to +4.0V
Pb-Free Temperature (soldering, 10sec.) ............................................................................................................... 260°C
Storage Temperature (Ts) ...................................................................................................................... –55°C to +150°C
4.2
Operating Ratings (Note 2)
Supply Voltage
(VDD1.2, PLLDVDD1.2, PLLSVDD1.2,
USB1VDD1.2, USB2VDD1.2............................................................................................... )+1.235V to +1.365V
VDD2.5 ....................................................................................................................................................... +2.3V to +2.7V
(VDD3.3, PLLVDDA3.3, PLLDVDD3.3,
USB1VDDA3.3, USB2VDDA3.3,
USBCVDDA3.3)........................................................................................................................... +3.0V to +3.6V
Ambient Temperature (TA)
Commercial ................................................................................................................................... 0°C to +70°C
Industrial .....................................................................................................................................-40°C to +85°C
Junction Temperature (TJ) ...................................................................................................................................... 150°C
Package Thermal Resistance (Note 3)
(JA) No Air Flow ...............................................................................................................................23.4°C/W
1m/s ..........................................................................................................................................21.1°C/W
2m/s ..........................................................................................................................................20.2°C/W
(JC) No Air Flow .................................................................................................................................9.5°C/W
4.3
Electrical Characteristics (Note 4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Total Supply Current with WAN and LAN ports under 1000 Mbps Data Traffic, DDR clock = 200MHz
I1.3V
VDD1.2, PLLDVDD1.2,
PLLSVDD1.2, USB1VDD1.2, USB2VDD1.2
Single supply at 1.3V
595
I2.6V
VDD2.5
Single supply at 2.6V
160
mA
I3.3v
VDD3.3, PLLVDDA3.3, PLL- Single supply at 3.3V
DVDD3.3, USB1VDDA3.3,
USB2VDDA3.3, USBCVDDA3.3
116
mA
mA
TTL Inputs (SDIO, Static Memory, UART, SPI, I2C, I2S, MDC/MDIO, GPIO)
VIH
Input High Voltage
VIL
Input Low Voltage
2008-2019 Microchip Technology Inc.
2.0
V
0.8
V
DS00003073A-page 37
KSZ9692PB/KSZ9692XPB
Symbol
IIN
Parameter
Input Current
(Excluding pull-up/pulldown)
Condition
VIN = GND ~ VDD3.3
Min
–10
Typ
Max
Units
10
µA
0.4
V
10
µA
TTL Outputs (SDIO, Static Memory, UART, SPI, I2C, I2S, MDC/MDIO, GPIO)
VOH
Output High Voltage
IOH = –8mA
VOL
Output Low Voltage
IOL = 8mA
IOZ
Output Tri-state Leakage
2.4
V
PCI Electrical: Compliant to PCI version 2.3 Standard
DDR Electrical: Compliant to EIA/JEDEC standard EIA/JESD8-9 (Stub series terminated logic for 2.5V, SSTL_2)
USB 2.0 Electrical: Compliant to USB 2.0 Standard
RGMII Electrical: Compliant to Reduced Gigabit Media Independent Interface (RGMII) Version 1.3 (Note 5)
MII Electrical: compliant to IEEE 802.3u Specification
Note 1: Exceeding the absolute maximum rating may damage the device.
2: The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to
an appropriate logic voltage level (Ground to VDD).
3: No heat spreader in package.
4: TA = 25°C. The specification is for the packaged product only.
5: RGMII interface is standard 3.3V CMOS VIO. However “Reduced Gigabit Media Independent Interface
(RGMII) Version 1.3” specification is based on 2.5V CMOS VIO. Therefore any chosen RGMII based PHY
must be evaluated based upon standard 3.3V CMOS VIO compatibility.
DS00003073A-page 38
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
5.0
TIMING SPECIFICATIONS
Figure 5-1 provides power sequencing requirement with respect to system reset.
FIGURE 5-1:
RESET TIMING
Note:
Power sequencing of supply voltages must be in order of 3.3V first, 2.5V/2.6V next and 1.3V
last.
TABLE 5-1:
RESET TIMING PARAMETERS
Symbol
Parameter
Min
Typ
Max
Units
tSR
Stable supply voltages to reset high
10
ms
tCS
Configuration set-up time
50
ns
tCH
Configuration hold time
50
ns
tRC
Reset to strap-in pin output
50
ns
Figure 5-2 and Figure 5-3 provide NOR FLASH, ROM and SRAM interface timing.
2008-2019 Microchip Technology Inc.
DS00003073A-page 39
KSZ9692PB/KSZ9692XPB
FIGURE 5-2:
STATIC MEMORY READ CYCLE
FIGURE 5-3:
STATIC MEMORY WRITE CYCLE
TABLE 5-2:
PROGRAMMABLE STATIC MEMORY TIMING PARAMETERS
Symbol
RBiTACC
Parameter (Note 1)
Programmable bank i access time
RBiTPA
Programmable bank i page access time
Note 1: "i" Refers to chip select parameters 0 and 1.
Registers
0x5010, 0x5014
0x5010, 0x5014
Figure 5-4 provides external I/O ports interface timing.
DS00003073A-page 40
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
FIGURE 5-4:
TABLE 5-3:
EXTERNAL I/O READ AND WRITE CYCLES
EXTERNAL I/O MEMORY TIMING PARAMETERS
Symbol
Parameter
Min(1)
Typ(1)
Max(1)
Units
Tcta
Valid address to CS setup time
EBiTACS
+0.8
EBiTACS
+1.1
EBiTACS
+1.3
ns
Tcos
OE valid to CS setup time
EBiTCOS
+0.6
EBiTCOS
+0.6
EBiTCOS
+1.0
ns
Tdsu
Valid read data to OE setup time
Tcws
WE valid to CS setup time
EBiTCOS
+0.6
EBiTCOS
+0.6
EBiTCOS
+1.0
Tdh
Write data to CS hold time
0
Tcah
Address to CS hold time
EBiTCOH
+1.0
Toew
OE/WE pulsewidth
EBiTACT
Tocs, Tcsw
Rising edge CS to OE/WE hold time
2.0
ns
ns
ns
EBiTCOH
+1.0
EBiTCOH
+1.4
ns
EBiTACT
ns
0
ns
Note 1: Measurements for minimum were taken at 0°C, typical at 25°C, and maximum at 100°C.
TABLE 5-4:
PROGRAMMABLE EXTERNAL I/O TIMING PARAMETERS
Parameter(1)
Symbol
Registers
EBiTACS
Programmable bank i address setup time before chip select
0x5000, 0x5004, 0x5008
EBiTACT
Programmable bank i write enable/output enable access time
0x5000, 0x5004, 0x5008
EBiTCOS
Programmable bank i chip select setup time before OEN
0x5000, 0x5004, 0x5008
EBiTCOH
Programmable bank i chip select hold time
0x5000, 0x5004, 0x5008
Note 1: "i" Refers to chip select parameters 0, 1, or 2.
2008-2019 Microchip Technology Inc.
DS00003073A-page 41
KSZ9692PB/KSZ9692XPB
5.1
Signal Location Information
FIGURE 5-5:
1
A
PMEN
B GNT1N
C REQ1N
D
BALL GRID ARRAY MAP
12
PAD26
PAD21
PAD20
CBEN3
CBEN2
CLKRUN DEVSEL
N
N
PERRN
11
PAD28
2
3
PAD13
PAD10
PAD6
TRSTN
PCLK
PAD31
PAD27
PAD22
PAD19
IDSEL
IRDYN
STOPN
PAD14
PAD12
PAD7
PAD4
GPIO19
MPCIACT
N
PRSTN
M66EN
PAD24
PAD23
PAD17
PAR
SERRN
CBEN0
PAD11
PAD5
PAD2
KSDCDN KDATA3 KDATA2 KDATA0 KCLK
PCLKOU PCLKOU
T2
T1
REQ3N
E SADDR2
4
GNT2N
SADDR1 SADDR0 GNT3N
5
PMBS
6
PAD29
PCLKOU
T0
REQ2N
7
PAD25
PAD30
8
PAD16
PAD18
9
10
FRAMEN PAD15
TRDYN
CBEN1
PAD8
PAD9
13
14
KCMD
15
16
17
18
19
20
TDO
TDI
TMS
TCK
I2S_SDO I2S_SDI
GPIO18
GPIO17
GPIO16
GPIO15
I2S_LRCL I2S_BCL
K
K
PAD1
KSDWP
PAD0
SPCK_S
KDATA1 CL
GPIO13
SPICS
I2S_MCL
K
SCKIN
SPMOSI_
SPMISO SDA
GPIO14
GPIO12
GPIO10
GPIO8
GPIO9
GPIO6
SCKOUT
GPIO7
G
SADDR
PCLKOU
SADDR6 SADDR5 SADDR3 SADDR4 T3
8
VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 PAD3
USB1
VDDA3.
SADDR7 SADDR9 SADDR11 SADDR10 SADDR13 VDD3.3 VDD1.2 VDD1.2 VDD1.2 VDD3.3 VDD3.3 3
H
SADDR12 SADDR14 SADDR16 SADDR18 SADDR19
VDD3.3 GND
GND
GND
GND
GND
USBVSS USBVSS
2
A3.3
VDD3.3 VDD1.2 USBREXT MDIO
J SADDR15 SADDR17 SADDR20 ERWEN0 ERWEN1
VDD3.3 GND
GND
GND
GND
GND
USBVSS USBVSS
1
A3.3
VDD3.3 VDD1.2 P1_TXEN P1_TXC
VDD3.3 VDD3.3 P1_RXDV P1_RXER P1_CRS P1_RXC P1_COL
F
USBXO
U1P
CLK25MH
Z_1
P1_TXD3
P1_TXD1 P1_TXD2 P1_TXD0
PLLVSSI
GND
SO
GND
GND
GND
GND
GND
PLLS
PLLVSSA
SDATA2 SDATA8 VDD1.2 VDD1.2 VDD1.2 3.3
GND
GND
GND
GND
GND
VDD1.2 VDD1.2 P0_RXC P0_CRS P0_TXC
PLLVSS1 PLLVSS1
.2
.2
GND
GND
GND
GND
GND
VDD1.2 U3TXD
GND
VDD1.2 VDD1.2 VDD1.2 VDD1.2 U1DSRN U1RXD
SADDR23 ECS2
EWAITN SDATA6 SDATA12 WRSTO
VDD1.2
U1M
USB1
GND
GND
U2M
MDC
USB2
GND
L RCSN0
N ECS1
USBC USB2
VDDA3. VDDA3.
USBCFG USBTEST USBXI
3
3
GND
PLL
VDDA3.
SDATA3 SDATA13 3
GND
ECS0
USBHOV USBHPW USBHPW USBHOV
C1
R1
R0
C0
U2P
GND
VDD3.3 GND
SDATA0 SDATA7
EROEN
GPIO11
USBVSS
A3.3
K SADDR22 SADDR21 RCSN1
M
SPIRDY
VDD3.3 P0_TXEN P0_TXD3 P1_RXD1 P1_RXD2 P1_RXD3
P0_TXD2 P1_RXD0
P0_RXD0 P0_RXD2 P0_RXDV P0_TXD0 P0_TXD1
P SDATA1
R SDATA4
SDATA5 SDATA11 NRBN1
PLLD
SCANEN VDD1.2 GND
SDATA10 NCLE
NREN
RESETN VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 U2RXD
T SDATA9
SDATA15 NCEN1
NWEN
DATA3
DM0
VREF
VDD2.5 VDD2.5 VDD2.5 VDD2.5 RSVD
BA1
RASN
ADDR2
GPIO2/EI
ADDR10 ADDR13 NT2
U4RXD
NWPN
NRBN0
DATA4
DQS0
VREF
DM1
RSVD
RSVD
RSVD
RSVD
CKE
CSN
CASN
ADDR3
GPIO0/EI GPIO4/T GPIO5/T
ADDR11 NT0
OUT0
OUT1
NCEN0
DATA1
DATA6
DATA8
DATA11
DQS1
RSVD
RSVD
RSVD
RSVD
RSVD
BA0
WEN
ADDR0
ADDR4
GPIO1/EI GPIO3/EI
ADDR12 NT1
NT3
U SDATA14 NALE
V TESTEN1 TESTEN
W XCLK2 TEST2
Y XCLK1 TEST1
GND
U1TXD
P0_RXD1 P0_RXD3 P0_RXER P0_COL
U2TXD
U3RXD
U1CTSN U1DCDN
U4TXD
SDOCLK DATA0
DATA5
DATA9
DATA12
DATA15
RSVD
RSVD
RSVD
RSVD
RSVD
CLK0N
CLK1N
RSVD
RSVD
ADDR5
ADDR8
ADDR9
SDICLK
DATA7
DATA10
DATA13
DATA14
RSVD
RSVD
RSVD
RSVD
RSVD
CLK0
CLK1
RSVD
RSVD
ADDR1
ADDR6
ADDR7
DATA2
Power - 1.2V (digital & analog)
Power - 3.3V (digital & analog)
VDD2.5
PCI
USB
UART
Test
Strap/Reset/XTAL Signals
GPIO
I2S
GND
ROM/SRAM/NAND
Ethernet
DDR
Note:
GND
JTAG
I2C/SPI
SDIO
For KSZ9692XPB SDIO balls (D14, C18, C15, C16, E13, C17, C14, D13) and PCI balls (E4, D4, D3, E6,
F6, D1) are no connect.
DS00003073A-page 42
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
6.0
PACKAGE INFORMATION
FIGURE 6-1:
Note:
400-PIN (27MM X 27MM) PBGA PACKAGE OUTLINE AND RECOMMENDED
LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2008-2019 Microchip Technology Inc.
DS00003073A-page 43
KSZ9692PB/KSZ9692XPB
APPENDIX A:
TABLE A-1:
DATA SHEET REVISION HISTORY
REVISION HISTORY
Revision
DS00003073A (06-11-19)
Section/Figure/Entry
Correction
Replaces previous Micrel version M9999-031810-4.0, March 2010; part number
changed from KSZ9692MPB to KSZ9692PB
Rev. 4.0 (01-28-10)
DDR Data Width Changed to 32-bit
Rev. 3.0 (08-10-09)
DDR Data Width Changed to 16-bit
Rev. 2.0 (03-10-09)
Power Sequencing, Added A1 (PMEN) to pin list, 1.3V Supply for Core, Power Consumption table
Rev. 1.0 (10-14-08)
Initial Release
DS00003073A-page 44
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
2008-2019 Microchip Technology Inc.
DS00003073A-page 45
KSZ9692PB/KSZ9692XPB
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
-
[X]
Temperature
Range
XXX
Package
Device:
KSZ9692PB, KSZ9692XPB
Temperature:
Blank
I
Package:
PB
=
XPB =
=
0C to
= -40C to
-
+70C
+85C
[X](1)
Tape and Reel
Option
(Commercial)
(Industrial)
Examples:
a)
KSZ9692PB
Commercial Temperature, 400-pin PBGA
RoHS Compliant Pkg, Tray
b)
KSZ9692PBI
Industrial Temperature, 400-pin PBGA
RoHS Complaint Pkg, Tray
c)
KSZ9692XPB(2)
Commercial Temperature, 400-pin PBGA
RoHS Compliant Pkg, Tray
400-pin PBGA
400-pin PBGA
Note 1:
Tape and Reel
Option:
Blank
TR
= Standard packaging (tray)
= Tape and Reel(1)
2:
DS00003073A-page 46
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Support for one PCI Master. No SDIO.
2008-2019 Microchip Technology Inc.
KSZ9692PB/KSZ9692XPB
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ,
Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINKME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere.
All other trademarks mentioned herein are property of their respective companies.
© 2008-2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522444633
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2008-2019 Microchip Technology Inc.
DS00003073A-page 47
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Finland - Espoo
Tel: 358-9-4520-820
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Tel: 86-769-8702-9880
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Tel: 81-3-6880- 3770
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Tel: 86-20-8755-8029
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Tel: 82-53-744-4301
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 86-571-8792-8115
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Tel: 82-2-554-7200
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
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Tel: 86-532-8502-7355
Philippines - Manila
Tel: 63-2-634-9065
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Israel - Ra’anana
Tel: 972-9-744-7705
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 512-257-3370
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Chicago
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Tel: 630-285-0071
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Dallas
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Tel: 972-818-7423
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Tel: 248-848-4000
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Tel: 281-894-5983
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Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
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Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS00003073A-page 48
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2008-2019 Microchip Technology Inc.
05/14/19
