KSZ9897RTXC

KSZ9897R 7-Port Gigabit Ethernet Switch with Two RGMII/MII/RMII Interfaces Highlights • Non-blocking wire-speed Ethernet switching fabric • Full-featured forwarding and filtering control, including Access Control List (ACL) filtering • Full VLAN and QoS support • Five ports with integrated 10/100/1000BASE-T PHY transceivers • Two ports with 10/100/1000 Ethernet MACs and configurable RGMII/MII/RMII interfaces • IEEE 802.1X access control support • EtherGreen™ power management features, including low power standby • Flexible management interface options: SPI, I2C, MIIM, and in-band management via any port • Commercial/Industrial temperature range support • 128-pin TQFP-EP (14 x 14mm) RoHS compliant pkg Target Applications • • • • • • • • Stand-alone 10/100/1000Mbps Ethernet switches VoIP infrastructure switches Broadband gateways/firewalls Wi-Fi access points Integrated DSL/cable modems Security/surveillance systems Industrial control/automation switches Networked measurement and control systems Features • Switch Management Capabilities - 10/100/1000Mbps Ethernet switch basic functions: frame buffer management, address look-up table, queue management, MIB counters - Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 4096 entry forwarding table with 256kByte frame buffer - Jumbo packet support up to 9000 bytes - Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port - MIB counters for fully-compliant statistics gathering 34 counters per port - Tail tagging mode (one byte added before FCS) support at host port to inform the processor which ingress port receives the packet and its priority - Loopback modes for remote failure diagnostics - Rapid spanning tree protocol (RSTP) support for topology management and ring/linear recovery - Multiple spanning tree protocol (MSTP) support  2022 Microchip Technology Inc. and its subsidiaries • Five Integrated PHY Ports - 1000BASE-T/100BASE-TX/10BASE-Te IEEE 802.3 Fast Link-up option significantly reduces link-up time Auto-negotiation and Auto-MDI/MDI-X support On-chip termination resistors and internal biasing for differential pairs to reduce power - LinkMD® cable diagnostic capabilities for determining cable opens, shorts, and length • Two Configurable External MAC Ports - Reduced Gigabit Media Independent Interface (RGMII) v2.0 - Reduced Media Independent Interface (RMII) v1.2 with 50MHz reference clock input/output option - Media Independent Interface (MII) in PHY/MAC mode • Advanced Switch Capabilities - IEEE 802.1Q VLAN support for 128 active VLAN groups and the full range of 4096 VLAN IDs - IEEE 802.1p/Q tag insertion/removal on per port basis - VLAN ID on per port or VLAN basis - IEEE 802.3x full-duplex flow control and half-duplex back pressure collision control - IEEE 802.1X access control (Port-based and MAC address based) - IGMP v1/v2/v3 snooping for multicast packet filtering - IPv6 multicast listener discovery (MLD) snooping - IPv4/IPv6 QoS support, QoS/CoS packet prioritization - 802.1p QoS packet classification with 4 priority queues - Programmable rate limiting at ingress/egress ports - Broadcast storm protection - Four priority queues with dynamic packet mapping for IEEE 802.1p, IPv4 DIFFSERV, IPv6 Traffic Class - MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets - Self-address filtering for implementing ring topologies • Comprehensive Configuration Registers Access - High-speed 4-wire SPI (up to 50MHz), I2C interfaces provide access to all internal registers - MII Management (MIIM, MDC/MDIO 2-wire) Interface provides access to all PHY registers - In-band management via any of the data ports - I/O pin strapping facility to set certain register bits from I/O pins at reset time - On-the-fly configurable control registers • Power Management - Energy detect power-down mode on cable disconnect Dynamic clock tree control Unused ports can be individually powered down Full-chip software power-down Wake-on-LAN (WoL) standby power mode with PME interrupt output for system wake upon triggered events DS00002330E-page 1 KSZ9897R TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. 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DS00002330E-page 2  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R Table of Contents 1.0 Preface ............................................................................................................................................................................................ 4 2.0 Introduction ..................................................................................................................................................................................... 8 3.0 Pin Descriptions and Configuration ................................................................................................................................................. 9 4.0 Functional Description .................................................................................................................................................................. 18 5.0 Device Registers ........................................................................................................................................................................... 63 6.0 Operational Characteristics ......................................................................................................................................................... 167 7.0 Design Guidelines ....................................................................................................................................................................... 182 8.0 Package Information ................................................................................................................................................................... 185 Appendix A: Data Sheet Revision History ......................................................................................................................................... 189 The Microchip Web Site .................................................................................................................................................................... 193 Customer Change Notification Service ............................................................................................................................................. 193 Customer Support ............................................................................................................................................................................. 193 Product Identification System ........................................................................................................................................................... 194  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 3 KSZ9897R 1.0 PREFACE 1.1 Glossary of Terms TABLE 1-1: GENERAL TERMS Term Description 10BASE-Te 10 Mbps Ethernet, 2.5V signaling, IEEE 802.3 compliant 100BASE-TX 100 Mbps Fast Ethernet, IEEE 802.3u compliant 1000BASE-T 1000 Mbps Gigabit Ethernet, IEEE 802.3ab compliant ADC Analog-to-Digital Converter AN Auto-Negotiation BLW Baseline Wander BPDU Bridge Protocol Data Unit. Messages which carry the Spanning Tree Protocol information. Byte 8 bits CRC Cyclic Redundancy Check. A common technique for detection data transmission errors. CRC for Ethernet is 32 bits long. CSR Control and Status Registers DA Destination Address DWORD 32 bits FCS Frame Check Sequence. The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction. FID Frame or Filter ID. Specifies the frame identifier. Alternately is the filter identifier. FIFO First In First Out buffer FSM Finite State Machine GPIO General Purpose I/O Host External system (Includes processor, application software, etc.) IGMP Internet Group Management Protocol. Defined by RFC 1112, RFC 2236, and RFC 4604 to establish multicast group membership in IPv4 networks. IPG Inter-Packet Gap. A time delay between successive data packets mandated by the network standard for protocol reasons. Jumbo Packet A packet larger than the standard Ethernet packet (1518 bytes). Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc.. lsb Least Significant Bit LSB Least Significant Byte MAC Media Access Controller. A functional block responsible for implementing the media access control layer, which is a sublayer of the data link layer. MDI Medium Dependent Interface. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDIX Media Independent Interface with Crossover. An Ethernet port connection that allows networked end stations (i.e., PCs or workstations) to connect to each other using a null-modem, or crossover, cable. MIB Management Information Base. The MIB comprises the management portion of network devices. This can include monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). MII Media Independent Interface. The MII accesses PHY registers as defined in the IEEE 802.3 specification. MIIM Media Independent Interface Management DS00002330E-page 4  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 1-1: GENERAL TERMS (CONTINUED) Term Description MLD Multicast Listening Discovery. This protocol is defined by RFC 3810 and RFC 4604 to establish multicast group membership in IPv6 networks. MLT-3 Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. msb Most Significant Bit MSB Most Significant Byte NRZ Non Return to Zero. A type of signal data encoding whereby the signal does not return to a zero state in between bits. NRZI Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and leaves the signal unchanged for a “0” N/A Not Applicable NC No Connect OUI Organizationally Unique Identifier PHY A device or function block which performs the physical layer interface function in a network. PLL Phase Locked Loop. A electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. RTC Real-Time Clock SA Source Address SFD Start of Frame Delimiter. The 8-bit value indicating the end of the preamble of an Ethernet frame. SQE Signal Quality Error (also known as “heartbeat”) SSD Start of Stream Delimiter TCP Transmission Control Protocol UDP User Datagram Protocol - A connectionless protocol run on top of IP networks UTP Unshielded Twisted Pair. Commonly a cable containing 4 twisted pairs of wire. UUID Universally Unique IDentifier VLAN Virtual Local Area Network WORD 16 bits  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 5 KSZ9897R 1.2 Buffer Types TABLE 1-2: BUFFER TYPES Buffer Type I Description Input IPU IPU/O IPD IPD/O O8 Input with internal pull-up (58 k ±30%) Input with internal pull-up (58 k ±30%) during power-up/reset; output pin during normal operation Input with internal pull-down (58 k ±30%) Input with internal pull-down (58 k ±30%) during power-up/reset; output pin during normal operation Output with 8 mA sink and 8 mA source O24 Output with 24 mA sink and 24 mA source OPU Output (8mA) with internal pull-up (58 k ±30%) OPD Output (8mA) with internal pull-down (58 k ±30%) A Analog AIO Analog bidirectional ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin P Power GND Ground Note: Refer to Section 6.3, "Electrical Characteristics," on page 168 for the electrical characteristics of the various buffers. DS00002330E-page 6  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 1.3 Register Nomenclature TABLE 1-3: REGISTER NOMENCLATURE Register Bit Type Notation R Read: A register or bit with this attribute can be read. W Write: A register or bit with this attribute can be written. RO Read only: Read only. Writes have no effect. RC Read to Clear: Contents is cleared after the read. Writes have no effect. WO Write only: If a register or bit is write-only, reads will return unspecified data. WC Write One to Clear: Writing a one clears the value. Writing a zero has no effect. LL Latch Low: Applies to certain RO status bits. If a status condition causes this bit to go low, it will maintain the low state until read, even if the status condition changes. A read clears the latch, allowing the bit to go high if dictated by the status condition. LH Latch High: Applies to certain RO status bits. If a status condition causes this bit to go high, it will maintain the high state until read, even if the status condition changes. A read clears the latch, allowing the bit to go low if dictated by the status condition. SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no effect. Contents can be read. RESERVED 1.4 Register Bit Description Reserved Field: Reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. The value of reserved bits is not guaranteed on a read. References • NXP I2C-Bus Specification (UM10204, April 4, 2014): www.nxp.com/documents/user_manual/UM10204.pdf  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 7 KSZ9897R 2.0 INTRODUCTION 2.1 General Description The KSZ9897R is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2 managed Gigabit Ethernet switch, five 10BASE-Te/100BASE-TX/1000BASE-T physical layer transceivers (PHYs) and associated MAC units, and two MAC ports with individually configurable RGMII/MII/RMII interfaces for direct connection to a host processor/controller, another Ethernet switch, or an Ethernet PHY transceiver. The KSZ9897R is built upon industry-leading Ethernet technology, with features designed to offload host processing and streamline the overall design: • • • • • • Non-blocking wire-speed Ethernet switch fabric supports 1 Gbps on RGMII Full-featured forwarding and filtering control, including port-based Access Control List (ACL) filtering Full VLAN and QoS support Traffic prioritization with per-port ingress/egress queues and by traffic classification Spanning Tree support IEEE 802.1X access control support A host processor can access all KSZ9897R registers for control over all PHY, MAC, and switch functions. Full register access is available via the integrated SPI or I2C interfaces, and by in-band management via any one of the data ports. PHY register access is provided by a MIIM interface. Flexible digital I/O voltage allows the MAC port to interface directly with a 1.8/2.5/3.3V host processor/controller/FPGA. Additionally, a robust assortment of power-management features including Wake-on-LAN (WoL) for low power standby operation, have been designed to satisfy energy-efficient system requirements. The KSZ9897R is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal block diagram of the KSZ9897R is shown in Figure 2-1. FIGURE 2-1: INTERNAL BLOCK DIAGRAM GMAC 1 GMAC 6 RGMII/MII/RMII Port 2 10/100/1000 PHY 2 GMAC 2 GMAC 7 RGMII/MII/RMII Port 3 10/100/1000 PHY 3 GMAC 3 Port 4 10/100/1000 PHY 4 GMAC 4 Port 5 10/100/1000 PHY 5 GMAC 5 Control Registers KSZ9897R DS00002330E-page 8 Queue Management, QOS, Etc. 10/100/1000 PHY 1 Switch Engine Port 1 Address Lookup MIB Counters Frame Buffers Queue Mgmt. SPI/I2C/MIIM  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 3.0 PIN DESCRIPTIONS AND CONFIGURATION 3.1 Pin Assignments The device pin diagram for the KSZ9897R can be seen in Figure 3-1. Table 3-1 provides a KSZ9897R pin assignment table. Pin descriptions are provided in Section 3.2, "Pin Descriptions". PIN ASSIGNMENTS (TOP VIEW) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RESET_N CLKO_25_125 INTRP_N PME_N LED2_1 LED2_0 NC LED3_1 LED3_0 DVDDL LED4_1 LED4_0 GND RXD7_0 RXD7_1 RXD7_2 RXD7_3 CRS7 RX_ER7 VDDIO RX_DV7/CRS_DV7/RX_CTL7 RX_CLK7/REFCLKO7 DVDDL TXD7_0 TXD7_1 TXD7_2 TXD7_3 COL7 TX_ER7 TX_EN7/TX_CTL7 TX_CLK7/REFCLKI7 RXD6_0 FIGURE 3-1: 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 KSZ9897R 128-TQFP-EP (Top View) GND (Connect exposed pad to ground with a via field) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RXD6_1 RXD6_2 RXD6_3 VDDIO CRS6 RX_ER6 RX_DV6/CRS_DV6/RX_CTL6 RX_CLK6/REFCLKO6 DVDDL TXD6_0 TXD6_1 TXD6_2 TXD6_3 COL6 TX_ER6 TX_EN6/TX_CTL6 TX_CLK6/REFCLKI6 GND GND DVDDL AVDDH TXRX4M_D TXRX4P_D AVDDL TXRX4M_C TXRX4P_C TXRX4M_B TXRX4P_B AVDDL TXRX4M_A TXRX4P_A AVDDH TXRX1P_A TXRX1M_A AVDDL TXRX1P_B TXRX1M_B TXRX1P_C TXRX1M_C TXRX1P_D TXRX1M_D AVDDH DVDDL TXRX2P_A TXRX2M_A AVDDL TXRX2P_B TXRX2M_B TXRX2P_C TXRX2M_C AVDDL TXRX2P_D TXRX2M_D AVDDH DVDDL TXRX3P_A TXRX3M_A TXRX3P_B TXRX3M_B TXRX3P_C TXRX3M_C AVDDL TXRX3P_D TXRX3M_D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SDO SDI/SDA/MDIO VDDIO SCS_N SCL/MDC LED5_0 LED5_1 DVDDL LED1_0 LED1_1 GND NC GND DVDDL AVDDH TXRX5P_A TXRX5M_A AVDDL TXRX5P_B TXRX5M_B TXRX5P_C TXRX5M_C AVDDL TXRX5P_D TXRX5M_D AVDDH GND AVDDL XO XI ISET AVDDH Note: When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example, RESET_N indicates that the reset signal is active low. The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Section 3.2, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 9 KSZ9897R TABLE 3-1: PIN ASSIGNMENTS Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name 1 TXRX1P_A 33 AVDDH 65 RXD6_0 (Note 3-1) 97 SDO 2 TXRX1M_A 34 TXRX4P_A 66 TX_CLK7/REFCLKI7 98 SDI/SDA/MDIO 3 AVDDL 35 TXRX4M_A 67 TX_EN7/TX_CTL7 99 VDDIO 4 TXRX1P_B 36 AVDDL 68 TX_ER7 100 SCS_N 5 TXRX1M_B 37 TXRX4P_B 69 COL7 101 SCL/MDC 6 TXRX1P_C 38 TXRX4M_B 70 TXD7_3 102 LED5_0 7 TXRX1M_C 39 TXRX4P_C 71 TXD7_2 103 LED5_1 (Note 3-1) 8 TXRX1P_D 40 TXRX4M_C 72 TXD7_1 104 DVDDL 9 TXRX1M_D 41 AVDDL 73 TXD7_0 105 LED1_0 10 AVDDH 42 TXRX4P_D 74 DVDDL 106 LED1_1 (Note 3-1) 11 DVDDL 43 TXRX4M_D 75 12 TXRX2P_A 44 AVDDH 76 RX_CLK7/REFCLKO7 107 RX_DV7/CRS_DV7/ RX_CTL7 (Note 3-1) 108 NC 13 TXRX2M_A 45 DVDDL 77 VDDIO 109 GND 14 AVDDL 46 GND 78 RX_ER7 110 DVDDL 15 TXRX2P_B 47 GND 79 CRS7 111 AVDDH GND 16 TXRX2M_B 48 TX_CLK6/REFCLKI6 80 RXD7_3 (Note 3-1) 112 TXRX5P_A 17 TXRX2P_C 49 TX_EN6/TX_CTL6 81 RXD7_2 (Note 3-1) 113 TXRX5M_A 18 TXRX2M_C 50 TX_ER6 82 RXD7_1 (Note 3-1) 114 AVDDL 19 AVDDL 51 COL6 83 RXD7_0 (Note 3-1) 115 TXRX5P_B 20 TXRX2P_D 52 TXD6_3 84 GND 116 TXRX5M_B 21 TXRX2M_D 53 TXD6_2 85 LED4_0 (Note 3-1) 117 TXRX5P_C 22 AVDDH 54 TXD6_1 86 LED4_1 (Note 3-1) 118 TXRX5M_C 23 DVDDL 55 TXD6_0 87 DVDDL 119 AVDDL 24 TXRX3P_A 56 DVDDL 88 LED3_0 120 TXRX5P_D 25 TXRX3M_A 57 RX_CLK6/REFCLKO6 89 LED3_1 (Note 3-1) 121 TXRX5M_D 26 TXRX3P_B 58 RX_DV6/CRS_DV6/ RX_CTL6 90 NC 122 AVDDH 27 TXRX3M_B 59 RX_ER6 91 LED2_0 (Note 3-1) 123 GND 28 TXRX3P_C 60 CRS6 92 LED2_1 (Note 3-1) 124 AVDDL PME_N 125 XO 29 TXRX3M_C 61 VDDIO 93 30 AVDDL 62 RXD6_3 (Note 3-1) 94 INTRP_N 126 XI 31 TXRX3P_D 63 RXD6_2 (Note 3-1) 95 CLKO_25_125 127 ISET 32 TXRX3M_D 64 RXD6_1 (Note 3-1) 96 RESET_N 128 AVDDH Exposed Pad Must be Connected to GND Note 3-1 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. DS00002330E-page 10  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 3.2 Pin Descriptions This sections details the functions of the various device signals. TABLE 3-2: PIN DESCRIPTIONS BUFFER TYPE NAME SYMBOL Port 5-1 Ethernet TX/RX Pair A + TXRX[5:1]P_A Port 5-1 Ethernet TX/RX Pair A - TXRX[5:1]M_A Port 5-1 Ethernet TX/RX Pair B + TXRX[5:1]P_B Port 5-1 Ethernet TX/RX Pair B - TXRX[5:1]M_B Port 5-1 Ethernet TX/RX Pair C + TXRX[5:1]P_C AIO Port 5-1 1000BASE-T Differential Data Pair C (+) Port 5-1 Ethernet TX/RX Pair C - TXRX[5:1]M_C AIO Port 5-1 1000BASE-T Differential Data Pair C (-) Port 5-1 Ethernet TX/RX Pair D + TXRX[5:1]P_D AIO Port 5-1 1000BASE-T Differential Data Pair D (+) Port 5-1 Ethernet TX/RX Pair D - TXRX[5:1]M_D AIO Port 5-1 1000BASE-T Differential Data Pair D (-) DESCRIPTION Ports 5-1 Gigabit Ethernet Pins AIO Port 5-1 1000BASE-T Differential Data Pair A (+) Note: AIO Port 5-1 1000BASE-T Differential Data Pair A (-) Note: AIO 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. Port 5-1 1000BASE-T Differential Data Pair B (+) Note: AIO 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. Port 5-1 1000BASE-T Differential Data Pair B (-) Note: 100BASE-TX and 10BASE-Te are also supported on the A and B pairs. Ports 7-6 RGMII/MII/RMII Pins Port 7-6 Transmit/ Reference Clock TX_CLK[7:6]/ REFCLKI[7:6] I/O8 MII Mode: TX_CLK[7:6] is the Port 7-6 25/2.5MHz Transmit Clock. In PHY mode this pin is an output, in MAC mode it is an input. RMII Mode: REFCLKI[7:6] is the Port 7-6 50MHz Reference Clock input when in RMII Normal mode. This pin is unused when in RMII Clock mode. RGMII Mode: TX_CLK[7:6] is the Port 7-6 125/25/2.5MHz Transmit Clock input. Port 7-6 Transmit Enable/Control TX_EN[7:6]/ TX_CTL[7:6] IPD MII/RMII Modes: TX_EN[7:6] is the Port 7-6 Transmit Enable. RGMII Mode: TX_CTL[7:6] is the Port 7-6 Transmit Control. Port 7-6 Transmit Error TX_ER[7:6] IPD MII Mode: Port 7-6 Transmit Error input. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 11 KSZ9897R TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Port 7-6 Collision Detect COL[7:6] IPD/O8 DESCRIPTION MII Mode: Port 7-6 Collision Detect. In PHY mode this pin is an output, in MAC mode it is an input. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. Port 7-6 Transmit Data 3 TXD[7:6]_3 IPD MII/RGMII Modes: Port 7-6 Transmit Data bus bit 3. RMII Mode: Not used. Do not connect this pin in this mode of operation. Port 7-6 Transmit Data 2 TXD[7:6]_2 IPD MII/RGMII Modes: Port 7-6 Transmit Data bus bit 2. RMII Mode: Not used. Do not connect this pin in this mode of operation. Port 7-6 Transmit Data 1 TXD[7:6]_1 IPD MII/RMII/RGMII Modes: Port 7-6 Transmit Data bus bit 1. Port 7-6 Transmit Data 0 TXD[7:6]_0 IPD MII/RMII/RGMII Modes: Port 7-6 Transmit Data bus bit 0. Port 7-6 Receive/ Reference Clock RX_CLK[7:6]/ REFCLKO[7:6] I/O24 MII Mode: RX_CLK[7:6] is the Port 7-6 25/2.5MHz Receive Clock. In PHY mode this pin is an output, in MAC mode it is an input. RMII Mode: REFCLKO[7:6] is the Port 7-6 50MHz Reference Clock output when in RMII Clock mode. This pin is unused when in RMII Normal mode. RGMII Mode: RX_CLK[7:6] is the Port 7-6 125/25/2.5MHz Receive Clock output. Port 7-6 Receive Data Valid / Carrier Sense / Control RX_DV[7:6]/ CRS_DV[7:6]/ RX_CTL[7:6] IPD/O24 MII Mode: RX_DV[7:6] is the Port 7-6 Received Data Valid output. RMII Mode: CRS_DV[7:6] is the Carrier Sense / Receive Data Valid output. RGMII Mode: RX_CTL[7:6] is the Receive Control output. Note: Port 7-6 Receive Error RX_ER[7:6] IPD/O24 The RX_DV7/CRS_DV7/RX_CTL7 pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. MII/RMII Modes: Port 7-6 Receive Error output. RGMII Modes: Not used. Do not connect this pin in this mode of operation. Port 7-6 Carrier Sense CRS[7:6] IPD/O8 MII Mode: Port 7-6 Carrier Sense. In PHY mode this pin is an output, in MAC mode it is an input. RMII/RGMII Modes: Not used. Do not connect this pin in these modes of operation. DS00002330E-page 12  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Port 7-6 Receive Data 3 RXD[7:6]_3 IPD/O24 DESCRIPTION MII/RGMII Modes: Port 7-6 Receive Data bus bit 3. RMII Mode: Not used. Do not connect this pin in this mode of operation. Note: Port 7-6 Receive Data 2 RXD[7:6]_2 IPD/O24 These pins also provide configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. MII/RGMII Modes: Port 7-6 Receive Data bus bit 2. RMII Mode: Not used. Do not connect this pin in this mode of operation. Note: Port 7-6 Receive Data 1 RXD[7:6]_1 Port 7-6 Receive Data 0 RXD[7:6]_0 IPD/O24 MII/RMII/RGMII Modes: Port 7-6 Receive Data bus bit 1. Note: IPD/O24 These pins also provide configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. These pins also provide configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. MII/RMII/RGMII Modes: Port 7-6 Receive Data bus bit 0. Note: These pins also provide configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. SPI/I2C/MIIM Interface Pins SPI/I2C/MIIM SCL/MDC IPU SDO O8 SPI/I2C Modes: SCL serial clock. Serial Clock MIIM Mode: MDC serial clock. SPI Data Out SPI Mode: Data out (also known as MISO). I2C/MIIM Modes: Not used. SPI Data In / I2C/MIIM Data In/Out SDI/SDA/MDIO IPU/O8 SPI Mode: SDI Data In (also known as MOSI). I2C Mode: SDA Data In/Out. MIIM Mode: MDIO Data In/Out. SDI and MDIO are open-drain signals when in the output state. An external pull-up resistor to VDDIO (1.0kΩ to 4.7kΩ) is required. SPI Chip Select SCS_N IPU SPI Mode: Chip Select (active low). I2C/MIIM Modes: Not used.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 13 KSZ9897R TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Port 1 LED Indicator 0 LED1_0 IPU/O8 Port 1 LED Indicator 0. Active low output sinks current to light an external LED. Port 1 LED Indicator 1 LED1_1 IPU/O8 Port 1 LED Indicator 1. Active low output sinks current to light an external LED. DESCRIPTION LED Pins Note: Port 2 LED Indicator 0 LED2_0 IPU/O8 Port 2 LED Indicator 0. Active low output sinks current to light an external LED. Note: Port 2 LED Indicator 1 LED2_1 IPU/O8 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 2 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 3 LED Indicator 0 LED3_0 IPU/O8 Port 3 LED Indicator 0. Active low output sinks current to light an external LED. Port 3 LED Indicator 1 LED3_1 IPU/O8 Port 3 LED Indicator 1. Active low output sinks current to light an external LED. Note: Port 4 LED Indicator 0 LED4_0 IPU/O8 Port 4 LED Indicator 0. Active low output sinks current to light an external LED. Note: Port 4 LED Indicator 1 LED4_1 IPU/O8 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 4 LED Indicator 1. Active low output sinks current to light an external LED. Note: This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information. Port 5 LED Indicator 0 LED5_0 IPU/O8 Port 5 LED Indicator 0. Active low output sinks current to light an external LED. Port 5 LED Indicator 1 LED5_1 IPU/O8 Port 5 LED Indicator 1. Active low output sinks current to light an external LED. Note: DS00002330E-page 14 This pin also provides configuration strap functions during hardware/software resets. Refer to Section 3.2.1, "Configuration Straps" for additional information.  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Interrupt INTRP_N OPU DESCRIPTION Miscellaneous Pins Active low, open-drain interrupt. Note: Power Management Event O8 PME_N This pin requires an external pull-up resistor. Power Management Event. This output signal indicates that an energy detect event has occurred. It is intended to wake up the system from a low power mode. Note: The assertion polarity is programmable (default active low). An external pull-up resistor is required for active-low operation; an external pull-down resistor is required for active-high operation. System Reset RESET_N IPU Active low system reset. The device must be reset either during or after power-on. An RC circuit is suggested for power-on reset. Crystal Clock / Oscillator Input XI ICLK Crystal clock / oscillator input. When using a 25MHz crystal, this input is connected to one lead of the crystal. When using an oscillator, this pin is the input from the oscillator. The crystal oscillator should have a tolerance of ±50ppm. Crystal Clock Output XO OCLK Crystal clock / oscillator output. When using a 25MHz crystal, this output is connected to one lead of the crystal. When using an oscillator, this pin is left unconnected. 25/125MHz Reference Clock Output CLKO_25_125 O24 25/125MHz reference clock output, derived from the crystal input. Transmit Output Current Set Resistor ISET A Transmit output current set resistor. This pin configures the physical transmit output current. It must be connected to GND through a 6.04kΩ 1% resistor. No Connect NC - No Connect. For proper operation, this pin must be left unconnected. +3.3/2.5/1.8V I/O Power VDDIO P +3.3V / +2.5V / +1.8V I/O Power +2.5V Analog Power AVDDH P +2.5V Analog Power +1.2V Analog Power AVDDL P +1.2V Analog Power +1.2V Digital Power DVDDL P +1.2V Digital Power Ground GND GND Power/Ground Pins  2022 Microchip Technology Inc. and its subsidiaries Ground (pins and pad) DS00002330E-page 15 KSZ9897R 3.2.1 CONFIGURATION STRAPS The KSZ9897R utilizes configuration strap pins to configure the device for different modes. While RESET_N is low, these pins are hi-Z. Pull-up/down resistors are used to create high or low states on these pins, which are internally sampled at the rising edge of RESET_N. All of these pins have a weak internal pull-up or pull-down resistor which provides a default level for strapping. To strap an LED pin low, use a 750Ω to 1kΩ external pull-down resistor. To strap any nonLED pin high, use an external 1kΩ to 10kΩ pull-up resistor to VDDIO. Once RESET_N is high, all of these pins become driven outputs. Because the internal pull-up/down resistors are not strong, consideration must be given to any other pull-up/down resistors which may reside on the board or inside a device connected to these pins. When an LED pin is directly driving an LED, the effect of the LED and LED load resistor on the strapping level must be considered. This is the reason for using a small value resistor to pull an LED pin low. This is especially true when an LED is powered from a voltage that is higher than VDDIO. The configuration strap pins and their associated functions are detailed in Table 3-3. TABLE 3-3: CONFIGURATION STRAP DESCRIPTIONS CONFIGURATION STRAP PIN DESCRIPTION LED1_1 Flow Control (All Ports) 0: Flow control disabled 1: Flow control enabled (Default) LED2_1 Link-up Mode (All PHYs) 0: Fast Link-up: Auto-negotiation and auto MDI/MDI-X are disabled 1: Normal Link-up: Auto-negotiation and auto MDI/MDI-X are enabled (Default) Note: Since Fast Link-up disables auto-negotiation and auto-crossover, it is suitable only for specialized applications. LED4_0, LED2_0 When LED2_1 = 1 at strap-in (Normal Link-up): [LED4_0, LED2_0]: Auto-Negotiation Enable (All PHYs) / NAND Tree Test Mode 00: Reserved 01: Auto-negotiation disabled, forced as 100 Mbps and half duplex. Auto-MDI-X is on. 10: NAND Tree test mode 11: Auto-negotiation enabled (Default) When LED2_1 = 0 at strap-in (Fast Link-up; All PHYs Full-Duplex; Auto-negotiation and Auto-MDI-X are off): LED2_0: 1000BASE-T Master/Slave Mode, 100BASE-T MDI/MDI-X Mode (All PHYs) 0: 1000BASE-T: Slave Mode 100BASE-T: MDI-X 1: 1000BASE-T: Master Mode (Default) 100BASE-T: MDI (Default) LED4_0: PHY Speed Select (All PHYs) 0: 1000BASE-T 1: 100BASE-TX (Default) LED4_1, LED3_1 [LED4_1, LED3_1]: Management Interface Mode 00: MIIM (MDIO) 01: I2C 1x: SPI (Default) LED5_1 RXD6_3, RXD6_2 DS00002330E-page 16 Switch Enable at Startup 0: Start Switch is disabled. The switch will not forward packets until the Start Switch bit is set in the Switch Operation Register. 1: Start Switch is enabled. The switch will forward packets immediately after reset. (Default) [RXD6_3, RXD6_2]: Port 6 Mode 00: RGMII (Default) 01: RMII 10: Reserved 11: MII  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 3-3: CONFIGURATION STRAP DESCRIPTIONS (CONTINUED) CONFIGURATION STRAP PIN DESCRIPTION RXD6_1 Port 6 MII/RMII Mode 0: MII: PHY Mode (Default) RMII: Clock Mode. RMII 50MHz reference clock is output on REFCLKO6. (Default) RGMII: No effect 1: MII: MAC Mode RMII: Normal Mode. RMII 50MHz reference clock is input on REFCLKI6. RGMII: No effect RXD6_0 Port 6 Speed Select 0: 1000Mbps Mode (Default) 1: 100Mbps Mode Note: RXD7_3, RXD7_2 If Port 6 is configured for MII or RMII, set the speed to 100Mbps. [RXD7_3, RXD7_2]: Port 7 Mode 00: RGMII (Default) 01: RMII 10: Reserved 11: MII RXD7_1 Port 7 MII/RMII Mode 0: MII: PHY Mode (Default) RMII: Clock Mode. RMII 50MHz reference clock is output on REFCLKO7. (Default) RGMII: No effect 1: MII: MAC Mode RMII: Normal Mode. RMII 50MHz reference clock is input on REFCLKI7. RGMII: No effect RXD7_0 Port 7 Speed Select 0: 1000Mbps Mode (Default) 1: 100Mbps Mode Note: If Port 7 is configured for MII or RMII, set the speed to 100Mbps. RX_DV7/CRS_DV7/ In-Band Management RX_CTL7 0: Disable In-Band Management (Default) 1: Enable In-Band Management Note: If using I2C, do not enable IBA.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 17 KSZ9897R 4.0 FUNCTIONAL DESCRIPTION This section provides functional descriptions for the following: • • • • • • • • • • • Physical Layer Transceiver (PHY) LEDs Media Access Controller (MAC) Switch NAND Tree Support Clocking Power Power Management Management Interface In-Band Management MAC Interface (RGMII/MII/RMII Port 6-7) 4.1 Physical Layer Transceiver (PHY) Ports 1 through 5 include completely integrated triple-speed (10BASE-Te, 100BASE-TX, 1000BASE-T) Ethernet physical layer transceivers for transmission and reception of data over standard four-pair unshielded twisted pair (UTP), CAT5 or better Ethernet cable. The device reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs, eliminating the need for external termination resistors. The internal chip termination and biasing provides significant power savings when compared with using external biasing and termination resistors. The device can automatically detect and correct for differential pair misplacements and polarity reversals, and correct for propagation delay differences between the four differential pairs, as specified in the IEEE 802.3 standard for 1000BASE-T operation. 4.1.1 1000BASE-T TRANSCEIVER The 1000BASE-T transceiver is based on a mixed-signal/digital signal processing (DSP) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, a precision clock recovery scheme, and power-efficient line drivers. 4.1.1.1 Analog Echo Cancellation Circuit In 1000BASE-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit relieves the burden of the ADC and the adaptive equalizer. This circuit is disabled in 10BASE-Te/100BASE-TX mode. 4.1.1.2 Automatic Gain Control (AGC) In 1000BASE-T mode, the automatic gain control circuit provides initial gain adjustment to boost up the signal level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal. 4.1.1.3 Analog-to-Digital Converter (ADC) In 1000BASE-T mode, the analog-to-digital converter digitizes the incoming signal. ADC performance is essential to the overall performance of the transceiver. This circuit is disabled in 10BASE-Te/100BASE-TX mode. 4.1.1.4 Timing Recovery Circuit In 1000BASE-T mode, the mixed signal clock recovery circuit, together with the digital phase locked loop (PLL), is used to recover and track the incoming timing information from the received data. The digital PLL has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal. The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This also helps to facilitate echo cancellation and NEXT removal. DS00002330E-page 18  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.1.1.5 Adaptive Equalizer In 1000BASE-T mode, the adaptive equalizer provides the following functions: • Detection for partial response signaling • Removal of NEXT and ECHO noise • Channel equalization Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch. The device uses a digital echo canceler to further reduce echo components on the receive signal. In 1000BASE-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels). This results in high-frequency cross-talk coming from adjacent wires. The device uses three NEXT cancelers on each receive channel to minimize the cross-talk induced by the other three channels. In 10BASE-Te/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. 4.1.1.6 Trellis Encoder and Decoder In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. On the receiving side, the idle stream is examined first. The scrambler seed, pair skew, pair order and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-bit symbols and de-scrambled into 8-bit data. 4.1.2 4.1.2.1 100BASE-TX TRANSCEIVER 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external ISET resistor sets the output current for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-Te output driver is also incorporated into the 100BASETX driver. 4.1.2.2 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/ 5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC. 4.1.2.3 Scrambler/De-Scrambler The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. The scrambler is used only for 100BASE-TX. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 19 KSZ9897R 4.1.3 10BASE-Te TRANSCEIVER 10BASE-Te is an energy-efficient version of 10BASE-T which is powered from a 2.5V supply. It has a reduced transmit signal amplitude and requires Cat5 cable. It is inter-operable to 100m with 10BASE-T when Cat5 cable is used. 4.1.3.1 10BASE-Te Transmit The 10BASE-Te driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with typical 1.75V amplitude (compared to the typical transmit amplitude of 2.5V for 10BASE-T). The harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 4.1.3.2 10BASE-Te Receive On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RXP1 or RXM1 input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the device decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. 4.1.4 AUTO MDI/MDI-X The automatic MDI/MDI-X feature, also known as auto crossover, eliminates the need to determine whether to use a straight cable or a crossover cable between the device and its link partner. The auto-sense function detects the MDI/ MDI-X pair mapping from the link partner, and assigns the MDI/MDI-X pair mapping of the device accordingly. Table 41 shows the device’s 10/100/1000 Mbps pin configuration assignments for MDI and MDI-X pin mapping. TABLE 4-1: MDI/MDI-X PIN DEFINITIONS Pin (RJ45 pair) MDI 1000BASE-T 100BASE-TX MDI-X 10BASE-Te 1000BASE-T 100BASE-TX 10BASE-Te TXRXxP/M_A (1,2) A+/- TX+/- TX+/- B+/- RX+/- RX+/- TXRXxP/M_B (3,6) B+/- RX+/- RX+/- A+/- TX+/- TX+/- TXRXxP/M_C (4,5) C+/- Not used Not used D+/- Not used Not used TXRXxP/M_D (7,8) D+/- Not used Not used C+/- Not used Not used Auto MDI/MDI-X is enabled by default. It can be disabled through the port control registers. If Auto MDI/MDI-X is disabled, the port control register can also be used to select between MDI and MDI-X settings. An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X. 4.1.5 PAIR-SWAP, ALIGNMENT, AND POLARITY CHECK In 1000Base-T mode, the device: • Detects incorrect channel order and automatically restores the pair order for the A and B pairs. This is also done separately for the C and D pairs. Crossing of A or B pairs to C or D pairs is not corrected. • Supports 50±10ns difference in propagation delay between pairs of channels in accordance with the IEEE 802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchronized. Incorrect pair polarities of the differential signals are automatically corrected for all speeds. 4.1.6 WAVE SHAPING, SLEW-RATE CONTROL, AND PARTIAL RESPONSE In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. • For 1000BASE-T, a special partial-response signaling method is used to provide the bandwidth-limiting feature for the transmission path. • For 100BASE-TX, a simple slew-rate control method is used to minimize EMI. • For 10BASE-Te, pre-emphasis is used to extend the signal quality through the cable. DS00002330E-page 20  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.1.7 AUTO-NEGOTIATION The device conforms to the auto-negotiation protocol as described by IEEE 802.3. Auto-negotiation allows each port to operate at either 10BASE-Te, 100BASE-TX or 1000BASE-T by allowing link partners to select the best common mode of operation. During auto-negotiation, the link partners advertise capabilities across the link to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. With parallel detection, the duplex will always be half-duplex. The following list shows the speed and duplex operation mode from highest to lowest priority. • • • • • • Priority 1: 1000BASE-T, full-duplex Priority 2: 1000BASE-T, half-duplex Priority 3: 100BASE-TX, full-duplex Priority 4: 100BASE-TX, half-duplex Priority 5: 10BASE-Te, full-duplex Priority 6: 10BASE-Te, half-duplex If the KSZ9897R link partner doesn’t support auto-negotiation or is forced to bypass auto-negotiation for 10BASE-Te and 100BASE-TX modes, the KSZ9897R port sets its operating speed by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ9897R to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation advertisement protocol. The auto-negotiation link-up process is shown in Figure 4-1. FIGURE 4-1: AUTO-NEGOTIATION AND PARALLEL OPERATION  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 21 KSZ9897R For 1000BASE-T mode, auto-negotiation is always required to establish a link. During 1000BASE-T auto-negotiation, the master and slave configuration is first resolved between link partners. Then the link is established with the highest common capabilities between link partners. Auto-negotiation is enabled by default after power-up or hardware reset. Afterwards, auto-negotiation can be enabled or disabled via bit 12 of the PHY Basic Control Register. If auto-negotiation is disabled, the speed is set by bits 6 and 13 of the PHY Basic Control Register, and the duplex is set by bit 8. If the speed is changed on the fly, the link goes down and either auto-negotiation or parallel detection initiate until a common speed between the KSZ9897R and its link partner is re-established for a link. If link is already established and there is no change of speed on the fly, the changes (for example, duplex and pause capabilities) will not take effect unless either auto-negotiation is restarted through bit 9 of the PHY Basic Control Register, or a link-down to link-up transition occurs (i.e. disconnecting and reconnecting the cable). After auto-negotiation is completed, the link status is updated in the PHY Basic Status Register, and the link partner capabilities are updated in the PHY Auto-Negotiation Link Partner Ability Register, PHY Auto-Negotiation Expansion Status Register, and PHY 1000BASE-T Status Register. 4.1.8 FAST LINK-UP Link up time is normally determined by the time it takes to complete auto-negotiation. Additional time may be added by the auto MDI/MDI-X feature. The total link up time from power-up or cable connect is typically a second or more. Fast Link-up mode significantly reduces 100BASE-TX link-up time by disabling both auto-negotiation and auto MDI/ MDI-X, and fixing the TX and RX channels. This mode is enabled or disabled by the LED2_1 strapping option. It is not set by registers, so fast link-up is available immediately upon power-up. Fast Link-up is available at power-up only for 100BASE-TX link speed, which is selected by strapping the LED4_0 pin high. Fast Link-up is also available for 10BASETe, but this link speed must first be selected via a register write. Fast Link-up is intended for specialized applications where both link partners are known in advance. The link must also be known so that the fixed transmit channel of one device connects to the fixed receive channel of the other device, and vice versa. The TX and RX channel assignments are determined by the MDI/MDI-X strapping option on LED2_0. If a device in Fast Link-up mode is connected to a normal device (auto-negotiate and auto-MDI/MDI-X), there will be no problems linking, but the speed advantage of Fast Link-up will not be realized. For more information on configuration straps, refer to Section 3.2.1, "Configuration Straps," on page 16. 4.1.9 LinkMD® CABLE DIAGNOSTICS The LinkMD® function utilizes Time Domain Reflectometry (TDR) to analyze the cabling for common cabling problems, such as open circuits, short circuits and impedance mismatches. LinkMD® works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, and then analyzing the shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD® function processes this TDR information and presents it as a numerical value that can be translated to a cable distance. A LinkMD test is initiated individually for each PHY and for a specific PHY differential pair. 4.1.9.1 Usage To run a LinkMD test on all four pairs of one PHY, follow this flow. 1. 2. 3. 4. 5. Disable auto-negotiation: Write 0 to of register 0xN100-0xN101 bit 12. Configure register 0xN112-0xN113 to enable master-slave manual configuration mode. Start cable diagnostic by writing 1 to register 0xN124-0xN125 bit 15. This enable bit is self-clearing. Wait (poll) for register 0xN124-0xN125 bit 15 to return 0, which indicates that the cable diagnostic test is completed. Alternatively, wait 250ms. Read cable diagnostic test status in register 0xN124-0xN125 bits [9-8]. The results are: a) 00 = normal operation b) 01 = open condition detected in cable (valid result) c) 10 = short condition detected in cable (valid result) d) 11 = cable diagnostic test invalid (test failed) DS00002330E-page 22  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R The ‘11’ case occurs when the PHY is unable to shut down the link partner. In this instance, the test is not run because it would be impossible for the PHY to determine if the detected signal is a reflection of the signal generated or a signal from another source. 6. 7. 8. 9. For status 01 or 10, read the Cable Diagnostic Result in register 0xN124-0xN125 bits [7:0]. Get distance to fault by the following formula: Distance to fault (meters) = 0.8 * (Cable Diagnostic Result – 22). To test another differential pair on this PHY, change the value of register 0xN124-0xN125 bits [13:12] when initiating the test. Return the registers to their original values and restart auto-negotiation. The following script will test the four pairs of port 1. For other ports, change the register addresses accordingly. “ww” = write word (16-bits) [register] [data] “rw” = read word (16-bits) [register] Values are hexadecimal. ww 1100 0140 ww 1112 1000 # initialization # initialization ww 1124 8000 # initiate test for pair A sleep 250 msec rw 1124 # read result for pair A ww 1124 9000 # initiate test for pair B sleep 250 msec rw 1124 # read result for pair B ww 1124 a000 # initiate test for pair C sleep 250 msec rw 1124 # read result for pair C ww 1124 b000 # initiate test for pair D sleep 250 msec rw 1124 # read result for pair D ww 1112 0700 # return register to default setting ww 0 1340 # return register to default setting (may vary by application) 4.1.10 REMOTE PHY LOOPBACK This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between the KSZ9897R and its Ethernet PHY link partner, and is supported for 10/100/1000 Mbps at full-duplex. The loopback data path is shown in Figure 4-2 and functions as follows: • The Ethernet PHY link partner transmits data to the KSZ9897R PHY port. • Data received at the external pins of the PHY port is looped back without passing through the MAC and internal switch fabric. • The same KSZ9897R PHY port transmits data back to the Ethernet PHY link partner.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 23 KSZ9897R FIGURE 4-2: REMOTE PHY LOOPBACK Device PHY Port N RJ-45 10/100/1000 PHY MAC Switch Fabric CAT-5 (UTP) RJ-45 Ethernet PHY Link Partner The following programming steps and register settings are for remote PHY loopback mode for 1000BASE-T Master Mode, 1000BASE-T Slave Mode, 100BASE-TX Mode, and 10BASE-T Mode. • 1000BASE-T Master Mode - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x1F00 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x1340 • 1000BASE-T Slave Mode - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x1300 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x1340 • 100BASE-TX Mode - Set Port N (1-5), PHY Auto-Negotiation Advertisement Register = 0x0181 - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x0C00 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x3300 • 10BASE-T Mode - Set Port N (1-5), PHY Auto-Negotiation Advertisement Register = 0x0061 - Set Port N (1-5), PHY 1000BASE-T Control Register = 0x0C00 - Set Port N (1-5), PHY Remote Loopback Register = 0x01F0 - Set Port N (1-5), PHY Basic Control Register = 0x3300 DS00002330E-page 24  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.2 LEDs Each PHY port has two programmable LED output pins, LEDx_0 and LEDx_1, to indicate the PHY link and activity status. Two different LED modes are available. The LED mode can be changed individually for each PHY port by writing to the PHY Mode bit in the PHY indirect register: MMD 2, address 0, bit 4: • 1 = Single-LED Mode • 0 = Tri-Color Dual-LED Mode (Default) Each LED output pin can directly drive an LED with a series resistor (typically 220Ω to 470Ω). LED outputs are activelow. 4.2.1 SINGLE-LED MODE In single-LED mode, the LEDx_1 pin indicates the link status while the LEDx_0 pin indicates the activity status, as shown in Figure 4-2. TABLE 4-2: SINGLE-LED MODE PIN DEFINITION LED Pin Pin State Pin LED Definition H OFF Link Off L ON Link On (any speed) LEDx_1 LEDx_0 4.2.2 Link/Activity H OFF No Activity Toggle Blinking Activity (RX,TX) TRI-COLOR DUAL-LED MODE In tri-color dual-LED mode, the link and activity status are indicated by the LEDx_1 pin for 1000BASE-T; by the LEDx_0 pin for 100BASE-TX; and by both LEDx_1 and LEDx_0 pins, working in conjunction, for 10BASE-T. This behavior is summarized in Figure 4-3. TABLE 4-3: TRI-COLOR DUAL-LED MODE PIN DEFINITION LED Pin (State) LED Pin (Definition) Link/Activity LEDx_1 LEDx_0 LEDx_1 LEDx_0 H H OFF OFF Link off L H ON OFF 1000Mbps Link / No Activity Toggle H Blinking OFF 1000Mbps Link / Activity (RX,TX) H L OFF ON 100Mbps Link / No Activity H Toggle OFF Blinking L L ON ON Toggle Toggle Blinking Blinking 4.3 4.3.1 100Mbps Link / Activity (RX,TX) 10Mbps Link / No Activity 10Mbps Link / Activity (RX,TX) Media Access Controller (MAC) MAC OPERATION The device strictly abides by IEEE 802.3 standards to maximize compatibility. Additionally, there is an added MAC filtering function to filter unicast packets. The MAC filtering function is useful in applications, such as VoIP, where restricting certain packets reduces congestion and thus improves performance. The transmit MAC takes data from the egress buffer and creates full Ethernet frames by adding the preamble and the start-of-frame delimiter ahead of the data, and generates the FCS that is appended to the end of the frame. It also sends flow control packets as needed.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 25 KSZ9897R The receive MAC accepts data via the integrated PHY or via the MII/RMII/RGMII interface. It decodes the data bytes, strips off the preamble and SFD of each frame. The destination and source addresses and VLAN tag are extracted for use in filtering and address/ID lookup, and the MAC also calculates the CRC of the received frame, which is compared to the FCS field. The MAC can discard frames that are the wrong size, that have an FCS error, or when the source MAC address matches the Switch MAC address. The receive MAC also implements the Wake on LAN (WoL) feature. This system power saving feature is described in detail in the Section 4.8, "Power Management". MIB statistics are collected in both receive and transmit directions. 4.3.2 INTER-PACKET GAP (IPG) If a frame is successfully transmitted, then the minimum 96-bit time for IPG is specified as being between two consecutive packets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is specified as being from carrier sense (CRS) to the next transmit packet. 4.3.3 BACK-OFF ALGORITHM The device implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After 16 consecutive collisions, the packet is dropped. 4.3.4 LATE COLLISION If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. 4.3.5 LEGAL PACKET SIZE On all ports, the device discards received packets smaller than 64 bytes (excluding VLAN tag, including FCS) or larger than the maximum size. The default maximum size is the IEEE standard of 1518 bytes, but the device can be configured to accept jumbo packets up to 9000 bytes. Jumbo packet traffic on multiple ports can stress switch resources and cause activation of flow control. 4.3.6 FLOW CONTROL The device supports standard MAC Control PAUSE (802.3x flow control) frames in both the transmit and receive directions for full-duplex connections. In the receive direction, if a PAUSE control frame is received on any port, the device will not transmit the next normal frame on that port until the timer, specified in the PAUSE control frame, expires. If another PAUSE frame is received before the current timer expires, the timer will then update with the new value in the second PAUSE frame. During this period (while it is flow controlled), only flow control packets from the device are transmitted. In the transmit direction, the device has intelligent and efficient ways to determine when to invoke flow control and send PAUSE frames. The flow control is based on availability of the system resources, including available buffers and available transmit queues. The device issues a PAUSE frame containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the device sends out another flow control frame with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. 4.3.7 HALF-DUPLEX BACK PRESSURE A half-duplex back pressure option (non-IEEE 802.3 standard) is also provided. The activation and deactivation conditions are the same as in full-duplex mode. If back pressure is required, the device sends preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the device discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier sense type back pressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type back pressure is reactivated again until chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet reception. DS00002330E-page 26  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R To ensure no packet loss in 10BASE-Te or 100BASE-TX half-duplex modes, the user must enable the following: • No excessive collision drop (Switch MAC Control 1 Register) • Back pressure (Port MAC Control 1 Register) 4.3.8 FLOW CONTROL AND BACK PRESSURE REGISTERS Table 4-4 provides a list of flow control and back pressure related registers. TABLE 4-4: FLOW CONTROL AND BACK PRESSURE REGISTERS Registers Description LED Configuration Strap Register LED configuration strap settings. (LED1_1 enables flow control and back pressure) Switch MAC Address 0 Register through Switch MAC Address 5 Register Switch's MAC address, used as source address of PAUSE control frames Switch MAC Control 0 Register “Aggressive back-off” enable Switch MAC Control 1 Register BP mode, “Fair mode” enable, “no excessive collision drop” enable Switch MAC Control 4 Register Pass PAUSE control frames Port Status Register Flow control enable (per port) PHY Auto-Negotiation Advertisement Register PHY - flow control advertisement (per port) Port MAC Control 1 Register Half-duplex back pressure enable (per port) Port Ingress Rate Limit Control Register Ingress rate limit flow control enable (per port) Port Control 0 Register Drop mode (per port) 4.3.9 BROADCAST STORM PROTECTION The device has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The device has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 5ms interval for 1000BASE-T, a 50ms interval for 100BASE-TX and a 500ms interval for 10BASE-Te. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in control registers. The default setting equates to a rate of 1%. 4.3.10 SELF-ADDRESS FILTERING Received packets can be filtered (dropped) if their source address matches the device's MAC address. This feature is useful for automatically terminating packets once they have traversed a ring network and returned to their source. It can be enabled on a per-port basis via the Switch Lookup Engine Control 1 Register and Port Control 2 Register. 4.4 4.4.1 Switch SWITCHING ENGINE A high-performance switching engine is used to move data to and from the MAC's packet buffers. It operates in store and forward mode, while an efficient switching mechanism reduces overall latency. The switching engine has a 256KByte internal frame buffer that is shared between all the ports. For the majority of switch functions, all of the data ports are treated equally. However, a few functions such as IGMP snooping, 802.1X, forwarding invalid VLAN packets, etc., give special recognition to the host port. Any port (but most commonly port 6 or port 7) may be assigned as the host port by enabling tail tagging mode for that port. Only one port may be a host port.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 27 KSZ9897R When a switch receives a non-error packet, it checks the packet's destination MAC address. If the address is known, the packet is forwarded to the output port that is associated with the destination MAC address. The following paragraphs describe the key functions of destination address lookup and source address learning. These processes may be combined with VLAN support and other features, which are described in the subsequent sub-sections. 4.4.2 ADDRESS LOOKUP Destination address lookup is performed in three separate internal address tables in the device: 1. 2. 3. Address Lookup (ALU) Table: 4K dynamic + static entries Static Address Table: 16 static entries Reserved Multicast Address Table: 8 pre-configured static entries 4.4.2.1 Address Lookup (ALU) Table The Address Lookup (ALU) Table stores MAC addresses and their associated information. This table holds both dynamic and static entries. Dynamic entries are created automatically in hardware, as described in Section 4.4.2.4, "Learning". Static entries are created by management software. This table is a 4-way associative memory, with 1K buckets, for a total of 4K entries. A hash function translates the received packet's MAC address (and optionally the FID) into a 10-bit index for accessing the table. At each bucket are four fully-associative address entries. All four entries are simultaneously compared to the MAC address (plus optional FID) for a possible match. Three options are available for the hashing function, as described in Table 4-5. If VLAN is enabled (802.1Q VLAN Enable bit in the Switch Lookup Engine Control 0 Register), the VLAN group (FID) is included in the hashing function along with the MAC address. If VLAN is not enabled the hashing function is applied to MAC address and the FID in the default VLAN (VID=1) which is 0. TABLE 4-5: ADDRESS LOOKUP TABLE HASHING OPTIONS HASH_OPTION (Switch Lookup Engine Control 0 Register) Description 01b (Default) A hash algorithm based on the CRC of the MAC address plus FID. The hash algorithm uses the CRC-CCITT polynomial. The input to the hash is reduced to a 16-bit CRC hash value. Bits [9:0] of the hash value plus (binary addition) 7-bit FID (zero extended on the left) are used as an index to the table. The CRC-CCITT polynomial is: X16+X12+X5+1. 10b An XOR algorithm based on 16 bits of the XOR of the triple-folded MAC address. Bits [9:0] of the XOR value plus 7-bit FID (left-extended) are used to index the table. 00b or 11b A direct algorithm. The 10 least significant bits of the MAC address plus 7 bit FID are used to index the table. 4.4.2.2 Static Address Table The 16-entry Static Address Table is typically used to hold multicast addresses, but is not limited to this. As with static entries in the ALU table, entries in the Static Address Table are created by management software. It serves the same function as static entries that are created in the ALU table, so its use is optional. DS00002330E-page 28  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.4.2.3 Reserved Multicast Address Table The Reserved Multicast Address Table holds 8 pre-configured address entries, as defined in Table 4-6. This table is an optional feature that is disabled at power-on. If desired, the forwarding ports may be modified. TABLE 4-6: Group RESERVED MULTICAST ADDRESS TABLE Address MAC Group Address Function Default PORT FORWARD Value Default Forwarding Action (defines forwarding port: P7...P1) 0 (01-80-C2-00)-00-00 Bridge Group Data 100_0000 1 (01-80-C2-00)-00-01 MAC Control Frame 000_0000 (typically flow control) Drop MAC flow control 2 (01-80-C2-00)-00-03 802.1X Access Control Forward to highest numbered port 3 (01-80-C2-00)-00-10 Bridge Management 111_1111 Flood to all ports 4 (01-80-C2-00)-00-20 GMRP 011_1111 Flood to all ports except highest numbered port 5 (01-80-C2-00)-00-21 GVRP 011_1111 Flood to all ports except highest numbered port 6 (01-80-C2-00)-00-02, (01-80-C2-00)-00-04 – (01-80-C2-00)-00-0F 100_0000 Forward to highest numbered port 7 (01-80-C2-00)-00-11 (01-80-C2-00)-00-1F, (01-80-C2-00)-00-22 (01-80-C2-00)-00-2F 011_1111 Flood to all ports except highest numbered port 100_0000 Forward only to the highest numbered port (default host port) If a match is found in one of the tables, then the destination port is read from that table entry. If a match is found in more than one table, static entries will take priority over dynamic entries. 4.4.2.4 Learning The internal lookup engine updates the ALU table with a new dynamic entry if the following conditions are met: • The received packet's source address (SA) does not exist in the lookup table. • The received packet has no errors, and the packet size is of legal length. • The received packet has a unicast SA. The lookup engine inserts the qualified SA into the table, along with the port number and age count. If all four table entries are valid, the oldest of the (up to four) dynamic entries may be deleted to make room for the new entry. Static entries are never deleted by the learning process. If all four entries are static entries, the address is not learned but an interrupt is generated and the table index number is made available to the interrupt service routine. 4.4.2.5 Migration The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the ALU table accordingly. Migration happens when the following conditions are met: • The received packet's SA is in the table but the associated source port information is different. • The received packet has no receiving errors, and the packet size is of legal length. The lookup engine updates the existing record in the table with the new source port information.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 29 KSZ9897R 4.4.2.6 Aging The lookup engine updates the age count information of a dynamic record in the ALU table whenever the corresponding SA appears. The age count is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record from the table. The lookup engine constantly performs the aging process and continuously removes aging records. The aging period is about 300 seconds (±75 seconds) and can be configured longer or shorter (1 second to 30 minutes). This feature can be enabled or disabled. Static entries are exempt from the aging process. 4.4.2.7 Forwarding The device forwards packets using the algorithm that is depicted in Figure 4-3. Figure 4-3 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1" (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes. The ACL process works in parallel with the flow outlined above. The authentication and ACL processes have the highest priority in the forwarding process, and the ACL result may override the result of the above flow. The output of the ACL process is the final “port-to-forward 2" (PTF2) destination port(s). The device will not forward the following packets: • Error packets: These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal size packet errors. • MAC Control PAUSE frames: The device intercepts these packets and performs full duplex flow control accordingly. • “Local” packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as “local”. • In-Band Management packets. FIGURE 4-3: PACKET FORWARDING PROCESS FLOWCHART Start PTF1 no PTF1=NULL VLAN ID Valid? - Search VLAN table - Ingress VLAN filtering -Discard NPVID check Spanning Tree Process - Check receiving port s receive enable bit - Check destination port s transmit enable bit - Check whether packets are special (BPDU) yes Get PTF1 from Static Array found Search Static Array Search based on DA or DA+FID IGMP / MLD Process - IGMP / MLD packets are forwarded to Host port - Process does not apply to packets received at Host port Port Mirror Process - not found Get PTF1 from Address Table found Search Address Look-up Table Search based on DA+FID RX Mirror TX Mirror RX or TX Mirror RX and TX Mirror not found DS00002330E-page 30 Get PTF1 from VLAN Table Port Authentication & ACL PTF1 PTF2  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.4.2.8 Lookup Engine Registers Table 4-7 provides a list of lookup engine related registers. TABLE 4-7: LOOKUP ENGINE REGISTERS Registers Description Global Interrupt Status Register, Global Interrupt Mask Register Top level LUE interrupt Switch Lookup Engine Control 0 Register, Switch Lookup Engine Control 1 Register, Switch Lookup Engine Control 2 Register, Switch Lookup Engine Control 3 Register Misc. Address Lookup Table Interrupt Register, Address Lookup Table Mask Register Low level LUE interrupts Address Lookup Table Entry Index 0 Register, Address Lookup Table Entry Index 1 Register Access failure address/index ALU Table Index 0 Register, ALU Table Index 1 Register, ALU Table Access Control Register, Static Address and Reserved Multicast Table Control Register, ALU / Static Address Table Entry 1 Register, ALU / Static Address / Reserved Multicast Table Entry 2 Register, ALU / Static Address Table Entry 3 Register, ALU / Static Address Table Entry 4 Register Address table access registers 4.4.3 IEEE 802.1Q VLAN Virtual LAN is a means of segregating a physical network into multiple virtual networks whereby traffic may be confined to specific subsets of the greater network. IEEE 802.1Q defines a VLAN protocol using a 4-byte tag that is added to the Ethernet frame header. The device supports port-based and tag-based VLANs, including tagging, un-tagging, forwarding and filtering. 4.4.3.1 Non-Tag Port-Based VLAN The simplest VLAN method establishes forwarding restrictions on a port-by-port basis without using VLAN tags. There is a register for each ingress port that is used to specify the allowed forwarding ports. An incoming packet is restricted from being forwarded to any egress port that is disallowed for that ingress port. The settings are made in the Port Control 1 Register. This function is always enabled; it is not enabled and disabled by the 802.1Q VLAN Enable bit in the Switch Lookup Engine Control 0 Register. The default setting is to allow all ingress-to-egress port paths. 4.4.3.2 Tag-Based VLAN When 802.1Q VLAN is enabled, an internal VLAN Table with 4k entries is used to a store port membership list, VLAN group ID (FID) and additional information relating to each VLAN. This table must be set up by an administrator prior to enabling 802.1Q VLAN. Enabling is done by setting the 802.1Q VLAN Enable bit in the Switch Lookup Engine Control 0 Register. In 802.1Q VLAN mode, the lookup process starts with VLAN Table lookup, using the tag's VID as the address. The first step is to determine whether the VID is valid. If the VID is not valid, the packet is dropped and its address is not learned. Alternatively, unknown VID packets may be forwarded to pre-defined ports or to the host port. If the VID is valid, the FID is retrieved for further lookup. The FID + Destination Address (hashed(DA) + FID) are used to determine the destination port. The FID + Source Address (hashed(SA) + FID) are used for address learning (see Table 4-9 and Table 4-10).  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 31 KSZ9897R The hashed(DA) + FID are hashed and used for forwarding lookup in the Address Lookup and Static Address Tables. For a successful address table lookup, the FID fields must also match. If the match fails, the packet is broadcast to all the VLAN port members defined in the VLAN Table entry. If there is a match and egress VLAN filtering is enabled, the packet is forwarded to those ports that are in both the address table port forwarding list and the VLAN table port membership list. A similar address table lookup is performed using the hashed(SA) + FID. If the lookup fails, the FID and SA are learned. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID (Port Default Tag 0 Register and Port Default Tag 1 Register) is used for lookup. Table 4-8 details the forwarding and discarding actions that are taken for the various VLAN scenarios. The first entry in the table is explained by the fact that VLAN Table lookup is enabled even when 802.1Q VLAN is not enabled. Notice that in the Port Default Tag 0 Register and Port Default Tag 1 Register, the port default VID is 1 for each port. Correspondingly, the VLAN port membership list in the VLAN Table entry for VID=1 is pre-configured at power-on to all ones. This provides the standard Ethernet switch behavior of broadcasting all packets with unknown destination address. If the VLAN table entry # 1 is changed, or if the port default VID is changed, this may affect the forwarding action for “unknown packets” even when VLAN is not enabled. It should also be noted that the default values of the Egress VLAN Filtering bits are zero. These bits are zero only for backwards compatibility with previous “KSZ” switches. The resulting switch behavior, in the event of a successful VLAN and ALU lookups, is to forward the packet to the ports in the address table port forwarding list, without regard to the VLAN port membership list. It is suggested that the Egress VLAN Filtering bits be set to one so that the VLAN port membership list from the VLAN Table will be used to qualify the forwarding determined from the address lookup. TABLE 4-8: VLAN Enable (Note 4-1) VLAN FORWARDING VLAN Match/ Valid (Note 4-2) Forward Option (Note 4-3) Egress VLAN Filtering Unknown VID Forward Drop Invalid VID ALU Match/ Valid (Note 4-4) (Note 4-5) (Note 4-6) (Note 4-7) Action 0 X X X X X No Forward to port membership list of default VID in LAN table 0 X X X X X Yes Forward to Address Lookup port forwarding list 1 No X X 0 0 X Forward to host port 1 No X X 0 (def) 1 (def) X Discard 1 No X X 1 X X Forward to Unknown VID packet forward port list 1 Yes 0 X X X No Broadcast: Forward to VLAN table port membership list (PORT FORWARD) Multicast: Forward to Unknown Multicast ports if UM is enabled. Else, forward to VLAN table port membership list. Unicast: Forward to Unknown Unicast ports if UU is enabled. Else forward to VLAN table port membership list. 1 Yes 0 0 (def) X X Yes Forward to address table lookup port forwarding list 1 Yes 0 1 X X Yes Forward to address table lookup port forwarding list & VLAN table port membership list (bitwise AND) 1 Yes 1 X X X Yes Forward to VLAN table port membership list DS00002330E-page 32  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R Note: “(def)” indicates the default power-up value. Note 4-1 VLAN Enable is bit 7 in the Switch Lookup Engine Control 0 Register Note 4-2 VLAN Match/Valid indicates when the VLAN Table entry is valid Note 4-3 Forward Option is a bit in the VLAN Table Entry 0 Register Note 4-4 Egress VLAN Filtering are bits 5 and 4 in the Switch Lookup Engine Control 2 Register Note 4-5 Unknown VID Forwarding is in the Unknown VLAN ID Control Register Note 4-6 Drop Invalid VID is bit 6 in the Switch Lookup Engine Control 0 Register Note 4-7 ALU Match/Valid indicates when the Address Lookup is a success Table 4-9 describes in more detail the address lookup process that follows the VLAN Table lookup. Lookup occurs in both the Address Lookup Table and the Static Address Table simultaneously, and the resulting action depends on the results of the two lookups. TABLE 4-9: HASHED(DA) + FID LOOKUP IN VLAN MODE DA found in Use FID Flag? Static MAC (Static MAC Table) Table? FID Match? DA+FID found in ALU Table? Action No Don’t Care Don’t Care No Lookup has failed. Broadcast to the membership ports defined in the VLAN Table No Don’t Care Don’t Care Yes Send to the destination port defined in the Address Lookup (ALU) Table Yes 0 Don’t Care Don’t Care Yes 1 No No Lookup has failed. Broadcast to the membership ports defined in the VLAN Table. Yes 1 No Yes Send to the destination port defined in the Address Lookup (ALU) Table Yes 1 Yes Don’t Care Send to the destination port(s) defined in the Static Address Table Send to the destination port(s) defined in the Static Address Table A source address (SA) lookup is also performed in the Address Lookup Table. SA lookup also performs SA filtering and MAC priority when the address is hit. Table 4-10 describes how learning is performed in the Address Lookup Table when a successful VLAN table lookup has been done and the no matching static entry is found in the Address Lookup Table or the Static Address Table. TABLE 4-10: HASHED(SA) + FID LOOKUP IN VLAN MODE FID + SA found in Address Lookup (ALU) Table? Action No Learn and add FID + SA to the Address Lookup (ALU) Table Yes If the static bit is 0, the time stamp and the egress port map are updated. If the static bit is 1, then nothing is done.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 33 KSZ9897R 4.4.3.2.1 Tag Insertion and Removal Tag insertion is enabled on all ports when the VLAN feature is enabled. At the ingress port, untagged packets are tagged with the ingress port's default tag. The default tag is separately programmable for each port. The switch does not add tags to already tagged packets unless double tagging is enabled. At the egress port, tagged packets will have their 802.1Q VLAN tags removed if un-tagging is enabled in the VLAN table entry. Untagged packets will not be modified if 802.1Q is enabled. 4.4.3.2.2 Double Tagging The switch supports double tagging, also known as Q-in-Q or VLAN stacking. This feature can be used for service providers to append a second VLAN tag in addition to a first VLAN tag applied by the customer. VLAN support can be enabled either with or without double tagging. When double tagging is enabled, the outer tag is recognized and is used for VLAN and address lookup instead of the inner tag. The outer tag precedes the inner tag in the frame header: the outer tag is located immediately after the source address, and contains a different Tag Protocol Identifier (TPID) value than the inner tag. Additional controls are available for full control of the VLAN function. Some of these features can be enabled on a perport basis, while others are global: • • • • • • • • • Ingress VLAN Filtering: Discard packet if VID port membership in VLAN table does not include the ingress port. Discard non PVID Packet: Discard packet if VID does not match the ingress port default VID. Discard un-tagged Packet: Discard any received packet without a tag. Drop tag: Drops the packet if it is VLAN tagged. Unknown VID Forward: Forward to a fixed set of ports if VLAN lookup fails. Drop unknown VID: Additional options for unknown VID packets: discard or forward to the host port. Null VID Replacement: Replace a null VID with the ingress port default VID. PVID Replacement: Replace a non-null VID with the ingress port default VID. Double Tag Mcast Trap: In double tag mode, trap all reserved multicast packets and forward to the host port. 4.4.3.3 VLAN Registers Table 4-11 provides a list of VLAN related registers. TABLE 4-11: VLAN REGISTERS Registers Description Switch Operation Register Double tag enable Switch Lookup Engine Control 0 Register VLAN enable; Drop invalid VID frames Switch Lookup Engine Control 2 Register Trap double tagged MC frames; Dynamic & status egress VLAN filtering Unknown VLAN ID Control Register Forward unknown VID Switch MAC Control 2 Register Null VID replacement with PVID at egress VLAN Table Entry 0 Register, VLAN Table Entry 1 Register, VLAN Table Entry 2 Register, VLAN Table Index Register, VLAN Table Access Control Register Read/write access to the VLAN table Port Default Tag 0 Register, Port Default Tag 1 Register Port default tag Port Ingress MAC Control Register Drop non-VLAN frames; Tag drop Port Transmit Queue PVID Register PVID replacement at egress Port Control 2 Register VLAN table lookup for VID=0; Ingress VLAN filtering; PVID mismatch discard DS00002330E-page 34  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.4.4 QUALITY-OF-SERVICE (QOS) PRIORITY SUPPORT The device provides quality-of-service (QoS) for applications such as VoIP. There are multiple methods for assigning priority to ingress packets. Depending on the packet prioritization method, the packet priority levels are mapped to the egress queues for each port. Each port can be configured for 1, 2, and 4 egress queues, which are prioritized. The default is 1 queue per port. When configured for 4 priority queues, Queue 3 is the highest priority queue and Queue 0 is the lowest priority. Likewise, for a 2-queue configuration, Queue 1 is the highest priority queue. If a port is not configured as 2 or 4 queues, then high priority and low priority packets have equal priority in the single transmit queue. There is an additional option for every port to select either to always deliver packets from the highest priority queue first, or use weighted round robin queuing amongst the multiple queues. This is described later in Section 4.4.13, "Scheduling and Rate Limiting". 4.4.4.1 Port-Based Priority With port-based priority, each ingress port is individually classified as a specific priority level. All packets received at the high-priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split into 2 or 4 queues. 4.4.4.2 IEEE 802.1p-Based Priority For IEEE 802.1p-based priority, the device examines the ingress packets to determine whether they are tagged. If tagged, the 3-bit PCP priority field in the VLAN tag is retrieved and used to look up the “priority mapping” value. The “priority mapping” value is programmable. Figure 4-4 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. FIGURE 4-4: 4.4.4.3 802.P PRIORITY FIELD FORMAT IEEE 802.1p Priority Field Re-Mapping This is a QoS feature that allows the device to set the “User Priority Ceiling” at any ingress port. If the ingress packet's priority field has a higher priority value than the default tag's priority field of the ingress port, the packet's priority field is replaced with the default tag's priority field. 4.4.4.4 DiffServ (DSCP) Priority (IP) DiffServ-based priority from the DSCP field in the IP header can be used to determine packet priority. The 6-bit DSCP value is used as an index to a set of registers which translate the 6-bit DSCP value to a 2-bit value that specifies one of the 4 (or 2) queues. These registers are fully programmable. 4.4.4.5 ACL Priority The Access Control List (ACL) Filtering feature can also be used to assign priority to received packets. This is discussed in Section 4.4.16, "Access Control List (ACL) Filtering".  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 35 KSZ9897R 4.4.5 4.4.5.1 TRAFFIC CONDITIONING & POLICING Two Rate Three Color Marker The Two Rate Three Color Marker meters an IP packet stream and marks its packets green, yellow, or red. A packet is marked red if it exceeds the Peak Information Rate (PIR). Otherwise, it is marked either yellow or green depending on whether it exceeds or doesn't exceed the Committed Information Rate (CIR). The Meter operates in one of two modes. In the Color-Blind mode, the Meter assumes that the packet stream is uncolored. In the Color-Aware mode, the Meter assumes that some preceding entity has pre-colored the incoming packet stream so that each packet is green, yellow, or red. The Marker (re)colors an IP packet according to the results of the Meter. 4.4.5.2 Weighted Random Early Detection (WRED) The WRED feature monitors the average queue size of packet memory and ingress queue size of each traffic class, and drops packets based on memory and queue utilization. If the buffers are almost empty, all incoming traffic is accepted. As the buffer utilization increases, the probability for dropping an incoming packet also increases. WRED is intended to avoid the problem of global synchronization. Global synchronization can occur when a switch becomes congested and begins dropping incoming packets all at once. For TCP streams, packet drops invoke the TCP congestion control mechanism, which reduce the transmission rate until there are no more packet drops. If there are many TCP streams and their congestion control mechanisms act in unison, this can cause an undesirable oscillation in traffic rates. By selectively dropping some packets early rather than waiting until the buffer is full, WRED avoids dropping large numbers of packets at once and minimizes the chances of global synchronization. The packet drop probability is based on the minimum threshold, maximum threshold, and a probability multiplier. When the average queue depth is above the minimum threshold, packets start getting dropped. The rate of packet drop increases linearly as the average queue size increases until the average queue size reaches the maximum threshold. The probability multiplier is the fraction of packets dropped when the average queue depth is at the maximum threshold. When the average queue size is above the maximum threshold, all packets are dropped. 4.4.6 SPANNING TREE SUPPORT To support spanning tree, one port is the designated port for the host processor, which is defined as the port for which tail tagging is enabled. Each of the other ports can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register bits. Table 4-12 shows the setting and software actions taken for each of the five spanning tree states. TABLE 4-12: SPANNING TREE STATES Disable State Port Setting Software Action The port should not forward or receive any packets. Learning is disabled. transmit enable = 0 receive enable = 0 learning disable = 1 The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the “Static MAC Table” with “overriding bit” set) and the processor should discard those packets. Address learning is disabled on the port in this state. Blocking State Port Setting Software Action Only packets to the processor are forwarded. Learning is disabled. transmit enable = 0 receive enable = 0 learning disable = 1 The processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. DS00002330E-page 36  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 4-12: SPANNING TREE STATES (CONTINUED) Listening State Port Setting Software Action Only packets to and from the transmit enable = 0 processor are forwarded. receive enable = 0 Learning is disabled. learning disable = 1 The processor should program the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. Address learning is disabled on the port in this state. Learning State Software Action Port Setting Only packets to and from the transmit enable = 0 processor are forwarded. receive enable = 0 Learning is enabled. learning disable = 0 The processor should program the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state. Address learning is enabled on the port in this state. Forwarding State Port Setting Software Action Packets are forwarded and received normally. Learning is enabled. transmit enable = 1 receive enable = 1 learning disable = 0 The processor programs the “Static MAC Table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. Address learning is enabled on the port in this state. 4.4.7 RAPID SPANNING TREE SUPPORT There are three operational states assigned to each port for the Rapid Spanning Tree Protocol (RSTP): 1. 2. 3. Discarding State Learning State Forwarding State 4.4.7.1 Discarding State Discarding ports do not participate in the active topology and do not learn MAC addresses. • Discarding state: the state includes three states of the disable, blocking and listening of STP. • Port setting: transmit enable = “0”, receive enable = “0”, learning disable = “1”. • Software action: The host processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those packets. When the port's learning capability (learning disable = '1') is disabled, port related entries in the ALU table and static MAC table can be rapidly flushed. 4.4.7.2 Learning State Ports in “learning state” learn MAC addresses, but do not forward user traffic. • Learning State: Only packets to and from the host processor are forwarded. Learning is enabled. • Port setting for Learning State: transmit enable = “0”, receive enable = “0”, learning disable = “0”. • Software action: The processor should program the Static Address Table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state (see Section 4.4.9, "Tail Tagging Mode" for details). Address learning is enabled on the port in this state. 4.4.7.3 Forwarding State Ports in “forwarding states” fully participate in both data forwarding and MAC learning. • Forwarding state: Packets are forwarded and received normally. Learning is enabled.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 37 KSZ9897R • Port setting: transmit enable = “1”, receive enable = “1”, learning disable = “0”. • Software action: The host processor should program the Static Address Table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state (see Section 4.4.9, "Tail Tagging Mode" for details). Address learning is enabled on the port in this state. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP configuration BPDUs with the exception of a type field set to “version 2" for RSTP and “version 0" for STP, and a flag field carrying additional information. 4.4.8 MULTIPLE SPANNING TREE SUPPORT Multiple Spanning Tree Protocol (MSTP) is an extension of RSTP that allows different VLANs to have different spanning tree configurations. The VLAN Table, Address Lookup Table and Static Address Table all contain a 3-bit field which can be used to specify one of eight spanning trees. Each port contains state registers for specifying unique states for each of the spanning trees. 4.4.9 TAIL TAGGING MODE Tail tagging is a method to communicate ingress and egress port information between the host processor and the switch. It is useful for spanning tree protocol, IGMP/MLD snooping, and other applications. As shown in Figure 4-5, the tail tag is inserted at the end of the packet, between the payload and the 4-byte CRC / FCS. FIGURE 4-5: BYTES TAIL TAG FRAME FORMAT 6 6 (4) 2 46 (42) - 1500 DEST ADDRESS SOURCE ADDRESS 802.1Q TAG ETYPE or LENGTH PAYLOAD 2 (From Host) 1 (To Host) TAIL TAG 4 FCS When the switch forwards a received packet to the host port, one tail tagging byte is added to the packet by the switch to indicate to the host processor the port that the packet was received on. The format is shown in Table 4-13. TABLE 4-13: RECEIVE TAIL TAG FORMAT (FROM SWITCH TO HOST) Bits Description 7 PTP Message Indication 0 = Is not a PTP message. A 4-byte receive timestamp has not been added. 1 = Is a PTP message. A 4-byte timestamp has been added before the tail tag. 6:3 Reserved 2:0 Received Port 000 = Packet received at Port 1 001 = Packet received at Port 2 010 = Packet received at Port 3 011 = Packet received at Port 4 100 = Packet received at Port 5 101 = Packet received at Port 6 110 = Packet received at Port 7 In the opposite direction, the host processor must add two tail tag bytes to each packet that it sends to the switch to indicate the intended egress ports. When multiple priority queues are enabled, the tail tag is also used to indicate the priority queue. The format is shown in Table 4-14. This tail tag is removed by the switch before the packet leaves the switch. If the Lookup bit (bit 10) is set, packet forwarding follows the standard forwarding process, and bits [9:0] are ignored. When the Lookup bit is not set, bits [8:0] determine the forwarding ports and priority queue, while the Override bit (bit 9) determines whether port blocking is overridden. Tail tagging applies only to the host port, never to any other ports of the switch. DS00002330E-page 38  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 4-14: TRANSMIT TAIL TAG FORMAT (FROM HOST TO SWITCH) Bits Description 15:11 Reserved 10 Lookup 0 = Port forwarding is determined by tail tag bits [9:0] below. 1 = Tail tag bits [9:0] are ignored and port forwarding is determined by the standard switch forwarding process (address lookup, VLAN, etc.) 9 Port Blocking Override When set, packets will be sent from the specified port(s) regardless, and any port blocking (see Port Transmit Enable in Port MSTP State Register) is ignored. 8:7 Egress priority (0 to 3) 6 Forward to Port 7 5 Forward to Port 6 4 Forward to Port 5 3 Forward to Port 4 2 Forward to Port 3 1 Forward to Port 2 0 Forward to Port 1 By default, tail tagging is disabled. To enable it, set the Tail Tag Enable bit in one of the Port Operation Control 0 Register at address 0xN020 for port “N”. When this bit is set for one port, that port is referred to as the “host” port. Do not set the Tail Tag Enable bit for more than one port. 4.4.10 IGMP SUPPORT For Internet Group Management Protocol (IGMP) support in Layer 2, the device provides two components: • “IGMP” Snooping • “Multicast Address Insertion” in the Static MAC Table 4.4.10.1 “IGMP” Snooping The device traps IGMP packets and forwards them only to the processor (host port). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. Note: 4.4.10.2 The port for which Tail Tagging Mode is enabled is the host port. “Multicast Address Insertion” in the Static MAC Table Once the multicast address is programmed in the Static Address Table or Address Lookup Table, the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. So that the host processor knows which port the IGMP packet was received on, Tail Tagging Mode must be enabled. 4.4.11 IPV6 MLD SNOOPING The device traps IPv6 Multicast Listener Discovery (MLD) packets and forwards them only to the processor (host port). 4.4.12 PORT MIRRORING the device supports “port mirroring” comprehensively as: • “Receive Only” Mirror-on-a-Port • “Transmit Only” Mirror-on-a-Port • “Receive and Transmit” Mirror-on-a-Port  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 39 KSZ9897R 4.4.12.1 “Receive Only” Mirror-on-a-Port All the packets received on the port are mirrored on the sniffer port. For example, 1 is programmed to be “receive sniff” and the host port is programmed to be the “sniffer”. A packet received on port 1 is destined to port 2 after the internal lookup. The packet is forwarded to both port 2 and the host port. The device can optionally even forward “bad” received packets to the “sniffer port”. 4.4.12.2 “Transmit Only” Mirror-on-a-Port All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “transmit sniff” and the host port is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the internal lookup. The device forwards the packet to both port 1 and the host port. 4.4.12.3 “Receive and Transmit” Mirror-on-a-Port All the packets received on port A and transmitted on port B are mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff”, and the host port is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The device forwards the packet to both port 2 and the host port. Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer port”. 4.4.13 SCHEDULING AND RATE LIMITING Each device port has two egress packet scheduling options, which can be applied when the port is configured for two or four queues. Additionally, each port has ingress and egress rate limiter features. 4.4.13.1 Strict Priority Scheduling When an egress port is configured as two or four queues, and strict priority scheduling is selected, each queue will take absolute priority over all lower priority queues. If a packet is available to transmit from queue 3 (the highest priority queue), then it will take priority for transmission over any packet that will also be available in any of the other queues. A packet in queue 2 will be transmitted only if no packet is available in queue 3. Weighted round robin is an alternative to strict priority scheduling. 4.4.13.2 Weighted Round Robin (WRR) Scheduling WRR scheduling is an alternative to strict priority scheduling for egress queues. It is referred to as fair queuing because it gives proportionally higher priority to the highest priority queue, but not absolute priority. 4.4.13.3 Rate Limiting The device supports independent ingress and egress hardware rate limiting on each port. Normally these two features are considered mutually exclusive, and users are discouraged from using both on the same port. For 10BASE-Te, a rate setting above 10Mbps means the rate is not limited. Likewise, for 100BASE-TX, a rate setting above 100Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. The size of each frame has options to include minimum inter-frame gap (IFG) or preamble byte, in addition to the data field (from packet DA to FCS). For ingress rate limiting, the device provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The data rate from those selected type of frames is counted. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit. For egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic. Inter-frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified. If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. To reduce congestion, it is a good practice to ensure that the egress bandwidth exceeds the ingress bandwidth. DS00002330E-page 40  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.4.14 INGRESS MAC ADDRESS FILTERING FUNCTION When a packet is received, the destination MAC address is looked up in both the static and dynamic MAC address tables. If the address is not found in either of these tables, then the destination MAC address is “unknown”. By default, an unknown packet is forwarded to all ports except the port at which it was received. An optional feature makes it possible to specify the port or ports to which to forward unknown packets. It is also possible to specify no ports, meaning that unknown packets will be discarded. This feature is implemented separately for unknown unicast, unknown multicast and unknown VID packets. 4.4.15 802.1X ACCESS CONTROL IEEE 802.1X is a Port-based authentication protocol. EAPOL is the protocol normally used by the authentication process as uncontrolled Port. By receiving and extracting special EAPOL frames, the host processor can control whether the ingress and egress ports should forward packets or not. If a user port wants service from another port (authenticator), it must get approved by the authenticator. The device detects EAPOL frames by checking the destination address of the frame. The destination addresses should be either a multicast address as defined in IEEE 802.1x (01-80-C2-0000-03) or an address used in the programmable reserved multicast address domain with offset -00-03. Once EAPOL frames are detected, the frames are forwarded to the host port so it can send the frames to the authenticator server. Eventually, the CPU determines whether the requester is qualified or not based on its source MAC address, and frames are either accepted or dropped. When the device is configured as an authenticator, the ports of the switch must then be configured for authorization. In an authenticator-initiated port authorization, a client is powered up or plugs into the port, and the authenticator port sends an Extensible Authentication Protocol (EAP) PDU to the supplicant requesting the identification of the supplicant. At this point in the process, the port on the switch is connected from a physical standpoint; however, the 802.1X process has not authorized the port and no frames are passed from the port on the supplicant into the switching fabric. If the supplicant attached to the switch (KSZ9897R) did not understand the EAP PDU that it was receiving from the switch, it would not be able to send an ID and the port would remain unauthorized. In this state, the port would be blocked from passing any user traffic. If the supplicant is running the 802.1X EAP, it would respond to the request with its configured ID. (This could be a user name/password combination or a certificate.) After the device receives the ID from the supplicant, it passes the ID information to an authentication server (RADIUS server) that can verify the identification information. The RADIUS server responds to the switch with either a success or failure message. If the response is a success, the port will be authorized and user traffic will be allowed to pass through the port like any switch port connected to an access device. If the response is a failure, the port will remain unauthorized and, therefore, unused. If there is no response from the server, the port will also remain unauthorized and will not pass any traffic. Port control can be performed via the Access Control List (ACL) Filtering feature. 4.4.16 ACCESS CONTROL LIST (ACL) FILTERING An Access Control List (ACL) can be created for each port to perform filtering on incoming layer 2 MAC, layer 3 IP or layer 4 TCP/UDP packets. Multicast filtering is handled in the Static Address Table and the Reserved Multicast Address Table, but the ACL provides additional capabilities for filtering routed network protocols. As shown in Figure 4-3, ACL filtering may take precedence over other forwarding functions. The ACL allows the switch to filter ingress traffic based on the following header fields: • • • • • • Source or destination MAC address and/or EtherType Source or destination IPv4 address with programmable mask IPv4 protocol Source or destination UDP port Source or destination TCP port TCP Flag with programmable mask The ACL is implemented as an ordered list of up to 16 access control rules which are programmed into the ACL Table. Each entry specifies certain rules (a set of matching conditions and action rules) to control the forwarding and priority of packets. When a packet is received on an interface, the switch compares the fields in the packet against any applied ACLs to verify that the packet has the permissions required to be forwarded, based on the conditions specified in the lists. Multiple match conditions can be either AND'ed or OR'ed together.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 41 KSZ9897R The ACL can also implement a count function that generates an interrupt rather than a forwarding action. The counter can be either a watchdog timer or an event counter. As a watchdog timer, an interrupt is generated if a packet with a specific MAC address and EtherType is not received within a specified time interval. As an event counter, an interrupt is generated once a specified number of packets with a specific MAC address and EtherType have been received. The ACL consists of three parts: matching rules, action rules, and processing entries. A matching rule specifies what comparison test shall be performed on the incoming packet. It can also enable a counter function. An action rule specifies the forwarding action to be taken if the matching test succeeds. Alternatively, when a count function is enabled in a matching rule, the 11-bit count value is stored in the corresponding action rule field and there is no forwarding action. In general, the 16 matching rules are not directly linked to the 16 action rules. For example, matching entry #0 is not necessarily related to action entry #0. The exception is when the counter function is enabled in a matching rule, whereby the matching rule and action rule fields at the same ACL table entry will function together and are no longer independent. Each of the 16 processing entries is used to link any number of matching rules (specified in RuleSet) to any one action rule (specified in FRN). When there are multiple matching rules in a RuleSet, those rules are AND'ed together. Only if all of those matching results are true will the FRN action be taken. It is also possible to configure the ACL table so that multiple processing entries specify the same action rule. In this way, the final matching result is the OR of the matching results from each of the multiple RuleSets. The 16 ACL rules represent an ordered list, with entry #0 having the highest priority and entry #15 having the lowest priority. All matching rules are evaluated. If there are multiple true match results and multiple corresponding actions, the highest priority (lowest numbered) of those actions will be the one taken. 4.4.16.1 Processing Entry Description The Processing Entry consists of two parameters as described in Table 4-15. TABLE 4-15: ACL PROCESSING ENTRY PARAMETERS Parameter Description FRN[3:0] First Rule Number Pointer to an Action rule entry. Possible values are 0 to 15. If all Matching rules specified in the RuleSet are evaluated true, then this is the resulting Action rule. RuleSet[15:0] Specifies a set of one or more Matching rule entries. RuleSet has one bit for each of the 16 Matching rule entries. If multiple Matching rules are selected, then all conditions will be AND'ed to produce a final match result. 0 = Matching rule not selected 1 = Matching rule selected DS00002330E-page 42  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R FIGURE 4-6: ACL STRUCTURE AND EXAMPLE RULE VALUES Processing Field Entry Number Action Rule RuleSet Matching Rule Entry #0 0 #0 0 Entry #0 Entry #1 0 #1 1 Entry #1 Entry #2 1 #2 2 Entry #2 Action Field #3 none Entry #3 Entry #3 #4 4, 5, 6 Entry #4 #5 none Entry #4 OR FRN 4 Entry #5 Entry #6 5 Entry #7 Entry #8 9 AND When counter function is enabled in Matching Rule. Entry #5 #6 6 Entry #6 #7 none Entry #7 #8 7, 11 Entry #8 Entry #9 #9 none Entry #9 Entry #10 #10 none Entry #10 Entry #11 #11 none Entry #11 Entry #12 #12 none Entry #12 Entry #13 #13 none Entry #13 Entry #14 #14 none Entry #14 Entry #15 #15 none Entry #15 The examples in Figure 4-6 are interpreted as follows: • • • • Rule #0: Test the matching rule entry #0. If true, apply action rule entry #0. Rule #1: Test the matching rule entry #1. If true, apply action rule entry #0. Rule #2: Test the matching rule entry #2. If true, apply action rule entry #1. Matching rule entry #3 is configured for the counter function. Action entry #3 is used to hold the corresponding count value. • Rule #4: Test the matching rule entries #4, 5 and 6. If all are true, apply action rule entry #4. • Rule #6: Test the matching rule entry #6. If true, apply action rule entry #5. • Rule #8: Test the matching rule entries #7 and 11. If both are true, apply action rule entry #9. No more than one action can be taken for any packet. If the matching conditions are true for multiple RuleSets, then the corresponding FRN field with the lowest value (highest priority) determines the action to be taken. Note that processing entries #0 and 1 produce an OR function: action #0 is taken if RuleSet #0 or RuleSet #1 is true. Notice that processing entries #4 and 6 have overlapping RuleSets, but different FRNs. This can be summarized as: If match #4, 5 and 6 are all true, then apply action #4, Else if match #6 is true, then apply action #5. Table 4-16 summarizes the available matching options. The MD and ENB fields are used to select the desired matching option. More configuration details are given in the following section.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 43 KSZ9897R TABLE 4-16: MATCHING RULE OPTIONS MD[1:0] ENB[1:0] 00 XX Matching rule disabled 01 (Layer 2 matching: MAC address, EtherType) 00 Action field is used as count value for packets matching MAC address and EtherType 01 Compare EtherType only 10 (Layer 3 matching: IP address) 11 (Layer 4 matching: TCP, UDP, IP protocol) 4.4.16.2 Matching Rule 10 Compare MAC address only 11 Compare both MAC address and EtherType 00 Reserved 01 Compare IPv4 source and destination address (with mask) 10 Compare both source and destination IPv4 addresses (without mask) 11 Reserved 00 Compare IPv4 protocol 01 Compare TCP source port or destination port 10 Compare UDP source port or destination port 11 Compare TCP sequence number Matching Rule Description The Matching Rule consists of several parameters. The first two parameters, MD[1:0] and ENB[1:0], determine the organization of the remainder of each Matching Rule. When MD = 00, the Matching Rule is disabled. TABLE 4-17: ACL MATCHING RULE PARAMETERS FOR MD = 01 Parameter Description MD[1:0] MODE 00 = Matching rule is disabled 01 = Layer 2 MAC header or counter filtering 10 = Layer 3 IP header filtering 11 = Layer 4 TCP header (and IP protocol) filtering ENB[1:0] 00 = Count Mode. Both the MAC Address and TYPE are tested. A count value (either time or packet count) is also incorporated. Details are given below this table. 01 = Comparison is performed only on the TYPE value 10 = Comparison is performed only on the MAC Address value 11 = Both the MAC Address and TYPE are tested S/D Source / Destination 0 = Destination address 1 = Source address EQ Equal / Not Equal 0 = Not Equal produces true result 1 = Equal produces true result MAC ADDRESS[47:0] 48-bit MAC address TYPE[15:0] EtherType Details for MD = 01, ENB = 00: The 11 bits of the aggregated bit fields from PM, P, RPE, RP and MM in the Action rule entry specify a count value for packets matching MAC Address and TYPE in the Matching Field. The count unit is determined by the TU bit (located in the Action rule). DS00002330E-page 44  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R • When 0, the unit is microsecond. • When 1, the unit is millisecond. The CA bit (located in the Action rule) determines the algorithm used to generate an interrupt when the count terminates. • When 0, an 11-bit counter will be loaded with the count value from the list and start counting down every unit time. An interrupt will be generated when the timer expires, i.e. the next qualified packet has not been received within the period specified by the value. • When 1, the counter is incremented with every matched packet received. An interrupt is generated when the terminal count is reached. The count resets thereafter. Time units are not used in this mode. TABLE 4-18: ACL MATCHING RULE PARAMETERS FOR MD = 10 Parameter Description MD[1:0] MODE 00 = Matching rule is disabled 01 = Layer 2 MAC header or counter filtering 10 = Layer 3 IP header filtering 11 = Layer 4 TCP header (and IP protocol) filtering ENB[1:0] 00 = Reserved 01 = IPv4 source or destination address (with mask) 10 = IPv4 source and destination address (without mask) 11 = Reserved S/D Source / Destination 0 = Destination address 1 = Source address EQ Equal / Not Equal 0 = Not Equal produces true result 1 = Equal produces true result IP ADDRESS[31:0] IPv4 address Source or destination address (determined by S/D) when ENB = 01, Source address when ENB = 10 IP MASK[31:0] Mask bits for the IPv4 address when ENB = 01: 0 = This bit of the address is compared 1 = This bit of the address is not compared Destination IPv4 address when ENB = 10 TABLE 4-19: ACL MATCHING RULE PARAMETERS FOR MD = 11 Parameter Description MD[1:0] MODE 00 = Matching rule is disabled 01 = Layer 2 MAC header or counter filtering 10 = Layer 3 IP header filtering 11 = Layer 4 TCP header (and IP protocol) filtering ENB[1:0] 00 = IP Protocol comparison is enabled 01 = TCP source/destination port comparison is enabled 10 = UDP source/destination port comparison is enabled 11 = TCP sequence number is compared S/D Source / Destination 0 = Destination address 1 = Source address EQ Equal / Not Equal 0 = Not Equal produces true result 1 = Equal produces true result  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 45 KSZ9897R TABLE 4-19: ACL MATCHING RULE PARAMETERS FOR MD = 11 (CONTINUED) Parameter Description MAX PORT[15:0] MIN PORT[15:0] Max and Min Ports for TCP/UDP or TCP Sequence Number[31:0] PC[1:0] Port Comparison 00 = Port comparison is disabled 01 = Port matches either one of MAX or MIN 10 = Match if port number is in the range of MIN to MIN 11 = Match if port number is out of the range PRO[7:0] IPv4 protocol to be matched FME TCP Flag Match Enable 0 = TCP FLAG matching disabled 1 = TCP FLAG matching enabled FMASK[7:0] TCP FLAG Mask 0 = This bit of the Flag field is compared 1 = This bit of the Flag field is not compared FLAG[7:0] TCP Flag to be matched 4.4.16.3 Action Rule Description TABLE 4-20: ACL ACTION RULE PARAMETERS FOR NON-COUNT MODES (MD ≠ 01 OR ENB ≠ 00) Parameter Description PM[1:0] Priority Mode 00 = ACL does not specify the packet priority. Priority is determined by standard QoS functions. 01 = Change packet priority to P[2:0] if it is greater than QoS result. 10 = Change packet priority to P[2:0] if it is smaller than the QoS result. 11 = Always change packet priority to P[2:0]. P[2:0] Priority value RPE Remark Priority Enable 0 = Disable priority remarking 1 = Enable priority remarking. VLAN tag priority (PCP) bits are replaced by RP[2:0]. RP[2:0] Remarked Priority value MM[1:0] Map Mode 00 = No forwarding remapping 01 = The forwarding map in FORWARD is OR'ed with the forwarding map from the Address Lookup Table. 10 = The forwarding map in FORWARD is AND'ed with the forwarding map from the Address Lookup Table. 11 = The forwarding map in FORWARD replaces the forwarding map from the Address Lookup Table. FORWARD[N-1:0] Forwarding Ports Bit 0 corresponds to port 1 Bit 1 corresponds to port 2, etc. 0 = Do not forward to this port 1 = Forward to this port DS00002330E-page 46  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 4-21: ACL ACTION RULE PARAMETERS FOR COUNT MODE (MD = 01 OR ENB = 00) Parameter Description COUNT[10:0] Count value TU Time unit for counter. 0 = Microseconds 1 = Milliseconds CA Counter Algorithm. 0 = An 11-bit counter will be loaded with the count value from the list and start counting down every unit time. An interrupt will be generated when the timer expires, i.e. the next qualified packet has not been received within the period specified by the value. 1 = The counter is incremented with every matched packet received. An interrupt is generated when the terminal count is reached. The count resets thereafter. Time units are not used in this mode. Figure 4-7 shows basic organization of the ACL Table. The table has 16 entries, and each entry includes a matching field, action field and process field. Although these fields are stored together in one table, it is important to note that for a given table entry, the Matching, Action and Process fields generally do not form an associated group. The one exception is when the Matching Rule is in Count Mode (MD = 01 and ENB = 00). In that case, the Matching and Action fields are used in tandem. FIGURE 4-7: ACL TABLE FORMAT S E / Q D MAC ADDRESS [47:0] TYPE [15:0] MD = 01 ENB != 00 F R N MD [1:0] ENB [1:0] S E / Q D MAC ADDRESS [47:0] TYPE [15:0] MD = 10 F R N MD [1:0] ENB [1:0] S E / Q D MD = 11 F R N MD [1:0] ENB [1:0] S E / Q D PROCESS Field 4.4.16.4 IP ADDRESS [31:0] MAX PORT [15:0] MIN PORT [15:0] Resvd (5) MATCHING Rule IP MASK [31:0] PC [1:0] PRO [7:0] F FMSK FLAG M [7:0] [7:0] E ENTRY # 0 ENB [1:0] ENTRY # 1 MD [1:0] ENTRY # 2 F R N ENTRY # 3 ENTRY # 4 ENTRY # 5 ENTRY # 6 ENTRY # 7 ENTRY # 8 ENTRY # 9 ENTRY # 10 ENTRY # 11 ENTRY # 12 ENTRY # 13 ENTRY # 14 ENTRY # 15 MD = 01 ENB = 00 COUNT[10:0] TU CA unu sed RULESET [15:0] PM [1:0] P [2:0] R P E RP [2:0] MM [1:0] FORWARD [# ports] RULESET [15:0] PM [1:0] P [2:0] R P E RP [2:0] MM [1:0] FORWARD [# ports] RULESET [15:0] PM [1:0] P [2:0] R P E RP [2:0] MM [1:0] FORWARD [# ports] RULESET [15:0] ACTION Rule PROCESS Field ACL Interrupts The ACL filtering functions do not generate interrupts. Interrupts apply only for the Count Mode (MD = 01, ENB = 00). The Matching Rule can be configured either to timeout if the interval between packets of a specific type (MAC address and EtherType), or when a set number of these packets are received. There is a separate interrupt for each port. Port specific interrupt status and masks are located in the Port Interrupt Status Register and Port Interrupt Mask Register. The top level interrupt registers for each port are in the Global Port Interrupt Status Register and Global Port Interrupt Mask Register.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 47 KSZ9897R 4.4.16.5 ACL Registers Table 4-22 provides a list of ACL related registers. TABLE 4-22: ACL REGISTERS Registers Description Port Interrupt Status Register, Port Interrupt Mask Register ACL interrupt Port ACL Access 0 Register through Port ACL Access F Register, Port ACL Byte Enable MSB Register, Port ACL Byte Enable LSB Register, Port ACL Access Control 0 Register ACL Table access Port Priority Control Register Priority classification Port Authentication Control Register ACL enable 4.5 NAND Tree Support The KSZ9897R provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree is a chain of nested NAND gates in which each KSZ9897R digital I/O (NAND tree input) pin is an input to one NAND gate along the chain. At the end of the chain, the INTRP_N pin provides the output for the last NAND gate. The NAND tree test process includes: • Enabling NAND tree mode • Pulling all NAND tree input pins high • Driving low each NAND tree input pin sequentially per the NAND tree pin order, starting with the first row of Table 4-23. • Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input driven low. TABLE 4-23: NAND TREE TEST PIN ORDER NAND Tree Sequence Pin Number Pin Name NAND Tree Description 1 48 TX_CLK6/REFCLKI6 Input 2 49 TX_EN6/TX_CTL6 Input 3 50 TX_ER6 Input 4 51 COL6 Input 5 52 TXD6_3 Input 6 53 TXD6_2 Input 7 54 TXD6_1 Input 8 55 TXD6_0 Input 9 57 RX_CLK6/REFCLKO6 Input 10 58 RX_DV6/CRS_DV6/RX_CTL6 Input 11 59 RX_ER6 Input 12 60 CRS6 Input 13 62 RXD6_3 Input 14 63 RXD6_2 Input 15 64 RXD6_1 Input 16 65 RXD6_0 Input 17 66 TX_CLK7/REFCLKI7 Input 18 67 TX_EN7/TX_CTL7 Input DS00002330E-page 48  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 4-23: NAND TREE TEST PIN ORDER (CONTINUED) NAND Tree Sequence Pin Number Pin Name NAND Tree Description 19 68 TX_ER7 Input 20 69 COL7 Input 21 70 TXD7_3 Input 22 71 TXD7_2 Input 23 72 TXD7_1 Input 24 73 TXD7_0 Input 25 75 RX_CLK7/REFCLKO7 Input 26 76 RX_DV7/CRS_DV7/RX_CTL7 Input 27 78 RX_ER7 Input 28 79 CRS7 Input 29 80 RXD7_3 Input 30 81 RXD7_2 Input 31 82 RXD7_1 Input 32 83 RXD7_0 Input 33 85 LED4_0 Input 34 86 LED4_1 Input 35 88 LED3_0 Input 36 89 LED3_1 Input 37 90 NC Input 38 91 LED2_0 Input 39 92 LED2_1 Input 40 93 PME_N Input 41 96 RESET_N Input 42 97 SDO Input 43 98 SDI/SDA/MDIO Input 44 100 SCS_N Input 45 101 SCL/MDC Input 46 102 LED5_0 Input 47 103 LED5_1 Input 48 105 LED1_0 Input 49 106 LED1_1 Input 50 94 INTRP_N Output The following procedure can be used to check for faults on the KSZ9897R digital I/O pin connections to the board: 1. 2. 3. Enable NAND tree mode via the LED2_1, LED2_0, and LED4_0 configuration strap pins option. Use board logic to drive all KSZ9897R NAND tree input pins high and verify that the INTRP_N pin output is high. Use board logic to drive each NAND tree input pin, per the NAND Tree pin order, as follows: a) Toggle the first pin in the NAND tree sequence (TX_CLK6/REFCLKI6) from high to low, and verify the INTRP_N pin switches from high to low to indicate that the first pin is connected properly. b) Leave the first pin (TX_CLK6/REFCLKI6) low. c) Toggle the second pin in the NAND tree sequence (TX_EN6/TX_CTL6) from high to low, and verify the INTRP_N pin switches from low to high to indicate that the second pin is connected properly. d) Leave the first pin (TX_CLK6/REFCLKI6) and the second pin (TX_EN6/TX_CTL6) low. e) Toggle the third pin in the NAND tree sequence (TX_ER6) from high to low, and verify the INTRP_N pin switches from high to low to indicate that the third pin is connected properly. f) Continue with this sequence until all KSZ9897R NAND tree input pins have been toggled.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 49 KSZ9897R Each KSZ9897R NAND tree input pin must cause the INTRP_N output pin to toggle high-to-low or low-to-high to indicate a good connection. If the INTRP_N pin fails to toggle when the KSZ9897R input pin toggles from high to low, the input pin has a fault. 4.6 4.6.1 Clocking PRIMARY CLOCK The device requires a 25MHz reference clock input at the XI pin. This clock is internally multiplied up and used to clock all of the internal logic and switching functions. It is also normally used as to clock the PHY transmit paths. This clock may be supplied by connecting a crystal between the XI and XO pins (and appropriate load capacitors to ground). Alternatively, an external CMOS clock signal may drive XI, while XO is left unconnected. The XI/XO block is powered from AVDDH. 4.6.2 MAC INTERFACE CLOCKS The MII interface is clocked asymmetrically, with the PHY device driving both the RX_CLKx receive clock and the TX_CLKx transmit clock to the MAC device. Each MII port may be configured at reset by a strapping option to take the role of either the PHY or the MAC. RX_CLKx and TX_CLKx are therefore either both inputs or both outputs, depending on the MII mode. The RMII interface uses a single 50MHz clock. This REFCLK may be sourced either from the KSZ9897R or from the connected device. A strapping option is used to select the mode for each port. “Normal Mode” is the mode where the other device supplies the clock, and the clock is an input to the REFCLKIx pin of the device. “Clock Mode” is the mode where the KSZ9897R generates the 50MHz clock on the REFCLKOx pin. The RGMII interface employs source synchronous clocking, so it is symmetrical and does not require a mode selection. An output clock is generated on the RX_CLKx pin, while an input clock is received on the TX_CLKx pin. The clock speed scales with the interface data rate - either 10, 100 or 1000 Mbps. A strapping option is used to select between the 100 and 1000 Mbps speeds. If the 10 Mbps rate is required, then a register setting is used to set that speed. The MAC interfaces are powered from VDDIO. Note: 4.6.3 Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information on using configuration straps. SERIAL MANAGEMENT INTERFACE CLOCK Whether configured to be SPI, I2C or MIIM, the KSZ9897R is always a slave and receives the clock as an input. The serial management interface is powered from VDDIO. 4.6.4 CLKO_25_125 An output clock, derived from the local 25MHz reference at XI, is provided on the CLKO_25_125 pin. The output frequency choices are 25MHz (default) and 125MHz. If not needed, this output clock can also be disabled. CLKO_25_125 is controlled via the Output Clock Control Register, and is powered from VDDIO. DS00002330E-page 50  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.7 Power The KSZ9897R requires two to three supply voltages. The device core operates from a 1.2V supply (DVDDL and AVDDL). The PHY transceivers and XI/XO crystal/clock interface operate from a 2.5V supply (AVDDH). The digital I/ O's can be operated from 1.8V, 2.5V or 3.3V (VDDIO). The digital I/Os powered from VDDIO include RGMII, RMII, MII, SPI, I2C, MIIM, LED, RESET_N, PME_N, INTRP_N and CLKO_25_125. An example power connection diagram can be seen in Figure 4-8 . FIGURE 4-8: POWER CONNECTION DIAGRAM +1.2V +2.5V 22µF 22µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL AVDDH AVDDH AVDDH AVDDH AVDDH AVDDH AVDDH 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DVDDL +1.8V, 2.5V or 3.3V 10µF VDDIO 22µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 4.8 VDDIO AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL VDDIO 0.1µF 0.1µF 0.1µF GND GND GND GND GND GND GND (exposed pad) Power Management The device supports enhanced power management features in a low-power state with energy detection to ensure lowpower dissipation during device idle periods. There are three operation modes under the power management function which are implemented globally (i.e., applying to all ports): • Normal Operation Mode • Energy Detect Mode • Global Soft Power Down Mode Table 4-24 summarizes all internal function blocks status under the three power-management operation modes.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 51 KSZ9897R TABLE 4-24: MDI/MDI-X PIN DEFINITIONS Functional Blocks Power Management Operation Modes Normal Mode Energy Detect Mode Soft Power Down Mode Internal PLL Clock Enabled Disabled Disabled TX/RX PHYs Enabled Energy Detect at RX Disabled MACs Enabled Disabled Disabled Host Interface Enabled Disabled Disabled There is one additional power saving mode that may be implemented on a per-port basis: • Port-Based Power Down The first three global power modes are mutually exclusive; only one mode may be selected at a time. Port-based power down may be enabled independent of the global power mode. 4.8.1 NORMAL OPERATION MODE At power-up, the device enters into Normal operation mode. It is also selected via bits [4:3] = 00 in the Power Down Control 0 Register. When the device is in normal operation mode, all PLL clocks are running, PHYs and MACs are on, and the CPU is ready to read or write the device registers through the serial interface (SPI, I2C or MIIM). During normal operation mode, the host processor can change the power management mode bits in the Power Down Control 0 Register to transition to any of the other power management modes. 4.8.2 ENERGY-DETECT MODE Energy-detect mode, also known as energy-detect power down (EDPD) mode, is enabled by setting bits [4:3] to 01 in the Power Down Control 0 Register. Energy-detect mode provides a mechanism to save power when the device is not connected to an active link partner. Auto-negotiation must be enabled when in energy-detect mode. Energy-detect mode consists of two states, normal-power state and low-power state. When the device is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than a pre-configured value, the device will go into the low-power state. While in low-power state, the device reduces power consumption by disabling all circuitry except the energy-detect circuitry of the receiver, which consumes minimal power. When the device is in the lowpower state, it will transmit link pulses at long intervals, with a very low duty cycle. At the same time, it continuously monitors for energy on the cable. Once energy is detected from the cable and is present for a time longer than 100ns, the device will enter the normal-power state. 4.8.3 GLOBAL SOFT POWER-DOWN MODE Soft power-down mode is used to power down the device when it is not in use after power-up. This mode disables all internal functions except for the serial (SPI or I2C) management interface. When soft power-down mode is exited, all registers are reset to their default values, and all configuration strap pins are sampled to set the device settings. 4.8.4 PORT-BASED POWER DOWN Unused ports may be powered down individually to save power. 4.8.5 WAKE ON LAN (WOL) Wake on LAN allows a computer to be turned on or woken up by a network message. The message is usually sent by a program executed on another computer on the same local area network. Wake-up frame events are used to awaken the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. The device can be programmed to notify the host of the Wake-Up frame detection with the assertion of the power management event signal (PME_N). The device’s MACs support the detection of the following Wake-Up events: • Detection of energy signal over a pre-configured value • Detection of a linkup in the network link state DS00002330E-page 52  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R • Receipt of a Magic Packet There are also other types of Wake-Up events that are not listed here as manufacturers may choose to implement these in their own way. 4.8.5.1 Direction of Energy The energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. 4.8.5.2 Direction of Link-up Link status wake events are useful to indicate a linkup in the network's connectivity status. 4.8.5.3 Magic PacketTM The Magic Packet is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF) followed by sixteen repetitions of the target computer's 48-bit DA MAC address. Since the magic packet is only scanned for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer protocol. Magic Packet technology is used to remotely wake up a sleeping or powered-off PC on a LAN. This is accomplished by sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the LAN controller receives a Magic Packet frame, it will alert the system to wake up. Once the device has been enabled for Magic Packet Detection, it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet frame. A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address (SA), Destination Address (DA), which may be the receiving station's IEEE MAC address, or a multicast or broadcast address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node, with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the address of the machine to be awakened. 4.8.5.4 Interrupt Generation on Power Management Related Events There are two ways an interrupt can be generated to the host whenever a power management related event takes place. The resulting interrupts are via the PME_N signal pin or via the INTRP_N signal pin. 4.9 Management Interface The management interface may be used by an external host processor to read and write the device’s registers. This interface has three available modes of operation: SPI, I2C or MIIM. The interface mode is selected at the deassertion of reset by a strapping option (refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information). Of the three interface options, SPI provides the highest performance, while MIIM performance is the lowest. Most importantly, MIIM provides access to the PHY control and status registers, but not to any of the switch registers. The vast majority of applications therefore can use SPI or I2C, but not MIIM. Register access is also available through the high-performance in-band management interface as described in Section 4.10, "In-Band Management," on page 57. 4.9.1 SPI SLAVE BUS The KSZ9897R supports a slave mode SPI interface that provides complete access to all device registers via an SPI master device. The SPI master device supplies the clock (SCL), select (SCS_N), and serial input data (SDI). Serial output data (SDO) is driven by the KSZ9897R. SCL is expected to stay low when SPI operation is idle. SPI operations start with the falling edge of SCS_N and end with the rising edge of SCS_N. A single read or write access consists of a 27-bit command/address phase, then a 5-bit turnaround (TA) phase, then an 8-bit data phase. For burst read or write access, SCS_N is held low while SCL continues to toggle. For every 8 cycles of SCL, the device will increment the address counter, and the corresponding data byte will be transferred on SDI or SDO in succession. All commands, addresses and data are transferred most significant bit first. Input data on SDI is latched on the rising edge of clock SCL. Output data on SDO is clocked on the falling edge of SCL.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 53 KSZ9897R As shown in Figure 4-25, there are two commands: register read and register write. Figure 4-9 and Figure 4-10 show the timing for these two operations. TABLE 4-25: REGISTER ACCESS USING THE SPI INTERFACE SPI Operation Command/Address Phase (SDI pin) Data Phase (SDO or SDI pins) TA bits (Note 4-8) Command Register Address Register Read 011 A23 A22 A21 A20 … A7 A6 A5 A4 A3 A2 A1 A0 XXXXX D7 D6 D5 D4 D3 D2 D1 D0 Register Write 010 A23 A22 A21 A20 … A7 A6 A5 A4 A3 A2 A1 A0 XXXXX D7 D6 D5 D4 D3 D2 D1 D0 Note 4-8 Note: TA bits are turn-around bits. They are “don't care” bits. The actual device address space is 16 bits (A15 - A0), so the values of address bits A23 - A16 in the SPI command/address phase are “don't care”. FIGURE 4-9: SPI REGISTER READ OPERATION SCS_N 1 2 3 0 1 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TA TA TA TA TA 33 34 35 36 37 38 39 40 SCL SDI (MOSI) SDO D7 D6 D5 D4 D3 D2 D1 D0 (MISO) Read Command Read Address FIGURE 4-10: TurnAround Read Data SPI REGISTER WRITE OPERATION SCS_N 1 2 3 0 1 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TA TA TA TA TA D7 D6 D5 D4 D3 D2 D1 D0 SCL SDI (MOSI) SDO (MISO) Write Command 4.9.2 Write Address TurnAround Write Data I2C BUS The management interface may be configured to be an I2C slave. In this mode, an I2C master has complete programming access to the device's internal control and status registers, including all MIB counters, address lookup tables, VLAN table and ACL table. The 7-bit device address is fixed as 1011_111. Because of the fixed address, only one KSZ9897R may be on the I2C bus at a time. The R/W control bit is then appended as the least significant bit to form these 8-bit address/control words: 1011_1110 1011_1111 DS00002330E-page 54  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R The internal registers and tables of the device are accessed using 16-bit addressing and 8-bit data. The access formats are as follows: FIGURE 4-11: SINGLE BYTE REGISTER WRITE FIGURE 4-12: SINGLE BYTE REGISTER READ FIGURE 4-13: BURST REGISTER WRITE FIGURE 4-14: BURST REGISTER READ 4.9.3 MII MANAGEMENT (MIIM) INTERFACE The device supports the IEEE 802.3 MII management interface, also known as the management data input/output (MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ9897R PHY blocks, but it does not provide access to the switch registers. An external device with MDC/MDIO capability can read the PHY status or configure the PHY settings. Details on the MIIM interface can be found in Clauses 22 and 45 of the IEEE 802.3 Specification. Use of MIIM conflicts with use of the In-Band Management interface. These interfaces cannot be used simultaneously. The MIIM interface consists of the following: • A physical connection that uses a data signal (MDIO) and a clock signal (MDC) for communication between an external controller and the KSZ9897R. Note that the MDIO signal is open-drain. • A specific protocol that operates across the two signal physical connection that allows an external controller to communicate with the internal PHY devices. • Access to a set of standard, vendor-specific and extended (MMD) 16-bit registers. These registers are also directly accessible via the SPI and I2C interface options.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 55 KSZ9897R The MIIM Interface can operate up to a maximum clock speed of 5MHz. Access is limited to only the registers in the PHY blocks of ports 1 through 5. Table 4-26 summarizes the MII management interface frame format. TABLE 4-26: MII MANAGEMENT INTERFACE FRAME FORMAT Preamble (32-bit) Start of Frame (2-bit) Operation Code (2-bit) PHY Address (5-bit) Register Address (5-bit) Turn Around (2-bit) Register Data (16-bit) Read All 1s 01 10 A[4:0] Reg[4:0] Z0 D[15:0] Z Write All 1s 01 01 A[4:0] Reg[4:0] 10 D[15:0] Z Operation Mode Idle The MIIM PHY address to PHY port mapping is as follows: • • • • • PHY Address 1h to PHY port 1 PHY Address 2h to PHY port 2 PHY Address 3h to PHY port 3 PHY Address 4h to PHY port 4 PHY Address 5h to PHY port 5 The MIIM register address space consists of two distinct areas. • Standard MIIM Registers (Direct) • MDIO Manageable Device (MMD) Registers (Indirect) 4.9.3.1 Standard MIIM Registers (Direct) Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE 802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor. The KSZ9897R supports the standard registers listed in Table 4-27 for each PHY port. Each 16-bit MIIM Standard Register Address maps to two corresponding 8-bit Port N Register Addresses. The register bit map and description are located at the 8-bit Port N Register Addresses. TABLE 4-27: STANDARD MIIM REGISTERS MIIM Standard Register Address (hex) Port N Register Address (hex) Description 0h 0xN100 - 0xN101 PHY Basic Control Register 1h 0xN102 - 0xN103 PHY Basic Status Register 2h 0xN104 - 0xN105 PHY ID High Register 3h 0xN106 - 0xN107 PHY ID Low Register IEEE-Defined Registers 4h 0xN108 - 0xN109 PHY Auto-Negotiation Advertisement Register 5h 0xN10A - 0xN10B PHY Auto-Negotiation Link Partner Ability Register 6h 0xN10C - 0xN10D PHY Auto-Negotiation Expansion Status Register 7h 0xN10E - 0xN10F PHY Auto-Negotiation Next Page Register 8h 0xN110 - 0xN111 PHY Auto-Negotiation Link Partner Next Page Ability Register 9h 0xN112 - 0xN113 PHY 1000BASE-T Control Register Ah 0xN114 - 0xN115 Bh-Ch - PHY 1000BASE-T Status Register RESERVED Dh 0xN11A - 0xN11B PHY MMD Setup Register Eh 0xN11C - 0xN11D PHY MMD Data Register Fh 0xN11E - 0xN11F PHY Extended Status Register DS00002330E-page 56  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 4-27: STANDARD MIIM REGISTERS (CONTINUED) MIIM Standard Register Address (hex) Port N Register Address (hex) Description Vendor-Specific Registers 10h - 11h 0xN122 - 0xN123 PHY Remote Loopback Register 12h 0xN124 - 0xN125 PHY LinkMD Register 13h 0xN126 - 0xN127 PHY Digital PMA/PCS Status Register 14h - 15h 0xN12A - 0xN12B 16h-1Ah - 1Bh 0xN136 - 0xN137 1Ch 0xN138 - 0xN139 1Dh-1Eh - 1Fh 0xN13E - 0xN13F 4.9.3.2 RESERVED RESERVED Port RXER Count Register RESERVED Port Interrupt Control / Status Register PHY Auto MDI / MDI-X Register RESERVED PHY Control Register MDIO Manageable Device (MMD) Registers (Indirect) The MIIM interface provides indirect access to a set of MMD registers as defined in Section 5.4, "MDIO Manageable Device (MMD) Registers (Indirect)," on page 165. 4.10 In-Band Management The in-band management access (IBA) is a feature that provides full register read and write access via any one of the seven data ports. Port 7 is the default IBA port. The in-band feature is enabled or disabled by a strapping option at power-up and reset. To use a different port instead of port 7 for IBA, the SPI or I2C interface or IBA must be used to write to a control register. IBA may not be used on more than one port at a time, but the IBA port can still be used for sending and receiving non-IBA traffic. In-band management frames are processed differently from normal network frames. They are recognized as special frames, so address and VID lookup, VLAN tagging, source address filtering, un-tag discard, tagged frame drop, etc. are not applied to them. Received in-band management frames are never forwarded to the switch fabric or to any other port. The In-Band Management (IBA) Control Register is used to enable and control the IBA feature and to specify one of the seven ports as the IBA port. The IBA frame format is shown in Figure 4-15. The layer 2 portion of the IBA frame contains normal destination address (DA) and source address (SA) fields. The DA of the frames are defined to be the switch MAC address (default 00-10A1-FF-FF-FF), and the SA is the MAC address of the source device. The DA and SA will be swapped in the response frame. A special 4-byte IBA tag follows the SA. This is then followed by the 2-byte EtherType/Length field that serves to identify this as an IBA frame. Only one IBA frame can be processed at a time. Any subsequent IBA frames received by the device will be dropped unless the most recent response frame has been fully transmitted. There are six types of read/write commands: READ, WRITE, WAIT on 0, WAIT on 1, MODIFY to 0 and MODIFY to 1. The minimum IBA read or write size is 32-bits. There is no IBA option for 8-bit or 16-bit transfers. The burst commands offer fast and bundled data return, up to the capacity of the IBA frame buffer. There are two types of operations in burst command: READ burst and Write burst.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 57 KSZ9897R FIGURE 4-15: IN-BAND MANAGEMENT FRAME FORMAT LSB 0 1 2 3 4 7 Bytes PREAMBLE 1 Byte SFD 6 Bytes DES. ADDRESS 5 6 Bytes SRC. ADDRESS 2 Bytes IBAF TAG TYPE 2 Bytes IBAF TAG CONTROL INFO. 2 Bytes MAC LENGTH/TYPE 2 Bytes 2 Bytes 6 7 MSB i/g u/l 46 bit address 010xxxxx 11111110 i/g=0, Individual Address; i/g=1, Group Address u/l=0, Globally Admin. Addr. u/l=1, Locally Admin. Addr. TPID Sequence # 3 bits of Priority, 1 bit of Canonical Format Indicator = 0 4 bits of mode, 8 bits of sequence # 10011000 00000000 0x9800 for 98xx Family ACCESS FORMAT 00000000 00000000 Reserved Reserved 0x0001 = Rd/Wr, 0x0002 = Burst p cfi mode IBAF TAG 2 Bytes IBAF Layer 3 Data – MAC DATA ACCESS CODE 4 Bytes ACCESS COMMAND 4 Bytes DATA 4 Bytes ACCESS COMMAND/DATA 4 Bytes DATA 4 Bytes ACCESS COMMAND/DATA 4 Bytes DATA 4 Bytes ACCESS COMMAND/DATA 4 Bytes DATA 4 Bytes ACCESS COMMAND/DATA 4 Bytes DATA COMMAND = 0x0001 (Rd/Wr) OP. 0eeeeAAAAAAAA Code AAAAAAAAAAAAAAAA COMMAND = 0x0002 (Burst) Dir 000000AAAAAAAA AAAAAAAAAAAAAAAA 3 bits of OP code: 001 = READ, 010 = WRITE, 100 = WAIT on 0, 101 = WAIT on 1, 110 = MODIFY to 0, 111 = MODIFY to 1, COMMAND = 0x0002000 (Dump) = end of command list OP. eeee = Byte enable 0000000000000 Code AAAA..AAAA[23:0] = Register Address 00000000000aaaaa 2 bits of Direction: 01 = READ, 10 = WRITE, AAAA..AAAA[23:0] = Starting Register Address COMMAND = 0x0001 (Rd/Wr) 0xdddddddd dddddddd = data written/read COMMAND = 0x0001 (WAIT/ MODIFY) 0xmaskmask Variable PAD 4 Bytes FRAME CHECK SEQUENCE Variable EXTENSION Mask (1) = bit in reg. to be tested for OP code 100/101 OR set (1) = bit to be set to 0/1 based on OP code 110/111 COMMAND = 0x0002 (Burst) 26 0's and 6 bits of burst count Bits Transmitted from Left to Right 4.11 MAC Interface (RGMII/MII/RMII Port 6-7) Strapping options are used to individually select any of these MAC interface options for ports 6 and 7: • Media Independent Interface (MII): Supports 100 and 10 Mbps data rates • Reduced Media Independent Interface (RMII): Supports 100 and 10 Mbps data rates • Reduced Gigabit Media Independent Interface (RGMII): Supports 1000, 100 and 10 Mbps data rates Note that the signals on the KSZ9897R MAC interfaces are named as they would be for a PHY: the TX direction is into the KSZ9897R, while the RX direction is out of the KSZ9897R, as if to a host processor with integrated MAC. Signal connection to such a “MAC” device is TX-to-TX, and RX-to-RX. An external PHY (such as the Microchip KSZ9031RNX) may be connected to either port, but in that case the signal connection will be RX-to-TX, and TX-to-RX. The RGMII/MII/RMII interfaces are powered by the VDDIO power supply. DS00002330E-page 58  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 4.11.1 MEDIA INDEPENDENT INTERFACE (MII) The media independent interface (MII) is specified in Clause 22 of the IEEE 802.3 standard. It provides a common interface between PHY layer and MAC layer devices. The data interface is 4-bits wide and runs at one quarter the network bit rate; either 2.5MHz in 10BASE-Te or 25MHz in 100BASE-TX (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side provides signals that convey when the data is valid and without physical layer errors. For half duplex operation, the COL signal indicates if a collision has occurred during transmission. Each MII interface operates in either PHY Mode or MAC Mode. Select PHY Mode when the port is connected to a processor or other device with a MAC function; select MAC Mode when connecting to an external PHY. Note that the direction of the TX_CLKx, RX_CLKx, COLx and CRSx signals is affected by the PHY mode or MAC mode setting, while other MII signals do not change direction. MII mode is selected at reset by a configuration strap option on pins RXD6_3 and RXD6_2 for port 6, and pins RXD7_3 and RXD7_2 for port 7. The Speed strapping option (on pin RXD6_0 for port 6 and RXD7_0 for port 7) should be set for 100/10 Mbps Mode. PHY Mode or MAC Mode is selected by strapping option on pins RXD6_1 (port 6) and RXD7_1 (port 7). Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information. The interface contains two distinct groups of signals, one for transmission and the other for reception. Table 4-28 and Table 4-29 describe the signals used by the MII interface to connect to an external MAC or to an external PHY, respectively. TABLE 4-28: MII (PHY MODE) CONNECTION TO EXTERNAL MAC MII Interface Signals Description KSZ9897R Signals in PHY Mode External MAC Device Signals Transmit Enable TX_ENx (input) TX_EN (output) Transit Error TX_ERx (input) TX_ER (output) Transmit Data Bits [3:0] TXDx_[3:0] (input) TXD[3:0] (output) Transmit Clock TX_CLKx (output) TX_CLK (input) Collision Detection COLx (output) COL (input) Carrier Sense CRSx (output) CRS (input) Received Data Valid RX_DVx (output) RX_DV (input) Receive Error RX_ERx (output) RX_ER (input) Receive Data Bits [3:0] RXDx_[3:0] (output) RXD[3:0] (input) Receive Clock RX_CLKx (output) RX_CLK (input) TABLE 4-29: MII (MAC MODE) CONNECTION TO EXTERNAL PHY MII Interface Signals Description KSZ9897R Signals in MAC Mode External PHY Device Signals Transmit Enable RX_DVx (output) TX_EN (input) Transit Error RX_ERx (output) TX_ER (input) Transmit Data Bits [3:0] RXDx_[3:0] (output) TXD[3:0] (input) Transmit Clock RX_CLKx (input) TX_CLK (output) Collision Detection COLx (input) COL (output) 4.11.2 Carrier Sense CRSx (input) CRS (output) Received Data Valid TX_ENx (input) RX_DV (output) Receive Error TX_ERx (input) RX_ER (output) Receive Data Bits [3:0] TXDx_[3:0] (input) RXD[3:0] (output) Receive Clock TX_CLKx (input) RX_CLK (output) REDUCED MEDIA INDEPENDENT INTERFACE (RMII) The reduced media independent interface (RMII) specifies a low pin count interface, which is based on MII, that provides communication with a MAC attached to the port. As with MII, RMII provides a common interface between physical layer and MAC layer devices, or between two MAC layer devices, and has the following key characteristics: • Supports network data rates of either 10Mbps or 100Mbps.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 59 KSZ9897R • Uses a single 50MHz clock reference (provided internally or externally) for both transmit and receive data. • Uses independent 2-bit wide transmit and receive data paths. • Contains two distinct groups of signals: one for transmission and the other for reception. The user selects one of the two RMII clocking modes by setting the appropriate strapping option. The clocking mode is selected separately for ports 6 and 7. While in RMII Normal Mode, the port will require an external 50MHz signal to be input to TX_CLKx/REFCLKIx from an external source. This mode is selected by strapping the appropriate pin (RXD6_1 for port 6; RXD7_1 for port 7) high during reset. While in RMII Clock Mode, the port will output a 50MHz clock on RX_CLKx/REFCLKOx, which is derived from the 25MHz crystal or oscillator attached to the XI clock input. The TX_CLKx/REFCLKIx input is unused in this mode. This mode is selected by strapping the appropriate pin (RXD6_1 for port 6; RXD7_1 for port 7) low during reset. Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional configuration strap information. Table 4-30 describes the signals used by the RMII interface. Refer to the RMII specification for full details on the signal descriptions. TABLE 4-30: RMII SIGNAL DESCRIPTIONS RMII Signal Name (per spec) RMII Signal (per KSZ9897R) Pin Direction (with respect to PHY, KSZ9897R) Pin Direction (with respect to MAC) RMII Signal Description REF_CLK REFCLKI6 REFCLKI7 Input Input or Output Synchronous 50MHz reference clock, when port is in RMII Normal Mode n/a REFCLKO6 REFCLKO7 Output Input Synchronous 50MHz reference clock, when port is in RMII Clock Mode TX_EN TX_EN6 TX_EN7 Input Output Transmit Enable TXD[1:0] TXD6_[1:0] TXD7_[1:0] Input Output Transmit Data Bit [1:0] CRS_DV RX_DV6 RX_DV7 Output Input RX_ER RX_ER6 RX_ER7 Output Input or not required RXD[1:0] RXD6_[1:0] RXD7_[1:0] Output Input Carrier Sense / Receive Data Valid Receive Error Receive Data Bit [1:0] A device port in RMII mode may connect to either an external MAC device (such as a host processor) or to an external PHY; but unlike MII, RMII does not provide separate PHY and MAC modes of operation. However, it is necessary to connect the pins properly. TABLE 4-31: RMII CONNECTION TO EXTERNAL MAC RMII Interface Signals Description KSZ9897R Signals External MAC Device Signals Transmit Enable TX_ENx (input) TX_EN (output) Transmit Data Bits [1:0] TXDx_[1:0] (input) TXD[1:0] (output) Reference Clock REFCLKIx (input) or REFCLKOx (output) REF_CLK (input or output) Carrier Sense Data Valid RX_DVx (output) CRS_DV (input) Receive Error RX_ERx (output) RX_ER (input) Receive Data Bits [1:0] RXDx_[1:0] (output) RXD[1:0] (input) DS00002330E-page 60  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 4-32: RMII CONNECTION TO EXTERNAL PHY RMII Interface Signals Description KSZ9897R Signals External PHY Device Signals Transmit Enable RX_DVx (output) TX_EN (input) Transmit Data Bits [1:0] RXDx_[1:0] (output) TXD[1:0] (input) Reference Clock REFCLKIx (input) or REFCLKOx (output) REF_CLK (input or output) Carrier Sense Data Valid TX_ENx (input) CRS_DV (output) Receive Error No connection RX_ER (output) Receive Data Bits [1:0] TXDx_[1:0] (input) RXD[1:0] (output) 4.11.3 REDUCED GIGABIT MEDIA INDEPENDENT INTERFACE (RGMII) RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics: • • • • Pin count is reduced from 24 pins for GMII to 12 pins for RGMII. All speeds (10Mbps, 100Mbps and 1000Mbps) are supported at both half- and full-duplex. Data transmission and reception are independent and belong to separate signal groups. Transmit data and receive data are each four bits wide - a nibble. In RGMII operation, the RGMII pins function as follows: • The MAC sources the transmit reference clock, TX_CLKx, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and 2.5MHz for 10Mbps. • The PHY recovers and sources the receive reference clock, RX_CLKx, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and 2.5MHz for 10Mbps. • For 1000BASE-T, the transmit data, TXDx_[3:0], is presented on both edges of TX_CLKx, and the received data, RXDx_[3:0], is clocked out on both edges of the recovered 125MHz clock, RX_CLKx. • For 10BASE-T/100BASE-TX, the MAC holds TX_CTLx low until both the PHY and MAC operate at the same speed. During the speed transition, the receive clock is stretched on either a positive of neagative pulse to ensure that no clock glitch is presented to the MAC. • TX_ERx and RX_ERx are combined with TX_ENx and RX_DVx, respectively, to form TX_CTLx and RX_CTLx. These two RGMII control signals are valid at the falling clock edge. After power-up or reset, the device is configured to RGMII mode if the appropriate configuration strap pins are set to one of the RGMII mode capability options. Refer to Section 3.2.1, "Configuration Straps," on page 16 for available options. Note that there is no mechanism for the RGMII interface to adapt its speed automatically to the speed of the connected RGMII device. A configuration strap option sets the speed of each RGMII interface at power-up to either 1000Mbps or 100Mbps. For each port, a control register can override the configuration strap option and set the RGMII speed to either 1000, 100 or 10Mbps. If a PHY is connected to an RGMII port, it should be ensured that the PHY link speed is fixed in order to avoid a mismatch to the RGMII speed. The device provides the option to add a minimum of 1.5ns internal delay to either TX_CLKx or RX_CLKx, via the RGMII Internal Delay control bits in the XMII Port Control 1 Register. This can reduce or eliminate the need to add trace delay to the clock signals on the printed circuit board. RGMII_ID_ig enables delay on TX_CLKx, and the default is off. RGMII_ID_eg enables delay on RX_CLKx, and the default is on. Users should also be aware of any internal clock delay that may be added by the connected RGMII device.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 61 KSZ9897R TABLE 4-33: RGMII SIGNAL DESCRIPTIONS RGMII Signal Name (per spec) RGMII Signal (per KSZ9897R) Pin Direction (with respect to PHY, KSZ9897R) Pin Direction (with respect to MAC) TXC TX_CLK6 TX_CLK7 Input Output Transmit Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) TX_CTL TX_CTL6 TX_CTL7 Input Output Transmit Control TXD[3:0] TXD6_[3:0] TXD7_[3:0] Input Output Transmit Data [3:0] RXC RX_CLK6 RX_CLK7 Output Input Receive Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) RX_CTL RX_CTL6 RX_CTL7 Output Input Receive Control RXD[3:0] RXD6_[3:0] RXD7_[3:0] Output Input Receive Data [3:0] DS00002330E-page 62 RGMII Signal Description  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.0 DEVICE REGISTERS The KSZ9897R has a rich set of registers for device management. The registers are accessed by the SPI or I2C interfaces, or by in-band management. Alternatively, the MIIM interface can be used to access the PHY registers only. The MIIM interface cannot access the switch registers. A 16-bit address is used to access the device registers. This address is split into three hierarchical spaces, as shown in Figure 5-1. These three spaces are used to designate the port/channel (4-bits), function (page) of the port (4-bits), and register of function (8-bits). The individual ports are numbered 1 through 7. In the port space, a value of 0 is used for global registers. Address bit 15 is always 0. FIGURE 5-1: Examples: Register Address REGISTER ADDRESS MAPPING 0 N N N 0 1 0 0 0 0 0 0 1 0 0 0 = 0xN408 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 = 0x0312 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port Space Function Space (Page) Register Space 0 = Global 0 = Operation 1 = I/O Interface 2 = PHY 3 = General 4 = Look-up Tables 5-F = Reserved N = Port # 0 = Operation 1 = PHY 2 = Reserved 3 = RGMII / MII / RMII 4 = MAC 5 = MIB Counters 6 = ACL 7 = Reserved 8 = Ingress – Classification, Policing 9 = Egress – Shaping A = Queue management B = Address lookup engine C-F = Reserved Values of N are 1 - 7  2022 Microchip Technology Inc. and its subsidiaries Control, Status, Storage, Etc. DS00002330E-page 63 KSZ9897R Register addressing is by bytes, and the management interface (SPI, I2C or in-band) transfers data by bytes. Where registers are shown as 16-bits or 32-bits, this is for descriptive purposes only. Data can always be written and read as individual bytes and in any order. For multi-byte registers, the data is addressed in a big-endian format, with the most significant byte at the lowest address, and the least significant byte at the highest address, as shown in Figure 5-2. FIGURE 5-2: BYTE ORDERING 16-bit register 32-bit register 0A0B0 0A0B0C0D 0A address a+1 0B 0A address a+1 0B address a address a memory address a+2 0C address a+3 0D memory The global and port register address maps are detailed in Table 5-1 and Table 5-2, respectively. Table 1-3, “Register Nomenclature,” on page 7 provides a list of register bit type notations. The remainder of this chapter is organized as follows: • • • • Global Registers Port Registers Tables and MIB Counters (Access) MDIO Manageable Device (MMD) Registers (Indirect) TABLE 5-1: GLOBAL REGISTER ADDRESS MAP Address Functional Group 0x0000 - 0x00FF Global Operation Control Registers (0x0000 - 0x00FF) 0x0100 - 0x01FF Global I/O Control Registers (0x0100 - 0x01FF) 0x0200 - 0x02FF Global PHY Control and Status Registers (0x0200 - 0x02FF) 0x0300 - 0x03FF Global Switch Control Registers (0x0300 - 0x03FF) 0x0400 - 0x04FF Global Switch Look Up Engine (LUE) Control Registers (0x0400 - 0x04FF) 0x0500 - 0x0FFF RESERVED DS00002330E-page 64  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 5-2: PORT N (1-7) REGISTER ADDRESS MAP Address Functional Group 0xN000 - 0xN0FF Port N: Port Operation Control Registers (0xN000 - 0xN0FF) 0xN100 - 0xN1FF Port N: Port Ethernet PHY Registers (0xN100 - 0xN1FF) 0xN200 - 0xN2FF RESERVED 0xN300 - 0xN3FF Port N: Port RGMII/MII/RMII Control Registers (0xN300 - 0xN3FF) 0xN400 - 0xN4FF Port N: Port Switch MAC Control Registers (0xN400 - 0xN4FF) 0xN500 - 0xN5FF Port N: Port Switch MIB Counters Registers (0xN500 - 0xN5FF) 0xN600 - 0xN6FF Port N: Port Switch ACL Control Registers (0xN600 - 0xN6FF) 0xN700 - 0xN7FF RESERVED 0xN800 - 0xN8FF Port N: Port Switch Ingress Control Registers (0xN800 - 0xN8FF) 0xN900 - 0xN9FF Port N: Port Switch Egress Control Registers (0xN900 - 0xN9FF) 0xNA00 - 0xNAFF Port N: Port Switch Queue Management Control Registers (0xNA00 - 0xNAFF) 0xNB00 - 0xNBFF Port N: Port Switch Address Lookup Control Registers (0xNB00 - 0xNBFF) 0xNC00 - 0xNFFF RESERVED Note: RESERVED address space must not be written under any circumstances. Failure to heed this warning may result in untoward operation and unexpected results. If it is necessary to write to registers which contain both writable and reserved bits in the same register, the user should first read back the reserved bits (RO or R/W), “OR” the desired settable bits with the value read, and then write back the “ORed” value to the register.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 65 KSZ9897R 5.1 Global Registers This section details the device’s global registers. For an overview of the device’s entire register map, refer to Section 5.0, "Device Registers". For details on the device’s port registers, refer to Section 5.2, "Port Registers". 5.1.1 5.1.1.1 GLOBAL OPERATION CONTROL REGISTERS (0x0000 - 0x00FF) Global Chip ID 0 Register Address: Bits 7:0 5.1.1.2 0x0001 Size: Default RO 0x00 Type Default RO 0x98 Type Default RO 0x97 Type Default 8 bits Description Chip ID (MSB) Global Chip ID 2 Register Bits 5.1.1.4 Type Global Chip ID 1 Register Address: 7:0 8 bits Fixed Value Bits 5.1.1.3 Size: Description Address: 7:0 0x0000 0x0002 Size: 8 bits Description Chip ID (LSB) Global Chip ID 3 Register Address: Bits 0x0003 Size: 8 bits Description 7:4 Revision ID RO - 3:1 RESERVED RO - Global Software Reset This bit dos not self-clear. Refer to the Switch Operation Register for another reset control bit. 0 = Normal operation 1 = Resets the data path and state machines, but not register values. R/W 0b 0 DS00002330E-page 66  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.1.1.5 PME Pin Control Register Address: Bits 0x0006 Size: 8 bits Type Default RESERVED RO - 1 PME Pin Output Enable 0 = Disabled 1 = Enabled R/W 0b 0 PME Pin Output Polarity 0 = PME is active low 1 = PME is active high R/W 0b 7:2 5.1.1.6 Description Global Interrupt Status Register Address: 0x0010 - 0x0013 Size: 32 bits This register provides the top level interrupt status for the LUE. These interrupts are enabled in the Global Interrupt Mask Register. For port specific interrupts, refer to the Port Interrupt Status Register. Bits 31 Description Lookup Engine (LUE) Interrupt Status Type Default RO 0b RO - Type Default R/W 0b RO - Refer to the Address Lookup Table Interrupt Register for detailed LUE interrupt status bits. 0 = No interrupt 1 = Interrupt request 30:0 5.1.1.7 RESERVED Global Interrupt Mask Register Address: 0x0014 - 0x0017 Size: 32 bits This register enables the interrupts in the Global Interrupt Status Register. Bits 31 Description Lookup Engine (LUE) Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled 30:0 RESERVED  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 67 KSZ9897R 5.1.1.8 Global Port Interrupt Status Register Address: 0x0018 - 0x001B Size: 32 bits This register provides the top level interrupt status for the individual ports. These interrupts are enabled in the Global Port Interrupt Mask Register. Refer to the Port Interrupt Status Register for detailed port interrupt status. Bits 31:7 6 Description Type Default RESERVED RO - Port 7 Interrupt Status RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b RO 0b 0 = No interrupt 1 = Interrupt request 5 Port 6 Interrupt Status 0 = No interrupt 1 = Interrupt request 4 Port 5 Interrupt Status 0 = No interrupt 1 = Interrupt request 3 Port 4 Interrupt Status 0 = No interrupt 1 = Interrupt request 2 Port 3 Interrupt Status 0 = No interrupt 1 = Interrupt request 1 Port 2 Interrupt Status 0 = No interrupt 1 = Interrupt request 0 Port 1 Interrupt Status 0 = No interrupt 1 = Interrupt request DS00002330E-page 68  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.1.1.9 Global Port Interrupt Mask Register Address: 0x001C - 0x001F Size: 32 bits This register enables the interrupts in the Global Port Interrupt Status Register. Bits 31:7 6 Description Type Default RESERVED RO - Port 7 Interrupt Mask R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b 0 = Interrupt enabled 1 = Interrupt disabled 5 Port 6 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled 4 Port 5 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled 3 Port 4 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled 2 Port 3 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled 1 Port 2 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled 0 Port 1 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 69 KSZ9897R 5.1.2 5.1.2.1 GLOBAL I/O CONTROL REGISTERS (0x0100 - 0x01FF) Serial I/O Control Register Address: Bits 7:3 2 0x0100 Size: 8 bits Description Type Default RESERVED R/W 0100_0b MIIM Preamble Suppression R/W 0b R/W 1b R/W 0b Type Default This feature affects only the MIIM (MDIO / MDC) interface. When using SPI or I2C, this bit has no effect. 0 = Normal operation. The switch always expects the MIIM preamble. 1 = The switch will respond to MIIM commands even in the absence of a preamble. 1 Automatic SPI Data Out Edge Select When enabled, this feature automatically determines the edge of SCL that is used to clock out the SPI data on SDO. If SCL ≥ ~25MHz, SDO data is clocked by the rising edge of SCL. If SCL < ~25 MHz, SDO data is clocked by the falling edge of SCL. 0 = The automatic feature is disabled, and bit 0 determines the SCL clock edge used for SDO. 1 = The automatic feature is enabled, and bit 0 is ignored. 0 SPI Data Out Edge Select When bit 1 is zero, then this bit determines the clock edge used for SPI data out. When bit 1 is set to 1, this bit is ignored. 0 = SDO data is clocked by the falling edge of SCL 1 = SDO data is clocked by the rising edge of SCL 5.1.2.2 Output Clock Control Register Address: Bits 0x0103 Description Size: 8 bits 7:5 RESERVED RO 000b 4:2 RESERVED R/W 000b CLKO_25_125 Output Pin Enable R/W 1b R/W 0b 1 0 = Disabled 1 = Enabled 0 CLKO_25_125 Frequency 0 = 25 MHz 1 = 125 MHz DS00002330E-page 70  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.1.2.3 In-Band Management (IBA) Control Register Address: 0x0104 - 0x0107 Size: 32 bits This register controls the In-Band Access (IBA) feature. Bits Type Default R/W Note 5-1 R/W 0b R/W SC 0b Set this bit to initialize the IBA state machine. This bit is self-clearing. 28:24 RESERVED RO 0x00 23:22 Priority Queue for IBA response R/W 01b 31 Description IBA Enable The initial value is strapped in from the RX_DV7/CRS_DV7/RX_CTL7 pin. 0 = Disabled 1 = Enabled Note: If using I2C, do not enable IBA. 30 IBA Destination MAC Address Match Enable Set this bit to enable checking of the destination MAC address in received IBA frames against the switch MAC address in the Switch MAC Address 0 Register through Switch MAC Address 5 Register. Non-matching frames are discarded. When not enabled, the MAC address is not checked. 29 IBA Reset Specifies the transmit priority queue for the IBA response frame. Typically this value is not changed. 21:19 RESERVED RO 00_0b 18:16 Port used for IBA communication R/W 110 R/W 0x40FE 000 = Port 1 001 = Port 2 010 = Port 3 011 = Port 4 100 = Port 5 101 = Port 6 110 = Port 7 111 = Reserved 15:0 Note 5-1 TPID (EtherType) value for IBA frame header The default value of this field is determined by the associated configuration strap value. Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 71 KSZ9897R 5.1.2.4 I/O Drive Strength Register Address: Bits 7 6:4 0x010D Size: 8 bits Description Type Default RESERVED R/W 0b High Speed Drive Strength (24mA) R/W 110b RESERVED R/W 0b Low Speed Drive Strength (8mA) R/W 10b Type Default RO 0b RO 0b RO 0b RESERVED RO 0x0000 IBA MAC Address Mismatch Error RO 0b RO 0b RO 0b Controls drive strength of RGMII / MII / RMII (except TX_CLK / REFCLKI, COL and CRS) and CLKO_25_125. 3 2:0 Controls drive strength of TX_CLK / REFCLKI, COL, CRS, LEDs, PME_N, INTRP_N, SDO and SDI/SDA/MDIO. 5.1.2.5 In-Band Management (IBA) Operation Status 1 Register Address: Bits 31 0x0110 - 0x0113 Size: 32 bits Description Good IBA Packet Detect 1 = A good IBA packet is received. 30 IBA Response Packet Transmit Done 1 = An IBA response packet is sent out. This bit is cleared when a packet with a matching IBA tag field is received. 29 IBA Execution Done 1 = All the commands in one IBA packet are completely executed. This bit is cleared when a packet with a matching IBA tag field is received. 28:15 14 This bit is active only when IBA_ENABLE (In-Band Management (IBA) Control Register, bit 30) is set. 1 = An IBA packet is received with an unmatched MAC address, unequal to the switch’s MAC address. This bit is cleared when a packet with a matching IBA tag field is received. 13 IBA Access Format Error 1 = An IBA packet with a wrong access format (not equal to 0x9800) is received. This bit is cleared when a packet with a matching IBA tag field is received. 12 IBA Access Code Error 1 = An IBA packet with an unrecognized access code is received. (Valid access codes are 0x0001 and 0x0002.) This bit is cleared when a packet with a matching IBA tag field is received. DS00002330E-page 72  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R Bits 11 Description IBA Access Command Error Type Default RO 0b RO 0b 1 = An IBA packet with an unrecognized command code is received. This bit is cleared when a packet with a matching IBA tag field is received. 10 IBA Oversize Packet Error 1 = An oversized IBA packet is received. The maximum IBA packet size is 320 bytes, including 8-byte zeros before FCS and the 4-byte FCS. No response packet is sent. This bit is cleared when a packet with a matching IBA tag field is received. 9:7 RESERVED RO 000b 6:0 IBA Access Code Error Location RO 0x000 Type Default RO 0x00000 When IBA Access Command Error (bit 11) is set, these bits indicate the address location of the wrong command code within the IBA packet. 5.1.2.6 LED Override Register Address: Bits 31:10 9:0 5.1.2.7 32 bits RESERVED Override LED These bits select whether each LEDx_0 and LEDx_1 pin will function as an LED or General Purpose Output (GPO). The LSB bit of this field represents LED1_0, followed by LED1_1, LED2_0, etc.. When configured as a GPO, the GPO output is controlled via the LED Output Register. 0 = LEDx_y pin functions as an LED 1 = LEDx_y pin functions as a GPO 0000000000b LED Output Register Bits 9:0 Size: Description Address: 31:10 0x0120 - 0x0123 0x0124 - 0x0127 Size: 32 bits Description Type Default RESERVED RO 0x00000 GPO Output Control When configured as a GPO via the LED Override Register, the GPO output is controlled via this field. The LSB bit of this field represents LED1_0, followed by LED1_1, LED2_0, etc. 0 = LEDx_y pin outputs low 1 = LEDx_y pin outputs high R/W 0000000000b  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 73 KSZ9897R 5.1.3 5.1.3.1 GLOBAL PHY CONTROL AND STATUS REGISTERS (0x0200 - 0x02FF) Power Down Control 0 Register Address: Bits 7:6 5 0x0201 Size: 8 bits Description Type Default RESERVED RO 00b PLL Power Down R/W 0b R/W 00b RO 000b Type Default RESERVED RO 0x000000 Configuration strap values of LED pins RO Note 5-2 0 = Normal operation. 1 = Disable PLL. This may be used in combination with EDPD mode – see below. 4:3 Power Management Mode 00 = Normal operation 01 = Energy Detect Power Down (EDPD) Mode 10 = Soft Power Down Mode 11 = invalid 2:0 5.1.3.2 RESERVED LED Configuration Strap Register Address: Bits 31:10 9:0 0x0210 - 0x0213 Size: 32 bits Description [LED4_1, LED4_0, LED3_1, LED3_0, LED2_1, LED2_0, LED1_1, LED1_0] Note 5-2 5.1.4 5.1.4.1 The default value of this field is determined by the associated configuration strap values. Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information. GLOBAL SWITCH CONTROL REGISTERS (0x0300 - 0x03FF) Switch Operation Register Address: Bits 7 0x0300 Description Double Tag Enable Size: 8 bits Type Default R/W 0b RO 0x00 1 = Double tagging is enabled 0 = Double tagging is disabled 6:2 RESERVED DS00002330E-page 74  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R Bits 1 Description Soft Hardware Reset When set to 1, all register settings, except configuration strap options, are reset to default values. 0 Start Switch Type Default R/W SC 0b R/W Note 5-3 1 = Switch function is enabled Note 5-3 5.1.4.2 0 = Switch function is disabled; no traffic will be passed until this bit is set The default value of this field is determined by the LED5_1 configuration strap value. Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information. Switch MAC Address 0 Register Address: Bits 7:0 0x0302 Size: 8 bits Description MAC Address [47:40] Type Default R/W 0x00 Type Default R/W 0x10 Type Default R/W 0xA1 This register, along with the Switch MAC Address 1-5 Registers, define the switch’s MAC address to be used as the source address in MAC pause control frames, and for self-address filtering. 5.1.4.3 Switch MAC Address 1 Register Address: Bits 7:0 5.1.4.4 Size: 8 bits Description MAC Address [39:32] Switch MAC Address 2 Register Address: Bits 7:0 0x0303 0x0304 Description MAC Address [31:24]  2022 Microchip Technology Inc. and its subsidiaries Size: 8 bits DS00002330E-page 75 KSZ9897R 5.1.4.5 Switch MAC Address 3 Register Address: Bits 7:0 5.1.4.6 0x0306 Size: Default R/W 0xFF Type Default R/W 0xFF Type Default R/W 0xFF Type Default 8 bits Description MAC Address [15:8] Switch MAC Address 5 Register Bits 5.1.4.8 Type Switch MAC Address 4 Register Address: 7:0 8 bits MAC Address [23:16] Bits 5.1.4.7 Size: Description Address: 7:0 0x0305 0x0307 Size: 8 bits Description MAC Address [7:0] Switch Maximum Transmit Unit Register Address: Bits 0x0308 - 0x0309 Size: 16 bits Description 15:14 RESERVED R/W 00b 13:0 Maximum Frame Length (MTU) R/W 0x07D0 Specifies the maximum transmission unit (MTU), which is the maximum frame payload size. Frames which exceed this maximum are truncated. This value can be set as high as 9000 (= 0x2328) if jumbo frame support is required. Also refer to the Switch MAC Control 1 Register and Port MAC Control 0 Register. DS00002330E-page 76  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.1.4.9 Switch ISP TPID Register Address: Bits 15:0 0x030A - 0x030B Size: 16 bits Description ISP Tag TPID Type Default R/W 0x9100 Type Default R/W 0b R/W 1b R/W 10_0b R/W 0b R/W 01b Default tag TPID (EtherType) for untagged incoming frames or the ISP frame tag TPID for the double tagging function. 5.1.4.10 Switch Lookup Engine Control 0 Register Address: Bits 7 0x0310 Size: 8 bits Description 802.1Q VLAN Enable This is the master enable for VLAN forwarding and filtering. Note that the VLAN Table must be set up before VLAN mode is enabled. 1 = VLAN mode enabled 0 = VLAN mode disabled 6 Drop Invalid VID 1 = All received packets with invalid VLAN ID are dropped. 0 = Received packets with invalid VLAN ID are forwarded to the host port. Note that the Unknown VID Forwarding feature (Unknown VLAN ID Control Register), if enabled, takes precedence over this bit. 5:3 Age Count This bit, in combination with the Age Period value (Switch Lookup Engine Control 3 Register), determines the aging time of dynamic entries in the address lookup table. This value is used for the Age Count field whenever a dynamic table entry is updated. 2 Reserved Multicast Lookup Enable 1 = Enable Reserved Multicast Table 0 = Disable Reserved Multicast Table 1:0 HASH_OPTION Defines the hashing option for mapping entries to the dynamic lookup table. 00, 11 = Entry is mapped directly using the 10 least significant bits of the destination address. 01 = The CRC hashing function is used. 10 = The XOR hashing function is used. Refer to Section 4.4.2.1, "Address Lookup (ALU) Table," on page 28 for additional information.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 77 KSZ9897R 5.1.4.11 Switch Lookup Engine Control 1 Register Address: 0x0311 Bits 7 Size: 8 bits Description Unicast Learning Disable Type Default R/W 0b R/W 0b R/W SC 0b R/W SC 0b R/W 1b R/W 1b R/W 0b R/W 0b 1 = Unicast address learning is disabled 0 = Unicast address learning is enabled 6 Self-Address Filtering – Global Enable The source address of received packets is compared to the MAC address in registers Switch MAC Address 0 Register through Switch MAC Address 5 Register, and the packet is dropped if there is a match. Self-address filtering can be enabled on a port-by-port basis by setting the port enable bit in the Port Control 2 Register in addition to setting this bit. 1 = Enable self-address filtering globally for those ports whose port enable bit (Port Control 2 Register) is set. 0 = Do not filter self-addressed packets on any port. 5 Flush Address Lookup Table The Flush Option bit in the Switch Lookup Engine Control 2 Register determines whether flushing is performed on dynamic entries, static entries, or both. 1 = Trigger a flush of the entire address lookup table. The static address table is not flushed. 0 = Normal operation 4 Flush MSTP Address Entries (Address Lookup Table) The Flush Option bit in the Switch Lookup Engine Control 2 Register determines whether flushing is performed on dynamic entries, static entries, or both. 1 = Trigger a flush of the matched MSTP entries 0 = Normal operation 3 Multicast Source Address Filtering 1 = Forward packets with a multicast source address 0 = Drop packets with a multicast source address 2 Aging Enable 1 = Enable address table aging 0 = Disable address table aging 1 Fast Aging 1 = Enable fast aging 0 = Disable fast aging 0 Link Down Flush 1 = Link down will cause the entries of any link down port to be flushed 0 = Link down flush is disabled DS00002330E-page 78  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.1.4.12 Switch Lookup Engine Control 2 Register Address: Bits 0x0312 Size: 8 bits Description Type Default 7 RESERVED R/W 0b 6 Double Tag Multicast Trap R/W 0b R/W 0b R/W 0b R/W 00b R/W 00b 1 = When double tagging mode is enabled, forward all reserved multicast packets to the host port only. 0 = Normal forwarding 5 Dynamic Entry Egress VLAN Filtering Egress VLAN filtering uses the forwarding port map from the VLAN table to restrict the forwarding ports determined from the address lookup. This is the recommended mode of operation when VLAN is enabled. The default value is 0 only for backwards compatibility with previous switches. 1 = Enable. For successful lookup of a dynamic entry in the address table, the forwarding ports are determined from the AND function of the address table port map and the VLAN table port map. 0 = Disable. For successful lookup of a dynamic entry in the address table, the forwarding ports are determined from the address table only. 4 Static Entry Egress VLAN Filtering Egress VLAN filtering uses the forwarding port map from the VLAN table to restrict the forwarding ports determined from the address lookup. This is the recommended mode of operation when VLAN is enabled. The default value is 0 only for backwards compatibility with previous switches. 1 = Enable. For successful lookup of a static entry in the address table, the forwarding ports are determined from the AND function of the address table port map and the VLAN table port map. 0 = Disable. For successful lookup of a static entry in the address table, the forwarding ports are determined from the address table only. 3:2 Flush Option Determines which address lookup table entries may be flushed by either of the flush operations in the Switch Lookup Engine Control 1 Register. 00 = No flush or flush is done 01 = Flush only dynamic table entries 10 = Flush only static table entries 11 = Flush both static and dynamic table entries 1:0 MAC Address Priority 00 = MAC Address (MACA) priority for a packet is determined from the destination address (DA) lookup 01 = MACA priority for a packet is determined from the source address (SA) lookup 10 = MACA priority for a packet is determined from the higher of the DA and SA lookups 11 = MACA priority for a packet is determined from the lower of the DA and SA lookups  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 79 KSZ9897R 5.1.4.13 Switch Lookup Engine Control 3 Register Address: Bits 7:0 0x0313 Size: 8 bits Description Age Period Type Default R/W 0x4B This value, multiplied by the Age Count value in the entries of the Address Lookup Table, determines the aging time of dynamic entries in that table. The unit is seconds. 5.1.4.14 Address Lookup Table Interrupt Register Address: 0x0314 Size: 8 bits This register provides the detailed interrupt status for the Address Lookup Table. These interrupts are enabled in the Address Lookup Table Mask Register. The LUE interrupt status bit in the Global Interrupt Status Register is the OR of the status bits in this register. Bits 7:3 2 Description RESERVED Learn Fail Interrupt Status Type Default RO 0x00 R/WC 0b R/WC 0b R/WC 0b An Address Lookup Table entry was not learned because all entries in the bucket are static 1 Almost Full Interrupt Status Interrupt indicates that the Address Lookup Table bucket was almost full (2 or 3 valid entries) when a new static entry was written. 0 Write Fail Interrupt Status Interrupt indicates that the Address Lookup Table bucket is full and a write failed 5.1.4.15 Address Lookup Table Mask Register Address: 0x0315 Size: 8 bits This register masks the Address Lookup Table interrupts in the Address Lookup Table Interrupt Register. Bits 7:3 2 Description Type Default RESERVED RO 0x00 Learn Fail Interrupt Mask R/W 1b R/W 1b 1 = Interrupt is disabled 0 = Interrupt is enabled 1 Almost Full Interrupt Mask 1 = Interrupt is disabled 0 = Interrupt is enabled DS00002330E-page 80  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R Bits 0 Description Write Fail Interrupt Mask Type Default R/W 1b Type Default 1 = Interrupt is disabled 0 = Interrupt is enabled 5.1.4.16 Address Lookup Table Entry Index 0 Register Address: 0x0316 - 0x0317 Bits Size: 16 bits Description 15:12 RESERVED RO 0x0 11:0 / 9:0 Almost Full Entry Index [11:0] RO 0x000 Type Default RESERVED RO 0000_00 Fail Learn Index RO 0x000 Type Default RESERVED RO 0000_00 CPU Access Index RO 0x000 When a static entry is successfully written into the Address Lookup Table, but the table bucket is almost full (contains 2 or 3 static entries prior to the write), the entry address is reported here. Fail Write Index [9:0] When a static entry write failure occurs in the Address Lookup Table, the bucket address is reported here. 5.1.4.17 Address Lookup Table Entry Index 1 Register Address: Bits 15:10 9:0 0x0318 - 0x0319 Size: 16 bits Description When a destination address fails to be learned in the Address Lookup Table because the bucket contains 4 static entries, the bucket address is reported here. 5.1.4.18 Address Lookup Table Entry Index 2 Register Address: Bits 15:10 9:0 0x031A - 0x031B Size: 16 bits Description Whenever there is an external read or write to the Address Lookup Table, the bucket address of the access is reported here.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 81 KSZ9897R 5.1.4.19 Unknown Unicast Control Register Address: 0x0320 - 0x0323 Size: 32 bits The following three registers control forwarding of packets with 1) unknown unicast destination address, 2) unknown multicast destination address, and 3) unknown VLAN ID. If a received packet falls into more than one of these categories, the precedence is: 1. 2. 3. Unknown VID Unknown Unicast Unknown Multicast Bits 31 Description Unknown Unicast Packet Forward Type Default R/W 0b 1 = Enable forwarding of unknown unicast packets to the ports specified below 0 = Disable unknown unicast packet forwarding 30:7 RESERVED RO 0x000000 6:0 Unknown Unicast Forwarding Ports R/W 000_0000b Type Default R/W 0b Bit 0 is for port 1 Bit 1 is for port 2, etc. 1 = Forward unknown unicast packets to that port 0 = Do not forward to that port All ones = Forwarded to all ports All zeros = Forwarded to no ports 5.1.4.20 Unknown Multicast Control Register Address: 0x0324 - 0x0327 Bits 31 Size: 32 bits Description Unknown Multicast Packet Forward 1 = Enable forwarding of unknown multicast packets to the ports specified below 0 = Disable unknown multicast packet forwarding 30:7 RESERVED RO 0x000000 6:0 Unknown Multicast Forwarding Ports R/W 000_0000b Bit 0 is for port 1 Bit 1 is for port 2, etc. 1 = Forward unknown multicast packets to that port 0 = Do not forward to that port All ones = Forwarded to all ports All zeros = Forwarded to no ports DS00002330E-page 82  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.1.4.21 Unknown VLAN ID Control Register Address: 0x0328 - 0x032B Bits 31 Size: 32 bits Description Unknown VID Packet Forward Type Default R/W 0b 1 = Enable forwarding of unknown VLAN ID (VID) packets to the ports specified below 0 = Disable unknown VID packet forwarding 30:7 RESERVED RO 0x000000 6:0 Unknown VID Forwarding Ports R/W 000_0000b Type Default R/W 0b RESERVED R/W 000b Frame Length Field Check R/W 0b R/W 1b Bit 0 is for port 1 Bit 1 is for port 2, etc. 1 = Forward unknown VID packets to that port 0 = Do not forward to that port All ones = Forwarded to all ports All zeros = Forwarded to no ports 5.1.4.22 Switch MAC Control 0 Register Address: Bits 7 0x0330 Size: 8 bits Description Alternate Back-off Mode The back-off mode applies to half-duplex only. This bit should be set if the No Excessive Collision Drop bit in the Switch MAC Control 1 Register is enabled. 1 = Enable alternate back-off mode 0 = Disable 6:4 3 This applies only when the EtherType/Length field is 0 = Entry has been accessed or learned since last aging process. A default value is reloaded every time the entry is learned or accessed. It is decremented during aging process. 0 = Entry has not been accessed or learned since last aging process. Entry is not valid if it’s not static. 25:3 RESERVED RO 0x000000 2:0 MSTP R/W 000b Type Default R/W 0b Multiple Spanning Tree Protocol group ID for matching 5.3.1.5 ALU Table Entry 2 Register Address: Bits 31 0x0424 - 0x0427 Description OVERRIDE Size: 32 bits 1 = Enable overriding of port state 0 = Do not enable 30:7 RESERVED RO 0x000000 6:0 PORT FORWARD R/W 0x00 Each bit corresponds to a device port. Bit 0 is for port 1 Bit 1 is for port 2, etc. 1 = Forward to the corresponding port 0 = Do not forward to the corresponding port DS00002330E-page 156  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.3.1.6 ALU Table Entry 3 Register Address: 0x0428 - 0x042B Bits Size: 32 bits Description Type Default 31:23 RESERVED RO 0x000 22:16 FID R/W 000_0000 R/W 0x0000 Type Default R/W 0x00000000 VLAN group ID for matching 15:0 5.3.1.7 MAC Address [47:32] ALU Table Entry 4 Register Address: Bits 31:0 5.3.2 0x042C - 0x042F Size: 32 bits Description MAC Address [31:0] STATIC ADDRESS TABLE The Static Address Table is one of three tables used for MAC address lookup. It can hold up to 16 static address entries, thereby minimizing the number of static entries that may need to be programmed into the Address Lookup Table, which is used primarily for dynamic entries. In response to a destination address (DA) lookup, all tables are searched to make a packet forwarding decision. Entries in this table are programmed by the host processor, and are never aged. A static DA lookup result (in either this table or the Address Lookup Table) takes precedence over the dynamic DA lookup result. The Static Address Table has 16 entries and is accessed indirectly. The Static Address and Reserved Multicast Table Control Register is used for indexing and read/write control. The following registers are used for the data fields: • • • • Static Address Table Entry 1 Register Static Address Table Entry 2 Register Static Address Table Entry 3 Register Static Address Table Entry 4 Register 5.3.2.1 1. 2. 3. Write the content of the table entry to the Static Address Table Entry 1 Register, Static Address Table Entry 2 Register, Static Address Table Entry 3 Register, and Static Address Table Entry 4 Register. Write to the Static Address and Reserved Multicast Table Control Register. a) Write the TABLE_INDEX field with the 4-bit index value. b) Set the TABLE_SELECT bit to 0 to select the Static Address Table. c) Set the ACTION bit to 0 to indicate a write operation. d) Set the START_FINISH bit to 1 to initiate the operation. When the operation is complete, the START_FINISH bit will be cleared automatically. 5.3.2.2 1. Static Address Table Write Operation Static Address Table Read Operation Write to the Static Address and Reserved Multicast Table Control Register. a) Write the TABLE_INDEX field with the 4-bit index value. b) Set the TABLE_SELECT bit to 0 to select the Static Address Table.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 157 KSZ9897R 2. c) Set the ACTION bit to 1 to indicate a read operation. d) Set the START_FINISH bit to 1 to initiate the operation. When the operation is complete, the START_FINISH bit will be cleared automatically. a) Read the contents of the indexed entry from the Static Address Table Entry 1 Register, Static Address Table Entry 2 Register, Static Address Table Entry 3 Register, and Static Address Table Entry 4 Register. 5.3.2.3 Static Address Table Entry 1 Register Address: Bits 31 0x0420 - 0x0423 Size: 32 bits Description VALID Type Default R/W 0b R/W 0b R/W 0b 1 = Entry is valid 0 = Entry is not valid 30 SRC FILTER 1 = Drop packet if source address match during source learning 0 = Don’t drop if source address match 29 DES FILTER 1 = Drop packet if destination address match during lookup 0 = Don’t drop if destination address match 28:26 PRIORITY R/W 0_00b 25:3 RESERVED RO 0x000000 2:0 MSTP R/W 000b Type Default R/W 0b R/W 0b Multiple Spanning Tree Protocol group ID for matching 5.3.2.4 Static Address Table Entry 2 Register Address: Bits 31 0x0424 - 0x0427 Description OVERRIDE Size: 32 bits 1 = Enable overriding of port state 0 = Do not enable 30 USE FID Use FID on multicast packets for matching 29:7 RESERVED RO 0x000000 6:0 PORT FORWARD R/W 0x00 Each bit corresponds to a device port. Bit 0 is for port 1 Bit 1 is for port 2, etc. 1 = Forward to the corresponding port 0 = Do not forward to the corresponding port DS00002330E-page 158  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.3.2.5 Static Address Table Entry 3 Register Address: Bits 0x0428 - 0x042B Size: 32 bits Description Type Default 31:23 RESERVED RO 0x000 22:16 FID R/W 000_0000b R/W 0x0000 Type Default R/W 0x00000000 VLAN group ID for matching 15:0 5.3.2.6 MAC Address [47:32] Static Address Table Entry 4 Register Address: Bits 31:0 5.3.3 0x042C - 0x042F Description MAC Address [31:0] Size: 32 bits RESERVED MULTICAST ADDRESS TABLE The Reserved Multicast Address Table determines the forwarding ports for 48 specific multicast addresses. The table is addressed by the least significant 6 bits of the multicast address, and the table contents are the bits (the PORT_FORWARD field) that represent each possible forwarding port of the device. It is not addressed by the group number in the first column of Table 4-6. Note that the 48 addresses are organized into 8 fixed groups, and changing a forwarding port for one address also makes the same change for all other addresses in the same group. The Reserved Multicast Table is accessed in the same manner as the Static Address Table, using the same indirect access registers. The Static Address and Reserved Multicast Table Control Register is used for indexing and read/write control, while the Reserved Multicast Address Table Entry 2 Register is used for the data fields. 5.3.3.1 1. 2. 3. Write the PORT_FORWARD value to the Reserved Multicast Address Table Entry 2 Register. Write to the Static Address and Reserved Multicast Table Control Register. a) Write the TABLE_INDEX field with the 6-bit index value. b) Set the TABLE_SELECT bit to 1 to select the Reserved Multicast Table. c) Set the ACTION bit to 0 to indicate a write operation. d) Set the START_FINISH bit to 1 to initiate the operation. When the operation is complete, the START_FINISH bit will be cleared automatically. 5.3.3.2 1. 2. Reserved Multicast Table Write Operation Reserved Multicast Table Read Operation Write to the Static Address and Reserved Multicast Table Control Register. a) Write the TABLE_INDEX field with the 6-bit index value. b) Set the TABLE_SELECT bit to 1 to select the Reserved Multicast Table. c) Set the ACTION bit to 1 to indicate a read operation. d) Set the START_FINISH bit to 1 to initiate the operation. When the operation is complete, the START_FINISH bit will be cleared automatically. a) Read the contents of the indexed entry from the Reserved Multicast Address Table Entry 2 Register.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 159 KSZ9897R 5.3.3.3 Reserved Multicast Address Table Entry 2 Register Address: 0x0424 - 0x0427 Bits Size: 32 bits Description Type Default R/W 00b 31:30 RESERVED 29:7 RESERVED RO 0x000000 6:0 PORT FORWARD R/W 0x00 Each bit corresponds to a device port. Bit 0 is for port 1 Bit 1 is for port 2, etc. 1 = Forward to the corresponding port 0 = Do not forward to the corresponding port 5.3.4 VLAN TABLE An internal VLAN Table is used for VLAN lookup. If 802.1Q VLAN mode is enabled (Switch Lookup Engine Control 0 Register), this table will be used to retrieve the VLAN information that is associated with the ingress packet. The table holds 4096 entries - one for each possible VLAN. The table must be set up before 802.1Q VLAN is enabled. The VLAN table is accessed one entry at a time using the following indirect registers: • • • • • VLAN Table Entry 0 Register VLAN Table Entry 1 Register VLAN Table Entry 2 Register VLAN Table Index Register VLAN Table Access Control Register The table data fields are described in Figure 5-4 and Table 5-4. FIGURE 5-4: VLAN TABLE STRUCTURE Entry # 0 Entry # 1 Entry # 2 Entry # 3 Entry # 4 V FO PRIORITY MSTP FID UNTAG FORWARD PORT FORWARD PORT UNTAG FILTER ID MSTP INDEX Entry # 4094 Entry # 4095 DS00002330E-page 160 PRIORITY FORWARD OPTION VALID  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 5-4: VLAN TABLE DATA FIELDS Field Size (bits) Description VALID 1 When 1, indicates that the table entry is valid. FORWARD OPTION 1 When 1, forward to VLAN port table (PORT FORWARD field). When 0, see Table 4-8, "VLAN Forwarding" for details. PRIORITY 3 Priority value for this VID. MSTP INDEX 3 Multiple Spanning Tree Protocol index. FID 7 Filter ID value. It is combined with destination address and hashed to index the Address Lookup Table. PORT UNTAG PORT FORWARD 7 (1 per port) When 1, untag at that egress port. 7 (1 per port) VLAN port membership list. There is one bit per port, starting with the LSB which corresponds to port 1. When 0, don’t untag. A bit value of 1 indicates the associated port is included in the port membership list for that VID. When 0, that port is excluded. 5.3.4.1 1. 2. 3. Write to the VLAN Table Entry 0 Register, VLAN Table Entry 1 Register, and VLAN Table Entry 2 Register to set up the data fields as described in Figure 5-4 and Table 5-4. Write the VLAN Index value in the VLAN Table Index Register. This is the 12-bit index (address) to select the table entry. It is equivalent to the VID which indexes the table during lookup. Write the VLAN Table Access Control Register to specify a write operation, and set START (bit 7). When the operation is complete, bit 7 will be cleared automatically. 5.3.4.2 1. 2. 3. VLAN Table Write Operation VLAN Table Read Operation Write the VLAN Index value in the VLAN Table Index Register to select one of the 4k table entries. Write the VLAN Table Access Control Register to specify a read operation and set START (bit 7). When the operation is complete, bit 7 will be cleared automatically. Read the VLAN Table Entry 0 Register, VLAN Table Entry 1 Register, and VLAN Table Entry 2 Register to retrieve the read results from the VLAN table. 5.3.5 ACCESS CONTROL LIST (ACL) TABLE ACL filtering is implemented individually per-port. The ACL tables are accessed using the Port N: Port Switch ACL Control Registers (0xN600 - 0xN6FF). The 16 entries in each ACL table are addressed indirectly by an index register. Table 5-5 shows how the various fields of the ACL Table entries are mapped to data registers. The Port ACL Byte Enable MSB Register and Port ACL Byte Enable LSB Register make it possible to write or read any combination of bytes. This is useful for writing the Matching rule, Action rule and Process field separately. There are 16 bits in these byte enable registers, corresponding to the 16 data registers Port ACL Access 0 Register through Port ACL Access F Register. Note that the enable bits are applied in reverse order: Bit 0 for the Port ACL Access F Register Bit 1 for the Port ACL Access E Register … Bit 14 for the Port ACL Access 1 Register Bit 15 for the Port ACL Access 0 Register Also note that the Port ACL Access C Register is not used, so byte enable bit 3 is a don't care.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 161 KSZ9897R TABLE 5-5: ACL FIELD REGISTER MAPPING MD = 01 ENB = 00 Count Mode MD = 01 ENB ≠ 00 Register Bits 0xN600 7:4 RESERVED 3:0 Process Field: FRN [3:0] 7:6 RESERVED 5:4 MD [1:0] 3:2 ENB [1:0] 1 S/D 0 EQ 0xN601 0xN602 7:0 0xN603 7:0 0xN604 7:0 0xN605 7:0 0xN606 7:3 0xN607 MAC ADDRESS [47:0] MD = 10 IP Address [31:0] IP MASK [31:0] PC [1:0] 0 PRO [7:0] 7:1 7:0 0xN609 7:0 0xN60A 7:6 FME TYPE [15:0] FMSK [7:0] FLAG [7:0] COUNT [10:3] 5:3 Action Rule: PM [1:0] Action Rule: P [2:0] 2 Action Rule: RPE 1:0 Action Rule: RP [2:1] 7 COUNT [2:0] 6:5 Action Field: RP [0] Action Field: MM [1:0] 4:0 RESERVED 0xN60C 7:0 RESERVED 0xN60D 7 6 RESERVED TU 5 CA 4:0 RESERVED Action Field: FORWARD [6:0] 0xN60E 7:0 Process Field: RuleSet [15:8] 0xN60F 7:0 Process Field: RuleSet [7:0] 1. 2. 3. RESERVED 2:1 0xN608 5.3.5.1 MAX PORT [15:0] MIN PORT [15:0] 0 0xN60B MD = 11 ACL Table Read Write to the Port ACL Access Control 0 Register with the table entry number (0 to 15) in the ACL Index field, and the Write/Read bit 4 cleared to zero. This one write to this register initiates the read operation. Poll the Read Status bit in the Port ACL Access Control 0 Register to determine when the read operation is complete. When the operation is complete, data may be retrieved from the Port ACL Access 0 Register through Port ACL Access F Register. DS00002330E-page 162  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 5.3.5.2 1. 2. 3. 4. ACL Table Write Write the ACL table entry values to the Port ACL Access 0 Register through Port ACL Access F Register. Write the Port ACL Byte Enable MSB Register and Port ACL Byte Enable LSB Register to select which registers (Port ACL Access 0 Register through Port ACL Access F Register) are to be written into the ACL table. Write to the Port ACL Access Control 0 Register with the table entry number in the ACL Index field, and the Write/ Read bit 4 set to one. This one write to this register initiates the write operation. The Write Status bit in the Port ACL Access Control 0 Register may be polled to determine when the operation is complete. 5.3.6 MANAGEMENT INFORMATION BASE (MIB) COUNTERS There are 36 MIB counters per port. These counters accumulate a variety of statistics on ingress and egress traffic and events for network management. They are accessed indirectly using the Port MIB Control and Status Register and Port MIB Data Register. The Switch MIB Control Register provides global flush and freeze control of the MIB counters. TABLE 5-6: MIB Index 0x00 0x01 MIB COUNTERS MIB Counter Size (bits) Description RxHiPriorityByte 30 RX high priority octet count, including bad packets. RxUndersizePkt 30 RX undersize packets with good CRC. RX fragment packets with bad CRC, symbol errors or alignment errors. 0x02 RxFragments 30 0x03 RxOversize 30 RX oversize packets w/ good CRC (max: 1536 or 1522 bytes). 0x04 RxJabbers 30 RX packets longer than 1522 bytes with either CRC errors, alignment errors or symbol errors (depends on max packet size setting); or RX packets longer than 1916 bytes only. 0x05 RxSymbolError 30 RX packets with invalid data symbol; and legal preamble and packet size. 0x06 RxCRCerror 30 RX packets between 64 and 1522 bytes in size, with an integral number of bytes and a bad CRC. (Upper limit depends on max packet size setting.) 0x07 RxAlighmentError 30 RX packets between 64 and 1522 bytes in size, with a non-integral number of bytes and a bad CRC. (Upper limit depends on max packet size setting.) 0x08 RxControl8808Pkts 30 MAC control frames received with 0x8808 in the EtherType field. 0x09 RxPausePkts 30 PAUSE frames received. PAUSE is defined as EtherType (0x8808), DA, control opcode (0x0001), minimum 64 byte data length, and a valid CRC. 0x0A RxBroadcast 30 RX good broadcast packets. Does not include erred broadcast packets or valid multicast packets. 0x0B RXMulticast 30 RX good multicast packets. Does not include MAC control frames, erred multicast packets, or valid broadcast packets. 0x0C RxUnicast 30 RX good unicast packets. 0x0D Rx64Octets 30 RX packets (bad packets included) that are 64 bytes in length. 0x0E Rx65to127Octets 30 RX packets (bad packets included) that are 65 to 127 bytes in length. 0x0F Rx128to255Octets 30 RX packets (bad packets included) that are 128 to 255 bytes in length. Rx256to511Octets 30 RX packets (bad packets included) that are 256 to 511 bytes in length. 0x11 Rx512to2023Octets 30 RX packets (bad packets included) that are 512 to 1023 bytes in length. 0x12 Rx1024to1522Octets 30 RX packets (bad packets included) that are 1024 to 1522 bytes in length. 0x13 Rx1523to2000Octets 30 RX packets (bad packets included) that are 1523 t0 2000 bytes in length. Rx2001+Octets 30 RX packets (bad packets included) that are between 2001 bytes and the upper limit in length. 0x10 0x14  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 163 KSZ9897R TABLE 5-6: MIB Index MIB COUNTERS (CONTINUED) MIB Counter Size (bits) Description 0x15 TxHiPriorityByte 30 TX high priority good octet count, including PAUSE packets. 0x16 TxLateCollision 30 Collision is detected later than 512 bit times into the transmission of a packet. 0x17 TxPausePkts 30 PAUSE frames transmitted. PAUSE is EtherType (0x8808), DA, control opcode (0x0001), minimum 64 byte data length, and a valid CRC. 0x18 TxBroadcastPkts 30 TX good broadcast packets. Does not include erred broadcast packets or valid multicast packets. 0x19 TxMulticastPkts 30 TX good multicast packets. Does not include MAC control frames, erred multicast packets, or valid broadcast packets. 0x1A TxUnicastPkts 30 TX good unicast packets. 0x1B TxDeferred 30 TX packets where the first transmit attempt is delayed due to the busy medium. 0x1C TxTotalCollision 30 TX total collisions. Half duplex only. 0x1D TxExcessiveCollision 30 TX fails due to excessive collisions. 0x1E TxSingleCollision 30 Successfully transmitted frames where transmission is inhibited by exactly one collision. 0x1F TxMultipleCollision 30 Successfully transmitted frames where transmission is inhibited by more than one collision. 0x80 RxByteCnt 36 RX byte count. TxByteCnt 36 TX byte count. 0x82 RxDropPackets 30 RX packets dropped due to lack of resources. 0x83 TXDropPackets 30 TX packets dropped due to lack of resources. 0x81 5.3.6.1 MIB Counter Read Operation Indirect access registers are used to read the MIB counters. Separate access registers are provided for each port via the Port MIB Control and Status Register and Port MIB Data Register. All MIB Counters are read-clear. The steps for reading a counter are as follows: 1. 2. 3. 4. Write the MIB Index to bits [23:16] of the Port MIB Control and Status Register. Set the MIB Read Enable in bit 25 of the Port MIB Control and Status Register. This step and the previous step may be done together. Read the MIB Read Enable / Count Valid in bit 25 of the Port MIB Control and Status Register. A '0' value indicates that the read is complete and the count is valid. Read the count value from the Port MIB Data Register. For 36-bit counters, counter bits [35:32] are read from the Port MIB Control and Status Register. The Counter Overflow bit is also found in the Port MIB Control and Status Register. 5.3.6.2 MIB Counter Freeze and Flush Functions Counter freeze and flush functions are available on a port-by-port basis. Freezing or flushing counters is initiated by setting the appropriate bit in the Switch MIB Control Register. The freeze or flush function will be applied to all ports for which the flush and freeze functions have been enabled. To enable flush and freeze for a port, set bit 24 in the Port MIB Control and Status Register. The following steps show an example of how flush and freeze are used to collect MIB statistics for all ports for a period of 1 second: 1. 2. Set the MIB Flush and Freeze Enable bit 24 in the Port MIB Control and Status Register for all ports N. Write 0x40 to the Switch MIB Control Register to freeze the MIB counters for all enabled ports. DS00002330E-page 164  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 3. Write 0xC0 to the Switch MIB Control Register to clear the MIB counters for all enabled ports (while continuing to also freeze the counters). At the beginning of the 1 second period, write 0x00 to the Switch MIB Control Register to enable the counters. At the end of the 1 second period, write 0x40 to the Switch MIB Control Register to freeze the counters. Read each counter for each port. 4. 5. 6. 5.4 MDIO Manageable Device (MMD) Registers (Indirect) MMD registers provide indirect read/write access to up to 32 MMD device addresses with each device supporting up to 65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. However, the KSZ9897R uses only a small fraction of the available registers. Refer to Table 5-7, "MMD Register Map" for a list of accessible MMD device addresses and their associated register addresses. Detailed descriptions of the supported MMD registers are provided in the following subsections. The following two standard port registers serve as the portal registers to access the indirect MMD registers. • PHY MMD Setup Register • PHY MMD Data Register TABLE 5-7: MMD REGISTER MAP Device Address (hex) Register Address (hex) 2h 00h MMD LED Mode Register 7h 3Ch MMD EEE Advertisement Register Description Example: MMD Register Write Write MMD - Device Address 2h, Register 00h = 0010h to enable single-LED mode. 1. 2. 3. 4. Write the PHY MMD Setup Register with 0002h // Set up register address for MMD – Device Address 2h. Write the PHY MMD Data Register with 0000h // Select Register 00h of MMD – Device Address 2h. Write the PHY MMD Setup Register with 4002h // Select register data for MMD – Device Address 2h, Reg. 00h. Write the PHY MMD Data Register with 0010h // Write value 0010h to MMD – Device Address 2h, Reg. 00h. Example: MMD Register Read Read MMD - Device Address 7h, Register 3Ch for the LED mode status. Optional auto-increment is used. 1. 2. 3. 4. Write the PHY MMD Setup Register with 0007h // Set up register address for MMD – Device Address 7h. Write the PHY MMD Data Register with 003Ch // Select Register 3Ch of MMD – Device Address 7h. Write the PHY MMD Setup Register with 8007h // Select register data for MMD – Device Address 7h, Reg. 3Ch. Read the PHY MMD Data Register // Read data in MMD – Device Address 7h, Reg. 3Ch.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 165 KSZ9897R 5.4.1 MMD LED MODE REGISTER MMD Address: Register: Bits 15:5 4 0x02 0x00 Size: 16 bits Description Type Default RESERVED RO 0x000 LED Mode R/W 0b RO 0001b Type Default 1 = Single-LED Mode 0 = Tri-color Dual-LED Mode 3:0 5.4.2 RESERVED MMD EEE ADVERTISEMENT REGISTER MMD Address: Register: Bits 15:3 0x07 0x3C Description Size: 16 bits RESERVED RO 0x000 2 1000BASE-T EEE Enable 1 = 1000 Mbps EEE capable 0 = No 1000 Mbps EEE capability R/W 1b 1 100BASE-T EEE Enable 1 = 100 Mbps EEE capable 0 = No 100 Mbps EEE capability R/W 1b 0 RESERVED RO 0b DS00002330E-page 166  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.0 OPERATIONAL CHARACTERISTICS 6.1 Absolute Maximum Ratings* Supply Voltage (AVDDL, DVDDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.8 V Supply Voltage (AVDDH, VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +5.0 V Input Voltage (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +5.0 V Output Voltage (all outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +5.0 V Lead Temperature (soldering, 20 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260oC Storage Temperature (TS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +/-6 kV *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 6.2, "Operating Conditions**", Section 6.3, "Electrical Characteristics", or any other applicable section of this specification is not implied. 6.2 Operating Conditions** Supply Voltage (AVDDL, DVDDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14V to +1.26 V Supply Voltage (AVDDH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.375 V to +2.625 V Supply Voltage (VDDIO @ 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.135 V to +3.465 V Supply Voltage (VDDIO @ 2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.375 V to +2.625 V Supply Voltage (VDDIO @ 1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.71 V to +1.89 V Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 6-1 Junction to Ambient Resistance (JA) (Note 6-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 6-3 Junction to Case Characterization (JT) (Note 6-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04oC/W Junction to Case Resistance (JC) (Note 6-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 6-4 Note 6-1 0oC to +70oC for commercial version, -40oC to +85oC for industrial version. Note 6-2 JT and JA are under a 0 m/s air velocity. A 6-layer PCB is required for industrial applications. Note 6-3 11.3oC/W on a 6-layer PCB per JESD51, 14.4oC/W on a 4-layer PCB per JESD51. Note 6-4 1.5oC/W on a 6-layer PCB per JESD51, 1.21oC/W on a 4-layer PCB per JESD51. **Proper operation of the device is guaranteed only within the ranges specified in this section.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 167 KSZ9897R 6.3 Electrical Characteristics TA = 25oC. TABLE 6-1: ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Units Supply Current - Full 1000 Mbps Operation IDD_AH AVDDH supply current IDD_IO VDDIO supply current IDD_CA AVDDL supply current IDD_CD DVDDL supply current VDDIO @ 3.3V Ports 1-5 in 1000BASE-T Ports 6 & 7 in RGMII (1000 Mbps) All ports 100% utilization 330 mA 80 mA 460 mA 750 mA 150 mA 80 mA 140 mA 350 mA 140 mA 35 mA 140 mA 350 mA 100 mA 30 mA 30 mA 150 mA Supply Current - Mixed 1000/100 Mbps Operation IDD_AH AVDDH supply current IDD_IO VDDIO supply current IDD_CA AVDDL supply current IDD_CD DVDDL supply current VDDIO @ 3.3V Ports 1-5 in 100BASE-TX Ports 6 & 7 in RGMII (1000 Mbps) All ports 100% utilization Supply Current - Full 100 Mbps Operation IDD_AH AVDDH supply current IDD_IO VDDIO supply current IDD_CA AVDDL supply current IDD_CD DVDDL supply current VDDIO @ 3.3V Ports 1-5 in 100BASE-TX Ports 6 & 7 in MII (100 Mbps) All ports 100% utilization Supply Current - Full 10 Mbps Operation IDD_AH IDD_IO IDD_CA IDD_CD AVDDH supply current VDDIO @ 3.3V VDDIO supply current (3.3V) Ports 1-5 in 10BASE-Te Ports 6 & 7 in MII (10 Mbps) AVDDL supply current All ports 100% utilization DVDDL supply current Supply Current - Power Management - Energy Detect Mode IDD_AH AVDDH supply current 20 mA IDD_IO VDDIO supply current (3.3V) 30 mA IDD_CA AVDDL supply current 30 mA IDD_CD DVDDL supply current 150 mA Supply Current - Power Management - Global Soft Power Down Mode IDD_AH AVDDH supply current 2 mA IDD_IO VDDIO supply current (3.3V) 6 mA IDD_CA AVDDL supply current 0.01 mA IDD_CD DVDDL supply current 5 mA DS00002330E-page 168  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE 6-1: Symbol ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter Conditions Min Typ Max Units I Type CMOS Input Buffers (VDDIO = 3.3/2.5/1.8V) VIH Input High Voltage VIL Input Low Voltage IIN Input Current 2.1/1.7/1.3 VIN = GND ~ VDDIO V -10 0.9/0.9/0.6 V 10 µA O8 Type CMOS Output Buffers (VDDIO = 3.3/2.5/1.8V) VOH Output High Voltage IOH = 8/8/6 mA VOL Output Low Voltage IOL = 8/8/6 mA IOZ Output Tri-State Leakage 2.4/1.9/1.5 V VIN = GND ~ VDDIO 0.4/0.4/0.2 V 10 µA O24 Type CMOS Output Buffers (VDDIO = 3.3/2.5/1.8V) VOH Output High Voltage IOH = 24/24/20 mA VOL Output Low Voltage IOL = 24/24/20 mA IOZ Output Tri-State Leakage 2.4/1.9/1.5 V VIN = GND ~ VDDIO 0.4/0.4/0.2 V 10 µA I/O Pin Internal Pull-Up and Pull-Down Effective Resistance R1.8PU I/O Pin Effective Pull-Up Resistance R1.8PD I/O Pin Effective Pull-Down Resistance R2.5PU I/O Pin Effective Pull-Up Resistance R2.5PD I/O Pin Effective Pull-Down Resistance R3.3PU I/O Pin Effective Pull-Up Resistance R3.3PD I/O Pin Effective Pull-Down Resistance VDDIO = 1.8V VDDIO = 2.5V VDDIO = 3.3V 125 kΩ 97 kΩ 58 kΩ 51 kΩ 38 kΩ 39 kΩ 100BASE-TX Transmit (Measured Differentially After 1:1 Transformer) VO Peak Differential Output 100Ω termination on the differential output Vimb Output Voltage Imbalance 100Ω termination on the differential output tr , tf Rise/Fall Time Rise/Fall Time Imbalance ±0.95 ±1.05 V 2 % 3 5 ns 0 0.5 ns ±0.25 ns 5 % Duty cycle Distortion Overshoot VSET Reference Voltage of ISET (using 6.04kΩ - 1% resistor) Output Jitter 1.21 Peak-to-Peak  2022 Microchip Technology Inc. and its subsidiaries 0.7 V 1.4 ns DS00002330E-page 169 KSZ9897R TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Symbol Parameter Conditions Min Typ Max Units 10BASE-Te Receive Vsq Squelch Threshold 5MHz Square Wave 400 mV 10BASE-Te Transmit (Measured Differentially After 1:1 Transformer) Vp tr , tf Peak Differential Output Voltage 100Ω termination on the differential output Jitter Added 100Ω termination on the differential output (peak-to-peak) Rise/Fall Time DS00002330E-page 170 1.54 1.75 25 1.96 V 3.5 ns ns  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.4 Timing Specifications This section details the various timing specifications of the device. Note: 6.4.1 The I2C interface timing adheres to the NXP I2C-Bus Specification (UM10204, Rev. 6) (high-speed mode and slower). Refer to the I2C-Bus Specification for additional information. RGMII TIMING Figure 6-1 illustrates the RGMII timing requirements. FIGURE 6-1: RGMII TIMING TCYC TX_CLK TSETUP THOLD TSETUP THOLD TX_CTL TXD[3:0] TCYC RX_CLK TSKEW RX_CTL RXD[3:0] TABLE 6-2: RGMII TIMING VALUES Symbol TSETUP Description Min Typ Max Units Port 6 Data to clock input setup (Note 6-5) 2.2 ns Port 7 Data to clock input setup (Note 6-5) 1.3 ns Port 6 Data to clock input hold (Note 6-5) 0 ns Port 7 Data to clock input hold (Note 6-5) 0.7 ns Data to clock output skew (Note 6-6) 1.1 2.0 Clock cycle duration (Note 6-7) 7.2 8 8.8 ns Duty_G 1000Mbps duty cycle 45 50 55 % Duty_T 10/100Mbps duty cycle 40 50 60 % Note 6-8 ns THOLD TSKEW TCYC T r / Tf Rise / Fall time (20-80%) ns Note 6-5 For cases where there is no (or insufficient) skew between the input data and input clock, it is possible to add internal delay to the TX_CLK pinout by setting the RGMII Ingress Internal Delay bit in the XMII Port Control 1 Register register. This feature reduces the setup time requirement and increases the hold time requirement nominally by 1.3ns. Note 6-6 The RGMII interface adheres to the RGMII Specification Version 2.0, which specified that the driving device delay the output clock relative to the output data. This is the TSKEW parameter. This skew can be disabled by clearing the RGMII Egress Internal Delay bit in the XMII Port Control 1 Register register. Generally this is not recommended.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 171 KSZ9897R Note 6-7 For 10Mbps and 100Mbps, TCYC will scale to 400ns +/- 40ns and 40ns +/- 4 ns, respectively. 0.75ns for VDDIO = 3.3V/2.5V, 1.0ns for VDDIO = 1.8V Note 6-8 6.4.2 MII TIMING 6.4.2.1 MII Transmit Timing in MAC Mode Figure 6-2 illustrates a write operation from the KSZ9897R to a PHY or other device while operating the KSZ9897R in MAC Mode. FIGURE 6-2: MII TRANSMIT TIMING IN MAC MODE TABLE 6-3: MII TRANSMIT TIMING IN MAC MODE VALUES Symbol Description tP (100BASE-TX / Min Typ Max Units RX_CLK period 40/400 ns RX_CLK pulse width low 20/200 ns RX_CLK pulse width high 20/200 ns 16 ns 10BASE-Te) tWL (100BASE-TX / 10BASE-Te) tWH (100BASE-TX / 10BASE-Te) tOD RX_DV, RXD_[3:0] output delay from rising edge of RX_CLK DS00002330E-page 172  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.4.2.2 MII Receive Timing in MAC Mode Figure 6-3 illustrates a read operation by the KSZ9897R from a PHY or other device while operating the KSZ9897R in MAC Mode. FIGURE 6-3: TABLE 6-4: MII RECEIVE TIMING IN MAC MODE MII RECEIVE TIMING IN MAC MODE VALUES Symbol tP (100BASE-TX / Description Min Typ Max Units TX_CLK period 40/400 ns TX_CLK pulse width low 20/200 ns TX_CLK pulse width high 20/200 ns 10BASE-Te) tWL (100BASE-TX / 10BASE-Te) tWH (100BASE-TX / 10BASE-Te) tSU1 TXD_[3:0] setup time to rising edge of TX_CLK 10 ns tSU2 TX_EN, TX_ER setup time to rising edge of TX_CLK 10 ns tHD1 TXD_[3:0] hold time from rising edge of TX_CLK 10 ns tHD2 TX_EN, TX_ER hold time from rising edge of TX_CLK 10 ns  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 173 KSZ9897R 6.4.2.3 MII Receive Timing in PHY Mode FIGURE 6-4: TABLE 6-5: MII RECEIVE TIMING IN PHY MODE MII RECEIVE TIMING IN PHY MODE VALUES Symbol tP (100BASE-TX / Description Min Typ Max Units RX_CLK period 40/400 ns RX_CLK pulse width low 20/200 ns RX_CLK pulse width high 20/200 ns 20 ns 10BASE-Te) tWL (100BASE-TX / 10BASE-Te) tWH (100BASE-TX / 10BASE-Te) tOD RX_DV, RXD_[3:0] output delay from rising edge of RX_CLK DS00002330E-page 174  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.4.2.4 MII Transmit Timing in PHY Mode FIGURE 6-5: MII TRANSMIT TIMING IN PHY MODE TABLE 6-6: MII TRANSMIT TIMING IN PHY MODE VALUES Symbol Description tP (100BASE-TX / Min Typ Max Units TX_CLK period 40/400 ns TX_CLK pulse width low 20/200 ns TX_CLK pulse width high 20/200 ns 10BASE-Te) tWL (100BASE-TX / 10BASE-Te) tWH (100BASE-TX / 10BASE-Te) tSU1 TXD_[3:0] setup time to rising edge of TX_CLK 10 ns tSU2 TX_EN, TX_ER setup time to rising edge of TX_CLK 10 ns tHD1 TXD_[3:0] hold time from rising edge of TX_CLK 0 ns tHD2 TX_EN, TX_ER hold time from rising edge of TX_CLK 0 ns  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 175 KSZ9897R 6.4.3 RMII TIMING Figure 6-6 and Figure 6-7 illustrate the RMII timing requirements. FIGURE 6-6: RMII TRANSMIT TIMING FIGURE 6-7: RMII RECEIVE TIMING TABLE 6-7: RMII TIMING VALUES Symbol Description Min tcyc Clock cycle t1 Setup time t2 Hold time 2 tod Output delay 7 DS00002330E-page 176 Typ Max 20 Units ns 4 ns ns 9 13 ns  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.4.4 MIIM TIMING Figure 6-8 illustrates the MIIM timing requirements. FIGURE 6-8: TABLE 6-8: MIIM TIMING MIIM TIMING VALUES Symbol Description Min Typ Max Units tP MDC period tOD Output delay tSU MDIO setup time to rising edge of MDC 10 ns tHD MDIO hold time from rising edge of MDC 5 ns  2022 Microchip Technology Inc. and its subsidiaries 400 ns 200 ns DS00002330E-page 177 KSZ9897R 6.4.5 SPI TIMING Figure 6-9 and Figure 6-10 illustrate the SPI timing requirements. FIGURE 6-9: SPI DATA INPUT TIMING SCS_N SCL SDI SDO FIGURE 6-10: SPI DATA OUTPUT TIMING SCS_N SCL SDO SDO SDI TABLE 6-9: SPI TIMING VALUES Symbol fSCLK Description Min SCL clock frequency Typ Max Units 50 MHz t1 SCS_N active setup time 8 ns t2 SDI data input setup time 3 ns t3 SDI data input hold time 3 ns t4 SCS_N active hold time 8 ns t5 SCS_N disable high time 8 t6 SCL falling edge to SDO data output valid 2 t7 SCS_N inactive to SDO data input invalid 1 DS00002330E-page 178 ns 9 ns ns  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.4.6 AUTO-NEGOTIATION TIMING Figure 6-11 illustrates the Auto-Negotiation timing requirements. FIGURE 6-11: TABLE 6-10: AUTO-NEGOTIATION TIMING AUTO-NEGOTIATION TIMING VALUES Symbol tBTB tFLPW Description FLP burst to FLP burst Min Typ Max Units 8 16 24 ms FLP burst width 2 ms 100 ns tPW Clock/Data pulse width tCTD Clock pulse to data pulse 55.5 64 69.5 s tCTC Clock pulse to clock pulse 111 128 139 s Number of clock/data pulses per burst 17  2022 Microchip Technology Inc. and its subsidiaries 33 DS00002330E-page 179 KSZ9897R 6.4.7 POWER-UP AND RESET TIMING Figure 6-12 illustrates the power-up and reset timing requirements. FIGURE 6-12: POWER-UP AND RESET TIMING NOTE 1 TRANSCEIVER (AVDDH), DIGITAL I/Os (VDDIO) NOTE 3 CORE (AVDDL, DVDDL) NOTE 2 SUPPLY VOLTAGES tvr tpc tsr RESET_N tcs tch CONFIGURATION STRAP INPUT trc CONFIGURATION STRAP OUTPUT TABLE 6-11: POWER-UP AND RESET TIMING VALUES Symbol Description Min Typ Max Units tvr Supply voltage rise time (must be monotonic) 200 s tsr Stable supply voltages to de-assertion of reset 10 ms tcs Configuration strap input setup time 5 ns tch Configuration strap input hold time 5 ns trc De-assertion of reset to configuration strap pin output 6 ns tpc Supply voltages cycle off-to-on time 150 ms trw Reset pulse width after power-up (warm-reset) 1 s Note 1: The recommended powering sequence is to bring up all voltages at the same time. If this cannot be done, RESET_N should be held low until all supplies are stable, then brought high. Note 2: After the de-assertion of reset, it is recommended to wait a minimum of 100s before starting to program the device through any interface. Note 3: The power supplies may be powered down in any sequence. Before the next power-up cycle, all supply voltages to the device should reach less than 0.4V and there should be a minimum wait time of 150ms from power-off to power-on. DS00002330E-page 180  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 6.5 Clock Specifications A crystal or external clock source, such as an oscillator, is used to provide a 25MHz reference clock for the KSZ9897R. If an external clock source is used, the XO pin must be left floating. Since the XI/XO circuit is powered from AVDDH, the external clock source should also be powered from the same power rail. Figure 6-13 details the available connection methods. Table 6-12 details the recommended crystal specifications. FIGURE 6-13: INPUT REFERENCE CLOCK CONNECTION OPTIONS Ethernet Switch Ethernet Switch XI XO XI 25 MHz OSC +/-50ppm 25 MHz XTAL +/-50ppm TABLE 6-12: No Connect No Connect XO REFERENCE CRYSTAL CHARACTERISTICS Characteristic Min Typ Max Oscillation Mode Fundamental Frequency 25 Units MHz ±50 ppm Effective Series Resistance (ESR) 50 Ω Total period jitter (peak-to-peak) 100 ps Drive level 100 uW Frequency tolerance  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 181 KSZ9897R 7.0 DESIGN GUIDELINES This section provides general design guidelines for the following: • Reset Circuit Guidelines • Magnetics Connection and Selection Guidelines 7.1 Reset Circuit Guidelines Figure 7-1 illustrates the recommended reset circuit for powering up the KSZ9897R if reset is triggered by the power supply. FIGURE 7-1: SIMPLE RESET CIRCUIT VDDIO D1: 1N4148 D1 Ethernet Switch R 10K RESET_N C 10uF Figure 7-2 illustrates a reset circuit recommended for applications where reset is driven by another device, such as a CPU. At power-on reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ9897R. The RST_OUT_N from the CPU provides a warm reset after power-up. FIGURE 7-2: RESET CIRCUIT FOR CPU RESET INTERFACE VDDIO Ethernet Switch R 10K D1 CPU/FPGA RESET_N RST_OUT_N C 10uF D2 D1, D2: 1N4148 DS00002330E-page 182  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 7.2 Magnetics Connection and Selection Guidelines A 1:1 isolation transformer is required at the line interface. For designs exceeding FCC requirements, utilize one with integrated common-mode chokes. An optional auto-transformer stage following the chokes provides additional common-mode noise and signal attenuation. The KSZ9897R PHY port design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltagemode implementation, the transmit drivers supply the common-mode voltages to the four differential pairs. Therefore, the four transformer center tap pins on the KSZ9897R chip side should not be connected to any power supply source on the board; rather, the center tap pins should be separated from one another and connected through separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage could be different between the differential pairs, depending on the connected speed mode. Figure 7-3 details a typical magnetic interface circuit for the KSZ9897R PHY port. FIGURE 7-3: TYPICAL MAGNETIC INTERFACE CIRCUIT 1 TXRXxP_A 2 TXRXxM_A Switch PHY Port x TXRXxM_B 4 5 TXRXxP_C RJ-45 CONNECTOR 3 TXRXxP_B TXRXxM_C 6 7 TXRXxP_D 8 TXRXxM_D 4X 75 Ohm (4X 0.1uF) 1000 pF / 2kV SIGNAL GROUND CHASSIS GROUND Table 7-1 provides a list of recommended magnetic characteristics. TABLE 7-1: MAGNETICS SELECTION CRITERIA Parameter Turns ratio Open-circuit inductance (min.) Insertion loss (typ.) HIPOT (min.)  2022 Microchip Technology Inc. and its subsidiaries Value Test Condition 1 CT : 1 CT 350µH 100mV, 100KHz, 8mA 1.0dB 100KHz to 100MHz 1500vrms DS00002330E-page 183 KSZ9897R Table 7-2 provides a list of KSZ9897R compatible single-port magnetics with separated transformer center tap pins on the Gigabit PHY chip side. TABLE 7-2: COMPATIBLE SINGLE-PORT 10/100/1000 MAGNETICS Manufacturer Bel Fuse Part Number 0826-1G1T-23-F Temperature Range Magnetic + RJ-45 Yes 0°C to 70°C Yes No Auto-Transformer HALO TG1G-E001NZRL No –40°C to 85°C HALO TG1G-S001NZRL No 0°C to 70°C No HALO TG1G-S002NZRL Yes 0°C to 70°C No Pulse H5007NL Yes 0°C to 70°C No Pulse H5062NL Yes 0°C to 70°C No Pulse HX5008NL Yes –40°C to 85°C No Yes Pulse JK0654219NL Yes 0°C to 70°C Pulse JK0-0136NL No 0°C to 70°C Yes TDK TLA-7T101LF No 0°C to 70°C No Wurth/Midcom 000-7093-37R-LF1 Yes 0°C to 70°C No DS00002330E-page 184  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R 8.0 PACKAGE INFORMATION 8.1 Package Marking Information 128-TQFP-EP MICROCHIP KSZ9897RTXt e3 Rnnn e3 YYWWNNN Legend: Note: t R nnn e3 YY WW NNN Temperature range designator (C = commercial, I = industrial) Product revision Internal code Pb-free JEDEC® designator for Matte Tin (Sn) Year code (last two digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard device marking consists of Microchip part number, year code, week code and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 185 KSZ9897R 8.2 Package Drawings FIGURE 8-1: PACKAGE (DRAWING) 128-Lead Thin Quad Flatpack (6XX) - 14x14x1.0 mm Body [TQFP] With 10x10 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SEATING PLANE C D A A2 D1 B (DATUM A) DETAIL A 128X b (DATUM B) 0.07 C A B E1 E NOTE 1 N 128 TIPS 0.20 C 2 1 3 4X TOP VIEW 0.20 C A A1 128X D2 0.08 C 1 3 2 SIDE VIEW N NOTE 1 E2 c GAUGE PLANE L Ĭ (L1) DETAIL A e DETAIL B BOTTOM VIEW Microchip Technology Drawing C04-418B Sheet 1 of 2 DS00002330E-page 186  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R FIGURE 8-2: PACKAGE (DIMENSIONS) 128-Lead Thin Quad Flatpack (6XX) - 14x14x1.0 mm Body [TQFP] With 10x10 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X= A OR B X e 2 DETAIL B Notes: Units Dimension Limits N Number of Terminals e Pitch Overall Height A Standoff A1 A2 Molded Package Thickness Overall Length D Molded Package Length D1 Exposed Pad Length D2 E Overall Width Molded Package Width E1 E2 Exposed Pad Width b Terminal Width Terminal Length L c Terminal Thickness (L1) Footprint Footprint Angle Ĭ MIN 0.05 0.95 9.85 9.85 0.13 0.45 0.09 0° MILLIMETERS NOM MAX 128 0.40 BSC 1.20 0.15 1.00 1.05 16.00 BSC 14.00 BSC 10.00 10.15 16.00 BSC 14.00 BSC 10.00 10.15 0.18 0.23 0.60 0.75 0.20 1.00 REF 7° 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-418B Sheet 2 of 2  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 187 KSZ9897R FIGURE 8-3: PACKAGE (LAND PATTERN) 128-Lead Thin Quad Flatpack (6XX) - 14x14x1.0 mm Body [TQFP] With 10x10 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV Y1 ØV C2 EV Y2 128 SILK SCREEN 12 3 X1 PIN 1 INDEX G1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Center Pad Width X2 Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X128) X1 Contact Pad Length (X128) Y1 Contact Pad to Contact Pad (X124) G1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 10.50 10.50 15.40 15.40 0.20 1.54 0.20 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2418B DS00002330E-page 188  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00002330E (07-15-22) Section/Figure/Entry Correction Section 5.1.4.69, "Global PM Available Register" The following has been defeatured in the document: 'low latency cut through mode' and 'time aware traffic scheduler per port'. Table 3-2, "Pin Descriptions" Updated Port Receive Error pin definition: from “MII Mode” to “MII/RMII Modes” and “RMII/RGMII Modes” to “RGMII Mode”. Table 3.2.1, "Configuration Straps" Updated strapping pin high instructions from “a non-LED pin” to “any pin”. Table 3-3, "Configuration Strap Descriptions" Updated In-Band Management to include the following note: “If using I2C, do not enable IBA.” Section 4.1.7, "Auto-Negotiation" Updated auto-negotiation bypass paragraph, changing “operating mode” to “operating speed”. Also added this sentence to the end of the paragraph: “With parallel detection, the duplex will always be half-duplex.” Section 5.1.2.3, "In-Band Management (IBA) Control Register" Updated bit 31 IBA Enable definition to add the following note: “If using I2C, do not enable IBA.” Section 5.1.4.69, "Global PM Available Register" Added new register to accommodate Packet Memory Available Block Count. Section 5.2.2.21, "Port Special Register" Added new register to accommodate Single-LED Mode Workaround Bit. Section 5.2.7.4, "Port Authentication Control Register" Updated bit 2 Access Control List (ACL) Enable definition from “0 = enable” to “0 = disable”. Section 5.2.9.3, "Port Transmit Queue Memory Register" Added new register to accommodate Port N Transmit Queue Blocks Used. Section 5.4.1, "MMD LED Mode Register" Updated bit 4 definition by adding the following sentence: “For Single-LED mode, set this bit and also set bit 9 in register 0xN13C-0xN13D.” Table 5-3, "Data Rate Selection Table for Ingress and Egress Rate Limiting" Updated 7d’1 - 7d’10 1000Mbps BPS definition from “1Mbps” to “10Mbps”. Section 6.4.7, "Power-up and Reset Timing" For Note 3, updated first sentence from: “The recommended power down sequence is to power down the low voltage core before powering down the transceiver and digital I/O voltages, or to have all supplies power down in unison” to “The power supplies may be powered down in any sequence.”  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 189 KSZ9897R TABLE A-1: REVISION HISTORY (CONTINUED) Revision DS00002330D (07-08-19) DS00002330C (10-23-18) DS00002330E-page 190 Section/Figure/Entry Correction Table 4-14, "Transmit Tail Tag Format (from Host to Switch)" Bit 7 changed to “15:11” and description changed to “Reserved”. Section 2.1, "General Description," on page 8 Updated first bullet to indicate the non-blocking wire-speed Ethernet switch fabric supports 1 Gbps on RGMII. Section 4.1.5, "Pair-Swap, Alignment, and Polarity Check" Updated first bullet description. Section 4.3.3, "Back-Off Algorithm" Updated second sentence. Section 4.3.5, "Legal Packet Size" Simplified paragraph for clarity. Section 4.3.6, "Flow Control" Simplified last sentence of third paragraph. Table 4-10 Updated Action description for the Yes entry. Section 4.4.3.2.1, Tag Insertion and Removal Updated last paragraph of section. Section 4.4.8, "Multiple Spanning Tree Support" Updated second sentence. Table 4-17, "ACL Matching Rule Parameters for MD = 01" Corrected ENB[1:0] “01” and “10” definitions to match those in Table 4-16, "Matching Rule Options". Section 4.10, "In-Band Management" • Added to last sentence of first paragraph. • Added additional sentence to end of second paragraph. • Added additional sentence to end of sixth paragraph. Section 5.2.1.7, "Port Operation Control 0 Register" Updated bit 6 and 7 descriptions to include references to the MAC and additional clarification. Section 5.2.2.15, "PHY Remote Loopback Register" Simplified bit 8 description. Section 5.2.4.1, "Port MAC Control 0 Register," on page 128 Bit 0 made reserved. Section 6.4.7, "Power-up and Reset Timing," on page 180 Updated Note 1. Table 6-11 Added new “trw” entry to table. Section 8.1, "Package Marking Information," on page 185 Updated top marking information.  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R TABLE A-1: REVISION HISTORY (CONTINUED) Revision DS00002330B (03-10-17) Section/Figure/Entry Correction Section 8.2, "Package Drawings," on page 186 Updated package drawings. Table 4-16, "Matching Rule Options" Table updated. Section 4.4.9, "Tail Tagging Mode," on page 38 Section updated. Section 4.1.9, "LinkMD® Cable Diagnostics," on page 22 LinkMD details added. Section 4.4.2.4, "Learning," on page 29 Text correction. Section 4.4.2.6, "Aging," on page 30 Corrected “time stamp” to “age count” in multiple locations. Section 5.2.2.5, "PHY AutoNegotiation Advertisement Register," on page 114 Changed default value of Pause (Flow Control) Capability bit to a note referencing the LED1_1 configuration strap. Section 5.2.2.10, "PHY 1000BASE-T Control Register," on page 118 Corrected bit 10 default value. Added information on Test Mode Bits 15:13. Section 5.2.7.4, "Port Authentication Control Register," on page 143 Corrected bits 1:0 description. Section 5.2.2.16, "PHY LinkMD Register," on page 122 Updated register bit descriptions. Section 5.1.1.4, "Global Chip ID 3 Register," on page 66 Corrected bit 0 description. Section 5.4, "MDIO Manageable Device (MMD) Registers (Indirect)," on page 165 Corrected the MMD register read example. Table 6-2, "RGMII Timing Values" Revised minimum RGMII TSKEW parameter. Table 3-3, "Configuration Strap Descriptions" Corrected swapping of LED2_0 and LED4_0, added notes in strapping. Corrected RXD6_0 and RXD7_0 in strapping table. Section 4.1.10, "Remote PHY Loopback," on page 23 Added new section. Section 4.4.5.1, "Two Rate Three Color Marker," on page 36 Added new section.  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 191 KSZ9897R TABLE A-1: REVISION HISTORY (CONTINUED) Revision DS00002330A (01-13-17) DS00002330E-page 192 Section/Figure/Entry Correction Section 4.4.5.2, "Weighted Random Early Detection (WRED)," on page 36 Updated section with additional information. Section 4.9.3, "MII Management (MIIM) Interface," on page 55, Section 4.9.3.1, "Standard MIIM Registers (Direct)", Section 4.9.3.2, "MDIO Manageable Device (MMD) Registers (Indirect)" Added additional information to end of section. Added new subsections on Standard MIIM and MMD registers. Section 5.4, "MDIO Manageable Device (MMD) Registers (Indirect)," on page 165 Added new section. Section 5.2.7.8, "Port Police Queue Rate Register," on page 145 through Section 5.2.7.14, "Port WRED Queue Performance Monitor Control Register," on page 147 Added new register definitions. Section 6.4.1, "RGMII Timing," on page 171 Updated RGMII timing diagrams and data. Table 1-2, “Buffer Types,” on page 6, Table 3-2, “Pin Descriptions,” on page 11, Table 6-1, “Electrical Characteristics,” on page 168 Updated/Clarified pin buffer type information. Initial Document Release  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2022 Microchip Technology Inc. and its subsidiaries DS00002330E-page 193 KSZ9897R PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX Device Package X [XX]( 1) Examples: Temp. Tape & Reel Range Option a) b) Device: KSZ9897R = 7-Port Switch with 2 RGMII/MII/RMII Interfaces Package: TX = 128-pin TQFP-EP Temperature Range: C I = 0C to = -40C to Tape and Reel Option: Blank -TR = Standard packaging (tray) = Tape and Reel (Note 1) DS00002330E-page 194 +70C +85C KSZ9897RTXC 128-pin TQFP-EP package, Commercial temperature, Standard packaging KSZ9897RTXI-TR 128-pin TQFP-EP package, Industrial temperature, Tape and reel (Commercial) (Industrial) Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2022 Microchip Technology Inc. and its subsidiaries KSZ9897R Note the following details of the code protection feature on Microchip products: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. • Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https://www.microchip.com/en-us/support/design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. 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AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2022, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. 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