LAN7500/LAN7500i
Hi-Speed USB 2.0 to 10/100/1000 Ethernet
Controller
Highlights
- Supports checksum offloads (IPv4, IPv6,
TCP, UDP)
- Supports Microsoft NDIS 6.2 large send offload
- Supports IEEE 802.1q VLAN tagging
• Single Chip Hi-Speed USB 2.0 to 10/100/1000
Ethernet Controller
• 10/100/1000 Ethernet MAC with Full-Duplex Support
• 10/100/1000 Ethernet PHY with HP Auto-MDIX
• Integrated USB 2.0 Hi-Speed Device Controller
• Integrated USB 2.0 Hi-Speed PHY
• Implements Reduced Power Operating Modes
• Supports EEPROM-less Operation for Reduced
BOM
• NetDetach provides automatic USB attach/detach
when Ethernet cable is connected/removed
- Ability to add and strip IEEE 802.1q VLAN tags
- VLAN tag based packet filtering (all 4096 VIDs)
- Flexible address filtering modes
- 33 exact matches (unicast or multicast)
- 512-bit hash filter for multicast frames
- Pass all multicast
- Promiscuous unicast/multicast modes
- Inverse filtering
- Pass all incoming with status report
- Wakeup packet support
- Perfect DA frame, wakeup frame, magic packet,
broadcast frame, IPv6 & IPv4 TCP SYN
- 8 programmable 128-bit wakeup frame filters
Target Applications
•
•
•
•
•
•
Embedded Systems/CE Devices
Set-Top Boxes/PVRs
Networked Printers
USB Port Replicators
Standalone USB to Ethernet Dongles
Test Instrumentation/Industrial
- ARP and NS offload
- PME pin support
- Integrated Ethernet PHY
- Auto-negotiation
- Automatic polarity detection and correction
- HP Auto-MDIX support
- Link status change wake-up detection
•
Key Benefits
• USB Device Controller
- Fully compliant with USB Specification Revision 2.0
- Supports HS (480 Mbps) and FS (12 Mbps)
modes
- Four endpoints supported
- Supports vendor specific commands
- Integrated USB 2.0 PHY
- Remote wakeup supported
- High-Performance 10/100/1000 Ethernet
Controller
- Fully compliant with IEEE802.3/802.3u/
802.3ab
- Integrated Ethernet MAC and PHY
- 10BASE-T, 100BASE-TX, and 1000BASE-T
support
- Full- and half-duplex capability (only fullduplex operation at 1000Mbps)
- Full-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and checking
- 9 KB jumbo frame support
- Automatic payload padding and pad removal
- Loop-back modes
2014-2016 Microchip Technology Inc.
•
•
•
•
- Support for 5 status LEDs
- Supports various statistical counters
Power and I/Os
- Various low power modes
- 12 GPIOs
- Supports bus-powered and self-powered
operation
- Variable voltage I/O supply (2.5V/3.3V)
Miscellaneous Features
- EEPROM Controller
- IEEE 1149.1 (JTAG) Boundary Scan
- Requires single 25 MHz crystal
Software
- Windows XP/ Vista / Windows 7 Driver
- Linux Driver
- Win CE Driver
- MAC OS Driver
- EEPROM/Manufacturing Utility for Windows/
DOS
- PXE Support
- DOS ODI Driver
Packaging
- 56-pin QFN (8x8 mm), RoHS compliant
Environmental
- Commercial Temperature Range (0°C to
+70°C)
- Industrial Temperature Range (-40°C to
+85°C)
DS00001734B-page 1
LAN7500/LAN7500I
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00001734B-page 2
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 7
3.0 EEPROM Controller (EPC) ........................................................................................................................................................... 15
4.0 PME Operation ............................................................................................................................................................................. 27
5.0 NetDetach Operation .................................................................................................................................................................... 30
6.0 Application Diagrams .................................................................................................................................................................... 32
7.0 Operational Characteristics ........................................................................................................................................................... 34
8.0 Package Outline ............................................................................................................................................................................ 50
Appendix A: Revision History .............................................................................................................................................................. 52
2014-2016 Microchip Technology Inc.
DS00001734B-page 3
LAN7500/LAN7500I
1.0
INTRODUCTION
1.1
Block Diagram
FIGURE 1-1:
USB
JTAG
LAN7500/LAN7500I SYSTEM DIAGRAM
USB
PHY
USB 2.0
Device
Controller
TAP
Controller
FIFO
Controller
SRAM
Receive
Filtering
Engine
10/100/
1000
Ethernet
MAC
Ethernet
PHY
EEPROM
Controller
Ethernet
EEPROM
LAN7500/LAN7500i
1.1.1
OVERVIEW
The LAN7500/LAN7500i is a high performance Hi-Speed USB 2.0 to 10/100/1000 Ethernet controller. With applications
ranging from embedded systems, set-top boxes, and PVRs, to USB port replicators, USB to Ethernet dongles, and test
instrumentation, the device is a high performance and cost competitive USB to Ethernet connectivity solution.
The LAN7500/LAN7500i contains an integrated 10/100/1000 Ethernet MAC and PHY, Filtering Engine, USB PHY, HiSpeed USB 2.0 device controller, TAP controller, EEPROM controller, and a FIFO controller with a total of 32 KB of internal packet buffering.
The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed standard. The device
implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is compliant with the
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab standards. ARP and NS offload is also supported.
Multiple power management features are provided, including various low power modes and “Magic Packet”, “Wake On
LAN”, and “Link Status Change” wake events. These wake events can be programmed to initiate a USB remote wakeup.
An internal EEPROM controller exists to load various USB configuration information and the device MAC address. The
integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
1.1.2
USB
The USB portion of the LAN7500/LAN7500i integrates a Hi-Speed USB 2.0 device controller and USB PHY.
The USB device controller contains a USB low-level protocol interpreter which implements the USB bus protocol, packet
generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with autonomous error handling. The USB
device controller is capable of operating in USB 2.0 Hi-Speed and Full-Speed compliant modes and contains autonomous protocol handling functions such as handling of suspend/resume/reset conditions, remote wakeup, and stall condition clearing on Setup packets. The USB device controller also autonomously handles error conditions such as retry
for CRC and data toggle errors, and generates NYET, STALL, ACK and NACK handshake responses, depending on
the endpoint buffer status.
The LAN7500/LAN7500i implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The Bulk-in and
Bulk-out Endpoints allow for Ethernet reception and transmission respectively. Implementation of vendor-specific commands allows for efficient statistics gathering and access to the device’s system control and status registers.
DS00001734B-page 4
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
1.1.3
FIFO CONTROLLER
The FIFO controller uses two internal SRAMs to buffer RX and TX traffic. Bulk-Out packets from the USB controller are
directly stored into the TX buffer. The FIFO Controller is responsible for extracting Ethernet frames from the USB packet
data and passing the frames to the MAC. Received Ethernet Frames are filtered by the Receive Filtering Engine and
frames meeting the filtering constraints are stored into the RX buffer and become the basis for bulk-in packets.
1.1.4
ETHERNET
The LAN7500/LAN7500i integrates an IEEE 802.3/802.3u/802.3ab compliant PHY for twisted pair Ethernet applications
and a 10/100/1000 Ethernet Media Access Controller (MAC).
The PHY can be configured for 1000 Mbps (1000BASE-T), 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) operation
in Full-Duplex mode. It can be configured for 100 Mbps or 10 Mbps operation in Half Duplex mode. The PHY block
includes auto-negotiation, auto-polarity correction, and Auto-MDIX. Minimal external components are required for the
utilization of the Integrated PHY.
The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic Packet”, “Wake on
LAN”, and “Link Status Change”. Microsoft NDIS 6.2 and Windows 7 compliant ARP and NS offload support is also provided.The device will respond to an NS or ARP request by generating and transmitting a response. When received in a
SUSPEND state, an NS or ARP request will not result in the generation of a wake event. Additionally, five status LEDs
are supported.
1.1.5
FRAME FILTERING
The LAN7500/LAN7500i Receive Filtering Engine performs frame filtering. It supports 33 perfect address filters. These
can be used to filter either the Ethernet source address or destination address. Additional address filtering is available
via a 512-bit hash filter. The hash filter can perform unicast or multicast filtering.
VLAN tagged frames can be filtered via the VLAN ID. A 4096-bit table exists to support all possible VLAN IDs. The VLAN
type can be programmed. Double tagging is supported.
1.1.6
HOST OFFLOADING
The LAN7500/LAN7500i supports a variety of TCP/UDP/IP checksum offloads to reduce the burden on the host processor. For Ethernet receive frames, the device can be configured to validate the IP checksum and UDP/TCP checksum. Both IPv4 and IPv6 packets are supported. A raw checksum across the layer 3 packet can also be provided.
For Ethernet transmitted frames, the device can be configured to calculate the IP checksum and UDP/TCP checksum.
Additionally, Large Send Offload (LSO) is supported to further reduce host CPU loading.
1.1.7
POWER MANAGEMENT
The LAN7500/LAN7500i features four variations of USB suspend: SUSPEND0, SUSPEND1, SUSPEND2, and SUSPEND3. These modes allow the application to select the ideal balance of remote wakeup functionality and power consumption.
• SUSPEND0: Supports GPIO, “Wake On LAN”, “Magic Packet”, and “PHY Link Up” remote wakeup events. It,
however, consumes the most power.
• SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend state consumes
less power than SUSPEND0.
• SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend mode for the
device.
• SUSPEND3: Supports GPIO, “Good Packet”, and “PHY Link Up” remote wakeup events. A “Good Packet” is a
received frame that is free of errors and passes certain filtering constraints independent of those imposed on
“Wake On LAN” and “Magic Packet” frames. This suspend state consumes power at a level similar to the NORMAL state, however, it allows for power savings in the Host CPU, which greatly exceeds that of the
LAN7500/LAN7500i. The driver may place the device in this state after prolonged periods of not receiving any
Ethernet traffic.
1.1.8
EEPROM CONTROLLER
The LAN7500/LAN7500i contains an EEPROM controller for connection to an external EEPROM. This allows for the
automatic loading of static configuration data upon pin reset, or software reset. The EEPROM can be configured to load
USB descriptors, USB device configuration, and MAC address.
Custom operation without EEPROM is also provided.
2014-2016 Microchip Technology Inc.
DS00001734B-page 5
LAN7500/LAN7500I
1.1.9
GENERAL PURPOSE I/O
Twelve GPIOs are supported. All GPIOs can serve as remote wakeup events when the LAN7500/LAN7500i is in a suspended state.
1.1.10
TAP CONTROLLER
IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.
The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four
pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and an instruction register. The JTAG
pins are described in Table 2-3, “JTAG Pins,” on page 10. The JTAG interface conforms to the IEEE Standard 1149.1 1990 Standard Test Access Port (TAP) and Boundary-Scan Architecture.
All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into
the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.
The JTAG logic is reset when the TMS and TDI pins are high for five TCK periods.
The implemented IEEE 1149.1 instructions and their op codes are shown in Table 1-1.
TABLE 1-1:
EEE 1149.1 OP CODES
Instruction
Op Code
Comment
Bypass
111
Mandatory Instruction
Sample/Preload
010
Mandatory Instruction
EXTEST
000
Mandatory Instruction
Clamp
011
Optional Instruction
HIGHZ
100
Optional Instruction
IDCODE
001
Optional Instruction
Note:
1.1.11
All digital I/O pins support IEEE 1149.1 operation. Analog pins and the XO pin do not support IEEE 1149.1
operation.
TEST FEATURES
Read/Write access to internal SRAMs is provided via the devices registers. JTAG based USB BIST is available.
1.1.12
SYSTEM SOFTWARE
LAN7500/LAN7500i software drivers are available for the following operating systems:
•
•
•
•
•
Windows XP/ Vista/ Windows 7
Win CE
Linux
MAC OS
DOS ODI
In addition, an EEPROM programming utility is available for configuring the external EEPROM. PXE Support is also
available.
DS00001734B-page 6
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
PIN DESCRIPTION AND CONFIGURATION
ETHRBIAS
GPIO6/PME_MODE_SEL
TEST
GPIO5/PME
VDDVARIO
VDD12CORE
GPIO4/LED4
GPIO3/LED3
GPIO2/LED2
GPIO1/LED1
GPIO0/LED0
VDD12CORE
EECS
41
40
39
38
37
36
35
34
33
32
31
30
29
LAN7500/LAN7500I 56-QFN PIN ASSIGNMENTS (TOP VIEW)
nRESET/PME_CLEAR
FIGURE 2-1:
42
2.0
TR0N
43
28
EEDO
TR0P
44
27
EEDI
VDD12A
45
26
EECLK
TR1N
46
LAN7500/LAN7500i
56 PIN QFN
25
GPIO11
TR1P
47
(TOP VIEW)
24
VDDVARIO
VDD12A
48
23
VDD12CORE
VDD12BIAS
49
22
GPIO10
VDD12PLL
50
21
GPIO9
TR2N
51
20
VDD12CORE
TR2P
52
19
VDDVARIO
VDD12A
53
18
GPIO8
TR3N
54
17
VDD12USBPLL
TR3P
55
16
USBRBIAS
VDD12A
56
15
VDD33A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TDI
TCK
TMS
TDO
XI
XO
VDDVARIO
VDD12CORE
SW_MODE
GPIO7
VDD12CORE
USBDM
USBDP
VBUS_DET
VSS
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
2014-2016 Microchip Technology Inc.
DS00001734B-page 7
LAN7500/LAN7500I
TABLE 2-1:
GPIO PINS
Name
Symbol
Buffer
Type
Indicator
LED0
LED0
VOD8
Used in conjunction with LED1. May be programmed to indicate Link and Speed or Link and
Speed and Activity.
General Purpose I/O 0
GPIO0
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
Num PINs
1
Description
Note:
1
Indicator
LED1
LED1
VOD8
Used in conjunction with LED0. May be programmed to indicate Ethernet Link and Speed or
Link and Speed and Activity.
General Purpose I/O 1
GPIO1
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
Note:
1
Indicator
LED2
LED2
VOD8
General Purpose I/O 2
GPIO2
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
This pin is configured as a GPIO by
default.
Indicator
LED3
LED3
VOD8
May be programmed for use as an Ethernet Link
indicator.
General Purpose I/O 3
GPIO3
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
Note:
1
This pin is configured as a GPIO by
default.
May be programmed to indicate Ethernet Link
and Activity or just Activity.
Note:
1
This pin is configured as a GPIO by
default.
Indicator
LED4
LED4
VOD8
General Purpose I/O 4
GPIO4
VIS/VO8/
VOD8
(PU)
PME
PME
VO8/
VOD8
General Purpose I/O 5
GPIO5
VIS/VO8/
VOD8
(PU)
1
DS00001734B-page 8
This pin is configured as a GPIO by
default.
May be programmed to indicate Ethernet Full
Duplex operation.
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
This pin may be used to signal PME when PME
mode of operation is in effect. Refer to Section
4.0, "PME Operation," on page 27 for additional
information.
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 2-1:
GPIO PINS (CONTINUED)
Name
Symbol
Buffer
Type
PME Mode
Select
PME_MODE_SEL
VIS
(PU)
General Purpose I/O 6
GPIO6
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
General Purpose I/O 7
GPIO7
1
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
General Purpose I/O 8
GPIO8
1
VIS/VO6/
VOD6
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
General Purpose I/O 9
GPIO9
1
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
General Purpose I/O 10
GPIO10
1
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
General Purpose I/O 11
GPIO11
1
VIS/VO8/
VOD8
(PU)
This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain
output, or a Schmitt-triggered input.
Buffer
Type
Description
Num PINs
1
TABLE 2-2:
Description
This pin may serve as the PME_MODE_SEL
input when PME mode of operation is in effect.
Refer to Section 4.0, "PME Operation," on
page 27 for additional information.
EEPROM PINS
Num PINs
Name
Symbol
1
EEPROM
Data In
EEDI
VIS
(PD)
This pin is driven by the EEDO output of the
external EEPROM.
1
EEPROM
Data Out
EEDO
VO8
This pin drives the EEDI input of the external
EEPROM.
EEPROM
Chip Select
EECS
VO8
This pin drives the chip select output of the external EEPROM.
Note:
1
1
EEPROM
Clock
2014-2016 Microchip Technology Inc.
EECLK
VO8
The EECS output may tri-state briefly
during power-up. Some EEPROM
devices may be prone to false selection during this time. When an
EEPROM is used, an external pulldown resistor is recommended on this
signal to prevent false selection. Refer
to your EEPROM manufacturer’s
datasheet for additional information.
This pin drives the EEPROM clock of the external
EEPROM.
DS00001734B-page 9
LAN7500/LAN7500I
TABLE 2-3:
JTAG PINS
Num PINs
Name
Symbol
Buffer
Type
1
JTAG Test
Data Out
TDO
VO8
JTAG (IEEE 1149.1) data output.
TDI
VIS
(PU)
JTAG (IEEE 1149.1) data input.
1
JTAG Test
Data Input
1
JTAG Test
Clock
TCK
VIS
(PD)
JTAG (IEEE 1149.1) test clock.
JTAG Test
Mode Select
TMS
VIS
(PU)
JTAG (IEEE 1149.1) test mode select.
1
TABLE 2-4:
Description
Note:
Note:
Note:
When not used, tie this pin to
VDDVARIO.
When not used, tie this pin to VSS.
When not used, tie this pin to
VDDVARIO.
USB PINS
Name
Symbol
Buffer
Type
USB DMINUS
USBDM
AIO
Note:
The functionality of this pin may be
swapped to USB DPLUS via the Port
Swap bit of Configuration Flags 0.
USB
DPLUS
USBDP
AIO
Note:
1
The functionality of this pin may be
swapped to USB DMINUS via the Port
Swap bit of Configuration Flags 0.
External USB
Bias Resistor.
USBRBIAS
AI
1
Num PINs
Description
1
DS00001734B-page 10
Used for setting HS transmit current level and onchip termination impedance. Connect to an external 12K 1.0% resistor to ground.
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 2-5:
ETHERNET PHY PINS
Num PINs
Name
Symbol
Buffer
Type
1
Crystal Input
XI
ICLK
Description
External 25 MHz crystal input.
Note:
This pin can also be driven by a singleended clock oscillator. When this
method is used, XO should be left
unconnected
1
Crystal Output
XO
OCLK
1
Ethernet
TX/RX Positive Channel
0
TR0P
AIO
Transmit/Receive Positive Channel 0.
1
Ethernet
TX/RX Negative Channel
0
TR0N
AIO
Transmit/Receive Negative Channel 0.
1
Ethernet
TX/RX Positive Channel
1
TR1P
AIO
Transmit/Receive Positive Channel 1.
1
Ethernet
TX/RX Negative Channel
1
TR1N
AIO
Transmit/Receive Negative Channel 1.
1
Ethernet
TX/RX Positive Channel
2
TR2P
AIO
Transmit/Receive Positive Channel 2.
1
Ethernet
TX/RX Negative Channel
2
TR2N
AIO
Transmit/Receive Negative Channel 2.
1
Ethernet
TX/RX Positive Channel
3
TR3P
AIO
Transmit/Receive Positive Channel 3.
1
Ethernet
TX/RX Negative Channel
3
TR3N
AIO
Transmit/Receive Negative Channel 3.
1
External PHY
Bias Resistor
ETHRBIAS
AI
2014-2016 Microchip Technology Inc.
External 25 MHz crystal output.
Used for the internal bias circuits. Connect to an
external 8.06K 1.0% resistor to ground.
DS00001734B-page 11
LAN7500/LAN7500I
TABLE 2-6:
MISCELLANEOUS PINS
Num PINs
Name
Symbol
1
System Reset
nRESET
Buffer
Type
VIS
(PU)
Description
This active-low pin allows external hardware to
reset the device.
Note:
1
PME Clear
PME_CLEAR
VIS
(PU)
Detect
Upstream
VBUS Power
VBUS_DET
IS_5V
(PD)
Assertion of nRESET is required following power-on.
This pin may serve as the PME_CLEAR input
when PME mode of operation is in effect. Refer to
Section 4.0, "PME Operation," on page 27 for
additional information.
Detects state of upstream bus power.
For bus powered operation, this pin must be tied
to VDD33A.
For self powered operation, refer to the
LAN7500/LAN7500i reference schematics.
1
Test
TEST
-
1
Switching
Regulator
Mode
SW_MODE
VO6
TABLE 2-7:
This pin must always be connected to VSS for
proper operation.
When asserted, this pin places the external
switching regulator into power saving mode.
Note:
The SW_MODE_POL and SW_MODE_SEL bits of Configuration
Flags 1 control the polarity of the pin
and when it is asserted, respectively.
I/O POWER PINS, CORE POWER PINS, AND GROUND PAD
Num PINs
Name
Symbol
Buffer
Type
1
+3.3V Analog Power
Supply Input
VDD33A
P
Refer to Section 6.0, "Application Diagrams," on
page 32 and the LAN7500/LAN7500i reference
schematics for connection information.
4
+3.3V/+2.5V
I/O Power
Supply Input
VDDVARIO
P
Refer to Section 6.0, "Application Diagrams," on
page 32 and the LAN7500/LAN7500i reference
schematics for connection information.
6
Digital Core
+1.2V Power
Supply Input
VDD12CORE
P
Refer to Section 6.0, "Application Diagrams" and
the LAN7500/LAN7500i reference schematics for
connection information.
1
USB PLL
+1.2V Power
Supply Input
VDD12USBPLL
P
Refer to Section 6.0, "Application Diagrams," on
page 32 and the LAN7500/LAN7500i reference
schematics for additional connection information.
4
Ethernet
+1.2V Port
Power Supply Input For
Channels 0-3
VDD12A
P
Refer to Section 6.0, "Application Diagrams," on
page 32 and the LAN7500/LAN7500i reference
schematics for additional connection information.
DS00001734B-page 12
Description
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 2-7:
I/O POWER PINS, CORE POWER PINS, AND GROUND PAD (CONTINUED)
Num PINs
Name
Symbol
Buffer
Type
1
Ethernet
+1.2V Bias
Power Supply Input
VDD12BIAS
P
Refer to Section 6.0, "Application Diagrams," on
page 32 and the LAN7500/LAN7500i reference
schematics for additional connection information.
1
Ethernet PLL
+1.2V Power
Supply Input
VDD12PLL
P
Refer toSection 6.0, "Application Diagrams," on
page 32 and the LAN7500/LAN7500i reference
schematics for additional connection information.
Exposed
pad on
package
bottom
(FIGURE
2-1:)
Ground
VSS
P
Common Ground
2.1
Description
Pin Assignments
TABLE 2-8:
56-QFN PACKAGE PIN ASSIGNMENTS
Pin
Num
Pin Name
Pin
Num
Pin Name
Pin
Num
Pin Name
Pin
Num
Pin Name
1
TDI
15
VDD33A
29
EECS
43
TR0N
2
TCK
16
USBRBIAS
30
VDD12CORE
44
TR0P
3
TMS
17
VDD12USBPLL
31
GPIO0/LED0
45
VDD12A
4
TDO
18
GPIO8
32
GPIO1/LED1
46
TR1N
5
XI
19
VDDVARIO
33
GPIO2/LED2
47
TR1P
6
XO
20
VDD12CORE
34
GPIO3/LED3
48
VDD12A
7
VDDVARIO
21
GPIO9
35
GPIO4/LED4
49
VDD12BIAS
8
VDD12CORE
22
GPIO10
36
VDD12CORE
50
VDD12PLL
9
SW_MODE
23
VDD12CORE
37
VDDVARIO
51
TR2N
10
GPIO7
24
VDDVARIO
38
GPIO5/PME
52
TR2P
11
VDD12CORE
25
GPIO11
39
TEST
53
VDD12A
12
USBDM
26
EECLK
40
GPIO6/
PME_MODE_SEL
54
TR3N
13
USBDP
27
EEDI
41
ETHRBIAS
55
TR3P
14
VBUS_DET
28
EEDO
42
nRESET/
PME_CLEAR
56
VDD12A
EXPOSED PAD
MUST BE CONNECTED TO VSS
2014-2016 Microchip Technology Inc.
DS00001734B-page 13
LAN7500/LAN7500I
2.2
Buffer Types
TABLE 2-9:
BUFFER TYPES
Buffer Type
VIS
IS_5V
VO6
VOD6
VO8
VOD8
PU
Description
Variable voltage Schmitt-triggered Input
5V Tolerant Schmitt-triggered Input
Variable voltage output with 6mA sink and 6mA source
Variable voltage open-drain output with 6mA sink
Variable voltage output with 8mA sink and 8mA source
Variable voltage open-drain output with 8mA sink
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Note:
PD
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pulldowns are always enabled.
Note:
AI
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to LAN7500/LAN7500i. When connected to a load that must be pulled high, an external resistor must be added.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to LAN7500/LAN7500i. When connected to a load that must be pulled low, an external resistor must be added.
Analog input
AIO
Analog bi-directional
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
P
DS00001734B-page 14
Power pin
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
3.0
EEPROM CONTROLLER (EPC)
LAN7500/LAN7500i may use an external EEPROM to store the default values for the USB descriptors and the MAC
address. The EEPROM controller supports most “93C56 or 93C66” type 256/512 byte EEPROMs. A total of nine
address bits are used for connection to the device.
A 3-wire style 2K/4K EEPROM that is organized for 256/512 x 8-bit operation must be used.
The MAC address is used as the default Ethernet MAC address and is loaded into the device’s MAC address registers.
If a properly configured EEPROM is not detected, it is the responsibility of the Host LAN Driver to set the IEEE
addresses.
After a system-level reset occurs, the device will load the default values from a properly configured EEPROM. The
device will not accept USB transactions from the Host until this process is completed.
The device’s EEPROM controller also allows the Host system to read, write and erase the contents of the Serial
EEPROM.
3.1
EEPROM Format
Table 3-1 illustrates the format in which data is stored inside of the EEPROM.
Note the EEPROM offsets are given in units of 16-bit word offsets. A length field with a value of zero indicates that the
field does not exist in the EEPROM. The device will use the field’s HW default value in this case.
Note:
For the device descriptor, the only valid values for the length are 0 and 18.
Note:
For the configuration and interface descriptor, the only valid values for the length are 0 and 18.
Note:
The EEPROM programmer must ensure that if a string descriptor does not exist in the EEPROM, the referencing descriptor must contain 00h for the respective string index field.
Note:
If all string descriptor lengths are zero, then a Language ID will not be supported.
TABLE 3-1:
EEPROM FORMAT
EEPROM Address
EEPROM Contents
00h
A5h (EEPROM Programmed Indicator)
01h
MAC Address [7:0]
02h
MAC Address [15:8]
03h
MAC Address [23:16]
04h
MAC Address [31:24]
05h
MAC Address [39:32]
06h
MAC Address [47:40]
07h
Full-Speed Polling Interval for Interrupt Endpoint
08h
Hi-Speed Polling Interval for Interrupt Endpoint
09h
Configuration Flags 0
0Ah
Language ID Descriptor [7:0]
0Bh
Language ID Descriptor [15:8]
0Ch
Manufacturer ID String Descriptor Length (bytes)
0Dh
Manufacturer ID String Descriptor EEPROM Word Offset
0Eh
Product Name String Descriptor Length (bytes)
2014-2016 Microchip Technology Inc.
DS00001734B-page 15
LAN7500/LAN7500I
TABLE 3-1:
EEPROM FORMAT (CONTINUED)
EEPROM Address
EEPROM Contents
0Fh
Product Name String Descriptor EEPROM Word Offset
10h
Serial Number String Descriptor Length (bytes)
11h
Serial Number String Descriptor EEPROM Word Offset
12h
Configuration String Descriptor Length (bytes)
13h
Configuration String Descriptor Word Offset
14h
Interface String Descriptor Length (bytes)
15h
Interface String Descriptor Word Offset
16h
Hi-Speed Device Descriptor Length (bytes)
17h
Hi-Speed Device Descriptor Word Offset
18h
Hi-Speed Configuration and Interface Descriptor Length (bytes)
19h
Hi-Speed Configuration and Interface Descriptor Word Offset
1Ah
Full-Speed Device Descriptor Length (bytes)
1Bh
Full-Speed Device Descriptor Word Offset
1Ch
Full-Speed Configuration and Interface Descriptor Length (bytes)
1Dh
Full-Speed Configuration and Interface Descriptor Word Offset
1Eh
GPIO[7:0] Wakeup Enables
Bit x = 0 -> GPIOx Pin Disabled for Wakeup Use.
Bit x = 1 -> GPIOx Pin Enabled for Wakeup Use.
1Fh
GPI0[11:8] Wakeup Enables
Bit x = 0 -> GPIO(x+8) Pin Disabled for Wakeup Use.
Bit x = 1 -> GPIO(x+8) Pin Enabled for Wakeup Use.
Note:
Note:
Bits 7:4 Unused.
20h
GPIO PME Flags
21h
Configuration Flags 1
EEPROM byte addresses past 21h can be used to store data for any purpose assuming these addresses
are not used for descriptor storage.
DS00001734B-page 16
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
Table 3-2 describes the Configuration Flags 0 byte. If a configuration descriptor exists in the EEPROM, it will override
the values in Configuration Flags 0.
TABLE 3-2:
CONFIGURATION FLAGS 0
Bits
7
Description
Port Swap
This bit facilitates swapping the mapping of USBDP and USBDM.
0 = USBDP maps to the USB D+ line and USBDM maps to the USB D- line.
1 = USBDP maps to the USB D- line. USBDM maps to the USB D+ line.
6:5
PHY Boost
This field provides the ability to boost the electrical drive strength of the HS output current to the
upstream port.
00 = Normal electrical drive strength.
01 = Elevated electrical drive strength (+4% boost).
10 = Elevated electrical drive strength (+8% boost).
11 = Elevated electrical drive strength (+12% boost).
4
Duplex Detection
This bit determines whether duplex operational mode is detected automatically or manually set.
0 = Manual
1 = Automatic
3
Speed Detection
This bit determines whether operational speed is detected automatically or manually set.
0 = Manual
1 = Automatic
2014-2016 Microchip Technology Inc.
DS00001734B-page 17
LAN7500/LAN7500I
TABLE 3-2:
CONFIGURATION FLAGS 0 (CONTINUED)
Bits
Description
2
SPD_LED_FUNCTION
This bit specifies the functionality of speed LEDs (LED0 and LED1). The Speed LEDs’ behavior is determined by line speed and the setting of this bit, as indicated in following table:
SPD_LED_FUNCTION
SPEED (Mbps)
LED0
LED1
0
No Link
Off
Off
0
10
On
Off
0
100
Off
On
0
1000
On
On
1
No Link
Off
Off
1
10
Blink
Off
1
100
Off
Blink
1
1000
Blink
Blink
When SPD_LED_FUNCTION = 0, the LEDs function solely as Link and Speed LEDs. When
SPD_LED_FUNCTION = 1, the LEDs function as Link and Speed and Activity LEDs. In those cases, the
table entry “Blink” indicates the LED will remain on when no transmit or receive activity is detected and
will blink at an 80 mS rate whenever TX or RX activity is detected.
Note:
1
GPIOEN[1:0] in Configuration Flags 1 must be set in order to properly control speed LED
operation. If only one of the bits is set, then untoward operation and unexpected results may
occur. If both bits are clear, then SPD_LED_FUNCTION is ignored.
Remote Wakeup Support
0 = Device does not support remote wakeup.
1 = Device supports remote wakeup.
0
Power Method
0 = Device is bus powered.
1 = Device is self powered.
DS00001734B-page 18
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
Table 3-3 describes the Configuration Flags 1.
TABLE 3-3:
CONFIGURATION FLAGS 1
Bits
7
Description
LED2_FUNCTION
This bit specifies the functionality of LED2.
0 = Link and Activity LED.
1 = Activity LED.
Note:
6:2
1
This bit is ignored if GPIOEN2 is not set in this flag byte.
GPIOEN[4:0]
This field specifies GPIO/LED functionality for GPIO[4:0].
0 = GPIOn Pin Functions as GPIO pin.
1 = GPIOn Pin Functions as LED.
SW_MODE_SEL
This bit specifies the modes of operation during which the SW_MODE pin will be asserted.
0 = SW_MODE asserted in SUSPEND2.
1 = SW_MODE asserted in SUSPEND2, SUSPEND1, and NetDetach.
0
SW_MODE_POL
This bit selects the polarity of the SW_MODE pin.
0 = Active low.
1 = Active high.
Table 3-4 describes the GPIO PME flags.
TABLE 3-4:
GPIO PME FLAGS
Bits
7
Description
GPIO PME Enable
Setting this bit enables the assertion of the GPIO5 pin, as a result of a Wakeup (GPIO) pin, Magic
Packet, or PHY Link Up. The host processor may use the GPIO5 pin to asynchronously wake up, in a
manner analogous to a PCI PME pin.
0 = The device does not support GPIO PME signaling.
1 = The device supports GPIO PME signaling.
Note:
6
When this bit is 0, the remaining GPIO PME parameters in this flag byte are ignored.
GPIO PME Configuration
This bit selects whether the GPIO PME is signaled on the GPIO5 pin as a level or a pulse. If pulse is
selected, the duration of the pulse is determined by the setting of the GPIO PME Length bit of this flag
byte. The level of the signal or the polarity of the pulse is determined by the GPIO PME Polarity bit of this
flag byte.
0 = GPIO PME is signaled via a level.
1 = GPIO PME is signaled via a pulse.
Note:
If GPIO PME Enable is 0, this bit is ignored.
2014-2016 Microchip Technology Inc.
DS00001734B-page 19
LAN7500/LAN7500I
TABLE 3-4:
GPIO PME FLAGS (CONTINUED)
Bits
5
Description
GPIO PME Length
When the GPIO PME Configuration bit of this flag byte indicates that the GPIO PME is signaled by a
pulse on the GPIO5 pin, this bit determines the duration of the pulse.
0 = GPIO PME pulse length is 1.5 mS.
1 = GPIO PME pulse length is 150 mS.
Note:
4
If GPIO PME Enable is 0, this bit is ignored.
GPIO PME Polarity
Specifies the level of the signal or the polarity of the pulse used for GPIO PME signaling.
0 = GPIO PME signaling polarity is low.
1 = GPIO PME signaling polarity is high.
Note:
3
If GPIO PME Enable is 0, this bit is ignored.
GPIO PME Buffer Type
This bit selects the output buffer type for GPIO5.
0 = Open drain driver / open source
1 = Push-Pull driver
2
Note:
Buffer Type = 0, Polarity = 0 implies Open Drain
Buffer Type = 0, Polarity = 1 implies Open Source
Note:
If GPIO PME Enable is 0, this bit is ignored.
GPIO PME WOL Select
Four types of wakeup events are supported; Magic Packet, Perfect DA, PHY Link Up, and Wakeup Pin(s)
assertion. Wakeup Pin(s) are selected via the GPIO Wakeup Enables specified in bytes 1Eh and 1Fh of
the EEPROM. This bit selects whether WOL events or Link Up wakeup events are supported.
0 = WOL event wakeup supported.
1 = PHY linkup wakeup supported.
1
Note:
If WOL is selected, the PME Magic Packet Enable and PME Perfect DA Enable bits determine
the WOL event(s) that will cause a wakeup.
Note:
If GPIO PME Enable is 0, this bit is ignored.
PME Magic Packet Enable
When GPIO PME WOL Select indicates WOL is selected, this bit enables/disables Magic Packet detection and wakeup.
0 = Magic Packet event wakeup disabled.
1 = Magic Packet event wakeup enabled.
Note:
0
This bit is ignored if GPIO PME WOL Select indicates WOL event wakeup not supported.
PME Perfect DA Enable
When GPIO PME WOL Select indicates WOL is selected, this bit enables/disables Perfect DA detection
and wakeup.
0 = Perfect DA event wakeup disabled.
1 = Perfect DA event wakeup enabled.
Note:
DS00001734B-page 20
This bit is ignored if GPIO PME WOL Select indicates WOL event wakeup not supported.
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
3.2
EEPROM Defaults
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the EEPROM controller that
no EEPROM or an un-programmed EEPROM is attached to the device. In this case, the hardware default values are
used, as shown in Table 3-5.
TABLE 3-5:
EEPROM DEFAULTS
Field
Default Value
MAC Address
FFFFFFFFFFFFh
Full-Speed Polling Interval (mS)
01h
Hi-Speed Polling Interval (mS)
04h
Configuration Flags 0
1Bh
Maximum Power (mA)
FAh
Vendor ID
0424h
Product ID
7500h
Note:
3.3
Refer to the LAN7500/LAN7500i Vendor/Product ID application note for details on proper usage of these
fields.
EEPROM Auto-Load
Certain system level resets (USB reset, nRESET, and SRST) cause the EEPROM contents to be loaded into the device.
After a reset, the EEPROM controller attempts to read the first byte of data from the EEPROM. If the value A5h is read
from the first address, then the EEPROM controller will assume that a programmed external Serial EEPROM is present.
Note:
3.4
The USB reset only loads the MAC address.
An Example of EEPROM Format Interpretation
Table 3-6 and Table 3-7 provide an example of how the contents of a EEPROM are formatted. Table 3-6 is a dump of
the EEPROM memory (256-byte EEPROM), while Table 3-7 illustrates, byte by byte, how the EEPROM is formatted.
The industrial version of the device is used in the example.
TABLE 3-6:
DUMP OF EEPROM MEMORY
Offset Byte
Value (Hex)
0000h
A5 12 34 56 78 9A BC 01
0008h
04 1E 09 04 0A 0F 12 14
0010h
10 1D 00 00 00 00 12 25
0018h
12 2E 12 37 12 40 00 04
0020h
8A 7C 0A 03 53 00 4D 00
0028h
53 00 43 00 12 03 4C 00
0030h
41 00 4E 00 37 00 35 00
0038h
30 00 30 00 69 00 10 03
2014-2016 Microchip Technology Inc.
DS00001734B-page 21
LAN7500/LAN7500I
TABLE 3-6:
DUMP OF EEPROM MEMORY
Offset Byte
Value (Hex)
0040h
30 00 30 00 30 00 35 00
0048h
31 00 32 00 33 00 12 01
0050h
00 02 FF 00 FF 40 24 04
0058h
00 75 00 01 01 02 03 01
0060h
09 02 27 00 01 01 00 A0
0068h
FA 09 04 00 00 03 FF 00
0070h
FF 00 12 01 00 02 FF 00
0078h
FF 40 24 04 00 75 00 01
0080h
01 02 03 01 09 02 27 00
0088h
01 01 00 A0 FA 09 04 00
0090h - 00FFh
00 03 FF 00 FF 00 .........
TABLE 3-7:
EEPROM EXAMPLE - 256 BYTE EEPROM
EEPROM
Address
EEPROM
Contents
(Hex)
00h
A5
EEPROM Programmed Indicator
01h - 06h
12 34 56 78 9A BC
MAC Address 12 34 56 78 9A BC
07h
01
Full-Speed Polling Interval for Interrupt Endpoint (1ms)
08h
04
Hi-Speed Polling Interval for Interrupt Endpoint (4ms)
09h
1E
Configuration Flags 0 - No USBDP/USBDM swapping, No PHY Boost,
Automatic Duplex and Speed detection, the device is bus powered and
supports remote wakeup, LEDs 0 and 1 are used as Link/Speed/Activity
LEDs (Since they are enabled as LEDs in Configuration Flags 1 GPIOEN field).
0Ah - 0Bh
09 04
0Ch
0A
Manufacturer ID String Descriptor Length (10 bytes)
0Dh
0F
Manufacturer ID String Descriptor EEPROM Word Offset (11h)
Corresponds to EEPROM Byte Offset 22h
0Eh
12
Product Name String Descriptor Length (18 bytes)
0Fh
14
Product Name String Descriptor EEPROM Word Offset (16h)
Corresponds to EEPROM Byte Offset 2Ch
10h
10
Serial Number String Descriptor Length (16 bytes)
11h
1D
Serial Number String Descriptor EEPROM Word Offset (1Fh)
Corresponds to EEPROM Byte Offset 3Eh
DS00001734B-page 22
Description
Language ID Descriptor 0409h, English
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 3-7:
EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED)
EEPROM
Address
EEPROM
Contents
(Hex)
12h
00
Configuration String Descriptor Length (0 bytes - NA)
13h
00
Configuration String Descriptor Word Offset (Don’t Care)
14h
00
Interface String Descriptor Length (0 bytes - NA)
15h
00
Interface String Descriptor Word Offset (Don’t Care)
16h
12
Hi-Speed Device Descriptor Length (18 bytes)
17h
25
Hi-Speed Device Descriptor Word Offset (27h)
Corresponds to EEPROM Byte Offset 4Eh
18h
12
Hi-Speed Configuration and Interface Descriptor Length (18 bytes)
19h
2E
Hi-Speed Configuration and Interface Descriptor Word Offset (30h)
Corresponds to EEPROM Byte Offset 60h
1Ah
12
Full-Speed Device Descriptor Length (18 bytes)
1Bh
37
Full-Speed Device Descriptor Word Offset (39h)
Corresponds to EEPROM Byte Offset 72h
1Ch
12
Full-Speed Configuration and Interface Descriptor Length (18 bytes)
1Dh
40
Full-Speed Configuration and Interface Descriptor Word Offset (42h)
Corresponds to EEPROM Byte Offset 84h
1Eh
00
GPIO[7:0] Wake Enables - GPIO[7:0] Not Used For Wakeup Signaling
1Fh
04
GPIO[11:8] Wake Enables - GPIO10 Used For Wakeup Signaling
20h
8A
GPIO PME Flags - PME Signaling Enabled via Low Level, Push-Pull
Driver, Magic Packet WOL selected.
21h
7C
Configuration Flags 1 - LED2 is Link and Activity LED, GPIO pins 0 to 4
function as LEDs, SW_MODE pin active low in SUSPEND2 state.
22h
0A
Size of Manufacturer ID String Descriptor (10 bytes)
23h
03
Descriptor Type (String Descriptor - 03h)
24h - 2Bh
53 00 4D 00 53 00 43 00
2Ch
12
Size of Product Name String Descriptor (18 bytes)
2Dh
03
Descriptor Type (String Descriptor - 03h)
2Eh - 3Dh
4C 00 41 00 4E 00 37 00
35 00 30 00 30 00
69 00
3Eh
10
Size of Serial Number String Descriptor (16 bytes)
3Fh
03
Descriptor Type (String Descriptor - 03h)
40h - 4Dh
30 00 30 00 30 00 35 00
31 00 32 00 33 00
4Eh
12
2014-2016 Microchip Technology Inc.
Description
Manufacturer ID String (“MCHP” in UNICODE)
Product Name String (“LAN7500i” in UNICODE)
Serial Number String (“0005123” in UNICODE)
Size of Hi-Speed Device Descriptor in Bytes (18 bytes)
DS00001734B-page 23
LAN7500/LAN7500I
TABLE 3-7:
EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED)
EEPROM
Address
EEPROM
Contents
(Hex)
4Fh
01
50h - 51h
00 02
52h
FF
Class Code
53h
00
Subclass Code
54h
FF
Protocol Code
55h
40
Maximum Packet Size for Endpoint 0
56h - 57h
24 04
Vendor ID (0424h)
58h - 59h
00 75
Product ID (7500h)
5Ah - 5Bh
00 01
Device Release Number (0100h)
5Ch
01
Index of Manufacturer String Descriptor
5Dh
02
Index of Product String Descriptor
5Eh
03
Index of Serial Number String Descriptor
5Fh
01
Number of Possible Configurations
60h
09
Size of Hi-Speed Configuration Descriptor in bytes (9 bytes)
61h
02
Descriptor Type (Configuration Descriptor - 02h)
62h - 63h
27 00
64h
01
Number of Interfaces
65h
01
Value to use as an argument to select this configuration
66h
00
Index of String Descriptor describing this configuration
67h
A0
Bus powered and remote wakeup enabled
68h
FA
Maximum Power Consumption is 500 mA
69h
09
Size of Descriptor in Bytes (9 Bytes)
6Ah
04
Descriptor Type (Interface Descriptor - 04h)
6Bh
00
Number identifying this Interface
6Ch
00
Value used to select alternative setting
6Dh
03
Number of Endpoints used for this interface (Less endpoint 0)
6Eh
FF
Class Code
6Fh
00
Subclass Code
70h
FF
Protocol Code
71h
00
Index of String Descriptor Describing this interface
72h
12
Size of Full-Speed Device Descriptor in Bytes (18 Bytes)
DS00001734B-page 24
Description
Descriptor Type (Device Descriptor - 01h)
USB Specification Number that the device complies with (0200h)
Total length in bytes of data returned (0027h = 39 bytes)
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 3-7:
EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED)
EEPROM
Address
EEPROM
Contents
(Hex)
73h
01
74h - 75h
00 02
76h
FF
Class Code
77h
00
Subclass Code
78h
FF
Protocol Code
79h
40
Maximum Packet Size for Endpoint 0
7Ah - 7Bh
24 04
Vendor ID (0424h)
7Ch - 7Dh
00 75
Product ID (7500h)
7Eh - 7Fh
00 01
Device Release Number (0100h)
80h
01
Index of Manufacturer String Descriptor
81h
02
Index of Product String Descriptor
82h
03
Index of Serial Number String Descriptor
83h
01
Number of Possible Configurations
84h
09
Size of Full-Speed Configuration Descriptor in bytes (9 bytes)
85h
02
Descriptor Type (Configuration Descriptor - 02h)
86h - 87h
27 00
88h
01
Number of Interfaces
89h
01
Value to use as an argument to select this configuration
8Ah
00
Index of String Descriptor describing this configuration
8Bh
A0
Bus powered and remote wakeup enabled
8Ch
FA
Maximum Power Consumption is 500 mA
8Dh
09
Size of Full-Speed Interface Descriptor in Bytes (9 Bytes)
8Eh
04
Descriptor Type (Interface Descriptor - 04h)
8Fh
00
Number identifying this Interface
90h
00
Value used to select alternative setting
91h
03
Number of Endpoints used for this interface (Less endpoint 0)
92h
FF
Class Code
93h
00
Subclass Code
94h
FF
Protocol Code
95h
00
Index of String Descriptor Describing this interface
96h - FFh
-
2014-2016 Microchip Technology Inc.
Description
Descriptor Type (Device Descriptor - 01h)
USB Specification Number that the device complies with (0200h)
Total length in bytes of data returned (0027h = 39 bytes)
Data storage for use by Host as desired
DS00001734B-page 25
LAN7500/LAN7500I
DS00001734B-page 26
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
4.0
PME OPERATION
LAN7500/LAN7500i provides a mechanism for waking up a host system via PME mode of operation. PME signaling is
only available while the device is operating in the self powered mode and a properly configured EEPROM is attached.
Figure 4-1 illustrates a typical application.
FIGURE 4-1:
TYPICAL APPLICATION
Host
Processor
Chipset
HC
DP/DM
Enable
PME
VBUS_DET
Embedded
Controller
(EC)
PME_CLEAR
LAN7500/
LAN7500i
PME_MODE_SEL
EEPROM
2014-2016 Microchip Technology Inc.
DS00001734B-page 27
LAN7500/LAN7500I
The Host Processor is connected to a Chipset containing the Host USB Controller (HC). The USB Host Controller interfaces to LAN7500/LAN7500i via the DP/DM USB signals. An Embedded Controller (EC) signals the Chipset and the
Host processor to power up via an Enable signal. The EC interfaces to LAN7500/LAN7500i via four signals. The PME
signal is an input to the EC from the device that indicates the occurrence of a wakeup event. The VBUS_DET output of
the EC is used to indicate bus power availability. The PME_CLEAR (nRESET) signal is used to clear the PME. The
PME_MODE_SEL signal is sampled by the device when PME_CLEAR (nRESET) is asserted and is used by the device
to determine whether it should remain in PME mode or resume normal operation.
GPIO pins are used for PME handling. GPIO5 is reserved for use as an output to signal the PME. GPIO6 is reserved
for use as the PME_MODE_SEL input.
The application scenario in Figure 4-1 assumes that the Host Processor and the Chipset are powered off, the EC is
operational, and the device is in PME mode, waiting for a wake event to occur. A wake event will result in the device
signaling a PME event to the EC, which will then wake up the Host Processor and Chipset via the Enable signal. The
EC asserts VBUS_DET after the USB bus is powered, sets PME_MODE_SEL to determine whether the device is to
begin normal operation or continue in PME mode, and asserts PME_CLEAR (nRESET) to clear the PME.
The following wake events are supported:
• Wakeup Pin(s)
The GPIO pins not reserved for PME handling have the capability to wake up the device when operating in PME
mode. In order for a GPIO to generate a wake event, it’s enable bit must be set
in the GPI0[11:8] Wakeup Enables or GPIO[7:0] Wakeup Enables bytes of the EEPROM, as appropriate. During
PME mode of operation, the GPIOs used for signaling (GPIO5 and GPIO6) are not affected by the values set in
the corresponding bits of GPIO[7:0] Wakeup Enables.
GPIOs 0 - 4 and 7 - 10 are available as wakeup pins in PME mode of operation and are active low by default.
• Magic Packet
Reception of a Magic Packet when in PME mode will result in a PME being asserted.
• Perfect DA match of Physical address
Reception of an Ethernet frame whose Destination address matches the device’s MAC address will result in a
PME being asserted.
• PHY Link Up
Detection of a PHY link partner when in PME mode will result in a PME being asserted.
In order to facilitate PME mode of operation, the GPIO PME Enable bit in the GPIO PME Flags field, must be set and
all remaining GPIO PME Flags field bits must be appropriately configured for pulse or level signaling, buffer type, and
GPIO PME WOL selection. The PME event is signaled on GPIO5.
The PME_MODE_SEL pin (GPIO6) must be driven to the value that determines whether or not the device remains in
PME mode of operation (1) or resumes normal operation (0) when the PME is recognized and cleared by the EC via
PME_CLEAR (nRESET) assertion.
Note:
When in PME mode or nRESET will always cause the contents of the EEPROM to be reloaded.
Figure 4-2 flowcharts PME operation while in Internal PHY mode. The following conditions hold:
EEPROM Configuration:
•
•
•
•
•
•
•
•
GPIO PME Enable = 1 (enabled)
GPIO PME Configuration = 0 (PME signaled via level on GPIO5 pin)
GPIO PME Length = 0 (NA)
GPIO PME Polarity = 1 (high level signals event)
GPIO PME Buffer Type = 1 (Push-Pull)
GPIO PME WOL Select = 0 (Magic Packet wakeup)
Power Method = 1 (self powered)
MAC address for Magic Packet
PME signaling configuration:
• GPIO5 signals PME
• GPIO6 is PME_MODE_SEL
DS00001734B-page 28
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
FIGURE 4-2:
PME OPERATION
VBUS_DET Set To 0 By EC
O r Via Circuitry
EC Sets PM E_M ODE_SEL = 1 And
Asserts PM E_CLEAR
Deassert PM E_CEAR
LAN 7500/LAN 7500i Has EEPROM
W ith GPIO PM E Enable =1, Enters
PM E M ode
False
W akeup Event Detected
By LAN7500/LAN7500i?
True
LAN7500/LAN7500i Asserts PM E
EC Detects PM E
EC To W ake System To
Process W akeup Event?
No
Yes
EC Signals Enable To Host
EC Asserts PM E_CLEAR
VBUS_DET Set to 1 By EC
Or Via Circuitry
LAN7500/LAN7500i Resets And
Deasserts PM E
EC Sets PM E_M ODE_SEL = 0 And
Asserts PM E_CLEAR
LAN7500/LAN7500i Resets And
Deasserts PM E
LAN7500/LAN7500i Connects To USB
Bus
2014-2016 Microchip Technology Inc.
DS00001734B-page 29
LAN7500/LAN7500I
5.0
NETDETACH OPERATION
5.1
NetDetach
NetDetach is a mode of operation where the device detaches from the USB bus after the Ethernet cable is disconnected.
This is advantageous for mobile devices, as an attached USB device may prevent the Host CPU from entering the ACPI
C3 state. Allowing the CPU to enter the C3 state maximizes battery life, as the C3 state is the lowest of the four APCI
power states.
When detached, the device is in a low power state. After the Ethernet cable is reconnected, or a programmed GPIO pin
asserts, the device automatically attaches to the USB bus.
FIGURE 5-1:
LAN7500/LAN7500I DETACH
Ethernet
1
Remove Ethernet Cable
2
USB Electricals Detach
3
Battery-powered Netbook PC
may enter C3 sleep mode
LAN7500/
LAN7500i
...ZZZ
DS00001734B-page 30
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
FIGURE 5-2:
LAN7500/LAN7500I ATTACH
Ethernet
1
Insert Ethernet Cable
2
USB Electricals Attach
3
LAN7500/LAN7500i
enumerates and the driver is
loaded
LAN7500/
LAN7500i
2014-2016 Microchip Technology Inc.
DS00001734B-page 31
LAN7500/LAN7500I
6.0
APPLICATION DIAGRAMS
This section provides typical application diagrams for the following:
• Simplified Application Diagram
• Power Supply & Twisted Pair Interface Diagram
6.1
Simplified Application Diagram
FIGURE 6-1:
SIMPLIFIED APPLICATION DIAGRAM
LAN7500/LAN7500i
USB
Magnetics
USBDM
USBDP
RJ45
TR0P
TR0N
TR1P
EEPROM
TR1N
(optional)
EEDI
EEDO
TR2P
EECS
TR2N
EECLK
TR3P
TR3N
XI
25MHz
Interface
12
GPIO[0:11]/
LED[0:4]
XO
JTAG
SW_MODE
nRESET
VBUS_DET
DS00001734B-page 32
(optional)
TCK
TDO
TDI
TMS
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
6.2
Power Supply & Twisted Pair Interface Diagram
FIGURE 6-2:
POWER SUPPLY & TWISTED PAIR INTERFACE DIAGRAM
LAN7500/LAN7500i
VDD12USBPLL
CBYPASS
VDD12PLL
CBYPASS
Circuitry within the dotted line is for Channel 0.
Duplicate this circuit for Channels 1, 2 and 3.
VDD12BIAS
(x4) VDD12A
CBYPASS
CBYPASS
Magnetics
RJ45
Power
Supply
1.2V
VDD12CORE (x6)
TR0P
CBYPASS
x6
Power
Supply
3.3V
Power
Supply
2.5V – 3.3V
1
2
3
4
5
6
7
8
75
TR0N
VDD33A
CBYPASS
1000 pF
2 kV
0.022uF
49.9
VDDVARIO (x4)
Note: 0.022uF capacitor is optional. In
an EMI constrained environment,
populate this capacitor. The component
must be placed close to the transformer.
CBYPASS
x4
USBRBIAS
ETHRBIAS
8.06K Ohm
1%
2014-2016 Microchip Technology Inc.
49.9
VSS
12.0K Ohm
1%
DS00001734B-page 33
LAN7500/LAN7500I
7.0
OPERATIONAL CHARACTERISTICS
7.1
Absolute Maximum Ratings*
Supply Voltage (VDDVARIO) (Note 7-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Analog Supply Voltage (VDD12A) (Note 7-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +1.5V
Analog USB Supply Voltage (VDD33A) (Note 7-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Digital Core Supply Voltage (VDD12CORE) (Note 7-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +1.5V
Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Positive voltage on signal pins, with respect to ground (Note 7-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0V
Negative voltage on signal pins, with respect to ground (Note 7-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V
Positive voltage on XI, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.6V
Positive voltage on XO, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.5V
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 7-4
Junction to Ambient (JA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24.4ºC/W
Junction to Top of Package (ΨJT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1ºC/W
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55ºC to +150ºC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .JEDEC Class 3A
Latch-up Performance per EIA/JESD 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±150mA
Note 7-1
When powering this device from laboratory or system power supplies, it is important that the absolute
maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp
circuit be used.
Note 7-2
This rating does not apply to the following pins: XI, XO, ETHRBIAS, USBRBIAS.
Note 7-3
This rating does not apply to the following pins: ETHRBIAS, USBRBIAS.
Note 7-4
0ºC to +70ºC for commercial version, -40ºC to +85ºC for industrial version.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 7.2, "Operating Conditions**", Section 7.4,
"DC Specifications", or any other applicable section of this specification is not implied. Note, device signals are NOT 5
volt tolerant unless specified otherwise.
7.2
Operating Conditions**
Supply Voltage (VDDVARIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25V to +3.6V
Supply Voltage (VDD12A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14V to +1.26V
Analog USB Supply Voltage (VDD33A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +3.6V
Digital Core Supply Voltage (VDD12CORE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14V to +1.26V
Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25V to +3.6V
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 7-4
**Proper operation of the device is guaranteed only within the ranges specified in this section. After the device has completed power-up, VDDVARIO and the magnetics power supply must maintain their voltage level with ±10%. Varying the
voltage greater than ±10% after the device has completed power-up can cause errors in device operation.
DS00001734B-page 34
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
7.3
Power Consumption
This section details the power consumption of the device as measured during various modes of operation. For each
mode of operation, two tables are provided: one for operation of VDDVARIO (and magnetics) at 2.5V, and the other for
operation of VDDVARIO (and magnetics) at 3.3V. Power consumption values are provided for both the device-only, and
for the device plus Ethernet components. Power dissipation is determined by temperature, supply voltage, and external
source/sink requirements.
7.3.1
SUSPEND0
7.3.1.1
TABLE 7-1:
VDDVARIO & Magnetics = 2.5V
SUSPEND0 CURRENT & POWER (VDDVARIO & MAGNETICS = 2.5V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDD33A = 3.3V)
0.4
mA
Supply current (VDDVARIO = 2.5V)
3.1
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
453
mA
Power Dissipation (Device Only)
553
mW
Power Dissipation (Device and Ethernet components)
1047
mW
7.3.1.2
TABLE 7-2:
VDDVARIO & Magnetics = 3.3V
SUSPEND0 CURRENT & POWER (VDDVARIO & MAGNETICS = 3.3V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDDVARIO, VDD33A = 3.3V)
3.5
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
453
mA
Power Dissipation (Device Only)
556
mW
Power Dissipation (Device and Ethernet components)
1231
mW
2014-2016 Microchip Technology Inc.
DS00001734B-page 35
LAN7500/LAN7500I
7.3.2
SUSPEND1
7.3.2.1
VDDVARIO & Magnetics = 2.5V
TABLE 7-3:
SUSPEND1 CURRENT & POWER (VDDVARIO & MAGNETICS = 2.5V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDD33A = 3.3V)
0.5
mA
Supply current (VDDVARIO = 2.5V)
0.3
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
35
mA
Power Dissipation (Device Only)
44
mW
Power Dissipation (Device and Ethernet components)
82
mW
7.3.2.2
VDDVARIO & Magnetics = 3.3V
TABLE 7-4:
SUSPEND1 CURRENT & POWER (VDDVARIO & MAGNETICS = 3.3V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDDVARIO, VDD33A = 3.3V)
0.8
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
35
mA
Power Dissipation (Device Only)
44
mW
Power Dissipation (Device and Ethernet components)
114
mW
7.3.3
SUSPEND2 (SELF-POWERED)
7.3.3.1
TABLE 7-5:
VDDVARIO & Magnetics = 2.5V
SUSPEND2 (SELF-POWERED) CURRENT & POWER (VDDVARIO & MAGNETICS =
2.5V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDD33A = 3.3V)
0.5
mA
Supply current (VDDVARIO = 2.5V)
0.2
mA
2.0
mA
Power Dissipation (Device Only)
4.4
mW
Power Dissipation (Device and Ethernet components)
4.5
mW
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
DS00001734B-page 36
n
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
7.3.3.2
VDDVARIO & Magnetics = 3.3V
TABLE 7-6:
SUSPEND2 (SELF-POWERED) CURRENT & POWER (VDDVARIO & MAGNETICS =
3.3V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDDVARIO, VDD33A = 3.3V)
0.7
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
2.0
mA
Power Dissipation (Device Only)
4.6
mW
Power Dissipation (Device and Ethernet components)
4.6
mW
7.3.4
SUSPEND2 (BUS-POWERED)
7.3.4.1
TABLE 7-7:
VDDVARIO & Magnetics = 2.5V
SUSPEND2 (BUS-POWERED) CURRENT & POWER (VDDVARIO & MAGNETICS =
2.5V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDD33A = 3.3V)
0.5
mA
Supply current (VDDVARIO = 2.5V)
0.2
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
1.0
mA
Power Dissipation (Device Only)
3.3
mW
Power Dissipation (Device and Ethernet components)
3.3
mW
7.3.4.2
TABLE 7-8:
VDDVARIO & Magnetics = 3.3V
SUSPEND2 (BUS-POWERED) CURRENT & POWER (VDDVARIO & MAGNETICS =
3.3V)
Parameter
Min
Typical
MAX
Unit
Supply current (VDDVARIO, VDD33A = 3.3V)
0.7
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
1.0
mA
Power Dissipation (Device Only)
3.4
mW
Power Dissipation (Device and Ethernet components)
3.5
mW
2014-2016 Microchip Technology Inc.
DS00001734B-page 37
LAN7500/LAN7500I
7.3.5
OPERATIONAL
7.3.5.1
VDDVARIO & Magnetics = 2.5V
TABLE 7-9:
OPERATIONAL CURRENT & POWER (VDDVARIO & MAGNETICS = 2.5V)
Parameter
Min
Typical
MAX
Unit
1000BASE-T Full Duplex (USB High-Speed)
Supply current (VDD33A = 3.3V)
6.8
mA
Supply current (VDDVARIO = 2.5V)
3.1
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
489
mA
Power Dissipation (Device Only)
617
mW
Power Dissipation (Device and Ethernet components)
1113
mW
Supply current (VDD33A = 3.3V)
6.6
mA
Supply current (VDDVARIO = 2.5V)
0.9
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
119
mA
Power Dissipation (Device Only)
167
mW
Power Dissipation (Device and Ethernet components)
311
mW
Supply current (VDD33A = 3.3V)
5.6
mA
Supply current (VDDVARIO = 2.5V)
0.8
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
66
mA
Power Dissipation (Device Only)
100
mW
Power Dissipation (Device and Ethernet components)
394
mW
100BASE-TX Full Duplex (USB High-Speed)
10BASE-T Full Duplex (USB High-Speed)
7.3.5.2
VDDVARIO & Magnetics = 3.3V
TABLE 7-10:
OPERATIONAL CURRENT & POWER (VDDVARIO & MAGNETICS = 3.3V)
Parameter
Min
Typical
MAX
Unit
1000BASE-T Full Duplex (USB High-Speed)
Supply current (VDDVARIO, VDD33A = 3.3V)
9.8
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
489
mA
Power Dissipation (Device Only)
620
mW
Power Dissipation (Device and Ethernet components)
1296
mW
DS00001734B-page 38
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 7-10:
OPERATIONAL CURRENT & POWER (VDDVARIO & MAGNETICS = 3.3V)
Parameter
Min
Typical
MAX
Unit
100BASE-TX Full Duplex (USB High-Speed)
Supply current (VDDVARIO, VDD33A = 3.3V)
7.5
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
119
mA
Power Dissipation (Device Only)
168
mW
Power Dissipation (Device and Ethernet components)
379
mW
Supply current (VDDVARIO, VDD33A = 3.3V)
6.4
mA
Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL,
VDD12PLL, VDD12A = 1.2V)
66
mA
Power Dissipation (Device Only)
101
mW
Power Dissipation (Device and Ethernet components)
512
mW
10BASE-T Full Duplex (USB High-Speed)
2014-2016 Microchip Technology Inc.
DS00001734B-page 39
LAN7500/LAN7500I
7.4
DC Specifications
TABLE 7-11:
I/O BUFFER CHARACTERISTICS
Parameter
2.5V
TYP
Symbol
Min
Low Input Level
VILI
-0.3
High Input Level
VIHI
Negative-Going Threshold
VILT
0.64
1.15
Positive-Going Threshold
VIHT
0.81
SchmittTrigger Hysteresis
(VIHT - VILT)
VHYS
102
Input Leakage
(VIN = VSS or VDDVARIO)
IIH
-10
Input Capacitance
CIN
3.3V
TYP
MAX
UNITS
NOTES
VIS Type Input Buffer
V
3.6
V
1.41
1.76
V
Schmitt trigger
1.29
1.65
1.90
V
Schmitt trigger
136
138
288
mV
10
uA
3
pF
Note 7-5
IS_5V Type Input Buffer
Low Input Level
VILI
-0.3
N/A
High Input Level
VIHI
Negative-Going Threshold
VILT
1.01
N/A
Positive-Going Threshold
VIHT
1.39
SchmittTrigger Hysteresis
(VIHT - VILT)
VHYS
336
Input Leakage
(VIN = VSS or VDDVARIO)
IIH
-10
Input Leakage
(VIN = 5.5V)
Input Capacitance
V
N/A
5.5
V
1.19
1.39
V
Schmitt trigger
N/A
1.59
1.79
V
Schmitt trigger
N/A
399
459
mV
10
uA
Note 7-5
IIH
35
uA
Note 7-5, Note 7-6
CIN
3
pF
Low Output Level
VOL
0.4
V
IOL = 6mA
High Output Level
VOH
V
IOH = -6mA
VO6 Type Buffers
VDDVARIO
- 0.4
VOD6 Type Buffer
VOL
0.4
V
IOL = 6mA
Low Output Level
VOL
0.4
V
IOL = 8mA
High Output Level
VOH
V
IOH = -8mA
V
IOL = 8mA
Low Output Level
VO8 Type Buffers
VDDVARIO
- 0.4
VOD8 Type Buffer
Low Output Level
VOL
0.4
Note 7-7
ICLK Type Buffer (XI Input)
Low Input Level
VILI
-0.3
0.5
V
High Input Level
VIHI
0.9
3.6
V
DS00001734B-page 40
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
Note 7-5
This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up
resistors add ±50 uA per-pin (typical).
Note 7-6
This is the total 5.5V input leakage for the entire device.
Note 7-7
XI can optionally be driven from a 25 MHz single-ended clock oscillator.
TABLE 7-12:
1000BASE-T TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
Min
Peak Differential Output Voltage
VOP
670
Signal Amplitude Symmetry
Typ
Max
Units
Notes
820
mV
Note 7-8
VSS
1
%
Note 7-8
Signal Scaling
VSC
2
%
Note 7-9
Output Droop
VOD
%
Note 7-8
10
mV
Note 7-10
73.1
Transmission Distortion
Note 7-8
IEEE 802.ab Test Mode 1
Note 7-9
From 1/2 of average VOP, Test Mode 1
Note 7-10
IEEE 802.ab distortion processing
TABLE 7-13:
100BASE-TX TRANSCEIVER CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Peak Differential Output Voltage High
VPPH
950
-
1050
mVpk
Note 7-11
Peak Differential Output Voltage Low
VPPL
-950
-
-1050
mVpk
Note 7-11
Signal Amplitude Symmetry
VSS
98
-
102
%
Note 7-11
Signal Rise and Fall Time
TRF
3.0
-
5.0
nS
Note 7-11
Rise and Fall Symmetry
TRFS
-
-
0.5
nS
Note 7-11
Duty Cycle Distortion
DCD
35
50
65
%
Note 7-12
Overshoot and Undershoot
VOS
-
-
5
%
1.4
nS
Note 7-13
Jitter
Note 7-11
Measured at line side of transformer, line replaced by 100 (±1%) resistor.
Note 7-12
Offset from 16nS pulse width at 50% of pulse peak.
Note 7-13
Measured differentially.
TABLE 7-14:
10BASE-T TRANSCEIVER CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Transmitter Peak Differential Output Voltage
VOUT
2.2
2.5
2.8
V
Note 7-14
Receiver Differential Squelch Threshold
VDS
300
420
585
mV
2014-2016 Microchip Technology Inc.
DS00001734B-page 41
LAN7500/LAN7500I
Note 7-14
7.5
Min/max voltages guaranteed as measured with 100 resistive load.
AC Specifications
This section details the various AC timing specifications of the device.
Note:
The USBDP and USBDM pin timing adheres to the USB 2.0 specification. Refer to the Universal Serial Bus
Revision 2.0 specification for detailed USB timing information.
Note:
The Ethernet TX/RX pin timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for detailed Ethernet timing information.
7.5.1
EQUIVALENT TEST LOAD
Output timing specifications assume the 25pF equivalent test load illustrated in Figure 7-1 below, unless otherwise
specified.
FIGURE 7-1:
OUTPUT EQUIVALENT TEST LOAD
OUTPUT
25 pF
7.5.2
POWER SEQUENCE TIMING
Power supplies must adhere to the following rules:
• All power supplies of the same voltage must be powered up/down together.
• There is no power-up sequencing requirement, however all power supplies must reach operational levels within
the time periods specified in Table 7-15.
• There is no power-down sequencing or timing requirement, however the device must not be powered for an
extended period of time without all supplies at operational levels.
• Following initial power-on, or if a power supply brownout occurs (i.e., one or more supplies drops below operational limits), a power-on reset must be executed once all power supplies reach operational levels. Refer to Section 7.5.3, "Power-On Reset Timing," on page 43 for power-on reset requirements.
• With the exception of VBUS_DET, do not drive input signals without power supplied to the device.
Note:
Violation of these specifications may damage the device.
DS00001734B-page 42
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
FIGURE 7-2:
POWER SEQUENCE TIMING
tpon
All 3.3V Power
Supply Pins
All 2.5V Power
Supply Pins
All 1.2V Power
Supply Pins
TABLE 7-15:
POWER SEQUENCE TIMING VALUES
SYMBOL
tpon
DESCRIPTION
MIN
Power supply turn on time
0
Note:
The VDDVARIO power supply can be run at 2.5V or 3.3V.
Note:
The magnetics power supply can be run at 2.5V or 3.3V.
7.5.3
TYP
MAX
UNITS
25
mS
POWER-ON RESET TIMING
Figure 7-3 illustrates the nRESET timing requirements in relation to power-on. A hardware reset (nRESET assertion) is
required following power-on. For proper operation, nRESET must be asserted for no less than trstia. The nRESET pin
can be asserted at any time, but must not be deasserted before tpurstd after all external power supplies have reached
operational levels.
FIGURE 7-3:
All External
Power Supplies
NRESET POWER-ON TIMING
Vopp
tpurstd
tpurstv
trstia
nRESET
2014-2016 Microchip Technology Inc.
DS00001734B-page 43
LAN7500/LAN7500I
TABLE 7-16:
NRESET POWER-ON TIMING VALUES
SYMBOL
DESCRIPTION
MIN
tpurstd
External power supplies at operational level to nRESET
deassertion
25
mS
tpurstv
External power supplies at operational level to nRESET
valid
0
nS
100
S
nRESET input assertion time
trstia
Note:
7.5.4
TYP
MAX
UNITS
nRESET deassertion must be monotonic.
RESET TIMING
Figure 7-3 illustrates the nRESET pin timing requirements. When used, nRESET must be asserted for no less than trstia.
Note:
A hardware reset (nRESET assertion) is required following power-on. Refer to Section 7.5.3, "Power-On
Reset Timing," on page 43 for additional information.
FIGURE 7-4:
NRESET TIMING
trstia
nRESET
TABLE 7-17:
NRESET TIMING VALUES
SYMBOL
trstia
DESCRIPTION
nRESET input assertion time
DS00001734B-page 44
MIN
1
TYP
MAX
UNITS
S
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
7.5.5
EEPROM TIMING
The following specifies the EEPROM timing requirements for the device:
FIGURE 7-5:
EEPROM TIMING
tcsl
EECS
tcshckh
tckcyc
tckh
tckl
tcklcs
l
EECLK
tckldis
tdvckh tckhinvld
EEDO
tdsckh
tdhckh
EEDI
tdhcsl
tcshdv
EEDI (VERIFY)
TABLE 7-18:
EEPROM TIMING VALUES
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tckcyc
EECLK Cycle time
1110
1130
ns
tckh
EECLK High time
550
570
ns
tckl
EECLK Low time
550
570
ns
tcshckh
EECS high before rising edge of EECLK
1070
ns
tcklcsl
EECLK falling edge to EECS low
30
ns
tdvckh
EEDO valid before rising edge of EECLK
550
ns
EEDO invalid after rising edge EECLK
550
ns
tdsckh
EEDI setup to rising edge of EECLK
90
ns
tdhckh
EEDI hold after rising edge of EECLK
0
ns
tckldis
EECLK low to data disable (OUTPUT)
580
ns
tcshdv
EEDIO valid after EECS high (VERIFY)
tdhcsl
EEDIO hold after EECS low (VERIFY)
tckhinvld
tcsl
EECS low
2014-2016 Microchip Technology Inc.
600
ns
0
ns
1070
ns
DS00001734B-page 45
LAN7500/LAN7500I
7.5.6
JTAG TIMING
This section specifies the JTAG timing of the device. Please refer to Section 1.1.10, "TAP Controller," on page 6 for additional details.
FIGURE 7-6:
JTAG TIMING
ttckp
ttckhl
ttckhl
TCK (Input)
tsu
th
TDI, TMS (Inputs)
tdov
tdoinvld
TDO (Output)
TABLE 7-19:
JTAG TIMING VALUES
Symbol
Description
ttckp
TCK clock period
ttckhl
TCK clock high/low time
Min
Max
66.67
ttckp*0.4
Units
ns
ttckp*0.6
ns
tsu
TDI, TMS setup to TCK rising edge
10
ns
th
TDI, TMS hold from TCK rising edge
10
ns
tdov
tdoinvld
TDO output valid from TCK falling edge
TDO output invalid from TCK falling edge
DS00001734B-page 46
16
0
Notes
ns
ns
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
7.6
Clock Circuit
The device can accept either a 25 MHz crystal (preferred) or a 25 MHz single-ended clock oscillator (±50 ppm) input. If
the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with
a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XI/XO). Either a 300uW or 100uW 25 MHz crystal may be utilized. The 300uW 25 MHz crystal specifications are
detailed in Section 7.6.1, "300uW 25 MHz Crystal Specification," on page 47. The 100uW 25 MHz crystal specifications
are detailed in Section 7.6.2, "100uW 25 MHz Crystal Specification," on page 48.
7.6.1
300UW 25 MHZ CRYSTAL SPECIFICATION
When utilizing a 300uW 25 MHz crystal, the following circuit design (Figure 7-7) and specifications (Table 7-20) are
required to ensure proper operation.
FIGURE 7-7:
300UW 25 MHZ CRYSTAL CIRCUIT
LAN7500
XO
Y1
XI
C2
C1
TABLE 7-20:
300UW 25 MHZ CRYSTAL SPECIFICATIONS
PARAMETER
SYMBOL
MIN
NOM
Crystal Cut
UNITS
NOTES
AT, typ
Crystal Oscillation Mode
Fundamental Mode
Crystal Calibration Mode
Parallel Resonant Mode
Frequency
MAX
Ffund
-
25.000
-
MHz
Frequency Tolerance @ 25ºC
Ftol
-
-
±50
PPM
Note 7-15
Frequency Stability Over Temp
Ftemp
-
-
±50
PPM
Note 7-15
Frequency Deviation Over Time
Fage
-
±3 to 5
-
PPM
Note 7-16
-
-
±50
PPM
Note 7-17
Total Allowable PPM Budget
Shunt Capacitance
CO
-
7 typ
-
pF
Load Capacitance
CL
-
20 typ
-
pF
Drive Level
PW
300
-
-
uW
Equivalent Series Resistance
R1
-
-
50
Ohm
Note 7-18
-
Note 7-19
ºC
LAN7500/LAN7500i XI Pin
Capacitance
-
3 typ
-
pF
Note 7-20
LAN7500/LAN7500i XO Pin
Capacitance
-
3 typ
-
pF
Note 7-20
Operating Temperature Range
2014-2016 Microchip Technology Inc.
DS00001734B-page 47
LAN7500/LAN7500I
Note 7-15
The maximum allowable values for Frequency Tolerance and Frequency Stability are application
dependent. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the
combination of these two values must be approximately ±45 PPM (allowing for aging).
Note 7-16
Frequency Deviation Over Time is also referred to as Aging.
Note 7-17
The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
±50 PPM.
Note 7-18
0ºC for commercial version, -40ºC for industrial version.
Note 7-19
+70ºC for commercial version, +85ºC for industrial version.
Note 7-20
This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included
in this value. The XO/XI pin and PCB capacitance values are required to accurately calculate the
value of the two external load capacitors. These two external load capacitors determine the accuracy
of the 25.000 MHz frequency.
7.6.2
100UW 25 MHZ CRYSTAL SPECIFICATION
When utilizing a 100uW 25 MHz crystal, the following circuit design (Figure 7-8) and specifications (Table 7-21) are
required to ensure proper operation.
FIGURE 7-8:
100UW 25 MHZ CRYSTAL CIRCUIT
LAN7500
XO
RS
Y1
XI
C1
TABLE 7-21:
C2
100UW 25 MHZ CRYSTAL SPECIFICATIONS
Parameter
Symbol
Min
Crystal Cut
Nom
Max
Units
Notes
AT, typ
—
Crystal Oscillation Mode
Fundamental Mode
—
Crystal Calibration Mode
Parallel Resonant Mode
—
Frequency
Ffund
—
25.000
—
MHz
—
Frequency Tolerance @ 25ºC
Ftol
—
—
±50
PPM
Note 7-21
Frequency Stability Over Temp
Ftemp
—
—
±50
PPM
Note 7-21
Frequency Deviation Over Time
Fage
—
±3 to 5
—
PPM
Note 7-22
Total Allowable PPM Budget
—
—
—
±50
PPM
Note 7-23
Shunt Capacitance
CO
—
—
5
pF
—
Load Capacitance
CL
8
—
12
pF
—
Drive Level
PW
—
100
—
uW
Note 7-24
DS00001734B-page 48
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
TABLE 7-21:
100UW 25 MHZ CRYSTAL SPECIFICATIONS (CONTINUED)
Parameter
Symbol
Min
Nom
Max
Units
Notes
Equivalent Series Resistance
R1
—
—
80
Ohm
—
LAN7500/LAN7500i XO Series
Resistor
Rs
495
500
505
Ohm
—
Operating Temperature Range
—
Note 7-25
—
Note 7-26
ºC
—
LAN7500/LAN7500i XI Pin
Capacitance
—
—
3 typ
—
pF
Note 7-27
LAN7500/LAN7500i XO Pin
Capacitance
—
—
3 typ
—
pF
Note 7-27
Note 7-21
The maximum allowable values for Frequency Tolerance and Frequency Stability are application
dependent. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the
combination of these two values must be approximately ±45 PPM (allowing for aging).
Note 7-22
Frequency Deviation Over Time is also referred to as Aging.
Note 7-23
The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
±100 PPM.
Note 7-24
The crystal must support 100uW operation to utilize this circuit.
Note 7-25
0ºC for extended commercial version, -40ºC for industrial version.
Note 7-26
70ºC for commercial version, +85ºC for industrial version.
Note 7-27
This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included
in this value. The XI pin, XO pin and PCB capacitance values are required to accurately calculate
the value of the two external load capacitors. The total load capacitance must be equivalent to what
the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 MHz.
2014-2016 Microchip Technology Inc.
DS00001734B-page 49
LAN7500/LAN7500I
8.0
PACKAGE OUTLINE
LAN7500/LAN7500I 56-QFN PACKAGE
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 8-1:
DS00001734B-page 50
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
LAN7500/LAN7500I 56-QFN RECOMMENDED PCB LAND PATTERN
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 8-2:
2014-2016 Microchip Technology Inc.
DS00001734B-page 51
LAN7500/LAN7500I
APPENDIX A:
TABLE 8-1:
REVISION HISTORY
REVISION HISTORY
Revision Level and
Date
DS00001374B
(07-22-16)
Section/Figure/Entry
Correction
All
Document converted to Microchip look and feel.
Section 7.2, "Operating Conditions**," on page 34
XTAL1 Absolute Maximum input voltage level
reduced to 3.6V.
Table 7-11, “I/O Buffer Characteristics,” on page 40
XTAL1 High-Level Input voltage maximum reduced
to 3.6V. XTAL1 Minimum Input High level reduced
to 0.9V
Section 7.6, "Clock Circuit," on
page 47
Updated to add Section 7.6.2, "100uW 25 MHz
Crystal Specification," on page 48.
Section 7.6.1, "300uW 25 MHz
Crystal Specification," on page 47
Updated to add Figure 7-7.
DS00001734A replaces the previous SMSC version, rev. 1.0
Rev. 1.0
(11-01-10)
DS00001734B-page 52
All
Initial Release.
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
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To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support
2014-2016 Microchip Technology Inc.
DS00001734B-page 53
LAN7500/LAN7500I
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
[X]
-
Temperature
Range
Device:
LAN7500
Temperature
Range:
Blank
i
Package:
ABZJ =
Tape and Reel
Option:
Blank
XXX
-
Package
[X](1)
Tape and Reel
Option
Examples:
a)
b)
=
0C to
= -40C to
+70C
+85C
LAN7500i-ABZJ
Industrial temperature,
56-pin QFN
Tray
LAN7500-ABZJ
Extended commercial temperature,
56-pin QFN
Tray
(Extended Commercial)
(Industrial)
56-pin QFN RoHS compliant package
= Standard packaging (tray)
Note:
DS00001734B-page 54
This product meets the halogen maximum
concentration
values
per
IEC61249-2-21
2014-2016 Microchip Technology Inc.
LAN7500/LAN7500I
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,
Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2014-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0797-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2014-2016 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00001734B-page 55
Worldwide Sales and Service
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Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
06/23/16
DS00001734B-page 56
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