LAN7850
Hi-Speed USB 2.0 to 10/100/1000
Ethernet Controller with HSIC
Highlights
• Single Chip Hi-Speed (HS) USB 2.0 to 10/100/
1000 Ethernet Controller
- Integrated Gigabit PHY with HP Auto-MDIX
- Integrated 10/100/1000 Ethernet MAC
(Full-Duplex Support)
- Integrated USB 2.0 Device Controller
- Integrated USB PHY
• Low Power Consumption
- Compliant with Energy Efficient Ethernet
IEEE 802.3az
- Wake on LAN support (WoL)
• Configuration via One Time Programmable (OTP)
Memory
• NetDetach provides automatic USB attach/detach
when Ethernet cable is connected/removed
Target Applications
•
•
•
•
•
•
•
•
Automotive Infotainment
Notebook/Tablet Docking Stations
Detachable Laptops
USB Port Replicators
Standalone USB to Ethernet Dongles
Embedded Systems / CE Devices
Set-Top Boxes / Video Recorders
Test Instrumentation / Industrial
System Considerations
• Power and I/Os
-
Multiple power management features
12 GPIOs
Supports bus and self-powered operation
Variable voltage I/O supply (1.8V-3.3V)
• Software Support
-
Windows 7, 8, 8.1, and 10 drivers (Microsoft Certified)
Linux driver
OS X and macOS driver
uBoot support
UEFI support
PXE support
FreeBSD support
Windows OTP/EEPROM programming
and testing utility
• Environmental
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
Key Benefits
• USB 2.0 Device Controller
- Supports HS (480 Mbps), and
FS (12 Mbps) modes
- Four endpoints supported
- Supports vendor specific commands
- Remote wakeup supported
- Integrated HSIC interface
• 10/100/1000 Ethernet Controller
- Compliant with IEEE802.3/802.3u/802.3ab/802.3az
-10BASE-T/100BASE-TX/1000BASE-T support
-Full- and half-duplex capability
(only full-duplex operation at 1000 Mbps)
- Controller Modes
-Microsoft AOAC support
(Always On Always Connected)
-Supports Microsoft NDIS 6.2 large send offload
-Full-duplex flow control
-Loop-back modes
-Supports IEEE 802.1q VLAN tagging
-VLAN tag based packet filtering (all 4096 tags)
-Flexible address filtering modes
-33 exact matches (unicast or multicast)
-512-bit hash filter for multicast frames
-Pass all multicast
-Promiscuous unicast/multicast modes
-Inverse filtering
-Pass all incoming with status report
-Supports various statistical counters
-PME pin support
- Frame Features
-Supports 32 wake-up frame patterns
-Preamble generation and removal
-Automatic 32-bit CRC generation and checking
-9 KB jumbo frame support
-Automatic payload padding and pad removal
-Supports Rx/Tx checksum offloads
(IPv4, IPv6, TCP, UDP, IGMP, ICMP)
-Ability to add and strip IEEE 802.1q VLAN tags
• Packaging
- RoHS compliant 56-pin SQFN (8 x 8 mm)
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 1
LAN7850
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DS00001993F-page 2
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 9
3.0 Pin Descriptions and Configuration ............................................................................................................................................... 10
4.0 Power Connections ....................................................................................................................................................................... 16
5.0 USB Device Controller .................................................................................................................................................................. 17
6.0 FIFO Controller (FCT) ................................................................................................................................................................... 42
7.0 Receive Filtering Engine (RFE) .................................................................................................................................................... 59
8.0 10/100/1000 Ethernet MAC .......................................................................................................................................................... 74
9.0 Gigabit Ethernet PHY (GPHY) ...................................................................................................................................................... 90
10.0 EEPROM Controller (EEP) ......................................................................................................................................................... 97
11.0 One Time Programmable (OTP) Memory ................................................................................................................................. 120
12.0 Resets ....................................................................................................................................................................................... 121
13.0 Clocks and Power Management (CPM) .................................................................................................................................... 124
14.0 Power Management Event (PME) Operation ............................................................................................................................ 134
15.0 Register Descriptions ................................................................................................................................................................ 138
16.0 Operational Characteristics ....................................................................................................................................................... 258
17.0 Package Information ................................................................................................................................................................. 266
18.0 Data Sheet Revision History ..................................................................................................................................................... 269
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 3
LAN7850
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
10BASE-T
10 Mbps Ethernet, IEEE 802.3 compliant
100BASE-TX
100 Mbps Fast Ethernet, IEEE802.3u compliant
1000BASE-T
100 Mbps Fast Ethernet, IEEE802.3ab compliant
ADC
Analog-to-Digital Converter
AFE
Analog Front End
ALR
Address Logic Resolution
AN
Auto-Negotiation
AOAC
Always on Always Connected
ARP
Address Resolution Protocol
BELT
Best Effort Latency Tolerance
BLW
Baseline Wander
Byte
8 bits
CPM
Clocks and Power Management
CSMA/CD
Carrier Sense Multiple Access/Collision Detect
CSR
Control and Status Registers
CTR
Counter
DA
Destination Address
DWORD
32 bits
EC
Embedded Controller
EEE
Energy Efficient Ethernet
EP
USB Endpoint
EPC
EEPROM Controller
FCS
Frame Check Sequence - The extra checksum characters added to the end of an
Ethernet frame, used for error detection and correction.
FCT
FIFO Controller
FIFO
First In First Out buffer
FS
Full Speed
FSM
Finite State Machine
FW
Firmware
GMII
Gigabit Media Independent Interface
GPIO
General Purpose I/O
GPHY
Gigabit Ethernet Physical Layer
Host
External system (Includes processor, application software, etc.)
HS
High Speed
HW
Hardware. Refers to function implemented by digital logic.
IGMP
Internet Group Management Protocol
Inbound
Refers to data input to the device from the host
LDO
Linear Drop-Out Regulator
Level-Triggered Sticky Bit
This type of status bit is set whenever the condition that it represents is asserted. The
bit remains set until the condition is no longer true and the status bit is cleared by writing a zero.
DS00001993F-page 4
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
TABLE 1-1:
GENERAL TERMS (CONTINUED)
Term
Description
LFPS
Low Frequency Periodic Signal
LFSR
Linear Feedback Shift Register
LPM
Link Power Management
lsb
Least Significant Bit
LSB
Least Significant Byte
LTM
Latency Tolerance Messaging
MAC
Media Access Controller
MDI
Medium Dependent Interface
MDIX
Media Dependent Interface with Crossover
MEF
Multiple Ethernet Frames
MII
Media Independent Interface
MIIM
Media Independent Interface Management
MIL
MAC Interface Layer
MLD
Multicast Listening Discovery
MLT-3
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a
change in the logic level represents a code bit “1” and the logic output remaining at the
same level represents a code bit “0”.
msb
Most Significant Bit
MSB
Most Significant Byte
NRZI
Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and
leaves the signal unchanged for a “0”
N/A
Not Applicable
NC
No Connect
OTP
One Time Programmable
OUI
Organizationally Unique Identifier
Outbound
Refers to data output from the device to the host
PCS
Physical Coding Sublayer
PHY
Physical Layer
PISO
Parallel In Serial Out
PLL
Phase Locked Loop
PMD
Physical Medium Dependent
PME
Power Management Event
PMIC
Power Management IC
POR
Power on Reset
PTP
Precision Time Protocol
QWORD
64 bits
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
RFE
Receive Filtering Engine
RGMII
Reduced Gigabit Media Independent Interface
RMON
Remote Monitoring
RMII
Reduced Media Independent Interface
RST
Reset
RTC
Real-Time Clock
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 5
LAN7850
TABLE 1-1:
GENERAL TERMS (CONTINUED)
Term
Description
SA
Source Address
SCSR
System Control and Status Registers
SEF
Single Ethernet Frame
SFD
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an
Ethernet frame.
SIPO
Serial In Parallel Out
SMI
Serial Management Interface
SMNP
Simple Network Management Protocol
SQE
Signal Quality Error (also known as “heartbeat”)
SSD
Start of Stream Delimiter
TMII
Turbo Media Independent Interface
UDP
User Datagram Protocol - A connectionless protocol run on top of IP networks
URX
USB Bulk-Out Receiver
USB
Universal Serial Bus
UTX
USB Bulk-In Transmitter
UUID
Universally Unique IDentifier
VSM
Vendor Specific Messaging
WORD
16 bits
ZLP
Zero Length USB Packet
DS00001993F-page 6
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
1.2
Buffer Types
TABLE 1-2:
BUFFER TYPES
Buffer Type
Description
VIS
Variable voltage Schmitt-triggered input
O8
Output with 8 mA sink and 8 mA source
OD8
Open-drain output with 8 mA sink
O12
Output with 12 mA sink and 12 mA source
OD12
Open-drain output with 12 mA sink
HSIC
High-Speed Inter-Chip (HSIC) USB Electrical Specification compliant input/output
PU
50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Note:
PD
50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note:
AI
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a
load that must be pulled high, an external resistor must be added.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
Analog Input
AIO
Analog bidirectional
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
P
Power pin
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 7
LAN7850
1.3
Register Nomenclature
TABLE 1-3:
REGISTER NOMENCLATURE
Register Bit Type Notation
Register Bit Description
R
Read: A register or bit with this attribute can be read.
W
Write: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
RS
Read to Set: This bit is set on read.
RC
Read to Clear: Contents is cleared after the read. Writes have no effect.
WO
Write only: If a register or bit is write-only, reads will return unspecified data.
WC
Write One to Clear: Writing a one clears the value. Writing a zero has no effect
WAC
Write Anything to Clear: Writing anything clears the value.
LL
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
SS
Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
RO/LH
Read Only, Latch High: This mode is used by the Ethernet PHY registers. Bits with
this attribute will stay high until the bit is read. After it is read, the bit will remain high,
but will change to low if the condition that caused the bit to go high is removed. If the
bit has not been read, the bit will remain high regardless of a change to the high condition.
NALR
Not Affected by Lite Reset. The state of NASR bits do not change on assertion of a
lite reset.
NASR
Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. The value of reserved bits is not guaranteed on a
read.
DS00001993F-page 8
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
2.0
INTRODUCTION
2.1
General Description
The LAN7850 is a high performance Hi-SpeedUSB 2.0 to 10/100/1000 Ethernet controller with an integrated 10/100/
1000 Ethernet PHY and High-Speed Inter-Connect (HSIC) interface. With applications ranging from notebook/tablet
docking stations, set-top boxes, and PVRs, to USB port replicators, USB to Ethernet dongles, embedded systems, and
test instrumentation, the LAN7850 is a high performance and cost effective USB/HSIC to Ethernet connectivity solution.
The LAN7850 contains an integrated 10/100/1000 Ethernet MAC and PHY, Filtering Engine, USB PHY (with HSIC interface), Hi-Speed USB 2.0 device controller, TAP controller, EEPROM controller, and a FIFO controller with internal
packet buffering.
The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed standard. The LAN7850
implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is compliant with the
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab, and 802.3az (Energy Efficient Ethernet) standards. ARP and NS offload are
also supported.
Multiple power management features are provided, including Energy Efficient Ethernet (IEEE 802.3az), support for Microsoft’s Always On Always Connected (AOAC), and “Magic Packet”, “Wake On LAN”, and “Link Status Change” wake
events. Wake events can be programmed to initiate a USB remote wakeup. Up to 32 different AOAC wake-up frame
patterns are supported along with Microsoft’s WPD (Whole Packet Detection).
An internal EEPROM controller exists to load various USB and Ethernet configuration parameters. For EEPROM-less
applications, the LAN7850 provides 1K Bytes of OTP memory that can be used to preload this same configuration data
before enumeration. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
The LAN7850 is available in commercial and industrial temperature range versions. An internal block diagram of the
LAN7850 is shown in Figure 2-1.
FIGURE 2-1:
USB
HSIC
JTAG
INTERNAL BLOCK DIAGRAM
USB
PHY
HSIC
Interface
USB 2.0
Device
Controller
TAP
Controller
FIFO
Controller
SRAM
10/100/
1000
Ethernet
MAC
OTP
Ethernet
PHY
EEPROM
Controller
Ethernet
EEPROM
LAN7850
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 9
LAN7850
3.0
PIN DESCRIPTIONS AND CONFIGURATION
3.1
Pin Assignments
FIGURE 3-1:
PIN ASSIGNMENTS (TOP VIEW)
TR0P
1
42
VDDVARIO
TR0N
2
41
RESET_N/PME_CLEAR
VDD25A
3
40
TEST
TR1P
4
39
PME_N
TR1N
5
38
DATA
VDD25A
6
37
USB_DM
TR2P
7
36
USB_DP
TR2N
8
35
STROBE
VDD25A
9
34
VDD12HSIC
TR3P
10
33
VDD12A
11
32
PME_MODE/GPIO8
31
LED0/GPIO7
30
HSIC_SEL
29
CONNECT/GPIO6
TR3N
VDD25A
12
VDDVARIO
13
TDI
14
LAN7850
56-SQFN
( To p V i ew )
VSS
(Connect exposed pad to ground with a via field)
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.
Note:
When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example,
RESET_N indicates that the reset signal is active low.
The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Section 3.2, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".
DS00001993F-page 10
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
TABLE 3-1:
PIN ASSIGNMENTS
Pin Number
Pin Name
Pin Number
Pin Name
1
TR0P
29
CONNECT/GPIO6
2
TR0N
30
HSIC_SEL
3
VDD25A
31
LED0/GPIO7
4
TR1P
32
PME_MODE/GPIO8
5
TR1N
33
VDD12A
6
VDD25A
34
VDD12HSIC
STROBE
7
TR2P
35
8
TR2N
36
USB_DP
9
VDD25A
37
USB_DM
10
TR3P
38
DATA
11
TR3N
39
PME_N
12
VDD25A
40
TEST
13
VDDVARIO
41
RESET_N/PME_CLEAR
14
TDI
42
VDDVARIO
15
TDO
43
USBRBIAS
16
TCK/GPIO0
44
VDD33A
17
TMS
45
VDDVARIO
18
VDD12_SW_OUT
46
XI
19
VDD_SW_IN
47
XO
20
VDD12_SW_FB
48
VDD12CORE
21
EECS/GPIO1
49
LED1/GPIO9
22
EEDI/GPIO2
50
LED2/GPIO10
23
EEDO/GPIO3
51
LED3/GPIO11
24
EECLK/GPIO4
52
VDD12A
25
VDDVARIO
53
VDD25_REG_OUT
26
VDD12CORE
54
VDD33_REG_IN
27
VBUS_DET
55
REF_REXT
28
SUSPEND_N/GPIO5
56
REF_FILT
Exposed Pad (VSS) must be connected to ground
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 11
LAN7850
3.2
Pin Descriptions
TABLE 3-2:
PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
Description
Gigabit Ethernet Pins
Ethernet TX/RX
Positive Channel 0
TR0P
AIO
Transmit/Receive Positive Channel 0.
Ethernet TX/RX
Negative Channel 0
TR0N
AIO
Transmit/Receive Negative Channel 0.
Ethernet TX/RX
Positive Channel 1
TR1P
AIO
Transmit/Receive Positive Channel 1.
Ethernet TX/RX
Negative Channel 1
TR1N
AIO
Transmit/Receive Negative Channel 1.
Ethernet TX/RX
Positive Channel 2
TR2P
AIO
Transmit/Receive Positive Channel 2.
Ethernet TX/RX
Negative Channel 2
TR2N
AIO
Transmit/Receive Negative Channel 2.
Ethernet TX/RX
Positive Channel 3
TR3P
AIO
Transmit/Receive Positive Channel 3.
Ethernet TX/RX
Negative Channel 3
TR3N
AIO
Transmit/Receive Negative Channel 3.
External PHY
Reference Filter
REF_FILT
AI
External PHY Reference Filter. Connect to an external 1uF
capacitor to ground.
External PHY
Reference Resistor
REF_REXT
AI
External PHY Reference Resistor. Connect to an external 2K
1.0% resistor to ground.
USB 2.0
DPLUS
USB_DP
AIO
Hi-Speed USB data plus.
USB 2.0
DMINUS
USB_DM
AIO
Hi-Speed USB Speed data minus.
External USB
Bias Resistor
USBRBIAS
AI
HSIC STROBE
STROBE
HSIC
Bi-directional data strobe signal as defined in the HighSpeed Inter-Chip USB Electrical Specification.
HSIC DATA
DATA
HSIC
Bi-directional Double Data Rate (DDR) data signal that is
synchronous to the STROBE signal as defined in the HighSpeed Inter-Chip USB Electrical Specification.
USB Pins
Used for setting HS transmit current level and on-chip termination impedance. Connect to an external 12K 1.0% resistor
to ground.
Miscellaneous Pins
Detect Upstream
VBUS Power
VBUS_DET
VIS
(PD)
Detects the state of the upstream bus power.
For bus powered operation, this pin must be tied to VDD33A.
Refer to Section 4.0, "Power Connections" for additional
information.
USB Connect
CONNECT
O12
This pin asserts when the device is attempting to attach to
the USB host.
This pin is intended to help address a known bug on existing
HSIC host controllers where the HSIC connect signaling is
missed.
DS00001993F-page 12
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
TABLE 3-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
HSIC Select
HSIC_SEL
VIS
Description
When tied to VDD, the device HSIC interface is enabled.
Otherwise, the USB 2.0 interface is enabled.
Note:
This is a static signal that may not be changed at
run time.
PME
PME_N
O8/OD8
This pin is used to signal PME when the PME mode of operation is in effect.
PME Mode Select
PME_MODE
VIS
This pin serves as the PME mode selection input when the
PME mode of operation is in effect.
PME Clear
PME_CLEAR
VIS
This pin may serves as PME clear input when the PME
mode of operation is in effect.
USB Suspend
SUSPEND_N
O12
This pin is asserted when the device is in one of the suspend
states as defined in Section 13.3, "Suspend States".
This pin may be configured to place an external switcher into
a low power state such as when the device is in SUSPEND2.
General Purpose
I/O 0-11
GPIO[0:11]
VIS/O8/
OD8
(PU)
Indicator LEDs 0-3
LED[0:3]
OD12
System Reset
RESET_N
VIS
These general purpose I/O pins are each fully programmable
as either a push-pull output, an open-drain output, or a
Schmitt-triggered input. A programmable pull-up may optionally be enabled.
These LEDs can be configured to indicate Ethernet link,
activity, duplex, and collision. Refer to Section 9.3, "LED
Interface," on page 92 for additional information.
System reset. This pin is active low.
If this signal is unused it must be pulled-up to VDD.
Test Pin
TEST
VIS
Active high test pin. JTAG test mode is selected when the
TEST pin is asserted. For proper functional operation this pin
should be connected to ground.
EEPROM
Chip Select
EECS
O12
This pin drives the chip select output of the external
EEPROM.
EEPROM Data In
EEDI
VIS
This pin is driven by the EEDO output of the external
EEPROM.
EEPROM Data Out
EEDO
O12
This pin drives the EEDI input of the external EEPROM.
EEPROM Clock
EECLK
O12
This pin drives the EEPROM clock of the external EEPROM.
JTAG
Test Mode Select
TMS
VIS
JTAG test mode select.
JTAG
Test Clock
TCK
VIS
JTAG test clock.
EEPROM
JTAG
The maximum operating frequency of this clock is half of the
system clock.
JTAG
Test Data Input
TDI
VIS
JTAG data input.
JTAG
Test Data Output
TDO
O12
JTAG data output.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 13
LAN7850
TABLE 3-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Crystal Input
XI
ICLK
Description
Clock Interface
External 25 MHz crystal input.
Note:
Crystal Output
XO
Variable I/O Power
Supply Input
VDDVARIO
OCLK
This pin can also be driven by a single-ended
clock oscillator. When this method is used, XO
should be left unconnected.
External 25 MHz crystal output.
I/O Power pins, Core Power Pins, and Ground Pad
P
+1.8V - +3.3V variable supply for I/Os.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+3.3V Analog
Power Supply Input
VDD33A
P
+3.3V analog power supply for USB 2.0 AFE.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+2.5V Analog
Power Supply Input
VDD25A
P
+2.5V analog power supply input for Gigabit Ethernet PHY.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+1.2V Ethernet Port
Power Supply Input
VDD12A
P
+1.2V analog power supply input for USB PLL/AFE.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+1.2V Digital Core
Power Supply Input
VDD12CORE
P
+1.2V digital core power supply input.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+1.2V HSIC Power
Supply Input
VDD12HSIC
P
+1.2V HSIC power supply input.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+3.3V LDO Input
Voltage
VDD33_REG_IN
P
+3.3V power supply input to the integrated LDO.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
+2.5V LDO Output
VDD25_REG_OUT
P
+2.5V power supply output from the integrated LDO. This is
used to supply power to Gigabit Ethernet PHY AFE.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
Switcher Input
Voltage
VDD_SW_IN
P
+3.3V input voltage for switching regulator.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
Switcher Feedback
VDD12_SW_FB
P
Feedback pin for the integrated switching regulator.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
Note:
DS00001993F-page 14
To disable the
VDD_SW_IN.
switcher,
tie
this
pin
to
2021 Microchip Technology Inc. and its subsidiaries
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TABLE 3-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
+1.2V Switcher
Output Voltage
VDD12_SW_OUT
P
Description
+1.2V power supply output voltage for switching regulator.
Refer to Section 4.0, "Power Connections," on page 16 for
connection information.
Ground
VSS
2021 Microchip Technology Inc. and its subsidiaries
P
Common Ground
DS00001993F-page 15
LAN7850
4.0
POWER CONNECTIONS
Figure 4-1 illustrates the device power connections in a typical application. Refer to the device reference schematic for
additional information. Refer to Section 3.0, "Pin Descriptions and Configuration," on page 10 for additional pin information.
FIGURE 4-1:
POWER CONNECTION DIAGRAM
+1.8 V to
+3.3 V
VDDVARIO
I/O Pads
+1.2V Core Logic
VDDVARIO
VDD12CORE
VDD12CORE
VDDVARIO
VDDVARIO
VDD12HSIC
USB PLL/AFE
VDD12A
+3.3 V
VDD33A
VDD_SW_IN
USB Common
Block
+1.2 V Switching
Regulator
+3.3 V
+1.2 V
(IN)
(OUT)
feedback
3.3 uH
VDD12_SW_OUT
VDD12_SW_FB
10 uF
Gigabit Ethernet
PHY
VDD12A
VDD25A
VDD25A
VDD25A
+2.5 V LDO
Regulator
VDD33_REG_IN
12kOhm
2kOhm
+3.3 V
(IN)
VDD25A
+2.5 V
(OUT)
VDD25_REG_OUT
USBRBIAS
1 uF
REF_REXT
1uF
REF_FILT
VSS
(exposed pad )
Note: Bypass and bulk caps as needed for PCB
Note:
For 3.3V I/O operation, the VDDVARIO and +3.3V supplies may be connected together.
To disable the internal switcher, tie the VDD12_SW_FB pin to 3.30V and ensure that all VDD12 rails are
connected to an external 1.20V supply.
DS00001993F-page 16
2021 Microchip Technology Inc. and its subsidiaries
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5.0
USB DEVICE CONTROLLER
5.1
Overview
The USB functionality consists of five major parts. The USB PHY, UDC (USB Device Controller), URX (USB Bulk Out
Receiver), UTX (USB Bulk In Transmitter), and CTL (USB Control Block).
The UDC is configured to support one configuration, one interface, one alternate setting, and four endpoints. Streams
are not supported in this device. The URX and UTX implement the Bulk-Out and Bulk-In endpoints respectively. The
CTL manages Control and Interrupt endpoints.
Each USB Controller endpoint is unidirectional with even numbered endpoints handling the OUT (from the host, actually
RX into the device) direction and odd numbered endpoints handling the IN (to the host, actually TX from the device)
direction.
The UDC endpoint numbers start at 0 and increment. Endpoint numbers are not skipped and have a fixed mapping to
the USB endpoint numbers. The corresponding USB endpoint is obtained by dividing the UDC endpoint number by 2
(rounding down). For example, single directional endpoint 0 indicates USB OUT endpoint 0, and single directional endpoint 1 corresponds to USB IN endpoint 0.
The mapping of the device’s USB endpoints to the UDC endpoints is shown in Table 5-1. As can be seen, one IN and
two OUT endpoints on the UDC are not utilized.
TABLE 5-1:
DEVICE TO UDC ENDPOINT MAPPING
Endpoint Function
USB EP Number
Control OUT
Control IN
0
0
unused
NA
Bulk IN
1
Bulk OUT
2
unused
NA
unused
NA
Interrupt IN
5.2
3
Control Endpoint
The Control endpoint is handled by the CTL (USB Control) module. The CTL module is responsible for handling standard USB requests, as well as USB vendor commands. The UDC does not handle USB commands. These commands
are passed to the CTL for completion.
5.2.1
USB STANDARD COMMAND PROCESSING
This section lists the supported USB standard device requests. The basic format of a device request is shown in section
9.3 of the USB 2.0 specification and the standard device requests are described in section 9.4. Valid values of the
parameters are given below.
Per the USB specifications, if an unsupported or invalid request is made to a USB device, the device responds by returning STALL in the Data or Status stage of the request. Receipt of an unsupported or invalid request does NOT cause the
optional Halt feature on the control pipe to be set.
For each request supported, the USB specifications provide details on the device behavior during the various configuration states and on the conditions which will return a Request Error. Some requests affect the state of the hardware.
In order to implement the Get Descriptor command, the CTL manages a 128x32 Descriptor RAM. The RAMs contents
are initialized via the EEPROM or OTP, after a system reset occurs. The Descriptor RAM may also be programmed by
the device driver to support EEPROM-Less mode.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 17
LAN7850
TABLE 5-2:
STRING DESCRIPTOR INDEX MAPPINGS
INDEX
STRING NAME
0
Language ID
1
Manufacturer ID
2
Product ID
3
Serial Number
4
Configuration String
5
Interface String
When the UDC decodes a Get Descriptor command, it will pass a pointer to the CTL. The CTL uses this pointer to determine what the command is and how to fill it.
5.2.1.1
Clear Feature
bmRequestType - 00h for the device, 01h for interfaces and 02h for endpoints.
wValue - Specifies the feature, 1=Device_Remote_Wakeup and 0=Endpoint_Halt.
wIndex - Always 0 when the device is selected, specifies the interface number (always 0) when an interface is selected
or the direction/endpoint number (0, 80h, 81h, 2 or 83h) when an endpoint is selected.
A ClearFeature(Endpoint_Halt) request will clear the USB 2.0 data toggle for the specified endpoint.
5.2.1.2
Get Configuration
All parameters are fixed per the USB specifications.
5.2.1.3
Get Descriptor
wValue - The high byte selects the descriptor type. The supported descriptors for this command are 1=Device, 2=Configuration (including Interface, Endpoint descriptors and Endpoint Companion descriptors (USB 2.1 LPM)), 3=String,
6=Device Qualifier (HS/FS), 7=Other Speed Configuration (USB2.0). The low byte selects the descriptor index and must
be 0.
Note:
Direct access to the Interface, Endpoint and Endpoint Companion (USB 2.1 LPM) descriptors are not supported by this command and will cause a USB stall.
wIndex - Specifies the Language ID for string descriptors or is 0 for other descriptors.
wLength - Specifies the number of bytes to return. If the descriptor is longer than the wLength field, only the initial bytes
of the descriptor are returned. If the descriptor is shorter than the wLength field, the device indicates the end of the control transfer by sending a short packet when further data is requested. A short packet is defined as a packet shorter than
the maximum payload size or a zero length data packet.
5.2.1.4
Get Interface
wIndex - Specifies the interface, always 0 for this device.
5.2.1.5
Get Status
bmRequestType - 00h for the device, 01h for interfaces and 02h for endpoints.
wIndex - Always 0 when the device is selected, specifies the interface number (always 0) when an interface is selected
or the direction/endpoint number (0, 80h, 81h, 2 or 83h) when an endpoint is selected.
Note:
5.2.1.6
Power Method (PWR_SEL) in Hardware Configuration Register (HW_CFG) is used as the source for the
Self-Power bit (D0).
Set Address
wValue - Specifies the new device address.
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2021 Microchip Technology Inc. and its subsidiaries
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Per the USB specification, the USB device does not change its device address until after the Status stage of this request
is completed successfully. This is a difference between this request and all other requests. For all other requests, the
operation indicated must be completed before the Status stage.
5.2.1.7
Set Configuration
wValue - The lower byte specifies the configuration value.
The device supports only one configuration. A value of 1 places the device into the Configured state while a value of 0
places the device into the Address state.
The Halt feature is reset for all endpoints upon the receipt of this request with a valid configuration value.
The USB 2.0 data toggle for all endpoints are initialized upon the receipt of this request with a valid configuration value.
5.2.1.8
Set Descriptor
This optional request is not supported and the device responds by returning STALL.
5.2.1.9
Set Feature
bmRequestType - 00h for the device, 01h for interfaces and 02h for endpoints.
wValue - Specifies the feature, 1=Device_Remote_Wakeup, 2=device Test_Mode, 0=Endpoint_Halt.
Note:
Endpoint_Halt is not implemented for Endpoint 0.
wIndex - Specifies the interface number (always 0) when an interface is selected or the direction/endpoint number (81h,
2 or 83h) when an endpoint is selected. When the device is selected, this field is always 0 unless device Test_Mode is
selected via wValue, in which case the upper byte is the Test Selector and the lower byte a 0.
5.2.1.10
Set Interface
wValue - Specifies the alternate setting (must be 0).
wIndex - Specifies the interface (always 0).
Only one interface with one setting is supported by the device. If the command is issued with an
interface other than 00h, the device responds with a Request Error. If the command is issued with an
interface setting of 00h but with an alternative setting other than 00h, the device responds with a
STALL.
The Halt feature is reset for all endpoints upon the receipt of this request with valid interface and
alternate setting values.
The USB 2.0 data toggle for all endpoints are initialized upon the receipt of this request with valid
interface and alternate setting values.
5.2.1.11
Set Isochronous Delay
This command is not supported. The device will respond with a Stall to this request.
5.2.1.12
Set SEL
This command is not supported. The device will respond with a Stall to this request.
5.2.1.13
Sync Frame
There are no isochronous endpoints in this device. The device will respond with a Stall to this request.
5.2.2
USB VENDOR COMMANDS
The device implements several vendor specific commands in order to directly access CSRs and efficiently gather statistics. The memory map utilized by the address field is defined in Table 15-1, “Memory Map,” on page 138.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 19
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5.2.2.1
Write Command
This command allows the Host to write a memory location. Burst writes are not supported. All writes are 32-bits.
TABLE 5-3:
FORMAT OF WRITE SETUP STAGE
Offset
Field
Value
0h
bmRequestType
40h
1h
bRequest
A0h
2h
wValue
00h
4h
wIndex
{Address[12:0]}
6h
wLength
TABLE 5-4:
FORMAT OF WRITE DATA STAGE
Offset
0h
04h
Field
Register Write Data [31:0]
5.2.2.2
Read Command
This command allows the Host to read a memory location. Burst reads are not supported. All reads return 32-bits.
TABLE 5-5:
FORMAT OF READ SETUP STAGE
Offset
Field
0h
bmRequestType
C0h
1h
bRequest
A1h
2h
wValue
00h
4h
wIndex
{Address[12:0]}
6h
wLength
TABLE 5-6:
5.2.2.3
04h
FORMAT OF READ DATA STAGE
Offset
0h
Value
Field
Register Read Data [31:0]
Get Statistics Command
The Get Statistics Command returns the entire contents of the RX and TX statistics counters. The statistics counters
are snapshot when fulfilling the command request. The statistics counters rollover.
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2021 Microchip Technology Inc. and its subsidiaries
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Note:
TX statistics counters are not affected by frames sent in response to NS/ARP requests when the device is
suspended.
Good byte and received frame counters will count all frames that are delivered to the Host. If Store Bad
Frames is set in the FIFO Controller RX FIFO Control Register (FCT_RX_CTL) any bad frames received
will be counted as well.
The statistics counters are cleared by all reset events including LRST.
TABLE 5-7:
FORMAT OF GET STATISTICS SETUP STAGE
Offset
Field
Value
0h
bmRequestType
C0h
1h
bRequest
A2h
2h
wValue
00h
4h
wIndex
00h
6h
wLength
BCh
TABLE 5-8:
FORMAT OF GET STATISTICS DATA STAGE
Offset
Field
00h
RX FCS Errors
04h
RX Alignment Errors
08h
Rx Fragment Errors
0Ch
RX Jabber Errors
10h
RX Undersize Frame Errors
14h
RX Oversize Frame Errors
18h
RX Dropped Frames
1Ch
RX Unicast Byte Count
20h
RX Broadcast Byte Count
24h
RX Multicast Byte Count
28h
RX Unicast Frames
2Ch
RX Broadcast Frames
30h
RX Multicast Frames
34h
RX Pause Frames
38h
RX 64 Byte Frames
3Ch
RX 65 - 127 Byte Frames
40h
RX 128 - 255 Byte Frames
44h
RX 256 - 511 Bytes Frames
48h
RX 512 - 1023 Byte Frames
4Ch
RX 1024 - 1518 Byte Frames
50h
RX Greater 1518 Byte Frames
54h
EEE RX LPI Transitions
58h
EEE RX LPI Time
5Ch
TX FCS Errors
60h
TX Excess Deferral Errors
64h
TX Carrier Errors
68h
TX Bad Byte Count
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 21
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TABLE 5-8:
FORMAT OF GET STATISTICS DATA STAGE (CONTINUED)
Offset
Field
6Ch
TX Single Collisions
70h
TX Multiple Collisions
74h
TX Excessive Collision
78h
TX Late Collisions
7Ch
TX Unicast Byte Count
80h
TX Broadcast Byte Count
84h
TX Multicast Byte Count
88h
TX Unicast Frames
8Ch
TX Broadcast Frames
90h
TX Multicast Frames
94h
TX Pause Frames
98h
TX 64 Byte Frames
9Ch
TX 65 - 127 Byte Frames
A0h
TX 128 - 255 Byte Frames
A4h
TX 256 - 511 Bytes Frames
A8h
TX 512 - 1023 Byte Frames
ACh
TX 1024 - 1518 Byte Frames
B0h
TX Greater 1518 Byte Frames
B4h
EEE TX LPI Transitions
B8h
EEE TX LPI Time
TABLE 5-9:
STATISTICS COUNTER DEFINITIONS
Name
RX FCS Errors
Description
Number of frames received with CRC-32 errors or RX errors.
Note:
If a frame has a Jabber Error and FCS error, only the RX
Jabber Errors counter will be incremented
Note:
If a frame is less than 64 bytes in length and has an FCS
error, only the RX Fragment Errors counter will be
incremented.
Size
(Bits)
20
RX Alignment Errors
Number of RX frames received with alignment errors.
20
RX Fragment Errors
Number of frames received that are < 64 bytes in size and have an
FCS error or RX error.
20
Note:
RX Jabber Errors
DS00001993F-page 22
If a frame is less than 64 bytes in length and has an FCS
error, only the RX Fragment Errors counter will be
incremented.
Number of frames received with a length greater than Maximum
Frame Size (MAX_SIZE) and have FCS errors or RX errors.
Note:
The existence of extra bits does not trigger a jabber error. A
jabber error requires at least one full byte beyond the value
specified by the Maximum Frame Size (MAX_SIZE) to be
received.
Note:
If a frame has a Jabber Error and FCS error, only the RX
Jabber Errors counter will be incremented.
20
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TABLE 5-9:
STATISTICS COUNTER DEFINITIONS (CONTINUED)
Description
Size
(Bits)
RX Undersize Frame Errors
Number of frames received with a length less than 64 bytes. No other
errors have been detected in the frame.
20
RX Oversize Frame Errors
Number of frames received with a length greater than the programmed
maximum Ethernet frame size (Maximum Frame Size (MAX_SIZE)
field of the MAC Receive Register (MAC_RX)). No other errors have
been detected in the frame.
20
Name
RX Dropped Frames
Note:
The VLAN Frame Size Enforcement (FSE) bit allows for the
maximum legal size to be increased by 4-bytes to account
for a single VLAN tag or 8-bytes to account for stacked VLAN
tags.
Note:
The MAC determines a VLAN tag is present if the type field
is equal to 8100h or the value programmed in the VLAN Type
Register (VLAN_TYPE).
Note:
The existence of extra bits does not trigger an oversize error.
An oversize error requires at least one full byte beyond the
value specified by the Maximum Frame Size (MAX_SIZE) to
be received.
Number of RX frames dropped by the FCT due to insufficient room in
the RX FIFO.
Note:
RX Unicast Byte Count
20
If a frame to be dropped has an Ethernet error, it will be
counted in the relevant bad frame counter. The RX Dropped
Frames counter will be incremented for the errored frame
only if Store Bad Frames is set in the FIFO Controller RX
FIFO Control Register (FCT_RX_CTL).
Total number of bytes received from unicast frames without errors.
32
This counter does not count frames that fail address filtering. Pause
frames filtered by Forward Pause Frames (FPF) are not counted.
Frames that are discarded from FIFO overflow are not counted.
Note:
RX Broadcast Byte Count
The per frame byte count does not include the VLAN TAG
and VID if the Enable VLAN Tag Stripping bit is set in the
Receive Filtering Engine Control Register (RFE_CTL). It
does not include the FCS if the FCS Stripping bit is set in the
MAC Receive Register (MAC_RX).
Total number of bytes received from broadcast frames without errors.
32
This counter does not count broadcast frames received when the
Accept Broadcast Frames (AB) bit is deasserted. Frames that are
discarded from FIFO overflow are not counted.
Note:
The per frame byte count does not include the VLAN TAG
and VID if the Enable VLAN Tag Stripping bit is set in the
Receive Filtering Engine Control Register (RFE_CTL). It
does not include the FCS if the FCS Stripping bit is set in the
MAC Receive Register (MAC_RX).
2021 Microchip Technology Inc. and its subsidiaries
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TABLE 5-9:
STATISTICS COUNTER DEFINITIONS (CONTINUED)
Description
Size
(Bits)
Total number of bytes received from multicast frames without errors.
32
Name
RX Multicast Byte Count
This counter does not count frames that fail address filtering. Pause
frames filtered by Forward Pause Frames (FPF) are not counted.
Frames that are discarded from FIFO overflow are not counted.
Note:
RX Unicast Frames
The per frame byte count does not include the VLAN TAG
and VID if the Enable VLAN Tag Stripping bit is set in the
Receive Filtering Engine Control Register (RFE_CTL). It
does not include the FCS if the FCS Stripping bit is set in the
MAC Receive Register (MAC_RX).
Number of unicast frames received without errors.
20
This counter does not count frames that fail address filtering. Pause
frames filtered by Forward Pause Frames (FPF) are not counted.
Frames that are discarded from FIFO overflow are not counted.
RX Broadcast Frames
Number of broadcast frames received without errors.
20
This counter does not count broadcast frames received when the
Accept Broadcast Frames (AB) bit is deasserted. Frames that are
discarded from FIFO overflow are not counted.
RX Multicast Frames
Number of multicast frames received without errors.
20
This counter does not count frames that fail address filtering. Pause
frames filtered by Forward Pause Frames (FPF) are not counted.
Frames that are discarded from FIFO overflow are not counted.
RX Pause Frames
Number of pause frames received without errors.
Note:
RX 64 Byte Frames
20
This counter records pause frames that failed address
filtering.
Number of frames received with a length of 64 bytes without errors.
20
This counter does not count frames that fail address filtering. Pause
frames filtered by Forward Pause Frames (FPF) are not counted.
Frames that are discarded from FIFO overflow are not counted.
RX 65 - 127 Byte Frames
Number of frames received with a length between 65 bytes and 127
bytes without errors.
20
This counter does not count frames that fail address filtering. Frames
that are discarded from FIFO overflow are not counted.
RX 128 - 255 Byte Frames
Number of frames received with a length between 128 bytes and 255
bytes without errors.
20
This counter does not count frames that fail address filtering. Frames
that are discarded from FIFO overflow are not counted.
RX 256 - 511 Bytes Frames
Number of frames received with a length between 256 bytes and 511
bytes without errors.
20
This counter does not count frames that fail address filtering. Frames
that are discarded from FIFO overflow are not counted.
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TABLE 5-9:
STATISTICS COUNTER DEFINITIONS (CONTINUED)
Description
Size
(Bits)
Number of frames received with a length between 512 bytes and 1023
bytes without errors.
20
Name
RX 512 - 1023 Byte Frames
This counter does not count frames that fail address filtering. Frames
that are discarded from FIFO overflow are not counted.
RX 1024 - 1518 Byte Frames
Number of frames received with a length between 1024 bytes and
1518 bytes without errors.
20
This counter does not count frames that fail address filtering. Frames
that are discarded from FIFO overflow are not counted.
RX Greater 1518 Byte Frames
Number of frames received with a length greater than 1518 bytes
without errors.
20
This counter does not count frames that fail address filtering. Frames
that are discarded from FIFO overflow are not counted.
EEE RX LPI Transitions
Number of times that the LPI indication from the PHY changes from
de-asserted to asserted.
32
This counter is reset if Energy Efficient Ethernet Enable (EEEEN) in
MAC Control Register (MAC_CR) is low.
This counters is required to operate during SUSPEND0, SUSPEND3
and Normal Configured Power states.
EEE RX LPI Time
The amount of time, in micro-seconds, that the PHY indicates LPI.
32
This counter is reset if Energy Efficient Ethernet Enable (EEEEN) in
MAC Control Register (MAC_CR) is low.
This counters is required to operate during SUSPEND0, SUSPEND3
and Normal Configured Power states.
TX FCS Errors
Number of frames transmitted with an FCS error. The MAC can be
forced to transmit frames with FCS errors by setting the Bad FCS
(BFCS) bit.
20
TX Excess Deferral Errors
Number of frames that were excessively deferred. The frame has
been deferred for more than two max-sized frame times + 16 bytes.
The maximum frame length is defined by Maximum Frame Size
(MAX_SIZE) in MAC Receive Register (MAC_RX)
20
Note:
Defer time is not cumulative. If the transmitter defers for
10,000 bit times, then transmits, collides, backs off, and then
has to defer again after completion of back-off, the deferral
timer resets to 0 and restarts.
Note:
The 16 bytes of margin is to account for the possibility of
double VLAN tags.
TX Carrier Errors
Number of frames that had a carrier sense error occur during
transmission. This error is caused by no carrier or loss of carrier.
20
TX Bad Byte Count
Total number of bytes sent from errored transmissions.
32
TX Single Collisions
Number of frames successfully transmitted after a single collision
occurs.
20
TX Multiple Collisions
Number of frames successfully transmitted after multiple collisions
occur.
20
2021 Microchip Technology Inc. and its subsidiaries
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TABLE 5-9:
STATISTICS COUNTER DEFINITIONS (CONTINUED)
Name
TX Excessive Collision
Description
Number of transmitted frames aborted due to excessive collisions.
Note:
Size
(Bits)
20
16 collisions results in an excessive collisions.
TX Late Collisions
Number of transmitted frames aborted because of a late collision.
20
TX Unicast Byte Count
Total number of bytes transmitted by unicast frames without errors.
32
This counter does not count flow control frames. Bytes transmitted as
part of a partial packet transmission (half-duplex collision) are not
counted.
TX Broadcast Byte Count
Total number of bytes transmitted by broadcast frames without errors.
32
This counter does not count flow control frames. Bytes transmitted as
part of a partial packet transmission (half-duplex collision) are not
counted.
TX Multicast Byte Count
Total number of bytes transmitted by multicast frames without errors.
32
This counter does not count flow control frames. Bytes transmitted as
part of a partial packet transmission (half-duplex collision) are not
counted.
TX Unicast Frames
Number of unicast TX frames transmitted without errors.
20
This counter does not count flow control frames.
TX Broadcast Frames
Number of broadcast TX frames transmitted without errors.
20
This counter does not count flow control frames.
TX Multicast Frames
Number of multicast TX frames transmitted without errors.
20
This counter does not count flow control frames.
TX Pause Frames
Number of successfully transmitted pause frames.
20
TX 64 Byte Frames
Number of frames transmitted with a length of 64 bytes without error.
20
This counter does not count flow control frames. Frames transmitted
as part of a partial packet transmission (half-duplex collision) are not
counted.
TX 65 - 127 Byte Frames
Number of frames transmitted with a length between 65 bytes and 127
bytes without error.
20
Frames transmitted as part of a partial packet transmission (halfduplex collision) are not counted.
TX 128 - 255 Byte Frames
Number of frames transmitted with a length between 128 bytes and
255 bytes without error.
20
Frames transmitted as part of a partial packet transmission (halfduplex collision) are not counted.
TX 256 - 511 Bytes Frames
Number of frames transmitted with a length between 256 bytes and
511 bytes without error.
20
Frames transmitted as part of a partial packet transmission (halfduplex collision) are not counted.
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TABLE 5-9:
STATISTICS COUNTER DEFINITIONS (CONTINUED)
Name
TX 512 - 1023 Byte Frames
Size
(Bits)
Description
Number of frames transmitted with a length between 512 bytes and
1023 bytes without error.
20
Frames transmitted as part of a partial packet transmission (halfduplex collision) are not counted.
TX 1024 - 1518 Byte Frames
Number of frames transmitted with a length between 1024 bytes and
1518 bytes without error.
20
Frames transmitted as part of a partial packet transmission (halfduplex collision) are not counted.
TX Greater 1518 Byte Frames
Number of frames transmitted with a length greater than 1518 bytes
without error.
20
Frames transmitted as part of a partial packet transmission (halfduplex collision) are not counted.
EEE TX LPI Transitions
Number of times that the LPI request to the PHY changes from deasserted to asserted.
32
This counter is reset if Energy Efficient Ethernet Enable (EEEEN) in
MAC Control Register (MAC_CR) is low.
This counter is required to operate during SUSPEND0, SUSPEND3
and Normal Configured Power states.
EEE TX LPI Time
The amount of time, in microseconds, that the PHY is requested to
send LPI.
32
This counter is reset if Energy Efficient Ethernet Enable (EEEEN) in
MAC Control Register (MAC_CR) is low.
This counters is required to operate during SUSPEND0, SUSPEND3
and Normal Configured Power states.
5.2.3
DESCRIPTOR RAM
The Control Endpoint manipulates an internal Descriptor RAM which stores various configuration for the device including USB descriptors. The descriptor RAM is typically loaded from either an external EEPROM or the integrated OTP.
However a mechanism exists, EEPROM-less mode, which allows the host software to directly configure the Descriptor
RAM. It is described in Section 10.6, "Customized Operation Without EEPROM". The Descriptor RAM format is discussed in Section 10.6.3, "Descriptor RAM Initialization"
The Control EP first evaluates whether an external EEPROM is present by the successful recognition of the EEPROM
signature. If an EEPROM exists, it shall be used to load the contents into the Descriptor RAM.
If an EEPROM does not exist, the Control EP considers whether the OTP is configured. If the OTP is configured it shall
be used to load the Descriptor RAM.
In the event that the EEPROM does not exist and the OTP is not configured, the Control EP shall utilize the CSR and
EEPROM defaults, as defined in Section 10.5, "EEPROM Defaults", for configuring the device.
EEPROM-Less operation may be invoked by host software. This mode shall take priority over an external EEPROM or
configured OTP. This mode is described in Section 10.6, "Customized Operation Without EEPROM".
5.3
Bulk In Endpoint
The Bulk In Endpoint is controlled by the UTX (USB Bulk In Transmitter). The UTX is responsible for encapsulating
Ethernet data into USB Bulk In packets. Ethernet frames are retrieved from the FCT’s RX FIFO and passed to the UDC.
The UTX manages an 8 KB UTX FIFO Buffer. USB packets from FCT are temporarily stored there to facilitate efficient
bursting. In support for bursting, a USB Command FIFO is managed by the UTX to track packet lengths.
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5.3.1
USB TX DATA FIFO
The UTX Data FIFO RAM is a 2K x 32 (8 KB) dual port type. All USB packets are DWORD aligned in the USB TX Data
FIFO. All Ethernet frames are DWORD aligned in USB packets. Within a USB transfer (assuming MEF mode is
enabled), consecutive Ethernet frames are not concatenated into the same DWORD. The unused bytes (up to 3) in the
DWORD at the end of an Ethernet frame (assuming it is not the last frame) are included in the USB packet and its length
and are discarded by the host driver software. At the end of a USB transfer, the unused bytes (up to 3) are not included
in the USB packet or it’s length. The USB Device Controller will discard any unused bytes within a DWORD.
5.3.2
USB TX COMMAND FIFO
As Ethernet frames are transferred into the USB TX Data FIFO, the resulting USB packet lengths (including any zero
length packets) are written into the USB TX Command FIFO. The USB Device Controller requires the packet lengths
and number of packets available at the start of a USB transmission.
The size of the USB command FIFO allows up to 32 packets to be queued. This number is based on the 8K byte size
of the USB TX Data FIFO divided by an average USB packet size of 256 bytes (e.g. 16 @ 512 byte packets and 16 zero
length packets, etc.). Since it is possible for the USB TX Command FIFO to fill before the USB TX Data FIFO, the USB
TX Command FIFO provides a full signal.
The head entry (USB packet length) and depth (number of entries) of the USB TX Command FIFO are passed as the
USB packet length and number of available packets, respectively, to the USB Device Controller.
5.3.3
MEF/SEF OPERATION
The UTX supports the following two modes of operation: MEF and SEF, selected via the Multiple Ethernet Frames per
USB Packet (MEF) bit of the Hardware Configuration Register (HW_CFG).
• MEF: Multiple Ethernet frames per Bulk In packet. This mode will maximize USB bus utilization by allowing multiple Ethernet frames to be packed into a USB packet. Frames greater than maximum USB packet size are split
across multiple Bulk In packets.
• SEF: Single Ethernet frame per Bulk In packet. This mode will not maximize USB bus utilization, but simplifies the
host software implementation and can potentially ease the burden on a low end Host processor. Frames greater
than maximum USB packet size are split across multiple Bulk In packets.
Each Ethernet frame is pre-pended with three RX Command Words, RX Command A, RX Command B and RX Command C by the FCT. RX Command A contains the frame length that is used by the UTX to perform the encapsulation
functions. The contents of the command words are generated by the MAC, RFE, and FCT.
FIGURE 5-1:
RX
CMD A
RX
CMD B
MEF USB ENCAPSULATION
C’
Ethernet
Frame
RX
CMD A
RX
CMD B
C’
Ethernet
Frame
RX
CMD A
RX
CMD B
C’
Ethernet
Frame
512 Byte USB Bulk Frame
RX
CMD A
RX
CMD B
C’
Ethernet
Frame
RX
CMD A
RX
CMD B
RX
CMD A
RX
CMD B
Ethernet Frame
C’
512 Byte USB Bulk Frame
Ethernet Frame
C’
512 Byte USB Bulk Frame
512 Byte USB Bulk Frame
C’
Denotes RX
Command Word C
An Ethernet frame (starting with RX Command A) always begins on a DWORD boundary in the FCT. In MEF mode,
UTX will not concatenate the end of the current frame and the beginning of the next frame into the same DWORD.
Therefore, the last DWORD of an Ethernet frame may have unused bytes added to ensure DWORD alignment of the
RX Command A of the next frame. The addition of pad bytes at the end of the frame depends on whether another frame
is available for transmission after the current one. If the current frame is the last frame to be transmitted, no pad bytes
will be added, as the USB protocol allows for termination of the packet on a byte boundary. If, however, another frame
is available for transmission, the current frame will be padded out so that it ends on the DWORD boundary. This ensures
the next frame to be transmitted, starting with RX Command A, will start on a DWORD boundary.
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Any unused bytes that were added to the last DWORD of a frame are not counted in the length field of RX Command A.
As noted in Section 5.3.1, UTX is responsible for storing USB packets into UTX Data FIFO. When calculating USB
packet lengths DWORD padding between Ethernet frames is included.
In accordance with the USB protocol, UTX terminates a burst with either a ZLP or a Bulk In packet with a size of less
than the Bulk In maximum packet size (512 for HS, 64 for FS). The ZLP is needed when the total amount of data transmitted is a multiple of a Bulk In maximum packet size. UTX monitors the UTX Data FIFO size to determine when a burst
has ended.
The UTX monitors the RX FIFO size signal from the FCT and moves data into the UTX Data FIFO as complete Ethernet
frames are received by the FCT and space is available. When the frame is moved its length is incorporated to packet
length of the USB packet being formed. After a complete USB packet is created an entry is written into the UTX Command FIFO. If the Ethernet frame can not fit into the USB packet the remainder is moved into subsequent USB
packet(s).
Note:
In SEF mode, a ZLP is transmitted if the Ethernet frame is the same size as a maximum size Bulk In packet,
or a multiple of the maximum Bulk In packet size.
The Host ignores unused bytes that exist in the last DWORD of an Ethernet frame.
When using SEF mode, there will never be any unused bytes added for end alignment padding. The USB
transfer always ends on the last byte of the Ethernet frame.
If UTX receives a Bulk In token when the RX FIFO is empty, it will transmit a ZLP if Bulk-In Empty Response
(BIR) is set otherwise it will NAK (FS/HS) or NRDY (SS) when cleared.
The UTX provides a mechanism for limiting the size of the USB burst per the burst cap function as described in Burst
Cap Usage. This caps the amount of data that can be moved in a USB transfer before termination by a ZLP. The burst
cap function applies for all operating speeds.
In order to more efficiently utilize USB bandwidth in MEF mode, the UTX has a mechanism for delaying the transmission
of a short packet, or ZLP. This mode entails having the UTX wait a time defined by the Bulk-In Delay Register
(BULK_IN_DLY) before terminating the burst. A value of zero in this register disables this feature. By default, a delay of
34 us is used.
After UTX transmits the last USB bMaxPacketSize packet in a burst, UTX enables an internal timer. When this timer is
equal to Bulk In Delay, any Bulk In data in the UTX Data FIFO is transmitted upon next opportunity to the host.
In HS/FS mode, if enough data arrives before the timer elapses to build at least one maximum sized packet, then the
UTX will transmit this packet when it receives the next Bulk In Token. After packet transmission, the UTX will reset its
internal timer and delay the short packet, or ZLP, transmission until the Bulk In Delay time elapses or new data is
received per above.
In the case where the UTX Data FIFO is empty and a single Ethernet packet less than USB bMaxPacketSize is then
received, the UTX enables its internal timer. If enough data arrives before the timer elapses to build at least one maximum sized packet, the UTX will transmit this packet and reset the timer. Otherwise, FIFO data is sent after the timer
expires.
In HS/FS mode, the UTX will NAK any Bulk In tokens while waiting for new data and Bulk In Delay to elapse.
Bulk In Delay is only intended for MEF operation and not appropriate for SEF mode.
5.3.4
USB ACKS AND RETRIES
In the case of an error condition, the UTX will issue a rewind to the FCT. This occurs when the UTX completes transmitting a Bulk In packet and does not receive an ACK from the Host. In this case, the next frame received by the UTX
will be another In token and the Bulk In packet is retransmitted. When the ACK is finally received, the UTX notifies the
FCT. The FCT will then advance the read head pointer to the next packet.
Both the USB TX Data and Command FIFOs handle USB retries. When a USB packet is acknowledged, its command
information is popped from the USB TX Command FIFO and its storage can be release from the USB TX Data FIFO
(note that zero length packets would not release any USB TX Data FIFO space).
Burst Cap Usage
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The UTX, via the Burst Cap Register (BURST_CAP), is capable of prematurely terminating a burst. The Burst Cap Register (BURST_CAP) uses units of USB packet size (64/512/1024 bytes). To enable use of the Burst Cap register, the
Burst Cap Enable (BCE) bit in the USB Configuration Register 0 (USB_CFG0) must be set.
For proper operation, the BURST_CAP field should be set by software so that the following relationships hold true:
For HS Operation, BURST_CAP * 512 >= Maximum Frame Size (MAX_SIZE)
For FS Operation, BURST_CAP * 64 >= Maximum Frame Size (MAX_SIZE)
Failure to set BURST_CAP values that obey the previous rules may result in untoward operation and may yield unpredictable results.
Note:
The first Ethernet frame of the burst is always sent without checking if it exceeds BURST_CAP.
Whenever Burst Cap enforcement is disabled and the RX FIFO, and UTX FIFO, are empty, the UTX will respond with
a ZLP if Bulk-In Empty Response (BIR) = “0”. However, it will respond with NAK (FS/HS) when Bulk-In Empty Response
(BIR) = “1”.
Whenever Burst Cap enforcement is enabled, the following holds:
• For HS Operation:
BURSTMax = BURST_CAP * 512
• For FS operation:
BURSTMax = BURST_CAP * 64
Let BURSTCur = Length of current burst = Summation of the lengths of frames in the current burst.
Let LENGTHNext = Length of the next frame available in the RX FIFO.
If the RX FIFO runs out of data, or a frame is available and BURSTCur + LENGTHNext > BURSTMax, then the burst is
terminated with either a short USB packet or with a ZLP.
Otherwise, the next frame is able to fit in the current burst without exceeding BURST_CAP. The burst is continued and
BURSTCur is incremented by LENGTHNext.
Note:
If Store Bad Frames is set in the FIFO Controller RX FIFO Control Register (FCT_RX_CTL), then the size
of the transmitted burst may exceed the value specified by BURST_CAP. This can happen if an oversized
frame is received that is larger than BURST_CAP.
Ethernet frames are not fragmented across bursts when using Burst Cap Enforcement.
5.4
Bulk Out Endpoint
The Bulk Out Endpoint is controlled by the URX (USB Bulk Out Receiver). URX is responsible for receiving Ethernet
data encapsulated over USB Bulk Out packet(s). Unlike the UTX, the URX does not explicitly track Ethernet frames. It
views all received packets purely as USB data. The extraction of Ethernet frames is handled by the FCT. The URX
always simultaneously supports MEF and SEF modes.
5.4.1
USB RX DATA FIFO
The URX manages an 8 KB Data FIFO. All USB packets start on DWORD boundaries. The format of the data within
USB packets and across USB transactions ensures that Ethernet frames (including command headers) are DWORD
aligned. Padding between Ethernet frames is added by the host driver and stripped by the TX FIFO.
5.4.2
RETRIES AND ERRORS
Packets from the USB Device Controller have the possibility of an error and subsequent retry. Based on the status of
the packet, the packet may be either rejected or accepted. If the packet is rejected, the write pointers and free space is
recovered from the data FIFO. If the packet is accepted, it can be made available to the FCT. Packet rejection or acceptance will occur before the start of the next packet, such that multiple outstanding packets need not be tracked.
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The FCT notifies the URX when it detects loss of sync. When this occurs, the URX stalls the Bulk Out pipe via the UDC.
This is an appropriate response, as loss of sync is a catastrophic error (which can only be caused by a host software
error. See Section 6.2.4, "TX Error Detection"). This behavior is configurable via the Stall Bulk-Out Pipe Disable (SBP)
bit in the USB Configuration Register 0 (USB_CFG0).
5.5
Interrupt Endpoint
The Interrupt endpoint is responsible for indicating the device’s status at each polling interval. The Interrupt endpoint is
implemented via the CTL module. When the endpoint is accessed the following fields are presented to the host.
5.5.1
INTERRUPT PACKET FORMAT
TABLE 5-10:
INTERRUPT PACKET FORMAT
Bits
31:29
Description
Reserved
28
OTP_WR_DONE_INT
27
Reserved
26
EEE_START_TX_LPI_INT
25
EEE_STOP_TX_LPI_INT
24
EEE_RX_LPI_INT
23
MACRTO_INT
22
RDFO_INT
21
TXE_INT
20
USB_STS_INT
19
TX_DIS_INT
18
RX_DIS_INT
17
PHY_INT
16
DP_INT
15
MAC_ERR_INT
14
TDFU
13
TDFO
12
UTX_FP
11:0
GPIOx_INT
If there is no interrupt status to report the device responds with a NAK unless Interrupt Endpoint Always On (INTEP_ON)
in Interrupt Endpoint Control Register (INT_EP_CTL) is set in which case an interrupt packet of 0x0 is returned.
Note:
The polling interval is static and set through OTP or EEPROM. The polling interval can be changed by the
host updating the contents of the EEPROM and resetting the part.
For an interrupt event to be reported via the Interrupt endpoint, the respective bit must be enabled in Interrupt Endpoint
Control Register (INT_EP_CTL). The interrupt status can be cleared by writing to the Interrupt Status Register
(INT_STS).
5.5.2
USB STATUS
USB_STS_INT bit is used to facilitate communication with the host software regarding OS programming of the device.
The following are tracked by this mechanism.
• SET Select (SET_SEL) command issued
• Function Remote Wakeup Status
• Device Remote Wakeup Status
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The USB Status Register (USB_STATUS) includes both status change bits as well as the current value of the respective
when appropriate.
APPLICATION NOTE: The majority of the above status information can also be obtained using the GET_STATUS
USB request.
5.6
LPM Support
The USB device controller supports Link Power Management (LPM). It is fully capable of responding to LPM devices
and placing the device into the L1 and L2 states or conversely moving the device to L0 via remote wakeup or Resume
signaling.
Further details on LPM implementation can be found in Section 13.0, "Clocks and Power Management (CPM)," on
page 124.
LPM is enabled by setting the LPM Capability (LPM_CAP) bit in USB Configuration Register 0 (USB_CFG0).
5.6.1
LPM L1
In L1 minimal components are powered down in order to ensure the device can quickly transition to L0 and not violate
the pertinent USB specification parameters.
The device shall automatically transition the link from L1 to L0 after it receives a frame which passes any programmed
filters in the RFE and MAC. Additionally, a scheduled interrupt EP packet shall also cause the device to transition out of
L0.
5.6.2
LPM L2
The L2 state mimics the respective suspend mode programmed in the Suspend Mode (SUSPEND_MODE) of the Power
Management Control Register (PMT_CTL).
5.7
USB Descriptors
In the event that the OTP is not configured or an external EEPROM is not available, the default values defined in the
descriptor tables below are used - except in the case where EEPROM-less mode is enabled. In that case, the descriptors are programmed as defined in Section 10.6, "Customized Operation Without EEPROM".
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5.7.1
DEVICE DESCRIPTOR
The Device Descriptors are initialized based on values stored in OTP or EEPROM. Table 5-11 shows the default Device
Descriptor values. These values are used for Full-Speed and High-Speed operation.
TABLE 5-11:
OFFSET
DEVICE DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
12h
Note 5-1
Size of the Descriptor in Bytes (18
bytes)
01h
bDescriptorType
1
01h
Note 5-1
Device Descriptor (0x01)
02h
bcdUSB
2
Note 5-2
Yes
USB Specification Number which
device complies to
04h
bDeviceClass
1
FFh
Yes
Class Code
05h
bDeviceSubClass
1
00h
Yes
Subclass Code
06h
bDeviceProtocol
1
FFh
Yes
Protocol Code
07h
bMaxPacketSize
1
Note 5-3
Yes
Maximum Packet Size for Endpoint 0
08h
IdVendor
2
0424h
Yes
Vendor ID
0Ah
IdProduct
2
7850h
Yes
Product ID
0Ch
bcdDevice
2
Note 5-4
Yes
Device Release Number
0Eh
iManufacturer
1
00h
Yes
Index of Manufacturer String
Descriptor
0Fh
iProduct
1
00h
Yes
Index of Product String Descriptor
10h
iSerialNumber
1
00h
Yes
Index of Serial Number String
Descriptor
11h
bNumConfigurations
1
01h
Note 5-5
Number of Possible Configurations
Note 5-1
The descriptor length and descriptor type for Device Descriptors specified in OTP or EEPROM are
“don’t cares” and are always overwritten by hardware as 0x12 and 0x01, respectively.
Note 5-2
When operating in USB 2.0 mode the default value is 0210h (USB 2.10).
Note 5-3
When operating in full-speed or high-speed mode it should be set to 40h. If the OTP is not configured,
or EEPROM is not present, the aforementioned values are returned.
Note 5-4
Default value is dependent on device release. The MSB matches the device release and the LSB is
hard-coded to 00h. The initial release value is 01h. Subsequent versions will increment the value.
Note 5-5
Value is loaded from OTP, or EEPROM, but must be equal to the Default Value in order to comply
with the USB Specification and provide for normal device operation. Specification of any other value
will result in unwanted behavior and untoward operation.
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5.7.2
CONFIGURATION DESCRIPTOR
The Configuration Descriptor is initialized based on values stored in OTP or EEPROM. Table 5-12 shows the default
Configuration Descriptor values. These values are used for Full-Speed and High-Speed operation.
TABLE 5-12:
OFFSET
CONFIGURATION DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
09h
Note 5-6
Size of the Configuration Descriptor
in bytes (9 bytes)
01h
bDescriptorType
1
02h
Note 5-7
Configuration Descriptor (0x02)
02h
wTotalLength
2
Note 5-8
Note 5-6
Total length in bytes of data returned
04h
bNumInterfaces
1
01h
Note 5-6
Number of Interfaces
05h
bConfigurationValue
1
01h
Note 5-6
Value to use as an argument to select
this configuration
06h
iConfiguration
1
00h
Yes
Index of String Descriptor describing
this configuration
07h
bmAttributes
1
E0h
Yes
Self powered and remote wakeup
enabled.
08h
bMaxPower
1
Note 5-9
Yes
Maximum Power Consumption
Note 5-6
Value is loaded from OTP, or EEPROM, but must be equal to the Default Value in order to provide
for normal device operation. Specification of any other value will result in unwanted behavior and
untoward operation.
Note 5-7
The descriptor type for Configuration Descriptors specified in OTP, or EEPROM, is a “don’t care” and
is always overwritten by hardware as 0x02.
Note 5-8
Default value is 0027h (39 bytes) when operating in USB 2.0 mode.
Note 5-9
Default value is 01h in Self Powered mode. In Bus Powered mode, default value is FAh (500mA).
Note:
The Configuration Flags of the OTP, or EEPROM, may affect the default value of bmAttributes.
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5.7.3
INTERFACE DESCRIPTOR DEFAULT
Table 5-13 shows the default value for Interface Descriptor 0. This descriptor is initialized based on values stored in OTP
or EEPROM.
TABLE 5-13:
OFFSET
INTERFACE DESCRIPTOR 0
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
09h
Note 5-10
Size of Descriptor in Bytes (9 Bytes
01h
bDescriptorType
1
04h
Note 5-10
Interface Descriptor (0x04)
02h
bInterfaceNumber
1
00h
Note 5-10
Number identifying this Interface
03h
bAlternateSetting
1
00h
Note 5-10
Value used to select alternative
setting
04h
bNumEndpoints
1
03h
Note 5-10
Number of Endpoints used for this
interface (Less endpoint 0)
05h
bInterfaceClass
1
FFh
Yes
Class Code
06h
bInterfaceSubClass
1
00h
Yes
Subclass Code
07h
bInterfaceProtocol
1
FFh
Yes
Protocol Code
08h
iInterface
1
00h
Yes
Index of String Descriptor Describing
this interface
Note 5-10
5.7.4
Value is loaded from OTP or EEPROM, but must be equal to the Default Value in order to comply
with the USB Specification and provide for normal device operation. Specification of any other value
will result in unwanted behavior and untoward operation.
ENDPOINT 1 DESCRIPTOR (BULK-IN)
Table 5-14 shows the default value for Endpoint Descriptor 1. This descriptor is not initialized from values stored in OTP
or EEPROM.
TABLE 5-14:
OFFSET
ENDPOINT 1 DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM
DESCRIPTION
00h
bLength
1
07h
No
Size of Descriptor in bytes
01h
bDescriptorType
1
05h
No
Endpoint Descriptor
02h
bEndpointAddress
1
81h
No
Endpoint Address
03h
bmAttributes
1
02h
No
Bulk Transfer Type
04h
wMaxPacketSize
2
Note 5-11
No
Maximum Packet Size this endpoint
is capable of sending.
06h
bInterval
1
00h
No
Interval for polling endpoint data
transfers. Ignored for bulk endpoints.
Note 5-11
64 bytes for full-speed mode, 512 bytes for high-speed mode.
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5.7.5
ENDPOINT 2 DESCRIPTOR (BULK-OUT)
Table 5-14 shows the default value for Endpoint Descriptor 2. This descriptor is not initialized from values stored in OTP
or EEPROM.
TABLE 5-15:
OFFSET
ENDPOINT 1 DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
07h
No
Size of Descriptor in bytes
01h
bDescriptorType
1
05h
No
Endpoint Descriptor
02h
bEndpointAddress
1
02h
No
Endpoint Address
03h
bmAttributes
1
02h
No
Bulk Transfer Type
04h
wMaxPacketSize
2
Note 5-12
No
Maximum Packet Size this endpoint
is capable of sending.
06h
bInterval
1
00h
No
Interval for polling endpoint data
transfers. Ignored for bulk endpoints.
Note 5-12
5.7.6
64 bytes for full-speed mode, 512 bytes for high-speed mode
ENDPOINT 3 DESCRIPTOR (INTERRUPT)
Table 5-16 shows the default value for Endpoint Descriptor 3. Only the bInterval field of this descriptor is initialized from
OTP or EEPROM.
TABLE 5-16:
OFFSET
ENDPOINT 2 DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
07h
No
Size of Descriptor in bytes
01h
bDescriptorType
1
05h
No
Endpoint Descriptor
02h
bEndpointAddress
1
83h
No
Endpoint Address
03h
bmAttributes
1
03h
No
Interrupt Transfer Type
04h
wMaxPacketSize
2
10h
No
Maximum Packet Size this endpoint
is capable of sending.
06h
bInterval
1
Note 5-13
Yes
Interval for polling endpoint data
transfers.
Note 5-13
This value is loaded from OTP, or EEPROM. A full-speed and high-speed polling interval exists. If
OTP is not configured, and EEPROM does not exist, then this value defaults to 04h for HS, 01h for
FS.
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5.7.7
OTHER SPEED CONFIGURATION DESCRIPTOR
The fields in this descriptor are derived from Configuration Descriptor information that is stored in OTP or EEPROM.
TABLE 5-17:
OFFSET
OTHER SPEED CONFIGURATION DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
09h
Note 5-14
Size of Descriptor in bytes (9 bytes)
01h
bDescriptorType
1
07h
No
Other Speed Configuration Descriptor
(0x07)
02h
wTotalLength
2
0027h
Note 5-14
Total length in bytes of data returned
(39 bytes)
04h
bNumInterfaces
1
01h
Note 5-14
Number of Interfaces
05h
bConfigurationValue
1
01h
Note 5-14
Value to use as an argument to select
this configuration
06h
iConfiguration
1
00h
Yes
Index of String Descriptor describing
this configuration
07h
bmAttributes
1
E0h
Yes
Bus powered and remote wakeup
enabled.
08h
bMaxPower
1
Note 5-15
Yes
Maximum Power Consumption
Note 5-14
Value is loaded from OTP or EEPROM, but must be equal to the Default Value in order to comply
with the USB 2.x Specification and provide for normal device operation. Specification of any other
value will result in unwanted behavior and untoward operation.
Note 5-15
Default value is 01h in Self Powered mode and FAh (500 mA) in Bus Powered mode.
Note:
OTP or EEPROM values are obtained for the Configuration Descriptor at the other USB speed. I.e., if the
current operating speed is FS, then the HS Configuration Descriptor values are used, and vice-versa.
The Configuration Flags of the OTP, or EEPROM, may affect the default value of bmAttributes
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5.7.8
DEVICE QUALIFIER DESCRIPTOR
The fields in this descriptor are derived from Device Descriptor information that is stored in the OTP or EEPROM.
TABLE 5-18:
OFFSET
DEVICE QUALIFIER DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
0Ah
No
Size of Descriptor in bytes (10 bytes)
01h
bDescriptorType
1
06h
No
Device Qualifier Descriptor (0x06)
02h
bcdUSB
2
0210h
Yes
USB Specification Number which
device complies to.
04h
bDeviceClass
1
FFh
Yes
Class Code
05h
bDeviceSubClass
1
00h
Yes
Subclass Code
06h
bDeviceProtocol
1
FFh
Yes
Protocol Code
07h
bMaxPacketSize0
1
40h
Note 5-16
Maximum Packet Size
08h
bNumConfigurations
1
01h
Note 5-16
Number of Other-Speed
Configurations
09h
Reserved
1
00h
No
Note 5-16
Note:
Must be zero
.Value is loaded from OTP or EEPROM, but must be equal to the Default Value in order to comply
with the USB 2.x Specification and provide for normal device operation.
OTP or EEPROM values are from the Device Descriptor (including any EEPROM override) at the opposite
HS/FS operating speed. I.e., if the current operating speed is HS, then Device Qualifier data is based on
the FS Device Descriptor, and vice-versa.
DS00001993F-page 38
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
5.7.9
5.7.9.1
STRING DESCRIPTORS
String Index = 0 (LANGID)
TABLE 5-19:
OFFSET
LANGID STRING DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
04h
No
Size of LANGID Descriptor in bytes (4
bytes)
01h
bDescriptorType
1
03h
No
String Descriptor (0x03)
02h
LANGID
2
None
Yes
Must be set to 0x0409 (US English).
Note:
If there is no valid/enabled OTP or EEPROM, or if all string lengths in the OTP or EEPROM are 0, then
there are no strings, so any Host attempt to read the LANGID string will return stall in the Data Stage of the
Control Transfer.
If there is a valid/enabled OTP or EEPROM, and if at least one of the string lengths is not 0, then the value
contained at addresses 0x23-0x24 shall be returned. These must be 0x0409 to allow for proper device
operation.
Note:
5.7.9.2
The device ignores the LANGID field in Control Read’s of Strings, and will return the String (if it exists),
regardless of whether the requested LANGID is 0x0409 or not.
String Indices 1-5
TABLE 5-20:
OFFSET
STRING DESCRIPTOR (INDICES 1-5)
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
none
Yes
Size of the String Descriptor in bytes
01h
bDescriptorType
1
none
Yes
String Descriptor (0x03)
02h
Unicode String
2*N
none
Yes
2 bytes per unicode character, no
trailing NULL.
Note:
If there is no valid/enabled OTP or EEPROM, or if the corresponding String Length and offset for a given
string index is zero, then that string does not exist, so any Host attempt to read that string will return stall
in the Data Stage of the Control Transfer.
The device returns whatever bytes are in the designated OTP or EEPROM area for each of these strings. It is the
responsibility of the OTP or EEPROM programmer to correctly set the bLength and bDescriptorType fields in the
descriptor consistent with the byte length specified in the corresponding EEPROM locations.
2021 Microchip Technology Inc. and its subsidiaries
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LAN7850
5.7.10
BINARY DEVICE OBJECT STORE DESCRIPTOR
The Binary Device Object Store Descriptor is initialized based on values stored in OTP or EEPROM. Table 5-21 shows
the default Binary Device Object Store Descriptor values.
TABLE 5-21:
OFFSET
BINARY DEVICE OBJECT STORE DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
05h
Note 5-17
Size of Descriptor in bytes (5 bytes)
01h
bDescriptorType
1
0Fh
Note 5-17
BOS Descriptor (0x0F)
02h
wTotalLength
2
0016h
Yes
Total length of this descriptor and its
sub-descriptors. (22 bytes)
04h
bNumDeviceCaps
1
02h
Yes
Number of Device Capability
Descriptors in this BOS.
Note 5-17
5.7.11
The descriptor length and descriptor type for Binary Device Object Store Descriptors specified in OTP
or EEPROM are “don’t cares” and are always overwritten by hardware as 0x05 and 0x0F,
respectively.
USB 2.0 EXTENSION DESCRIPTOR
The USB 2.0 Extension Descriptor is initialized based on values stored in EEPROM. Table 5-22 shows the default USB
2.0 Extension Descriptor values.
TABLE 5-22:
OFFSET
USB 2.0 EXTENSION DESCRIPTOR
FIELD
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
DESCRIPTION
00h
bLength
1
07h
Note 5-18
Size of Descriptor in bytes (7 bytes)
01h
bDescriptorType
1
10h
Note 5-18
Device Capability Descriptor (0x10)
02h
bDevCapabilityType
1
02h
Note 5-18
USB 2.0 Extension Capability (0x02)
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2021 Microchip Technology Inc. and its subsidiaries
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TABLE 5-22:
OFFSET
03h
USB 2.0 EXTENSION DESCRIPTOR (CONTINUED)
FIELD
bmAttributes
SIZE
(BYTES)
DEFAULT
VALUE
LOADED
FROM
EEPROM/
OTP
4
0006h
Yes
DESCRIPTION
Bitmap encoding of number of
supported device level features. A
value of 1 in a bit location indicates a
feature is supported. A value of 0
indicates it is not supported.
Encodings are:
BIT
ENCODING
31:16 RESERVED (0)
15:12 Recommended Deep BESL
value. Field shall be ignored
by system software if bit[4]
is zero.
11:8
Recommended Baseline
BESL value. Field shall be
ignored by system software
if bit[3] is zero.
4
Recommended deep BESL
valid.
3
Recommended baseline
BESL valid.
2
BESL & Alternate HIRD
definitions supported. The
LPM bit must be set to a
one when this bit is a one.
1
(LPM) Note 5-19
A value of 1 in this bit
position indicates that this
device supports the Link
Power Management
protocol.
0
RESERVED (0)
Note 5-18
The descriptor length, descriptor type, and device capability type for USB 2.0 Extension Descriptors
specified in OTP or EEPROM are “don’t cares” and are always overwritten by hardware as 0x07,
0x10, and 0x02, respectively.
Note 5-19
The value of this bit must match that of the LPM Capable (CFG0_LPM_CAPABLE) flag contained in
Configuration Flags 0 of the OTP or EEPROM, if present. If the bit values disagree, unexpected
results and untoward operation may result.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 41
LAN7850
6.0
FIFO CONTROLLER (FCT)
The FIFO controller uses internal RAMs to buffer RX and TX traffic. Bulk-Out packets from the URX are directly stored
into the FCT TX FIFO. The FCT is responsible for extracting Ethernet frames from the USB packet data and passing
the frames to the MAC.
Received Ethernet Frames are stored into the FCT RX FIFO and become the basis for bulk-in packets. The FCT passes
the stored data to the UTX in blocks typically 1024, 512 or 64 bytes in size, depending on the current USB operating
speed.
6.1
RX Path (Ethernet to USB)
The 12 KB RX FIFO buffers Ethernet frames received from the RFE. The UTX extracts these frames from the FCT to
form USB Bulk In packets. Host software will ultimately reassemble the Ethernet frames from the USB packets.
FCT manages the writing of data into the RX FIFO through the use of two pointers - the rx_wr_ptr and the rx_wr_hd_ptr.
The rx_wr_ptr is used to write Ethernet frame data into the FIFO. The rx_wr_hd_ptr points to two locations prior to the
first FIFO location that holds frame data. The two DWORD space is used to write RX Command A and RX Command
B upon completion of frame reception. Additionally, each Ethernet frame includes RX Command C which resides in the
same DWORD that includes the first two bytes of frame data. The command words include information about the frame
and status provided by the MAC, RFE, and FCT.
The rx_rd_ptr is used for reading data from the FIFO and passing it to the UTX. In order to support rewinds, the rx_rd_hd_ptr exists, as discussed in Section 6.1.1, "RX Error Detection". After an Ethernet frame is successfully read from the
FIFO, the rx_rd_hd_ptr advances to point to the start of the next frame. Figure 6-1 illustrates how a frame is stored in
the FIFO, along with pointer usage.
When the RFE signals that it has Data ready, the RFE controller starts passing the RX packet data to the FCT. The FCT
updates the RX FIFO pointers as the data is written into the FIFO. The last information written into the FIFO are the
Command Words.
Note:
RX Command C also serves the purpose of DWORD aligning the Ethernet frame TCP, IP and other protocol headers.
The RX FCT operates in store and forward mode. A received Ethernet frame is not visible to the UTX until the complete
frame, including the Command Words, has been written into the RX FIFO. This is due to the fact that the frame may
have to be removed via a rewind (pointer adjustment), in case of an error. Such is the case when a FIFO overflow condition is detected as the frame is being received. The FCT may be configured to discard errored frames and filtered
frames through the use of a rewind operation. The automatic discard of errored and filtered frames is enabled/disabled
by the Store Bad Frames bit of the FIFO Controller RX FIFO Control Register (FCT_RX_CTL). Please refer to Section
6.1.1, "RX Error Detection," on page 43 for further details concerning errors which may result in the FCT performing
rewind operation.
The FCT provides the UTX with an indication of how much data is available in the RX FIFO. This information is reflected
in the FIFO Controller RX FIFO Control Register (FCT_RX_CTL). In addition, internal signaling is used to inform the
UTX that at least one entire frame has been received.
A RX FIFO overflow condition may be signaled via the RX Data FIFO Overflow Interrupt (RDFO_INT). The FCT RX
Overflow bit of the FIFO Controller RX FIFO Control Register (FCT_RX_CTL) is also asserted when an overflow has
occurred.
DS00001993F-page 42
2021 Microchip Technology Inc. and its subsidiaries
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FIGURE 6-1:
RX FIFO STORAGE
FIFO data is available for
transmit only after a
complete Ethernet frame is
received and stored.
Therefore, the RX FIFO
size will not reflect partially
received packets.
RX Ethernet
Frame 2
rx_wr_ptr
RX Cmd C
USB
Packet 3
RX Command B
RX Command A
rx_wr_hd_ptr
After the complete
Ethernet frame is written,
the three Command
Words are updated
starting at the location
pointed to by the write
head pointer. The write
head pointer will then
advance to the starting
location for the next
Ethernet frame.
The read head pointer is
used for implementing
rewinds of USB packets.
USB
Packet 2
RX Ethernet
Frame 1
RX FIFO Size
USB
Packet 1
rx_rd_ptr
USB
Packet 0
rx_rd_hd_ptr
6.1.1
RX Cmd C
RX Command B
RX Command A
The unused bytes in the
last DWORD are ignored
by the host.
RX Ethernet
Frame 0
RX Cmd C
RX Command B
RX Command A
RX ERROR DETECTION
The FCT can be configured to drop Ethernet frames when certain error conditions occur. The setting of the Store Bad
Frames bit of the FIFO Controller RX FIFO Control Register (FCT_RX_CTL) determines if the frame will be retained or
dropped. Error conditions are indicated in RX Command A. Please refer to Table 5-9, “Statistics Counter Definitions,”
on page 22 for more details on the error conditions tracked by the device.
Note:
The disposition of frames having checksum errors (IP/TCP/UDP) is not affected by Store Bad Frames.
These frames are always passed to the Host Controller.
2021 Microchip Technology Inc. and its subsidiaries
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The FCT also drops frames when it detects a FIFO overflow condition. This occurs when the FIFO full condition occurs
while a frame is being received. The FCT also maintains a count of the number of times a FIFO overflow condition has
occurred.
Dropping an Ethernet frame is implemented by rewinding the received frame. A write side rewind is implemented by
setting the rx_wr_ptr to be equal to the rx_wr_hd_ptr. Similarly, a read side rewind is implemented by setting the
rx_rd_ptr to be equal to the rx_rd_hd_ptr.
For the case where the frame is dropped due to overflow, the FCT ignores the remainder of the frame. It will not begin
writing into the RX FIFO again until the next frame is received.
In the read direction, the FCT also supports rewinds for the UTX. This is needed for the case where the USB Bulk Out
packet is not successfully received by the Host and needs to be retransmitted.
6.1.2
RX COMMAND FORMAT
Every received Ethernet frame has Command Words concatenated to it that provide information about the frame.
Table 6-1, "RX Command A", Table 6-2, "RX Command B" and Table 6-3, "RX Command C" define the contents of the
Command Words.
RX Command A contains the frame length and has various status bits in regards to the frame. RX Command B provides
the raw layer 3 checksum if enabled and the VLAN tag, if applicable. The raw checksum can be used to assist in the
verification of checksums in unsupported layer 3 protocols. RX Command C provides additional information required for
wakeup support.
TABLE 6-1:
RX COMMAND A
BITS
SYMBOL
31
ICE
DESCRIPTION
IP Checksum Error
When set, this bit indicates an error was detected in the IP checksum.
Note:
This field does not apply for IPv6 packets.
30
TCE
TCP/UDP/ICMP/IGMP Checksum Error
When set, this bit indicates an error was detected in the TCP, UDP, ICMP or IGMP
checksum.
29
IPV
IP Version
When set, indicates the frame contains an IPv6 packet. Otherwise, the frame contains
an IPv4 packet.
Note:
28:27
PID
This field is not valid if the Protocol ID is set to 00b.
Protocol ID
Indicates the L3/L4 protocol of the received packet.
00b - None IP
01b - TCP and IP
10b - UDP and IP
11b - IP
Note:
11b shall be used for ICMP and IGMP packets.
26
PFF
Perfect Filter Passed
When set, this bit indicates the frame passed a perfect filter match of the MAC
destination address. If this bit is not set, then the frame was passed due to the hash
filter and needs to be further analyzed by the Host.
25
BAM
Broadcast Frame
When set, this bit indicates that the received frame has a Broadcast address.
Note:
DS00001993F-page 44
If the destination MAC address is 0xFFFF_FFFF_FFFF then the address is
broadcast.
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
TABLE 6-1:
RX COMMAND A (CONTINUED)
BITS
SYMBOL
24
MAM
DESCRIPTION
Multicast Frame
When set, this bit indicates that the received frame has a Multicast address.
Note:
If the least significant bit of the most significant byte of the destination MAC
address is 1b, then the address is multicast. This bit is not set for a broadcast
address.
23
FVTG
Frame is VLAN tagged
When set, this bit indicates a VLAN tag was extracted from the frame. The tag is
stored in the VLAN Tag field of RX Command B.
22
RED
Receive Error Detected
When set, this bit indicates that an error was found in the received frame. One or more
of the following fields will be set: FCS, ALN, RXE, LONG, RUNT, RWT, ICE, TCE.
21
RWT
Receive Watchdog Timer Expired
When set, this bit indicates the received frame was longer than 11,264 bytes and was
truncated by the MAC.
20
RUNT
Short/Runt Frame
When set, this bit indicates that frame was prematurely terminated before the collision
window (64 bytes). Runt frames are passed on to the Host only if the Store Bad
Frames bit is set in the FIFO Controller RX FIFO Control Register (FCT_RX_CTL).
This bit is also set when a short frame has been received.
19
LONG
Frame Too Long
When set, this bit indicates that the frame length exceeds the size specified in the
Maximum Frame Size (MAX_SIZE) field of the MAC Receive Register (MAC_RX).
This is only a frame too long indication and will not cause the frame reception to be
truncated.
18
RXE
RX Error
When set, this bit indicates that a receive error (internal PHY RX error signal asserted)
was detected during frame reception.
17
ALN
Alignment Error
When set, this bit indicates that the frame contained a non-integer multiple of 8 bits
and the frame had an FCS Error.
Note:
Valid only for 10/100 mode.
16
FCS
FCS Error
When set, this bit indicates that a FCS error was detected. This bit is also set when
the internal PHY RX error signal is asserted during the reception of a frame even
though the FCS may be correct. This bit is not valid if the received frame is a Runt
frame or the Receive Watchdog Timer Expired.
15
UAM
Unicast Frame
When set, this bit indicates that the received frame has a Unicast address.
14
ICSM
Ignore TCP/UDP/ICMP/IGMP Checksum
When set, this bit indicates that the hardware was unable to calculate a UDP, TCP,
ICMP or IGMP checksum for the packet. This implies that the value of TCE is “don’t
care”.
13:0
LEN
Frame Length
The size, in bytes, of the corresponding received frame. Size of the frame received
from the network.
Note:
If the FCS Stripping bit of the MAC Receive Register (MAC_RX) is enabled,
this value is decremented by four bytes.
2021 Microchip Technology Inc. and its subsidiaries
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TABLE 6-2:
RX COMMAND B
BITS
SYMBOL
DESCRIPTION
31:16
CSUM
Raw L3 Checksum
This field contains the checksum computed for the frame over the L3 packet.
15:0
VTAG
VLAN Tag
When the Frame is VLAN tagged bit is set, this field contains the frame’s VLAN tag.
Otherwise the contents of this field are undefined.
[15:13] - PRI
[12] - CFI
[11:0] - VID
TABLE 6-3:
RX COMMAND C
BITS
SYMBOL
DESCRIPTION
15
WAKE
Wakeup Frame Received
When set, this field indicates that the corresponding frame is identified as the wakeup
frame which cause remote wakeup over USB. This bit only has meaning when
SUSPEND3 is used and Store Wakeup Frame (STORE_WAKE) is set.
14
RFE_FAIL
RFE Filter Fail
When set, this field indicates that the received wakeup frame did not pass RFE filter
rules.
This bit only has meaning when both Always Pass Wakeup Frame (PASS_WKP) and
Store Wakeup Frame (STORE_WAKE) are set and the device is in SUSPEND3.
Note:
13:0
-
This bit should never be set when Wakeup Frame Received is not set. It is
not possible for a non-wake up frame to fail RFE filtering and still be
transmitted to the host as they would have been discarded by the FCT RX
FIFO.
Reserved
APPLICATION NOTE: It is possible for a received wakeup frame to cause a USB remote wakeup but not pass the
filtering rules programmed in the RFE. In order to obviate the need for system software to
implement the RFE filtering rules on a received wakeup frame, the RFE Filter Fail bit has
been provided. This serves as an additional condition for dropping a frame such as ICE or
TCE in RX Command A.
APPLICATION NOTE: Due to race conditions relating to when the device suspends relative to the reception of
received data frames, the wakeup frame may have frame(s) preceding it in the FIFO. A
pathological worst case can exist in which the RX FIFO is completely filled with data frames
and drops the wakeup frame due to FIFO overflow error.
6.1.3
FLUSHING THE RX FIFO
The device allows for the Host to the flush the entire contents of the FCT RX FIFO. When a flush is activated, the read
and write pointers of the RX FIFO are returned to their reset state.
Before flushing the RX FIFO, the device’s receiver must be stopped, as specified in Section 6.1.3.1. Once the receiver
stop completion is confirmed, the FCT RX Enable is cleared in the FIFO Controller RX FIFO Control Register (FCT_RX_CTL) to stop RX FIFO operation. The FCT RX Disabled bit and the RX Disabled Interrupt (RX_DIS_INT) (if enabled)
DS00001993F-page 46
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
assert when the RX FIFO hardware has completed the disabling process. The FCT RX RESET bit can then be set in
the FIFO Controller RX FIFO Control Register (FCT_RX_CTL) to initiate the flush operation. This bit is cleared by the
hardware when the flush operation has completed.
Note:
RX Disabled Interrupt (RX_DIS_INT) will persist until the FCT RX Disabled status bit is cleared. The
Receiver Disabled (RXD) status bit in the MAC Receive Register (MAC_RX) must also be cleared in order
for RX_DIS_INT to de-assert. The RX Disabled Interrupt (RX_DIS_INT) is set in the Interrupt Status Register (INT_STS) and is also visible to the Host via the Interrupt Endpoint.
After the RX FIFO has been flushed, the receiver may be restarted, as specified in Section 6.1.3.1. RX FIFO operation
may then be restarted by asserting the FCT RX Enable bit.
6.1.3.1
Stopping and Starting the Receiver
To stop the receiver, the Host must clear the Receiver Enable (RXEN) bit in the MAC Receive Register (MAC_RX).
When the receiver is halted, the Receiver Disabled (RXD) bit and the RX Disabled Interrupt (RX_DIS_INT) (if enabled)
will assert. Once stopped, the host software shall flush the RX FIFO. The Host must re-enable the receiver by setting
the Receiver Enable (RXEN) bit.
Note:
6.1.3.2
RX Disabled Interrupt (RX_DIS_INT) will persist until the Receiver Disabled (RXD) status bit is cleared.
The FCT RX Disabled status bit in the FIFO Controller RX FIFO Control Register (FCT_RX_CTL) must
also be cleared in order for RX_DIS_INT to de-assert. The RX Disabled Interrupt (RX_DIS_INT) is set in
the Interrupt Status Register (INT_STS) and is also visible via the Interrupt Endpoint.
Flow Control
The FCT supports 802.3 flow control. The FCT can trigger the MAC to transmit a pause frame based upon programmable FIFO thresholds.
The FCT provides flow control on and flow control off signals to the MAC. These signals are asserted based upon the
amount of data stored in the RX FIFO and the contents of the FCT Flow Control Threshold Register (FCT_FLOW).
When the amount of FIFO data exceeds the value specified by Flow Control On Threshold field of the FCT Flow Control
Threshold Register (FCT_FLOW), the internal flow control on signal is asserted. The MAC may then (depending on the
setting of the TX Flow Control Enable (TX_FCEN) of the Flow Control Register (FLOW)) transmit a Pause frame to
instruct its link partner to halt transmission.
At some point in the future, the amount of FIFO data will fall below the value specified by Flow Control Off Threshold
field of the FCT Flow Control Threshold Register (FCT_FLOW). This, in turn, causes the internal flow control off signal
to the MAC to assert. The MAC may then (depending on the setting of TX_FCEN) transmit a Pause frame with a value
of zero. Upon reception of the pause frame, the link partner resumes transmission.
APPLICATION NOTE: In order to avoid frame drops in the RX FIFO when using jumbo frames with flow control the
maximum frame size should be restricted to 4 KB or less. Consider the scenario where the
flow control threshold is set to 4 KB. The reception of the first 4 KB frame triggers the
transmission of a Pause frame. However, the Pause frame may be blocked if the TX path is
at that moment in the process of transmitting a 4 KB packet. While the transmitter is sending
its jumbo a frame a second jumbo frame may be received followed by a third frame before
the partner has processed the Pause frame. A larger jumbo frame can result in frame drops
which would require retransmissions by a higher layer protocol in such a corner case.
6.2
TX Path (USB to Ethernet)
The 12 KB TX FIFO buffers USB Bulk Out packets received by the URX. The FCT is responsible for extracting the Ethernet frames embedded in the USB Bulk Out Packets and passing them to the MAC. The Ethernet frames are segmented
across the USB packets by the host software.
The FCT receives valid USB bulk out packets from the URX and writes them into the TX FIFO. The write side of the
FCT does not perform any processing on the USB packet data. No provisions for rewind of these packets on the write
side is required, as the URX manages its own buffer RAM, URX FIFO, and performs rewinds in the event that the Bulk
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 47
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Out Packet is errored and needs to be retransmitted by the Host. When the FCT writes the Ethernet frame into the FCT
TX FIFO RAM, it prepends a DWORD in front of the TX Command Words, used for internal processing, that contains
the length of the Ethernet frame.
The read side of the FCT TX FIFO is responsible for extracting the Ethernet frames.
The Ethernet frames may have been split across multiple USB buffers, as shown in Figure 6-2 which illustrates how
frames are stored in the URX FIFO. Figure 6-3 illustrates how Ethernet frames are stored in the FCT TX FIFO after being
read and assembled from the URX FIFO.
APPLICATION NOTE: Software shall not attempt to flush the FCT TX FIFO if there are pending IN transactions.
FIGURE 6-2:
URX FIFO RAM
TX Command B
TX Command A
USB Packet N+1
721 Byte Payload
721 Byte
Ethernet
Frame
USB Packet N
TX Command B
TX Command A
DS00001993F-page 48
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
FIGURE 6-3:
FCT TX FIFO RAM
Ethernet Frame
TX Command B
TX Command A
Frame Length
Ethernet Frame
TX Command B
TX Command A
Frame Length
Ethernet Frame
TX Command B
TX Command A
Contains frame
processing flags.
Frame Length
2021 Microchip Technology Inc. and its subsidiaries
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6.2.1
TX COMMAND FORMAT
Each buffer starts with two TX Command DWORDs, TX Command A and TX Command B, which precede the data to
be transmitted. The TX Commands instructs the FCT on the handling of the associated buffer.
The formats of TX Command A and TX Command B are shown in Table 6-4 and Table 6-5, respectively.
TX Command A contains the frame length and information to instruct how the frame must be processed. TX Command
B provides the VLAN Tag and Maximum Segment Size. The former is needed when it is desired to have a VLAN ID
inserted into the frame. The latter is used when Large Send Offload is specified. Please refer to Section 6.2.5, "VLAN
Support," on page 52 and Section 6.2.8, "Large Send Offload (LSO)," on page 54 for further details on these features.
TABLE 6-4:
TX COMMAND A
BITS
SYMBOL
31:30
RESERVED
29
IGE
DESCRIPTION
RESERVED
IGMP Checksum Offload Enable
When set, the IGMP checksum will be calculated.
Note:
28
ICE
This bit has no meaning if LSO is enabled.
ICMP/ICMPV6 Checksum Offload Enable
When set, the ICMP (IPV4)/ICMPV6(IPV6) checksum will be calculated.
Note:
This bit has no meaning if LSO is enabled.
27
LSO
Large Send Offload Enable
When set, this bit enables TCP large send offload. The TCP packet will be segmented
into blocks no larger than the amount specified by Maximum Segment Size.
26
IPE
IP Checksum Offload Enable
When set, the IP checksum will be calculated.
Note:
25
TPE
This bit has no meaning if LSO is enabled.
TCP/UDP Checksum Offload Enable
When set, the TCP/UDP will be calculated.
Note:
This bit has no meaning if LSO is enabled.
24
IVTG
Insert VLAN Tag
When set, this bit instructs the FCT to insert a VLAN tag into the frame.
23
RVTG
Replace VLAN Tag
This bit only applies if the TX frame has a pre-existing VLAN tag and the IVTG bit is
set.
When set, this bit causes the VLAN that exists in the frame to be overwritten by VLAN
Tag. Otherwise, a second tag shall be inserted between the source address and the
pre-existing tag.
22
FCS
Insert FCS and Pad
When set, an FCS is generated and inserted for the frame.The MAC will insert
padding if the frame is less than 64 bytes.
If this bit is not set, then the MAC will never insert any padding and will assume the
frame has an FCS.
21:20
RESERVED
DS00001993F-page 50
Note:
It is not valid to enable checksum offloads or VLAN insertion when this bit is
cleared. Doing so shall result in the frame being erroneous and at a minimum
having an incorrect FCS.
Note:
Zero-es are always used for padding.
RESERVED
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TABLE 6-4:
TX COMMAND A (CONTINUED)
BITS
SYMBOL
19:0
LEN
TABLE 6-5:
Frame Length [19:0]
This field indicates the size of the frame to be transmitted.
Note:
If Insert FCS and Pad is not set in this Command Word, then minimum
transmit frame length must be at least 32 bytes. Values less than 32 bytes
specified in this field when Insert FCS and Pad is clear may yield untoward
operation and unexpected results.
Note:
During LSO operation this field defines the LSO packet size.
TX COMMAND B
BITS
SYMBOL
31:30
RESERVED
29:16
MSS
15:0
DESCRIPTION
VTAG
DESCRIPTION
RESERVED
Maximum Segment Size
When LSO is enabled, this 14-bit field specifies the maximum size of the TCP
segments that are extracted from the TX IP packet.
Note:
The maximum jumbo frame size is 9 KB.
Note:
The minimum permissible value for this field is 8 bytes.
VLAN Tag
When the IVTG bit is set, a VLAN Tag will be inserted into the frame as defined by
this field.
[15:13] - PRI
[12] - CFI
[11:0] - VID
6.2.2
TX DATA FORMAT
The TX data section begins immediately after TX Command B. TX data is contiguous until the end of the buffer. The
buffer may end on a byte boundary. Unused bytes at the end of the packet will not be sent to the MAC for transmission.
6.2.3
FCT ACTIONS ON TX FIFO READ
The FCT performs basic sanity checks on the correctness of the buffer configuration, as described in Section 6.2.4, "TX
Error Detection," on page 52. Errors in this regard indicate the TX path is out of sync, which is catastrophic and requires
a reinitialization of the TX path. A TX error can only be caused by a host software error.
The FCT performs the following steps when extracting an Ethernet frame from the TX FIFO:
•
•
•
•
Strip out Frame Length DWORD
Strip out TX Command A
Strip out TX Command B
Based upon the buffer size field of TX Command A, the FCT can numerically determine any unused bytes in the
last word of the buffer. When transferring these respective DWORDs to the MAC, the FCT adjusts the byte
enables accordingly.
• Configuration information required by the MAC from TX Command A is sent to it by the FCT through sideband
channels.
Unlike the write side, the read side of the TX FIFO supports rewinds. The rewind_fr and release_fr signals from the MAC
instruct the FCT on what actions to take on the TX FIFO buffer. The rewind_fr signal is asserted by the MAC when the
frame must be re-transmitted due to a collision. When this signal is asserted, the FCT adjusts its internal read pointer
to the start of the buffer to facilitate retransmission of the frame to the MAC. The release_fr signal is asserted by the
MAC when the frame has been successfully transmitted or the maximum number of collisions has occurred. On assertion of release_fr, the FCT will purge the buffer from the TX FIFO through adjustment of its internal pointers.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 51
LAN7850
Errors are reported via the Transmitter Error (TXE) flag, which is visible to the Host via the Interrupt Endpoint and is also
set in the Interrupt Status Register (INT_STS).
6.2.4
TX ERROR DETECTION
The following error conditions indicate that the TX path is out of sync and result in the Transmitter Error (TXE) flag being
asserted:
•
•
•
•
•
•
•
•
•
MSS is less than 8 and LSO is asserted or MSS is not 0 and LSO is not asserted
LSO is asserted and detected template header size is more than 256 bytes
TX Command A[19:16] is not 0 and LSO is not asserted
TX Command A[15:0] is more than 2FF7h and LSO is not asserted (since extra 2 command words will be written
to the TX FIFO as well)
TX Command A Frame Length [19:0] field less than 32 bytes and Insert FCS and Pad is not asserted
TX Command A[23] (Replace VLAN Tag (RVTG)) = 1 and TX Command A[24] (Insert VLAN Tag (IVTG)) = 0
TX Command A[31:30] is not 0 (reserved bits)
TX Command A[21:20] is not 0 (reserved bits)
TX Command B[31:30] is not 0 (reserved bits)
Note:
The FCT can be configured to stall the Bulk Out pipe when a Transmit Error is detected. This is accomplished via the Stall Bulk-Out Pipe Disable (SBP) bit of the Hardware Configuration Register (HW_CFG).
Note:
A TX Error is a catastrophic condition that can only be caused by a host software error. The device should
be reset in order to recover from it.
6.2.5
VLAN SUPPORT
The FCT supports insertion and manipulation of VLAN tags in transmitted frames. The FCT will insert a VLAN tag when
the Insert VLAN Tag bit is set in TX Command A. In this case, the FCT will insert the tag specified by the VLAN Tag field
in TX Command B. The type field used is the default VLAN type or 8100h. An additional VLAN type can be specified by
the VLAN Type Register (VLAN_TYPE).
The FCT can also be instructed to replace a frame’s VLAN tag. This occurs when the Replace VLAN Tag bit is set in TX
Command A. In this case, the FCT will replace the existing tag with the one specified by the VLAN Tag field.
If the frame is already tagged, the FCT will insert a second VLAN tag if the Insert VLAN Tag is set and Replace VLAN
Tag is clear. The new tag will be inserted between the source address and the original VLAN tag.
Note:
The Replace VLAN Tag bit has no meaning if the frame does not have a preexisting VLAN tag.
Note:
The VLAN insertion and replacement occurs as a frame is read out of the FIFO.
6.2.6
FCS GENERATION
The TX FCT shall generate an FCS for all transmitted frames when Insert FCS and Pad bit is set in TX Command A.
DS00001993F-page 52
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
6.2.7
TRANSMIT CHECKSUM OFFLOAD
The FCT is capable of offloading the generation of IP, ICMP/ICMPV6, IGMP, TCP, and UDP checksums for transmitted
frames. The offload is enabled via the IP Checksum Offload Enable and TCP/UDP Checksum Offload Enable bits of TX
Command A. Table 6-6 summarizes the transmit checksum offload capabilities.
TABLE 6-6:
CHECKSUM OFFLOAD CAPABILITY SUMMARY
PACKET TYPE
IP
CHECKSUM
CAPABLE
TCP/UDP
CHECKSUM
CAPABLE
ICMP
CHECKSUM
CAPABLE
IGMP
CHECKSUM
CAPABLE
Type II Ethernet
Yes
Yes
Yes
Yes
SNAP Header
Yes
Yes
Yes
Yes
Single VLAN Tag
Yes
Yes
Yes
Yes
Stacked VLAN Tags
Yes
Yes
Yes
Yes
IPv4
Yes
Yes
Yes
Yes
IPv6
No
Yes
Yes
No
IP Fragment
Yes
No
No
No
IP Options
Yes
Yes
Yes
Yes
TCP or UDP Options
Yes
Yes
N/A
N/A
L4 protocol is not TCP or
UDP
Yes
No
N/A
N/A
IPv6 with IP options next
headers
Note 6-1
No
Yes
Yes
No
IPv6 tunneled over IPv4
Yes (IPv4)
Yes
Yes
No
IPv4 tunneled over IPv4
No
No
No
No
Note 6-1
Note:
Fragmentation is not supported. Hop-by-Hop, Destination, and Routing options are supported.
IPv6 does not have a header checksum.
Please refer to Section 7.2, "Checksum Offload," on page 66 for a discussion of the implementation of the checksum
offload. Section 7.2 specifically addresses the receive checksum offload case. The pseudo header formats and scope
of the checksum, however, are the same for both receive and transmit offload operations.
6.2.7.1
Configuration
In order to utilize the checksum offload, the host software performs the following steps:
1.
2.
Host software receives an IP packet from the application. The software must determine if a TCP or UDP packet
is encapsulated.
The driver must indicate the checksum calculation to be offloaded by setting the proper bits in TX Command A.
For IP checksum offload, the IP Checksum Offload Enable bit is set. For TCP or UDP checksum offload, the TCP/
UDP Checksum Offload Enable bit is set. To enable ICMP and IGMP checksums the ICMP/ICMPV6 Checksum
Offload Enable and IGMP Checksum Offload Enable bits are set respectively.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 53
LAN7850
6.2.8
LARGE SEND OFFLOAD (LSO)
Large send offload (LSO), also known as TCP Segmentation, allows the TX FCT to segment a large TCP packet into
multiple Ethernet frames. This feature relieves a significant burden on Host CPU resources.
The assertion of the Large Send Offload Enable bit in TX Command A enables this feature in the FCT. The size of the
final Ethernet frames are determined by the Maximum Segment Size field in TX Command B, and the size of the encapsulating headers. Figure 6-4 illustrates a high level view of the TCP segmentation process.
The TX FCT performs the following operations:
•
•
•
•
•
•
Breaks the large TCP packet into segments
Creates the Ethernet Header
Creates the IP Header
Creates the TCP Header
Calculates the IP checksum (IPv4 only)
Calculates the TCP checksum
FIGURE 6-4:
TCP SEGMENTATION
Template header for
segmentation. The MAC,
IP, and TCP header
templates are stored in an
on chip cache. Maximum
of 256 bytes can be
stored.
M
A
C
H
e
a
d
e
r
M
A
C
H
e
a
d
e
r
I
P
H
e
a
d
e
r
I
P
H
e
a
d
e
r
The TCP data and template headers are stored in
host memory. It may exist in a single buffer or
across multiple buffers.
T
C
P
H
e
a
d
e
r
TCP Data
T
C
P
H
e
a
d
e
r
M
A
C
TCP Data
Maximum Segment Size (MSS)
DS00001993F-page 54
H
e
a
d
e
r
I
P
H
e
a
d
e
r
T
C
P
H
e
a
d
e
r
M
A
C
TCP Data
Maximum Segment Size (MSS)
H
e
a
d
e
r
I
P
H
e
a
d
e
r
T
C
P
H
e
a
d
e
r
TCP
Data
NORMAL-Configured
Ready bit asserts after Ethernet
PHY reset is deasserted and PHY
becomes operational.
Ready bit is set.
Transition from
SUSPEND2 ->
NORMAL-Configured
Ethernet PHY is held in reset while
SUSPEND2 to save power. After
PHY reset is deasserted after moving to the Normal-Configured the
READY bit asserts.
The External Ethernet PHY is not
reset from moving to SUSPEND2.
Ready bit remains cleared until
PHY reset deasserts.
Ready bit remains cleared until
PHY reset deasserts.
PHY Reset (PHY_RST)
DS00001993F-page 152
There is no state change in
READY bit since it is set in the
NORMAL-Unconfigured state.
Ready bit does not clear when
entering SUSPEND2.
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.5
GENERAL PURPOSE IO CONFIGURATION 0 REGISTER (GPIO_CFG0)
Address:
018h
Size:
32 bits
This register configures the external GPIO[3:0] pins.
In order for a GPIO to function as a wake event or interrupt source, it must be configured as an input. GPIO pins used
to generate wake events must also be enabled by General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE).
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:12
GPIO Enable (GPIOEN)
When clear, the pin functions as a GPIO.
R/W
Note 15-11
R/W
Note 15-12
R/W
Note 15-13
R/W
Note 15-14
GPIOEN0
GPIOEN1
GPIOEN2
GPIOEN3
Note:
11:8
–
–
–
–
GPIO Buffer Type (GPIOBUF)
When set, the output buffer for the corresponding GPIO signal is configured
as a push/pull driver. When cleared, the corresponding GPIO signal is
configured as an open-drain driver. Bits are assigned as follows:
Note:
–
–
–
–
bit
bit
bit
bit
8
9
10
11
This field is protected by Reset Protection (RST_PROTECT).
GPIO Direction (GPIODIR)
When set, enables the corresponding GPIO as an output. When cleared the
GPIO is enabled as an input. Bits are assigned as follows:
GPIODIR0
GPIODIR1
GPIODIR2
GPIODIR3
Note:
3:0
12
13
14
15
This field is protected by Reset Protection (RST_PROTECT).
GPIOBUF0
GPIOBUF1
GPIOBUF2
GPIOBUF3
7:4
bit
bit
bit
bit
–
–
–
–
bit
bit
bit
bit
4
5
6
7
This field is protected by Reset Protection (RST_PROTECT).
GPIO Data (GPIOD)
When enabled as an output, the value written is reflected on GPIOn. When
read, GPIOn reflects the current state of the corresponding GPIO pin. Bits
are assigned as follows:
GPIOD0
GPIOD1
GPIOD2
GPIOD3
–
–
–
–
Note:
This field is protected by Reset Protection (RST_PROTECT).
Note 15-11
bit
bit
bit
bit
0
1
2
3
The default value of this field is determined by the value of the GPIO 0-11 Enable contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 0xF is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 0xF if neither
is present.
2021 Microchip Technology Inc. and its subsidiaries
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LAN7850
Note 15-12 The default value of this field is determined by the value of the GPIO 0-11 Buffer contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 0x0 is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 0x0 if neither
is present.
Note 15-13 The default value of this field is determined by the value of the GPIO 0-11 Direction contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 0x0 is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 0x0 if neither
is present.
Note 15-14 The default value of this field is determined by the value of the GPIO 0-11 Data contained within the
EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If OTP
is not configured then 0x0 is the default. A USB Reset or Lite Reset (LRST) will cause this field to
be restored to the image value last loaded from EEPROM, or OTP, or to be set to 0x0 if neither is
present. In the event that the GPIO is configured as an input the default state is unknown.
15.1.6
GENERAL PURPOSE IO CONFIGURATION 1 REGISTER (GPIO_CFG1)
Address:
01Ch
Size:
32 bits
This register configures the external GPIO[4:11] pins.
In order for a GPIO to function as a wake event or interrupt source, it must be configured as an input. GPIOs used as
wake events must also be enabled by General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE).
BITS
31:24
DESCRIPTION
GPIO Enable (GPIOEN)
When clear, the pin functions as a GPIO.
TYPE
DEFAULT
R/W
Note 15-15
R/W
Note 15-12
GPIOEN4 - bit 24
GPIOEN5 - bit 25
GPIOEN6 - bit 26
GPIOEN7 - bit 27
GPIOEN8 - bit 28
GPIOEN9 - bit 29
GPIOEN10 - bit 30
GPIOEN11 - bit 31
Note:
23:16
This field is protected by Reset Protection (RST_PROTECT).
GPIO Buffer Type (GPIOBUF)
When set, the output buffer for the corresponding GPIO signal is configured
as a push/pull driver. When cleared, the corresponding GPIO signal is
configured as an open-drain driver.
GPIOBUF4 - bit 16
GPIOBUF5 - bit 17
GPIOBUF6 - bit 18
GPIOBUF7 - bit 19
GPIOBUF8 - bit 20
GPIOBUF9 - bit 21
GPIOBUF10 - bit 22
GPIOBUF11 - bit 23
Note:
This field is protected by Reset Protection (RST_PROTECT).
DS00001993F-page 154
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
BITS
15:8
DESCRIPTION
GPIO Direction (GPIODIR)
When set, enables the corresponding GPIO as output. When cleared, the
GPIO is enabled as an input.
TYPE
DEFAULT
R/W
Note 15-13
R/W
Note 15-14
GPIODIR4 - bit 8
GPIODIR5 - bit 9
GPIODIR6 - bit 10
GPIODIR7 - bit 11
GPIODIR8 - bit 12
GPIODIR9 - bit 13
GPIODIR10 - bit 14
GPIODIR11 - bit 15
Note:
7:0
This field is protected by Reset Protection (RST_PROTECT).
GPIO Data (GPIOD)
When enabled as an output, the value written is reflected on GPIOn. When
read, GPIOn reflects the current state of the corresponding GPIO pin.
GPIOD4 - bit 0
GPIOD5 - bit 1
GPIOD6 - bit 2
GPIOD7 - bit 3
GPIOD8 - bit 4
GPIOD9 - bit 5
GPIOD10 - bit 6
GPIOD11 - bit 7
Note:
This field is protected by Reset Protection (RST_PROTECT).
Note 15-15 The default value of this field is determined by the value of the GPIO 0-11 Enable contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 0xFF is the default. A USB Reset or Lite Reset (LRST) will cause this
field to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 0xFF if
neither is present.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 155
LAN7850
15.1.7
GENERAL PURPOSE IO WAKE ENABLE AND POLARITY REGISTER (GPIO_WAKE)
Address:
020h
Size:
32 bits
This register enables the GPIOs to function as wake events for the device when asserted. It also allows the polarity used
for a wake event/interrupt to be configured.
Note:
GPIOs must not cause a wake event to the device when not configured as a GPIO.
BITS
DESCRIPTION
TYPE
DEFAULT
31:28
RESERVED
RO
-
27:16
GPIO Polarity 0-11 (GPIOPOL[11:0])
R/W
Note 15-16
RESERVED
RO
-
GPIO Wake 0-11 (GPIOWK[11:0])
R/W
Note 15-16
0 = Wakeup/interrupt is triggered when GPIO is driven low
1 = Wakeup/interrupt is triggered when GPIO is driven high
GPIOPOL0 - bit 16
GPIOPOL1 - bit 17
GPIOPOL2 - bit 18
GPIOPOL3 - bit 19
GPIOPOL4 - bit 20
GPIOPOL5 - bit 21
GPIOPOL6 - bit 22
GPIOPOL7 - bit 23
GPIOPOL8 - bit 24
GPIOPOL9 - bit 25
GPIOPOL10 - bit 26
GPIOPOL11 - bit 27
Note:
15:12
11:0
This field is protected by Reset Protection (RST_PROTECT).
0 = The GPIO can not wake up the device.
1 = The GPIO can trigger a wake up event.
GPIOWK0 - bit 0
GPIOWK1 - bit 1
GPIOWK2 - bit 2
GPIOWK3 - bit 3
GPIOWK4 - bit 4
GPIOWK5 - bit 5
GPIOWK6 - bit 6
GPIOWK7 - bit 7
GPIOWK8 - bit 8
GPIOWK9 - bit 9
GPIOWK10 - bit 10
GPIOWK11 - bit 11
Note:
This field is protected by Reset Protection (RST_PROTECT).
Note 15-16 The default value of this field is loaded from the associated bytes of the EEPROM. The high order,
unused bits, of the EEPROM are ignored. If no EEPROM is present then default depends on the
OTP programmed value. It the OTP is not programmed than 0h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, OTP,
or to be set to 0h if neither is available.
DS00001993F-page 156
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.8
DATA PORT SELECT REGISTER (DP_SEL)
Offset:
024h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
Data Port Ready (DPRDY)
The Data Port Ready bit indicates when the data port RAM access has
completed. In the case of a read operation, this bit indicates when the read
data has been stored in the DP_DATA register
RO
1b
1 = Data Port is ready.
0 = Data Port is busy processing a transaction.
30:4
RESERVED
RO
-
3:0
Select (SEL)
Selects which RAM to access.
R/W
0000b
0000 = URX Buffer RAM (Do not access at run time)
0001 = RFE VLAN and DA Hash Table (VHF RAM)
0010 = LSO Header RAM (Do not access at run time)
0011 = FCT RX RAM (Do not access at run time)
0100 = FCT TX RAM (Do not access at run time)
0101 = Descriptor RAM (Do not access at run time)
0110 = RESERVED
0111 = UTX Buffer RAM (Do not access at run time)
1000 = RESERVED
1001 = RESERVED
1010 = RESERVED
1011 = RESERVED
1100 = RESERVED
1101 = RESERVED
1110 = RESERVED
1111 = RESERVED
15.1.9
DATA PORT COMMAND REGISTER (DP_CMD)
Offset:
028h
Size:
32 bits
This register commences the data port access. Writing a one to this register will enable a write access, while writing a
zero will do a read access.
The address and data registers need to be configured appropriately for the desired read or write operation before
accessing this register.
BITS
31:1
0
DESCRIPTION
TYPE
DEFAULT
RESERVED
RO
-
Data Port Write. Selects operation. Writing to this bit initiates the dataport
access.
R/W
0b
1 = Write operation
0 = Read operation
2021 Microchip Technology Inc. and its subsidiaries
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LAN7850
15.1.10
DATA PORT ADDRESS REGISTER (DP_ADDR)
Offset:
02Ch
Size:
32 bits
Indicates the address to be used for the data port access.
BITS
DESCRIPTION
TYPE
DEFAULT
31:14
RESERVED
RO
-
13:0
Data Port Address[13:0]
R/W
0000h
15.1.11
DATA PORT DATA REGISTER (DP_DATA)
Offset:
030h
Size:
32 bits
The Data Port Data register holds the write data for a write access and the resultant read data for a read access.
Before reading this register for the result of a read operation, the Data Port Ready bit should be checked. The Data Port
Ready bit must indicate the data port is ready. Otherwise the read operation is still in progress.
BITS
31:0
15.1.12
DESCRIPTION
Data Port Data (DATA_PORT_DATA)
TYPE
DEFAULT
R/W
0000_0000h
EEPROM COMMAND REGISTER (E2P_CMD)
Offset:
040h
Size:
32 bits
This register is used to control the read and write operations on the Serial EEPROM.
BITS
DESCRIPTION
TYPE
DEFAULT
31
EPC Busy (EPC_BSY)
When a “1” is written into this bit, the operation specified in the EPC
Command field is performed at the specified EEPROM address. This bit will
remain set until the operation is at which time it will clear. In the case of a
read, this means that the Host can read valid data from the EEPROM Data
Register (E2P_DATA). The E2P_CMD and E2P_DATA registers should not
be modified until this bit is cleared. In the case where a write is attempted
and an EEPROM is not present, the EPC Busy remains busy until the EPC
Time-out occurs. At that time, the busy bit is cleared.
SC
0b
DS00001993F-page 158
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
BITS
DESCRIPTION
TYPE
DEFAULT
30:28
EPC Command (EPC_CMD)
This field is used to issue commands to the EEPROM Controller. The EPC
will execute commands when the EPC Busy bit is set. A new command must
not be issued until the previous command completes. This field is encoded
as follows:
R/W
000b
RO
-
000 = READ
001 = EWDS
010 = EWEN
011 = WRITE
100 = WRAL
101 = ERASE
110 = ERAL
111 = RELOAD
READ (Read Location): This command will cause a read of the EEPROM
location pointed to by EPC Address (EPC_ADDR). The result of the read is
available in the E2P_DATA register.
EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase
and write commands. To re-enable erase/write operations, issue the EWEN
command.
EWEN (Erase/Write Enable): Enables the EEPROM for erase and write
operations. The EEPROM will allow erase and write operations until the
Erase/Write Disable command is sent, or until power is cycled.
Note:
The EEPROM device will power-up in the erase/write-disabled
state. Any erase or write operations will fail until an Erase/Write
Enable command is issued.
WRITE (Write Location): If erase/write operations are enabled in the
EEPROM, this command will cause the contents of the E2P_DATA register
to be written to the EEPROM location selected by the EPC Address
(EPC_ADDR) field.
WRAL (Write All): If erase/write operations are enabled in the EEPROM,
this command will cause the contents of the E2P_DATA register to be written
to every EEPROM memory location.
ERASE (Erase Location): If erase/write operations are enabled in the
EEPROM, this command will erase the location selected by the EPC
Address (EPC_ADDR) field.
ERAL (Erase All): If erase/write operations are enabled in the EEPROM,
this command will initiate a bulk erase of the entire EEPROM.
RELOAD (Data Reload): Instructs the EEPROM Controller to reload the
data from the EEPROM. If a value of A5h is not found in the first address of
the EEPROM, the EEPROM is assumed to be un-programmed and the
Reload operation will fail. The EPC Data Loaded (EPC_DL) bit indicates a
successful load of the data.
Note:
27:11
A failed reload operation will result in no change to descriptor
information or register contents. These items will not be set to
default values as a result of the reload failure.
RESERVED
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 159
LAN7850
BITS
DESCRIPTION
TYPE
DEFAULT
10
EPC Time-out (EPC_TO)
If an EEPROM operation is performed, and there is no response from the
EEPROM within 30mS, the EEPROM Controller will time-out and return to
its idle state. This bit is set when a time-out occurs, indicating that the last
operation was unsuccessful.
R/WC
0b
Note:
If the EEDI pin is pulled-high (default if left unconnected), EPC
commands will not time out if the EEPROM device is missing. In
this case, the EPC Busy bit will be cleared as soon as the
command sequence is complete. It should also be noted that the
ERASE, ERAL, WRITE and WRAL commands are the only EPC
commands that will time-out if an EEPROM device is not present
and the EEDI signal is pulled low.
9
EPC Data Loaded (EPC_DL)
When set, this bit indicates that a valid EEPROM was found, and that the
MAC Address and default register programming has completed normally.
This bit is set after a successful load of the data after power-up, or after a
RELOAD command has completed.
R/WC
0b
8:0
EPC Address (EPC_ADDR)
The 9-bit value in this field is used by the EEPROM Controller to address a
specific memory location in the Serial EEPROM. This is a BYTE aligned
address.
R/W
00h
15.1.13
EEPROM DATA REGISTER (E2P_DATA)
Offset:
044h
Size:
32 bits
This register is used in conjunction with the E2P_CMD register to perform read and write operations to the Serial
EEPROM.
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
RESERVED
RO
-
7:0
EEPROM Data (EPC_DATA)
Value read from or written to the EEPROM.
R/W
-
DS00001993F-page 160
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.14
BOS DESCRIPTOR ATTRIBUTES REGISTER (BOS_ATTR)
Offset:
050h
Size:
32 bits
This register sets the length values for BOS Block contents that have been loaded into Descriptor RAM via the Data
Port registers. The Descriptor RAM images may be used, in conjunction with this register, to facilitate customized operation when no EEPROM is present and OTP is not configured.
Note:
• If the block does not exist in Descriptor RAM, its size value must be written as 00h.
• This register only affects system operation when an EEPROM is not present, OTP is not configured and the
EEPROM Emulation Enable (EEM) bit indicates Descriptor RAM and the Attributes Registers are to be used for
descriptor processing.
• Writing to this register when an EEPROM is present or OTP is configured is prohibited and shall result in untoward operation and unexpected results.
• This register is protected by Reset Protection (RST_PROTECT).
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
RESERVED
RO
-
7:0
BOS Block Size (BOS_BLOCK_SIZE)
Note 15-17
R/W
Note 15-18
Note 15-17 If this field is not 0, the block must include Binary Object Store (BOS) Descriptor; and may include
USB 2.0 Extension Descriptor, and Container ID Descriptor.
Note 15-18 The default value of this field is determined by the value of the Binary Object Store (BOS) Block
Length (Bytes) contained within the EEPROM, if present. If no EEPROM is present then default
depends on the OTP programmed value. It the OTP is not programmed then 00h is the default. A
USB Reset or Lite Reset (LRST) will cause this field to be restored to the image value last loaded
from EEPROM, OTP, or to be set to 00h if neither is available.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 161
LAN7850
15.1.15
HS DESCRIPTOR ATTRIBUTES REGISTER (HS_ATTR)
Address:
058h
Size:
32 bits
This register sets the length values for HS descriptors that have been loaded into Descriptor RAM via the Data Port
registers. The HS Polling interval is also defined by a field within this register. The Descriptor RAM images may be used,
in conjunction with this register, to facilitate customized operation when no EEPROM is present or OTP is not configured.
Note:
• If a descriptor does not exist in Descriptor RAM, its size value must be written as 00h.
• This register only affects system operation when an EEPROM is not present, OTP is not configured, and the
EEPROM Emulation Enable (EEM) bit indicates Descriptor RAM and the Attributes Registers are to be used for
descriptor processing.
• Writing to this register when an EEPROM is present or OTP is configured is prohibited and will result in untoward
operation and unexpected results.
• This register is protected by Reset Protection (RST_PROTECT).
BITS
DESCRIPTION
TYPE
DEFAULT
31:24
RESERVED
RO
-
23:16
HS Polling Interval (HS_POLL_INT)
R/W
Note 15-19
15:8
HS Device Descriptor Size (HS_DEV_DESC_SIZE) Note 15-20
R/W
Note 15-21
7:0
HS Configuration Descriptor Size (HS_CFG_DESC_SIZE) Note 15-20
R/W
Note 15-22
Note 15-19 The default value of this field is determined by the value of the High-Speed Polling Interval for
Interrupt Endpoint contained within the EEPROM, if present. If no EEPROM is present then the vale
programmed in OTP is used. If OTP is not configured then 04h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 04h if neither is present.
Note 15-20 The only legal values are 0 and 12h. Writing any other values will result in untoward behavior and
unexpected results.
Note 15-21 The default value of this field is determined by the value of the High-Speed Device Descriptor (bytes)
contained within the EEPROM, if present. If no EEPROM is present then the vale programmed in
OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite Reset (LRST)
will cause this field to be restored to the image value last loaded from EEPROM, or OTP, or to be
set to 00h if neither is present.
Note 15-22 The default value of this field is determined by the value of the High-Speed Configuration and
Interface Descriptor Length (bytes) contained within the EEPROM, if present. If no EEPROM is
present then the vale programmed in OTP is used. If OTP is not configured then 00h is the default.
A USB Reset or Lite Reset (LRST) will cause this field to be restored to the image value last loaded
from EEPROM, or OTP, or to be set to 00h if neither is present.
DS00001993F-page 162
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.16
FS DESCRIPTOR ATTRIBUTES REGISTER (FS_ATTR)
Address:
05Ch
Size:
32 bits
This register sets the length values for FS descriptors that have been loaded into Descriptor RAM via the Data Port registers. The FS Polling interval is also defined by a field within this register. The Descriptor RAM images may be used,
in conjunction with this register, to facilitate customized operation when no EEPROM is present or OTP is not configured.
Note:
• If a descriptor does not exist in Descriptor RAM, its size value must be written as 00h.
• This register only affects system operation when an EEPROM is not present, OTP is not configured, and the
EEPROM Emulation Enable (EEM) bit indicates Descriptor RAM and the Attributes Registers are to be used for
descriptor processing.
• Writing to this register when an EEPROM is present or OTP is configured is prohibited and will result in untoward
operation and unexpected results.
• This register is protected by Reset Protection (RST_PROTECT)
BITS
DESCRIPTION
TYPE
DEFAULT
31:24
RESERVED
RO
-
23:16
FS Polling Interval (FS_POLL_INT)
R/W
Note 15-23
15:8
FS Device Descriptor Size (FS_DEV_DESC_SIZE) Note 15-24
R/W
Note 15-25
7:0
FS Configuration Descriptor Size (FS_CFG_DESC_SIZE) Note 15-24
R/W
Note 15-26
Note 15-23 The default value of this field is determined by the value of the Full-Speed Polling Interval for Interrupt
Endpoint contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 01h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 01h if neither is present.
Note 15-24 The only legal values are 0 and 12h. Writing any other values will result in untoward behavior and
unexpected results.
Note 15-25 The default value of this field is determined by the value of the Full-Speed Device Descriptor Length
(bytes) contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
Note 15-26 The default value of this field is determined by the value of the Full-Speed Configuration and Interface
Descriptor Length (bytes) contained within the EEPROM, if present. If no EEPROM is present then
the vale programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset
or Lite Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM,
or OTP, or to be set to 00h if neither is present.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 163
LAN7850
15.1.17
STRING ATTRIBUTES REGISTER 0 (STRNG_ATTR0)
Offset:
060h
Size:
32 bits
This register sets the length values for the named string descriptors that have been loaded into Descriptor RAM via the
Data Port registers. The Descriptor RAM images may be used, in conjunction with this register, to facilitate customized
operation when no EEPROM is present or OTP is not configured.
Note:
• If a descriptor does not exist in Descriptor RAM, its size value must be written as 00h.
• This register only affects system operation when an EEPROM is not present, OTP is not configured, and the
EEPROM Emulation Enable (EEM) bit indicates Descriptor RAM and the Attributes Registers are to be used for
descriptor processing.
• Writing to this register when an EEPROM is present or OTP is configured is prohibited and will result in untoward
operation and unexpected results.
• This register is protected by Reset Protection (RST_PROTECT).
BITS
DESCRIPTION
TYPE
DEFAULT
31:24
Configuration String Descriptor Size (CFGSTR_DESC_SIZE)
R/W
Note 15-27
23:16
Serial Number String Descriptor Size (SERSTR_DESC_SIZE)
R/W
Note 15-28
15:8
Product Name String Descriptor Size (PRODSTR_DESC_SIZE)
R/W
Note 15-29
7:0
Manufacturing String Descriptor Size (MANUF_DESC_SIZE)
R/W
Note 15-30
Note 15-27 The default value of this field is determined by the value of the Configuration String Descriptor Length
(bytes) contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
Note 15-28 The default value of this field is determined by the value of the Serial Number String Descriptor
Length (bytes) contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
Note 15-29 The default value of this field is determined by the value of the Product Name String Descriptor
Length (bytes) contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
Note 15-30 The default value of this field is determined by the value of the Manufacturer ID String Descriptor
Length (bytes) contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
DS00001993F-page 164
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.18
STRING ATTRIBUTES REGISTER 1 (STRNG_ATTR1)
Offset:
064h
Size:
32 bits
This register sets the length values for the named string descriptors that have been loaded into Descriptor RAM via the
Data Port registers. The Descriptor RAM images may be used, in conjunction with this register, to facilitate customized
operation when no EEPROM is present or OTP is not configured.
Note:
• If a descriptor does not exist in Descriptor RAM, its size value must be written as 00h.
• This register only affects system operation when an EEPROM is not present, OTP is not configured, and the
EEPROM Emulation Enable (EEM) bit indicates Descriptor RAM and the Attributes Registers are to be used for
descriptor processing.
• Writing to this register when an EEPROM is present or OTP is configured is prohibited and will result in untoward
operation and unexpected results.
• This register is protected by Reset Protection (RST_PROTECT).
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
RESERVED
RO
-
7:0
Interface String Descriptor Size (INTSTR_DESC_SIZE)
R/W
Note 15-31
Note 15-31 The default value of this field is determined by the value of the Interface String Descriptor Length
(bytes) contained within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
15.1.19
FLAG ATTRIBUTES REGISTER (FLAG_ATTR)
Offset:
068h
Size:
32 bits
This register sets the value of the GPIO PME Flags 0 and GPIO PME Flags 1 when no EEPROM is present and customized operation, using Descriptor RAM images, is to occur.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:8
GPIO PME Flags 1 (PME_FLAGS1)
Refer to Table 10-4, “GPIO PME Flags 1,” on page 107 for bit definitions.
R/W
Note 15-33
R/W
Note 15-32
Note:
7:0
This field is protected by Reset Protection (RST_PROTECT).
GPIO PME Flags 0 (PME_FLAGS0)
Refer to Table 10-3, “GPIO PME Flags 0,” on page 106 for bit definitions.
Note:
This field is protected by Reset Protection (RST_PROTECT).
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 165
LAN7850
Note 15-32 The default value of this field is determined by the value of the GPIO PME Flags 0 contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 00h is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 00h if neither
is present.
Note 15-33 The default value of this field is determined by the value of the GPIO PME Flags 1 contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 00h is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 00h if neither
is present.
15.1.20
SOFTWARE GENERAL PURPOSE REGISTER X (SW_GPX)
Offset:
06Ch - 077h
Size:
32 bits
The device implements three general purpose registers for use by host software.
BITS
31:0
DESCRIPTION
Software General Purpose Register (SW_GPx)
Note:
TYPE
DEFAULT
R/W
0h
This field is protected by Reset Protection (RST_PROTECT).
DS00001993F-page 166
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.21
USB CONFIGURATION REGISTER 0 (USB_CFG0)
Offset:
BITS
080h
Size:
32 bits
DESCRIPTION
TYPE
DEFAULT
31
RESERVED
RO
-
30
LPM Capability (LPM_CAP)
This bit enables the support of the Link Power Management (LPM) protocol.
R/W
Note 15-36
R/W
Note 15-34
0: LPM capability is not enabled.
1: LPM capability is enabled.
Note:
29
This field is protected by Reset Protection (RST_PROTECT).
Suspend Enable (SUSP_EN)
When cleared this bit prevents the SUSPEND_N pin from asserting a
suspend. Under normal operation when Suspend conditions are valid, the
USB PHY enters suspend mode when this bit is set.
Note:
This field is protected by Reset Protection (RST_PROTECT).
28:16
RESERVED
RO
-
15:13
Device Speed to Connect (DEV_SPEED)
R/W
000b
RESERVED
RO
-
10
USB Bulk-In Transmitter (UTX) RESET
When set, the UTX is reset.
SC
0b
9
USB Bulk-Out Receiver (URX) RESET
When set, the URX is reset.
SC
0b
RESERVED
RO
-
Bulk-In Empty Response (BIR)
This bit controls the response to Bulk-In tokens when the RX FIFO is empty.
R/W
0b
R/W
0b
RO
Note 15-35
RO
-
000: High-Speed
001: Full-Speed
Note:
12:11
8:7
6
This field is protected by Reset Protection (RST_PROTECT).
0 = Respond to the IN token with a ZLP
1 = Respond to the IN token with a NAK
5
Burst Cap Enable (BCE)
This register enables use of the Burst Cap Register (BURST_CAP).
0 = Burst Cap register is not used to limit the TX burst size.
1 = Burst Cap register is used to limit the TX burst size.
4
Port Swap (PORT_SWAP)
Swaps the mapping of USB_DP and USB_DM.
0 = USB_DP maps to USB D+ and USB_DM maps to USB D-.
1 = USB_DP maps to USB D- and USB_DM maps to USB D+.
3
RESERVED
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 167
LAN7850
BITS
2
DESCRIPTION
Remote Wakeup Support (RMT_WKP)
0 = Device does not support remote wakeup.
1 = Device supports remote wakeup.
TYPE
DEFAULT
R/W
Note 15-36
R/W
Note 15-37
R/W
0b
This bit must be set for both DEVICE_REMOTE_WAKEUP and
FUNCTION_REMOTE_WAKEUP to be supported.
Note:
1
This field is protected by Reset Protection (RST_PROTECT).
Power Method (PWR_SEL)
This bit controls the device’s USB power mode.
0 = The device is bus powered.
1 = The device is self powered.
Note:
0
This field is protected by Reset Protection (RST_PROTECT).
Stall Bulk-Out Pipe Disable (SBP)
This bit controls the operation of the Bulk-Out pipe when the FIFO Controller
detects the loss of sync condition. Please refer to Section 6.2.4, "TX Error
Detection" for details.
0 = Stall the Bulk-Out pipe when loss of sync detected.
1 = Do not stall the Bulk-Out pipe when loss of sync detected.
Note 15-34 The default value of this field is determined by Suspend Enable (SUSP_EN) bit of the Configuration
Flags 0 field contained within the EEPROM, if present. If no EEPROM is present then default
depends on the OTP programmed value. It the OTP is not programmed then 1b is the default. A USB
Reset or Lite Reset (LRST) will cause this field to be restored to the image value last loaded from
EEPROM, OTP, or to be set to 1b if neither is available.
Note 15-35 The default value of this field is determined by Port Swap (CFG0_PORT_SWAP) bit of the
Configuration Flags 0 field contained within the EEPROM, if present. If no EEPROM is present then
default depends on the OTP programmed value. It the OTP is not programmed then 0b is the default.
A USB Reset or Lite Reset (LRST) will cause this field to be restored to the image value last loaded
from EEPROM, OTP, or to be set to 0b if neither is available.
Note 15-36 The default value of this field is determined by the respective bit of the Configuration Flags 0 field
contained within the EEPROM, if present. If no EEPROM is present then default depends on the OTP
programmed value. It the OTP is not programmed then 1b is the default. A USB Reset or Lite Reset
(LRST) will cause this field to be restored to the image value last loaded from EEPROM, OTP, or to
be set to 1b if neither is available.
Note 15-37 The default value of this field is determined by the value of the Power Method (CFG0_PWR_SEL)
bit of Configuration Flags 0 contained within the EEPROM, if present. If no EEPROM is present, 1b
is the default. A USB Reset or Lite Reset (LRST) will cause this field to be restored to the image
value last loaded from EEPROM, or to be set to 1b if no EEPROM is present.
DS00001993F-page 168
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.22
USB CONFIGURATION REGISTER 1 (USB_CFG1)
Offset:
BITS
084h
Size:
32 bits
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:13
HS Timeout Calibration (HS_TOUT_CAL)
The number of PHY clocks are indicated in this field. The controller multiplies
this number by a bit-time factor, then adds the product to the high-speed
inter-packet timeout duration in the core. This result accounts for additional
delays introduced by the PHY. This is required because the delay introduced
by generating the line-state condition varies among PHYs.
R/W
Note 15-40
The USB standard timeout value for high-speed operation is 736 to 816
(inclusive) bit times. The number of bit times added per PHY clock are:
High-speed operation:
One 30-MHz PHY clock = 16 bit times.
One 60-MHz PHY clock = 8 bit times.
Note:
Only 60 MHz operation is supported in this device.
12:7
RESERVED
RO
-
6:4
FS Timeout Calibration (FS_TOUT_CAL)
The number of PHY clocks are indicated in this field. The controller multiplies
this number by a bit-time factor, then adds the product to the full-speed interpacket timeout duration in the core. This result accounts for additional delays
introduced by the PHY. This is required because the delay introduced by
generating the line-state condition varies among PHYs.
R/W
Note 15-41
The USB standard timeout value for full-speed operation is 16 to 18
(inclusive) bit times. The number of bit times added per PHY clock are:
Full-speed operation:
• One 30-MHz PHY clock = 0.4 bit times.
• One 60-MHz PHY clock = 0.2 bit times.
• One 48-MHz PHY clock = 0.25 bit times
Note:
Only 60 MHz operation is supported in this device.
3:2
RESERVED
RO
-
1:0
Scale Down Mode
Scale down mode to reduce simulation time. When Scale-Down mode is
enabled: Core uses scaled-down timing values, resulting in faster
simulations.
RW
00b
When Scale-Down mode is disabled: Core uses actual timing values, as
required for hardware operation.
Scale-down status for HS/FS/LS Modes
• 00: Disabled. Actual timing values are used.
• 01: Enabled for all timing values except Device mode suspend and
resume, including speed enumeration.
• 10: Enabled for only Device mode suspend and resume.
• 11: Enabled bit 0 and bit 1 scale-down values.
Note:
This field is for simulation only and should be set to 00b for normal
operation.
2021 Microchip Technology Inc. and its subsidiaries
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LAN7850
Note 15-38 The default value of this field is determined by the respective bit in of Configuration Flags 0 within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 0b is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 0b if neither is
present.
Note 15-39 The default value of this field is determined by the respective bit in of Configuration Flags 0 within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then 1b is the default. A USB Reset or Lite Reset (LRST) will cause this field
to be restored to the image value last loaded from EEPROM, or OTP, or to be set to 1b if neither is
present.
Note 15-40 The default value of this field is determined by the value of HS Timeout Calibration (HS_TOutCal) in
Configuration Flags 2 within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
Note 15-41 The default value of this field is determined by the value of FS Timeout Calibration (FS_TOutCal) in
Configuration Flags 2 within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 00h is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 00h if neither is present.
15.1.23
USB CONFIGURATION REGISTER 2 (USB_CFG2)
Offset:
BITS
088h
Size:
32 bits
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:0
HS Detach Time (HS_DETACH)
Indicates amount of time, in ms, the device shall detach from the USB bus
after Soft Reset is requested when operating in high-speed or full-speed
mode.
R/W
Note 15-42
Note:
This field is protected by Reset Protection (RST_PROTECT).
Note 15-42 The default value of this field is determined by the value of HS Detach Time (HS_DETACH) of
Configuration Flags 3 within the EEPROM, if present. If no EEPROM is present then the value
programmed in OTP is used. If OTP is not configured then 0x0A is the default. A USB Reset or Lite
Reset (LRST) will cause this field to be restored to the image value last loaded from EEPROM, or
OTP, or to be set to 0x0A if neither is present.
DS00001993F-page 170
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.24
BURST CAP REGISTER (BURST_CAP)
Address:
090h
Size:
32 bits
This register is used to limit the size of the data burst transmitted by the USB Bulk-In Transmitter (UTX). When the
amount specified in the BURST_CAP register is transmitted, the UTX will send a ZLP.
Note:
This register must be enabled through the USB Configuration Register 0 (USB_CFG0).
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
RESERVED
RO
-
7:0
BURST_CAP
The maximum amount of contiguous data that may be transmitted by the
UTX before a ZLP or short packet is sent. This field has units of 512 bytes
for HS mode and 64 bytes for FS mode.
R/W
00h
TYPE
DEFAULT
15.1.25
Note:
The amount of contiguous data specified must be >= the Maximum
Frame Size (MAX_SIZE) specified in the MAC_RX register. Failure
to obey this rule may result in untoward operation and may yield
unpredictable results.
Note:
The device will disable the BURST_CAP function if the setting is
less than or equal to 2048 bytes.
BULK-IN DELAY REGISTER (BULK_IN_DLY)
Address:
BITS
094h
Size:
32 bits
DESCRIPTION
31:16
RESERVED
RO
-
15:0
Bulk In Delay
Before sending a short packet, or ZLP, the USB Bulk-In Transmitter (UTX)
waits the delay specified by this register.
R/W
0800h
This register has units of 16.667 ns and a default interval of 34.133 us.
2021 Microchip Technology Inc. and its subsidiaries
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15.1.26
INTERRUPT ENDPOINT CONTROL REGISTER (INT_EP_CTL)
Address:
098h
Size:
32 bits
This register determines which events cause status to be reported by the interrupt endpoint. Please refer to Section 5.5,
"Interrupt Endpoint," on page 31 for further details.
BITS
DESCRIPTION
TYPE
DEFAULT
31
Interrupt Endpoint Always On (INTEP_ON)
When this bit is set, an interrupt packet will always be sent at the interrupt
endpoint interval.
R/W
0b
RESERVED
RO
-
OTP Write Done Enable (OTP_WR_DONE_EN)
R/W
0b
0 = Only allow the transmission of an interrupt packet when an interrupt
source is enabled and occurs.
1 = Always transmit an interrupt packet at the interrupt interval.
30:29
28
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
27
RESERVED
RO
-
26
Energy Efficient Ethernet Start TX Low Power Enable
(EEE_START_TX_LPI_EN)
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
25
Energy Efficient Ethernet Stop TX Low Power Enable
(EEE_STOP_TX_LPI_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
24
Energy Efficient Ethernet RX Low Power Enable (EEE_RX_LPI_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
23
MAC Reset Time Out (MACRTO_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
22
RX Data FIFO Overflow Enable (RDFO_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
21
Transmit Error Enable (TXE_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
20
USB Status Interrupt Enable (USB_STS_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
DS00001993F-page 172
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BITS
19
DESCRIPTION
TX Disabled Interrupt Enable (TX_DIS_EN)
TYPE
DEFAULT
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
18
RX Disabled Interrupt Enable (RX_DIS_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
17
PHY Interrupt Enable (PHY_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
16
Data Port Interrupt Enable (DP_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
15
MAC Error Interrupt Enable (MAC_ERR_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
14
TX Data FIFO Under-run Interrupt Enable (TDFU_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
13
TX Data FIFO Overrun Interrupt Enable (TDFO_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
12
USB Bulk-In Transmitter (UTX) Frame Pending Enable (UTX_FP_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
11:0
GPIOx Interrupt Enable (GPIOx_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
2021 Microchip Technology Inc. and its subsidiaries
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15.1.27
PIPE CONTROL REGISTER (PIPE_CTL)
Address:
BITS
31:7
6
DEFAULT
RESERVED
RO
-
TX Swing (TxSwing)
Refer to table 5-3 of the PIPE3 specification.
R/W
Note 15-43
R/W
Note 15-44
R/W
Note 15-45
R/W
Note 15-46
This field is protected by Reset Protection (RST_PROTECT).
TX Margin (TxMargin)
Refer to table 5-3 of the PIPE3 specification.
This field is protected by Reset Protection (RST_PROTECT).
TX Deemphasis (TxDeemphasis)
Refer to table 5-3 of the PIPE3 specification.
Note:
0
32 bits
TYPE
Note:
2:1
Size:
DESCRIPTION
Note:
5:3
09Ch
This field is protected by Reset Protection (RST_PROTECT).
Elasticity Buffer Mode (ElasticityBufferMode)
Refer to table 5-3 of the PIPE3 specification.
Note:
This field is protected by Reset Protection (RST_PROTECT).
Note 15-43 The default value of this field is determined by the value of the TX Swing (TxSwing) bit of
Configuration Flags 1 contained within the EEPROM, if present. If no EEPROM is present then
default depends on the OTP programmed value. It the OTP is not programmed then 0b is the default.
A USB Reset or Lite Reset (LRST) shall cause this field to be restored to the image value last loaded
from EEPROM, OTP, or to be set to 0b if neither is available.
Note 15-44 The default value of this field is determined by the value of the TX Margin (TxMargin) bit of
Configuration Flags 1 contained within the EEPROM, if present. If no EEPROM is present then
default depends on the OTP programmed value. It the OTP is not programmed then 0b is the default.
A USB Reset or Lite Reset (LRST) shall cause this field to be restored to the image value last loaded
from EEPROM, OTP, or to be set to 0b if neither is available.
Note 15-45 The default value of this field is determined by the value of the TX Deemphasis (TxDeemphasis) bit
of Configuration Flags 1 contained within the EEPROM, if present. If no EEPROM is present then
default depends on the OTP programmed value. It the OTP is not programmed then 0b is the default.
A USB Reset or Lite Reset (LRST) shall cause this field to be restored to the image value last loaded
from EEPROM, OTP, or to be set to 0b if neither is available.
Note 15-46 The default value of this field is determined by the value of the Elasticity Buffer Mode
(ElasticityBufferMode) bit of Configuration Flags 1 contained within the EEPROM, if present. If no
EEPROM is present then default depends on the OTP programmed value. It the OTP is not
programmed then 0b is the default. A USB Reset or Lite Reset (LRST) shall cause this field to be
restored to the image value last loaded from EEPROM, OTP, or to be set to 0b if neither is available.
DS00001993F-page 174
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15.1.28
USB STATUS REGISTER (USB_STATUS)
Address:
0A8h
Size:
32 bits
Bits 15:0 of this CSR are used to generate the USB_STS_INT bit of the Interrupt EP. They indicate a change in the state
of the respective bit. When applicable, the current state of the bit is listed in the mirror bit location in bits 31:16.
BITS
31:21
DESCRIPTION
RESERVED
TYPE
DEFAULT
RO
-
20
Remote Wakeup (REMOTE_WK)
Indicates the current state of Device Remote Wakeup.
RO/
NALR
0b
19
Function Remote Wakeup (FUNC_REMOTE_WK)
Indicates the current state of Function Remote Wakeup Capable.
RO/
NALR
0b
RO
-
18:5
RESERVED
4
Remote Wakeup Status Change (REMOTE_WK_STS)
Indicates that the host set or cleared Device Remote Wakeup.
R/WC
0b
3
Function Remote Wakeup Status Change (FUNC_REMOTE_WK_STS)
Indicates that the host set or cleared Function Remote Wake Capable
R/WC
0b
RO
-
2:0
RESERVED
2021 Microchip Technology Inc. and its subsidiaries
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15.1.29
RECEIVE FILTERING ENGINE CONTROL REGISTER (RFE_CTL)
Offset:
0B0h
Size:
32 bits
This register configures the Receive Filtering Engine (RFE).
If neither Enable IGMP Checksum Validation, Enable ICMP Checksum Validation or Enable TCP/UDP Checksum Validation bits are set, then the RFE inserts 0000h for the L3 raw checksum field.
BITS
TYPE
DEFAULT
RESERVED
RO
-
15
Always Pass Wakeup Frame (PASS_WKP)
When set, the RFE shall never discard a received wakeup frame which
awakened the device while in SUSPEND3 and Store Wakeup Frame
(STORE_WAKE) is set.
R/W
0b
14
Enable IGMP Checksum Validation
When set, the RFE will check the IGMP checksum.
R/W
0b
R/W
0b
R/W
0b
R/W
0b
31:16
DESCRIPTION
Additionally, the RFE calculates the L3 raw checksum and inserts it into RX
Status Word 1.
Note:
13
If the frame is not IGMP raw checksum is still calculated.
Enable ICMP Checksum Validation
When set, the RFE will check the ICMP checksum.
Additionally, the RFE calculates the L3 raw checksum and inserts it into RX
Status Word 1.
Note:
12
If the frame is not ICMP raw checksum is still calculated.
Enable TCP/UDP Checksum Validation
When set, the RFE will check the TCP or UDP checksum.
Additionally, the RFE calculates the L3 raw checksum and inserts it into RX
Status Word 1.
Note:
11
If the frame is not TCP or UDP the raw checksum is still calculated.
Enable IP Checksum Validation
When set, the RFE will check the IP checksum.
This bit has no effect if the frame is not IPv4 or IPv6.
10
Accept Broadcast Frames (AB)
When set, all broadcast frames are accepted. Otherwise broadcast frames
are dropped.
R/W
0b
9
Accept Multicast Frames (AM)
When set, all multicast frames are accepted. Otherwise multicast frames
must pass the perfect filtering or hash filtering.
R/W
0b
Note:
This bit does not apply to broadcast frames.
8
Accept Unicast Frames (AU)
When set, all unicast frames are accepted.
R/W
0b
7
Enable VLAN Tag Stripping
When set, this bit enables stripping of a received frame’s VLAN ID.
R/W
0b
6
Untagged Frame Filtering (UF)
When set, all untagged receive frames are discarded.
R/W
0b
5
Enable VLAN Filtering (VF)
When set, this bit enables filtering of a received frame’s VLAN ID.
R/W
0b
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BITS
4
DESCRIPTION
Enable Source Address Perfect Filtering (SPF)
When set, this bit enables perfect filtering of a received frame’s Ethernet
source address.
Note:
3
DEFAULT
R/W
0b
R/W
0b
If destination address filtering is enabled (perfect or hash), the
frame must pass both source address filtering and destination
address filtering to not be discarded.
Enable Multicast Address Hash Filtering (MHF)
When set, multicast destination addresses will be hashed.
Note:
TYPE
The broadcast address is never hashed.
2
Enable Destination Address Hash Filtering (DHF)
When set, unicast destination addresses will be hashed.
R/W
0b
1
Enable Destination Address Perfect Filtering (DPF)
When set, this bit enables perfect filtering of a received frame’s Ethernet
destination address.
R/W
0b
0
Reset Receive Filtering Engine
When set, this bit resets the RFE.
SC
0b
15.1.30
VLAN TYPE REGISTER (VLAN_TYPE)
Offset:
0B4h
Size:
32 bits
This register extends the Ethernet type used to indicate the presence of a VLAN tag in the RFE in addition to 8100h. In
the FCT this is the value used for the Ethernet type when VLAN tag insertion is enabled.
The intention of this register is to allow for a proprietary VLAN type to be supported. If only the standard VLAN type of
8100h is desired to be supported, then this register should retain its default value of 8100h.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:0
VLAN Ethernet Type
R/W
8100h
2021 Microchip Technology Inc. and its subsidiaries
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15.1.31
FIFO CONTROLLER RX FIFO CONTROL REGISTER (FCT_RX_CTL)
Offset:
0C0h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
FCT RX Enable
When set, the FIFO is capable of accepting traffic from the RFE. If this bit
is deasserted, all received frames from the RFE are aborted and not written
into the FIFO. After this bit is asserted, the FIFO will accept the next full
frame it receives.
R/W
0b
SC
f
RESERVED
RO
-
Store Bad Frames
When set, the RX FCT will store errored frames that were detected by the
Ethernet MAC.
R/W
0b
After the FIFO is enabled, the FIFO begins accepting data after it receives
the first complete frame. If the FIFO is disabled while receiving a frame, the
FIFO will allow the current frame to be received before disabling the FIFO.
After the FIFO is successfully disabled the FCT RX Disabled bit is asserted.
Note:
30
This bit does not cause frame dropped counter to increment.
FCT RX RESET
When set, the FCT RX is reset. It also clears any remnant data from the
FIFO stored in the UTX interface pipeline.
The FIFO must be disabled before a reset is issued.
29:26
25
The following conditions cause the MAC to consider a frame bad: RX error,
FCS error, runt frame, alignment error, jabber error, undersize frame error,
and oversize frame error.
24
FCT RX Overflow
R/WC
0b
23
RX Frame Dropped
See RX Dropped Frames for a description
R/WC
0b
RO
-
R/WC
0b
22:21
20
RESERVED
FCT RX Disabled
This bit indicates the FIFO has been successfully disabled via clearing the
FCT RX Enable bit. It is set when the hardware disabling process, invoked
by a transition of the FCT RX Enable bit from 1 to 0 (enabled to disabled),
completes.
19:16
RESERVED
RO
-
15:0
RX Data FIFO Used Space (RXUSED)
Reads the amount of space in bytes, used by the FIFO. For each frame, this
field is incremented by the length of the frame rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary). Additionally
any Command Words or checksums associated with the frame are also
added in.
RO
0000h
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15.1.32
FIFO CONTROLLER TX FIFO CONTROL REGISTER (FCT_TX_CTL)
Offsets:
BITS
31
0C4h
Size:
32 bits
DESCRIPTION
FCT TX Enable
When set, the FIFO is capable of transmitting frames to the MAC.
TYPE
DEFAULT
R/W
0b
SC
0b
RO
-
R/WC
0b
If the FIFO is disabled while transmitting a frame, the frame transmission is
allowed to complete. Upon completion of the last frame FCT TX Disabled bit
is asserted.
An exception to the above can happen in half duplex mode in which the
FIFO may discard the frame in transmit. This case happens when the frame
in transmit is retried by the MAC after the FIFO has been disabled. The FIFO
does not allow any further retries.
30
FCT TX Reset
When set, this bit resets the FCT TX. It also clears any remnant data from
the FIFO stored in the URX interface pipeline.
The FIFO must be disabled before a reset is issued.
29:21
20
RESERVED
FCT TX Disabled
This bit indicates the FIFO has been successfully disabled via clearing the
FCT TX Enable bit. It is set when the hardware disabling process, invoked
by a transition of the FCT TX Enable bit from 1 to 0 (enabled to disabled),
completes.
19:16
RESERVED
RO
-
15:0
TX Data FIFO Used Space (TXUSED)
Reads the amount of space in bytes, used by the FIFO. For each frame, this
field is incremented by the length of the frame rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary). Additionally
any Command Words or checksums associated with the frame are also
added in.
RO
0000h
15.1.33
FCT RX FIFO END REGISTER (FCT_RX_FIFO_END)
Offset:
0C8h
Size:
32 bits
This register specifies the end address of the RX FIFO in DWORD units. The contents of this register times 128 plus
127 is the end address of the FIFO.
Note:
This register’s contents may not be modified at run time. The RX data path must be halted before changing
the FIFO size. After modifying the FIFO’s size, the FIFO must be flushed.
BITS
DESCRIPTION
TYPE
DEFAULT
31:7
RESERVED
RO
-
6:0
FCT_RX_FIFO_END
R/W
17h
2021 Microchip Technology Inc. and its subsidiaries
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Note:
15.1.34
Maximum RX FIFO size is 12 KB which is the.default value.
FCT TX FIFO END REGISTER (FCT_TX_FIFO_END)
Offset:
0CCh
Size:
32 bits
This register specifies the end address of the TX FIFO in DWORD units. The contents of this register times 128 plus
127 is the end address of the FIFO.
Note:
This register’s contents may not be modified at run time. The TX data path must be halted before changing
the FIFO size. After modifying the FIFO’s size, the FIFO must be flushed.
BITS
DESCRIPTION
TYPE
DEFAULT
31:6
RESERVED
RO
-
5:0
FCT_TX_FIFO_END
R/W
17h
Note:
15.1.35
Maximum TX FIFO size is 12 KB which is the default.
FCT FLOW CONTROL THRESHOLD REGISTER (FCT_FLOW)
Offset:
0D0h
Size:
32 bits
This register specifies the thresholds for controlling pause frame generation. The units of the thresholds are 512 bytes
and correspond to high and low watermarks in the RX FIFO.
Note:
The values in this register must be programmed before the TX Flow Control Enable (TX_FCEN) bit is set.
Please refer to Section 15.1.41, "Flow Control Register (FLOW)," on page 187 for further details.
BITS
DESCRIPTION
TYPE
DEFAULT
31:15
RESERVED
RO
-
14:8
Flow Control Off Threshold
The threshold to turn flow control off. If RX Data FIFO Used Space
(RXUSED) / 512 is less than or equal to this value, then flow control is turned
off.
R/W
0000000b
RESERVED
RO
-
Flow Control On Threshold
The threshold to turn flow control on. If RX Data FIFO Used Space
(RXUSED) / 512 is greater than or equal to this value, then flow control is
turned on.
R/W
0000000b
7
6:0
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15.1.36
RX DATAPATH STORAGE (RX_DP_STOR)
Offset:
0D4h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
Total RX Data Path Used Space (TOT_RXUSED)
Reads the amount of space in bytes, used by both the UTX FIFO and FCT
RX FIFO.
RO
0000h
15:0
UTX FIFO Used Space (UTX_RXUSED)
Reads the amount of space in bytes, used by the UTX FIFO.
RO
0000h
15.1.37
TX DATAPATH STORAGE (TX_DP_STOR)
Offset:
0D8h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
Total TX Data Path Used Space (TOT_TXUSED)
Reads the amount of space in bytes, used by both the URX FIFO and FCT
TX FIFO.
RO
0000h
15:0
URX FIFO Used Space (URX_TXUSED)
Reads the amount of space in bytes, used by the URX FIFO.
RO
0000h
2021 Microchip Technology Inc. and its subsidiaries
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15.1.38
MAC CONTROL REGISTER (MAC_CR)
Offset:
100h
Size:
32 bits
This register establishes the RX and TX operating modes.
BITS
31:19
18
DESCRIPTION
TYPE
DEFAULT
RESERVED
RO
-
Energy Efficient Ethernet TX Clock Stop Enable
(EEE_TX_CLK_STOP_EN)
When set, the MAC will halt the GMII GTX_CLK to the PHY during TX LPI.
This bit is unused in 100Mbs mode.
R/W
Note 15-47
R/W
Note 15-47
R/W
Note 15-47
RESERVED
RO
-
Automatic Duplex Polarity (ADP)
This bit indicate the polarity of the FDUPLEX PHY LED.
R/W
1b
R/W
Note 15-49
This bit should only be set if the Clock stop capable bit in PHY MMD register
3.1 indicates that the PHY is capable of allowing a stopped TX clock.
Note:
17
This field is protected by Reset Protection (RST_PROTECT).
Energy Efficient Ethernet Enable (EEEEN)
When set, enables Energy Efficient Ethernet operation in the MAC. When
cleared, Energy Efficient Ethernet operation is disabled. Note 15-48
The MAC will generate LPI requests even if Transmitter Enable (TXEN) is
cleared and will decode the LPI indication even if Receiver Enable (RXEN)
is cleared.
Note:
16
This field is protected by Reset Protection (RST_PROTECT).
Energy Efficient Ethernet TX LPI Automatic Removal Enable
(EEE_TX_LPI_AUTO_REMOVAL_EN)
When set, enables the automatic deassertion of LPI in anticipation of a
periodic transmission event. The time to wait is specified in the EEE TX LPI
Automatic Removal Delay Register
(EEE_TX_LPI_AUTO_REMOVAL_DELAY). The interval is timed from the
point where the MAC initiates LPI signaling.
Host software should only change this field when Energy Efficient Ethernet
Enable (EEEEN) is cleared.
Note:
15:14
13
This field is protected by Reset Protection (RST_PROTECT).
0: DUPLEX asserted low indicates the PHY is in full duplex mode.
1: DUPLEX asserted high indicates the PHY is in full duplex mode.
12
Note:
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
Note:
This field is protected by Reset Protection (RST_PROTECT).
Automatic Duplex Detection (ADD)
When set, the MAC ignores the setting of the Duplex Mode (DPX) bit and
automatically determines the duplex operational mode. The MAC uses a
PHY LED/signal to accomplish mode detection and reports the last
determined status via the Duplex Mode (DPX) bit. When reset, the setting of
the Duplex Mode (DPX) bit determines Duplex operation.
Note:
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
Note:
This field is protected by Reset Protection (RST_PROTECT).
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BITS
DESCRIPTION
TYPE
DEFAULT
11
Automatic Speed Detection (ASD)
When set, the MAC ignores the setting of the MAC Configuration (CFG) field
and automatically determines the speed of operation. The MAC samples the
RX_CLK input to accomplish speed detection and reports the last
determined speed via the MAC Configuration (CFG) field. When reset, the
setting of the MAC Configuration (CFG) field determines operational speed.
R/W
Note 15-50
R/W
0b
10
Note:
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
Note:
This field is protected by Reset Protection (RST_PROTECT).
Internal Loopback Operation Mode (INT_LOOP)
Loops back data between the TX data path and RX data path interfaces.
This is only for full duplex mode.
In internal loopback mode, the TX frame is received by the Internal GMII
interface, and sent back to the MAC without being sent to the PHY.
0: Normal mode
1: Internal loopback enabled
Note:
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
9:8
RESERVED
RO
-
7:6
Back Off Limit (BOLMT)
The BOLMT bits allow the user to set its back-off limit in a relaxed or
aggressive mode. According to IEEE 802.3, the MAC has to wait for a
random number [r] of slot-times after it detects a collision, where:
R/W
00b
RO
-
(eq.1)0 < r < 2K
The exponent K is dependent on how many times the current frame to be
transmitted has been retried, as follows:
(eq.2)K = min (n, 10) where n is the current number of retries.
If a frame has been retried three times, then K = 3 and r= 8 slot-times
maximum. If it has been retried 12 times, then K = 10, and r = 1024 slottimes maximum.
An LFSR (linear feedback shift register) counter emulates a random number
generator, from which r is obtained. Once a collision is detected, the number
of the current retry of the current frame is used to obtain K (eq.2). This value
of K translates into the number of bits to use from the LFSR counter. If the
value of K is 3, the MAC takes the value in the first three bits of the LFSR
counter and uses it to count down to zero on every slot-time. This effectively
causes the MAC to wait eight slot-times. To give the user more flexibility, the
BOLMT value forces the number of bits to be used from the LFSR counter
to a predetermined value as in the table below.
Thus, if the value of K = 10, the MAC will look at the BOLMT if it is 00, then use
the lower ten bits of the LFSR counter for the wait countdown. If the BOLMT is 10,
then it will only use the value in the first four bits for the wait countdown, etc.
Slot-time = 512 bit times. (See IEEE 802.3 Spec., Sections 4.2.3.2.5 and
4.4.2.1).
Note:
5:4
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
RESERVED
2021 Microchip Technology Inc. and its subsidiaries
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BITS
DESCRIPTION
TYPE
DEFAULT
3
Duplex Mode (DPX)
This bit determines the duplex operational mode of the MAC when the
Automatic Duplex Detection (ADD) bit is reset. When the Automatic Duplex
Detection (ADD) bit is set, this bit is read-only and reports the last
determined duplex operational mode.
Note 1551
Note 15-47
Note 1552
Note 15-47
SC
0b
When set, the MAC is operating in Full-Duplex mode, in which it can transmit
and receive simultaneously.
0: MAC is in half duplex mode
1: MAC is in full duplex mode
2:1
Note:
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
Note:
Half duplex mode is disabled if the detected or manually set speed
is 1000Mbs, regardless of the setting of this bit.
Note:
This field is protected by Reset Protection (RST_PROTECT).
MAC Configuration (CFG)
This field determines the operational speed of the MAC when the Automatic
Speed Detection (ASD) bit is reset. When the Automatic Speed Detection
(ASD) bit is set, this field is read-only and reports the last determined
operational speed.
0: MII Mode - 10 Mbps
1: MII Mode - 100 Mbps
2,3: RGMII/GMII Mode - 1000 Mbps
0
Note:
This bit should not be modified while the MAC's receiver or
transmitter is enabled (Receiver Enable (RXEN) or Transmitter
Enable (TXEN) bit set).
Note:
This field is protected by Reset Protection (RST_PROTECT).
MAC Reset (MRST)
0: MAC is enabled
1: MAC is reset
Note 15-47 The default value of this field is determined by the value of the respective field in Configuration Flags
2 contained within the EEPROM, if present. If no EEPROM is present then default depends on the
OTP programmed value. It the OTP is not programmed then 0h is the default. A USB Reset or Soft
Lite Reset (LRST) shall cause this field to be restored to the image value last loaded from EEPROM,
OTP, or to be set to 0h if neither is available.
Note 15-48 If this bit is manually changed, then the EEE configuration in the Ethernet PHY must be updated and
auto-negotiation rerun.
Note 15-49 The default value of this field is determined by the value of the Automatic Duplex Detection
(CFG0_ADD) bit of Configuration Flags 0 contained within the EEPROM, if present. If no EEPROM
is present then default depends on the OTP programmed value. It the OTP is not programmed then
1b is the default. A USB Reset or Soft Lite Reset (LRST) shall cause this field to be restored to the
image value last loaded from EEPROM, OTP, or to be set to 1b if neither is available.
Note 15-50 The default value of this field is determined by the value of the Automatic Speed Detection
(CFG0_ASD) bit of Configuration Flags 0 contained within the EEPROM, if present. If no EEPROM
is present then default depends on the OTP programmed value. It the OTP is not programmed then
0b is the default. A USB Reset or Soft Lite Reset (LRST) shall cause this field to be restored to the
image value last loaded from EEPROM, OTP, or to be set to 0b if neither is available.
Note 15-51 When Automatic Duplex Detection (ADD) is reset, this bit is R/W and determines duplex operation.
When Automatic Duplex Detection (ADD) is set, this field is RO and reports the last duplex
operational mode determined by the MAC.
DS00001993F-page 184
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Note 15-52 When Automatic Speed Detection (ASD) is reset, this field is R/W and determines operational speed.
When Automatic Speed Detection (ASD) is set, this field is RO and reports the last operational speed
determined by the MAC.
15.1.39
MAC RECEIVE REGISTER (MAC_RX)
Offset:
BITS
104h
Size:
32 bits
DESCRIPTION
TYPE
DEFAULT
31:30
RESERVED
RO
-
29:16
Maximum Frame Size (MAX_SIZE)
Defines the maximum size for a received frame. Frames exceeding this size
are aborted.
R/W
1518
RESERVED
RO
-
Watchdog Truncation Length (WTL)
0: The MAC truncates the Rx FRAME at MAC_RX.MAX_SIZE+1. The
RxCmdA of the truncated received frame passed to the FCT has LONG bit
set and length MAC_RX.MAX_SIZE+1 and FCS likely set.
R/W
1b
R/W
0b
15:6
5
Note:
A frame longer than 11,264 bytes will cause the watchdog timer to
truncate and abort the frame.
Note:
This field should not be modified while the MAC's receiver is
enabled (Receiver Enable (RXEN) bit set in MAC Receive Register
(MAC_RX)).
1: The MAC truncates the Rx FRAME at 11265. The RxCmdA of the
truncated received frame passed to the FCT has LONG bit set and length
11265 and FCS more than likely set and RWT bit set also.
Note:
4
This bit should not be modified while the MAC's receiver is enabled
(Receiver Enable (RXEN) bit set in MAC Receive Register
(MAC_RX)).
FCS Stripping
When set, the MAC will strip the FC (last 4 bytes) off of all received frames.
Note:
This bit should not be modified while the MAC's receiver is enabled
(Receiver Enable (RXEN) bit set in MAC Receive Register
(MAC_RX)).
3
RESERVED
RO
-
2
VLAN Frame Size Enforcement (FSE)
0: Abort all frames larger than the maximum frame size.
1: Abort all non-VLAN frames larger than maximum frame size. Abort all
frames with a single VLAN tag that are larger the maximum frame size + 4.
Abort all frames with two VLAN tags that are larger than the maximum frame
size + 8.
R/W
0b
R/WC
0b
Note:
1
This bit should not be modified while the MAC's receiver is enabled
(Receiver Enable (RXEN) bit set in MAC Receive Register
(MAC_RX)).
Receiver Disabled (RXD)
This bit indicates the MAC’s receiver has been successfully disabled via
clearing the Receiver Enable (RXEN) bit. It is set when the hardware
disabling process, invoked by a transition of the Receiver Enable (RXEN) bit
from 1 to 0 (enabled to disabled), completes.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 185
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BITS
0
DESCRIPTION
TYPE
DEFAULT
R/W
0b
TYPE
DEFAULT
RESERVED
RO
-
Bad FCS (BFCS)
When set, the MAC’s transmitter will append a bad FCS on all transmitted
frames. This feature is useful for diagnostic purposes.
R/W
0b
Receiver Enable (RXEN)
When set, the MAC’s receiver is enabled and will receive frames from the
PHY. When reset, the MAC’s receiver is disabled and will not receive any
frames from the PHY.
If this bit is deasserted while a frame is being received, the received frames
allowed to complete. Upon completion, the MAC’s receiver is disabled and
the Receiver Disabled (RXD) bit is asserted.
15.1.40
MAC TRANSMIT REGISTER (MAC_TX)
Offset:
BITS
31:3
2
108h
Size:
32 bits
DESCRIPTION
This function may only be used in conjunction with Insert FCS and Pad of
TX Command A.
1
Transmitter Disabled (TXD)
This bit indicates the MAC’s transmitter has been successfully disabled via
clearing the Transmitter Enable (TXEN) bit. It is set when the hardware
disabling process, invoked by a transition of the Transmitter Enable (TXEN)
bit from 1 to 0 (enabled to disabled), completes.
R/WC
0b
0
Transmitter Enable (TXEN)
When set, the MAC’s transmitter is enabled and it will transmit frames from
the buffer onto the cable. When reset, the MAC’s transmitter is disabled and
will not transmit any frames.
R/W
0b
If this bit is cleared while a frame is being transmitted, the frame is allowed
to complete. Upon completion, the MAC’s transmitter is disabled and the
Transmitter Disabled (TXD) bit is asserted.
DS00001993F-page 186
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15.1.41
FLOW CONTROL REGISTER (FLOW)
Offset:
10Ch
Size:
32 bits
This register is used to control the handling of the RX and TX flow control frames by the MAC.
RX flow control frames are received by the MAC. When RX flow control is enabled, the MAC will pause transmissions
from the transmit data path for the amount of time specified in the flow control frame.
TX flow control frames may be generated manually or automatically using RX FIFO thresholds. By setting the
FORCE_FC bit, a flow control frame will be manually transmitted with the value specified by Pause Time (FCPT). After
the frame is transmitted, the FORCE_FC bit clears.
Whenever TX_FCEN is set, transmit flow control frames are generated automatically, based on the thresholds set in the
FCT Flow Control Threshold Register (FCT_FLOW). Whenever the high watermark is crossed (RX Data FIFO Used
Space (RXUSED) / 512 greater than or equal to Flow Control On Threshold), the MAC transmits a flow control frame
with the pause value specified by the Pause Time (FCPT) field. When the low watermark is subsequently crossed (RX
Data FIFO Used Space (RXUSED) / 512 less than or equal to Flow Control Off Threshold), the MAC transmits a flow
control frame with a pause value of zero.
Flow Control is only applicable when the MAC is set in full duplex mode.
BITS
DESCRIPTION
TYPE
DEFAULT
31
Force Transmission of TX Flow Control Frame (FORCE_FC)
This bit forces the transmission of a TX flow control frames. Writing a “1”
initiates the frame transmission. The frame will be generated with the Pause
Time value. After the frame is transmitted, the MAC will clear this bit.
SC
0b
30
TX Flow Control Enable (TX_FCEN)
When set, enables the transmit MAC flow control function based on high and
low watermarks in the RX FIFO, as discussed in this section.
R/W
0b
Note:
The threshold values in the FCT Flow Control Threshold Register
(FCT_FLOW) must be programmed before this bit is set.
29
RX Flow Control Enable (RX_FCEN)
When set, enables the receive MAC flow control function. The MAC decodes
all incoming frames for control frames; if it receives a valid control frame
(PAUSE command), it disables the transmitter for a specified time (Decoded
pause time x slot time). When not set, the MAC flow control function is
disabled; the MAC does not decode frames for control frames.
R/W
0b
28
Forward Pause Frames (FPF)
Enables passing received pause frames to RX data path interface.
R/W
0b
0 = Sink received pause frames.
1 = Pass received pause frames to the RX data path interface.
Note:
Flow Control is applicable when the MAC is set in full duplex mode.
27:16
RESERVED
RO
-
15:0
Pause Time (FCPT)
This field indicates the value to be used in the PAUSE TIME field in the
control frame.
R/W
0000h
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 187
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15.1.42
RANDOM NUMBER SEED VALUE REGISTER (RAND_SEED)
Offset:
BITS
110h
Size:
32 bits
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:0
Random Number Seed (RAND_SEED)
The MAC random number generator seed value. The content of this register
is the seed value for the LFSR (linear feedback shift register) counter used
to emulate the random number generator in the MAC TX back-off timer logic.
R/W
9876h
TYPE
DEFAULT
RO
-
15.1.43
ERROR STATUS REGISTER (ERR_STS)
Offset:
BITS
31:9
114h
Size:
32 bits
DESCRIPTION
RESERVED
9
RX Error (RXERR)
Indicates that a receive error (PHY RX error signal asserted) has been
detected during frame reception.
R/WAC
0b
8
FCS Error (FERR)
An FCS errored frame has been received.
R/WAC
0b
7
Large Frame Error (LFERR)
A frame larger than the maximum allow frame size has been received.
R/WAC
0b
6
Runt/Short Frame Error (RFERR)
A runt frame or a short frame has been received.
R/WAC
0b
5
Receive Watchdog Timer Expired (RWTERR)
When set, this bit indicates the received frame was longer than 11,264 bytes
and was truncated by the MAC.
R/WAC
0b
4
Excessive Collision Error (ECERR)
A received frame was aborted due to sixteen collisions occurring.
R/WAC
0b
3
Alignment Error (ALERR)
An alignment error has been detected on a received frame.
R/WAC
0b
2
Under Run Error (URERR)
The MAC has been under run by the transmit data-path.
R/WAC
0b
RO
-
1:0
RESERVED
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15.1.44
MAC RECEIVE ADDRESS HIGH REGISTER (RX_ADDRH)
Address:
118h
Size:
32 bits
This register contains the upper 16 bits of the physical address of the MAC, where RX_ADDRH[15:8] is the 6th octet of
the received frame.
This register used to specify the address used for Perfect DA, Magic Packet and Wakeup frames, the unicast destination
address for received pause frames, and the source address for transmitted pause frames. This register is not used for
packet filtering.
Note:
This register is protected by Reset Protection (RST_PROTECT).
BITS
DESCRIPTION
TYPE
DEFAULT
-
31:16
RESERVED
RO
15-0
Physical Address [47:32]
This field contains the upper 16 bits [47:32] of the physical address of the
device.
R/W
FFFFh
Note 15-53
Note 15-53 The default value of this field is determined by the value of the MAC Address field contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then FFFF_FFFFh is the default. A USB Reset will cause this field to be
restored to the value last loaded from EEPROM, or OTP, otherwise the current value in this register
will be maintained.
15.1.45
MAC RECEIVE ADDRESS LOW REGISTER (RX_ADDRL)
Address:
11Ch
Size:
32 bits
This register contains the lower 32 bits of the physical address of the MAC, where RX_ADDRL[7:0] is the first octet of
the Ethernet frame.
This register used to specify the address used for Perfect DA, Magic Packet, and Wakeup frames, the unicast destination address for received pause frames, and the source address for transmitted pause frames. This register is not used
for packet filtering.
This register is protected by Reset Protection (RST_PROTECT).
BITS
31:0
DESCRIPTION
Physical Address [31:0]
This field contains the lower 32 bits [31:0] of the physical address of the
device.
TYPE
DEFAULT
R/W
FFFF_FFFFh
Note 15-54
Note 15-54 The default value of this field is determined by the value of the MAC Address filed contained within
the EEPROM, if present. If no EEPROM is present then the value programmed in OTP is used. If
OTP is not configured then FFFF_FFFFh is the default. A USB Reset will cause this field to be
restored to the image value last loaded from EEPROM, or OTP, or to be set to FFFF_FFFFh if neither
is present.
2021 Microchip Technology Inc. and its subsidiaries
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Table 15-4 illustrates the byte ordering of the RX_ADDRL and RX_ADDRH registers with respect to the reception of the
Ethernet physical address.
TABLE 15-4:
15.1.46
RX_ADDRL, RX_ADDRH BYTE ORDERING
RX_ADDRL, RX_ADDRH
ORDER OF RECEPTION ON ETHERNET
RX_ADDRL[7:0]
1st
RX_ADDRL[15:8]
2nd
RX_ADDRL[23:16]
3rd
RX_ADDRL[31:24]
4th
RX_ADDRH[7:0]
5th
RX_ADDRH[15:8]
6th
MII ACCESS REGISTER (MII_ACCESS)
Address:
120h
Size:
32 bits
This register is used to control the management cycles to the PHY.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15:11
PHY Address
For every access to this register, this field must be set to 00001b.
R/W
00001b
10:6
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY.
R/W
00000b
5:2
RESERVED
RO
-
1
MII Write (MIIWnR)
Setting this bit tells the PHY that this will be a write operation using the MII
data register. If this bit is not set, this will be a read operation, packing the
data in the MII data register.
R/W
0b
0
MII Busy (MIIBZY)
This bit must be polled to determine when the MII register access is
complete. This bit must read a logical 0 before writing to this register or to
the MII data register. The LAN driver software must set (1) this bit in order
for the Host to read or write any of the MII PHY registers.
SC
0b
During a MII register access, this bit will be set, signifying a read or write
access is in progress. The MII data register must be kept valid until the MAC
clears this bit during a PHY write operation. The MII data register is invalid
until the MAC has cleared this bit during a PHY read operation.
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15.1.47
MII DATA REGISTER (MII_DATA)
Address:
124h
Size:
32 bits
This register contains either the data to be written to the PHY register specified in the MII Access Register, or the read
data from the PHY register whose index is specified in the MII Access Register. Refer to Section 15.1.46, "MII Access
Register (MII_ACCESS)," on page 190 for further details.
Note:
The MIIBZY bit in the MII_ACCESS register must be cleared when writing to this register.
BITS
DESCRIPTION
31:16
RESERVED
RO
-
15:0
MII Data
This contains the 16-bit value read from the PHY read operation or the 16bit data value to be written to the PHY before an MII write operation.
R/W
0000h
15.1.48
EEE TX LPI REQUEST DELAY COUNT REGISTER (EEE_TX_LPI_REQUEST_DELAY_CNT)
Offset:
130h
Size:
32 bits
Contains the count corresponding to the amount of time, in us, the MAC must wait after the TX FIFO is empty before
invoking the LPI protocol.
Whenever the TX FIFO is empty, the device checks the Energy Efficient Ethernet Enable (EEEEN) bit of the MAC Control Register (MAC_CR) to determine whether or not the Energy Efficient Ethernet mode of operation is in effect. If the
bit is clear, no action is taken, otherwise, the device waits the amount of time indicated in this register. After the wait
period has expired, the LPI protocol is initiated and the Energy Efficient Ethernet Start TX Low Power Interrupt
(EEE_START_TX_LPI_INT) bit of the Interrupt Status Register (INT_STS) will be set.
Note:
• Due to a 1us pre-scaler, the actually time can be up to 1us longer than specified.
• A value of zero is valid and will cause no delay to occur.
If the TX FIFO becomes non-empty, the timer is restarted.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
EEE TX LPI Request Delay Count
(EEE_TX_LPI_REQUEST_DELAY_CNT)
Count representing time to wait before invoking LPI protocol. Units are in us.
R/W
00000000h
Note:
Host software should only change this field when Energy Efficient
Ethernet Enable (EEEEN) is cleared.
APPLICATION NOTE: A value of zero may adversely affect the ability of the TX data path to support Gigabit
operation. A reasonable value when the part is operating at Gigabit speeds is 50 us. This
value may be increased pending the results of performance testing with EEE enabled. The
motivation for 802.3az is the scenario where the EEE link is idle most of the time with the
occasional full bandwidth transmission bursts. Aggressively optimizing power consumption
during pockets of inactivity is not the objective for this mode of operation.
2021 Microchip Technology Inc. and its subsidiaries
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15.1.49
EEE TIME WAIT TX SYSTEM REGISTER (EEE_TW_TX_SYS)
Offset:
134h
Size:
32 bits
Contains the count corresponding to the amount of time, in us, the MAC must wait after LPI is exited before it can transmit packets. Time is specified in separate fields for 100Mbs and 1000Mbs operation. This wait time is in addition to the
IPG time.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
EEE TIME Wait TX System Count 1000 (EEE_TW_TX_SYS_CNT_1000)
Count representing time to wait before commencing transmission after LPI
is exited when operating at 1000Mbs. Units are in 0.5 us.
R/W
000021h
R/W
00001Eh
Host software should only change this field when Energy Efficient Ethernet
Enable (EEEEN) is cleared.
Note:
15:0
In order to meet the IEEE 802.3 specified requirement, the
minimum value of this field should be 000021h.
EEE TIME Wait TX System Count 100 (EEE_TW_TX_SYS_CNT_100)
Count representing time to wait before commencing transmission after LPI
is exited when operating at 100Mbs. Units are in us.
Host software should only change this field when Energy Efficient Ethernet
Enable (EEEEN) is cleared.
Note:
In order to meet the IEEE 802.3 specified requirement, the
minimum value of this field should be 00001Eh.
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15.1.50
EEE TX LPI AUTOMATIC REMOVAL DELAY REGISTER
(EEE_TX_LPI_AUTO_REMOVAL_DELAY)
Offset:
138h
Size:
32 bits
Contains the count corresponding to the amount of time, in us, the MAC will wait after the TX LPI protocol is initiated
until it automatically deasserts LPI in anticipation of a periodic transmission. TX LPI automatic removal functionality is
enabled via the Energy Efficient Ethernet TX LPI Automatic Removal Enable (EEE_TX_LPI_AUTO_REMOVAL_EN) bit
of the MAC Control Register (MAC_CR).
When this time period expires, the Energy Efficient Ethernet Stop TX Low Power Interrupt (EEE_STOP_TX_LPI_INT)
bit of the Interrupt Status Register (INT_STS) and the Energy Efficient Ethernet TX Wake (EEE_TX_WAKE) bit of the
Wakeup Control and Status Register 1 (WUCSR1) will be set.
Upon automatic TX LPI deassertion, the MAC will return to waiting for the TX FIFO to be empty, for the time specified
in EEE TX LPI Request Delay Count (EEE_TX_LPI_REQUEST_DELAY_CNT) before requesting LPI once again.
Note:
Due to a 1 us pre-scaler, the actually time can be up to 1us longer than specified.
The MAC will generate LPI requests only when the Energy Efficient Ethernet Enable (EEEEN) bit of the MAC Control
Register (MAC_CR) is set, the current speed is 100 Mbps or 1000 Mbps, the current duplex is full and the auto-negotiation result indicates that both the local and partner device support EEE at the current operating speed.
BITS
DESCRIPTION
TYPE
DEFAULT
31:24
RESERVED
RO
-
23:0
EEE TX LPI Automatic Removal Delay Count
(EEE_TX_LPI_AUTO_REMOVAL_DELAY_CNT)
Count representing time to wait after the TX LPI protocol is initiated until it
is automatically deasserted in anticipation of a periodic transmission. Units
are in us.
R/W
000000h
Note:
Host software should only change this field when Energy Efficient
Ethernet Enable (EEEEN) is cleared.
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15.1.51
WAKEUP CONTROL AND STATUS REGISTER 1 (WUCSR1)
Offset:
140h
Size:
32 bits
This register contains data pertaining to the MAC’s remote wakeup status and capabilities.
All enables within this register must be clear during normal operation. Failure to do so will result in improper MAC receive
operation.
BITS
31:15
14
DESCRIPTION
TYPE
DEFAULT
RESERVED
RO
-
RFE Wake Enable (RFE_WAKE_EN)
When set, remote wakeup mode is enabled and device is capable of
generating a wakeup from a non-errored receive frame that passes the
RFE’s filters.
R/W
0b
R/WC
0b
R/W
0b
R/WC
0b
R/W
0b
R/WC
0b
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
13
Energy Efficient Ethernet TX Wake (EEE_TX_WAKE)
The MAC sets this bit upon the transmitter exiting the Low Power Idle state
due to the expiration of the time specified in EEE TX LPI Request Delay
Count Register (EEE_TX_LPI_REQUEST_DELAY_CNT).
This bit will not set if Energy Efficient Ethernet TX Wake Enable
(EEE_TX_WAKE_EN) is cleared.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
This bit is held low if the Energy Efficient Ethernet Enable (EEEEN) bit in the
MAC Control Register (MAC_CR) is low.
12
Energy Efficient Ethernet TX Wake Enable (EEE_TX_WAKE_EN)
When set, remote wakeup is enabled upon the transmitter exiting the Low
Power Idle state.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
11
Energy Efficient Ethernet RX Wake (EEE_RX_WAKE)
The MAC sets this bit upon the receiver exiting Low Power Idle state due to
the reception of wake signaling.
This bit will not set if Energy Efficient Ethernet RX Wake Enable
(EEE_RX_WAKE_EN) is cleared.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
This bit is held low if the Energy Efficient Ethernet Enable (EEEEN) bit in the
MAC Control Register (MAC_CR) is low.
10
Energy Efficient Ethernet RX Wake Enable (EEE_RX_WAKE_EN)
When set, remote wakeup is enabled upon reception of wake signaling.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
9
RFE Wakeup Frame Received (RFE_WAKE_FR)
This bit is set upon reception of a non-errored frame that passes the RFE
filters.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
DS00001993F-page 194
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BITS
DESCRIPTION
TYPE
DEFAULT
8
Store Wakeup Frame (STORE_WAKE)
When set, the frame associated with a wake event is stored in the FCT RX
FIFO. All subsequents frames received after the wake event which are not
corrupted and pass any applicable frame filters in the MAC and RFE are
stored in the FIFO.
R/W
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/W
0b
R/W
0b
R/W
0b
When cleared, only frames received after the wake event are stored in the
RX FIFO. The frames must not be corrupted and pass any applicable frame
filters in the MAC and RFE.
7
Note:
It is possible that the wakeup source was not a frame. In that case
all subsequent received frames are stored in the FIFO.
Note:
This bit only has meaning when SUSPEND3 is used. For other
suspend modes this bit shall have no affect.
Perfect DA Frame Received (PFDA_FR)
The MAC sets this bit upon receiving a valid frame with a destination
address that matches the physical address.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
6
Remote Wakeup Frame Received (WUFR)
The MAC sets this bit upon receiving a valid remote Wakeup Frame.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
5
Magic Packet Received (MPR)
The MAC sets this bit upon receiving a valid Magic Packet.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
4
Broadcast Frame Received (BCAST_FR)
The MAC Sets this bit upon receiving a valid broadcast frame.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
3
Perfect DA Wakeup Enable (PFDA_EN)
When set, remote wakeup mode is enabled and the MAC is capable of
waking up on receipt of a frame with a destination address that matches the
physical address of the device. The physical address is stored in the MAC
Receive Address High Register (RX_ADDRH) and MAC Receiver Address
Low Register (RX_ADDRL).
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
2
Wakeup Frame Enable (WUEN)
When set, remote wakeup mode is enabled and the MAC is capable of
detecting Wakeup Frames as programmed in the Wakeup Frame Filter.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
1
Magic Packet Enable (MPEN)
When set, Magic Packet wakeup mode is enabled.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
2021 Microchip Technology Inc. and its subsidiaries
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BITS
0
DESCRIPTION
Broadcast Wakeup Enable (BCAST_EN)
When set, remote wakeup mode is enabled and the MAC is capable of
waking up from a broadcast frame.
TYPE
DEFAULT
R/W
0b
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
15.1.52
WAKEUP SOURCE REGISTER (WK_SRC)
Offset:
144h
Size:
32 bits
This register indicates the source of the wakeup event that resulted in the device issuing wakeup signaling. Any wake
events that occurred while the device was being placed into the SUSPENDx state are ignored. Additionally, any wake
events that occur after the device has commenced the process of waking up are likewise ignored.
It is possible for a received wakeup packet to match several of the conditions listed in this CSR. In that case all matching
bits for that packet shall be set.
The status fields in this CSR are not cleared until explicitly done so by SW.
BITS
DESCRIPTION
TYPE
DEFAULT
31:20
GPIO [11:0] (GPIOx_INT_WK)
These bits assert from a GPIO wake event that results in the device issuing
wakeup signaling.
R/WAC
000h
19:17
RESERVED
RO
-
16
IPv6 TCP SYN Packet Received (IPV6_TCPSYN_RCD_WK)
The MAC sets this bit upon receiving a valid IPv6 TCP SYN packet that
results in the device issuing wakeup signaling.
R/WAC
0b
15
IPv4 TCP SYN Packet Received (IPV4_TCPSYN_RCD_WK)
The MAC sets this bit upon receiving a valid IPv4 TCP SYN packet that
results in the device issuing wakeup signaling.
R/WAC
0b
14
Energy Efficient Ethernet TX Wake (EEE_TX_WK)
The MAC sets this bit upon the transmitter exiting the Low Power Idle state
due to the expiration of the time specified in EEE TX LPI Request Delay
Count Register (EEE_TX_LPI_REQUEST_DELAY_CNT).
R/WAC
0b
R/WAC
0b
This bit will not set if Energy Efficient Ethernet TX Wake Enable
(EEE_TX_WAKE_EN) is cleared.
This bit is held low if the Energy Efficient Ethernet Enable (EEEEN) bit in the
MAC Control Register (MAC_CR) is low.
13
Energy Efficient Ethernet RX Wake (EEE_RX_WK)
The MAC sets this bit upon the receiver exiting Low Power Idle state due to
the reception of wake signaling.
This bit will not set if Energy Efficient Ethernet RX Wake Enable
(EEE_RX_WAKE_EN) is cleared.
This bit is held low if the Energy Efficient Ethernet Enable (EEEEN) bit in the
MAC Control Register (MAC_CR) is low.
DS00001993F-page 196
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
BITS
DESCRIPTION
TYPE
DEFAULT
12
RFE Wakeup Frame Received (RFE_FR_WK)
This bit is set bit upon reception of a non-errored frame that passes the
RFE’s filters and results in the device issuing wakeup signaling.
R/WAC
0b
11
Perfect DA Frame Received (PFDA_FR_WK)
The MAC sets this bit upon receiving a valid frame with a destination
address that matches the physical address that results in the device issuing
wakeup signaling.
R/WAC
0b
10
Magic Packet Received (MP_FR_WK)
The MAC sets this bit upon receiving a valid Magic Packet that results in the
device issuing wakeup signaling.
R/WAC
0b
9
Broadcast Frame Received (BCAST_FR_WK)
The MAC Sets this bit upon receiving a valid broadcast frame that results in
the device issuing wakeup signaling.
R/WAC
0b
8
Remote Wakeup Frame Received (WU_FR_WK)
The MAC sets this bit upon receiving a valid remote Wakeup Frame that
results in the device issuing wakeup signaling.
R/WAC
0b
RO
-
R/WAC
0b
7:5
RESERVED
4:0
Remote Wakeup Frame Match (WUFF_MATCH)
This field indicates which wakeup frame filter caused the wake up event. The
contents of this field are only valid when Remote Wakeup Frame Received
(WU_FR_WK) is set.
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 197
LAN7850
15.1.53
WAKEUP FILTER X CONFIGURATION REGISTER (WUF_CFGX)
Offset:
150h - 1CCh
Size:
32 bits
These CSRs enable the respective wakeup filter to be enabled. A total of 32 programmable filters are available in this
device where each filter can match a pattern up to 128 bytes in length.
Note:
WUF_CFG0 supports Reset Protection (RST_PROTECT).
BITS
TYPE
DEFAULT
Filter Enable
0b: Filter disabled
1b: Filter enabled
R/W
0b
30:26
RESERVED
RO
-
25:24
Filter Address Type
Defines the destination address type of the pattern (as specified for filter x
in the Wakeup Filter x Byte Mask Registers (WUF_MASKx) block).
R/W
00b
31
DESCRIPTION
Note 15-55
Note 15-55
00b: Pattern applies only to unicast frames.
10b: Pattern applies only to multicast frames.
X1b: Pattern applies to all frames.
23:16
15:0
Filter Pattern Offset
Specifies the offset of the first byte in the frame on which CRC checking
begins for Wakeup Frame recognition. Offset 0 is the first byte of the
incoming frame's destination address.
R/W
Filter CRC-16
Specifies the expected 16-bit CRC value for the filter that should be obtained
by using the pattern offset and the byte mask programmed for the filter. This
value is compared against the CRC calculated on the incoming frame, and
a match indicates the reception of a Wakeup Frame.
R/W
00h
Note 15-55
0000h
Note 15-55
Note 15-55 The default value for Wakeup Filter 0 is loaded from EEPROM, see Table 10-2, “EEPROM Format,”
on page 103. If no EEPROM is present, or if this information is not configured, then the default
depends on the OTP programmed value. It the OTP is not programmed then 0h is the default. A USB
Reset or Lite Reset (LRST) shall cause this field to be restored to the image value last loaded from
EEPROM, OTP, or to be set to 0h if neither is available.
DS00001993F-page 198
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.54
WAKEUP FILTER X BYTE MASK REGISTERS (WUF_MASKX)
Offset:
200h - 3FCh
Size:
128 bits
Each of the 32 wakeup filters has a 128-bit byte mask. The 128-bit mask is accessed via 4 consecutive byte mask
(DWORD) registers. The DWORD offset required to access a particular portion of the mask is indicated in the following
table. The start offset of the least significant DWORD register for each 128-bit filter block is the first element in the range
indicated in the preceding table and in the register map, Table 15-2, “System Control and Status Registers Map,” on
page 139.
If bit j of the byte mask is set, the CRC machine processes byte pattern offset + j of the incoming frame. Otherwise, byte
pattern offset + j is ignored.
Note:
WUF_MASK0 supports Reset Protection (RST_PROTECT).
DWORD
OFFSET
BITS
00h
31:0
DESCRIPTION
Filter x Byte Mask [31:0]
TYPE
DEFAULT
R/W
0h
Note 15-55
01h
31:0
Filter x Byte Mask [63:32]
R/W
0h
Note 15-55
02h
31:0
Filter x Byte Mask [95:64]
R/W
0h
Note 15-55
03h
31:0
Filter x Byte Mask [127:96]
R/W
0h
Note 15-55
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 199
LAN7850
15.1.55
MAC ADDRESS PERFECT FILTER REGISTERS (ADDR_FILTX)
Offset:
400h - 504h
Size:
32 bits
These registers specify the MAC addresses used for perfect filtering.
It is permissible to change the value of an entry at run time. However, the address valid bit must be cleared before doing
so. Otherwise an invalid value will temporarily be in the MAC address filter.
Note:
The MAC address storage scheme matches that for the RX_ADDRH and RX_ADDRL registers, see
Table 15-4, "RX_ADDRL, RX_ADDRH Byte Ordering".
DWORD
OFFSET
BITS
DESCRIPTION
TYPE
DEFAULT
0h
31
Address Valid
When set, this bit indicates that the entry has valid data and is
used in the perfect filtering.
R/W
0h
0h
30
Address Type
When set, this bit indicates the address represents the MAC
source address. Otherwise this entry applies to the MAC
destination address.
R/W
0h
0h
29:16
RESERVED
RO
-
0h
15-0
Physical Address [47:32]
This field contains the upper 16 bits [47:32] of the physical
address of the device.
R/W
0h
1h
31:0
Physical Address [31:0]
This field contains the lower 32 bits [31:0] of the physical address
of the device.
R/W
0h
DS00001993F-page 200
2021 Microchip Technology Inc. and its subsidiaries
LAN7850
15.1.56
WAKEUP CONTROL AND STATUS REGISTER 2 (WUCSR2)
Offset:
600h
Size:
32 bits
This register contains data pertaining to Windows 7 Power Management wake and off-load features.
BITS
DESCRIPTION
TYPE
DEFAULT
31
Checksum Disable (CSUM_DISABLE)
When clear, the IP header checksum, TCP checksum, and FCS are
calculated and all must agree with the frame contents, in order for the frame
(ARP, TCP_SYN, or NS) to be considered for detection analysis.
R/W
0b
RESERVED
RO
-
Forward ARP Frames (FARP_FR)
Enables passing received ARP frames that target this device and were
processed by the ARP offload logic to the RX datapath interface.
R/W
0b
R/W
0b
R/W
0b
When set, only the FCS is calculated and checked for ARP, TCP_SYN, and
NS frames. The IP header checksum, ICMP payload checksum, and TCP
checksum are not calculated, hence any mismatches are ignored.
30:11
10
0 = Sink received ARP frames.
1 = Pass received ARP frames to the RX datapath interface.
9
Forward NS Frames (FNS_FR)
Enables passing received NS frames that target this device and were
processed by the NS offload logic to the RX datapath interface.
0 = Sink received NS frames.
1 = Pass received NS frames to the RX datapath interface.
8
NA SA Select (NA_SA_SEL)
Used to select source for IPv6 SA in NA message.
When set, NSx IPv6 Destination Address Register
(NSx_IPV6_ADDR_DEST) value is used as the source.
When cleared, the Target Address in NS packet is used.
7
NS Packet Received (NS_RCD)
The MAC sets this bit upon receiving a valid NS packet.
R/WC
0b
6
ARP Packet Received (ARP_RCD)
The MAC sets this bit upon receiving a valid ARP packet.
R/WC
0b
5
IPv6 TCP SYN Packet Received (IPV6_TCPSYN_RCD)
The MAC sets this bit upon receiving a valid IPv6 TCP SYN packet.
R/WC
0b
R/WC
0b
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
4
IPv4 TCP SYN Packet Received (IPV4_TCPSYN_RCD)
The MAC sets this bit upon receiving a valid IPv4 TCP SYN packet.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) is set.
3
NS Offload Enable (NS_OFFLOAD_EN)
When set, enables the response to Neighbor Solicitation packets.
R/W
0b
2
ARP Offload Enable (ARP_OFFLOAD_EN)
When set, enables the response to ARP packets.
R/W
0b
2021 Microchip Technology Inc. and its subsidiaries
DS00001993F-page 201
LAN7850
BITS
1
DESCRIPTION
IPv6 TCP SYN Wake Enable (IPV6_TCPSYN_WAKE_EN)
When set, enables the wakeup on receiving an IPv6 TCP SYN packet.
TYPE
DEFAULT
R/W
0b
R/W
0b
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
Note this is only a documentation change.
0
IPv4 TCP SYN Wake Enable (IPV4_TCPSYN_WAKE_EN)
When set, enables the wakeup on receiving an IPv4 TCP SYN packet.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
15.1.57
NSX IPV6 DESTINATION ADDRESS REGISTER (NSX_IPV6_ADDR_DEST)
Offset:
610h - 61Ch,
650h - 65Ch
Size:
32 bits
Used in IPv6 NS header matching, each IPv6 destination address is 128-bits. The 128-bit address is accessed via 4
consecutive (DWORD) registers. The DWORD offset required to access a particular portion of the address is indicated
in the following table. The start offset of the least significant DWORD register for each 128-bit address block is the first
element in the range indicated in the preceding table and in the register map, Table 15-2, “System Control and Status
Registers Map,” on page 139.
These registers are used when NS Offload Enable (NS_OFFLOAD_EN) is set in the Wakeup Control and Status Register 2 (WUCSR2). Received packets whose Ethernet destination address is the device’s MAC address, a multi-cast
address, or the broadcast address are processed as follows:
The headers of all IPv6 packets are checked to determine whether (for 0
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