LAN91C111
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Highlights
Network Interface
•
•
•
•
•
• Fully Integrated IEEE 802.3/802.3u-100Base-TX/
10Base-T Physical Layer
• Auto-Negotiation: 10/100, Full / Half Duplex
• On Chip Wave Shaping - No External Filters
Required
• Adaptive Equalizer
• Baseline Wander Correction
• LED Outputs (User selectable – Up to 2 LED functions at one time)
- Link
- Activity
- Full Duplex
- 10/100
- Transmit
- Receive
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer
Memory)
Built-in Transparent Arbitration for Slave Sequential Access Architecture
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
3.3V Operation with 5V Tolerant IO Buffers (See
Pin List Description for Additional Details)
Single 25 MHz Reference Clock for Both PHY and
MAC
External 25Mhz-output pin for an external PHY
supporting PHYs physical media.
Low Power CMOS Design
Supports Multiple Embedded Processor Host
Interfaces
- ARM
- SH
- Power PC
- Coldfire
- 680X0, 683XX
- MIPS R3000
3.3V MII (Media Independent Interface) MACPHY Interface Running at Nibble Rate
MII Management Serial Interface
128-Pin QFP RoHS compliant package
128-Pin TQFP 1.0 mm height RoHS compliant
package
Commercial Temperature Range from 0C to
70C (LAN91C111)
Industrial Temperature Range from -40C to 85C
(LAN91C111i)
2011-2016 Microchip Technology Inc.
DS00002276A-page 1
LAN91C111
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00002276A-page 2
2011-2016 Microchip Technology Inc.
LAN91C111
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Configurations ........................................................................................................................................................................... 5
3.0 Block Diagrams ............................................................................................................................................................................... 7
4.0 Signal Descriptions ....................................................................................................................................................................... 10
5.0 Description of Pin Functions ......................................................................................................................................................... 11
6.0 Signal Description Parameters ..................................................................................................................................................... 15
7.0 Functional Description .................................................................................................................................................................. 16
8.0 MAC Data Structures and Registers ............................................................................................................................................. 38
9.0 PHY MII Registers ....................................................................................................................................................................... 65
10.0 Software Driver and Hardware Sequence Flow .......................................................................................................................... 77
11.0 Board Setup Information ............................................................................................................................................................. 88
12.0 Application Considerations ......................................................................................................................................................... 90
13.0 Operational Description .............................................................................................................................................................. 97
14.0 Timing Diagrams ....................................................................................................................................................................... 102
15.0 Package Outlines ...................................................................................................................................................................... 118
Appendix A: Data Sheet Revision History ......................................................................................................................................... 120
The Microchip Web Site .................................................................................................................................................................... 121
Customer Change Notification Service ............................................................................................................................................. 121
Customer Support ............................................................................................................................................................................. 121
Product Identification System ........................................................................................................................................................... 122
2011-2016 Microchip Technology Inc.
DS00002276A-page 3
LAN91C111
1.0
GENERAL DESCRIPTION
The Microchip LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity
solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design
requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the
CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
The Microchip LAN91C111 is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU (Memory Management Unit) architecture and a 32bit wide internal data path. This I/O mapped architecture can sustain back-to-back frame transmission and reception for
superior data throughput and optimal performance. It also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these housekeeping functions.
The Microchip LAN91C111 provides a flexible slave interface for easy connectivity with industry-standard buses. The
Bus Interface Unit (BIU) can handle synchronous as well as asynchronous transfers, with different signals being used
for each one. Asynchronous bus support for ISA is supported even though ISA cannot sustain 100 Mbps traffic. Fast
Ethernet data rates are attainable for ISA-based nodes on the basis of the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first Interface is a standard Magnetics transmit/receive
pair interfacing to 10/100Base-T utilizing the internal physical layer block. The second interface follows the MII (Media
Independent Interface) specification standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is
applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks. Three of the LAN91C111’s pins are used to
interface to the two-line MII serial management protocol.
The Microchip LAN91C111 integrates IEEE 802.3 Physical Layer for twisted pair Ethernet applications. The PHY can
be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation. The Analog PHY block
consists of a 4B5B/Manchester encoder/decoder, scrambler/de-scrambler, transmitter with wave shaping and output
driver, twisted pair receiver with on chip equalizer and baseline wander correction, clock and data recovery, Auto-Negotiation, controller interface (MII), and serial port (MI). Internal output wave shaping circuitry and on-chip filters eliminate
the need for external filters normally required in 100Base-TX and 10Base-T applications.
The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip
Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for embedded application desiring Ethernet
connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs. The
LAN91C111 operates from a single 3.3V supply. The inputs and outputs of the host Interface are 5V tolerant and will
directly interface to other 5V devices.
DS00002276A-page 4
2011-2016 Microchip Technology Inc.
LAN91C111
2.0
PIN CONFIGURATIONS
PIN CONFIGURATION - LAN91C111-FEAST 128-PIN TQFP
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
XTAL2
XTAL1
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3
VDD
CRS100
RX25
GND
TXD0
TXD1
TXD2
TXD3
COL100
TXEN100
VDD
TX25
GND
D0
D1
D2
D3
GND
D4
D5
D6
D7
VDD
nBE3
FIGURE 2-1:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LAN91C111FEASTTM
128 PIN TQFP
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
nBE2
nBE1
nBE0
GND
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
VDD
D8
D9
D10
D11
GND
D12
D13
D14
D15
GND
D16
D17
VDD
nDATACS
nCYCLE
W/nR
nADS
ARDY
GND
nVLBUS
AEN
LCLK
nSRDY
VDD
nLDEV
nRDYRTN
X25OUT
D31
D30
D29
D28
GND
D27
D26
D25
D24
GND
D23
D22
D21
D20
VDD
D19
D18
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
nCSOUT
IOS0
IOS1
IOS2
ENEEP
EEDO
EEDI
EESK
EECS
AVDD
RBIAS
AGND
TPO+
TPOAVDD
TPI+
TPIAGND
nLNK
LBK
nLEDA
nLEDB
GND
MDI
MDO
MCLK
nCNTRL
INTR0
RESET
nRD
nWR
2011-2016 Microchip Technology Inc.
DS00002276A-page 5
LAN91C111
PIN CONFIGURATION - LAN91C111-FEAST 128-PIN QFP
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3
VDD
CRS100
RX25
GND
TXD0
TXD1
TXD2
TXD3
COL100
TXEN100
VDD
TX25
GND
D0
D1
D2
D3
GND
D4
D5
FIGURE 2-2:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LAN91C111FEASTTM
128 PIN QFP
D6
D7
VDD
nBE3
nBE2
nBE1
nBE0
GND
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
VDD
D8
D9
D10
D11
GND
D12
D13
D14
D15
GND
D16
D17
D18
D19
nADS
ARDY
GND
nVLBUS
AEN
LCLK
nSRDY
VDD
nLDEV
nRDYRTN
X25OUT
D31
D30
D29
D28
GND
D27
D26
D25
D24
GND
D23
D22
D21
D20
VDD
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
XTAL1
XTAL2
VDD
nCSOUT
IOS0
IOS1
IOS2
ENEEP
EEDO
EEDI
EESK
EECS
AVDD
RBIAS
AGND
TPO+
TPOAVDD
TPI+
TPIAGND
nLNK
LBK
nLEDA
nLEDB
GND
MDI
MDO
MCLK
nCNTRL
INTR0
RESET
nRD
nWR
VDD
nDATACS
nCYCLE
W/nR
DS00002276A-page 6
2011-2016 Microchip Technology Inc.
LAN91C111
3.0
BLOCK DIAGRAMS
The diagram shown in Figure 3-1, "Basic Functional Block Diagram", describes the device basic functional blocks. The
Microchip LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices
required to implement 10/100 Ethernet connectivity solutions.
The optional Serial EEPROM is used to store information relating to default IO offset parameters as well as which of the
Interrupt line are used by the host.
FIGURE 3-1:
BASIC FUNCTIONAL BLOCK DIAGRAM
Host System
LAN91C111
ISA,Embedded
Processor
Ethernet
MAC
Internal IEEE 802.3 MII (Media
Independent Interface)
PHY
Core
Transformer
RJ45
TX/RX Buffer (8K)
Serial
EEProm
(Optional)
2011-2016 Microchip Technology Inc.
Minimal LAN91C111
Configuration
DS00002276A-page 7
LAN91C111
FIGURE 3-2:
BLOCK DIAGRAM
EEPROM
INTERFACE
MII
Control
Control
Control
Control
Address
8-32 bit
Bus
Interface
Unit
Control
Arbiter
Control
TPO
Control
WR
FIFO
Data
RD
FIFO
MMU
TX/RX
FIFO
Pointer
Ethernet
Protocol
Handler
(EPH)
DMA
TX Data
8K Byte
Dynamically
Allocated
SRAM
10/100
PHY
TXD[0-3]
32-bit Data
TPI
RX Data
32-bit Data
RXD[0-3]
The diagram shown in Figure 3-2 describes the supported Host interfaces, which include ISA or Generic Embedded.
The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC
and ARM processors.
The figure shown next page describes the Microchip LAN91C111 functional blocks required to integrate a 10/100 Ethernet Physical layer framer to the internal MAC.
DS00002276A-page 8
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 3-3:
LAN91C111 PHYSICAL LAYER TO INTERNAL MAC BLOCK DIAGRAM
EECS
EESK
EEDO
EEDI
MII External
Signals
RBIAS
EEPROM
CONTROL
To MII External Signals
CSMA/CD
TXD[3:0]
TX_ER
TXEN100
TX25
4B5B
ENCODER
100BASE-TX
TRANSMITTER
SCRAMBLER
MLT3
ENCODER
SWITCHED
CURRENT
SOURCE
LP
FILTER
TPO+
-
TPO-
CLOCK
GEN
(PLL)
10BASE-T
TRANSMITTER
MANCHESTER
CRS100
COL100
ROM
DAC
+
LP
FILTER
-
CLOCK
GEN
(PLL)
COLLISION
RXD[3:0]
RX_ER
RX_DV
RX25
100BASE-TX
RECEIVER
SQUELCH
DESCRAMBL
ER
CLOCK &
DATA
RECOVERY
+/- Vth
MLT
ENCODER
+
+
4B5B
DECODER
MII
SERIAL
Manage
-ment
+
TPI+
ADAPTIVE
EQUALIZER
TPI-
AUTO
NEGOTIATION
& LINK
MDI
MCLK
MDO
SQUELCH
10BASE-T
RECEIVER
+/- Vth
+
+
MII
CLOCK &
DATA
Recovery
(Manchester
Decoder)
LP
FILTER
Multiplexer
S1
Power
On
Reset
PHY
CONTROLS
nPLED[0-5]
AUTONEG
LOGIC
C1
LS[2-0]A
LED
Control
D
LEDA
S8
C2
C3
EN
B
Multiplexer
S1
D
LEDB
S8
C1
C2
C3
EN
B
LS[2-0]B
2011-2016 Microchip Technology Inc.
DS00002276A-page 9
LAN91C111
4.0
SIGNAL DESCRIPTIONS
TABLE 4-1:
LAN91C111 PIN REQUIREMENTS (128 PIN QFP AND 1.0MM TQFP PACKAGE)
Function
Pin Symbols
Number of Pins
System Address Bus
A1-A15, AEN, nBE0-nBE3
20
System Data Bus
D0-D31
32
System Control Bus
RESET, nADS, LCLK, ARDY,
nRDYRTN, nSRDY, INTR0, nLDEV,
nRD, nWR, nDATACS, nCYCLE, W/nR,
nVLBUS
14
Serial EEPROM
EEDI, EEDO, EECS, EESK, ENEEP,
IOS0-IOS2
8
LEDs
nLEDA, nLEDB
2
PHY
TPO+, TPO-, TPI+, TPI-, nLNK, LBK,
nCNTRL, RBIAS
8
Crystal Oscillator
XTAL1, XTAL2
2
Power
VDD, AVDD
10
Ground
GND, AGND
12
Physical Interface (MII)
TXEN100, CRS100, COL100, RX_DV,
RX_ER, TXD0-TXD3, RXD0-RXD3,
MDI, MDO, MCLK, RX25, TX25
18
MISC
nCSOUT, X25OUT
2
TOTAL
DS00002276A-page 10
128
2011-2016 Microchip Technology Inc.
LAN91C111
5.0
DESCRIPTION OF PIN FUNCTIONS
Pin No.
Name
TQFP
Buffer
Type
Symbol
QFP
Description
81-92
83-94
Address
A4-A15
I**
Input. Decoded by LAN91C111 to
determine access to its registers.
78-80
80-82
Address
A1-A3
I**
Input. Used by LAN91C111 for internal
register selection.
41
43
Address Enable
AEN
I**
Input. Used as an address qualifier.
Address decoding is only enabled when
AEN is low.
94-97
96-99
nByte Enable
nBE0nBE3
I**
Input. Used during LAN91C111 register
accesses to determine the width of the
access and the register(s) being
accessed. nBE0-nBE3 are ignored when
nDATACS is low (burst accesses)
because 32 bit transfers are assumed.
107-104,
102-99, 7673, 71-68,
66-63, 6158, 56-53,
51-48
109-106,
104-101,
78-75, 7370, 68-65,
63-60, 5855, 53-50
Data Bus
D0-D31
I/O24**
Bidirectional. 32 bit data bus used to
access the LAN91C111’s internal
registers. Data bus has weak internal
pullups. Supports direct connection to the
system bus without external buffering. For
16 bit systems, only D0-D15 are used.
30
32
Reset
RESET
IS**
Input. When this pin is asserted high, the
controller performs an internal system
(MAC & PHY) reset. It programs all the
registers to their default value, the
controller will read the EEPROM device
through the EEPROM interface (Note 5-1).
This input is not considered active unless
it is active for at least 100ns to filter
narrow glitches.
37
39
nAddress
Strobe
nADS
IS**
Input. For systems that require address
latching, the rising edge of nADS
indicates the latching moment for A1-A15
and AEN. All LAN91C111 internal
functions of A1-A15, AEN are latched
except for nLDEV decoding.
35
37
nCycle
nCYCLE
I**
Input. This active low signal is used to
control LAN91C111 EISA burst mode
synchronous bus cycles.
36
38
Write/
nRead
W/nR
IS**
Input. Defines the direction of
synchronous cycles. Write cycles when
high, read cycles when low.
40
42
nVL Bus Access nVLBUS
I with
pullup**
Input. When low, the LAN91C111
synchronous bus interface is configured
for VL Bus accesses. Otherwise, the
LAN91C111 is configured for EISA DMA
burst accesses. Does not affect the
asynchronous bus interface.
42
44
Local Bus Clock LCLK
I**
Input. Used to interface synchronous
buses. Maximum frequency is 50 MHz.
Limited to 8.33 MHz for EISA DMA burst
mode. This pin should be tied high if it is
in asynchronous mode.
2011-2016 Microchip Technology Inc.
DS00002276A-page 11
LAN91C111
Pin No.
Name
TQFP
Buffer
Type
Symbol
QFP
Description
38
40
Asynchronous
Ready
ARDY
OD16
Open drain output. ARDY may be used
when interfacing asynchronous buses to
extend accesses. Its rising (access
completion) edge is controlled by the
XTAL1 clock and, therefore,
asynchronous to the host CPU or bus
clock. ARDY is negated during
Asynchronous cycle when one of the
following conditions occurs:
No_Wait Bit in the Configuration Register
is cleared.
Read FIFO contains less than 4 bytes
when read.
Write FIFO is full when write.
43
45
nSynchronous
Ready
nSRDY
O16
Output. This output is used when
interfacing synchronous buses and
nVLBUS=0 to extend accesses. This
signal remains normally inactive, and its
falling edge indicates completion. This
signal is synchronous to the bus clock
LCLK.
46
48
nReady Return
nRDYRTN
I**
Input. This input is used to complete
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK
edges, and synchronous cycles are
delayed until it is sampled high.
29
31
Interrupt
INTR0
O24
Interrupt Output – Active High, it’s used to
interrupt the Host on a status event. Note:
The selection bits used to determined by
the value of INT SEL 1-0 bits in the
Configuration Register are no longer
required and have been set to reserved in
this revision of the FEAST family of
devices.
45
47
nLocal Device
nLDEV
O16
Output. This active low output is asserted
when AEN is low and A4-A15 decode to
the LAN91C111 address programmed
into the high byte of the Base Address
Register. nLDEV is a combinatorial
decode of unlatched address and AEN
signals.
31
33
nRead Strobe
nRD
IS**
Input. Used in asynchronous bus
interfaces.
32
34
nWrite Strobe
nWR
IS**
Input. Used in asynchronous bus
interfaces.
34
36
nData Path
Chip Select
nDATACS
I with
pullup**
Input. When nDATACS is low, the Data
Path can be accessed regardless of the
values of AEN, A1-A15 and the content of
the BANK SELECT Register. nDATACS
provides an interface for bursting to and
from the LAN91C111 32 bits at a time.
9
11
EEPROM Clock
EESK
O4
Output. 4 sec clock used to shift data in
and out of the serial EEPROM.
10
12
EEPROM
Select
EECS
O4
Output. Serial EEPROM chip select.
Used for selection and command framing
of the serial EEPROM.
DS00002276A-page 12
2011-2016 Microchip Technology Inc.
LAN91C111
Pin No.
Name
TQFP
Symbol
QFP
Buffer
Type
Description
7
9
EEPROM Data
Out
EEDO
O4
Output. Connected to the DI input of the
serial EEPROM.
8
10
EEPROM Data
In
EEDI
I with
pulldown**
Input. Connected to the DO output of the
serial EEPROM.
3-5
5-7
I/O Base
IOS0-IOS2
I with
pullup**
Input. External switches can be
connected to these lines to select
between predefined EEPROM
configurations.
6
8
Enable
EEPROM
ENEEP
I with
pullup**
Input. Enables (when high or open)
LAN91C111 accesses to the serial
EEPROM. Must be grounded if no
EEPROM is connected to the
LAN91C111.
127, 128
1, 2
Crystal 1
Crystal 2
XTAL1
XTAL2
Iclk**
An external 25 MHz crystal is connected
across these pins. If a TTL clock is
supplied instead, it should be connected
to XTAL1 and XTAL2 should be left open.
XTAL1 is the 5V tolerant input of the
internal amplifier and XTAL2 is the output
of the internal amplifier.
1, 33, 44,
62, 77, 98,
110, 120
3, 35, 46,
64, 79,
100, 112,
122
Power
VDD
+3.3V Power supply pins.
11, 16
13, 18
Analog Power
AVDD
+3.3V Analog power supply pins.
24, 39, 52,
57, 67, 72,
93, 103,
108, 117
26, 41, 54,
59, 69, 74,
95, 105,
110, 119
Ground
GND
Ground pins.
13, 19
15, 21
Analog Ground
AGND
Analog Ground pins
21
23
Loopback
LBK
O4
Output. Active when LOOP bit is set
(TCR bit 1).
20
22
nLink Status
nLNK
I with
pullup
Input. General-purpose input port used to
convey LINK status (EPHSR bit 14).
28
30
nCNTRL
nCNTRL
O12
General Purpose Control Pin
47
49
X25out
X25out
O12
25Mhz Output to external PHY
111
113
Transmit Enable
100 Mbps
TXEN100
O12
Output to MII PHY. Envelope to 100 Mbps
transmission.
119
121
Carrier Sense
100 Mbps
CRS100
I with
pulldown
Input from MII PHY. Envelope of packet
reception used for deferral and backoff
purposes.
125
127
Receive Data
Valid
RX_DV
I with
pulldown
Input from MII PHY. Envelope of data
valid reception. Used for receive data
framing.
112
114
Collision Detect
100 Mbps
COL100
I with
pulldown
Input from MII PHY. Collision detection
input.
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DS00002276A-page 13
LAN91C111
Pin No.
Name
TQFP
Symbol
QFP
Buffer
Type
Description
113-116
115-118
Transmit Data
TXD3TXD0
O12
Outputs. Transmit Data nibble to MII PHY.
109
111
Transmit Clock
TX25
I with
pullup
Input. Transmit clock input from MII.
Nibble rate clock (25MHz for 100Mbps &
2.5MHz for 10Mbps).
118
120
Receive Clock
RX25
I with
pullup
Input. Receive clock input from MII PHY.
Nibble rate clock. (25MHz for 100Mbps &
2.5MHz for 10Mbps).
121-124
123-126
Receive Data
RXD3RXD0
I with
pullup
Inputs. Received Data nibble from MII
PHY.
25
27
Management
Data Input
MDI
I with
pulldown
MII management data input.
26
28
Management
Data Output
MDO
O4
MII management data output.
27
29
Management
Clock
MCLK
O4
MII management clock.
126
128
Receive Error
RX_ER
I with
pulldown
Input. Indicates a code error detected by
PHY. Used by the LAN91C111 to discard
the packet being received. The error
indication reported for this event is the
same as a bad CRC (Receive Status
Word bit 13).
2
4
nChip Select
Output
nCSOUT
O4
Output. Chip Select provided for mapping
of PHY functions into LAN91C111
decoded space. Active on accesses to
LAN91C111’s eight lower addresses
when the BANK SELECTED is 7.
12
14
External
Resistor
RBIAS
NA
Transmit Current Set. An external resistor
connected between this pin and GND will
set the output current for the TP transmit
outputs
14
16
TPO+
O/I
Twisted Pair Transmit Output, Positive.
15
17
TPO-
O/I
Twisted Pair Transmit Output, Negative
17
19
TPI+
I/O
Twisted Pair Receive Input, Positive
18
20
TPI-
I/O
Twisted Pair Receive Input, Negative.
22
24
nLEDA
OD24
PHY LED Output
23
25
nLEDB
OD24
PHY LED Output
Note 5-1
If the EEPROM is enabled.
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2011-2016 Microchip Technology Inc.
LAN91C111
6.0
SIGNAL DESCRIPTION PARAMETERS
This section provides a detailed description of each Microchip LAN91C111 signal. The signals are arranged in functional
groups according to their associated function.
The ‘n’ symbol at the beginning of a signal name indicates that it is an active low signal. When ‘n’ is not present before
the signal name, it indicates an active high signal.
The term “assert” or “assertion” indicates that a signal is active; independent of whether that level is represented by a
high or low voltage. The term negates or negation indicates that a signal is inactive.
The term High-Z means tri-stated.
The term Undefined means the signal could be high, low, tri-stated, or in some in-between level.
6.1
Buffer Types
O4
Output buffer with 2mA source and 4mA sink
O12
Output buffer with 6mA source and 12mA sink
O16
Output buffer with 8mA source and 16mA sink
O24
Output buffer with 12mA source and 24mA sink
OD16
Open drain buffer with 16mA sink
OD24
Open drain buffer with 24mA sink
I/O4
Bidirectional buffer with 2mA source and 4mA sink
I/O24
Bidirectional buffer with 12mA source and 24mA sink
I/OD
Bidirectional Open drain buffer with 4mA sink
I
Input buffer
IS
Input buffer with Schmitt Trigger Hysteresis
Iclk
Clock input buffer
I/O
Differential Input
O/I
Differential Output
**
5V tolerant. Input pins are able to accept 5V signals
DC levels and conditions defined in the DC Electrical Characteristics section.
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DS00002276A-page 15
LAN91C111
7.0
FUNCTIONAL DESCRIPTION
7.1
Clock Generator Block
1.
2.
3.
4.
The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal.
TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10 Mbps
PHY, and 25 MHz for a 100 Mbps PHY).
RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive
state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
LCLK - Bus clock - Used by the BIU for synchronous accesses. Maximum frequency is 50 MHz for VL BUS mode,
and 8.33 MHz for EISA slave DMA.
7.2
CSMA/CD Block
This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out of the block
consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of the FIFO stores 32 bits to
exploit the 32 bit data path into memory, but the FIFOs themselves are 16 bit wide. The Control Path consists of a set
of registers interfaced to the CPU via the BIU.
7.2.1
DMA BLOCK
This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing received data. It interfaces the CSMA/CD Transmit and Receive FIFOs on one side and the Arbiter block on the other. To increase the bandwidth into memory, a 50 MHz clock is used by the DMA block, and the data path is 32 bits wide.
For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the Receive FIFO every
160ns. The DMA will read the FIFO and accumulate two words on the output port to request a memory cycle from the
Arbiter every 320ns.
The DMA machine is able to support full duplex operation. Independent receive and transmit counters are used. Transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed.
7.2.2
ARBITER BLOCK
The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement.
Internal SRAM read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the appropriate
lanes as a function of the address.
The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs can be
accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready' whenever a cycle is
initiated that cannot be satisfied by the present state of the FIFO.
7.3
MMU Block
The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also determines
the value of the transmit and receive interrupts as a function of the queues. The page size is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048 byte units.
7.4
BIU Block
The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one.
Transparent latches are added on the address path using rising nADS for latching.
When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and
nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C111 clock
and, therefore, asynchronous to the bus.
In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations. Completion of the
cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and synchronous to the bus.
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2011-2016 Microchip Technology Inc.
LAN91C111
Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting nDATACS, external DMA
type of devices will bypass the BIU address decoders and can sequentially access memory with no CPU intervention.
nDATACS accesses can be used in the EISA DMA burst mode (nVLBUS=1) or in asynchronous cycles. These cycles
MUST be 32 bit cycles. Please refer to the corresponding timing diagrams for details on these cycles.
The BIU is implemented using the following principles:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
Address decoding is based on the values of A15-A4 and AEN.
Address latching is performed by using transparent latches that are transparent when nADS=0 and nRD=1,
nWR=1 and latch on nADS rising edge.
Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword write to
offset Ch will only write the BANK SELECT REGISTER (offset 0x0Fh).
No bus byte swapping is implemented (no eight bit mode).
Word swapping as a function of A1 is implemented for 16 bit bus support.
The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading edge of
the strobe. The ARDY trailing edge is controlled by CLK.
The VLBUS synchronous interface uses LCLK, nADS, and W/nR as defined in the VESA specification as well as
nCYCLE to control read and write operations and generate nSRDY.
EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA Slave Mode "C"
specification when nDATACS is driven by nDAK.
Synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously.
Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating the nDATACS
pin.
7.5
MAC-PHY Interface
The LAN91C111 integrates the IEEE 802.3 Physical Layer (PHY) and Media Access Control (MAC) into the same silicon. The data path connection between the MAC and the internal PHY is provided by the internal MII. The LAN91C111
also supports the EXT_PHY mode for the use of an external PHY, such as HPNA. This mode isolates the internal PHY
to allow interface with an external PHY through the MII pins. To enter this mode, set EXT PHY bit to 1 in the Configuration Register.
7.5.1
MANAGEMENT DATA SOFTWARE IMPLEMENTATION
The MII interface contains of a pair of signals that physically transport the management information across the MII, a
frame format and a protocol specification for exchanging management frames, and a register set that can be read and
written using these frames. MII management refers to the ability of a management entity to communicate with PHY via
the MII serial management interface (MI) for the purpose of displaying, selecting and/or controlling different PHY
options. The host manipulates the MAC to drive the MII management serial interface. By manipulating the MAC's registers, MII management frames are generated on the management interface for reading or writing information from the
PHY registers. Timing and framing for each management command is to be generated by the CPU (host).
The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface.
MDIO:
Management Data input/output. Bi-directional between MAC and PHY that carries management data. All control and status information sent over this pin is driven and sampled synchronously to the rising edge of MDC
signal.
MDC:
Management Data Clock. Sourced by the MAC as a timing reference for transfer of information on the MDIO
signal. MDC is a periodic signal with no maximum high or low times. The minimum high and low times should
be 160ns each and the minimum period of the signal should be 400ns. These values are regardless of the nominal period of the TX and RX clocks.
7.5.2
MANAGEMENT DATA TIMING
A timing diagram for a Ml serial port frame is shown in Figure 7-1. The Ml serial port is idle when at least 32 continuous
1's are detected on MDIO and remains idle as long as continuous 1's are detected. During idle, MDIO is in the high
impedance state. When the Ml serial port is in the idle state, a 01 pattern on the MDIO initiates a serial shift cycle. Data
on MDIO is then shifted in on the next 14 rising edges of MDC (MDIO is high impedance). If the register access mode
is not enabled, on the next 16 rising edges of MDC, data is either shifted in or out on MDIO, depending on whether a
write or read cycle was selected with the bits READ and WRITE. After the 32 MDC cycles have been completed, one
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DS00002276A-page 17
LAN91C111
complete register has been read/written, the serial shift process is halted, data is latched into the device, and MDIO
goes into high impedance state. Another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous 1's) is detected.
7.5.3
MI SERIAL PORT FRAME STRUCTURE
The structure of the PHY serial port frame is shown in Table 9-1 and timing diagram of a frame is shown in Figure 7-1.
Each serial port access cycle consists of 32 bits (or 192 bits if multiple register access is enabled and
REGAD[4:0]=11111), exclusive of idle. The first 16 bits of the serial port cycle are always write bits and are used for
addressing. The last 16/176 bits are from one/all of the 11 data registers.
The first 2 bit in Table 9-1and Figure 7-1 are start bits and need to be written as a 01 for the serial port cycle to continue.
The next 2 bits are a read and write bit which determine if the accessed data register bits will be read or write. The next
5 bits are device addresses. The next 5 bits are register address select bits, which select one of the five data registers
for access. The next 1 bit is a turnaround bit which is not an actual register bit but extra time to switch MDIO from write
to read if necessary, as shown in Figure 7-1. The final 16 bits of the PHY Ml serial port cycle (or 176 bits if multiple register access is enabled and REGAD[4:0]=11111) come from the specific data register designated by the register address
bits REGAD[4:0].
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2011-2016 Microchip Technology Inc.
2011-2016 Microchip Technology Inc.
MDIO
MDC
ST[1:0]
0
0
READ CYCLE
ST[1:0]
0
0
1
1
1
1
OP[1:0]
1
2
OP[1:0]
0
2
0
1
3
3
P4
P3
P2
6
PHYAD[4:0]
P2
6
PHYAD[4:0]
5
P3
5
P1
7
P1
7
P0
8
P0
8
R4
9
R4
9
R3
R2
11
12
R1
REGAD[4:0]
R2
11
R1
12
R0
13
1
15
0
TA[1:0]
14
D15
16
D14
17
D13
18
R0
13
TA[1:0]
Z
14
0
15
D15
16
D14
17
D13
18
WRITE
BITS
PHY CLOCKS IN DATA ON RISING EDGES OF MDC
REGAD[4:0]
10
R3
10
WRITE
BITS
PHY CLOCKS IN DATA ON RISING EDGES OF MDC
4
P4
4
D12
19
D12
19
D10
21
D10
21
D9
22
D9
22
DATA[15:0]
D8
23
24
D7
24
D7
DATA[15:0]
D8
23
D6
25
D6
25
D5
26
D5
26
READ BITS
PHY CLOCKS OUT DATA ON RISING EDGES OF MDC
D11
20
D11
20
D4
27
D4
27
D3
28
D3
28
D2
29
D2
29
D1
30
D1
30
D0
31
D0
31
FIGURE 7-1:
MDIO
MDC
WRITE CYCLE
LAN91C111
MI SERIAL PORT FRAME TIMING DIAGRAM
DS00002276A-page 19
LAN91C111
7.5.4
MII PACKET DATA COMMUNICATION WITH EXTERNAL PHY
The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements
outlined in IEEE 802.3 and shown in Figure 7-2.
FIGURE 7-2:
MII FRAME FORMAT & MII NIBBLE ORDER
TX_EN = 1
TX_EN = 0
IDLE
TX_EN = 0
START
PREAMBLE
OF
FRAME
DELIM.
PRMBLE
SFD
62 BT
2 BT
IDLE
DATA NIBBLES
DATA 1
DATA 2
DATA N-1
DATA N
PREAMBLE = [ 1 0 1 0 ... ] 62 BITS LONG
SFD = [ 1 1 ]
DATAn = [ BETWEEN 64-1518 DATA BYTES ]
IDLE = TX_EN = 0
FIRST BIT
LSB
FIRST
NIBBLE
MAC's SERIAL BIT STREAM
D0
D1
D2
D3
D4
D5
D6
D7
MSB
SECOND
NIBBLE
TXD0 / RXD0
MII
NIBBLE
STREAM
TXD1 / RXD1
TXD2 / RXD2
TXD3 / RXD3
The Mll consists of the following signals: four transmit data bits (TXD[3:0]), transmit clock (TX25),transmit enable
(TXEN100), four receive data bits(RXD[3:0]), receive clock(RX25), carrier sense (CRS100), receive data valid (RX_DV),
receive data error (RX_ER), and collision (COL100). Transmit data is clocked out using the TX25 clock input, while receive
data is clocked in using RX25. The transmit and receive clocks operate at 25 MHz in 100Mbps mode and 2.5 MHz in
10Mbps.
In 100 Mbps mode, the LAN91C111 provides the following interface signals to the PHY:
• For transmission: TXEN100, TXD0-3, TX25
• For reception: RX_DV, RX_ER, RXD0-3, RX25
• For CSMA/CD state machines: CRS100, COL100
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble nibble. TXD0
carries the least significant bit of the nibble (that is the one that would go first out of the EPH at 100 Mbps), while TXD3
carries the most significant bit of the nibble. TXEN100 and TXD0-TXD3 are clocked by the LAN91C111 using TX25 rising edges. TXEN100 goes inactive at the end of the packet on the last nibble of the CRC.
During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to the
LAN91C111’s clocks and will be synchronized internally to TX25.
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will be present at
RXD0-RXD3 when RX_DV is activated. The LAN91C111 requires no training sequence beyond a full flag octet for
reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0 carries the least significant bit and
RXD3 the most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of the packet (CRC) is presented at RXD0-RXD3.
RX_ER might be asserted during packet reception to signal the LAN91C111 that the present receive packet is invalid.
The LAN91C111 will discard the packet by treating it as a CRC error.
DS00002276A-page 20
2011-2016 Microchip Technology Inc.
LAN91C111
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned
cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on non-preamble patterns.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff functions),
but it is not used for receive framing functions. CRS100 is an asynchronous signal and it will be active whenever there
is activity on the cable, including LAN91C111 transmissions and collisions.
7.6
Serial EEPROM Interface
This block is responsible for reading the serial EEPROM upon hardware reset (or equivalent command) and defining
defaults for some key registers. A write operation is also implemented by this block, that under CPU command will program specific locations in the EEPROM. This block is an autonomous state machine and controls the internal Data Bus
of the LAN91C111 during active operation.
7.7
Internal Physical Layer
The LAN91C111 integrates the IEEE 802.3 physical layer (PHY) internally. The EXT PHY bit in the Configuration Register is 0 as the default configuration to set the internal PHY enabled. The internal PHY address is 00000, the driver
must use this address to talk to the internal PHY. The internal PHY is placed in isolation mode at power up and reset. It
can be removed from isolation mode by clearing the MII_DIS bit in the PHY Control Register. If necessary, the internal
PHY can be enabled by clearing the EXT_PHY bit in the Configuration Register.
The internal PHY of LAN91C111 has nine main sections: controller interface, encoder, decoder, scrambler, descrambler,
clock and data recovery, twisted pair transmitter, twisted pair receiver, and MI serial port.
The LAN91C111 can operate as a 100BASE-TX device (hereafter referred to as 100Mbps mode) or as a 10BASE-T
device (hereafter referred to as 10Mbps mode). The difference between the 100Mbps mode and the 10Mbps mode is
data rate, signaling protocol, and allowed wiring. The 100Mbps TX mode uses two pairs of category 5 or better UTP or
STP twisted pair cable with 4B5B encoded, scrambled, and MLT-3 coded 62.5 MHz ternary data to achieve a throughput
of 100Mbps. The 10Mbps mode uses two pairs of category 3 or better UTP or STP twisted pair cable with Manchester
encoded, 10MHz binary data to achieve a 10Mbps throughput. The data symbol format on the twisted pair cable for the
100 and 10Mbps modes are defined in IEEE 802.3 specifications and shown in Figure 7-3.
2011-2016 Microchip Technology Inc.
DS00002276A-page 21
LAN91C111
FIGURE 7-3:
TX/10BT FRAME FORMAT
ETHERNET MAC
FRAME
INTERFRAME
GAP
PREAMBLE
SFD
DA
SA
LN
LLC DATA
FCS
LN
LLC DATA
FCS
INTERFRAME
GAP
100 BASE-TX DATA SYMBOLS
IDLE
SSD
PREAMBLE
DA
SFD
IDLE
SSD
SA
ESD
IDLE
SOI
IDLE
= [ 1 1 1 1...]
= [ 1 1 0 0 0 1 0 0 0 1]
BEFORE / AFTER
4B5B ENCODING,
SCRAMBLING,
AND MLT3
CODING
PREAMBLE = [ 1 0 1 0 ...] 62 BITS LONG
SFD = [ 1 1]
DA, SA, LN, LLC DATA, FCS = [ DATA]
ESD = [ 0 1 1 0 1 0 0 1 1 1]
10 BASE-T DATA SYMBOLS
IDLE
PREAMBLE
SFD
DA
SA
IDLE
= [ NO TRANSITIONS]
PREAMBLE = [ 1 0 1 0 ... ] 62 BITS LONG
SFD = [ 1 1]
DA, SA, LN, LLC DATA, FCS
= [ DATA]
LN
LLC DATA
FCS
BEFORE / AFTER
MANCHESTER
ENCODING
SOI = [ 1 1 ] WITH NO MID BIT TRANSITION
On the transmit side for 100Mbps TX operation, data is received on the controller and then sent to the 4B5B encoder
for formatting. The encoded data is then sent to the scrambler. The scrambled and encoded data is then sent to the TP
transmitter. The TP transmitter converts the encoded and scrambled data into MLT-3 ternary format, reshapes the output, and drives the twisted pair cable.
On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming encoded and scrambled MLT3 data from the twisted pair cable, remove any high frequency noise, equalizes the input signal to compensate for the
effects of the cable, qualifies the data with a squelch algorithm, and converts the data from MLT-3 coded twisted pair
levels to internal digital levels. The output of the twisted pair receiver then goes to a clock and data recovery block which
recovers a clock from the incoming data, uses the clock to latch in valid data into the device, and converts the data back
to NRZ format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler, respectively,
and outputted to the Ethernet controller.
10Mbps operation is similar to the 100Mbps TX operation except, (1) there is no scrambler/descrambler, (2) the
encoder/decoder is Manchester instead of 4B5B, (3) the data rate is 10Mbps instead of 100Mbps, and (4) the twisted
pair symbol data is two level Manchester instead of ternary MLT-3.
The Management Interface, (hereafter referred to as the MI serial port), is a two pin bi-directional link through which
configuration inputs can be set and status outputs can be read. Each block plus the operating modes are described in
more detail in the following sections.
7.7.1
MII DISABLE
The internal PHY MII interface can be disabled by setting the MII disable bit in the MI serial port Control register. When
the MII is disabled, the MII inputs are ignored, the MII outputs are placed in high impedance state, and the TP output is
high impedance.
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2011-2016 Microchip Technology Inc.
LAN91C111
7.7.2
ENCODER
7.7.2.1
4B5B Encoder - 100 Mbps
100BASE-TX requires that the data be 4B5B encoded. 4B5B coding converts the 4-Bit data nibbles into 5-Bit date code
words. The mapping of the 4B nibbles to the 5B code words is specified in IEEE 802.3. The 4B5B encoder on the
LAN91C111 takes 4B nibbles from the controller interface, converts them into 5B words and sends the 5B words to the
scrambler. The 4B5B encoder also substitutes the first 8 bits of the preamble with the SSD delimiters (a.k.a. /J/K/ symbols) and adds an ESD delimiter (a.k.a. MR/ symbols) to the end of every packet, as defined in IEEE 802.3. The 4B5B
encoder also fills the period between packets, called the idle period, with the continuous stream of idle symbols.
7.7.2.2
Manchester Encoder - 10 Mbps
The Manchester encoding process combines clock and NRZ data such that the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data, as specified in IEEE 802.3. This ensures
that a transition always occurs in the middle of the bit call. The Manchester encoder on the LAN91C111 converts the
10Mbps NRZ data from the controller interface into a Manchester Encoded data stream for the TP transmitter and adds
a start of idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. The Manchester encoding process is only
done on actual packet data, and the idle period between packets is not Manchester encoded and filled with link pulses.
7.7.3
DECODER
7.7.3.1
4B5B Decoder - 100 Mbps
Since the TP input data is 4B5B encoded on the transmit side, it must also be decoded by the 4B5B decoder on the
receive side. The mapping of the 5B nibbles to the 4B code words is specified in IEEE 802.3. The 4B5B decoder on the
LAN91C111 takes the 5B code words from the descrambler, converts them into 4B nibbles per Table 2, and sends the
4B nibbles to the controller interface. The 4B5B decoder also strips off the SSD delimiter (a.k.a. /J/K/ symbols) and
replaces them with two 4B Data 5 nibbles (a.k.a. /5/ symbol), and strips off the ESD delimiter (a.k.a. /T/R/ symbols) and
replaces it with two 4B Data 0 nibbles (a.k.a. /I/symbol), per IEEE 802.3 specifications and shown in Figure 7-3.
TABLE 7-1:
4B/5B SYMBOL MAPPING
Symbol Name
Description
5B Code
4B Code
0
Data 0
11110
0000
1
Data 1
01001
0001
2
Data 2
10100
0010
3
Data 3
10101
0011
4
Data 4
01010
0100
5
Data 5
01011
0101
6
Data 6
01110
0110
7
Data 7
01111
0111
8
Data 8
10010
1000
9
Data 9
10011
1001
A
Data A
10110
1010
B
Data B
10111
1011
C
Data C
11010
1100
D
Data D
11011
1101
E
Data E
11100
1110
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LAN91C111
TABLE 7-1:
4B/5B SYMBOL MAPPING (CONTINUED)
Symbol Name
Description
5B Code
4B Code
F
Data F
11101
1111
I
Idle
11111
0000
J
SSD #1
11000
0101
K
SSD #2
10001
0101
T
ESD #1
01101
0000
R
ESD #2
00111
0000
H
Halt
00100
Undefined
---
Invalid codes
All others*
0000*
* These 5B codes are not used. For decoder, these 5B codes are decoded to 4B 0000. For encoder, 4B 0000 is encoded
to 5B 11110, as shown in symbol Data 0.
The 4B5B decoder detects SSD, ESD and codeword errors in the incoming data stream as specified in IEEE 802.3.
These errors are indicated by asserting RX_ER output while the errors are being transmitted across RXD[3:0], and they
are also indicated in the serial port by setting SSD, ESD, and codeword error bits in the PHY MI serial port Status Output
register.
7.7.3.2
Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the
data bit contains the true data. The Manchester decoder in the LAN91C111 converts the Manchester encoded data
stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI
pulse. Since the clock and data recovery block has already separated the clock and data from the TP receiver, the Manchester decoding process to NRZ data is inherently performed by that block.
7.7.4
7.7.4.1
CLOCK AND DATA RECOVERY
Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked to the 25 MHz
TX25. When valid data is detected on the TP inputs with the squelch circuit and when the adaptive equalizer has settled,
the PLL input is switched to the incoming data on the TP input. The PLL then recovers a clock by locking onto the transitions of the incoming signal from the twisted pair wire. The recovered dock frequency is a 25 MHz nibble dock, and
that clock is outputted on the controller interface signal RX25.
7.7.4.2
Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted by the PLL. The
data is then converted from a single bit stream into nibble wide data word according to the format shown in Figure 7-2.
7.7.4.3
Clock Recovery - 10 Mbps
The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except, (1) the recovered clock frequency is 2.5 MHz nibble clock, (2) the PLL is switched from TX25 to the TP input when the squelch indicates valid data,
(3) The PLL takes up to 12 transitions (bit times) to lock onto the preamble, so some of the preamble data symbols are
lost, but the dock recovery block recovers enough preamble symbols to pass at least 6 nibbles of preamble to the
receive controller interface as shown in Figure 7-2.
7.7.4.4
Data Recovery - 10 Mbps
The data recovery process for 10Mbps mode is identical to the 100Mbps mode. As mentioned in the Manchester
Decoder section, the data recovery process inherently performs decoding of Manchester encoded data from the TP
inputs.
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LAN91C111
7.7.5
7.7.5.1
SCRAMBLER
100 Mbps
100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The LAN91C111 scrambler
takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends it to the TP
transmitter.
7.7.5.2
10 Mbps
A scrambler is not used in 10Mbps mode.
7.7.5.3
Scrambler Bypass
The scrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY Ml serial port Configuration
1 register. When this bit is set, the 5B data bypasses the scrambler and goes directly from the 4B5B encoder to the
twisted pair transmitter.
7.7.6
7.7.6.1
DESCRAMBLER
100 Mbps
The LAN91C111 descrambler takes the scrambled data from the data recovery block, descrambles it per the IEEE 802.3
specifications, aligns the data on the correct 5B word boundaries, and sends it to the 4B5B decoder.
The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE 802.3 specification. Once the descrambler is synchronized, it will maintain synchronization as long as enough descrambled idle pattern
1's are defected within a given interval. To stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1's in a 1ms interval. If 25 consecutive descrambled idle pattern 1's are not detected
within the 1ms interval, the descrambler goes out of synchronization and restarts the synchronization process.
If the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is set in the Ml serial
port Status Output register to indicate this condition. Once this bit is set, it will stay set until the descrambler achieves
synchronization.
7.7.6.2
10 Mbps
A descrambler is not used in 10 Mbps mode.
7.7.6.3
Descrambler Bypass
The descrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY MI serial port Configuration 1 register. When this bit is set, the data bypasses the descrambler and goes directly from the TP receiver to the
4B5B decoder.
7.7.7
7.7.7.1
TWISTED PAIR TRANSMITTER
Transmitter - 100 Mbps
The TX transmitter consists of MLT-3 encoder, waveform generator and line driver.
The MLT-3 encoder converts the NRZ data from the scrambler into a three level MLT-3 code required by IEEE 802.3.
MLT-3 coding uses three levels and converts 1's to transitions between the three levels, and converts 0's to no transitions or changes in level.
The purpose of the waveform generator is to shape the transmit output pulse. The waveform generator takes the MLT3 three level encoded waveform and uses an array of switched current sources to control the rise/fall time and level of
the signal at the Output. The output of the switched current sources then goes through a low pass filter in order to
"smooth" the current output and remove any high frequency components. In this way, the waveform generator preshapes the output waveform transmitted onto the twisted pair cable to meet the pulse template requirements outlined
in IEEE 802.3. The waveform generator eliminates the need for any external filters on the TP transmit output.
The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category
5 unshielded twisted pair cable or 150 Ohm shielded twisted pair cable.
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LAN91C111
7.7.7.2
Transmitter - 10 Mbps
The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter. Even so, the transmitter
still consists of a waveform generator and line driver.
The purpose of the waveform generator is to shape the output transmit pulse. The waveform generator consists of a
ROM, DAC, dock generator, and filter. The DAC generates a stair-stepped representation of the desired output waveform. The stairstepped DAC output then goes through a low pass filter in order to "smooth' the DAC output and remove
any high frequency components. The DAC values are determined from the ROM outputs; the ROM contents are chosen
to shape the pulse to the desired template and are clocked into the DAC at high speed by the clock generator. In this
way, the waveform generator preshapes the output waveform to be transmitted onto the twisted pair cable to meet the
pulse template requirements outlined in IEEE 802.3 Clause 14 and also shown in Figure 7-4. The waveshaper replaces
and eliminates external filters on the TP transmit output.
The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category
3/4/5 100 Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied directly to the TP output pins
without any external filters. During the idle period, no output signal is transmitted on the TP outputs (except link pulse).
FIGURE 7-4:
TP OUTPUT VOLTAGE TEMPLATE - 10 MBPS
N
B
1.0
0.8
P
H
0.6
D
0.4
C
I
O
E
Voltage (V)
0.2
Q
0.0
A
M
F
R
J
-0.2
S
-0.4
U
LK
-0.6
W
V
-0.8
G
-1.0
0
10
20
30
40
50
60
70
80
90
100
T
10
TIME (ns)
Reference
Time (NS) Internal MAU
Voltage (V)
A
0
0
B
15
1.0
C
15
0.4
D
25
0.55
E
32
0.45
F
39
0
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LAN91C111
7.7.7.3
Reference
Time (NS) Internal MAU
Voltage (V)
G
57
-1.0
H
48
0.7
I
67
0.6
J
89
0
K
74
-0.55
L
73
-0.55
M
61
0
N
85
1.0
O
100
0.4
P
110
0.75
Q
111
0.15
R
111
0
S
111
-0.15
T
110
-1.0
U
100
-0.3
V
110
-0.7
W
90
-0.7
Transmit Level Adjust
The transmit output current level is derived from an internal reference voltage and the external resistor on RBIAS pin.
The transmit level can be adjusted with either (1) the external resistor on the RBIAS pin, or (2) the four transmit level
adjust bits in the PHY Ml serial port Configuration 1 register as shown in Table 7-2. The adjustment range is approximately -14% to +16% in 2% steps.
TABLE 7-2:
TRANSMIT LEVEL ADJUST
TLVL[3:0]
Gain
0000
1.16
0001
1.14
0010
1.12
0011
1.10
0100
1.08
0101
1.06
0110
1.04
0111
1.02
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TABLE 7-2:
7.7.7.4
TRANSMIT LEVEL ADJUST (CONTINUED)
TLVL[3:0]
Gain
1000
1.00
1001
0.98
1010
0.96
1011
0.94
1100
0.92
1101
0.90
1110
0.88
1111
0.86
Transmit Rise and Fall Time Adjust
The transmit output rise and fall time can be adjusted with the two transmit rise/fall time adjust bits in the PHY Ml serial
port Configuration 1. The adjustment range is -0.25ns to +0.5ns in 0.25ns steps.
7.7.7.5
STP (150 Ohm) Cable Mode
The transmitter can be configured to drive 150 Ohm shielded twisted pair cable. The STP mode can be selected by
appropriately setting the cable type select bit in the PHY MI serial port Configuration 1 register. When STP mode is
enabled, the output current is automatically adjusted to comply with IEEE 802.3 levels.
7.7.7.6
Transmit Disable
The TP transmitter can be disabled by setting the transmit disable bit in the PHY Ml serial port Configuration 1 register.
When the transmit disable bit is set, the TP transmitter is forced into the idle state, no data is transmitted, no link pulses
are transmitted, and internal loopback is disabled.
7.7.7.7
Transmit Powerdown
The TP transmitter can be powered down by setting the transmit powerdown bit in the PHY Ml serial port Configuration
1 register. When the transmit powerdown bit is set, the TP transmitter is powered down, the TP transmit outputs are
high impedance, and the rest of the LAN91C111 operates normally.
7.7.8
7.7.8.1
TWISTED PAIR RECEIVER
Receiver - 100 Mbps
The TX receiver detects input signals from the twisted pair input and converts it to a digital data bit stream ready for dock
and data recovery. The receiver can reliably detect data from a 100BASE-TX transmitter that has been passed through
0-100 meters of 100-Ohm category 5 UTP or 150 Ohm STP.
The TX receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and MLT-3 decoder.
The TP inputs first go to an adaptive equalizer. The adaptive equalizer compensates for the low pass characteristic of
the cable, and it has the ability to adapt and compensate for 0-100 meters of category 5, 100 Ohm UTP or 150 Ohm
STP twisted pair cable. The baseline wander correction circuit restores the DC component of the input waveform that
was removed by external transformers. The comparators convert the equalized signal back to digital levels and are used
to qualify the data with the squelch circuit. The MLT-3 decoder takes the three level MLT-3 digital data from the comparators and converts it to back to normal digital data to be used for dock and data recovery.
7.7.8.2
Receiver - 10 Mbps
The 10 Mbps receiver is able to detect input signals from the twisted pair cable that are within the template shown in
Figure 7-5. The inputs are biased by internal resistors. The TP inputs pass through a low pass filter designed to eliminate
any high frequency noise on the input. The output of the receive filter goes to two different types of comparators, squelch
and zero crossing. The squelch comparator determines whether the signal is valid, and the zero crossing comparator
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LAN91C111
is used to sense the actual data transitions once the signal is determined to be valid. The output of the squelch comparator goes to the squelch circuit and is also used for link pulse detection, SOI detection, and reverse polarity detection;
the output of the zero crossing comparator is used for clock and data recovery in the Manchester decoder.
FIGURE 7-5:
TP INPUT VOLTAGE TEMPLATE -10MBPS
a. Short Bit
3.1V
Slope 0.5 V/ ns
585mV
585 mV sin (
*t/PW)
PW
0
b. Long Bit
3.1V
Slope 0.5 V/ ns
585mV
585 mV sin (2 * t/PW)
585 mV sin [2
0
7.7.8.3
PW/4
(t - PW/2)/PW]
3PW/4
PW
TP Squelch - 100 Mbps
The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one of the criteria used
to determine link integrity. The squelch comparators compare the TP inputs against fixed positive and negative thresholds, called squelch levels. The output from the squelch comparator goes to a digital squelch circuit which determines
if the receive input data on that channel is valid. If the data is invalid, the receiver is in the squelched state. If the input
voltage exceeds the squelch levels at least 4 times with alternating polarity within a 10 S interval, the data is considered
to be valid by the squelch circuit and the receiver now enters into the unsquelch state. In the unsquelch state, the receive
threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. When
the receiver is in the unsquelch state, then the input signal is deemed to be valid. The device stays in the unsquelch
state until loss of data is detected. Loss of data is detected if no alternating polarity unsquelch transitions are detected
during any 10 S interval. When the loss of data is detected, the receive squelch is turned on again.
7.7.8.4
TP Squelch, 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps mode except, (1) the 10 Mbps TP squelch
algorithm is not used for link integrity but to sense the beginning of a packet, (2) the receiver goes into the unsquelch
state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50-250 nS interval, (3) the receiver goes into the squelch state when idle is detected, (4) unsquelch detection has no affect on link integ-
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LAN91C111
rity, link pulses are used for that in 10 Mbps mode, (5) start of packet is determined when the receiver goes into the
unsquelch state an a CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3
Clause 14.
7.7.8.5
Equalizer Disable
The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY Ml serial port Configuration 1
register. When disabled, the equalizer is forced into the response it would normally have if zero cable length was
detected.
7.7.8.6
Receive Level Adjust
The receiver squelch and unsquelch levels can be lowered by 4.5 dB by setting the receive level adjust bit in the PHY
Ml serial port Configuration 1 register. By setting this bit, the device may be able to support longer cable lengths.
7.7.9
7.7.9.1
COLLISION
100 Mbps
Collision occurs whenever transmit and receive occur simultaneously while the device is in Half Duplex.
Collision is sensed whenever there is simultaneous transmission (packet transmission on TPO±) and reception (nonidle symbols detected on TP input). When collision is detected, the MAC is notified. Once collision starts, the receive
and transmit packets that caused the collision are terminated by their respective MACs until the responsible MACs terminate the transmission, the PHY continues to pass the data on.
The collision function is disabled if the device is in the Full Duplex mode, is in the Link Fail State, or if the device is in
the diagnostic loopback mode.
7.7.9.2
10 Mbps
Collision in 10Mbps mode is identical to the 100Mbps mode except, (1) reception is determined by the 10Mbps squelch
criteria, (2) data being passed to the MAC are forced to all 0's, (3) MAC is notified of the collision when the SQE test is
performed, (4) MAC is notified of the collision when the jabber condition has been detected.
7.7.9.3
Collision Test
The MAC and PHY collision indication can be tested by setting the collision test register bit in the PHY MI serial port
Control register. When this bit is set, internal TXEN from the MAC is looped back onto COL and the TP outputs are
disabled.
7.7.10
7.7.10.1
START OF PACKET
100 Mbps
Start of packet for 100 Mbps mode is indicated by a unique Start of Stream Delimiter (referred to as SSD). The SSD
pattern consists of the two /J/K/ 5B symbols inserted at the beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24.
The transmit SSD is generated by the 4B5B encoder and the /J/K/ symbols are inserted by the 4B5B encoder at the
beginning of the transmit data packet in place of the first two 5B symbols of the preamble.
The receive pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits (two 5B words)
from the descrambler. Between packets, the receiver will be detecting the idle pattern, which is 5B /I/ symbols. While in
the idle state, the MAC is notified that no data/invalid data is received.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /J/K/ symbols, the start
of packet is detected, data reception is begun, the MAC is notified that valid data is received, and 5/5/ symbols are substituted in place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/I/
nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered
to be faulty and a False Carrier Indication (also referred to as bad SSD) is signaled to the controller interface. When
False Carrier is detected, the MAC is notified of false carrier and invalid received, and the bad SSD bit is set in the PHY
Ml serial port Status Output register. Once a False Carrier Event is detected, the idle pattern (two /I/I/ symbols) must be
detected before any new SSD's can be sensed.
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LAN91C111
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /l/l/
nor /J/K/ symbols but does not contain at least 2 non-contiguous 0's, the data is ignored and the receiver stays in the
idle state.
7.7.10.2
10 Mbps
Since the idle period in 10 Mbps mode is defined to be the period when no data is present on the TP inputs, then the
start of packet for 10 Mbps mode is detected when valid data is detected by the TP squelch circuit. When start of packet
is detected, carrier sense signal at internal MII is asserted as described in the Controller Interface section. Refer to the
TP squelch section for 10 Mbps mode for the algorithm for valid data detection.
7.7.11
7.7.11.1
END OF PACKET
100 Mbps
End of packet for 100 Mbps mode is indicated by the End of Stream Delimiter (referred to as ESD). The ESD pattern
consists of the two /T/R/ 4B5B symbols inserted after the end of the packet, as defined in IEEE 802.3 Clause 24.
The transmit ESD is generated by the 4B5B encoder and the /T/R/ symbols are inserted by the 4B5B encoder after the
end of the transmit data packet.
The receive ESD pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits (two 5B
words) from the descrambler during valid packet reception to determine if there is an ESD.
If the 10 consecutive code bits from the receiver during valid packet reception consist of the /T/R/ symbols, the end of
packet is detected, data reception is terminated, the MAC is notified of valid data received, and /I/I/ symbols are substituted in place of the /T/R/ symbols.
If 10 consecutive code bits from the receiver during valid packet reception do not consist of /T/R/ symbols but consist
of /I/I/ symbols instead, then the packet is considered to have been terminated prematurely and abnormally. When this
premature end of packet condition is detected, the MAC is notified of invalid data received for the nibble associated with
the first /I/ symbol. Premature end of packet condition is also indicated by setting the bad ESD bit in the PHY Ml serial
port Status Output register.
7.7.11.2
10 Mbps
The end of packet for 10 Mbps mode is indicated with the SOI (Start of Idle) pulse. The SOI pulse is a positive pulse
containing a Manchester code violation inserted at the end of every packet.
The transmit SOI pulse is generated by the TP transmitter and inserted at the end of the data packet after TXEN is deasserted. The transmitted SOI output pulse at the TP output is shaped by the transmit waveshaper to meet the pulse template requirements specified in IEEE 802.3 Clause 14 and shown in Figure 7-6.
The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI pulse is
detected, data reception is ended and the MAC is notified of no data/invalid data received.
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LAN91C111
FIGURE 7-6:
SOI OUTPUT VOLTAGE TEMPLATE - 10MBPS
0 BT
4.5 BT
3.1 V
0.5 V/ns
0.25 BT
2.25 BT
585 mV
6.0 BT
+50 mV
-50 mV
45.0 BT
585 mV sin(2 * * (t/1BT))
0 t 0.25 BT and
2.25 t 2.5 BT
-3.1 V
2.5 BT
7.7.12
7.7.12.1
4.5 BT
LINK INTEGRITY & AUTO-NEGOTIATION
General
The LAN91C111 can be configured to implement either the standard link integrity algorithms or the Auto-Negotiation
algorithm.
The standard link integrity algorithms are used solely to establish an active link to and from a remote device. There are
different standard link integrity algorithms for 10 and 100 Mbps modes. The Auto-Negotiation algorithm is used for two
purposes: (1) To automatically configure the device for either 10/100 Mbps and Half/Full Duplex modes, and (2) to establish an active link to and from a remote device. The standard link integrity and Auto-Negotiation algorithms are described
below.
Auto-Negotiation is only specified for 100BASE-TX and 10BASE-T operation.
7.7.12.2
10BASE-T Link Integrity Algorithm - 10Mbps
The LAN91C111 uses the same 10BASE-T link integrity algorithm that is defined in IEEE 802.3 Clause 14. This algorithm uses normal link pulses, referred to as NLP's and transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called Link Pass State). The transmit link pulse meets the template
defined in IEEE 802.3 Clause 14 and shown in Figure 7-7. Refer to IEEE 802.3 Clause 14 for more details if needed.
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LAN91C111
FIGURE 7-7:
LINK PULSE OUTPUT VOLTAGE TEMPLATE - NLP, FLP
1.3
BT
0
BT
3.1 V
0.5 V/ns
585 mV
0.5
BT 0.6
BT
2.0
BT
300 mV
4.0
BT
+50 mV
+50 mV
-50 mV
0.25
BT
200 mV
-50 mV
4.0
BT
42.0
BT
-3.1 V
0.85
BT
7.7.12.3
2.0
BT
100BASE-TX Link Integrity Algorithm - 100Mbps
Since 100BASE-TX is defined to have an active idle signal, then there is no need to have separate link pulses like those
defined for 10BASE-T. The LAN91C111 uses the squelch criteria and descrambler synchronization algorithm on the
input data to determine if the device has successfully established a link with a remote device (called Link Pass State).
Refer to IEEE 802.3 for both of these algorithms for more details.
7.7.12.4
Auto-Negotiation Algorithm
As stated previously, the Auto-Negotiation algorithm is used for two purposes: (1) To automatically configure the device
for either 10/100 Mbps and Half/ Full Duplex modes, and (2) to establish an active link to and from a remote device. The
Auto-Negotiation algorithm is the same algorithm that is defined in IEEE 802.3 Clause 28. Auto-Negotiation uses a burst
of link pulses, called fast link pulses and referred to as FLP'S, to pass up to 16 bits of signaling data back and forth
between the LAN91C111 and a remote device. The transmit FLP pulses meet the templated specified in IEEE 802.3
and shown in Figure 7-7. A timing diagram contrasting NLP's and FLP's is shown in Figure 7-8.
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FIGURE 7-8:
NLP VS. FLP LINK PULSE
a.) Normal Link Pulse (NLP)
TPO±
b.) Fast Link Pulse (FLP)
TPO±
D0
Clock
D1
Clock
Data
D2
Clock
Data
D3
Clock
Data
D14
Clock
Data
D15
Clock
Data
Clock
Data
The Auto-Negotiation algorithm is initiated by any of these events: (1) Auto-Negotiation enabled, (2) a device enters the
Link Fail State, (3) Auto-Negotiation Reset. Once a negotiation has been initiated, the LAN91C111 first determines if the
remote device has Auto-Negotiation capability. If the remote device is not Auto-Negotiation capable and is just transmitting either a 10BASE-T or 100BASE-TX signal, the LAN91C111 will sense that and place itself in the correct mode. If
the LAN91C111 detects FLP's from the remote device, then the remote device is determined to have Auto-Negotiation
capability and the device then uses the contents of the Ml serial port Auto-Negotiation Advertisement register and FLP's
to advertise its capabilities to a remote device. The remote device does the same, and the capabilities read back from
the remote device are stored in the PHY Ml serial port Auto-Negotiation Remote End Capability register. The
LAN91C111 negotiation algorithm then matches it's capabilities to the remote device's capabilities and determines what
mode the device should be configured to according to the priority resolution algorithm defined in IEEE 802.3 Clause 28.
Once the negotiation process is completed, the LAN91C111 then configures itself for either 10 or 100 Mbps mode and
either Full or Half Duplex modes (depending on the outcome of the negotiation process), and it switches to either the
100BASETX or 10BASE-T link integrity algorithms (depending on which mode was enabled by Auto-Negotiation). Refer
to IEEE 802.3 Clause 28 for more details.
7.7.12.5
Auto-Negotiation Outcome Indication
The outcome or result of the Auto-Negotiation process is stored in the speed detect and duplex detect bits in the PHY
MI serial port Status Output register.
7.7.12.6
Auto-Negotiation Status
The status of the Auto-Negotiation process can be monitored by reading the Auto-Negotiation acknowledgment bit in
the Ml serial port Status register. The Ml serial port Status register contains a single Auto-Negotiation acknowledgment
bit which indicates when an Auto-Negotiation has been initiated and successfully completed.
7.7.12.7
Auto-Negotiation Enable
The Auto-Negotiation algorithm can be enabled by setting both the ANEG bit in the MAC Receive/PHY Control Register
and the ANEG_EN bit in the MI PHY Register 0 (Control register). Clearing either of these two bits will turn off AutoNegotiation mode. When the Auto-Negotiation algorithm is enabled, the device halts all transmissions including link
pulses for 1200-1500 ms, enters the Link Fail State, and restarts the negotiation process. When Auto-Negotiation mode
is turned on or reset, software driver should wait for at least 1500ms to read the ANEG_ACK bit in the MI PHY Status
Register to determine whether the Auto-Negotiation process has been completed. When the ANEG bit in the
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LAN91C111
Receive/PHY Control Register is cleared, Auto-Negotiation algorithm is disabled, the selection of 10/100 Mbps mode
and duplex mode is determined by the SPEED bit and the DPLX bit in the MAC Receive/PHY Control register. When
the ANEG bit in the Receive/PHY Control Register is set and the ANEG_EN bit in the MI PHY Register 0 (Control Register) is cleared, Auto-Negotiation algorithm is disabled, the selection of 10/100 Mbps mode and duplex mode is determined by the SPEED bit and the DPLX bit in the MI PHY Register 0 (Control Register).
7.7.12.8
Auto-Negotiation Reset
The Auto-Negotiation algorithm can be initiated at any time by setting the Auto-Negotiation reset bit in the PHY MI serial
port Control register.
7.7.12.9
Link Disable
The link integrity function can be disabled by setting the link disable bit in the PHY Ml serial port Configuration 1 register.
When the link integrity function is disabled, the device is forced into the Link Pass state, configures itself for Half/Full
Duplex based on the value of the duplex bit in the PHY MI serial port Control register, configures itself for 100/10 Mbps
operation based on the values of the speed bit in the Ml serial port Control register, and continues to transmit NLP'S or
TX idle patterns, depending on whether the device is in 10 or 100 Mbps mode.
7.7.13
7.7.13.1
JABBER
100 Mbps
Jabber function is disabled in the 100 Mbps mode.
7.7.13.2
10 Mbps
Jabber condition occurs when the transmit packet exceeds a predetermined length. When jabber is detected, the TP
transmit outputs are forced to the idle state, collision is asserted, and register bits in the PHY Ml serial port Status and
Status Output registers are set.
7.7.13.3
Jabber Disable
The jabber function can be disabled by setting the jabber disable bit in the PHY MI serial port Configuration 2 register.
7.7.14
7.7.14.1
RECEIVE POLARITY CORRECTION
100 Mbps
No polarity detection or correction is needed in 100Mbps mode.
7.7.14.2
10 Mbps
The polarity of the signal on the TP receive input is continuously monitored. If either 3 consecutive link pulses or one
SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally determined to be incorrect, and a
reverse polarity bit is set in the PHY Ml serial port Status Output register.
The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not
disabled.
Note:
7.7.14.3
The first 3 received packets must be discarded after the correction of a reverse polarity condition.
Autopolarity Disable
The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2
register.
7.7.15
7.7.15.1
FULL DUPLEX MODE
100 Mbps
Full Duplex mode allows transmission and reception to occur simultaneously. When Full Duplex mode is enabled, collision is disabled.
The device can be either forced into Half or Full Duplex mode, or the device can detect either Half or Full Duplex capability from a remote device and automatically place itself in the correct mode.
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LAN91C111
The device can be forced into the Full or Half Duplex modes by either setting the duplex bit in the MI serial port Control
register.
The device can automatically configure itself for Full or Half Duplex modes by using the Auto-Negotiation algorithm to
advertise and detect Full and Half Duplex capabilities to and from a remote terminal. All of this is described in detail in
the Link Integrity and Auto-Negotiation section.
7.7.15.2
10 Mbps
Full Duplex in 10 Mbps mode is identical to the 100 Mbps mode.
7.7.15.3
100/10 Mbps Selection
General
The device can be forced into either the 100 or 10 Mbps mode, or the device also can detect 100 or 10 Mbps capability
from a remote device and automatically place itself in the correct mode.
The device can be forced into either the 100 or 10 Mbps mode by setting the speed select bit in the PHY MI serial port
Control register assuming Auto-Negotiation is not enabled.
The device can automatically configure itself for 100 or 10 Mbps mode by using the Auto-Negotiation algorithm to advertise and detect 100 and 10 Mbps capabilities to and from a remote terminal. All of this is described in detail in the Link
Integrity & Auto-Negotiation section.
7.7.16
7.7.16.1
LOOPBACK
Diagnostic Loopback
A diagnostic loopback mode can also be selected by setting the loopback bit in the MI serial port Control register. When
diagnostic loopback is enabled, transmit data at internal MII is looped back onto receive data output at internal MII, transmit enable signal is looped back onto carrier sense output at internal MII, the TP receive and transmit paths are disabled,
the transmit link pulses are halted, and the Half/Full Duplex modes do not change.
7.7.17
PHY POWERDOWN
The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY Ml serial port Control
register. In powerdown mode, the TP outputs are in high impedance state, all functions are disabled except the PHY Ml
serial port, and the power consumption is reduced to a minimum. To restore PHY to normal power mode, set the PDN
bit in PHY MI Register 0 to 0. The PHY is then in isolation mode (MII_DIS bit is set); This MII_DIS bit is needed to be
cleared. The device is ready for normal operation 500mS after powerdown is de-asserted.
Note:
7.7.18
The PDN bit must not be set when the device is in external PHY mode.
PHY INTERRUPT
The LAN91C111 PHY has interrupt capability. The interrupt is triggered by certain output status bits (also referred to as
interrupt bits) in the serial port. R/LT bits are read bits that latch on transition. R/LT bits are also interrupt bits if they are
not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register locations and
assert the interrupt indication when they change state. Interrupt bits stay latched until they are read. When interrupt bits
are read, the interrupt indication is deasserted and the interrupt bits that caused the interrupt to happen are updated to
their current value. Each interrupt bit can be individually masked and subsequently be removed as an interrupt bit by
setting the appropriate mask register bits in the Mask register.
lnterrupt indication is done in two ways: (1) MDINT bit in Interrupt Status Register, (2) INT bit in the PHY Ml Serial Port
Status Output register. The INT bit is an active high interrupt register bit that resides in the PHY MI Serial Port Status
Output register.
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LAN91C111
7.8
Reset
The chip (MAC & PHY) performs an internal system reset when either (1) the RESET pin is asserted high for at least
100ns, (2) writing “1” to the SOFT_RST bit in the Receive Control Register, this reset bit is not a self-clearing bit, reset
can be terminated by writing the bit low. It programs all registers to their default value. When reset is initiated by (1) and
the EEPROM is presented and enabled, the controller will load the EEPROM to obtain the following configurations: 1)
Configuration Register, 2) BASE Register, or/and 3) MAC Address. The internal MAC is not a power on reset device,
thus reset is required after power up to ensure all register bits are in default state.
The internal PHY is reset when either (1) VDD is applied to the device, (2) the RST bit is set in the PHY Ml serial port
Control register, this reset bit is a self-clearing bit, and the PHY will return a “1” on reads to this bit until the reset is
completed, 3) the RESET pin is asserted high, (4) the SOFT_RST bit is set high and then cleared. When reset is initiated
by (1) or (2), an internal power-on reset pulse is generated which resets all internal circuits, forces the PHY Ml serial
port bits to their default values, and latches in new values for the MI address. After the power-on reset pulse has finished,
the reset bit in the PHY Ml serial port Control registers cleared and the device is ready for normal operation. When reset
is initiated by (3), the same procedure occurs except the device stays in the reset state as long as the RESET pin is
held high. The internal PHY is ready for normal operation 50 mS after the reset pin was de-asserted or the reset bit is
set. Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again.
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LAN91C111
8.0
MAC DATA STRUCTURES AND REGISTERS
8.1
Frame Format In Buffer Memory
The frame format in memory is similar for the Transmit and Receive areas. The first word is reserved for the status word.
The next word is used to specify the total number of bytes, and it is followed by the data area. The data area holds the
frame itself. By default, the last byte in the receive frame format is followed by the CRC, and the Control byte follows
the CRC.
FIGURE 8-1:
DATA FRAME FORMAT
bit0
bit15
RAM
OFFSET
(DECIMAL)
2nd Byte
1st Byte
0
2
STATUS WORD
BYTE COUNT (always even)
RESERVED
4
DATA AREA
CRC (4 BYTES)
2046 Max
CONTROL BYTE
LAST DATA BYTE (if odd)
Last Byte
Transmit Packet
Receive Packet
STATUS WORD
Written by CSMA upon transmit
completion (see Status Register)
Written by CSMA upon receive
completion (see RX Frame Status
Word)
BYTE COUNT
Written by CPU
Written by CSMA
DATA AREA
Written/modified by CPU
Written by CSMA
CONTROL BYTE
Written by CPU to control odd/even
data bytes
Written by CSMA; also has odd/even
bit
BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT
WORD, the DATA AREA, the CRC, and the CONTROL BYTE. The CRC is not included if the STRIP_CRC bit is set.
The maximum number of bytes in a RAM page is 2048 bytes.
The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of
the last word is relevant.
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LAN91C111
The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory.
DATA AREA - The data area starts at offset 4 of the packet structure and can extend up to 2043 bytes.
The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS, followed
by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
LAN91C111 does not insert its own source address. On receive, all bytes are provided by the CSMA side.
The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C111. It is treated transparently
as data both for transmit and receive operations.
CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the CPU as:
X
X
ODD
CRC
0
0
0
0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the
number of data bytes is even and the byte before the CONTROL BYTE is not transmitted.
CRC - When set, CRC will be appended to the frame. This bit has meaning only if the NOCRC bit in the TCR is set.
For receive packets the CONTROL BYTE is written by the controller as:
0
1
ODD
0
0
0
0
0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the
number of data bytes is even and the byte before the CONTROL BYTE should be ignored.
8.2
Receive Frame Status
This word is written at the beginning of each receive frame in memory. It is not available as a register.
HIGH
BYTE
ALGN
ERR
BROD
CAST
BAD
CRC
LOW
BYTE
ODD
FRM
TOOLNG
TOO
SHORT
HASH VALUE
Reserved
5
4
3
MULT
CAST
2
1
0
ALGNERR - Frame had alignment error.
BROADCAST - Receive frame was broadcast. When a broadcast packet is received, the MULTCAST bit may be also
set on the status word in addition to the BRODCAST bit. The software implement may just ignore the MULTCAST bit if
for BRODCAST packet.
BADCRC - Frame had CRC error, or RX_ER was asserted during reception.
ODDFRM - This bit when set indicates that the received frame had an odd number of bytes.
TOOLNG - Frame length was longer than 802.3 maximum size (1518 bytes on the cable).
TOOSHORT - Frame length was shorter than 802.3 minimum size (64 bytes on the cable).
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LAN91C111
HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed
up the group address search. The hash value consists of the six most significant bits of the CRC calculated on the Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the hash value select a byte of the multicast table,
while bits 2,1,0 determine the bit within the byte selected. Examples of the address mapping:
Address
Hash Value 5-0
ED 00 00 00 00 00
0D 00 00 00 00 00
01 00 00 00 00 00
2F 00 00 00 00 00
000 000
010 000
100 111
111 111
Multicast Table Bit
MT-0
MT-2
MT-4
MT-7
bit
bit
bit
bit
0
0
7
7
MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set, and the address
was a multicast, the packet will pass address filtering regardless of other filtering criteria.
8.3
I/O Space
The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O area is shared by all banks
and can be used to change the bank in use. Registers are described using the following convention:
OFFSET
HIGH
BYTE
LOW
BYTE
NAME
TYPE
SYMBOL
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
X
X
X
X
X
X
X
X
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
X
X
X
X
X
X
X
X
FFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided the bank select
has the appropriate value.
The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.
The odd byte can be accessed using address (offset + 1).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that
case the offset of each one is independently specified.
Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.
The default bit values upon hard reset are highlighted below each register.
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LAN91C111
TABLE 8-1:
INTERNAL I/O SPACE MAPPING
BANK0
TCR
EPH STATUS
RCR
COUNTER
MIR
RPCR
RESERVED
BANK
0
2
4
6
8
A
C
E
BANK1
CONFIG
BASE
IA0-1
IA2-3
IA4-5
GENERAL PURPOSE
CONTROL
BANK
BANK2
MMU COMMAND
PNR
FIFO PORTS
POINTER
DATA
DATA
INTERRUPT
BANK
BANK3
MT0-1
MT2-3
MT4-5
MT6-7
MGMT
REVISION
RCV
BANK
A special BANK (BANK7) exists to support the addition of external registers.
8.4
Bank Select Register
HIGH
BYTE
OFFSET
NAME
TYPE
SYMBOL
E
BANK SELECT REGISTER
READ/WRITE
BSR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
BS2
BS1
BS0
0
0
0
LOW
BYTE
X
X
X
X
X
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register
bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C111.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2.
Note:
The bank select register can be accessed as a doubleword at offset 0x0Ch, as a word at offset 0x0Eh, or
as a byte at offset 0x0Eh, A doubleword write to offset 0x0Ch will write the BANK SELECT REGISTER but
will not write the registers 0x0Ch and 0x0Dh, but will only write to register 0x0Eh.
BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles where BANK7 is
selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers.
Note:
BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be
done if the Revision Control register indicates the device is the LAN91C111.
Bank 7 is a new register Bank to the Microchip LAN91C111 device. This bank has extended registers that allow the
extended feature set of the Microchip LAN91C111.
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LAN91C111
8.5
Bank 0 - Transmit Control Register
OFFSET
NAME
TYPE
SYMBOL
0
TRANSMIT CONTROL
REGISTER
READ/WRITE
TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH
BYTE
LOW
BYTE
SWFDUP
Reserved
EPH
LOOP
STP
SQET
FDUPLX
MON_
CSN
Reserved
NOCRC
0
0
0
0
0
0
0
0
PAD_EN
Reserved
Reserved
Reserved
Reserved
FORCOL
LOOP
TXENA
0
0
0
0
0
0
0
0
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from recognizing carrier sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision related status bits in the
EPHSR are not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and SNGL COL). Uses COL100 as flow control,
limiting backoff and jam to 1 clock each before inter-frame gap, then retry will occur after IFG. If COL100 is active during
preamble, full preamble will be output before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have
no effect.
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults low. When
EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3 = 0h, TXEN100 = 0. The following
and external inputs are blocked: CRS100=0, COL100=0, RX_DV= RX_ER=0.
STP_SQET - STP_SQET - Stop transmission on SQET error. If this bit is set, LAN91C111 will stop and disable the transmitter on SQE test error. If the external SQET generator on the network generates the SQET pulse during the IPG (Inter
Frame Gap), this bit will not be set and subsequent transmits will occur as in the case of implementing “Auto Release”
for multiple transmit packets. If this bit is cleared, then the SQET bit in the EPH Status register will be cleared. Defaults
low.
FDUPLX - When set the LAN91C111 will cause frames to be received if they pass the address filter regardless of the
source for the frame. When clear the node will not receive a frame sourced by itself. This bit does not control the duplex
mode operation, the duplex mode operation is controlled by the SWFDUP bit.
MON_CSN - When set the LAN91C111 monitors carrier while transmitting. It must see its own carrier by the end of the
preamble. If it is not seen, or if carrier is lost during transmission, the transmitter aborts the frame without CRC and turns
itself off and sets the LOST CARR bit in the EPHSR. When this bit is clear the transmitter ignores its own carrier. Defaults
low. Should be 0 for MII operation.
NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired CRC. Defaults
to zero, namely CRC inserted.
PAD_EN - When set, the LAN91C111 will pad transmit frames shorter than 64 bytes with 00. For TX, CPU should write
the actual BYTE COUNT before padded by the LAN91C111 to the buffer RAM, excludes the padded 00. When this bit
is cleared, the LAN91C111 does not pad frames.
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only
by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C111
will transmit a preamble pattern the next time a carrier is seen on the line. If a packet is queued, a preamble and SFD
will be transmitted. This bit defaults low to normal operation. NOTE: The LATCOL bit in the EPHSR, setting up as a
result of FORCOL, will reset TXENA to 0. In order to force another collision, TXENA must be set to 1 again.
LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY chip in loopback mode.
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LAN91C111
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C111 will complete
the current transmission before stopping. When stopping due to an error, this bit is automatically cleared.
8.6
Bank 0 - EPH Status Register
OFFSET
NAME
TYPE
SYMBOL
2
EPH STATUS REGISTER
READ ONLY
EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the
copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used for
real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status.
HIGH
BYTE
LOW
BYTE
Reserved
LINK_
OK
Reserved
CTR
_ROL
EXC
_DEF
LOST
CARR
LATCOL
Reserved
0
-nLNK pin
0
0
0
0
0
0
TX
DEFR
LTX
BRD
SQET
16COL
LTX
MULT
MUL
COL
SNGL
COL
TX_SUC
0
0
0
0
0
0
0
0
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value
of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by
reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/current transmit was deferred for more than 1518 * 2 byte times. Cleared
at the end of every packet sent.
LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of preamble. Valid
only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset. Cleared by setting TXENA bit in TCR.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into
the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting
TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 s of the inter frame gap. Cleared at
the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit
frame.
SQET - Signal Quality Error Test. This bit is set under the following conditions:
1.
2.
3.
LAN91C111 is set to operate in Half Duplex mode (SWFDUP=0);
When STP_SQET=1 and SWFDUP=0, SQET bit will be set upon completion of a transmit operation and no
SQET Pulse has occurred during the IPG (Inter Frame Gap). If a pulse has occurred during the IPG, SQET bit
will not get set.
Once SQET bit is set, setting the TXENA bit in TCR register, or via hardware /software reset can clear this bit.
16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset.
Cleared when TXENA is set high.
LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit
frame.
MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced.
Cleared when TX_SUC is high at the end of the packet being sent.
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LAN91C111
SNGLCOL - Single collision detected for the last transmit frame. Set when a collision is detected. Cleared when TX_SUC is high at the end of the packet being sent.
TX_SUC - Last transmit was successful. Set if transmit completes without a fatal error. This bit is cleared by the start of
a new frame transmission or when TXENA is set high. Fatal errors are:
•
•
•
•
16 collisions (1/2 duplex mode only)
SQET fail and STP_SQET = 1 (1/2 duplex mode only)
Carrier lost and MON_CSN = 1 (1/2 duplex mode only)
Late collision (1/2 duplex mode only)
8.7
Bank 0 - Receive Control Register
HIGH
BYTE
LOW
BYTE
OFFSET
NAME
TYPE
SYMBOL
4
RECEIVE CONTROL
REGISTER
READ/WRITE
RCR
SOFT
RST
FILT
CAR
ABORT_E
NB
Reserved
Reserved
Reserved
STRIP
CRC
RXEN
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
ALMUL
PRMS
RX_
ABORT
0
0
0
0
0
0
0
0
SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit
low. The LAN91C111’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM
is not reloaded after software reset.
FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active. (Does NOT filter RX DV on MII!)
ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP
bit in the TCR is set.
STRIP_CRC - When set, it strips the CRC on received frames. As a result, both the Byte Count and the frame format
do not contain the CRC. When clear, the CRC is stored in memory following the packet. Defaults low.
RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low
on reset.
ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear accepts only the
multicast frames that match the multicast table setting. Defaults low.
PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission unless it is in Full
Duplex!
RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be
received. The bit is cleared by RESET or by the CPU writing it low.
Reserved - Must be 0.
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LAN91C111
8.8
Bank 0 - Counter Register
OFFSET
NAME
TYPE
SYMBOL
6
COUNTER REGISTER
READ ONLY
ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared
when reading the register and do not wrap around beyond 15.
NUMBER OF EXC. DEFFERED TX
HIGH
BYTE
0
0
0
NUMBER OF DEFFERED TX
0
0
MULTIPLE COLLISION COUNT
LOW
BYTE
0
0
0
0
0
0
SINGLE COLLISION COUNT
0
0
0
0
0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS REGISTER
bit description, occurs. Note that the counters can only increment once per enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the counters. For example if a packet is successfully transmitted
after one collision the SINGLE COLLISION COUNT field is incremented by one. If a packet experiences between 2 to
16 collisions, the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences deferral the
NUMBER OF DEFERRED TX field is incremented by one, even if the packet experienced multiple deferrals during its
collision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts
are generated on successful transmissions.
Reading the register in the transmit service routine will be enough to maintain statistics.
8.9
Bank 0 - Memory Information Register
OFFSET
NAME
TYPE
SYMBOL
8
MEMORY INFORMATION
REGISTER
READ ONLY
MIR
HIGH
BYTE
FREE MEMORY AVAILABLE (IN BYTES * 2K * M)
0
0
0
LOW
BYTE
0
0
1
0
0
1
0
0
MEMORY SIZE (IN BYTES *2K * M)
0
0
0
0
0
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The register defaults to the MEMORY SIZE upon POR (Power On Reset) or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size.
All memory related information is represented in 2K * M byte units, where the multiplier M is 1 for LAN91C111.
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LAN91C111
8.10
Bank 0 - Receive/Phy Control Register
HIGH
BYTE
LOW
BYTE
OFFSET
NAME
TYPE
SYMBOL
A
RECEIVE/PHY CONTROL
REGISTER
READ/WRITE
RPCR
Reserved
Reserved
SPEED
DPLX
ANEG
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
LS2A
LS1A
LS0A
LS2B
LS1B
LS0B
Reserved
Reserved
0
0
0
0
0
0
0
0
SPEED – Speed select Input. This bit is valid and selects 10/100 PHY operation only when the ANEG Bit = 0, this bit
overrides the SPEED bit in the PHY Register 0 (Control Register) and determine the speed mode. When this bit is set
(1), the Internal PHY will operate at 100Mbps. When this bit is cleared (0), the Internal PHY will operate at 10Mbps.
When the ANEG bit = 1, this bit is ignored and 10/100 operation is determined by the outcome of the Auto-Negotiation
or this bit is overridden by the SPEED bit in the PHY Register 0 (Control Register) when the ANEG_EN bit in the PHY
Register 0 (Control Register) is clear.
DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only
when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control Register) and determine the
duplex mode. When this bit is set (1), the Internal PHY will operate at full duplex mode. When this bit is cleared (0), the
Internal PHY will operate at half Duplex mode. When the ANEG bit = 1, this bit is ignored and duplex mode is determined
by the outcome of the Auto-Negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register)
when the ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
ANEG – Auto-Negotiation mode select - The PHY is placed in Auto-Negotiation mode when the ANEG bit and the
ANEG_EN bit in PHY Register 0 (Control Register) both are set. When either of these bits is cleared (0), the PHY is
placed in manual mode.
What do you want to
do?
Try to Auto-Negotiate
to ……
Auto-Negotiation
Control Bits
Auto-Negotiation Advertisement Register
Duplex Mode
Control for
the MAC
ANEG
Bit
ANEG_EN
Bit
TX_FDX
Bit
TX_HDX
Bit
10_FDX
Bit
10_HDX
Bit
SWFDUP
Bit
RPCR
(MAC)
Register 0
(PHY)
Register 4
(PHY)
Register 4
(PHY)
Register 4
(PHY)
Register 4
(PHY)
Transmit
Control
Register
(MAC)
100 Full Duplex
1
1
1
1
1
1
1
100 Half Duplex
1
1
0
1
1
1
0
10 Full Duplex
1
1
0
0
1
1
1
10 Half Duplex
1
1
0
0
0
1
0
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LAN91C111
What do you
want to do?
Auto-Negotiation
Control Bits
Try to Manually
Set to ……
Speed and Duplex Mode Control for the PHY
Duplex
Mode
Control for
the MAC
ANEG
Bit
ANEG_EN
Bit
SPEED
Bit
DPLX
Bit
SPEED
Bit
DPLX
Bit
SWFDUP
Bit
RPCR
(MAC
Bank 0
Offset A)
Register 0
(PHY)
RPCR
(MAC
Bank 0
Offset A)
RPCR
(MAC
Bank 0
Offset A)
Register 0
(PHY)
Register 0
(PHY)
Transmit
Control
Register
(MAC)
0
0
1
1
X
X
1
0
1
1
1
X
X
1
1
0
X
X
1
1
1
0
0
1
0
X
X
0
0
1
1
0
X
X
0
1
0
X
X
1
0
0
0
0
0
1
X
X
1
0
1
0
1
X
X
1
1
0
X
X
0
1
1
0
0
0
0
X
X
0
0
1
0
0
X
X
0
1
0
X
X
0
0
0
100 Full Duplex
100 Half Duplex
10 Full Duplex
10 Half Duplex
LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to the LEDA
output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2A
LS1A
LS0A
LED Select Signal – LEDA
0
0
0
nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0
0
1
Reserved
0
1
0
nPLED0 - 10Mbps Link detected
0
1
1
nPLED1 - Full Duplex Mode enabled
1
0
0
nPLED2 - Transmit or Receive packet occurred
1
0
1
nPLED3 - 100Mbps Link detected
1
1
0
nPLED4 - Receive packet occurred
1
1
1
nPLED5 - Transmit packet occurred
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LAN91C111
LS2B, LS1B, LS0B – LED select Signal Enable. These bits define what LED control signals are routed to the LEDB
output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2B
LS1B
LS0B
LED Select Signal – LEDB
0
0
0
nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0
0
1
Reserved
0
1
0
nPLED0 - 10Mbps Link detected
0
1
1
nPLED1 – Full Duplex Mode enabled
1
0
0
nPLED2 – Transmit or Receive packet occurred
1
0
1
nPLED3 - 100Mbps Link detected
1
1
0
nPLED4 - Receive packet occurred
1
1
1
nPLED5 - Transmit packet occurred
Reserved – Must be 0.
8.11
Bank 1 - Configuration Register
OFFSET
NAME
TYPE
SYMBOL
0
CONFIGURATION
REGISTER
READ/WRITE
CR
The Configuration Register holds bits that define the adapter configuration and are not expected to change during runtime. This register is part of the EEPROM saved setup.
HIGH
BYTE
LOW
BYTE
EPH
Power
EN
Reserved
Reserved
NO
WAIT
Reserved
GPCNTRL
EXT PHY
Reserved
1
0
1
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
0
0
1
Reserved
1
1
0
EPH Power EN - Used to selectively power transition the EPH to a low power mode. When this bit is cleared (0), the
Host will place the EPH into a low power mode. The Ethernet MAC will gate the 25Mhz TX and RX clock so that the
Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active
allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible.
However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is
initiated.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if
not ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C111.
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LAN91C111
GPCNTRL - This bit is a general purpose output port. Its inverse value drives pin nCNTRL and it is typically connected
to a SELECT pin of the external PHY device such as a power enable. It can be used to select the signaling mode for
the external PHY or as a general purpose non-volatile configuration pin. Defaults low.
EXT PHY – External PHY Enabled.
This bit, when set (1):
a)
b)
Enables the external MII.
The Internal PHY is disabled and is disconnected (Tri-stated from the internal MII along with any sideband signals
(such as MDINT) going to the MAC Core).
When this bit is cleared (0 - Default):
a)
b)
The internal PHY is enabled.
The external MII pins, including the MII Management interface pins are tri-stated.
Reserved – Reserved bits.
8.12
Bank 1 - Base Address Register
OFFSET
NAME
TYPE
SYMBOL
2
BASE ADDRESS
REGISTER
READ/WRITE
BAR
This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM saved setup
and is not usually modified during run-time.
HIGH
BYTE
A15
A14
A13
A9
A8
A7
A6
A5
0
0
0
1
1
0
0
0
LOW
BYTE
Reserved
0
0
0
Reserved
0
0
0
0
1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the
LAN91C111‘s registers. The 64k I/O space is fully decoded by the LAN91C111 down to a 16 location space, therefore
the unspecified address lines A4, A10, A11 and A12 must be all zeros.
All bits in this register are loaded from the serial EEPROM. The I/O base decode defaults to 300h (namely, the high byte
defaults to 18h).
Reserved – Reserved bits.
Below chart shows the decoding of I/O Base Address 300h:
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
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LAN91C111
8.13
Bank 1 - Individual Address Registers
OFFSET
NAME
TYPE
SYMBOL
4 THROUGH 9
INDIVIDUAL ADDRESS
REGISTERS
READ/WRITE
IAR
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The
registers can be modified by the software driver, but a STORE operation will not modify the EEPROM Individual Address
contents. Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable.
LOW
BYTE
ADDRESS 0
0
0
0
HIGH
BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDRESS 1
0
0
0
LOW
BYTE
0
0
ADDRESS 2
0
0
0
HIGH
BYTE
0
0
ADDRESS 3
0
0
0
LOW
BYTE
0
0
ADDRESS 4
0
0
0
HIGH
BYTE
0
0
ADDRESS 5
0
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0
0
0
0
2011-2016 Microchip Technology Inc.
LAN91C111
8.14
Bank 1 - General Purpose Register
OFFSET
NAME
TYPE
SYMBOL
A
GENERAL PURPOSE
REGISTER
READ/WRITE
GPR
HIGH
BYTE
HIGH DATA BYTE
0
0
0
LOW
BYTE
0
0
0
0
0
0
0
0
LOW DATA BYTE
0
0
0
0
0
This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the
software driver. The storage is word oriented, and the EEPROM word address to be read or written is specified using
the six lowest bits of the Pointer Register.
This register can also be used to sequentially program the Individual Address area of the EEPROM, that is normally
protected from accidental Store operations.
This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is
set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111.
8.15
Bank 1 - Control Register
HIGH
BYTE
LOW BYTE
OFFSET
NAME
TYPE
SYMBOL
C
CONTROL REGISTER
READ/WRITE
CTR
Reserved
RCV_
BAD
Reserved
Reserved
AUTO
RELEASE
Reserved
Reserved
Reserved
0
0
0
1
0
0
1
0
LE
ENABLE
CR
ENABLE
TE
ENABLE
Reserved
Reserved
EEPROM
SELECT
RELOAD
STORE
0
0
0
1
0
0
0
0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and
their memory is released.
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful
(when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet
numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will generate an interrupt
only when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The
packet number that failed, is present in the FIFO PORTS register, and its pages are not released, allowing the CPU to
restart the sequence after corrective action is taken.
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LAN91C111
LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into
the EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused by a LINK_OK transition, will acknowledge the interrupt. LE ENABLE defaults low (disabled).
CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts merged into
the EPH INT bit. Reading the COUNTER register after an EPH INT interrupt caused by a counter rollover, will acknowledge the interrupt. CR ENABLE defaults low (disabled).
TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH
INT bit. An EPH INT interrupt caused by a transmitter error is acknowledged by setting TXENA bit in the TCR register
to 1 or by clearing the TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears
TXENA with TX_SUC staying low as described in the EPHSR register.
EEPROM SELECT - This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE refers to.
When high, the General Purpose Register is the only register read or written. When low, RELOAD reads Configuration,
Base and Individual Address, and STORE writes the Configuration and Base registers.
RELOAD - When set it will read the EEPROM and update relevant registers with its contents. Clears upon completing
the operation.
STORE - When set, stores the contents of all relevant registers in the serial EEPROM. Clears upon completing the operation.
Note:
8.16
When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high. The
remaining 14 bits of this register will be invalid. During this time attempted read/write operations, other than
polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume
accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET
or by software takes less than 750 s.
Bank 2 - MMU Command Register
OFFSET
NAME
TYPE
SYMBOL
0
MMU COMMAND
REGISTER
WRITE ONLY
BUSY BIT
READABLE
MMUCR
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control.
The three command bits determine the command issued as described below:
HIGH
BYTE
LOW
BYTE
COMMAND
Reserved
Reserved
Reserved
Reserved
BUSY
Operation Code
0
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LAN91C111
COMMAND SET:
Operation
Code
Decimal
Value
Command
000
0
NOOP - NO OPERATION
001
1
ALLOCATE MEMORY FOR TX
010
2
RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant
interrupts, resets packet FIFO pointers.
011
3
REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has
completed processing of present receive frame. This command removes the
receive packet number from the RX FIFO and brings the next receive frame (if
any) to the RX area (output of RX FIFO).
100
4
REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all
memory used by the packet presently at the RX FIFO output. The MMU busy
time after issuing REMOVE and RELEASE command depends on the time when
the busy bit is cleared. The time from issuing REMOVE and RELEASE command
on the last receive packet to the time when receive FIFO is empty depends on
RX INT bit turning low. An alternate approach can be checking the read RX FIFO
register.
101
5
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified
in the PACKET NUMBER REGISTER. Should not be used for frames pending
transmission. Typically used to remove transmitted frames, after reading their
completion status. Can be used following 3) to release receive packet memory in
a more flexible way than 4).
110
6
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of
transmitting a packet just loaded into RAM. The packet number to be enqueued
is taken from the PACKET NUMBER REGISTER.
111
7
RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO
holding the packet numbers awaiting transmission and the TX Completion FIFO.
This command provides a mechanism for canceling packet transmissions, and
reordering or bypassing the transmit queue. The RESET TX FIFOs command
should only be used when the transmitter is disabled. Unlike the RESET MMU
command, the RESET TX FIFOs does not release any memory.
Note:
• When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
• MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it.
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DS00002276A-page 53
LAN91C111
COMMAND SEQUENCING
A second allocate command (command 1) should not be issued until the present one has completed. Completion is
determined by reading the FAILED bit of the allocation result register or through the allocation interrupt.
A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The
BUSY bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should
not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low.
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing
a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set
upon the trailing edge of command.
8.17
Bank 2 - Packet Number Register
OFFSET
NAME
TYPE
SYMBOL
2
PACKET NUMBER
REGISTER
READ/WRITE
PNR
Reserved
Reserved
0
0
PACKET NUMBER AT TX AREA
0
0
0
0
0
0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible
through the TX area. Some MMU commands use the number stored in this register as the packet number parameter.
This register is cleared by a RESET or a RESET MMU Command.
OFFSET
NAME
TYPE
SYMBOL
3
ALLOCATION RESULT
REGISTER
READ ONLY
ARR
This register is updated upon an ALLOCATE MEMORY MMU command.
FAILED
Reserved
1
0
ALLOCATED PACKET NUMBER
0
0
0
0
0
0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when
the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the
ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence:
1.
2.
3.
Allocate Command
Poll ALLOC_INT bit until set
Read Allocation Result Register
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only
valid if the FAILED bit is clear.
Note:
For software compatibility with future versions, the value read from the ARR after an allocation request is
intended to be written into the PNR as is, without masking higher bits (provided FAILED = 0).
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LAN91C111
8.18
Bank 2 - FIFO Ports Register
OFFSET
NAME
TYPE
SYMBOL
4
FIFO PORTS REGISTER
READ ONLY
FIFO
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register.
HIGH
BYTE
LOW
BYTE
REMPTY
Reserved
1
0
TEMPTY
Reserved
1
0
RX FIFO PACKET NUMBER
0
0
0
0
0
0
0
0
TX FIFO PACKET NUMBER
0
0
0
0
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the Interrupt Status Register.
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid if REMPTY
is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status
Register.
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if TEMPTY is clear. The
packet is removed when a TX INT acknowledge is issued.
Note:
For software compatibility with future versions, the value read from each FIFO register is intended to be
written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
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LAN91C111
8.19
Bank 2 - Pointer Register
OFFSET
6
HIGH
BYTE
NAME
TYPE
SYMBOL
POINTER REGISTER
READ/WRITE
NOT EMPTY IS
A READ ONLY
BIT
PTR
RCV
AUTO
INCR.
READ
Reserved
NOT
EMPTY
0
0
0
0
0
LOW
BYTE
POINTER HIGH
0
0
0
0
0
0
POINTER LOW
0
0
0
0
0
POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive
areas. It will auto-increment on accesses to the data register when AUTO INCR. is set. The increment is by one for every
byte access, by two for every word access, and by four for every double word access. When RCV is set the address
refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers
to the transmit area and uses the packet number at the Packet Number Register.
READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If the READ
bit is low the operation is a write. Loading a new pointer value, with the READ bit high, generates a pre-fetch into the
Data Register for read purposes.
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last prefetched). This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process
being interrupted. The Pointer Register should not be loaded until the Data Register FIFO is empty. The NOT EMPTY
bit of this register can be read to determine if the FIFO is empty. On reads, if ARDY is not connected to the host, the
Data Register should not be read before 370ns after the pointer was loaded to allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
Reserved - Must be 0
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty
before loading a new pointer value. This is a read only bit.
Note:
If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
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LAN91C111
8.20
Bank 2 - Data Register
OFFSET
NAME
TYPE
SYMBOL
8 THROUGH
BH
DATA REGISTER
READ/WRITE
DATA
DATA HIGH
X
X
X
X
X
X
X
X
X
X
X
X
DATA LOW
X
X
X
X
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C111 regardless
of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is
pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed
through the Data Low or Data High registers. The order to and from the FIFO is preserved. Byte, word and dword
accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate double word move operations regardless of the
actual bus width (16 or 32 bits). The DATA register is accessible at any address in the 8 through Bh range, while the
number of bytes being transferred is determined by A1 and nBE0-nBE3. The FIFOs are 12 bytes each.
8.21
Bank 2 - Interrupt Status Registers
OFFSET
NAME
TYPE
SYMBOL
C
INTERRUPT STATUS
REGISTER
READ ONLY
IST
MDINT
Reserved
EPH INT
RX_OVRN
INT
ALLOC INT
TX EMPTY
INT
TX INT
RCV INT
0
0
0
0
0
1
0
0
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LAN91C111
MDINT
OFFSET
NAME
TYPE
SYMBOL
C
INTERRUPT
ACKNOWLEDGE
REGISTER
WRITE ONLY
IST
Reserved
RX_OVRN
INT
TX EMPTY
INT
TX INT
OFFSET
NAME
TYPE
SYMBOL
D
INTERRUPT MASK
REGISTER
READ/WRITE
MSK
MDINT
MASK
Reserved
EPH INT
MASK
RX_OVRN
INT
MASK
ALLOC INT
MASK
TX EMPTY
INT
MASK
TX INT
MASK
RCV INT
MASK
0
0
0
0
0
0
0
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being
set will cause a hardware interrupt.
MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register) change state.
1.
LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.
These bits automatically latch upon changing state and stay latched until they are read. When they are read, the bits
that caused the interrupt to happen are updated to their current value. The MDINT bit will be cleared by writing the
acknowledge register with MDINT bit set.
Reserved - Must be 0
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This
bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level
drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these
sources can be done via the Control Register. The possible sources are:
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits:
•
•
•
•
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
• LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error Enable)
DS00002276A-page 58
2011-2016 Microchip Technology Inc.
LAN91C111
EPH INT will only be cleared by the following methods:
• Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK transition.
• Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.
• Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above (3.1 to 3.5).
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2) the receiver
aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the RCV DISCRD bit in the RCV
register set. The RX_OVRN INT bit latches the condition for the purpose of being polled or generating an interrupt, and
will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement of the FAILED bit
in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the next allocation request is
processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a sequence of
packets enqueued for transmission. This bit latches the empty condition, and the bit will stay set until it is specifically
cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is
desired, the bit should be first cleared and then read.
The TX_EMPTY MASK bit should only be set after the following steps:
• A packet is enqueued for transmission
• The previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal errors occurs:
•
•
•
•
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is always the logic
complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet number, its TX INT interrupt is
removed by writing the Interrupt Acknowledge Register with the TX INT bit set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO
PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
2011-2016 Microchip Technology Inc.
DS00002276A-page 59
DS00002276A-page 60
EPHSR INTERRUPTS
MERGED INTO EPH INT
TX_SVC
TXENA
TEMASK
CRMASK
CTR-ROL
LEMASK
Fatal TX Error
TX Complete
nWRACK
IntAck7
IntAck4
IntAck2
IntAck1
nRDIST
nQ
D S Q
MDINT
nQ
D S Q
RX_OVRN
ALLOCATION
FAILED
nQ
D S Q
TX FIFO EMPTY
nQ
D S Q
6
5
4
3
2
1
0
DATA BUS
D[15:0]
OE
D[7:0]
Interrupt Status Register
7
RCV FIFO
NOT EMPTY
7
6
5
4
3
2
1
0
nOE
D[15:8]
Interrupt Mask Register
MAIN INTERRUPTS
MDINT
EPH INT
RX_OVRN INT
ALLOC INT
TX EMPTY INT
TX INT
RCV INT
INT
FIGURE 8-2:
Edge Detector on Link Err
SQET
LOST CARR
LATCOL
16COL
LAN91C111
INTERRUPT STRUCTURE
2011-2016 Microchip Technology Inc.
LAN91C111
8.22
Bank 3 - Multicast Table Registers
OFFSET
NAME
TYPE
SYMBOL
0
THROUG
H7
MULTICAST TABLE
READ/WRITE
MT
LOW
BYTE
MULTICAST TABLE 0
0
0
0
HIGH
BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MULTICAST TABLE 1
0
0
0
LOW
BYTE
0
0
MULTICAST TABLE 2
0
0
0
HIGH
BYTE
0
0
MULTICAST TABLE 3
0
0
0
LOW
BYTE
0
0
MULTICAST TABLE 4
0
0
0
HIGH
BYTE
0
0
MULTICAST TABLE 5
0
0
0
LOW
BYTE
0
0
MULTICAST TABLE 6
0
0
0
HIGH
BYTE
0
0
MULTICAST TABLE 7
0
0
0
0
0
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits
of the CRC of the destination addresses. The three msb's determine the register to be used (MT0-MT7), while the other
three determine the bit within the register.
If the appropriate bit in the table is set, the packet is received.
If the ALMUL bit in the RCR register is set, all multicast addresses are received regardless of the multicast table values.
Hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive
status word, the receive routine can reduce the search time significantly. With the proper memory structure, the search
is limited to comparing only the multicast addresses that have the actual hash value in question.
2011-2016 Microchip Technology Inc.
DS00002276A-page 61
LAN91C111
8.23
Bank 3 - Management Interface
HIGH
BYTE
OFFSET
NAME
TYPE
SYMBOL
8
MANAGEMENT
INTERFACE
READ/WRITE
MGMT
Reserved
MSK_
CRS100
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
MDOE
MCLK
MDI
MDO
0
0
MDI Pin
0
LOW
BYTE
Reserved
0
0
1
1
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated.
The purpose of this interface, along with the corresponding pins is to implement MII PHY management in software.
8.24
Bank 3 - Revision Register
OFFSET
NAME
TYPE
SYMBOL
A
REVISION REGISTER
READ ONLY
REV
HIGH
BYTE
0
0
LOW
BYTE
1
1
0
0
CHIP
1
0
1
1
1
0
REV
0
1
0
0
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
DS00002276A-page 62
2011-2016 Microchip Technology Inc.
LAN91C111
8.25
Bank 3 - RCV Register
OFFSET
NAME
TYPE
SYMBOL
C
RCV REGISTER
READ/WRITE
RCV
HIGH
BYTE
LOW
BYTE
Reserved
0
0
0
0
0
0
0
0
RCV
DISCRD
Reserved
Reserved
MBO
MBO
MBO
MBO
MBO
0
0
0
1
1
1
1
1
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being received. When
set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will be set to indicate that the packet
was discarded. Otherwise, the packet will be received normally and bit 0 set (RCVINT) in the interrupt status register.
RCV DISCRD is self clearing.
MBO - Must be 1.
8.26
Bank 7 - External Registers
OFFSET
NAME
TYPE
0
THROUG
H7
EXTERNAL REGISTERS
SYMBOL
nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range occurs.
HIGH
BYTE
EXTERNAL R/W REGISTER
LOW
BYTE
EXTERNAL R/W REGISTER
Cycle
nCSOUT
LAN91C111 Data Bus
AEN=0
A3=0
A4-15 matches I/O BASE
BANK SELECT = 7
Driven low. Transparently latched on nADS
rising edge.
Ignored on writes.
Tri-stated on reads.
BANK SELECT = 4,5,6
High
Ignore cycle.
Otherwise
High
Normal LAN91C111 cycle.
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DS00002276A-page 63
LAN91C111
9.0
PHY MII REGISTERS
Multiple Register Access
Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features.
The multiple register access features can be enabled by setting the multiple register access enables bit in the PHY Ml
serial port Configuration 2 register. When multiple register access is enabled, multiple registers can be accessed on a
single PHY Ml serial port access cycle by setting the register address to 11111 during the first 16 MDC clock cycles.
There is no actual register residing in register address location 11111, so when the register address is then set to 11111,
all eleven registers are accessed on the 176 rising edges of MDC that occur after the first 16 MDC clock cycles of the
PHY Ml serial port access cycle. The registers are accessed in numerical order from 0 to 20. After all 192 MDC clocks
have been completed, all the registers have been read/written, and the serial shift process is halted, data is latched into
the device, and MDIO goes into high impedance state. Another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous 1's) is detected.
Bit Types
Since the serial port is bi-directional, there are many types of bits. Write bits (W) are inputs during a write cycle and are
high impedance during a read cycle. Read bits (R) are outputs during a read cycle and high impedance during a write
cycle. Read/Write bits (RW) are actually write bits, which can be read out during a read cycle. R/WSC bits are R/W bits
that are self-clearing after a set period of time or after a specific event has completed. R/LL bits are read bits that latch
themselves when they go low, and they stay latched low until read. After they are read, they are reset high. R/LH bits
are the same as R/LL bits except that they latch high. R/LT are read bits that latch themselves whenever they make a
transition or change value, and they stay latched until they are read. After R/LT bits are read, they are updated to their
current value. R/LT bits can also be programmed to assert the interrupt function.
Bit Type Definition:
R:
Read Only
R/WSC:
Read/Write Self Clearing
W:
Write Only
R/LH:
Read/Latch high
RW:
Read/Write
R/LL:
Read/Latch low
R/LT:
Read/Latch on Transition
Register Address
Register Name
0
Control
1
Status
2,3
PHY ID
4
Auto-Negotiation Advertisement
5
Auto-Negotiation Remote End Capability
6....15
Reserved
16
Configuration 1
17
Configuration 2
18
Status Output
19
Mask
20
Reserved
2011-2016 Microchip Technology Inc.
DS00002276A-page 65
LAN91C111
PHY Register Description:
TABLE 9-1:
MII SERIAL FRAME STRUCTURE
IDLE
ST[1:0]
READ
WRITE
PHYAD[4:0]
REGAD[4:0]
TA[1:0]
D[15:0]
D[15:0]
Register 0
Control
Register 1
Status
Register 2
PHY ID#1
Register 3
PHY ID#2
Register 4
Auto-Negotiation Advertisement
Register 5
Auto-Negotiation Remote End Capability
Register 16
Configuration 1
Register 17
Configuration 2
Register 18
Status Output
Register 19
Mask
Register 20
Reserved
Symbol
Name
Definition
R/W
IDLE
Idle Pattern
These bits are an idle pattern. Device will not initiate an MI cycle until
it detects at least 32 1's
W
ST1
ST0
Start Bits
When ST[1:0]=01, a MI Serial Port access cycle starts.
W
READ
Read Select
1 = Read Cycle
W
WRITE
Write Select
1 = Write Cycle
W
PHYAD[4:0]
Physical
Device
Address
PHYSICAL ADDRESS
R
REGAD[4:0]
Register
Address
If REGAD[4:0] = 00000-11110, these bits determine the specific
register from which D[15:0] is read/written. If multiple register access
is enabled and REGAD[4:0] = 11111, all registers are read/written in
a single cycle.
W
DS00002276A-page 66
2011-2016 Microchip Technology Inc.
LAN91C111
Symbol
TA1
TA0
Name
Turnaround
Time
Definition
R/W
These bits provide some turnaround time for MDIO
R/W
When READ = 1, TA[1:0] = Z0
When WRITE = 1, TA[1:0] = 10
The turnaround time is a 2 bit time spacing between the Register
Address field and the Data field of a management frame to avoid
contention during a read transaction. For a read transaction, both the
STA and the PHY shall remain in a high impedance state for the first
bit time of the turnaround. The PHY shall drive a zero bit during the
second bit time of the turnaround of a read transaction. During a write
transaction, the STA shall drive a one bit for the first bit time of the
turnaround and a zero bit for the second bit time of the turnaround.
D[15:0]....
Data
These 16 bits contain data to/from one of the eleven registers
selected by register address bits REGAD[4:0].
2011-2016 Microchip Technology Inc.
Any
DS00002276A-page 67
DS00002276A-page 68
PHY ID #2
AutoNegot.
Advertisement
3
4
Status
Output
Mask
Reserved
18
19
20
17 Configuration 2
16 Configuration 1
5
PHY ID #1
2
AutoNegot.
Remote
Capability
Status
Control
0
0
0
MLNKFAIL
MINT
R/W
0
R/W
0
0
Reserved
R/W
Reserved
1
1
1
Reserved
R/W
R/W
R/W
MLOSSSYN
R/LT
R/LT
R
0
LOSSSYNC
1
R/W
Reserved
0
R/W
LNKFAIL
1
R/W
Reserved
0
R/W
XMTPDN
0
R
RF
0
R/W
RF
1
R
OUI21
0
R
OUI5
1
R
CAP_TXH
1
R/W
SPEED
x.13
INT
1
R/W
Reserved
0
R/W
XMTDIS
R
R
0
LNKDIS
ACK
0
0
NP
R
R/W
1
ACK
R
R
1
NP
OUI20
0
OUI19
R
R
0
1
OUI4
R
R
0
OUI3
CAP_TXF
0
R/W
LPBK
CAP_T4
0
R/WSC
RST
x.14
0
R/W
Reserved
1
R/W
MCWRD
0
R/LT
CWRD
1
R/W
Reserved
0
R/W
Reserved
0
R
Reserved
0
R/W
Reserved
1
R
OUI22
0
R
OUI6
1
R
CAP_TF
1
R/W
ANEG_EN
x.12
0
R/W
Reserved
1
R/W
MSSD
0
R/LT
SSD
1
R/W
Reserved
0
R/W
Reserved
0
R
Reserved
0
R/W
Reserved
1
R
OUI23
0
R
OUI7
1
R
CAP_TH
0
R/W
PDN
x.11
0
R/W
Reserved
1
R/W
MESD
0
R/LT
ESD
1
R/W
Reserved
0
R/W
BYPSCR
0
R
Reserved
0
R/W
Reserved
0
R
OUI24
0
R
OUI8
0
0
R/W
Reserved
1
R/W
MRPOL
0
R/LT
RPOL
1
R/W
Reserved
0
R/W
UNSCDS
0
R
T4
0
R/W
T4
0
R
PART5
0
R
OUI9
0
R
Reserved
Reserved
R
0
R/WSC
ANEG_RST
x.9
1 or 0
R/W
MII_DIS
x.10
0
R/W
Reserved
1
1
R/W
Reserved
1
R/W
MSPDDT
MJAB
R/W
1
R/LT
SPDDET
0
R/W
Reserved
0
R/W
CABLE
0
R
TX_HDX
1
R/W
TX_HDX
0
R
PART3
0
R
OUI11
0
R
Reserved
0
R/W
COLTST
x.7
0
R/LT
JAB
1
R/W
Reserved
0
R/W
EQLZR
0
R
TX_FDX
1
R/W
TX_FDX
0
R
PART4
0
R
OUI10
0
R
Reserved
0
R/W
DPLX
x.8
0
R/W
Reserved
1
R/W
MDPLDT
0
R/LT
DPLXDET
0
R/W
Reserved
0
R/W
RLVL0
0
R
10_FDX
1
R/W
10_FDX
1
R
PART2
0
R
OUI12
0
R
CAP_SUPR
0
R/W
Reserved
x.6
1
R/W
Reserved
0
0
R/W
Reserved
0
R/W
Reserved
Reserved
R/W
0
R/LT
Reserved
0
0
R/LT
Reserved
0
R/W
JABDIS
APOLDIS
R/W
0
R/W
TLVL2
0
R
Reserved
0
R/W
Reserved
0
R
PART0
1
R
OUI14
0
R/LH
REM_FLT
0
R/W
Reserved
x.4
1
R/W
TLVL3
0
R
10_HDX
1
R/W
10_HDX
0
R
PART1
0
R
OUI13
0
R
ANEG_ACK
0
R/W
Reserved
x.5
0
R/W
Reserved
0
R/W
Reserved
0
R
Reserved
0
R/W
MREG
0
R/W
TLVL1
0
R
Reserved
0
R/W
Reserved
0
R
REV3
0
R
OUI15
1
R
CAP_ANEG
0
R/W
Reserved
x.3
Reserved
R/W
0
R/W
0
0
R/W
Reserved
0
R
0
R/W
Reserved
0
R/W
Reserved
0
R
Reserved
0
Reserved
R/W
0
Reserved
0
R/W
TRF0
0
R
CSMA
1
R/W
CSMA
0
R
REV0
0
R
OUI18
1
R
EXREG
0
R/W
Reserved
x.0
R/W
Reserved
1
R/W
TRF1
0
R
Reserved
0
R/W
Reserved
0
R
REV1
1
R
OUI17
0
R/LH
JAB
0
R/W
Reserved
x.1
Reserved
0
R/W
Reserved
0
R
Reserved
0
R/W
INTMDIO
0
R/W
TLVL0
0
R
Reserved
0
R/W
Reserved
0
R
REV2
1
R
OUI16
0
R/LL
LINK
0
R/W
Reserved
x.2
FIGURE 9-1:
1
0
x.15
LAN91C111
MII SERIAL PORT REGISTER MAP
2011-2016 Microchip Technology Inc.
LAN91C111
9.1
Register 0. Control Register
RST
LPBK
SPEED
ANEG_EN
PDN
MII_DIS
ANEG_RST
DPLX
RW, SC
RW
RW
RW
RW
RW
RW. SC
RW
0
0
1
1
0
1
0
0
COLST
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
9.1.1
RST - RESET
A ‘1’ written to this bit will initiate a reset of the PHY. The bit is self-clearing, and the PHY will return a ‘1’ on reads to this
bit until the reset is completed. Write transactions to this register may be ignored while the PHY is processing the reset.
All PHY registers will be driven to their default states after a reset. The internal PHY is ready for normal operation 50
mS after the RST bit is set. Software driver requires to wait for 50mS after setting the RST bit to high to access the
internal PHY again.
9.1.2
LPBK - Loopback
Writing a ‘1’ will put the PHY into loopback mode.
9.1.3
SPEED (SPEED SELECTION)
When Auto-Negotiation is disabled this bit can be used to manually select the link speed. Writing a ‘1’ to this bit selects
100 Mbps, a ‘0’ selects 10 Mbps.
When Auto-Negotiation is enabled reading or writing this bit has no meaning/effect.
9.1.4
ANEN_EN - AUTO-NEGOTIATION ENABLE
Auto-Negotiation (ANEG) is on when this bit is ‘1’. In that case the contents of bits Speed and Duplex are ignored and
the ANEG process determines the link configuration.
9.1.5
PDN - POWER DOWN
Setting this bit to ‘1’ will put the PHY in PowerDown mode. In this state the PHY will respond to management transactions.
Note:
9.1.6
This bit must not be set when the device is in external PHY mode.
MII_DIS - MII DISABLE
Setting this bit will set the PHY to an isolated mode in which it will respond to MII management frames over the MII
management interface but will ignore data on the MII data interface. The internal PHY is placed in isolation mode at
power up and reset. It can be removed from isolation mode by clearing the MII_DIS bit in the PHY Control Register. If
necessary, the internal PHY can be enabled by clearing the EXT_PHY bit in the Configuration Register.
9.1.7
ANEG_RST - AUTO-NEGOTIATION RESET
This bit will return 0 if the PHY does not support ANEG or if ANEG is disabled through the ANEG_EN bit. If neither of
the previous is true, setting this bit to ‘1’ resets the ANEG process. This bit is self clearing and the PHY will return a ‘1’
until ANEG is initiated, writing a ‘0’ does not affect the ANEG process.
2011-2016 Microchip Technology Inc.
DS00002276A-page 69
LAN91C111
9.1.8
DPLX - DUPLEX MODE
When Auto-Negotiation is disabled this bit can be used to manually select the link duplex state. Writing a ‘1’ to this bit
selects full duplex while a ‘0’ selects half duplex.
When Auto-Negotiation is enabled reading or writing this bit has no effect.
9.1.9
COLTST - COLLISION TEST
Setting a ‘1’ allows for testing of the MII COL signal. ‘0’ allows normal operation.
Reserved: Reserved, Must be 0 for Proper Operation
9.2
Register 1. Status Register
CAP_T4
CAP_TXF
CAP_TXH
CAP_TF
CAP_TH
Reserved
Reserved.
Reserved
R
R
R
R
R
R
R
R
0
1
1
1
1
0
0
0
Reserved
CAP_SUPR
ANEG_ACK
REM_FLT
CAP_ANEG
LINK
JAB
EXREG
R
R
R
R, LH
R
R, LL
R, LH
R
0
0
0
0
1
0
0
1
9.2.1
CAP_T4 - 100BASE-T4 CAPABLE
‘1’ Indicates 100Base-T4 capable PHY, ‘0’ not capable.
9.2.2
CAP_TXF - 100BASE-TX FULL DUPLEX CAPABLE
‘1’ Indicates 100Base-X full duplex capable PHY, ‘0’ not capable.
9.2.3
CAP_TXH - 100BASE-TX HALF DUPLEX CAPABLE
‘1’ Indicates 100Base-X alf duplex capable PHY, ‘0’ not capable.
9.2.4
CAP_TF - 10BASE-T FULL DUPLEX CAPABLE
‘1’ Indicates 10Mbps full duplex capable PHY, ‘0’ not capable.
9.2.5
CAP_TH - 10BASE-T HALF DUPLEX CAPABLE
‘1’ Indicates 10Mbps half duplex capable PHY, ‘0’ not capable.
Reserved: Reserved, Must be 0 for Proper Operation.
9.2.6
CAP_SUPR - MI PREAMBLE SUPPRESSION CAPABLE
‘1’ indicates the PHY is able to receive management frames even if not preceded by a preamble. ‘0’ when it is not able.
9.2.7
ANEG_ACK - AUTO-NEGOTIATION ACKNOWLEDGMENT
When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are valid. ‘0’ means
ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY returns zero if ANEG is disabled.
9.2.8
REM_FLT- REMOTE FAULT DETECT
‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or resetting the PHY.
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LAN91C111
9.2.9
CAP_ANEG - AUTO-NEGOTIATION CAPABLE
Indicates the ability (‘1’) to perform ANEG or not (‘0’).
9.2.10
LINK - LINK STATUS
A ‘1’ indicates a valid Link and a ‘0’ and invalid Link. The ‘0’ condition is latched until this register is read.
9.2.11
JAB - JABBER DETECT
Jabber condition detected when ‘1’ for 10Mbps. ‘1’ latched until this register is read or the PHY is reset. Always ‘0’ for
100Mbps
9.2.12
EXREG - EXTENDED CAPABILITY REGISTER
‘1’ Indicates extended registers are implemented
9.3
Register 2&3. PHY Identifier Register
These two registers (offsets 2 and 3) provide a 32-bit value unique to the PHY.
REG
Bits
Name
Default Value
R/W
Soft Reset
2
15-0
Company ID
0000000000010110
R
Retains Original Value
3
15-10
Company ID
111110
R
Retains Original Value
3
9-4
Manufacturer's ID
000100
R
Retains Original Value
3
3-0
Manufacturer's Revision #
----
R
Retains Original Value
9.4
Register 4. Auto-Negotiation Advertisement Register
NP
ACK
RF
Reserved
Reserved
Reserved
T4
TX_FDX
RW
R
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
1
TX_HDX
10_FDX
10_HDX
Reserved
Reserved
Reserved
Reserved
CSMA
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
0
0
0
0
1
This register control the values transmitted by the PHY to the remote partner when advertising its abilities.
9.4.1
NP - NEXT PAGE
A ‘1’ indicates the PHY wishes to exchange Next Page information.
9.4.2
ACK - ACKNOWLEDGE
It is used by the Auto-Negotiation function to indicate that a device has successfully received its Link Partner’s Link code
Word.
9.4.3
RF - REMOTE FAULT
When set, an advertisement frame will be sent with the corresponding bit set. This in turn will cause the PHY receiving
it to set the Remote Fault bit in its Status register
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9.4.4
T4 - 100BASE-T4
A '1' indicates the PHY is capable of 100BASE-T4
9.4.5
TX_FDX - 100BASE-TX FULL DUPLEX CAPABLE
A '1' indicates the PHY is capable of 100BASE-TX Full Duplex
9.4.6
TX_HDX - 100BASE-TX HALF DUPLEX CAPABLE
A '1' indicates the PHY is capable of 100BASE-TX Half Duplex
9.4.7
10_FDX - 10BASE-T FULL DUPLEX CAPABLE
A '1' indicates the PHY is capable of 10BASE-T Full Duplex
9.4.8
10_HDX - 10BASE-T HALF DUPLEX CAPABLE
A '1' indicates the PHY is capable of 10BASE-T Half Duplex
The management entity sets the value of this field prior to Auto-Negotiation.
‘1’ in these bit indicates that the mode of operation that corresponds to these will be acceptable to be auto-negotiated
to. Only modes supported by the PHY can be set.
9.4.9
CSMA
A '1' indicates the PHY is capable of 802.3 CSMA Operation.
9.5
Register 5. Auto-Negotiation Remote End Capability Register
NP
ACK
RF
Reserved
Reserved
Reserved
T4
TX_FDX
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
TX_HDX
10_FDX
10_HDX
Reserved
Reserved
Reserved
Reserved
CSMA
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
The bit definitions are analogous to the Auto-Negotiation Advertisement Register.
9.6
Register 16. Configuration 1- Structure and Bit Definition
LNKDIS
XMTDIS
XMTPDN
Reserved
Reserved
BYPSCR
UNSCDS
EQLZR
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
CABLE
RLVL0
TLVL3
TLVL2
TLVL1
TLVL0
TRF1
TRF0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
0
0
1
0
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LAN91C111
LNKDIS:
Link Disable
1 = Receive Link Detect Function
Disabled (Force Link Pass)
XMTDIS:
TP Transmit
1 = TP Transmitter Disabled
XMTPDN:
TP Transmit
1 = TP Transmitter Powered Down
0 = Normal
0 = Normal
Powerdown
0 = Normal
RESERVED:
RESERVED
Reserved, Must be 0 for Proper
Operation
BYPSCR:
Bypass
1 = Bypass Scrambler/Descrambler
Scrambler/Descr-
0 = No Bypass
ambler Select
UNSCDS:
Unscrambled Idle
1 = Disable Auto-Negotiation with
devices that transmit unscrambled
Reception Disable
idle on powerup and various
instances
0 = Enables Auto-Negotiation with
devices that transmit unscrambled
idle on powerup and various
instances
EQLZR:
CABLE
Receive Equalizer
1 = Receive Equalizer Disabled, Set
To 0 Length
Select
0 = Receive Equalizer On (For
100MB Mode Only)
Cable Type Select
1 = STP (150 Ohm)
0 = UTP (100 Ohm)
RLVL0
TLVL0-3
Receive Input
1 = Receive Squelch Levels Reduced
By 4.5 dB R/W
Level Adjust
0 = Normal
Transmit Output
See Table 7-2
Level Adjust
TRF0-1
Transmitter
11 = -0.25nS
Rise/Fall Time
10 = +0.0nS
Adjust
01 = +0.25nS
00 = +0.50nS
9.7
Register 17. Configuration 2 - Structure and Bit Definition
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
Reserved
Reserved
APOLDIS
JABDIS
MREG
INTMDIO
Reserved
Reserved
R
R
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
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LAN91C111
APOLDIS:
Auto Polarity Disable
JABDIS:
1 = Auto Polarity Correction 1 = Auto Polarity Correction
Function Disabled
Function Disabled
Jabber Disable Select
MREG:
Multiple Register Access
Enable
0 = Normal
0 = Normal
1 = Jabber Disabled RW
1 = Jabber Disabled
0 = Enabled
0 = Enabled
1 = Multiple Register
Access Enabled
0 = No Multiple Register
Access
INTMDIO:
Interrupt Scheme Select
1 = Interrupt Signaled With 1 = Interrupt Signaled With
MDIO Pulse During Idle
MDIO Pulse During Idle
0 = Interrupt Not Signaled
On MDIO
Reserved:
9.8
0 = No Multiple Register
Access
0 = Interrupt Not Signaled
On MDIO
Reserved for Factory Use
Register 18. Status Output - Structure and Bit Definition
INT
LNKFAIL
LOSSSYNC
CWRD
SSD
ESD
RPOL
JAB
R
R/LT
R/LT
R/LT
R/LT
R/LT
R/LT
R/LT
0
0
0
0
0
0
0
0
SPDDET
DPLXDET
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/LT
R/LT
R
R
R
R
R
R
1
0
0
0
0
0
0
0
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LAN91C111
INT:
Interrupt Detect
1 = Interrupt Bit(s) Have Changed
Since Last Read Operation.
0 = No Change
LNKFAIL:
Link Fail Detect
1 = Link Not Detected
0 = Normal
LOSSSYNC:
Descrambler Loss of
1 = Descrambler Has Lost
Synchronization
Synchronization Detect
0 = Normal
CWRD:
Codeword Error
1 = Invalid 4B5B Code Detected On
Receive Data
SSD:
Start Of Stream Error
1 = No Start Of Stream Delimiter
Detected on Receive Data
0 = Normal
0 = Normal
ESD:
End Of Stream Error
1 = No End Of Stream Delimiter
Detected on Receive Data
0 = Normal
RPOL:
Reverse Polarity Detect
1 = Reverse Polarity Detected
JAB:
Jabber Detect
1 = Jabber Detected
0 = Normal
SPDDET:
100/10 Speed Detect
1 = Device in 100Mbps Mode
(100BASE-TX)
0 = Device in 10Mbps Mode
(10BASE-T)
DPLXDET:
Duplex Detect
1 = Device In Full Duplex
Reserved:
Reserved
Reserved for Factory Use
0 = Device In Half Duplex
9.9
Register 19. Mask - Structure and Bit Definition
MINT
MLNKFAIL
MLOSSSYN
MCWRD
MSSD
MESD
MRPOL
MJAB
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
MSPDDT
MDPLDT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
1
0
0
0
0
0
0
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LAN91C111
MINT:
Interrupt Mask Interrupt Detect
1 = Mask Interrupt For INT In
Register 18
0 = No Mask
MLNKFAIL:
Interrupt Mask Link Fail Detect
1 = Mask Interrupt For LNKFAIL In
Register 18
MLOSSSYN:
Interrupt Mask Descrambler Loss
1 = Mask Interrupt For LOSSSYNC
In Register 18
of Synchronization Detect
0 = No Mask
Interrupt Mask Codeword Error
1 = Mask Interrupt For CWRD In
Register 18
0 = No Mask
MCWRD:
0 = No Mask
MSSD:
Interrupt Mask Start Of Stream Error 1 = Mask Interrupt For SSD In
Register 18
MESD:
Interrupt Mask End Of Stream Error
0 = No Mask
1 = Mask Interrupt For ESD In
Register 18
0 = No Mask
MRPOL:
Interrupt Mask Reverse Polarity
Detect
1 = Mask Interrupt For RPOL In
Register 18
0 = No Mask
MJAB:
Interrupt Mask Jabber Detect
1 = Mask Interrupt For JAB In
Register 18
MSPDDT:
Interrupt Mask 100/10 Speed Detect
1 = Mask Interrupt For SPDDET In
Register 18
MDPLDT:
Interrupt Mask Duplex Detect
1 = Mask Interrupt For DPLXDET In
Register 18
Reserved:
Reserved
Reserved for Factory Use
0 = No Mask
0 = No Mask
0 = No Mask
9.10
Register 20. Reserved - Structure and Bit Definition
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
0
1
0
0
0
0
0
Reserved: Reserved for Factory Use.
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LAN91C111
10.0
SOFTWARE DRIVER AND HARDWARE SEQUENCE FLOW
10.1
Software Driver and Hardware Sequence Flow for Power Management
This section describes the sequence of events and the interaction between the Host Driver and the Ethernet controller
to perform power management. The Ethernet controller has the ability to reduce its power consumption when the Device
is not required to receive or transmit Ethernet Packets.
Power Management is obtained by disabling the EPH clocks, including the Clocks derived from the Internal PHY block
to reduce internal switching, this reducing current consumption.
The Host interface however, will still be accessible. As discussed in Table 10-1 and Table 10-2, the tables describe the
interaction between the EPH and Host driver allowing the Device to transition from low power state to normal functionality and vice versa.
TABLE 10-1:
TYPICAL FLOW OF EVENTS FOR PLACING DEVICE IN LOW POWER MODE
S/W Driver
Controller Function
1
Disable Transmitter – Clear the TXENA bit of the
Transmit Control Register
Ethernet MAC finishes packet currently being
transmitted.
2
Remove and release all TX completion packet
numbers on the TX completion FIFO.
3
Disable Receiver – Clear the RXEN bit of the
Receive Control Register.
The receiver completes receiving the current frame, if
any, and then goes idle. Ethernet MAC will no longer
receive any packets.
4
Process all Received packets and Issue a Remove
and Release command for each respective RX
packet buffer.
RX and TX completion FIFO’s are now Empty and
all MMU packet numbers are now free.
5
Disable Interrupt sources – Clear the Interrupt
Status Register
Save Device Context – Save all Specific Register
Values set by the driver.
6
Set PDN bit in PHY MI Register 0 to 1
Note:
This bit must not be set when the device is
in external PHY mode.
7
8
The internal PHY entered in powerdown mode, the
TP outputs are in high impedance state.
Write to the “EPH Power EN” Bit located in the
configuration register, Bank 1 Offset 0.
9
10
Ethernet MAC gates the RX Clock, TX clock derived
from the Internal PHY. The EPH Clock is also
disabled.
The Ethernet MAC is now in low power mode. The
Host may access all Runtime IO mapped registers.
All IO registers are still accessible. However, the
Host should not read or write to the registers with
the exception of:
Configuration Register
Control Register
Bank Register
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TABLE 10-2:
FLOW OF EVENTS FOR RESTORING DEVICE IN NORMAL POWER MODE
S/W Driver
1
Write and set (1) the “EPH Power EN” Bit, located in
the configuration register, Bank 1 Offset 0.
2
3
Controller Function
Ethernet MAC Enables the RX Clock, TX clock
derived from the Internal PHY. The EPH Clock is
also enabled.
Write the PDN bit in PHY MI Register 0 to 0
Note:
Only performed when device is in internal
PHY mode.
4
The PHY is then set in isolation mode (MII_DIS bit
is set). Need to clear this MII_DIS bit; and, need to
wait for 500 ms for the PHY to restore normal.
Internal PHY entered normal operation mode
5
Issue MMU Reset Command
6
Restore Device Register Level Context.
7
Enable Transmitter – Set the TXENA bit of the
Transmit Control Register
Ethernet MAC can now transmit Ethernet Packets.
8
Enable Receiver – Set (1) the RXEN bit of the
Receive Control Register.
Ethernet MAC is now able to receive Packets.
9
10.2
Ethernet MAC is now restored for normal operation.
Typical Flow of Events for Transmit (Auto Release = 0)
S/W Driver
1
ISSUE ALLOCATE MEMORY FOR TX - N BYTES the MMU attempts to allocate N bytes of RAM.
2
WAIT FOR SUCCESSFUL COMPLETION CODE Poll until the ALLOC INT bit is set or enable its mask
bit and wait for the interrupt. The TX packet number
is now at the Allocation Result Register.
3
LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write the
Pointer Register, then use a block move operation
from the upper layer transmit queue into the Data
Register.
4
ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO"
- This command writes the number present in the
Packet Number Register into the TX FIFO. The
transmission is now enqueued. No further CPU
intervention is needed until a transmit interrupt is
generated.
5
DS00002276A-page 78
MAC Side
The enqueued packet will be transferred to the MAC
block as a function of TXENA (nTCR) bit and of the
deferral process (1/2 duplex mode only) state.
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LAN91C111
S/W Driver
6
7
10.3
MAC Side
Upon transmit completion the first word in memory is
written with the status word. The packet number is
moved from the TX FIFO into the TX completion
FIFO. Interrupt is generated by the TX completion
FIFO being not empty.
If a TX failure occurs on any packets, TX INT is
generated and TXENA is cleared, transmission
sequence stops. The packet number of the failure
packet is presented at the TX FIFO PORTS Register.
SERVICE INTERRUPT - Read Interrupt Status
Register. If it is a transmit interrupt, read the TX FIFO
Packet Number from the FIFO Ports Register. Write
the packet number into the Packet Number Register.
The corresponding status word is now readable from
memory. If status word shows successful
transmission, issue RELEASE packet number
command to free up the memory used by this packet.
Remove packet number from completion FIFO by
writing TX INT Acknowledge Register.
Option 1) Release the packet.
Option 2) Check the transmit status in the EPH
STATUS Register, write the packet number of the
current packet to the Packet Number Register, reenable TXENA, then go to step 4 to start the TX
sequence again.
Typical Flow of Events for Transmit (Auto Release = 1)
S/W Driver
1
ISSUE ALLOCATE MEMORY FOR TX - N BYTES the MMU attempts to allocate N bytes of RAM.
2
WAIT FOR SUCCESSFUL COMPLETION CODE Poll until the ALLOC INT bit is set or enable its mask
bit and wait for the interrupt. The TX packet number
is now at the Allocation Result Register.
3
LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write the
Pointer Register, then use a block move operation
from the upper layer transmit queue into the Data
Register.
4
ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO"
- This command writes the number present in the
Packet Number Register into the TX FIFO. The
transmission is now enqueued. No further CPU
intervention is needed until a transmit interrupt is
generated.
MAC Side
5
The enqueued packet will be transferred to the MAC
block as a function of TXENA (nTCR) bit and of the
deferral process (1/2 duplex mode only) state.
6
Transmit pages are released by transmit completion.
7
The MAC generates a TXEMPTY interrupt upon a
completion of a sequence of enqueued packets.
If a TX failure occurs on any packets, TX INT is
generated and TXENA is cleared, transmission
sequence stops. The packet number of the failure
packet is presented at the TX FIFO PORTS Register.
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S/W Driver
8
10.4
SERVICE INTERRUPT – Read Interrupt Status
Register, exit the interrupt service routine.
Option 1) Release the packet.
Option 2) Check the transmit status in the EPH
STATUS Register, write the packet number of the
current packet to the Packet Number Register, reenable TXENA, then go to step 4 to start the TX
sequence again.
Typical Flow of Event For Receive
S/W Driver
1
MAC Side
MAC Side
ENABLE RECEPTION - By setting the RXEN bit.
2
A packet is received with matching address. Memory
is requested from MMU. A packet number is assigned
to it. Additional memory is requested if more pages
are needed.
3
The internal DMA logic generates sequential
addresses and writes the receive words into memory.
The MMU does the sequential to physical address
translation. If overrun, packet is dropped and memory
is released.
4
When the end of packet is detected, the status word
is placed at the beginning of the receive packet in
memory. Byte count is placed at the second word. If
the CRC checks correctly the packet number is
written into the RX FIFO. The RX FIFO, being not
empty, causes RCV INT (interrupt) to be set. The
RCV_BAD bit of the Bank 1 Control Register controls
whether or not to generate interrupts when bad CRC
packets are received.
5
SERVICE INTERRUPT - Read the Interrupt Status
Register and determine if RCV INT is set. The next
receive packet is at receive area. (Its packet number
can be read from the FIFO Ports Register). The
software driver can process the packet by accessing
the RX area, and can move it out to system memory
if desired. When processing is complete the CPU
issues the REMOVE AND RELEASE FROM TOP OF
RX command to have the MMU free up the used
memory and packet number.
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LAN91C111
FIGURE 10-1:
INTERRUPT SERVICE ROUTINE
ISR
Save Bank Select & Address
Ptr Registers
Mask SMC91C111
Interrupts
Read Interrupt Register
No
Yes
RX INTR?
Yes
TX INTR?
Call TX INTR or TXEMPTY
INTR
No
Call RXINTR
Get Next TX
Yes
ALLOC INTR?
Packet
Available for
Transmission?
No
Yes
Write Allocated Pkt # into
Packet Number Reg.
No
Call ALLOCATE
Write Ad Ptr Reg. & Copy Data
& Source Address
Enqueue Packet
EPH INTR?
Yes
No
Set "Ready for Packet" Flag
Call EPH INTR
Return Buffers to Upper Layer
MDINT?
Disable Allocation Interrupt
Mask
Yes
Restore Address Pointer &
Bank Select Registers
Call MDINT
Unmask SMC91C111
Interrupts
Exit ISR
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LAN91C111
FIGURE 10-2:
RX INTR
RX INTR
Write Ad. Ptr. Reg. & Read
Word 0 from RAM
Yes
Destination
Multicast?
No
Read Words 2, 3, 4 from RAM
for Address Filtering
No
No
Address
Filtering Pass?
Status Word
OK?
Yes
Yes
Do Receive Lookahead
Get Copy Specs from Upper
Layer
No
Okay to
Copy?
Yes
Copy Data Per Upper Layer
Specs
Issue "Remove and Release"
Command
Return to ISR
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LAN91C111
FIGURE 10-3:
TX INTR
TX Interrupt With AUTO_RELEASE = FALSE
1. Save the Packet Number Register
Saved_PNR = Read Byte (Bank 2, Offset 2)
2. Read the EPH Status Register
Temp = Read (Bank 0, Offset 2)
3. Acknowledge TX Interrupt
Write Byte (0x02, (Bank 2, Offset C));
4. Check for Status of Transmission
If ( Temp AND 0x0001)
{
//If Successful Transmission
Step 4.1.1: Issue MMU Release (Release Specific Packet)
Write (0x00A0, (Bank2, Offset 0));
Step 4.1.2: Return from the routine
}
else
{
//Transmission has FAILED
// Now we can either release or re-enqueue the packet
Step 4.2.1: Get the packet to release/re-enqueue, stored in FIFO
Temp = Read (Bank 2, Offset 4)
Temp = Temp & 0x003F
Step 4.2.2: Write to the PNR
Write (Temp, (Bank2, Offset 2))
Step 4.2.3
// Option 1: Release the packet
Write (0x00A0, (Bank2, Offset 0));
//Option 2: Re-Enqueue the packet
Write (0x00C0, (Bank2, Offset 0));
Step 4.2.4: Re-Enable Transmission
Temp = Read(Bank0, Offset 0);
Temp = Temp2 OR 0x0001
Write (Temp2, (Bank 0, Offset 0));
Step 4.2.5: Return from the routine
}
5. Restore the Packet Number Register
Write Byte (Saved_PNR, (Bank 2, Offset 2))
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LAN91C111
FIGURE 10-4:
TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED)
TXEMPTY INTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 0
&
TXINT = 0
(Waiting for Completion)
TXEMPTY = X
&
TXINT = 1
(Transmission Failed)
TXEMPTY = 1
&
TXINT = 0
(Everything went through
successfully)
Read Pkt. # Register & Save
Write Address Pointer
Register
Read Status Word from RAM
Update Statistics
Issue "Release" Command
Update Variables
Acknowledge TXINTR
Re-Enable TXENA
Restore Packet Number
Return to ISR
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LAN91C111
FIGURE 10-5:
DRIVE SEND AND ALLOCATE ROUTINES
D R IV E R S E N D
A L L O C ATE
C h o o se B a n k S e le ct
R e g iste r 2
Issu e "A llo ca te M e m o ry"
C o m m a n d to M M U
C a ll A L L O C ATE
R e a d In te rru p t S ta tu s R e g iste r
E xit D rive r S e n d
Ye s
A llo ca tio n
Pa sse d ?
No
R e a d A llo ca tio n R e su lt
R e g iste r
W rite A llo ca te d Pa cke t in to
Pa cke t # R e g iste r
S to re D a ta B u ffe r Po in te r
W rite A d d re ss Po in te r R e g iste r
C le a r "R e a d y fo r Pa cke t" Fla g
C o py Pa rt o f TX D a ta Pa cke t
in to R A M
E n a ble A llo ca tio n In te rru p t
W rite S o u rce A d d re ss in to
P ro p e r L o ca tio n
C o py R e m a in in g T X D a ta
Pa cke t in to R A M
E n q u e u e Pa cke t
S e t "R e a d y fo r Pa cke t" Fla g
R e tu rn B u ffe rs to U p p e r L aye r
Re tu rn
10.5
Memory Partitioning
Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit and receive
resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the
CPU to prevent the receive process from starving the transmit memory allocation.
Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the MAC for receive.
The CPU can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive
process is going to demand. Furthermore, the receive process requests will be dependent on network traffic, in particular
on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer
software flow control.
2011-2016 Microchip Technology Inc.
DS00002276A-page 85
LAN91C111
10.6
Interrupt Generation
The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the
transmit and receive queue management between the software driver and the controller. For that purpose there is no
register reading necessary before the next element in the queue (namely transmit or receive packet) can be handled by
the controller. The transmit and receive results are placed in memory.
The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and receive interrupts
are enabled. This allows the interrupt service routine to process many receive packets without exiting, or one at a time
if the ISR just returns after processing and removing one.
There are two types of transmit interrupt strategies:
1.
2.
One interrupt per packet.
One interrupt per sequence of packets.
The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used.
TX INT bit - Set whenever the TX completion FIFO is not empty.
TX EMPTY INT bit - Set whenever the TX FIFO is empty.
AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their memory is
released automatically.
1.
2.
One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the completion
result in memory and process the interrupt one packet at a time. Depending on the completion code the driver
will take different actions. Note that the transmit process is working in parallel and other transmissions might be
taking place. The LAN91C111 is virtually queuing the packet numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the
TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of
packet numbers being transmitted. The numbers are queued by the LAN91C111 and provided back to the CPU
as their transmission completes.
One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY
INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and
therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when
AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.
Note:
The pointer register is shared by any process accessing the LAN91C111 memory. In order to allow processes to be interruptible, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1.
2.
3.
Transmit loading (sometimes interrupt driven)
Receive unloading (interrupt driven)
Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required
from interrupt service routines.
DS00002276A-page 86
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 10-6:
INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
INTERRUPT
'NOT EMPTY'
STATUS REGISTER
RCV
INT
TWO
OPTIONS
PACKET NUMBER
RX FIFO
PACKET NUMBER
REGISTER
TX EMPTY
INT
TX
INT
RX
FIFO
TX
FIFO
ALLOC
INT
'EMPTY'
RX PACKET
NUMBER
TX COMPLETION
FIFO
'NOT EMPTY'
TX DONE
PACKET NUMBER
CSMA ADDRESS
CPU ADDRESS
CSMA/CD
LOGICAL
ADDRESS
PACKET #
MMU
M.S. BIT ONLY
PACK # OUT
PHYSICAL ADDRESS
RAM
2011-2016 Microchip Technology Inc.
DS00002276A-page 87
LAN91C111
11.0
BOARD SETUP INFORMATION
The following parameters are obtained from the EEPROM as board setup information:
• ETHERNET INDIVIDUAL ADDRESS
• I/O BASE ADDRESS
• MII INTERFACE
All the above mentioned values are read from the EEPROM upon hardware reset. Except for the INDIVIDUAL
ADDRESS, the value of the IOS switches determines the offset within the EEPROM for these parameters, in such a
way that many identical boards can be plugged into the same system by just changing the IOS jumpers.
In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can
be written using the LAN91C111. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE) that can always be used regardless of the EEPROM based value being programmed. This value will
be used if all IOS pins are left open or pulled high.
The EEPROM is arranged as a 64 x 16 array. The specific target device is the 9346 1024-bit Serial EEPROM. All
EEPROM accesses are done in words. All EEPROM addresses in the spec are specified as word addresses.
Register
EEPROM Word Address
Configuration Register
IOS Value * 4
Base Register
(IOS Value * 4) + 1
INDIVIDUAL ADDRESS 20-22 hex
If IOS2-IOS0 = 7, only the INDIVIDUAL ADDRESS is read from the EEPROM. Currently assigned values are assumed
for the other registers. These values are default if the EEPROM read operation follows hardware reset.
The EEPROM SELECT bit is used to determine the type of EEPROM operation: a) normal or b) general purpose register.
1.
NORMAL EEPROM OPERATION - EEPROM SELECT bit = 0
On EEPROM read operations (after reset or after setting RELOAD high) the CONFIGURATION REGISTER and
BASE REGISTER are updated with the EEPROM values at locations defined by the IOS2-0 pins. The INDIVIDUAL ADDRESS registers are updated with the values stored in the INDIVIDUAL ADDRESS area of the
EEPROM.
On EEPROM write operations (after setting the STORE bit) the values of the CONFIGURATION REGISTER and
BASE REGISTER are written in the EEPROM locations defined by the IOS2-IOS0 pins.
The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and STORE) are
used to control the EEPROM. Their values are not stored nor loaded from the EEPROM.
2.
GENERAL PURPOSE REGISTER - EEPROM SELECT bit = 1
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the POINTER
REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER.
On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE REGISTER
is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits.
RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until
read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD
bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the
EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
DS00002276A-page 88
2011-2016 Microchip Technology Inc.
LAN91C111
Note:
If no EEPROM is connected to the LAN91C111, for example for some embedded applications, the ENEEP
pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value.
FIGURE 11-1:
64 X 16 SERIAL EEPROM MAP
16 BITS
IOS2-0
WORD ADDRESS
000
0h
CONFIGURATION REG.
1h
BASE REG.
4h
CONFIGURATION REG.
5h
BASE REG.
8h
CONFIGURATION REG.
9h
BASE REG.
Ch
CONFIGURATION REG.
Dh
BASE REG.
10h
CONFIGURATION REG.
11h
BASE REG.
14h
CONFIGURATION REG.
15h
BASE REG.
18h
CONFIGURATION REG.
19h
BASE REG.
20h
IA0-1
21h
IA2-3
22h
IA4-5
001
010
011
100
101
110
XXX
2011-2016 Microchip Technology Inc.
DS00002276A-page 89
LAN91C111
12.0
APPLICATION CONSIDERATIONS
The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines, system level
implications and sample configurations for the most relevant bus types. All applications are based on buffered architectures with a private SRAM bus.
12.1
Fast Ethernet Slave Adapter
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
1.
2.
3.
LAN91C111 chip
Serial EEPROM (93C46)
Some bus specific glue logic
Target systems:
1.
2.
3.
VL Local Bus 32 bit systems
High-end ISA or non-burst EISA machines
EISA 32 bit slave
12.2
VL Local Bus 32 Bit Systems
On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as a 32 bit peripheral in terms of the
bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to
the DATA REGISTER could use byte, word, or dword instructions.
TABLE 12-1:
VL LOCAL BUS SIGNAL CONNECTIONS
VL Bus Signal
LAN91C111 Signal
A2-A15
A2-A15
Address bus used for I/O space and register decoding, latched by nADS
rising edge, and transparent on nADS low time.
M/nIO
AEN
Qualifies valid I/O decoding - enabled access when low. This signal is
latched by nADS rising edge and transparent on nADS low time.
W/nR
W/nR
Direction of access. Sampled by the LAN91C111 on first rising clock that
has nCYCLE active. High on writes, low on reads.
nRDYRTN
nRDYRTN
Ready return. Direct connection to VL bus.
nLRDY
nSRDY and some
logic
nSRDY has the appropriate functionality and timing to create the VL
nLRDY except that nLRDY behaves like an open drain output most of
the time.
LCLK
LCLK
Local Bus Clock. Rising edges used for synchronous bus interface
transactions.
nRESET
RESET
Connected via inverter to the LAN91C111.
nBE0 nBE1
nBE2 nBE3
nBE0 nBE1 nBE2
nBE3
Byte enables. Latched transparently by nADS rising edge.
nADS
nADS, nCYCLE
Address Strobe is connected directly to the VL bus. nCYCLE is created
typically by using nADS delayed by one LCLK.
IRQn
INTR0
Typically uses the interrupt lines on the ISA edge connector of VL bus
DS00002276A-page 90
Notes
2011-2016 Microchip Technology Inc.
LAN91C111
TABLE 12-1:
VL LOCAL BUS SIGNAL CONNECTIONS (CONTINUED)
VL Bus Signal
LAN91C111 Signal
D0-D31
D0-D31
Notes
32 bit data bus. The bus byte(s) used to access the device are a function
of nBE0-nBE3:
nBE0
0
0
nBE1
nBE2
nBE3
0
0
Double word access
0
0
1
1
Low word access
1
1
0
0
High word access
0
1
1
1
Byte 0 access
1
0
1
1
Byte 1 access
1
1
0
1
Byte 2 access
1
1
1
0
Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that nBE2 and
nBE3 override the value of A1, which is tied low in this application.
nLDEV
nLDEV
nLDEV is a totem pole output. nLDEV is active on valid decodes of A15A4 and AEN=0.
Unused Pins
VCC
nRD nWR
GND
A1 nVLBUS
OPEN
nDATCS
2011-2016 Microchip Technology Inc.
DS00002276A-page 91
LAN91C111
FIGURE 12-1:
LAN91C111 ON VL BUS
VLBUS
W/nR
W/nR
A2-A15
A2-A15
LCLK
LCLK
M/nIO
AEN
nRESET
RESET
IRQn
LAN91C111
INTR0
D0-D31
D0-D31
nRDYRTN
nRDYRTN
nBE0-nBE3
nBE0-nBE3
nADS
nADS
Delay 1 LCLK
nCYCLE
nSRDY
nLRDY
nLDEV
O.C.
simulated
O.C.
nLDEV
12.3
High-End ISA or Non-Burst EISA Machines
On ISA machines, the LAN91C111 is accessed as a 16 bit peripheral. The signal connections are listed in the following
table:
TABLE 12-2:
ISA Bus
Signal
HIGH-END ISA OR NON-BURST EISA MACHINES SIGNAL CONNECTORS
LAN91C111 Signal
Notes
A1-A15
A1-A15
Address bus used for I/O space and register decoding.
AEN
AEN
Qualifies valid I/O decoding - enabled access when low.
nIORD
nRD
I/O Read strobe - asynchronous read accesses. Address is valid before
leading edge.
DS00002276A-page 92
2011-2016 Microchip Technology Inc.
LAN91C111
TABLE 12-2:
ISA Bus
Signal
HIGH-END ISA OR NON-BURST EISA MACHINES SIGNAL CONNECTORS
(CONTINUED)
LAN91C111 Signal
Notes
nIOWR
nWR
I/O Write strobe - asynchronous write access. Address is valid before
leading edge. Data is latched on trailing edge.
IOCHRDY
ARDY
This signal is negated on leading nRD, nWR if necessary. It is then
asserted on CLK rising edge after the access condition is satisfied.
RESET
RESET
A0
nBE0
nSBHE
nBE1
IRQn
INTR0
D0-D15
D0-D15
16 bit data bus. The bus byte(s) used to access the device are a function
of nBE0 and nBE1:
nBE0
nBE1
D0-D7
D8-D15
0
0
Lower
Upper
0
1
Lower
Not used
1
0
Not used
Upper
Not used = tri-state on reads, ignored on writes
nIOCS16
nLDEV buffered
nLDEV is a totem pole output. Must be buffered using an open collector
driver. nLDEV is active on valid decodes of A15-A4 and AEN=0.
UNUSED PINS
GND
nADS
VCC
nBE2, nBE3,
nCYCLE, W/nR,
nRDYRTN, LCLK
2011-2016 Microchip Technology Inc.
No upper word access.
DS00002276A-page 93
LAN91C111
FIGURE 12-2:
LAN91C111 ON ISA BUS
ISA BUS
A1-A15, AEN
A1-A15, AEN
RESET
RESET
nBE2, nBE3
VCC
D0-D15
D0-D15
LAN91C111
INTR0
IRQ
nIORD
nRD
nIOWR
nWR
A0
nBE0
nBE1
nSBHE
nLDEV
nIOCS16
12.4
O.C.
EISA 32 Bit Slave
On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an
I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is
externally derived from nCMD edges. Given that the access will be at least 1.5 to 2 clocks (more than 180ns at least)
there is no need to negate EXRDY, simplifying the EISA interface implementation. As a DMA Slave, the LAN91C111
accepts burst transfers and is able to sustain the peak rate of one doubleword every BCLK. Doubleword alignment is
assumed for DMA transfers. The LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycle solicits
wait states.
TABLE 12-3:
EISA 32 BIT SLAVE SIGNAL CONNECTIONS
EISA Bus Signal
LAN91C111 Signal
Notes
LA2-LA15
A2-A15
Address bus used for I/O space and register decoding, latched by
nADS (nSTART) trailing edge.
M/nIO
AEN
AEN
Qualifies valid I/O decoding - enabled access when low. These
signals are externally ORed. Internally the AEN pin is latched by
nADS rising edge and transparent while nADS is low.
Latched W-R
combined with
nCMD
nRD
I/O Read strobe - asynchronous read accesses. Address is valid
before its leading edge. Must not be active during DMA bursts if
DMA is supported.
DS00002276A-page 94
2011-2016 Microchip Technology Inc.
LAN91C111
TABLE 12-3:
EISA 32 BIT SLAVE SIGNAL CONNECTIONS (CONTINUED)
EISA Bus Signal
LAN91C111 Signal
Notes
Latched W-R
combined with
nCMD
nWR
I/O Write strobe - asynchronous write access. Address is valid
before leading edge . Data latched on trailing edge. Must not be
active during DMA bursts if DMA is supported.
nSTART
nADS
Address strobe is connected to EISA nSTART.
RESDRV
RESET
nBE0 nBE1 nBE2
nBE3
nBE0 n BE1 nBE2
nBE3
Byte enables. Latched on nADS rising edge.
IRQn
INTR0
Interrupts used as active high edge triggered
D0-D31
D0-D31
32 bit data bus. The bus byte(s) used to access the device are a
function of nBE0-nBE3:
nBE0
nBE1
nBE2
nBE3
0
0
0
0
Double word access
0
0
1
1
Low word access
1
1
0
0
High word access
0
1
1
1
Byte 0 access
1
0
1
1
Byte 1 access
1
1
0
1
Byte 2 access
1
1
1
0
Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that nBE2 and
nBE3 override the value of A1, which is tied low in this application.
Other combinations of nBE are not supported by the LAN91C111.
Software drivers are not anticipated to generate them.
nEX32
nNOWS
(optional additional
logic)
nLDEV
nLDEV is a totem pole output. nLDEV is active on valid decodes of
LAN91C111 pins A15-A4, and AEN=0. nNOWS is similar to nLDEV
except that it should go inactive on nSTART rising. nNOWS can be
used to request compressed cycles (1.5 BCLK long, nRD/nWR will
be 1/2 BCLK wide).
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
BCLK
LCLK
EISA Bus Clock. Data transfer clock for DMA bursts.
nDAK
nDATACS
DMA Acknowledge. Active during Slave DMA cycles. Used by the
LAN91C111 as nDATACS direct access to data path.
nIORC
W/nR
Indicates the direction and timing of the DMA cycles. High during
LAN91C111 writes, low during LAN91C111 reads.
nIOWC
nCYCLE
Indicates slave DMA writes.
nEXRDY
nRDYRTN
EISA bus signal indicating whether a slave DMA cycle will take place
on the next BCLK rising edge, or should be postponed. nRDYRTN
is used as an input in the slave DMA mode to bring in EXRDY.
UNUSED PINS
VCC
nVLBUS
GND
A1
2011-2016 Microchip Technology Inc.
DS00002276A-page 95
LAN91C111
FIGURE 12-3:
LAN91C111 ON EISA BUS
EISA BUS
LA2- LA15
A2-A15
RESET
RESET
AEN
AEN
M/nIO
D0-D31
D0-D31
INTR0
IRQn
LAN91C111
nBE[0:3]
nCMD
nWR
nBE[0:3]
nRD
LATCH
+
gates
nWR
LCLK
BCLK
nSTART
nADS
nLDEV
nEX32
DS00002276A-page 96
O.C.
2011-2016 Microchip Technology Inc.
LAN91C111
13.0
OPERATIONAL DESCRIPTION
13.1
Maximum Ratings*
Operating Temperature Range
0C to +70C for LAN91C111 (-40C to 85C
for LAN91C111I)
Storage Temperature Range
-55C to + 150C
Lead Temperature Range (soldering, 10 seconds)
+325C
Positive Voltage on any pin, with respect to Ground
VCC + 0.3V
Negative Voltage on any pin, with respect to Ground
-0.3V
Maximum VCC
+5V
*Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification
is not implied.
Note:
When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line
may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
.
13.2
DC Electrical Characteristics
(VCC = +3.3.0 V ± 10%)
Parameter
Symbol
MIN
TYP
MAX
Unit
Comments
0.8
V
TTL Levels
I Type Input Buffer
Low Input Level
VILI
High Input Level
VIHI
2.0
V
IS Type Input Buffer
Low Input Level
VILIS
High Input Level
VIHIS
Schmitt Trigger Hysteresis
VHYS
0.8
2.2
250
V
Schmitt Trigger
V
Schmitt Trigger
mV
ICLK Input Buffer
Low Input Level
VILCK
0.8
V
High Input Level
VIHCK
2.2
IIL
-10
+10
µA
VIN = 0
IIH
-10
+10
µA
VIN = VCC
V
Input Leakage
(All I and IS buffers except
pins with
pullups/pulldowns)
Low Input Leakage
High Input Leakage
2011-2016 Microchip Technology Inc.
DS00002276A-page 97
LAN91C111
Parameter
Symbol
MIN
TYP
IIL
-110
-45
MAX
Unit
Comments
A
VIN = 0
+110
A
VIN = VCC
0.4
V
IOL = 6 mA
V
IOH = -4 mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 6 mA
V
IOH = -4 mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 20 mA
V
IOH = -10 mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 35 mA
V
IOH = -15 mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 35 mA
V
IOH = -15 mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 35 mA
V
IOH = -15 mA
+10
µA
VIN = 0 to VCC
0.4
V
IOL = 4 mA
V
na
µA
VIN = 0 to VCC
IP Type Buffers
Input Current
ID Type Buffers
Input Current
IIH
+45
O4 Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
I/O4 Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
O12 Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
O16 Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
O24 Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
I/O24 Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
I/OD Type Buffer
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
IOL
-10
DS00002276A-page 98
+10
2011-2016 Microchip Technology Inc.
LAN91C111
Parameter
Symbol
MIN
TYP
MAX
Unit
Comments
ICC
100
140
mA
Dynamic Current
(Assuming internal PHY is
used)
IPDN
15
38
mA
Internal PHY in
Powerdown mode
14
36
mA
Internal MAC+PHY in
Powerdown mode
Supply Current Active
Powerdown Supply Current
CAPACITANCE TA = 25C; fc = 1MHz; VCC = 3.3V
Limits
Parameter
Symbol
Clock Input Capacitance
MIN
TYP
MAX
Unit
Test Condition
CIN
20
pF
All pins except pin
under test tied to
AC ground
Input Capacitance
CIN
10
pF
Output Capacitance
COUT
20
pF
CAPACITIVE LOAD ON OUTPUTS
ARDY, D0-D31 (non VLBUS)
45 pF
D0-D31 in VLBUS
45 pF
All other outputs
45 pF
2011-2016 Microchip Technology Inc.
DS00002276A-page 99
LAN91C111
13.3
Twisted Pair Characteristics, Transmit
VDD = 3.3v +/- 5%
RBIAS = 11K +/- 1%, no load
Limits
SYM
Parameter
Unit
MIN
Tov
TP Differential Output
Voltage
TYP
Conditions
MAX
0.950
1.000
1.050
Vpk
100 Mbps, UTP Mode,
100 Ohm Load
1.165
1.225
1.285
Vpk
100 Mbps, STP Mode,
150 Ohm Load
2.2
2.5
2.8
Vpk
10 Mbps, UTP Mode,
100 Ohm Load
2.694
3.062
3.429
Vpk
10 Mbps, STP Mode,
150 Ohm Load
Tovs
TP Differential Output
Voltage Symmetry
98
102
%
100 Mbps, Ratio of Positive And
Negative Amplitude Peaks on TPO±
TORF
TP Differential Output
Rise And Fall Time
3.0
5.0
nS
100 Mbps
TRFADJ [1:0] = 10
TORFS
TP Differential Output
Rise And Fall Time
Symmetry
+/-0.5
ToDC
TP Differential Output
Duty Cycle Distortion
+/0.25
nS
100 Mbps, Output Data=0101... NRZ
Pattern Unscrambled, Measure At
50% Points
ToJ
TP Differential Output
Jitter
+/-1.4
nS
100 Mbps, Output Data=scrambled /H/
Too
TP Differential Output
Overshoot
5.0
%
100 Mbps
TOVT
TP Differential Output
Voltage Template
See Figure 7-4
10 Mbps
TSOI
TP Differential Output
SOI Voltage
Template
See Figure 7-6
10 Mbps
TLPT
TP Differential Output
Link Pulse Voltage
Template
See Figure 7-7
10 Mbps, NLP and FLP
TOIV
TP Differential Output
Idle Voltage
TOIA
TP Output Current
DS00002276A-page 100
nS
100 Mbps, Difference Between Rise
and Fall Times on TPO±
+/-50
mV
10 Mbps.
38
40
42
mA pk
100 Mbps, UTP with TLVL[3:0]=1000
31.06
32.66
34.26
mA pk
100 Mbps, STP with TLVL[3:0]=1000
88
100
112
mA pk
10 Mbps, UTP with TLVL[3:0]=1000
71.86
81.64
91.44
mA pk
10 Mbps, STP with TLVL[3:0]=1000
2011-2016 Microchip Technology Inc.
LAN91C111
Limits
SYM
Parameter
Unit
MIN
TOIR
TP Output Current
Adjustment Range
TYP
0.80
1.2
VDD = 3.3V, Adjustable with RBIAS,
relative to TOIA with RBIAS=11K
0.86
1.16
VDD = 3.3V, Adjustable with LVL[3:0]
Relative to Value at TLVL[3:0]=1000
TORA
TP Output Current
TLVL Step Accuracy
TOR
TP Output
Resistance
10K
Ohm
TOC
TP Output
Capacitance
15
pF
13.4
Conditions
MAX
+/-50
%
Relative to Ideal Values in Table 3.
Table 3 Values Relative to Output with
TLVL[3:0]=1000.
Twisted Pair Characteristics, Receive
Unless otherwise noted, all test conditions are as follows:
• Vcc = 3.3V +/-5%
• RBIAS = 11K +/- 1%, no load
• 62.5/10 Mhz Square Wave on TP inputs in 100/10 Mbps
Limits
SYM
Parameter
Unit
MIN
RST
RUT
TP Input Squelch
Threshold
TP Input Unsquelch
Threshold
TYP
Conditions
MAX
166
500
mV pk
100 Mbps, RLVL=0
310
540
mV pk
10 Mbps, RLVL=0
60
200
mV pk
100 Mbps, RLVL=1
186
324
mV pk
10 Mbps, RLVL=1
100
300
mV pk
100 Mbps, RLVL=0
186
324
mV pk
10 Mbps, RLVL=0
20
90
mV pk
100 Mbps, RLVL=1
112
194
mV pk
10 Mbps, RLVL=1
TP Input Open Circuit
Voltage
VDD- 2.4
± 0.2
Volt
Voltage on Either TPI+ or TPI- with
Respect to GND.
RCMR
TP Input Common
Mode Voltage Range
ROCV
± 0.25
Volt
Voltage on TPI± with Respect to
GND.
RDR
TP Input Differential
Voltage Range
RIR
TP Input Resistance
RIC
TP Input Capacitance
2011-2016 Microchip Technology Inc.
VDD
5K
Volt
Ohm
10
pF
DS00002276A-page 101
LAN91C111
14.0
TIMING DIAGRAMS
FIGURE 14-1:
ASYNCHRONOUS CYCLE - NADS=0
t2
Address, AEN, nBE[3:0]
Valid
nADS
t3
t4
Read Data
Valid
t6
t1
t5
nRD, nWR
t5A
Write Data
Valid
Parameter
MIN
TYP
MAX
Units
t1
A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active
2
ns
t2
A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming
nADS Tied Low)
5
ns
t3
nRD Low to Valid Data
t4
nRD High to Data Invalid
2
t5
Data Setup to nWR Inactive
10
ns
t5A
Data Hold After nWR Inactive
5
ns
t6
nRD Strobe Width
15
ns
DS00002276A-page 102
15
ns
15
ns
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-2:
ASYNCHRONOUS CYCLE - USING NADS
0ns
50ns
100ns
Asynchronous Cycle -- Using nADS
150ns
200ns
250
t9
Addr,AEN,nBE[1:0]
valid
t8
nADS
t3
t4
Read Data
valid
t6
t1
t5
nRD,nWR
t5A
Write Data
valid
Parameter
MIN
TYP
MAX
t1
A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active
t3
nRD Low to Valid Data
t4
nRD High to Data Invalid
2
t5
Data Setup to nWR Inactive
10
ns
t5A
Data Hold After nWR Inactive
5
ns
t6
nRD Strobe Width
15
ns
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
8
ns
t9
A1-A15, AEN, nBE[3:0] Hold after nADS Rising
5
ns
2011-2016 Microchip Technology Inc.
2
Units
ns
15
ns
15
ns
DS00002276A-page 103
LAN91C111
FIGURE 14-3:
ASYNCHRONOUS CYCLE - NADS=0
0ns
50ns
100ns
150ns
200ns
Asynchronous Cycle - nADS=0
250n
t2
nDATACS
t3A
t4
Read Data
valid
t6A
t1A
t5
nRD,nWR
t5A
Write Data
D0~D31 valid
Parameter
MIN
TYP
MAX
Units
t1A
nDATACS Setup to nRD, nWR Active
2
ns
t2
nDATACS Hold After nRD, nWR Inactive (Assuming nADS Tied
Low)
5
ns
t3A
nRD Low to Valid Data
t4
nRD High to Data Invalid
2
t5
Data Setup to nWR Inactive
10
ns
t5A
Data Hold After nWR Inactive
5
ns
t6A
nRD Strobe Width
30
ns
DS00002276A-page 104
30
ns
15
ns
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-4:
ASYNCHRONOUS READY
Address, AEN, nBE[3:0]
Valid Address
Valid Address
nRD, nWR
t26
t26A
t13
ARDY
Data
Valid
Parameter
t26
ARDY Low Pulse Width
t26A
Control Active to ARDY Low
t13
Valid Data to ARDY High
2011-2016 Microchip Technology Inc.
Valid Data
MIN
100
10
TYP
MAX
Units
150
ns
10
ns
ns
DS00002276A-page 105
LAN91C111
FIGURE 14-5:
BURST WRITE CYCLES - NVLBUS=1
t17
t12
t22
t18
t14
t18
Clock
t12A
nDATACS
t17A
W/nR
t22A
nCYCLE
t20
Write Data
a
t20
t20
b
c
t15
nRDYRTN
Parameter
MIN
TYP
MAX
Units
t12
nDATACS Setup to LCLK Rising
20
ns
t12A
nDATACS Hold After LCLK Rising
0
ns
t14
nRDYRTN Setup to LCLK Falling
10
ns
t15
nRDYRTN Hold after LCLK Falling
10
ns
t17
W/nR Setup to LCLK Falling
15
ns
t17A
W/nR Hold After LCLK Falling
3
ns
t18
Data Setup to LCLK Rising (Write)
15
ns
t20
Data Hold from LCLK Rising (Write)
4
ns
t22
nCYCLE Setup to LCLK Rising
5
ns
t22A
nCYCLE Hold After LCLK Rising
10
ns
DS00002276A-page 106
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-6:
BURST READ CYCLES - NVLBUS=1
t17
t12
t14
Clock
t12A
nDATACS
t17A
W/nR
nCYCLE
t19
Read Data
t19
a
b
c
t15
nRDYRTN
Parameter
MIN
TYP
MAX
Units
t12
nDATACS Setup to LCLK Rising
20
ns
t12A
nDATACS Hold after LCLK Rising
0
ns
t14
nRDYRTN Setup to LCLK Falling
10
ns
t15
nRDYRTN Hold after LCLK Falling
10
ns
t17
W/nR Setup to LCLK Falling
15
ns
t17A
W/nR Hold After LCLK Falling
3
ns
t19
Data Delay from LCLK Rising (Read)
5
2011-2016 Microchip Technology Inc.
15
ns
DS00002276A-page 107
LAN91C111
FIGURE 14-7:
ADDRESS LATCHING FOR ALL MODES
t8
nADS
t9
Address, AEN, nBE[3:0]
Valid
t25
nLDEV
Parameter
MIN
TYP
MAX
Units
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
8
ns
t9
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
5
ns
t25
A4-A15, AEN to nLDEV Delay
DS00002276A-page 108
30
ns
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-8:
SYNCHRONOUS WRITE CYCLE - NVLBUS=0
t18
t10
t20
Clock
t9
Address, AEN, nBE[3:0]
Valid
t8
nADS
t17A
t16
W/nR
t11
nCYCLE
Write Data
Valid
t21
t21
nSRDY
Parameter
MIN
TYP
MAX
Units
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
8
ns
t9
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
5
ns
t10
nCYCLE Setup to LCLK Rising
5
ns
t11
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
3
ns
t16
W/nR Setup to nCYCLE Active
0
ns
t17A
W/nR Hold after LCLK Rising with nSRDY Active
3
ns
t18
Data Setup to LCLK Rising (Write)
15
ns
t20
Data Hold from LCLK Rising (Write)
4
ns
t21
nSRDY Delay from LCLK Rising
2011-2016 Microchip Technology Inc.
7
ns
DS00002276A-page 109
LAN91C111
FIGURE 14-9:
SYNCHRONOUS READ CYCLE - NVLBUS=0
t23
t20
t24
t10
Clock
t9
Address, AEN, nBE[3:0]
Valid
t8
nADS
t16
W/nR
t11
nCYCLE
Read Data
Valid
t21
t21
nSRDY
nRDYRTN
Parameter
MIN
TYP
MAX
Units
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
8
ns
t9
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
5
ns
t10
nCYCLE Setup to LCLK Rising
5
ns
t11
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
3
ns
t16
W/nR Setup to nCYCLE Active
0
ns
t20
Data Hold from LCLK Rising (Read)
4
ns
t21
nSRDY Delay from LCLK Rising
t23
nRDYRTN Setup to LCLK Rising
3
ns
t24
nRDYRTN Hold after LCLK Rising
3
ns
DS00002276A-page 110
7
ns
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-10:
MII TIMING
t27
TXD0-TXD3
t27
TXEN100
t28
RXD0-RXD3
t28
t28
RX25
t29
RX_DV
t29
RX_ER
Parameter
MIN
TYP
MAX
15
Units
t27
TXD0-TXD3, TXEN100 Delay from TX25 Rising
0
ns
t28
RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising
10
ns
t29
RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising
10
ns
AC TEST TIMING CONDITIONS
Unless otherwise noted, all test conditions are as follows:
1.
2.
3.
4.
5.
VDD = 3.3V +/-5%
RBIAS = 11K +/- 1%, no load
Measurement Points:
TPO±, TPI±: 0.0 V During Data, ±0.3V at start/end of packet
All other inputs and outputs: 1.4 Volts
TABLE 14-1:
TRANSMIT TIMING CHARACTERISTICS
Limit
SYM
Parameter
Unit
MIN
t30
Transmit Propagation Delay
2011-2016 Microchip Technology Inc.
60
TYP
Condition
MAX
140
nS
100Mbps
600
nS
10Mbps
DS00002276A-page 111
LAN91C111
TABLE 14-1:
TRANSMIT TIMING CHARACTERISTICS
Limit
SYM
Parameter
Unit
MIN
t31
TYP
Transmit Output Jitter
±0.7
nS pk-pk
100Mbps
±5.5
nS pk-pk
10Mbps
nS
10Mbps
10Mbps
t32
Transmit SOI Pulse Width to
0.3V
t33
Transmit SOI Pulse Width to
40mV
4500
nS
t34
LEDn Delay Time
25
mS
t35
LEDn Pulse Width
105
mS
FIGURE 14-11:
250
80
Condition
MAX
TRANSMIT TIMING
100Mbps
t
t 30
TPO±
FXO±
IDLE
IDLE
31
DATA
/J/K/
/T/R/
IDLE
10Mbps
t 33
t31
t30
TPO±
PREAMBLE
t32
PREAMBLE
DATA
t34
DATA
SOI
t35
LEDn
TXEN Bit is Set
TABLE 14-2:
RECEIVE TIMING CHARACTERISTICS
Limit
SYM
Parameter
Unit
MIN
t36
t37
Receive Input Jitter
SOI Pulse Minimum Width
Required for Idle Detection
DS00002276A-page 112
125
TYP
Condition
MAX
±3.0
nS pk-pk
100Mbps
±13.5
nS pk-pk
10Mbps
200
nS
10Mbps
Measure TPI± from last zero
cross to 0.3V point
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-12:
RECEIVE TIMING, END OF PACKET - 10 MBPS
t 36
TPI±
DATA
DATA DATA DATA DATA
SOI
t 37
TABLE 14-3:
COLLISION AND JAM TIMING CHARACTERISTICS
Limit
SYM
Parameter
Unit
MIN
t38
t39
t40
t41
Rcv Packet Start to COL
Assert Time
Xmt Packet Start to COL
Assert Time
Start of Packet to Transmit
JAM Packet Start During JAM
Xmt Packet Start to COL
Assert Time
2011-2016 Microchip Technology Inc.
TYP
Condition
MAX
200
nS
100Mbps
700
nS
10Mbps
300
nS
10Mbps
200
nS
100Mbps
700
nS
10Mbps
500
nS
100Mbps
1500
nS
10Mbps
200
nS
100Mbps
700
nS
10Mbps
DS00002276A-page 113
LAN91C111
FIGURE 14-13:
COLLISION TIMING, RECEIVE
MII 100 Mbps
TPO±
I
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
TPI±
I
I
I
I
J
K
DATA
DATA
DATA
DATA
t
DATA
T
DATA
DATA
DATA
R
I
I
38
Collision Observed
by Physical Layer
t 34
t 35
LEDn
MII 10 Mbps
TPO±
TPI±
t
38
Collision Observed
by Physical Layer
t 34
t 35
LEDn
DS00002276A-page 114
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-14:
COLLISION TIMING, TRANSMIT
MII 100 Mbps
TPI±
I
TPO±
I
DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
I
I
I
J
K
t
DATA DATA DATA DATA
T
R
I
I
39
Collision Observed
by Physical Layer
t 34
t 35
LEDn
MII 10 Mbps
TPI±
TPO±
t
39
Collision Observed
by Physical Layer
t 34
t 35
LEDn
2011-2016 Microchip Technology Inc.
DS00002276A-page 115
LAN91C111
FIGURE 14-15:
JAM TIMING
MII 100 Mbps
TPO±
I
I
J
K
t
TPO±
I
I
I
DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
40
I
I
J
K
JAM
JAM
JAM
JAM
T
R
I
I
I
t 41
Collision Observed
by Physical Layer
MII 10 Mbps
TPI±
t
TPO±
DS00002276A-page 116
40
JAM
JAM
JAM
JAM
2011-2016 Microchip Technology Inc.
LAN91C111
TABLE 14-4:
LINK PULSE TIMING CHARACTERISTICS
Limit
SYM
Unit
Condition
Parameter
MIN
TYP
MAX
t42
NLP Transmit Link Pulse Width
See Figure 7-8
t43
NLP Transmit Link Pulse Period
8
t44
NLP Receive Link Pulse Width Required
For Detection
50
t45
NLP Receive Link Pulse Minimum Period
Required For Detection
6
7
mS
link_test_min
t46
NLP Receive Link Pulse Maximum
Period Required For Detection
50
150
mS
link_test_max
t47
NLP Receive Link Pulse Required To
Exit Link Fail State
3
3
Link
Pulses
lc_max
t48
FLP Transmit Link Pulse Width
100
150
nS
t49
FLP Transmit Clock Pulse to Data Pulse
Period
55.5
62.5
69.5
S
t50
FLP Transmit Clock Pulse to Clock Pulse
Period
111
125
139
S
t51
FLP Transmit Link Pulse Burst Period
8
22
mS
t52
FLP Receive Link Pulse Width Required
For Detection
50
t53
FLP Receive Link Pulse Minimum Period
Required For Clock Pulse Detection
5
25
S
flp_test_min_timer
t54
FLP Receive Link Pulse Maximum
Period Required For Clock Pulse
Detection
165
185
S
flp_test_max_timer
t55
FLP Receive Link Pulse Minimum Period
Required For Data Pulse Detection
15
47
S
data_detect_min_timer
t56
FLP Receive Link Pulse Maximum
Period Required For Data Pulse
Detection
78
100
S
data_detect_max_timer
t57
FLP Receive Link Pulse Burst Minimum
Period Required For Detection
5
7
mS
nlp_test_min_timer
t58
FLP Receive Link Pulse Burst Maximum
Period Required For Detection
50
150
mS
nlp_test_max_timer
t59
FLP Receive Link Pulses Bursts
Required To Detect Auto-Negotiation
Capability
3
3
Link
Pulses
2011-2016 Microchip Technology Inc.
nS
24
mS
nS
3
interval_timer
transmit_link_burst_time
r
nS
3
DS00002276A-page 117
LAN91C111
FIGURE 14-16:
LINK PULSE TIMING
TPO±
t 42
t 43
a.) Transmit NLP
TPI±
t 44
t 45
t 47
t 46
LEDn
b.) Receive NLP
DS00002276A-page 118
2011-2016 Microchip Technology Inc.
LAN91C111
FIGURE 14-17:
FLP LINK PULSE TIMING
CLK
DATA
CLK
DATA
CLK
CLK
DATA
TPO±
t 48
t 49
t 50
t 51
a.) Transmit FLP and Transmit FLP Burst
CLK
DATA
CLK
DATA
TPI±
31.25
t 52
62.5
93.75
125
156.25
t 53
t 54
t 55
t 56
b.) Receive FLP
TPI±
t 59
t 57
t 58
LEDn
c.) Receive FLP Burst
2011-2016 Microchip Technology Inc.
DS00002276A-page 119
LAN91C111
PACKAGE OUTLINES
128-PIN TQFP PACKAGE OUTLINE, 14X14X1.0 BODY, 0.4MM PITCH
Note: For the most current package drawings,
see the Microchip Packaging Specification at
FIGURE 15-1:
DS00002276A-page 118
http://www.microchip.com/packaging
15.0
2011-2016 Microchip Technology Inc.
LAN91C111
128-PIN QFP PACKAGE OUTLINE, 14X20X2.7MM BODY, 3.9 MM FOOTPRINT
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 15-2:
2011-2016 Microchip Technology Inc.
DS00002276A-page 119
LAN91C111
APPENDIX A:
TABLE A-1:
DATA SHEET REVISION HISTORY
REVISION HISTORY
REVISION LEVEL & DATE
DS00002276A (09-01-16)
Rev. 1.92 (06-27-11)
Rev. 1.91 (06-01-09)
DS00002276A-page 120
SECTION/FIGURE/ENTRY
CORRECTION
Replaces previous SMSC version Rev. 1.92 (06-27-11)
Section 7.7.17, "PHY
Powerdown," on page 36
Added note stating that the PDN bit must not be
set when the device is in external PHY mode.
Table 10-1, “Typical Flow Of
Events For Placing Device
In Low Power Mode,” on
page 77
Added note to step 6 stating that the bit (PDN)
must not be set when the device is in external PHY
mode.
Table 10-2, “Flow Of Events
For Restoring Device In
Normal Power Mode,” on
page 78
Added note to step 3 stating that the step is only
performed when the device is in internal PHY
mode.
Table 9.1, “Register 0.
Control Register,” on
page 69
Added note to PDN bit definition stating that the bit
must not be set when the device is in external PHY
mode.
The following ordering information has been removed: “LAN91C111-NC,
LAN91C111i-NC (Industrial Temperature) for 128 pin QFP packages”,
“LAN91C111-NE, LAN91C111i-NE (Industrial Temperature) for 128-pin TQFP
packages” as these has been discontinued.
All
Updated document references to Rev. C.
Section 13.1, "Maximum
Ratings*," on page 97
Fixed commercial temp range to state “0C to
+70C for LAN91C111”
Cover
Added bullet: “Commercial Temperature Range
from 0C to 70C (LAN91C111)”
Section 8.24, "Bank 3 Revision Register," on
page 62
Changed REV default from “0001” to “0010”
Table 14-3, “Asynchronous
Cycle - nADS=0,” on
page 104
Changed T1A time in table under figure from 10nS
min to 2nS min.
Section 10.4, "Typical Flow
of Event For Receive," on
page 80
In step 4, changed last sentence from “If CRC is
incorrect the packet memory is released and no
interrupt will occur.”, to “The RCV_BAD bit of the
Bank 1 Control Register controls whether or not to
generate interrupts when bad CRC packets are
received.”
Section 7.7.14, "Receive
Polarity Correction," on
page 35
Added note at end of 10 Mbps subsection stating
“The first 3 received packets must be discarded
after the correction of a reverse polarity condition.”
2011-2016 Microchip Technology Inc.
LAN91C111
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
2011-2016 Microchip Technology Inc.
DS00002276A-page 121
LAN91C111
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
[X]
-
XXX
-
[X](1)
Examples:
a)
Device
Temperature
Range
Package
Tape and Reel
Option
b)
Device:
LAN91C111, LAN91C111i
c)
Temperature
Range:
Blank
i
Package:
NS
NU
Tape and Reel
Option:
Blank
TR
DS00002276A-page 122
=
0C to
= -40C to
=
=
+70C
+85C
(Commercial)
(Industrial)
128-pin QFP
128-pin TQFP
= Standard packaging (tray)
= Tape and Reel(1)
d)
LAN91C111-NS
Commercial temperature,
128-pin QFP, Tray
LAN91C111i-NS
Industrial temperature,
128-pin QFP, Tape & Reel
LAN91C111-NU
Commercial temperature,
128-pin TQFP, Tray
LAN91C111i-NU
Industrial temperature,
128-pin TQFP, Tape & Reel
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
2011-2016 Microchip Technology Inc.
LAN91C111
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch,
Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2011-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522409144
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2011-2016 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00002276A-page 123
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 86-592-2388138
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tel: 86-756-3210040
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Tel: 45-4450-2828
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Tel: 91-80-3090-4444
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Tel: 33-1-69-53-63-20
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Tel: 91-11-4160-8631
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Tel: 49-2129-3766400
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Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
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Tel: 512-257-3370
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Tel: 86-28-8665-5511
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Tel: 774-760-0087
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Tel: 86-23-8980-9588
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Tel: 630-285-0071
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Tel: 216-447-0464
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Tel: 248-848-4000
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Tel: 281-894-5983
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Tel: 317-773-8323
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Tel: 949-462-9523
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New York, NY
Tel: 631-435-6000
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Tel: 408-735-9110
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
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Tel: 63-2-634-9065
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Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
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Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
06/23/16
2011-2016 Microchip Technology Inc.
DS00002276A-page 124