LAN9218i
High-Performance Single-Chip 10/100 Ethernet Controller
with HP Auto-MDIX and Industrial Temperature Support
Highlights
• Optimized for the highest performance applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 32-bit and 16-bit embedded CPU’s
• Integrated PHY with HP Auto-MDIX support
• Supports audio & video streaming over Ethernet:
multiple high-definition (HD) MPEG2 streams
Target Applications
•
•
•
•
•
•
•
•
Video distribution systems, multi-room PVR
Cable, satellite, and IP set-top boxes
Digital video recorders and DVD recorder/players
Digital TV
Digital media clients/servers and home gateways
Video-over IP solutions, IP PBX & video phones
Wireless routers & access points
High-end audio distribution systems
Key Benefits
• Non-PCI Ethernet controller for the highest performance applications
- Highest performing non-PCI Ethernet
controller
- 32-bit interface with fast bus cycle times
- Burst-mode read support
• Eliminates dropped packets
- Internal buffer memory can store over 200
packets
- Automatic PAUSE and back-pressure flow
control
• Minimizes CPU overhead
- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off
timer
• Reduces system cost and increases design flexibility
• SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
• Reduced Power Modes
- Numerous power management modes
- Wake on LAN
- Magic packet wakeup
- Wakeup indicator event signal
- Link Status Change
2006-2017 Microchip Technology Inc.
• Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u standards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and
checking
- Automatic payload padding and pad removal
- Loop-back modes
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY
- Supports HP Auto-MDIX
- Auto-negotiation
- Supports energy-detect power down
• Host bus interface
- Simple, SRAM-like interface
- 32 or 16-bit data bus
- 16Kbyte FIFO with flexible TX/RX allocation
- One configurable host interrupt
• Miscellaneous features
- Low-profile 100-pin TQFP, RoHS Compliant
package
- Integrated 1.8V regulator
- General Purpose Timer
- Optional EEPROM interface
- Support for 3 status LEDs multiplexed with
Programmable GPIO signals
• Single 3.3V Power Supply with 5V tolerant
I/O
• -40C to +85C Industrial Temperature Support
DS00002410A-page 1
LAN9218i
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00002410A-page 2
2006-2017 Microchip Technology Inc.
LAN9218i
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Description and Configuration .................................................................................................................................................. 8
3.0 Functional Description .................................................................................................................................................................. 15
4.0 Internal Ethernet PHY ................................................................................................................................................................... 47
5.0 Register Description ...................................................................................................................................................................... 56
6.0 Timing Diagrams ......................................................................................................................................................................... 102
7.0 Operational Characteristics ......................................................................................................................................................... 113
8.0 Package Information ................................................................................................................................................................... 120
Appendix A: Data Sheet Revision History ......................................................................................................................................... 121
2006-2017 Microchip Technology Inc.
DS00002410A-page 3
LAN9218i
1.0
GENERAL DESCRIPTION
The LAN9218i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9218i has been specifically architected to provide the highest performance possible for any given architecture. The LAN9218i is fully IEEE 802.3
10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.
The LAN9218i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The
simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit microprocessors and microcontrollers . The LAN9218i includes large transmit and receive data FIFOs with a high-speed host
bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9218i memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity.
Applications
The LAN9218i is well suited for many high performance embedded applications, including:
•
•
•
•
•
•
•
High-end cable, satellite and IP set-top boxes
Video distribution systems
Multi-room PVR (Personal Video Recorder)
Digital video recorders
High-definition televisions
Digital media clients/servers
Home gateways
The LAN9218i also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over
200 received packets. If the receive FIFO gets too full, the LAN9218i can automatically generate flow control packets to
the remote node, or assert back-pressure on the remote node by generating network collisions.
The LAN9218i supports numerous power management and wakeup features. The LAN9218i can be placed in a reduced
power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”,
“Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet
wakeup events. The device can be removed from the low power state via a host processor command.
DS00002410A-page 4
2006-2017 Microchip Technology Inc.
LAN9218i
1.1
Block Diagram
.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
System Memory
System
Peripherals
Magnetics
Microprocessor/
Microcontroller
System Bus
Ethernet
LAN9218i
LEDS/
GPIO
25MHz
XTAL
EEPROM
(Optional)
The Microchip LAN9218i integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9218i Ethernet MAC/PHY controller is designed
and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9218i in a typical embedded environment.
The LAN9218i is a general purpose, platform independent, Ethernet controller. The LAN9218i consists of four major
functional blocks. The four blocks are:
•
•
•
•
10/100 Ethernet PHY
10/100 Ethernet MAC
RX/TX FIFOs
Host Bus Interface (HBI)
2006-2017 Microchip Technology Inc.
DS00002410A-page 5
LAN9218i
1.2
Compatibility with First-generation LAN9118 Family Devices
The LAN9218i is driver-, register-, and footprint-compatible with previous generation LAN9118 Family devices. Drivers
written for these products will work with the LAN9218i. However, in order to support HP Auto-MDIX, other components
such as the magnetics and the passive components around the magnetics need to change, and supporting these
changes does require a minor PCB change. A reference design for the LAN9218i will be available on Microchip’s website.
1.3
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".
FIGURE 1-2:
INTERNAL BLOCK DIAGRAM
25MHz
+3.3V
PME
Wakup Indicator
Power
Management
Host Bus Interface
(HBI)
SRAM I/F
3.3V to 1.8V
Core Regulator
TX Status FIFO
RX Status FIFO
IRQ
Interrupt
Controller
GP
Timer
1.4
EEPROM
(Optional )
3.3V to 1.8V
PLL Regulator
EEPRO
M
Controller
2kB to 14kB
Configurable TX FIFO
PIO
Controller
FIFO _SEL
PLL
+3.3V
2kB to 14kB
Configurable RX FIFO
10/100
Ethernet
MAC
10/100
Ethernet
PHY
LAN
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
10/100 Ethernet PHY
The LAN9218i integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
1.5
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full
duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Payload data as well as transmit and receive status is passed on these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the
host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port
internal to the LAN9218i. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through
the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The
differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive pack-
DS00002410A-page 6
2006-2017 Microchip Technology Inc.
LAN9218i
ets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and
RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first
to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and
will queue an entire frame before beginning transmission.
1.6
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing
or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition,
the RX and TX FIFOs are configurable in size, allowing increased flexibility.
1.7
Interrupt Controller
The LAN9218i supports a single programmable interrupt. The programmable nature of this interrupt allows the user the
ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the
interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain
output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval
is provided.
1.8
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9218i. It is
accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and
open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with programmable polarity.
1.9
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9218i. The serial EEPROM is optional and can be programmed with
the LAN9218i MAC address. The LAN9218i can optionally load the MAC address automatically after power-on reset,
hardware reset, or soft reset.
1.10
Power Management Controls
The LAN9218i supports comprehensive array of power management modes to allow use in power sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9218i. An external PME
(Power Management Event) interrupt is provided to indicate detection of a wakeup event.
1.11
General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9218i and may be programmed to issue a timed
interrupt.
1.12
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the
LAN9218i Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are
supported.
The LAN9218i host bus interface supports 32-bit and 16-bit bus transfers. Internally, all data paths are 32-bits wide. The
LAN9218i can be interfaced to either Big-Endian or Little-Endian processors.
2006-2017 Microchip Technology Inc.
DS00002410A-page 7
LAN9218i
2.0
PIN DESCRIPTION AND CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PD
SPEED_SEL
AMDIX_EN
IRQ
NC
PME
EECLK**
EECS
EEDIO**
GND_CORE
VDD_CORE
D0
D1
D2
VDD_IO
GND_IO
D3
D4
D5
D6
VDD_IO
GND_IO
D7
D8
D9
FIGURE 2-1:
FIFO_SEL
76
VSS_A
(Note 1) TPO-
77
78
(Note 1) TPO+
79
VSS_A
VDD_A
80
81
(Note 1) TPI (Note 1) TPI+
82
83
NC
VDD_A
84
85
VSS_A
86
EXRES1
VSS_A
87
88
VDD_A
NC
89
90
91
92
93
nCS
94
nRESET
GND_IO
95
96
VDD_IO
GPIO0/nLED1**
97
98
GPIO1/nLED2**
GPIO2/nLED3**
99
100
D10
D11
48
VDD_IO
47
46
GND_IO
D12
45
44
D13
D14
43
42
D15
VDD_IO
41
GND_IO
40
39
D16
D17
LAN9218i
38
D18
37
36
D19
D20
100 PIN TQFP
35
34
VDD_IO
GND_IO
33
D21
32
31
D22
D23
30
29
D24
D25
28
27
VDD_IO
GND_IO
26
D26
GND_CORE
VREG
VDD_CORE
VSS_PLL
XTAL2
XTAL1
VDD_PLL
VDD_REF
ATEST
RBIAS
VSS_REF
A7
A6
A5
A4
A3
A2
A1
GND_IO
VDD_IO
D31
D30
D29
D28
D27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
nRD
nWR
50
49
**DENOTES A MULTIFUNCTON PIN
NOTE 1: When HP Auto -MDIX is activated, the TPO+/- pins function as TPI +/- and vice-versa.
DS00002410A-page 8
2006-2017 Microchip Technology Inc.
LAN9218i
2.1
Pin List
TABLE 2-1:
HOST BUS INTERFACE SIGNALS
Buffer
Type
#
Pins
D[31:16]
I/O8
(PD)
16
Bi-directional data port.
Note that Pull-downs are disabled in 32 bit mode.
Host Data Low
D[15:0]
I/O8
16
Bi-directional data port.
Host Address
A[7:1]
IS
7
7-bit Address Port. Used to select Internal CSR’s and
TX and RX FIFOs.
Read Strobe
nRD
IS
1
Active low strobe to indicate a read cycle.
Write Strobe
nWR
IS
1
Active low strobe to indicate a write cycle. This signal,
qualified with nCS, is also used to wakeup the
LAN9218i when it is in a reduced power state.
Chip Select
nCS
IS
1
Active low signal used to qualify read and write
operations. This signal qualified with nWR is also used
to wakeup the LAN9218i when it is in a reduced power
state.
Interrupt
Request
IRQ
O8/OD8
1
Programmable Interrupt request. Programmable
polarity, source and buffer types.
FIFO Select
FIFO_SEL
IS
1
When driven high all accesses to the LAN9218i are to
the RX or TX Data FIFOs. In this mode, the A[7:3]
upper address inputs are ignored.
Name
Symbol
Host Data High
TABLE 2-2:
Description
DEFAULT ETHERNET SETTINGS
Default Ethernet Settings
SPEED_SEL
Speed
Duplex
Auto Neg.
0
10Mbps
Half-Duplex
Disabled
1
100Mbps
Half-Duplex
Enabled
TABLE 2-3:
LAN INTERFACE SIGNALS
Name
Symbol
Buffer
Type
# Pins
TPO+
TPO+
AO
1
Transmit Positive Output (normal)
Receive Positive Input (reversed)
TPO-
TPO-
AO
1
Transmit Negative Output (normal)
Receive Negative Input (reversed)
TPI+
TPI+
AI
1
Receive Positive Input (normal)
Transmit Positive Input (reversed)
TPI-
TPI-
AI
1
Receive Negative Input (normal)
Transmit Negative Output (reversed)
PHY External Bias
Resistor
EXRES1
AI
1
Must be connected to ground through a 12.4K
ohm 1% resistor.
2006-2017 Microchip Technology Inc.
Description
DS00002410A-page 9
LAN9218i
Note:
The pin names for the twisted pair pins shown above apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected, or a reverse connection is manually selected, the input pins
become outputs, and vice-versa, as indicated in the descriptions.
TABLE 2-4:
SERIAL EEPROM INTERFACE SIGNALS
Name
Symbol
EEPROM Data,
GPO3, TX_EN,
TX_CLK,
D32/nD16
EEDIO/GPO3/
TX_EN/TX_CLK
Buffer
Type
# Pins
Description
I/O8
1
EEPROM Data: This bi-directional pin can be
connected to a serial EEPROM DIO. This is
optional.
(D32/nD16)
General Purpose Output 3: This pin can also
function as a general purpose output, or it can
be configured to monitor the TX_EN or
TX_CLK signals on the internal MII port. When
configured as a GPO signal, or as a
TX_EN/TX_CLK monitor, the EECS pin is
deasserted so as to never unintentionally
access the serial EEPROM. This signal cannot
function as a general-purpose input.
Data Bus Width Select: This signal also
functions as a configuration input on power-up
and is used to select the host bus data width.
Upon deassertion of reset, the value of the
input is latched. When high, a 32-bit data bus
is utilized. When low, a 16-bit interface is
utilized.
EEPROM Chip
Select
EECS
O8
1
Serial EEPROM chip select.
EEPROM Clock,
GPO4 RX_DV,
RX_CLK
EECLK/GPO4/
RX_DV/RX_CLK
O8
1
EEPROM Clock: Serial EEPROM Clock pin.
General Purpose Output 4: This pin can also
function as a general-purpose output, or it can
be configured to monitor the RX_DV or
RX_CLK signals on the internal MII port. When
configured as a GPO signal, or as an
RX_DV/RX_CLK monitor, the EECS pin is
deasserted so as to never unintentionally
access the serial EEPROM. This signal cannot
function as a general-purpose input.
Note:
DS00002410A-page 10
When the EEPROM interface is not
used, the EECLK pin must be left
unconnected.
2006-2017 Microchip Technology Inc.
LAN9218i
TABLE 2-5:
SYSTEM AND POWER SIGNALS
Name
Symbol
Buffer
Type
# Pins
Description
Crystal 1, Clock In
XTAL1/CLKIN
lCLK
1
External 25MHz Crystal Input. This pin can also
be connected to single-ended TTL oscillator
(CLKIN). If this method is implemented, XTAL2
should be left unconnected.
Crystal 2
XTAL2
OCLK
1
External 25MHz Crystal output.
Reset
nRESET
IS
(PU)
1
Active-low reset input. Resets all logic and
registers within the LAN9218i. This signal is
pulled high with a weak internal pull-up resistor.
If nRESET is left unconnected, the LAN9218i
will rely on its internal power-on reset circuitry.
Note:
The LAN9218i must always be read
at least once after power-up, reset,
or upon return from a power-saving
state or write operations will not
function. See Section 3.10, "Detailed
Reset Description," on page 32 for
additional information
Wakeup Indicator
PME
O8/OD8
1
When programmed to do so, is asserted when
the LAN9218i detects a wake event and is
requesting the system to wake up from the
associated sleep state. The polarity and buffer
type of this signal is programmable.
Note:
Detection of a Power Management
Event, and assertion of the PME signal will not wakeup the LAN9218i.
The LAN9218i will only wake up
when it detects a host write cycle
(assertion of nCS and nWR).
Although any write to the LAN9218i,
regardless of the data written, will
wake-up the device when it is in a
power-saving mode, it is required
that the BYTE_TEST register be
used for this purpose.
Auto-MDIX Enable
AMDIX_EN
I
(PD)
1
Enables Auto-MDIX. Pull high enable AutoMDIX, pull low or leave unconnected to disable
Auto-MDIX.
10/100 Selector
SPEED_SEL
I
(PU)
1
This signal functions as a configuration input on
power-up and is used to select the default
Ethernet settings. Upon deassertion of reset,
the value of the input is latched. This signal
functions as shown in Table 2-2, "Default
Ethernet Settings", below.
No Connect
NC
4
No Connect. These pins must be left open.
Pull-Down
(Reserved)
PD
1
Reserved for internal test purposes only. This
pin should be pulled low through an external
pull-down resistor.
2006-2017 Microchip Technology Inc.
DS00002410A-page 11
LAN9218i
TABLE 2-5:
SYSTEM AND POWER SIGNALS (CONTINUED)
Name
Symbol
Buffer
Type
General Purpose
I/O data,
nLED1 (Speed
Indicator),
nLED2 (Link &
Activity Indicator),
GPIO[2:0]/
nLED[3:1]
IS/O12/
OD12
# Pins
Description
3
General Purpose I/O data: These three
general-purpose signals are fully programmable
as either push-pull output, open-drain output or
input by writing the GPIO_CFG configuration
register in the CSR’s. They are also multiplexed
as GP LED connections.
GPIO signals are Schmitt-triggered inputs.
When configured as LED outputs these signals
are open-drain.
nLED3 (FullDuplex
Indicator).
nLED1 (Speed Indicator). This signal is driven
low when the operating speed is 100Mb. During
auto-negotiation, when the cable is
disconnected, and during 10Mbs operation, this
signal is driven high.
nLED2 (Link & Activity Indicator). This signal
is driven low (LED on) when the LAN9218i
detects a valid link. This signal is pulsed high
(LED off) for 80mS whenever transmit or
receive activity is detected. This signal is then
driven low again for a minimum of 80mS, after
which time it will repeat the process if TX or RX
activity is detected. Effectively, LED2 is
activated solid for a link. When transmit or
receive activity is sensed LED2 will flash as an
activity indicator.
nLED3 (Full-Duplex Indicator). This signal is
driven low when the link is operating in fullduplex mode.
RBIAS
RBIAS
AI
1
PLL Bias: Connect to an external 12.0K ohm
1.0% resistor to ground. Used for the PLL Bias
circuit.
Test Pin
ATEST
I
1
This pin must be connected to VDD for normal
operation.
Internal Regulator
Power
VREG
P
1
3.3V input for internal voltage regulator
+3.3V I/O Power
VDD_IO
P
8
+3.3V I/O logic power supply pins
I/O Ground
GND_IO
P
8
Ground for I/O pins
+3.3V Analog
Power
VDD_A
P
3
+3.3V analog power supply pins. See Note 2-1.
Analog Ground
VSS_A
P
4
Ground for analog circuitry
Core Voltage
Decoupling
VDD_CORE
P
2
+1.8 V from internal core regulator. Both pins
must be connected together externally. Each
pin requires a 0.01uF decoupling capacitor. In
addition, pin 3 requires a bulk 10uF capacitor
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