LAN9254
2/3-Port EtherCAT® Slave Controller with Integrated
Ethernet PHYs and Demultiplexed HBI / 32 DIGIOs
Highlights
Key Benefits
• 2/3-port EtherCAT slave controller with 8 Fieldbus
Memory Management Units (FMMUs) and
8 SyncManagers
• Interfaces to most 8/16-bit embedded controllers
and 32-bit embedded controllers with an 8/16-bit
bus
• Integrated Ethernet PHYs with HP Auto-MDIX
• Wake on LAN (WoL) support
• Low power mode allows systems to enter sleep
mode until addressed by the Master
• Cable diagnostic support
• 1.8V to 3.3V variable voltage I/O
• Integrated 1.2V regulator for single 3.3V operation
• Integrated high-performance 100Mbps Ethernet
transceivers
Target Applications
•
•
•
•
•
•
Motor Motion Control
Process/Factory Automation
Communication Modules, Interface Cards
Sensors
Hydraulic & Pneumatic Valve Systems
Operator Interfaces
-
Compliant with IEEE 802.3/802.3u (Fast Ethernet)
Signal Quality Index diagnostics
Loop-back modes
Automatic polarity detection and correction
HP Auto-MDIX
Compatible with EtherCAT P
• EtherCAT slave controller
- Supports 8 FMMUs
- Supports 8 SyncManagers
- Distributed clock support allows synchronization with
other EtherCAT devices
- 8K bytes of DPRAM
• 8/16-Bit Host Bus Interface
- Indexed register, multiplexed or demultiplexed bus
- Allows local host to enter sleep mode until addressed by
EtherCAT Master
- SPI / SQI (Quad SPI) support
• Digital I/O Mode for optimized system cost
- 32 available Digital I/Os
• 3rd port for flexible network configurations
• Comprehensive power management features
- 3 power-down levels
- Wake on link status change (energy detect)
- Magic packet wakeup, Wake on LAN (WoL), wake on
broadcast, wake on perfect DA
- Wakeup indicator event signal
• Power and I/O
- Integrated power-on reset circuit
- Latch-up performance exceeds 150mA
per EIA/JESD78, Class II
- JEDEC Class 3A ESD performance
- Single 3.3V power supply
(integrated 1.2V regulator)
• Additional Features
- EEPROM emulation
- Transformer-less link support
- Multifunction GPIOs
- Ability to use low cost 25MHz crystal for reduced BOM
- 25MHz clock output for reference clock daisy chaining
• Packaging
- Pb-free RoHS compliant 80-pin TQFP-EP
• Available in commercial, industrial, and extended
industrial temp. ranges
2020 Microchip Technology Inc.
DS00003422A-page 1
LAN9254
TO OUR VALUED CUSTOMERS
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DS00003422A-page 2
2020 Microchip Technology Inc.
LAN9254
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 General Description ........................................................................................................................................................................ 8
3.0 Pin Descriptions and Configuration ............................................................................................................................................... 12
4.0 Power Connections ....................................................................................................................................................................... 37
5.0 Register Map ................................................................................................................................................................................. 40
6.0 Clocks, Resets, and Power Management ..................................................................................................................................... 45
7.0 System Interrupts .......................................................................................................................................................................... 60
8.0 Host Bus Interface ........................................................................................................................................................................ 68
9.0 SPI/SQI Slave ............................................................................................................................................................................. 163
10.0 Ethernet PHYs .......................................................................................................................................................................... 201
11.0 EtherCAT .................................................................................................................................................................................. 282
12.0 EEPROM Interface ................................................................................................................................................................... 388
13.0 Chip Mode Configuration .......................................................................................................................................................... 390
14.0 General Purpose Timer & Free-Running Clock ........................................................................................................................ 394
15.0 Miscellaneous ........................................................................................................................................................................... 397
16.0 JTAG ......................................................................................................................................................................................... 401
17.0 Operational Characteristics ....................................................................................................................................................... 403
18.0 Package Information ................................................................................................................................................................. 418
Appendix A: Revision History ............................................................................................................................................................ 419
The Microchip Web Site .................................................................................................................................................................... 420
Customer Change Notification Service ............................................................................................................................................. 420
Customer Support ............................................................................................................................................................................. 420
Product Identification System ........................................................................................................................................................... 421
2020 Microchip Technology Inc.
DS00003422A-page 3
LAN9254
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
10BASE-T
10 Mbps Ethernet, IEEE 802.3 compliant
100BASE-TX
100 Mbps Fast Ethernet, IEEE802.3u compliant
ADC
Analog-to-Digital Converter
ALR
Address Logic Resolution
AN
Auto-Negotiation
BLW
Baseline Wander
BM
Buffer Manager - Part of the switch fabric
BPDU
Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol information
Byte
8 bits
CSMA/CD
Carrier Sense Multiple Access/Collision Detect
CSR
Control and Status Registers
CTR
Counter
DA
Destination Address
DWORD
32 bits
EPC
EEPROM Controller
FCS
Frame Check Sequence - The extra checksum characters added to the end of an
Ethernet frame, used for error detection and correction.
FIFO
First In First Out buffer
FSM
Finite State Machine
GPIO
General Purpose I/O
Host
External system (Includes processor, application software, etc.)
IGMP
Internet Group Management Protocol
Inbound
Refers to data input to the device from the host
Level-Triggered Sticky Bit
This type of status bit is set whenever the condition that it represents is asserted. The
bit remains set until the condition is no longer true and the status bit is cleared by writing a zero.
lsb
Least Significant Bit
LSB
Least Significant Byte
LVDS
Low Voltage Differential Signaling
MDI
Medium Dependent Interface
MDIX
Media Independent Interface with Crossover
MII
Media Independent Interface
MIIM
Media Independent Interface Management
MIL
MAC Interface Layer
MLD
Multicast Listening Discovery
MLT-3
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a
change in the logic level represents a code bit “1” and the logic output remaining at the
same level represents a code bit “0”.
msb
Most Significant Bit
MSB
Most Significant Byte
DS00003422A-page 4
2020 Microchip Technology Inc.
LAN9254
TABLE 1-1:
GENERAL TERMS (CONTINUED)
Term
Description
NRZI
Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and
leaves the signal unchanged for a “0”
N/A
Not Applicable
NC
No Connect
OUI
Organizationally Unique Identifier
Outbound
Refers to data output from the device to the host
PISO
Parallel In Serial Out
PLL
Phase Locked Loop
PTP
Precision Time Protocol
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
RTC
Real-Time Clock
SA
Source Address
SFD
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an
Ethernet frame.
SIPO
Serial In Parallel Out
SMI
Serial Management Interface
SQE
Signal Quality Error (also known as “heartbeat”)
SSD
Start of Stream Delimiter
UDP
User Datagram Protocol - A connectionless protocol run on top of IP networks
UUID
Universally Unique IDentifier
WORD
16 bits
2020 Microchip Technology Inc.
DS00003422A-page 5
LAN9254
1.2
Buffer Types
TABLE 1-2:
BUFFER TYPES
BUFFER TYPE
DESCRIPTION
IS
Schmitt-triggered input
O8
3.3V output with 8 mA sink and 8 mA source
OD8
3.3V open-drain output with 8 mA sink
OD12
3.3V open-drain output with 12 mA sink
OS12
3.3V open-source output with 12 mA source
VIS
Variable voltage Schmitt-triggered input
VO8
Variable voltage output with 8 mA sink and 8 mA source
VOD8
Variable voltage open-drain output with 8 mA sink
VOS8
Variable voltage open-source output with 8 mA source
VO12
Variable voltage output with 12 mA sink and 12 mA source
VOD12
Variable voltage open-drain output with 12 mA sink
VOS12
Variable voltage open-source output with 12 mA source
PU
50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Note:
PD
50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note:
AI
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
Analog input
AIO
Analog bidirectional
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
P
DS00003422A-page 6
Power pin
2020 Microchip Technology Inc.
LAN9254
1.3
Register Nomenclature
TABLE 1-3:
REGISTER NOMENCLATURE
Register Bit Type Notation
R
Register Bit Description
Read: A register or bit with this attribute can be read.
W
Read: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
WO
Write only: If a register or bit is write-only, reads will return unspecified data.
W1S
Write One to Set: Writing a one sets the value. Writing a zero has no effect
W1C
Write One to Clear: Writing a one clears the value. Writing a zero has no effect
WAC
Write Anything to Clear: Writing anything clears the value.
RC
Read to Clear: Contents is cleared after the read. Writes have no effect.
LL
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
RO/LH
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it
is read, the bit will either remain high if the high condition remains, or will go low if the
high condition has been removed. If the bit has not been read, the bit will remain high
regardless of a change to the high condition. This mode is used in some Ethernet PHY
registers.
NASR
Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros to ensure future compatibility. The value of reserved bits is not guaranteed on a read.
2020 Microchip Technology Inc.
DS00003422A-page 7
LAN9254
2.0
GENERAL DESCRIPTION
The LAN9254 is a 2/3-port EtherCAT slave controller with dual integrated Ethernet PHYs, each containing a full-duplex
100BASE-TX transceiver that supports 100Mbps (100BASE-TX) operation. The LAN9254 supports HP Auto-MDIX,
allowing the use of direct connect or cross-over LAN cables. EtherCAT P and Signal Quality Index PHY diagnostics are
supported.
The LAN9254 includes an EtherCAT slave controller with 8K bytes of Dual Port memory (DPRAM) and 8 Fieldbus Memory Management Units (FMMUs). Each FMMU performs the task of mapping logical addresses to physical addresses.
The EtherCAT slave controller also includes 8 SyncManagers to allow the exchange of data between the EtherCAT master and the local application. Each SyncManager's direction and mode of operation is configured by the EtherCAT master. Two modes of operation are available: buffered mode or mailbox mode. In the buffered mode, both the local
microcontroller and EtherCAT master can write to the device concurrently. The buffer within the LAN9254 will always
contain the latest data. If newer data arrives before the old data can be read out, the old data will be dropped. In mailbox
mode, access to the buffer by the local microcontroller and the EtherCAT master is performed using handshakes, guaranteeing that no data will be dropped.
The LAN9254 provides an EtherCAT direct mapping mode, which inserts the EtherCAT registers into the base address
space. The EtherCAT direct mapping mode eliminates the need for a command/data access structure, which can
increase the speed of smaller data blocks.
The LAN9254 supports numerous power management and wakeup features. The LAN9254 can be placed in a reduced
power mode and can be programmed to issue an external wake signal (IRQ or PME) via several methods, including
“Magic Packet”, “Wake on LAN”, wake on broadcast, wake on perfect DA, and “Link Status Change”. This signal is ideal
for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power
state via a host processor command or one of the wake events.
The LAN9254 contains an I2C master EEPROM controller for connection to an EEPROM, allowing for the storage and
retrieval of static data. The internal EEPROM Loader automatically loads stored configuration settings from the
EEPROM into the device at reset. An EEPROM emulation feature, which requires additional software support, is available for EEPROM-less operation.
For simple digital modules without microcontrollers, the LAN9254 can also operate in Digital I/O Mode where 32 digital
signals can be controlled or monitored by the EtherCAT master.
To enable star or tree network topologies, the device can be configured as a 3-port slave, providing an additional MII
port. This port can be connected to an external PHY, forming a tap along the current daisy chain, or to another LAN9254
creating a 4-port solution. The MII port can point upstream (as Port 0) or downstream (as Port 2).
LED support consists of a standard RUN indicator and a LINK / Activity indicator per port. Configuration options enable
ERR and STATE_RUN indicators.
A 64-bit distributed clock is included to enable high-precision synchronization and to provide accurate information about
the local timing of data acquisition.
The LAN9254 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator.
The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system
power dissipation.
The LAN9254 is available in commercial, industrial, and extended industrial temperature ranges. Figure 2-1 details a
typical system application, while Figure 2-2 provides an internal block diagram of the LAN9254.
Note:
Extended temp. (105ºC) is supported only with an external voltage regulator (internal regulator must be disabled) and 2.5V (typ) Ethernet magnetics.
DS00003422A-page 8
2020 Microchip Technology Inc.
LAN9254
FIGURE 2-1:
SYSTEM BLOCK DIAGRAM
EtherCAT Slave
Microprocessor/
Microcontroller
EEPROM
(optional)
EtherCAT
Master
Local
Bus
Magnetics
RJ45
Magnetics
RJ45
PHY
RJ45
LAN9254
32 x DIGIOs
16 x GPIOs
EtherCAT
Slave
EtherCAT
Slave
EtherCAT
Slave
25MHz
FIGURE 2-2:
INTERNAL BLOCK DIAGRAM
Registers / RAM
ESC Address Space
SyncManager
FMMU
GPIO /
DIGIO
Port 0
100 PHY
ECAT Mux
Port 2
Ethernet
Auto
Fowarder
Loopback
Auto
Fowarder
Loopback
Auto
Fowarder
Loopback
SPI Slave
Controller
Host Bus
Interface
Registers
Port 1
Ethernet
PIN Mux
To 8/16-bit
Host Bus,
MII, SPI,
Digital IOs,
GPIOs
EtherCAT Slave Controller
100 PHY
Registers
LED
Controller
I2C
EEPROM
System
Interrupt
Controller
System Clocks/
Reset Controller
25MHz In
To optional LEDs
2020 Microchip Technology Inc.
To I 2C
IRQ
External
25MHz Crystal
25MHz Out
DS00003422A-page 9
LAN9254
The LAN9254 can operate in Microcontroller, Expansion, or Digital I/O mode:
Microcontroller Mode: The LAN9254 communicates with the microcontroller through an SRAM-like slave interface.
The simple, yet highly functional host bus interface provides a glue-less connection to most common 8 or 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with an 8 or 16-bit external bus.
The integrated Host Bus Interface (HBI) supports 8/16-bit operation with big, little, and mixed endian operations. Two
process data RAM FIFOs interface the HBI to the EtherCAT slave controller and facilitate the transferring of process
data information between the host CPU and the EtherCAT slave. A configurable host interrupt pin allows the device to
inform the host CPU of any internal interrupts.
Three user selectable Microcontroller Mode Host Bus Interface (HBI) options are available:
• Indexed register access
This implementation provides three index/data register banks, each with independent Byte/WORD to DWORD
conversion. Internal registers are accessed by first writing one of the three index registers, followed by reading or
writing the corresponding data register. Three index/data register banks support up to 3 independent driver
threads without access conflicts. Each thread can write its assigned index register without the issue of another
thread overwriting it. Two 16-bit cycles or four 8-bit cycles are required within the same 32-bit index/data register however, these access can be interleaved. Non-indexed read and write accesses are supported to the process
data FIFOs. The non-indexed FIFO access provides independent Byte/WORD to DWORD conversion, supporting
interleaved accesses with the index/data registers.
• Multiplexed address/data bus
This implementation provides a multiplexed address and data bus with both single phase and dual phase address
support. The address is loaded with an address strobe followed by data access using a read or write strobe. Two
back to back 16-bit data cycles or 4 back to back 8-bit data cycles are required within the same 32-bit DWORD.
These accesses must be sequential without any interleaved accesses to other registers.
• Demultiplexed address/data bus
This implementation provides a demultiplexed address and data bus with the address and endianness select
inputs directly provided by the host. Two back to back 16-bit data cycles or 4 back to back 8-bit data cycles are
required within the same 32-bit DWORD. These accesses must be sequential without any interleaved accesses to
other registers.
Alternatively, the device can be accessed via SPI/SQI, while also providing up to 16 inputs or outputs for general purpose usage. An SPI / SQI (Quad SPI) slave controller provides a low pin count synchronous slave interface that facilitates communication between the device and a host system. The SPI / SQI slave allows access to the System CSRs,
internal FIFOs and memories. It supports single and multiple register read and write commands with incrementing, decrementing and static addressing. Single, Dual and Quad bit lanes are supported with a clock rate of up to 80 MHz.
Expansion Mode: While the device is in SPI/SQI mode, a third networking port can be enabled to provide an additional
MII port. This port can be connected to an external PHY, to enable star or tree network topologies, or to another
LAN9254 to create a four port solution. This port can be configured for the upstream or downstream direction.
Digital I/O Mode: For simple digital modules without microcontrollers, the LAN9254 can operate in Digital I/O Mode
where 32 digital signals can be controlled or monitored by the EtherCAT master. Up to 7 control signals are also provided.
DS00003422A-page 10
2020 Microchip Technology Inc.
LAN9254
Figure 2-3 provides a system level overview of each mode of operation.
FIGURE 2-3:
MODES OF OPERATION
Microcontroller Mode
Digital I/O Mode
(via Host Bus Interface)
Microprocessor/
Microcontroller
Host Bus Interface
RJ45
Magnetics
LAN9254
Magnetics
RJ45
Magnetics
LAN9254
Magnetics
RJ45
Magnetics
RJ45
RJ45
Digital I/Os
Microcontroller Mode
Expansion Mode
(via SPI)
Microprocessor/
Microcontroller
Microprocessor/
Microcontroller
SPI/SQI
SPI/SQI
RJ45
RJ45
Magnetics
LAN9254
Magnetics
Magnetics
LAN9254
RJ45
PHY
GPIOs
Magnetics
2020 Microchip Technology Inc.
RJ45
DS00003422A-page 11
LAN9254
3.0
PIN DESCRIPTIONS AND CONFIGURATION
3.1
Pin Assignments
RXPA
RXNA
TXPA
TXNA
VDD33TXRX1
DIGIO31/LATCH1
DIGIO30/LATCH0
BE1/DIGIO29
D5/AD5/OUTVALID/SCS#
D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK
LINKACTLED0/TDO/
CHIP_MODE0/100FD_A/LEDPOL0
69
68
67
66
65
64
63
62
61
VDD33BIAS
70
VDD12TX2
74
71
RXPB
75
RBIAS
RXNB
76
VDD12TX1
TXPB
77
72
TXNB
78
73
VDD33TXRX2
79
PIN ASSIGNMENTS (TOP VIEW)
80
FIGURE 3-1:
OSCI
1
60
VDDIO
OSCO
2
59
LINKACTLED1/TDI/CHIP_MODE1/LEDPOL1
OSCVDD12
3
58
RUNLED/STATE_RUNLED/E2PSIZE/EE_EMUL0/LEDPOL3
OSCVSS
4
57
IRQ/LATCH1
VDD33
5
56
EESCL/TCK/EE_EMUL2
VDDCR
6
55
EESDA/TMS/EE_EMUL1
REG_EN
7
54
TESTMODE
CLK_25/CLK_25_EN/XTAL_MODE
8
53
D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO
ERRLED/PME/100FD_B/LEDPOL4
9
52
D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC
51
VDDCR
50
VDDIO
LAN9254
WAIT_ACK/PME/LATCH0/EE_EMUL_SPI3
10
RST#
11
A5/DIGIO16
12
49
D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK
A6/DIGIO17
13
48
D3/AD3/WD_TRIG/SIO3/EE_EMUL_SPI1
D2/AD2/SOF/SIO2/EE_EMUL_SPI0
14
47
BE0/DIGIO28
D1/AD1/EOF/SO/SIO1
15
46
END_SEL/DIGIO27
VDDIO
16
45
A15/DIGIO26
A7/DIGIO18
17
44
A14/DIGIO25
A8/DIGIO19
18
43
SYNC0/LATCH0/PME
D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1
19
42
A13/DIGIO24
D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0
20
41
A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER
80-T QFP-EP
( To p Vi ew )
VSS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A10/DIGIO21
A11/DIGIO22
D9/AD9/LATCH_IN/SCK
VDDIO
D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1/100FD_B
D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0/100FD_A
D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN
VDDCR
A1/ALELO/OE_EXT/MII_CLK25/EE_EMUL_SPI2
A3/BE0/DIGIO11/GPI11/GPO11/MII_RXDV
A4/BE1/DIGIO12/GPI12/GPO12/MII_RXD0
CS/DIGIO13/GPI13/GPO13/MII_RXD1
A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/
EE_EMUL_ALELO_POL/MII_LINKPOL/LEDPOL2
WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2
RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3
VDDIO
A12/DIGIO23
22
SYNC1/LATCH1/PME
A9/DIGIO20
21
D0/AD0/WD_STATE/SI/SIO0
(Connect exposed pad to ground with a via field)
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.
Note:
When a “#” is used at the end of the signal name, it indicates that the signal is active low. For example,
RST# indicates that the reset signal is active low.
Configuration straps are identified by an underlined symbol name. Refer to Section 3.3, "Configuration
Straps," on page 36 for additional information.
The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Section 3.2, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".
DS00003422A-page 12
2020 Microchip Technology Inc.
LAN9254
Table 3-1 details the pin assignments in table format. As shown, select pin functions may change based on the device’s
mode of operation. For modes where a specific pin has no function, the table cell will be marked with “-”.
TABLE 3-1:
PIN ASSIGNMENTS
HBI
SPI/SQI with
Pin
HBI Indexed HBI Multiplexed
SPI/SQI with MII
Digital I/O
Demultiplexed GPIO Mode Pin
Number Mode Pin Name Mode Pin Name
Mode Pin Name Mode Pin Name
Mode Pin Name
Name
1
OSCI
2
OSCO
3
OSCVDD12
4
OSCVSS
5
VDD33
6
VDDCR
7
REG_EN
8
CLK_25/CLK_25_EN/XTAL_MODE
9
ERRLED/PME/100FD_B/LEDPOL4
10
WAIT_ACK/PME
ERRLED/
PME/
LEDPOL4
ERRLED/
100FD_B/
LEDPOL4
WAIT_ACK/PME/EE_EMUL_SPI3
LATCH0
RST#
11
12
-
-
A5
-
-
DIGIO16
13
-
-
A6
-
-
DIGIO17
14
D2
AD2
D2
SIO2/EE_EMUL_SPI0
SOF
15
D1
AD1
D1
SO/SIO1
EOF
VDDIO
16
17
-
-
A7
-
-
DIGIO18
18
-
-
A8
-
-
DIGIO19
19
D14
AD14
D14
GPI8/GPO8
MII_TXD3/
TX_SHIFT1
DIGIO8
20
D13
AD13
D13
GPI7/GPO7
MII_TXD2/
TX_SHIFT0
DIGIO7
21
D0
AD0
D0
SI/SIO0
WD_STATE
SYNC1/LATCH1/PME
22
SYNC1/
LATCH1
23
-
-
A9
-
-
DIGIO20
24
-
-
A10
-
-
DIGIO21
25
-
-
A11
-
-
DIGIO22
26
D9
AD9
D9
27
2020 Microchip Technology Inc.
SCK
LATCH_IN
VDDIO
DS00003422A-page 13
LAN9254
TABLE 3-1:
PIN ASSIGNMENTS (CONTINUED)
HBI
SPI/SQI with
Pin
HBI Indexed HBI Multiplexed
SPI/SQI with MII
Digital I/O
Demultiplexed GPIO Mode Pin
Number Mode Pin Name Mode Pin Name
Mode Pin Name Mode Pin Name
Mode Pin Name
Name
28
D12
AD12
D12
GPI6/GPO6
MII_TXD1/
100FD_B
DIGIO6
29
D11
AD11
D11
GPI5/GPO5
MII_TXD0/
100FD_A
DIGIO5
30
D10
AD10
D10
GPI4/GPO4
MII_TXEN
DIGIO4
MII_CLK25/
OE_EXT
VDDCR
31
32
A1
ALELO
A1
-
EE_EMUL_SPI2
33
A3
BE0
A3
GPI11/GPO11
MII_RXDV
DIGIO11
34
A4
BE1
A4
GPI12/GPO12
MII_RXD0
DIGIO12
GPI13/GPO13
MII_RXD1
DIGIO13
GPI10/GPO10
LINKACTLED2/
MII_LINKPOL/
LEDPOL2
DIGIO10
CS
35
36
A2
ALEHI/
EE_EMUL_A
LELO_POL
A2
37
WR/ENB
GPI14/GPO14
MII_RXD2
DIGIO14
38
RD/RD_WR
GPI15/GPO15
MII_RXD3
DIGIO15
VDDIO
39
40
-
-
A12
-
-
DIGIO23
41
A0/D15
AD15
A0/D15
GPI9/GPO9
MII_RXER
DIGIO9
42
-
-
A13
-
-
DIGIO24
SYNC0/LATCH0/PME
43
SYNC0/
LATCH0
44
-
-
A14
-
-
DIGIO25
45
-
-
A15
-
-
DIGIO26
46
-
-
END_SEL
-
-
DIGIO27
47
-
-
BE0
-
-
DIGIO28
48
D3
AD3
D3
49
D6
AD6
D6
SIO3/EE_EMUL_SPI1
GPI0/GPO0
50
VDDIO
51
VDDCR
WD_TRIG
MII_RXCLK
DIGIO0
52
D7
AD7
D7
GPI1/GPO1
MII_MDC
DIGIO1
53
D8
AD8
D8
GPI2/GPO2
MII_MDIO
DIGIO2
TESTMODE
54
55
EESDA/TMS/EE_EMUL1
EESDA/TMS
56
EESCL/TCK/EE_EMUL2
EESCL/TCK
57
IRQ
LATCH1
DS00003422A-page 14
2020 Microchip Technology Inc.
LAN9254
TABLE 3-1:
PIN ASSIGNMENTS (CONTINUED)
HBI
SPI/SQI with
Pin
HBI Indexed HBI Multiplexed
SPI/SQI with MII
Digital I/O
Demultiplexed GPIO Mode Pin
Number Mode Pin Name Mode Pin Name
Mode Pin Name Mode Pin Name
Mode Pin Name
Name
RUNLED/STATE_RUNLED/E2PSIZE/EE_EMUL0/LEDPOL3
58
RUNLED/
STATE_RUNLED/
E2PSIZE/
LEDPOL3
59
LINKACTLED1/TDI/CHIP_MODE1/LEDPOL1
60
VDDIO
61
LINKACTLED0/TDO/CHIP_MODE0/100FD_A/LEDPOL0
LINKACTLED0/
LINKACTLED0/
CHIP_MODE0/
CHIP_MODE0/
MII_LINK
DIGIO3
TDO/
LEDPOL0
62
D4
AD4
D4
GPI3/GPO3
63
D5
AD5
D5
64
-
-
BE1
SCS#
-
TDO/
100FD_A/
LEDPOL0
OUTVALID
-
DIGIO29
65
LATCH0
DIGIO30
66
LATCH1
DIGIO31
67
VDD33TXRX1
68
TXNA
69
TXPA
70
RXNA
71
RXPA
72
VDD12TX1
73
RBIAS
74
VDD33BIAS
75
VDD12TX2
76
RXPB
77
RXNB
78
TXPB
78
TXNB
80
VDD33TXRX2
Exposed
Pad
VSS
2020 Microchip Technology Inc.
DS00003422A-page 15
LAN9254
3.2
Pin Descriptions
This section contains descriptions of the various LAN9254 pins. The pin descriptions have been broken into functional
groups as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
LAN Port A Pins
LAN Port B Pins
LAN Port A & B Power and Common Pins
EtherCAT MII Port & Configuration Strap Pins
Host Bus Pins
SPI/SQI Pins
EtherCAT Distributed Clock Pins
EtherCAT Digital I/O and GPIO Pins
EEPROM Pins
LED & Configuration Strap Pins
Miscellaneous Pins
JTAG Pins
Core and I/O Power and Ground Pins
Note:
Table 3-1 details how the functions described in this section are mapped on the physical device pins. Not
all functions are used for all modes of operation.
TABLE 3-2:
LAN PORT A PINS
NUM
PINS
NAME
SYMBOL
BUFFER
TYPE
1
Port A TP TX/
RX Positive
Channel 1
TXPA
AIO
Port A Twisted Pair Transmit/Receive Positive
Channel 1. See Note 3-1.
1
Port A TP TX/
RX Negative
Channel 1
TXNA
AIO
Port A Twisted Pair Transmit/Receive Negative
Channel 1. See Note 3-1.
1
Port A TP TX/
RX Positive
Channel 2
RXPA
AIO
Port A Twisted Pair Transmit/Receive Positive
Channel 2. See Note 3-1.
1
Port A TP TX/
RX Negative
Channel 2
RXNA
AIO
Port A Twisted Pair Transmit/Receive Negative
Channel 2. See Note 3-1.
Note 3-1
Note:
DESCRIPTION
Either channel 1 or 2 may function as the transmit pair while the other channel functions as the
receive pair. The pin name symbols for the twisted pair pins apply to a normal connection. If AutoMDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will
be swapped internally.
Port A is connected EtherCAT port 0 or 2.
DS00003422A-page 16
2020 Microchip Technology Inc.
LAN9254
TABLE 3-3:
LAN PORT B PINS
NUM
PINS
NAME
SYMBOL
BUFFER
TYPE
1
Port B TP TX/
RX Positive
Channel 1
TXPB
AIO
Port B Twisted Pair Transmit/Receive Positive
Channel 1. See Note 3-2.
1
Port B TP TX/
RX Negative
Channel 1
TXNB
AIO
Port B Twisted Pair Transmit/Receive Negative
Channel 1. See Note 3-2.
1
Port B TP TX/
RX Positive
Channel 2
RXPB
AIO
Port B Twisted Pair Transmit/Receive Positive
Channel 2. See Note 3-2.
1
Port B TP TX/
RX Negative
Channel 2
RXNB
AIO
Port B Twisted Pair Transmit/Receive Negative
Channel 2. See Note 3-2.
Note 3-2
Note:
Either channel 1 or 2 may function as the transmit pair while the other channel functions as the
receive pair. The pin name symbols for the twisted pair pins apply to a normal connection. If AutoMDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will
be swapped internally.
Port B is connected EtherCAT port 1.
TABLE 3-4:
NUM
PINS
DESCRIPTION
LAN PORT A & B POWER AND COMMON PINS
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
Used for internal bias circuits. Connect to an external 12.1 kΩ, 1% resistor to ground.
1
Bias Reference
RBIAS
AI
Refer to the device reference schematic for connection information.
Note:
1
+3.3 V Port A
Analog Power
Supply
VDD33TXRX1
P
1
+3.3 V Port B
Analog Power
Supply
VDD33TXRX2
P
1
+3.3 V Master
Bias Power
Supply
VDD33BIAS
P
2020 Microchip Technology Inc.
The nominal voltage is 1.2 V and the
resistor will dissipate approximately 1 mW
of power.
See Note 3-3.
See Note 3-3.
See Note 3-3.
DS00003422A-page 17
LAN9254
TABLE 3-4:
LAN PORT A & B POWER AND COMMON PINS (CONTINUED)
NUM
PINS
NAME
1
Port A
Transmitter
+1.2 V Power
Supply
Port B
Transmitter
+1.2 V Power
Supply
1
Note 3-3
VDD12TX1
BUFFER
TYPE
P
DESCRIPTION
This pin is supplied from the VDDCR supply either
externally or from the internal voltage regulator.
This pin must be tied to the VDD12TX2 pin for
proper operation.
See Note 3-3.
VDD12TX2
P
This pin is supplied from the VDDCR supply either
externally or from the internal voltage regulator.
This pin must be tied to the VDD12TX1 pin for
proper operation.
See Note 3-3.
Refer to the Power Connections section of the datasheet, the device reference schematic, and the
device LANCheck schematic checklist for additional connection information.
TABLE 3-5:
NUM
PINS
SYMBOL
ETHERCAT MII PORT & CONFIGURATION STRAP PINS
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
25MHz Clock
MII_CLK25
VO12
Note 3-4
This pin is a free running 25MHz clock that can be
used as the clock input to the PHY.
VIS
(PD)
This configuration strap, along with EE_EMUL_SPI0, EE_EMUL_SPI1, and EE_EMUL_SPI3, configures the operation of the Beckhoff SPI interface
during EEPROM Emulation mode. EE_EMUL_SPI2 configures SCS# polarity.
EEPROM
Emulation SPI
Configuration
Strap 2
EE_EMUL_SPI2
Note 3-5
4
Receive Data
MII Port
MII_RXD[3:0]
VIS
(PD)
These pins are the receive data from the external
PHY.
1
Receive Data
Valid MII Port
MII_RXDV
VIS
(PD)
This pin is the receive data valid signal from the
external PHY.
1
Receive Error
MII Port
MII_RXER
VIS
(PD)
This pin is the receive error signal from the external
PHY.
1
Receive Clock
MII Port
MII_RXCLK
VIS
(PD)
This pin is the receive clock from the external PHY.
1
DS00003422A-page 18
0: SCS# active low
1: SCS# active high
2020 Microchip Technology Inc.
LAN9254
TABLE 3-5:
NUM
PINS
ETHERCAT MII PORT & CONFIGURATION STRAP PINS (CONTINUED)
NAME
SYMBOL
BUFFER
TYPE
Transmit Data
MII Port
MII_TXD[3:0]
VO8
DESCRIPTION
These pins are the transmit data to the external
PHY.
These straps configure the value of the external MII
Bus TX timing.
MII Transmit
Timing Shift
Configuration
Straps
4
100Mbps Full
Duplex
Configuration
Strap B
TX_SHIFT[1:0]
Note 3-5
VIS
(PU)
Note 3-6
TX_SHIFT1 is on the MII_TXD3 pin and
TX_SHIFT0 is on the MII_TXD2 pin.
TX_SHIFT[1:0]
00: 20ns
01: 30ns
10: 0ns
11: 10ns
For 3 port mode (as selected by CHIP_MODE1),
this strap configures the default of the ANEG Disable PHY B and AMDIX Disable PHY B fields in the
Hardware Configuration Register (HW_CFG) and
sets the PHY to fixed 100Mbps full-duplex operation by default.
100FD_B
Note 3-5
VIS
(PD)
Note 3-6
0: Auto-negotiation and AMDIX enabled by default
1: Auto-negotiation and AMDIX disabled (fixed
100Mbps full-duplex) by default
100FD_B is located on the MII_TXD1 pin.
Note:
100Mbps Full
Duplex
Configuration
Strap A
In 2 port mode, this strap is on the
ERRLED pin.
For 3 port mode (as selected by CHIP_MODE1),
this strap configures the default of the ANEG Disable PHY A and AMDIX Disable PHY A fields in the
Hardware Configuration Register (HW_CFG) and
sets the PHY to fixed 100Mbps full-duplex operation by default.
100FD_A
Note 3-5
VIS
(PD)
Note 3-6
0: Auto-negotiation and AMDIX enabled by default
1: Auto-negotiation and AMDIX disabled (fixed
100Mbps full-duplex) by default
100FD_A is located on the MII_TXD0 pin.
Note:
1
Transmit Data
Enable MII Port
1
Link Status MII
Port
2020 Microchip Technology Inc.
MII_TXEN
MII_LINK
In 2 port mode, this strap is on the
LINKACTLED0 pin.
VO8
This pin is the transmit data enable signal to the
external PHY.
VIS
This pin is the provided by the PHY to indicate that
a 100 Mbit/s Full Duplex link is established. The
polarity is configurable via the MII_LINKPOL configuration strap.
DS00003422A-page 19
LAN9254
TABLE 3-5:
ETHERCAT MII PORT & CONFIGURATION STRAP PINS (CONTINUED)
NUM
PINS
NAME
SYMBOL
BUFFER
TYPE
1
SMI Clock
MII_MDC
VO8
1
SMI Data
MII_MDIO
VIS/
VO8
DESCRIPTION
This pin is the serial management clock to the
external PHY.
This pin is the serial management Interface data
input/output to the external PHY.
Note:
An external pull-up is required to ensure
that the non-driven state of the MDIO
signal is a logic one.
Note 3-4
A series terminating resistor is recommended for the best PCB signal integrity.
Note 3-5
Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset, EtherCAT reset, or RST# de-assertion. Refer to Section 3.3,
"Configuration Straps," on page 36 for further information.
Note 3-6
An external supplemental pull-up or pull-down may be needed, depending upon the input current
loading of the external MAC/PHY device.
TABLE 3-6:
NUM
PINS
HOST BUS PINS
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
This pin is the host bus read strobe.
Read
RD
VIS
1
Read or Write
RD_WR
VIS
Normally active low, the polarity can be changed
via configuration register settings.
This pin is the host bus direction control. Used in
conjunction with the ENB pin it indicates a read or
write operation.
The normal polarity is read when 1, write when 0
(R/nW) but can be changed via configuration register settings.
This pin is the host bus write strobe.
Write
WR
VIS
1
Enable
ENB
VIS
Normally active low, the polarity can be changed
via configuration register settings.
This pin is the host bus data enable strobe. Used in
conjunction with the RD_WR pin it indicates the
data phase of the operation.
Normally active low, the polarity can be changed
via configuration register settings.
1
Chip Select
DS00003422A-page 20
CS
VIS
This pin is the host bus chip select and indicates
that the device is selected for the current transfer.
Normally active low, the polarity can be changed
via configuration register settings.
2020 Microchip Technology Inc.
LAN9254
TABLE 3-6:
NUM
PINS
HOST BUS PINS (CONTINUED)
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
In 16-bit data mode, these pins indicate which
byte(s) is(are) to be written or read.
In 8-bit data mode, these pins are not used.
These pins are only available in multiplexed and
demultiplexed modes.
2
Byte Enable
BE1
BE0
VIS
(PD)
Normally active low, the polarity can be changed
via configuration register settings.
Note:
The location of these signals varies
dependent on the device mode.
Note:
The pull-down holds the undriven state of
these pins to active, such that previous
PCB designs which do not drive these
signals may work with 16-bit only bus
cycles.
These pins provide the address for indexed and
demultiplexed address modes.
16
Address
A[15:0]
VIS
In 16-bit data mode, bit 0 is not used.
Address bit 0 is shared with data bit 15.
In Indexed Address Mode, A[15:5] are not used.
Data
D[15:0]
VIS/
VO8
These pins are the host bus data bus for non-multiplexed address modes.
In 8-bit data mode, bits 15-8 are not used. Their
input and output drivers are disabled.
Address bit 0 is shared with data bit 15.
These pins are the host bus address / data bus for
multiplexed address mode.
16
Bits 15-8 provide the upper byte of address for single phase multiplexed address mode.
Address and
Data
AD[15:0]
VIS/
VO8
Bits 7-0 provide the lower byte of address for single
phase multiplexed address mode and both bytes of
address for dual phase multiplexed address mode.
In 8-bit data dual phase multiplexed address mode,
bits 15-8 are not used. Their input and output drivers are disabled.
2020 Microchip Technology Inc.
DS00003422A-page 21
LAN9254
TABLE 3-6:
NUM
PINS
HOST BUS PINS (CONTINUED)
NAME
SYMBOL
Address Latch
Enable High
ALEHI
EEPROM Emulation ALELO
Polarity Strap 0
EE_EMUL_ALEL
O_POL
Note 3-7
BUFFER
TYPE
VIS
Address Latch
Enable Low
This pin indicates the address phase for multiplexed address modes. It is used to load the higher
address byte in dual phase multiplexed address
mode.
Normally active low (address saved on rising
edge), the polarity can be changed via configuration register settings.
1
1
DESCRIPTION
ALELO
VIS
(PU)
VIS
During EEPROM Emulation mode, if the default
PDI selection is set to HBI Multiplexed 1 Phase,
this strap is used to set the HBI ALE polarity until
the EEPROM configuration data has been loaded.
This pin indicates the address phase for multiplexed address modes. It is used to load both
address bytes in single phase multiplexed address
mode and the lower address byte in dual phase
multiplexed address mode.
Normally active low (address saved on rising
edge), the polarity can be changed via configuration register settings.
This pin indicates when the host bus cycle may be
finished.
This pin is tri-state when the device is not selected.
1
Wait /
Acknowledge
WAIT_ACK
VO8/
VOD8
Normally push-pull, the buffer type can be changed
to open-drain via configuration register settings.
Normally active low indicating wait, for push-pull
operation, the polarity can be changed via configuration register settings.
This pin is disabled when both bits are low.
1
Note 3-7
Endianess
Select
This pin provides the endianess control for demultiplexed address mode.
END_SEL
VIS
A high chooses big endian mode and a low
chooses little endian mode. This can be dynamically changed or held static.
Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset, EtherCAT reset, or RST# de-assertion. Refer to Section 3.3,
"Configuration Straps," on page 36 for further information.
DS00003422A-page 22
2020 Microchip Technology Inc.
LAN9254
TABLE 3-7:
NUM
PINS
1
SPI/SQI PINS
NAME
SYMBOL
SPI/SQI Slave
Chip Select
SCS#
BUFFER
TYPE
VIS
(PU)
DESCRIPTION
This pin is the SPI/SQI slave chip select input.
When low, the SPI/SQI slave is selected for SPI/
SQI transfers. When high, the SPI/SQI serial data
output(s) is(are) 3-stated.
When the Beckhoff SPI interface is used, the polarity of this signal is controlled via an internal register.
1
4
SPI/SQI Slave
Serial Clock
SCK
VIS
(PU)
This pin is the SPI/SQI slave serial clock input.
SPI/SQI Slave
Serial Data
Input/Output
SIO[3:0]
VIS/
VO8
(PU)
These pins are the SPI/SQI slave data input and
output for multiple bit I/O.
SPI Slave Serial
Data Input
SI
VIS
(PU)
This pin is the SPI slave serial data input. SI is
shared with SIO0.
SPI Slave Serial
Data Output
SO
VO8
(PU)
Note 3-8
EEPROM
Emulation SPI
Configuration
Strap 1
EEPROM
Emulation SPI
Configuration
Strap 0
This pin is the SPI slave serial data output. SO is
shared with SIO1.
This configuration strap, along with EE_EMUL_SPI0, EE_EMUL_SPI2, and EE_EMUL_SPI3, configures the operation of the Beckhoff SPI interface
during EEPROM Emulation mode.
EE_EMUL_SPI[1:0] configure the SPI mode.
EE_EMUL_SPI1
Note 3-9
VIS
(PU)
EE_EMUL_SPI1 is located on the SIO3 pin.
EE_EMUL_SPI[1:0]
00: SPI mode 0
01: SPI mode 1
10: SPI mode 2
11: SPI mode 3
EE_EMUL_SPI0
Note 3-9
VIS
(PU)
This configuration strap, along with EE_EMUL_SPI1, EE_EMUL_SPI2, and EE_EMUL_SPI3, configures the operation of the Beckhoff SPI interface
during EEPROM Emulation mode.
EE_EMUL_SPI[1:0] configure the SPI mode. Refer
to the EE_EMUL_SPI1 pin description for details.
EE_EMUL_SPI0 is located on the SIO2 pin.
2020 Microchip Technology Inc.
DS00003422A-page 23
LAN9254
TABLE 3-7:
NUM
PINS
SPI/SQI PINS (CONTINUED)
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
This pin indicates when the host bus cycle may be
finished.
This pin is tri-state when the device is not selected.
Wait /
Acknowledge
WAIT_ACK
VO8/
VOD8
Normally push-pull, the buffer type can be changed
to open-drain via configuration register settings.
Normally active low indicating wait, for push-pull
operation, the polarity can be changed via configuration register settings.
This pin is disabled when both bits are low.
When the Beckhoff SPI interface is used, this pin is
not used and is disabled.
1
EEPROM
Emulation SPI
Configuration
Strap 3
This configuration strap, along with EE_EMUL_SPI0, EE_EMUL_SPI1, and EE_EMUL_SPI2, configures the operation of the Beckhoff SPI interface
during EEPROM Emulation mode. EE_EMUL_SPI3 configures the Data Out sample mode.
EE_EMUL_SPI3
Note 3-9
VIS
(PD)
0: Normal Data Out sample
(SPI_DO and SPI_DI are sampled at the same
SPI_CLK edge)
1: Late Data Out sample
(SPI_DO and SPI_DI are sampled at different
SPI_CLK edges)
Note 3-8
Although this pin is an output for SPI instructions, it includes a pull-up, since it is actually SIO bit 1.
Note 3-9
Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset, EtherCAT reset, or RST# de-assertion. Refer to Section 3.3,
"Configuration Straps," on page 36 for further information.
DS00003422A-page 24
2020 Microchip Technology Inc.
LAN9254
TABLE 3-8:
NUM
PINS
ETHERCAT DISTRIBUTED CLOCK PINS
NAME
2
Sync
SYMBOL
BUFFER
TYPE
SYNC1
SYNC0
VO8/
VOD8/
VOS8
DESCRIPTION
These pins are the Distributed Clock Sync (OUT)
signals.
Note:
These signals are not driven (high
impedance) until the EEPROM is loaded.
These pins are the Distributed Clock Latch (IN) signals.
Note:
2
Latch
(See
Note)
TABLE 3-9:
NUM
PINS
LATCH1
LATCH0
VIS
ETHERCAT DIGITAL I/O AND GPIO PINS
NAME
General Purpose Input
SYMBOL
GPI[15:0]
BUFFER
TYPE
DESCRIPTION
VIS
These pins are the general purpose inputs and are
directly mapped into the General Purpose Input
Register. Consistency of the general purpose
inputs is not provided.
16
General Purpose Output
32
Digital I/O
GPO[15:0]
DIGIO[31:0]
VO8/
VOD8
VIS/
VO8
1
Output Valid
OUTVALID
VO8
1
Latch In
LATCH_IN
VIS
1
Normally shared with the SYNC0/SYNC1
functions, these signals are mapped onto
alternate pins in some device
configurations when the SYNC function is
enabled. Refer to Section 11.2.1, SYNC/
LATCH Pin Multiplexing for additional
information.
Watchdog
Trigger
2020 Microchip Technology Inc.
WD_TRIG
VO8
These pins are the general purpose outputs and
reflect the values of the General Purpose Output
Register without watchdog protection.
Note:
These signals are not driven (high
impedance) until the EEPROM is loaded.
These pins are the Input/Output or Bidirectional
data.
Note:
These signals are not driven (high
impedance) until the EEPROM is loaded.
This pin indicates that the outputs are valid and can
be captured into external registers.
Note:
This signal is not driven (high impedance)
until the EEPROM is loaded.
This pin is the external data latch signal. The input
data is sampled each time a rising edge of
LATCH_IN is recognized.
This pin is the SyncManager Watchdog Trigger output.
Note:
This signal is not driven (high impedance)
until the EEPROM is loaded.
DS00003422A-page 25
LAN9254
TABLE 3-9:
NUM
PINS
1
1
ETHERCAT DIGITAL I/O AND GPIO PINS (CONTINUED)
NAME
Watchdog State
SYMBOL
WD_STATE
SOF
Start of Frame
BUFFER
TYPE
VO8
VO8
1
End of Frame
EOF
VO8
1
Output Enable
OE_EXT
VIS
TABLE 3-10:
NUM
PINS
DESCRIPTION
This pin is the SyncManager Watchdog State output. A 0 indicates the watchdog has expired.
Note:
This signal is not driven (high impedance)
until the EEPROM is loaded.
This pin is the Start of Frame output and indicates
the start of an Ethernet/EtherCAT frame.
Note:
This signal is not driven (high impedance)
until the EEPROM is loaded.
This pin is the End of Frame output and indicates
the end of an Ethernet/EtherCAT frame.
Note:
This signal is not driven (high impedance)
until the EEPROM is loaded.
This pin is the Output Enable input. When low, it
clears the output data.
EEPROM PINS
NAME
EEPROM I2C
Serial Data
Input/Output
SYMBOL
EESDA
BUFFER
TYPE
VIS/
VOD8
DS00003422A-page 26
EE_EMUL1
Note 3-10
When the device is accessing an external
EEPROM, this pin is the I2C serial data input/opendrain output.
Note:
This pin must be pulled-up by an external
resistor at all times.
This strap, along with EE_EMUL2, configures the
value of the EEPROM emulation hard-strap. Either
low enables emulation.
1
EEPROM
Emulation
Configuration
Strap 1
DESCRIPTION
VIS
This strap, along with EE_EMUL0 and EE_EMUL2
configures the default PDI selection during
EEPROM Emulation mode. Refer to the
EE_EMUL2 pin description for details.
2020 Microchip Technology Inc.
LAN9254
TABLE 3-10:
NUM
PINS
EEPROM PINS (CONTINUED)
NAME
EEPROM I2C
Serial Clock
SYMBOL
EESCL
BUFFER
TYPE
VIS/
VOD8
DESCRIPTION
When the device is accessing an external
EEPROM this pin is the I2C clock input/open-drain
output.
Note:
If an EEPROM is used, this pin must be
pulled-up by an external resistor at all
times.
This strap, along with EE_EMUL1, configures the
value of the EEPROM emulation hard-strap. Either
low enables emulation.
This strap, along with EE_EMUL0 and EE_EMUL1
configures the default PDI selection during
EEPROM Emulation mode.
1
EEPROM
Emulation
Configuration
Strap 2
Note 3-10
EE_EMUL2
Note 3-10
VIS
EE_EMUL[2:0]
000: SPI
001: HBI Demultiplexed 16-bit EtherCAT Direct Mapped
010: HBI Multiplexed 1 Phase 16-bit EtherCAT Direct Mapped
011: HBI Multiplexed 2 Phase 16-bit EtherCAT Direct Mapped
100: SPI EtherCAT Direct Mapped
101: Beckhoff SPI Mode
110: N/A (EEPROM is enabled)
111: N/A (EEPROM is enabled)
Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset, EtherCAT reset, or RST# de-assertion. Refer to Section 3.3,
"Configuration Straps," on page 36 for further information.
2020 Microchip Technology Inc.
DS00003422A-page 27
LAN9254
TABLE 3-11:
NUM
PINS
LED & CONFIGURATION STRAP PINS
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
This pin is the ERR LED output and is controlled
either by the ESC or the local MCU.
ERR LED
ERRLED
OD12/
OS12
This pin is configured to be an open-drain/opensource output. The default choice of open-drain vs.
open-source as well as the default polarity of this
pin depends upon the strap value sampled at reset.
This pin is enabled as an output via bit 14 - ERR
LED Enable of the ASIC Configuration Register
(0x0142:0x0143). If active low, this pin is forced
enabled in the event of an EEPROM loading error.
For 2 port mode (as selected by CHIP_MODE1),
this strap configures the default of the ANEG Disable PHY B and AMDIX Disable PHY B fields in the
Hardware Configuration Register (HW_CFG) and
sets the PHY to fixed 100Mbps full-duplex operation by default.
0: Auto-negotiation and AMDIX enabled by default
1: Auto-negotiation and AMDIX disabled (fixed
100Mbps full-duplex) by default
1
100Mbps Full
Duplex
Configuration
Strap B
In 3 port mode (as selected by CHIP_MODE1), this
strap is moved to the MII_TXD1 pin.
100FD_B
/
LEDPOL4
Note 3-12
IS
(PD)
Note:
If an external pull-up is used, it should
be connected to VDD33.
Note:
If ERRLED is used as the PME output
(with potential to be a wired-OR’d
shared signal), careful consideration
must be paid to the strap value. Host
software might need to correct the strap
results via the AMDIX Disable PHY B
and ANEG Disable PHY B bits in the
Hardware
Configuration
Register
(HW_CFG) as well as reconfiguring
PHY B.
Since this pin is shared with a configuration strap,
the default polarity of the ERRLED pin is determined during strap loading.
LED 4 Polarity
Configuration
Strap
If the strap value is 0, the LED is set as active high
by default, since it is assumed that if an LED is
present it is used as the pull-down. See Note 3-11.
If the strap value is 1, the LED is set as active low
by default, since it is assumed that an LED to
VDD33 is used as the pull-up.
DS00003422A-page 28
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LAN9254
TABLE 3-11:
NUM
PINS
LED & CONFIGURATION STRAP PINS (CONTINUED)
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
This pin is the RUN LED output and is controlled by
the AL Status Register.
RUNLED
RUN LED
VOD12/
VOS12
This pin is configured to be open-drain/open-source
output. The default choice of open-drain vs. opensource as well as the default polarity of this pin
depends upon the strap value sampled at reset.
This pin is the STATE_RUN LED output and is
equal to the RUN LED combined with the negation
of the ERR LED. It can be used to control the RUN
side of a bi-color RUN/ERR LED.
STATE_RUN
LED
STATE_RUNLED
VOD12/
VOS12
This pin is configured to be open-drain/open-source
output. The default choice of open-drain vs. opensource as well as the default polarity of this pin
depends upon the strap value sampled at reset.
The selection between RUN and STATE_RUN is
via bit 6 - STATE_RUN LED enable, of the ASIC
Configuration Register (0x0142:0x0143).
1
This strap configures the size of the EEPROM.
EEPROM Size
Configuration
Strap
EEPROM
Emulation
Configuration
Strap 0
LED 3 Polarity
Configuration
Strap
0: Selects 1K bits (128 x 8) through 16K bits
(2K x 8).
1: 32K bits (4K x 8) through 4Mbits (512K x 8).
E2PSIZE
/
EE_EMUL0
/
LEDPOL3
Note 3-12
VIS
(PU)
This strap, along with EE_EMUL1 and EE_EMUL2
configures the default PDI selection during
EEPROM Emulation mode. Refer to the
EE_EMUL2 pin description for details.
Since this pin is shared with a configuration strap,
the default polarity of the RUNLED / STATE_RUNLED pin is determined during strap loading.
If the strap value is 0, the LED is set as active high
be default, since it is assumed that an LED to
ground is used as the pull-down. See Note 3-11.
If the strap value is 1, the LED is set as active low
by default, since it is assumed that an LED to
VDDIO is used as the pull-up.
2020 Microchip Technology Inc.
DS00003422A-page 29
LAN9254
TABLE 3-11:
NUM
PINS
LED & CONFIGURATION STRAP PINS (CONTINUED)
NAME
Link / Activity
LED Port 2
SYMBOL
LINKACTLED2
BUFFER
TYPE
VOD12/
VOS12
DESCRIPTION
This pin is the Link/Activity LED output (off=no link,
on=link without activity, blinking=link and activity)
for port 2.
This pin is configured to be open-drain/open-source
output. The default choice of open-drain vs. opensource as well as the default polarity of this pin
depends upon the strap value sampled at reset.
This strap configures the polarity of the MII_LINK
pin.
1
MII Port Link
Polarity
LED 2 Polarity
Configuration
Strap
0: MII_LINK low indicates a 100 Mbit/s FullDuplex link is established.
1: MII_LINK high indicates a 100 Mbit/s FullDuplex link is established.
MII_LINKPOL
/
LEDPOL2
Note 3-12
VIS
(PU)
Since this pin is shared with a configuration strap,
the default polarity of the LINKACTLED2 pin is
determined during strap loading.
If the strap value is 0, the LED is set as active high
by default, since it is assumed that an LED to
ground is used as the pull-down. See Note 3-11.
If the strap value is 1, the LED is set as active low
by default, since it is assumed that an LED to
VDDIO is used as the pull-up.
DS00003422A-page 30
2020 Microchip Technology Inc.
LAN9254
TABLE 3-11:
NUM
PINS
LED & CONFIGURATION STRAP PINS (CONTINUED)
NAME
Link / Activity
LED Port 1
SYMBOL
LINKACTLED1
BUFFER
TYPE
VOD12/
VOS12
DESCRIPTION
This pin is the Link/Activity LED output (off=no link,
on=link without activity, blinking=link and activity)
for port 1.
This pin is configured to be open-drain/open-source
output. The default choice of open-drain vs. opensource as well as the default polarity of this pin
depends upon the strap value sampled at reset.
This strap, along with CHIP_MODE0, configures
the value of the EtherCAT Chip Mode:
1
Chip Mode
Strap 1
CHIP_MODE1
/
LEDPOL1
Note 3-12
LED 1 Polarity
Configuration
Strap
VIS
(PU)
CHIP_MODE[1:0]
0X: 2-Port Mode. Ports 0 and 1 are connected to
the internal PHYs A and B.
10: 3-Port Downstream Mode. Ports 0 and 1 are
connected to internal PHYs A and B. Port 2 is connected to the external MII pins.
11: 3-Port Upstream Mode. Ports 2 and 1 are connected to internal PHYs A and B. Port 0 is connected to the external MII pins.
Since this pin is shared with a configuration strap,
the default polarity of the LINKACTLED1 pin is
determined during strap loading.
If the strap value is 0, the LED is set as active high
by default, since it is assumed that an LED to
ground is used as the pull-down. See Note 3-11
If the strap value is 1, the LED is set as active low
by default, since it is assumed that an LED to
VDDIO is used as the pull-up.
2020 Microchip Technology Inc.
DS00003422A-page 31
LAN9254
TABLE 3-11:
NUM
PINS
LED & CONFIGURATION STRAP PINS (CONTINUED)
NAME
Link / Activity
LED Port 0
SYMBOL
LINKACTLED0
BUFFER
TYPE
VOD12/
VOS12
This pin is the Link/Activity LED output (off=no link,
on=link without activity, blinking=link and activity)
for port 0.
This pin is configured to be open-drain/open-source
output. The default choice of open-drain vs. opensource as well as the default polarity of this pin
depends upon the strap value sampled at reset.
This strap, along with CHIP_MODE1, configures
the value of the Chip Mode hard-strap. Refer to the
CHIP_MODE1 description for details on the chip
mode strap settings.
Chip Mode
Strap 0
Note:
CHIP_MODE0
/
100FD_A
/
LEDPOL0
Note 3-12
CHIP_MODE0 is unused in 2 port
mode.
For 2 port mode (as selected by CHIP_MODE1),
this strap configures the default of the ANEG Disable PHY A and AMDIX Disable PHY A fields in the
Hardware Configuration Register (HW_CFG) and
sets the PHY to fixed 100Mbps full-duplex operation by default.
1
100Mbps Full
Duplex
Configuration
Strap A
DESCRIPTION
VIS
(PU)
0: Auto-negotiation and AMDIX enabled by default
1: Auto-negotiation and AMDIX disabled (fixed
100Mbps full-duplex) by default
In 3 port mode (as selected by CHIP_MODE1), this
strap is moved to the MII_TXD0 pin.
Since this pin is shared with a configuration strap,
the default polarity of the LINKACTLED0 pin is
determined during strap loading.
LED 0 Polarity
Configuration
Strap
If the strap value is 0, the LED is set as active high
by default, since it is assumed that an LED to
ground is used as the pull-down. See Note 3-11.
If the strap value is 1, the LED is set as active low
by default, since it is assumed that an LED to
VDDIO is used as the pull-up.
Note 3-11
When using a LED as a pull-down strap, a external supplemental pull-down is needed to ensure a
valid low level.
Note 3-12
Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset, EtherCAT reset, or RST# de-assertion. Refer to Section 3.3,
"Configuration Straps," on page 36 for further information.
DS00003422A-page 32
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LAN9254
TABLE 3-12:
MISCELLANEOUS PINS
NUM
PINS
NAME
SYMBOL
1
Interrupt Output
IRQ
VO8/
VOD8
Interrupt request output. The polarity, source and
buffer type of this signal is programmable via configuration register settings.
0
Power Management Event
Output
PME
VO8/
VOD8
When programmed accordingly, this signal is
asserted upon detection of a wakeup event. The
polarity and buffer type of this signal is programmable via an internal register.
(See
Note)
1
System Reset
Input
BUFFER
TYPE
O8/
OD8
(see note)
RST#
VIS/
VOD8
(PU)
DESCRIPTION
Refer to the Power Management section for additional information on the power management features.
Note:
Optionally enabled, this pin may be
mapped onto several other pins via an
internal register.
Note:
When mapped into the ERRLED pin,
this signal is in the VDD33 voltage
domain and has an O8/OD8 buffer type.
Note:
When mapped onto the ERRLED pin, in
the event of an EEPROM loading error,
the ERRLED function is forced enabled
and false PME events might occur.
As an input, this active low signal allows external
hardware to reset the device. The device also contains an internal power-on reset circuit. Thus this
signal may be left unconnected if an external hardware reset is not needed. When used, this signal
must adhere to the reset timing requirements as
detailed in the Operational Characteritics section.
As an output, this signal is driven low during POR
or in response to an EtherCAT reset command
sequence from the Master Controller or Host interface.
1
Regulator
Enable
REG_EN
AI
When tied to 3.3 V, the internal 1.2 V regulators are
enabled.
1
Test Mode
Select
TESTMODE
VIS
(PD)
This pin must be tied to VSS for proper operation.
1
Crystal Input
OSCI
ICLK
External 25 MHz crystal input. This signal can also
be over-driven by a single-ended clock oscillator.
When this method is used, OSCO should be left
unconnected.
Note:
2020 Microchip Technology Inc.
In clock daisy chaining configuration,
using the CLK_25 of the previous
devices as the input clock source, this
pin should be set to Schmitt trigger input
mode via the XTAL_MODE strap input.
DS00003422A-page 33
LAN9254
TABLE 3-12:
MISCELLANEOUS PINS (CONTINUED)
NUM
PINS
NAME
SYMBOL
BUFFER
TYPE
1
Crystal Output
OSCO
OCLK
Crystal Clock
Output
CLK_25
Crystal Clock
Output Enable
Configuration
Strap
CLK_25_EN
Note 3-14
Crystal Clock
Input Mode
Configuration
Strap
XTAL_MODE
Note 3-14
O8
AI
(see note)
DESCRIPTION
External 25 MHz crystal output.
25 MHz crystal output.
This multiple DC level strap enables the CLK_25
output and selects between the operation of a crystal oscillator amplifier or a Schmitt trigger input on
the OSCI pin.
A level below 0.8V disables the CLK_25 output and
selects the crystal oscillator amplifier.
A level of 1.5V enables the CLK_25 output and
selects the crystal oscillator amplifier.
A level above 2.2V enables the CLK_25 output and
selects the Schmitt trigger input.
1
Note:
If left floated during strap load, the pin
will be biased to VDD33/2. An external
voltage divider is not required.
If an external pull-up is used to set this
pin above 2.2V, it should be connected
to VDD33.
An external pull-down or connecting to
VSS may be used to set this pin to below
0.8V.
1
Crystal +1.2 V
Power Supply
OSCVDD12
P
Supplied by the on-chip regulator unless configured
for regulator off mode via the REG_EN pin. See
Note 3-13.
1
Crystal Ground
OSCVSS
P
Crystal ground.
Note 3-13
Refer to the Power Connections section, the device reference schematic, and the device LANCheck
schematic checklist for additional connection information.
Note 3-14
Configuration strap pins are identified by an underlined symbol name. Configuration strap values are
latched on power-on reset, EtherCAT reset, or RST# de-assertion. Refer to Section 3.3,
"Configuration Straps," on page 36 for further information.
DS00003422A-page 34
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LAN9254
TABLE 3-13:
NUM
PINS
JTAG PINS
NAME
SYMBOL
BUFFER
TYPE
1
JTAG Test Mux
Select
TMS
VIS
JTAG test mode select.
1
JTAG Test
Clock
TCK
VIS
JTAG test clock.
1
JTAG Test Data
Input
TDI
VIS
JTAG data input.
1
JTAG Test Data
Output
TDO
VO12
TABLE 3-14:
NUM
PINS
1
5
3
DESCRIPTION
JTAG data output.
CORE AND I/O POWER AND GROUND PINS
NAME
SYMBOL
BUFFER
TYPE
Regulator
+3.3 V Power
Supply
VDD33
P
+1.8 V to +3.3 V
Variable I/O
Power
VDDIO
+1.2 V Digital
Core Power
Supply
VDDCR
DESCRIPTION
+3.3 V power supply for internal regulators.
Note:
+3.3 V must be supplied to this pin even
if the internal regulators are disabled.
See Note 3-15.
P
+1.8 V to +3.3 V variable I/O power.
See Note 3-15.
P
Supplied by the on-chip regulator unless configured
for regulator off mode via the REG_EN pin.
1 µF and 470 pF decoupling capacitors in parallel to
ground should be used on pin 6 (the regulator output pin).
See Note 3-15.
1
Ground
VSS
P
Common ground. This exposed pad must be connected to the ground plane with a via array.
Note:
Note 3-15
The crystal oscillator has its own ground
pin OSCVSS.
Refer to the Power Connections section, the device reference schematic, and the device LANCheck
schematic checklist for additional connection information.
2020 Microchip Technology Inc.
DS00003422A-page 35
LAN9254
3.3
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined values. Configuration straps are latched upon Power-On Reset (POR), EtherCAT reset, or pin reset (RST#). Configuration straps are
identified by an underlined symbol name and are defined throughout Section 3.2, "Pin Descriptions," on page 16.
Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the
internal resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be
overridden by the addition of an external resistor.
Note:
The system designer must guarantee that configuration strap pins meet the timing requirements specified
in Section 17.6.3, "Reset and Configuration Strap Timing". If configuration strap pins are not at the correct
voltage level prior to being latched, the device may capture incorrect strap values.
DS00003422A-page 36
2020 Microchip Technology Inc.
LAN9254
4.0
POWER CONNECTIONS
Figure 4-1 and Figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respectively. Refer to the device reference schematic and the device LANCheck schematic checklist for additional information.
Section 4.1 provides additional information on the devices internal voltage regulators.
FIGURE 4-1:
POWER CONNECTIONS - REGULATORS ENABLED
+1.8 V to
+3.3 V
VDDIO
IO Pads
VDDIO
VDDCR
VDDCR
VDDIO
VDDIO
VDDIO
Core Logic &
PHY digital
+3.3 V
VDD33
Internal 1.2 V Core
Regulator
+1.2 V
(OUT)
+3.3 V
(IN)
VDDCR
(Pin 6)
enable
470 pF
REG_EN
Internal 1.2 V Oscillator
Regulator
+1.2 V
(OUT)
+3.3 V
(IN)
+3.3 V
enable
1.0 µF
0.1 ESR
OSCVDD12
VSS
Crystal Oscillator
optional 2.5V
magnetics
operation
VSS
+2.5 V
OSCVSS
CLK_25
To PHY1
Magnetics
optional 2.5V
magnetics
operation
VDD33TXRX1
Ethernet PHY 1
Analog
VDD33BIAS
Ethernet Master
Bias
VDD33TXRX2
Ethernet PHY 2
Analog
VDD12TX1
+2.5 V
To PHY2
Magnetics
VSS
(exposed pad)
VDD12TX2
PLL
Note: Bypass and bulk caps as needed for PCB
2020 Microchip Technology Inc.
DS00003422A-page 37
LAN9254
FIGURE 4-2:
POWER CONNECTIONS - REGULATORS DISABLED
+1.2 V
+1.8 V to
+3.3 V
VDDIO
IO Pads
VDDIO
VDDCR
VDDCR
VDDIO
VDDIO
VDDIO
Core Logic &
PHY digital
+3.3 V
VDD33
Internal 1.2 V Core
Regulator
+1.2 V
(OUT)
+3.3 V
(IN)
VDDCR
(Pin 6)
enable
REG_EN
Internal 1.2 V Oscillator
Regulator
+1.2 V
(OUT)
+3.3 V
(IN)
enable
+3.3 V
OSCVDD12
VSS
Crystal Oscillator
optional 2.5V
magnetics
operation
VSS
+2.5 V
OSCVSS
CLK_25
To PHY1
Magnetics
optional 2.5V
magnetics
operation
VDD33TXRX1
Ethernet PHY 1
Analog
VDD33BIAS
Ethernet Master
Bias
VDD33TXRX2
Ethernet PHY 2
Analog
VDD12TX1
+2.5 V
To PHY2
Magnetics
VSS
(exposed pad)
VDD12TX2
PLL
Note: Bypass and bulk caps as needed for PCB
DS00003422A-page 38
2020 Microchip Technology Inc.
LAN9254
4.1
Internal Voltage Regulators
The device contains two internal 1.2 V regulators:
• 1.2 V Core Regulator
• 1.2 V Crystal Oscillator Regulator
4.1.1
1.2 V CORE REGULATOR
The core regulator supplies 1.2 V volts to the main core digital logic, the I/O pads, and the PHY’s digital logic and can
be used to supply the 1.2 V power to the PHY analog sections (via an external connection).
When the REG_EN input pin is connected to 3.3 V, the core regulator is enabled and receives 3.3 V on the VDD33 pin.
A 1.0 uF 0.1 ESR capacitor must be connected to the VDDCR pin associated with the regulator.
When the REG_EN input pin is connected to VSS, the core regulator is disabled. However, 3.3 V must still be supplied
to the VDD33 pin. The 1.2 V core voltage must then be externally input into the VDDCR pins.
4.1.2
1.2 V CRYSTAL OSCILLATOR REGULATOR
The crystal oscillator regulator supplies 1.2 V volts to the crystal oscillator and the CLK_25 pin. When the REG_EN input
pin is connected to 3.3 V, the crystal oscillator regulator is enabled and receives 3.3 V on the VDD33 pin. An external
capacitor is not required.
When the REG_EN input pin is connected to VSS, the crystal oscillator regulator is disabled. However, 3.3 V must still
be supplied to the VDD33 pin. The 1.2 V crystal oscillator voltage must then be externally input into the OSCVDD12 pin.
2020 Microchip Technology Inc.
DS00003422A-page 39
LAN9254
5.0
REGISTER MAP
This chapter details the device register map and summarizes the various directly addressable System Control and Status Registers (CSRs). Detailed descriptions of the System CSRs are provided in the chapters corresponding to their
function. Additional indirectly addressable registers are available in the various sub-blocks of the device. These registers are also detailed in their corresponding chapters.
Directly Addressable Registers
• Section 11.15, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 305
• EtherCAT Core Control and Status Registers and Process RAM while EtherCAT Direct Mapped mode
• Section 5.1, "System Control and Status Registers," on page 42
Indirectly Addressable Registers
• Section 10.2.18, "PHY Registers," on page 225
• Section 11.16, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 314
Figure 5-1 contains an overall base register memory map of the device. This memory map is not drawn to scale, and
should be used for general reference only. Table 5-1 provides a summary of all directly addressable CSRs and their
corresponding addresses.
There are two address modes. By default, the register mapping is compatible to the LAN9252 with the EtherCAT Core
Control and Status Registers and Process RAM accessed via a command and data register structure. Once enabled,
EtherCAT Direct Mapped mode maps the EtherCAT Core Control and Status Registers and EtherCAT Core Process
RAM to there native addresses (byte address 0h to FFFh and 1000h to 2FFFh respectively) while remapping the System
Control and Status Registers starting at a base offset of 3000h.
Note:
The Section 11.15, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on
page 305 (including the EtherCAT Process RAM Read and Write Data FIFO) are not used and are not
accessible during EtherCAT Direct Mapped mode.
Note:
Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 7.
Not all device registers are memory mapped or directly addressable. For details on the accessibility of the
various device registers, refer the register sub-sections listed above.
DS00003422A-page 40
2020 Microchip Technology Inc.
LAN9254
FIGURE 5-1:
REGISTER ADDRESS MAP
Compatibility Mode
EtherCAT Direct Mapped Mode
3FFFh
3FFh
System CSRs
314h
EtherCAT
300h
not mapped
3040h
2FFFh
EtherCAT Core Process RAM
Test
1000h
0FFFh
09Ch
08Ch
GP Timer and Free Run Counter
05Ch
054h
Interrupts
EtherCAT Core CSRs
03Ch
EtherCAT Process RAM Write FIFO
020h
01Ch
EtherCAT Process RAM Read FIFO
000h
0000h
Not all registers are shown
2020 Microchip Technology Inc.
DS00003422A-page 41
LAN9254
5.1
System Control and Status Registers
The System CSRs are directly addressable memory mapped registers with a base address offset range of 050h to 314h
or from 3050h to 31FCh while in EtherCAT Direct Mapped mode. These registers are addressable by the Host via the
Host Bus Interface (HBI) or SPI/SQI. For more information on the various device modes and their corresponding
address configurations, see Section 2.0, "General Description," on page 8.
Table 5-1 lists the System CSRs and their corresponding addresses in order. All system CSRs are reset to their default
value on the assertion of a chip-level reset.
The System CSRs can be divided into the following sub-categories. Each of these sub-categories is located in the corresponding chapter and contains the System CSR descriptions of the associated registers. The register descriptions
are categorized as follows:
•
•
•
•
•
•
Section 6.2.3, "Reset Registers," on page 50
Section 6.3.5, "Power Management Registers," on page 56
Section 7.3, "Interrupt Registers," on page 63
Section 11.15, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 305
Section 15.1, "Miscellaneous System Configuration & Status Registers," on page 397
Section 14.3, "General Purpose Timer and Free-Running Clock Registers," on page 394
Note:
Unlisted registers are reserved for future use.
TABLE 5-1:
SYSTEM CONTROL AND STATUS REGISTERS
Address
EtherCAT
Direct
Mapped
Mode
000h-01Ch
N/A
EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA)
020h-03Ch
N/A
EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA)
050h
3050h
Chip ID and Revision (ID_REV)
054h
3054h
Interrupt Configuration Register (IRQ_CFG)
Register Name (Symbol)
058h
3058h
Interrupt Status Register (INT_STS)
05Ch
305Ch
Interrupt Enable Register (INT_EN)
064h
3064h
Byte Order Test Register (BYTE_TEST)
074h
3074h
Hardware Configuration Register (HW_CFG)
084h
3084h
Power Management Control Register (PMT_CTRL)
08Ch
308Ch
General Purpose Timer Configuration Register (GPT_CFG)
090h
3090h
General Purpose Timer Count Register (GPT_CNT)
09Ch
309Ch
Free Running 25MHz Counter Register (FREE_RUN)
1F8h
31F8h
Reset Control Register (RESET_CTL)
EtherCAT Registers
300h
N/A
EtherCAT CSR Interface Data Register (ECAT_CSR_DATA)
304h
N/A
EtherCAT CSR Interface Command Register (ECAT_CSR_CMD)
308h
N/A
EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN)
30Ch
N/A
EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD)
310h
N/A
EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN)
314h
N/A
EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD)
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LAN9254
5.2
Special Restrictions on Back-to-Back Cycles
5.2.1
BACK-TO-BACK WRITE-READ CYCLES
It is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. These
restrictions concern reading registers after any write cycle that may affect the register. In all cases there is a delay
between writing to a register and the new value becoming available to be read. In other cases, there is a delay between
writing to a register and the subsequent side effect on other registers.
In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established.
These periods are specified in Table 5-2. The host processor is required to wait the specified period of time after writing
to the indicated register before reading the resource specified in the table. Note that the required wait period is dependent upon the register being read after the write.
Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that
the minimum write-to-read timing restriction is met. Table 5-2 shows the number of dummy reads that are required
before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum cycle
timing of 45ns. For microprocessors with slower busses the number of reads may be reduced as long as the total time
is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not
required as long as the minimum time period is met.
Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient
time between writes and read. It is required of the system design and register access mechanisms to ensure the proper
timing. For example, a write and read to the same register may occur faster than a write and read to different registers.
For 8 and 16-bit write cycles, the wait time for the back-to-back write-read operation applies only to the writing of the
last BYTE or WORD of the register, which completes a single DWORD transfer.
For Indexed Address mode HBI operation, the wait time for the back-to-back write-read operation applies only to access
to the internal registers and FIFOs. It does not apply to the Host Bus Interface Index Registers or the Host Bus Interface
Configuration Register.
TABLE 5-2:
READ AFTER WRITE TIMING RULES
After Writing...
wait for this many
nanoseconds...
or Perform this many
Reads of BYTE_TEST…
(assuming Tcyc of 45ns)
any register
45
1
the same register
or any other register affected
by the write
Interrupt Configuration Register (IRQ_CFG)
60
2
Interrupt Configuration Register (IRQ_CFG)
Interrupt Enable Register
(INT_EN)
90
2
Interrupt Configuration Register (IRQ_CFG)
60
2
Interrupt Status Register
(INT_STS)
180
4
Interrupt Configuration Register (IRQ_CFG)
170
4
Interrupt Status Register
(INT_STS)
165
4
Power Management Control
Register (PMT_CTRL)
170
4
Interrupt Configuration Register (IRQ_CFG)
160
4
Interrupt Status Register
(INT_STS)
Interrupt Status Register
(INT_STS)
Power Management Control
Register (PMT_CTRL)
2020 Microchip Technology Inc.
before reading...
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TABLE 5-2:
READ AFTER WRITE TIMING RULES (CONTINUED)
After Writing...
General Purpose Timer Configuration Register
(GPT_CFG)
EtherCAT Process RAM Write
Data FIFO
(ECAT_PRAM_WR_DATA)
5.2.2
wait for this many
nanoseconds...
or Perform this many
Reads of BYTE_TEST…
(assuming Tcyc of 45ns)
55
2
General Purpose Timer Configuration Register
(GPT_CFG)
170
4
General Purpose Timer Count
Register (GPT_CNT)
50
2
EtherCAT Process RAM Write
Command Register
(ECAT_PRAM_WR_CMD)
before reading...
BACK-TO-BACK READ CYCLES
There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific
registers after reading a resource that has side effects. In many cases there is a delay between reading the device, and
the subsequent indication of the expected change in the control and status register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been established. These periods are specified in Table 5-3. The host processor is required to wait the specified period of time
between read operations of specific combinations of resources. The wait period is dependent upon the combination of
registers being read.
Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that
the minimum wait time restriction is met. Table 5-3 below also shows the number of dummy reads that are required for
back-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc
(45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal
to, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as
the minimum time period is met.
Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient
time between reads. It is required of the system design and register access mechanisms to ensure the proper timing.
For example, multiple reads to the same register may occur faster than reads to different registers.
For 8 and 16-bit read cycles, the wait time for the back-to-back read operation is required only after the reading of the
last BYTE or WORD of the register, which completes a single DWORD transfer. There is no wait requirement between
the BYTE or WORD accesses within the DWORD transfer.
TABLE 5-3:
READ AFTER READ TIMING RULES
After reading...
EtherCAT Process RAM Read
Data FIFO
(ECAT_PRAM_RD_DATA)
DS00003422A-page 44
wait for this many
nanoseconds...
or Perform this many
Reads of BYTE_TEST…
(assuming Tcyc of 45ns)
50
2
before reading...
EtherCAT Process RAM Read
Command Register
(ECAT_PRAM_RD_CMD)
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6.0
CLOCKS, RESETS, AND POWER MANAGEMENT
6.1
Clocks
The device provides generation of all system clocks as required by the various sub-modules of the device. The clocking
sub-system is comprised of the following:
• Crystal Oscillator
• PHY PLL
6.1.1
CRYSTAL OSCILLATOR
The device requires a fixed-frequency 25 MHz clock source for use by the internal clock oscillator and PLL. This is typically provided by attaching a 25 MHz crystal to the OSCI and OSCO pins as specified in Section 17.7, "Clock Circuit,"
on page 416. Optionally, this clock can be provided by driving the OSCI input pin with a single-ended 25 MHz clock
source. If a single-ended source is selected, the clock input must run continuously for normal device operation.
Application Note:In clock daisy chaining configuration, using the CLK_25 of the previous devices as the input clock
source, this pin should be set to Schmitt trigger input mode via the XTAL_MODE strap input.
Power savings modes allow for the oscillator or external clock input to be halted. The crystal oscillator can be disabled
as describe in Section 6.3.4, "Chip Level Power Management," on page 54.
For system level verification, the crystal oscillator output can be enabled onto the IRQ pin. See Section 7.2.7, "Clock
Output Test Mode," on page 63.
Power for the crystal oscillator is provided by a dedicated regulator or separate input pin. See Section 4.1.2, "1.2 V Crystal Oscillator Regulator," on page 39.
Note:
6.1.1.1
Crystal specifications are provided in Table 17-12, “Crystal Specifications,” on page 416.
Crystal Clock Output Pin
The crystal clock may be output onto the dedicated CLK_25 pin for use as the reference clock to another device. This
pin is enabled when the CLK_25_EN is high.
6.1.2
PHY PLL
The PHY module receives the 25 MHz reference clock and, in addition to its internal clock usage, outputs a main system
clock that is used to derive device sub-system clocks.
The PHY PLL can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 54. The PHY
PLL will be disabled only when requested and if the PHY ports are in a power down mode.
Power for PHY PLL is provided by an external input pin, usually sourced by the device’s 1.2V core regulator. See Section
4.0, "Power Connections," on page 37.
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6.2
Resets
The device provides multiple hardware and software reset sources, which allow varying levels of the device to be reset.
All resets can be categorized into three reset types as described in the following sections:
• Chip-Level Resets
- Power-On Reset (POR)
- RST# Pin Reset
- EtherCAT System Reset
• Multi-Module Resets
- DIGITAL RESET (DIGITAL_RST)
• Single-Module Resets
- Port A PHY Reset
- Port B PHY Reset
- EtherCAT Controller Reset
The device supports the use of configuration straps to allow automatic custom configurations of various device parameters. These configuration strap values are set upon de-assertion of all chip-level resets and can be used to easily set
the default parameters of the chip at power-on or pin (RST#) reset. Refer to Section 6.3, "Power Management," on
page 51 for detailed information on the usage of these straps.
Table 6-1 summarizes the effect of the various reset sources on the device. Refer to the following sections for detailed
information on each of these reset types.
TABLE 6-1:
RESET SOURCES AND AFFECTED DEVICE FUNCTIONALITY
Module/
Functionality
POR
25 MHz Oscillator
Voltage Regulators
EtherCAT Core
PHY A
PHY B
PHY Common
Voltage Supervision
PLL
SPI/SQI Slave
Host Bus Interface
Power Management
General Purpose Timer
Free Running Counter
System CSR
Config. Straps Latched
EEPROM Loader Run
Tristate Output Pins(5)
RST# Pin Driven Low
(1)
(2)
X
X
X
(3)
(3)
(3)
X
X
X
X
X
X
YES
YES
YES
YES
Note
1:
2:
3:
4:
5:
RST#
Pin
EtherCAT
System Reset
Digital
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
YES
YES
YES
X
X
X
X
X
X
YES
YES
YES
YES
X
X
X
X
X
X
NO(4)
YES
POR is performed by the XTAL voltage regulator, not at the system level
POR is performed internal to the voltage regulators
POR is performed internal to the PHY
Strap inputs are not re-latched
Only those output pins that are used for straps
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6.2.1
CHIP-LEVEL RESETS
A chip-level reset event activates all internal resets, effectively resetting the entire device. A chip-level reset is initiated
by assertion of any of the following input events:
• Power-On Reset (POR)
• RST# Pin Reset
• EtherCAT System Reset
Chip-level reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST).
The returned data will be invalid until the Host interface resets are complete. Once the returned data is the correct byte
ordering value, the Host interface resets have completed.
The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configuration Register (HW_CFG) or the Power Management Control Register (PMT_CTRL) until it is set. When set, the READY
bit indicates that the reset has completed and the device is ready to be accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal
resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY
bit is set.
A chip-level reset involves tuning of the variable output level pads, latching of configuration straps and generation of the
master reset.
CONFIGURATION STRAPS LATCHING
During POR, EtherCAT reset or RST# pin reset, the latches for the straps are open. Following the release of POR, EtherCAT reset or RST# pin reset, the latches for the straps are closed.
The CLK_25_EN and the XTAL_MODE configuration straps and the output enable, pull-up, and pull-down for the
CLK_25 pin are not controlled by the EtherCAT reset or the RST# pin reset; the latches for the straps are closed.
VARIABLE LEVEL I/O PAD TUNING
Following the release of the EtherCAT, POR or RST# pin resets, a 1 uS pulse (active low), is sent into the VO tuning
circuit. 2 uS later, the output pins are enabled. The 2 uS delay allows time for the variable output level pins to tune before
enabling the outputs and also provides input hold time for strap pins that are shared with output pins.
MASTER RESET AND CLOCK GENERATION RESET
Following the enabling of the output pins, the reset is synchronized to the main system clock to become the master
reset. Master reset is used to generate the local resets and to reset the clocks generation.
6.2.1.1
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to
the device. This event resets all circuitry within the device. Configuration straps are latched and EEPROM loading is
performed as a result of this reset. The POR is used to trigger the tuning of the Variable Level I/O Pads as well as a
chip-level reset.
The POR can also used as a system level reset. RST# becomes an open-drain output and is asserted for the POR time.
Its purpose is to perform a complete reset of the EtherCAT slave and/or to hold an external PHY in reset while the EtherCAT core is in reset. As an open-drain output, RST is intended to be wired OR’d into the system reset.
Note:
The Ethernet PHY should be connected to the RST# pin so that the PHY is held in reset until the EtherCAT
Slave is ready. Otherwise, the far end Link Partner would detect valid link signals from the PHY and would
“open” its port assuming that the local EtherCAT Slave was ready.
The RST# pin is not driven until all voltages are operational. External, system level solutions are necessary
if the system needs to be held in reset during power ramp-up.
Following valid voltage levels, a POR reset typically takes approximately 21 ms.
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6.2.1.2
RST# Pin Reset
Driving the RST# input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this
reset input is optional, but when used, it must be driven for the period of time specified in Section 17.6.3, "Reset and
Configuration Strap Timing," on page 413. Configuration straps are latched, and EEPROM loading is performed as a
result of this reset.
A RST# pin reset typically takes approximately 1.3 ms.
Note:
The RST# pin is pulled-high internally. If unused, this signal can be left unconnected. Do not rely on internal
pull-up resistors to drive signals external to the device.
Please refer to Table 3-12, “Miscellaneous Pins,” on page 33 for a description of the RST# pin.
6.2.1.3
EtherCAT System Reset
An EtherCAT system reset, initiated by a special sequence of three independent and consecutive frames/commands,
is functionally identical to a RST# pin reset, except that during an EtherCAT system reset, the RST# pin becomes an
open-drain output and is asserted for the minimum required time of 80 ms.
The RST# is an open-drain output intended to be wired OR’d into the system reset.
Note:
6.2.2
The purpose of connecting the RST# pin into the system reset is to perform a complete reset of the EtherCAT slave. The EtherCAT master issues this reset in rare and extreme cases when the local microcontroller is seriously halted and can not be otherwise informed to reinitialize.
BLOCK-LEVEL RESETS
The block level resets contain an assortment of reset register bit inputs and generate resets for the various blocks. Block
level resets can affect one or multiple modules.
6.2.2.1
Multi-Module Resets
Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration straps are not latched
upon multi-module resets. A multi-module reset is initiated by assertion of the following:
• DIGITAL RESET (DIGITAL_RST)
Multi-module reset/configuration completion can be determined by first polling the Byte Order Test Register
(BYTE_TEST). The returned data will be invalid until the Host interface resets are complete. Once the returned data is
the correct byte ordering value, the Host interface resets have completed.
The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configuration Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bit
indicates that the reset has completed and the device is ready to be accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal
resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY
bit is set.
Note:
The digital reset does not reset register bits designated as NASR.
DIGITAL RESET (DIGITAL_RST)
A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register (RESET_CTL). A digital reset
will reset all device sub-modules except the Ethernet PHYs. EEPROM loading is performed following this reset. Configuration straps are not latched as a result of a digital reset.
A digital reset typically takes approximately 1.3 ms.
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6.2.2.2
Single-Module Resets
A single-module reset will reset only the specified module. Single-module resets do not latch the configuration straps.
A single-module reset is initiated by assertion of the following:
• Port A PHY Reset
• Port B PHY Reset
• EtherCAT Controller Reset
Port A PHY Reset
A Port A PHY reset is performed by setting the PHY_A_RST bit of the Reset Control Register (RESET_CTL) or the Soft
Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port A PHY reset,
the PHY_A_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this
reset.
Port A PHY reset completion can be determined by polling the PHY_A_RST bit in the Reset Control Register
(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.
Under normal conditions, the PHY_A_RST and Soft Reset bit will clear approximately 102 uS after the Port A PHY reset
occurrence.
Note:
When using the Soft Reset bit to reset the Port A PHY, register bits designated as NASR are not reset.
In addition to the methods above, the Port A PHY is automatically reset after returning from a PHY power-down mode.
This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to
Section 10.2.9, "PHY Power-Down Modes," on page 212 for additional information.
Refer to Section 10.2.11, "Resets," on page 216 for additional information on Port A PHY resets.
Port B PHY Reset
A Port B PHY reset is performed by setting the PHY_B_RST bit of the Reset Control Register (RESET_CTL) or the Soft
Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port B PHY reset,
the PHY_B_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this
reset.
Port B PHY reset completion can be determined by polling the PHY_B_RST bit in the Reset Control Register
(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.
Under normal conditions, the PHY_B_RST and Soft Reset bit will clear approximately 102 us after the Port B PHY reset
occurrence.
Note:
When using the Soft Reset bit to reset the Port B PHY, register bits designated as NASR are not reset.
In addition to the methods above, the Port B PHY is automatically reset after returning from a PHY power-down mode.
This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to
Section 10.2.9, "PHY Power-Down Modes," on page 212 for additional information.
Refer to Section 10.2.11, "Resets," on page 216 for additional information on Port B PHY resets.
EtherCAT Controller Reset
A compete device and system reset can be initiated by either the EtherCAT master or by the local host by writing the
value sequence of 0x52 (‘R’), 0x45 (‘E’) and 0x53 (‘S’) into the ESC Reset ECAT Register (for the master) or the ESC
Reset PDI Register (for the local host). This will trigger the reset described in Section 6.2.1.3, "EtherCAT System Reset".
A reset of just the EtherCAT Controller may be performed by setting the ETHERCAT_RST bit in the Reset Control Register (RESET_CTL).
This will reset the EtherCAT Core and its registers. It will also reset the EtherCAT CSR and Process Data RAM Access
logic described in Section 11.13, on page 297 and will reset the registers described in Section 11.15, "EtherCAT CSR
and Process Data RAM Access Registers (Directly Addressable)," on page 305.
Since the EtherCAT module will reconfigure the device from the EEPROM, the Host interfaces will be disabled until reset
is complete. Completion of the reset must be determined by using the methods described in Section 8.4.2.2, on page 78
for HBI and Section 9.2.1.1, on page 167 for SPI/SQI.
An EtherCAT Controller reset typically takes approximately 1.3 ms.
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6.2.3
6.2.3.1
RESET REGISTERS
Reset Control Register (RESET_CTL)
Offset:
1F8h / 31F8h
Size:
32 bits
This register contains software controlled resets.
Note:
This register can be read while the device is in the reset or not ready / power savings states without leaving
the host interface in an intermediate state. If the host interface is in a reset state, returned data may be
invalid.
It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.
Bits
Type
Default
RESERVED
RO
-
EtherCAT Reset (ETHERCAT_RST)
Setting this bit resets the EtherCAT core. When the EtherCAT core is
released from reset, this bit is automatically cleared. All writes to this bit are
ignored while this bit is set.
R/W
SC
0b
RESERVED
RO
-
2
Port B PHY Reset (PHY_B_RST)
Setting this bit resets the Port B PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port B PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
R/W
SC
0b
1
Port A PHY Reset (PHY_A_RST)
Setting this bit resets the Port A PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port A PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
R/W
SC
0b
0
Digital Reset (DIGITAL_RST)
Setting this bit resets the complete chip except the PLL, Port B PHY and Port
A PHY. All system CSRs are reset except for any NASR type bits. Any in
progress EEPROM commands are terminated.
R/W
SC
0b
31:7
6
5:3
Description
When the chip is released from reset, this bit is automatically cleared. All
writes to this bit are ignored while this bit is set.
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6.3
Power Management
The device supports several block and chip level power management features as well as wake-up event detection and
notification.
6.3.1
6.3.1.1
WAKE-UP EVENT DETECTION
PHY A & B Energy Detect
Energy Detect Power Down mode reduces PHY power consumption. In energy-detect power-down mode, the PHY will
resume from power-down when energy is seen on the cable (typically from link pulses) and set the ENERGYON interrupt bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
Refer to Section 10.2.9.2, "Energy Detect Power-Down," on page 212 for details on the operation and configuration of
the PHY energy-detect power-down mode.
Note:
If a carrier is present when Energy Detect Power Down is enabled, then detection will occur immediately.
If enabled, via the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY will generate an interrupt.
This interrupt is reflected in the Interrupt Status Register (INT_STS), bit 26 (PHY_INT_A) for PHY A and bit 27
(PHY_INT_B) for PHY B. The INT_STS register bits will trigger the IRQ interrupt output pin if enabled, as described in
Section 7.2.1, "Ethernet PHY Interrupts," on page 61.
The energy-detect PHY interrupts will also set the appropriate Energy-Detect / WoL Status Port A (ED_WOL_STS_A)
or Energy-Detect / WoL Status Port B (ED_WOL_STS_B) bit of the Power Management Control Register (PMT_CTRL).
The Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) and Energy-Detect / WoL Enable Port B (ED_WOL_EN_B)
bits will enable the corresponding status bits as a PME event.
Note:
6.3.1.2
Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt
source in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).
PHY A & B Wake on LAN (WoL)
PHY A and B provide WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames.
When enabled, the PHY will detect WoL events and set the WoL interrupt bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). If enabled via the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY will generate an interrupt. This interrupt is reflected in the Interrupt Status Register
(INT_STS), bit 26 (PHY_INT_A) for PHY A and bit 27 (PHY_INT_B) for PHY B. The INT_STS register bits will trigger
the IRQ interrupt output pin if enabled, as described in Section 7.2.1, "Ethernet PHY Interrupts," on page 61.
Refer to Section 10.2.10, "Wake on LAN (WoL)," on page 213 for details on the operation and configuration of the PHY
WoL.
The WoL PHY interrupts will also set the appropriate Energy-Detect / WoL Status Port A (ED_WOL_STS_A) or EnergyDetect / WoL Status Port B (ED_WOL_STS_B) bit of the Power Management Control Register (PMT_CTRL). The
Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) and Energy-Detect / WoL Enable Port B (ED_WOL_EN_B) bits
enable the corresponding status bits as a PME event.
Note:
6.3.2
Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt
source in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).
WAKE-UP (PME) NOTIFICATION
A simplified diagram of the logic that controls the PME interrupt can be seen in Figure 6-1.
The PME module handles the latching of the PHY B Energy-Detect / WoL Status Port B (ED_WOL_STS_B) bit and the
PHY A Energy-Detect / WoL Status Port A (ED_WOL_STS_A) bit in the Power Management Control Register (PMT_CTRL).
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LAN9254
This module also masks the status bits with the corresponding enable bits (Energy-Detect / WoL Enable Port B
(ED_WOL_EN_B) and Energy-Detect / WoL Enable Port A (ED_WOL_EN_A)) and combines the results together to
generate the Power Management Interrupt Event (PME_INT) status bit in the Interrupt Status Register (INT_STS). The
PME_INT status bit is then masked with the Power Management Event Interrupt Enable (PME_INT_EN) bit and combined with the other interrupt sources to drive the IRQ output pin.
Note:
The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of
PME_INT_EN.
In addition to generating interrupt events, the PME event can also drive the PME output pin to indicate wake-up events
exclusively. The PME event is enabled with the PME Enable (PME_EN) bit in the Power Management Control Register
(PMT_CTRL), The PME output pin characteristics can be configured via the PME Buffer Type (PME_TYPE), PME Indication (PME_IND) and PME Polarity (PME_POL) bits of the Power Management Control Register (PMT_CTRL). These
bits allow the PME output pin to be open-drain, active high push-pull or active-low push-pull and configure the output to
be continuous, or pulse for 50 ms.
The PME output does not have a dedicated pin and is mapped onto several other pins as controlled by the PME Pin
Map (PME_PIN_SEL) field in the Power Management Control Register (PMT_CTRL), replacing the normal pin function.
Even when mapped, the PME output must be enabled, otherwise the mapped pin remains undriven. By default, PME
is not enabled or mapped.
Note:
Before PME is mapped onto another pin, the default state of that pin is that of the pin’s normal function.
The pin may or may not be driven and an internal or external pull-up or pull-down may be present. It is the
responsibility of the system designer to account for this, keeping in mind:
ERRLED: This is enabled via the EEPROM contents and should be set to disabled. In the event of an
EEPROM loading error, the ERRLED function is forced enabled and false PME events might occur.
ERRLED is also used as the 100FD_B configuration strap pin. If ERRLED is used as the PME output (with
potential to be wire-ORed shared signal), careful consideration must be paid to strap value. Host software
might need to correct the strap results via the AMDIX Disable PHY B and ANEG Disable PHY B bits in the
Hardware Configuration Register (HW_CFG) as well as reconfiguring PHY B. Also note that ERRLED is
in the VDD33 I/O voltage domain.
WAIT_ACK: This is enabled via the EEPROM contents and should be set to disabled.
SYNC0/LATCH0 / SYNC1/LATCH1: This is configured via the EEPROM contents. If set as SYNC0/SYNC1,
the driven value could be incorrect until the PME Pin Map (PME_PIN_SEL) value is set.
In system configurations where the PME output pin is shared among multiple devices (wired ORed), the
ED_WOL_STS_B and ED_WOL_STS_A bits within the PMT_CTRL register can be read to determine which device is
driving the PME signal.
When the PM_WAKE bit of the Power Management Control Register (PMT_CTRL) is set, the PME event will automatically wake up the system in certain chip level power modes, as described in Section 6.3.4.2, "Exiting Low Power
Modes," on page 55. This is done independent from the values of the PME_EN, PME_POL, PME_IND and PME_TYPE
register bits.
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FIGURE 6-1:
PME PIN AND PME INTERRUPT SIGNAL GENERATION
ED_WOL_EN_A (bit
14 ) of PMT_CTRL
register
INT8 (bit 8) o f
PHY_INTERRUP T_SOURCE_A register
PM_WAK E (bit 28) of
PMT_CTRL register
INT8_ MA SK (bit 8) of
PHY_ INTERRUPT_MASK_A re gister
ED_WOL_STS _A (bit 1 6)
of PMT_CTRL register
PME wake-up
INT7 (bit 7) o f
PHY_INTERRUP T_SOURCE_A register
PHYs A & B
INT7_ MA SK (bit 7) of
PHY_ INTERRUPT_MASK_A re gister
Other P HY Interrupts
ED_WOL_EN_B (bit
15 ) of PMT_CTRL
register
INT8 (bit 8) o f
PHY_INTERRUP T_SOURCE_B register
INT8_ MA SK (bit 8) of
PHY_ INTERRUPT_MASK_B re gister
ED_WOL_STS _B (bit 1 7)
of PMT_CTRL register
INT7 (bit 7) o f
PHY_INTERRUP T_SOURCE_B register
INT7_ MA SK (bit 7) of
PHY_ INTERRUPT_MASK_B re gister
Other P HY Interrupts
PME_INT (bit 17)
of INT_STS register
Other System
In terrupts
Polarit y &
Buffer Type
Logic
Denotes a level-triggered "sticky" status bit
PME_INT_EN (bit 17)
of INT_EN re gister
IRQ
IRQ_EN (bit 8)
of IRQ_CFG register
Power Management Control
Normal pin functions
PME_EN (bit 1) of
PMT_CTRL register
50ms
PME_IND (bit 3) of
PMT_CTRL register
PME
Device
pins
LOGIC
PME_POL (bit 2 ) of
PMT_CTRL register
PME_TYPE (bit 6) of
PMT_CTRL register
PME_PIN_SEL (bits 9:7)
of PMT_CTRL reg ister
6.3.3
BLOCK LEVEL POWER MANAGEMENT
The device supports software controlled clock disabling of various modules in order to reduce power consumption.
Note:
6.3.3.1
Disabling individual blocks does not automatically reset the block, it only places it into a static non-operational state in order to reduce the power consumption of the device. If a block reset is not performed before
re-enabling the block, then care must be taken to ensure that the block is in a state where it can be disabled
and then re-enabled.
Disabling The EtherCAT Core
The entire EtherCAT Core may be disabled by setting the ECAT_DIS bit in the Power Management Control Register
(PMT_CTRL). As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive times. A
write of a 0 will reset the count.
6.3.3.2
PHY Power Down
A PHY may be placed into power-down as described in Section 10.2.9, "PHY Power-Down Modes," on page 212.
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6.3.3.3
LED Pins Power Down
All LED outputs may be disabled by setting the LED_DIS bit in the Power Management Control Register (PMT_CTRL).
Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive state.
6.3.4
CHIP LEVEL POWER MANAGEMENT
The device supports power-down modes to allow applications to minimize power consumption.
Power is reduced by disabling the clocks as outlined in Table 6-2, "Power Management States". All configuration data
is saved when in any power state. Register contents are not affected unless specifically indicated in the register description.
There is one normal operating power state, D0, and three power saving states: D1, D2 and D3. Although appropriate
for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions.
D0: Normal Mode - This is the normal mode of operation of this device. In this mode, all functionality is available.
This mode is entered automatically on any chip-level reset (POR, RST# pin reset, EtherCAT system reset).
D1: System Clocks Disabled, XTAL, PLL and network clocks enabled - In this low power mode, all clocks derived
from the PLL clock are disabled. The network clocks remain enabled if supplied by the PHYs or externally. The
crystal oscillator and the PLL remain enabled. Exit from this mode may be done manually or automatically.
This mode could be used for PHY General Power Down mode, PHY WoL mode and PHY Energy Detect Power
Down mode.
D2: System Clocks Disabled, PLL disable requested, XTAL enabled - In this low power mode, all clocks derived
from the PLL clock are disabled. The PLL is allowed to be disabled (and will disable if both of the PHYs are in
either Energy Detect or General Power Down). The network clocks remain enabled if supplied by the PHYs or
externally. The crystal oscillator remains enabled. Exit from this mode may be done manually or automatically.
This mode is useful for PHY Energy Detect Power Down mode and PHY WoL mode. This mode could be used
for PHY General Power Down mode.
D3: System Clocks Disabled, PLL disabled, XTAL disabled - In this low power mode, all clocks derived from the
100 MHz PLL clock are disabled. The PLL will be disabled. External network clocks are gated off. The crystal
oscillator is disabled. Exit from this mode may be only be done manually.
This mode is useful for PHY General Power Down mode.
The Host must place the PHY into General Power Down mode by setting the Power Down (PHY_PWR_DWN)
bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) before setting this power state.
Note:
Disabling the crystal oscillator will disable the CLK_25 output signal.
TABLE 6-2:
POWER MANAGEMENT STATES
Clock Source
25 MHz Crystal Oscillator
PLL
system clocks (100 MHz, 50 MHz, 25 MHz and others)
network clocks
Note
1:
2:
3:
D0
ON
ON
ON
available(1)
D1
ON
ON
OFF
available(1)
D2
ON
OFF(2)
OFF
available(1)
D3
OFF
OFF
OFF
OFF(3)
If supplied by the PHYs or externally
PLL is requested to be turned off and will disable if both of the PHYs are in either Energy Detect or General Power Down
PHY clocks are off, external clocks are gated off
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6.3.4.1
Entering Low Power Modes
To enter any of the low power modes (D1 - D3) from normal mode (D0), follow these steps:
1.
2.
3.
4.
5.
Write the PM_MODE and PM_WAKE fields in the Power Management Control Register (PMT_CTRL) to their
desired values
Set the wake-up detection desired per Section 6.3.1, "Wake-Up Event Detection".
Set the appropriate wake-up notification per Section 6.3.2, "Wake-Up (PME) Notification".
Ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted,
receivers disabled, packets processed / flushed, etc.)
Set the PM_SLEEP_EN bit in the Power Management Control Register (PMT_CTRL).
Note:
The PM_MODE field cannot be changed at the same time as the PM_SLEEP_EN bit is set and the
PM_SLEEP_EN bit cannot be set at the same time that the PM_MODE field is changed.
Upon entering any low power mode, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG)
and the Power Management Control Register (PMT_CTRL) is forced low.
Note:
6.3.4.2
Upon entry into any of the power saving states the host interfaces are not functional.
Exiting Low Power Modes
Exiting from a low power mode can be done manually or automatically.
An automatic wake-up will occur based on the events described in Section 6.3.2, "Wake-Up (PME) Notification". Automatic wake-up is enabled with the Power Management Wakeup (PM_WAKE) bit in the Power Management Control
Register (PMT_CTRL).
A manual wake-up is initiated by the host when:
• an HBI write (CS and WR or CS, RD_WR and ENB) is performed to the device. Although all writes are ignored
until the device has been woken and a read performed, the host should direct the write to the Byte Order Test
Register (BYTE_TEST). Writes to any other addresses should not be attempted until the device is awake.
• an SPI/SQI cycle (SCS# low and SCK high) is performed to the device. Although all reads and writes are ignored
until the device has been woken, the host should direct the use a read of the Byte Order Test Register
(BYTE_TEST) to wake the device. Reads and writes to any other addresses should not be attempted until the
device is awake.
To determine when the host interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once
the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in
the Hardware Configuration Register (HW_CFG) or the Power Management Control Register (PMT_CTRL) can be
polled to determine when the device is fully awake.
For both automatic and manual wake-up, the Device Ready (READY) bit will go high once the device is returned to
power savings state D0 and the PLL has re-stabilized. The PM_MODE and PM_SLEEP_EN fields in the Power Management Control Register (PMT_CTRL) will also clear at this point.
Under normal conditions, the device will wake-up within 2 ms.
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6.3.5
6.3.5.1
POWER MANAGEMENT REGISTERS
Power Management Control Register (PMT_CTRL)
Offset:
084h / 3084h
Size:
32 bits
This read-write register controls the power management features and the PME pin of the device. The ready state of the
device be determined via the Device Ready (READY) bit of this register.
Note:
This register can be read while the device is in the reset or not ready / power savings states without leaving
the host interface in an intermediate state. If the host interface is in a reset state, returned data may be
invalid.
It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.
Bits
31:29
Description
Power Management Mode (PM_MODE)
This register field determines the chip level power management mode that
will be entered when the Power Management Sleep Enable
(PM_SLEEP_EN) bit is set.
Type
Default
R/W/SC
000b
R/W/SC
0b
000: D0
001: D1
010: D2
011: D3
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Writes to this field are ignored if Power Management Sleep Enable
(PM_SLEEP_EN) is also being written with a 1.
This field is cleared when the device wakes up.
28
Power Management Sleep Enable (PM_SLEEP_EN)
Setting this bit enters the chip level power management mode specified with
the Power Management Mode (PM_MODE) field.
0: Device is not in a low power sleep state
1: Device is in a low power sleep state
This bit can not be written at the same time as the PM_MODE register field.
The PM_MODE field must be set, and then this bit must be set for proper
device operation.
Writes to this bit with a value of 1 are ignored if Power Management Mode
(PM_MODE) is being written with a new value.
Note:
Although not prevented by H/W, this bit should not be written with
a value of 1 while Power Management Mode (PM_MODE) has a
value of “D0”.
This field is cleared when the device wakes up.
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Bits
27
Description
Type
Default
R/W
0b
R/W
0b
RESERVED
RO
-
EtherCAT Core Clock Disable (ECAT_DIS)
This bit disables the clocks for the EtherCAT core.
R/W
0b
RO
-
R/W1C
0b
R/W1C
0b
Power Management Wakeup (PM_WAKE)
When set, this bit enables automatic wake-up based on PME events.
0: Manual Wakeup only
1: Auto Wakeup enabled
26
LED Disable (LED_DIS)
This bit disables LED outputs. Open-drain / open-source LEDs are un-driven.
Push-pull LEDs are still driven but are set to their inactive state.
0: LEDs are enabled
1: LEDs are disabled
25:22
21
0: Clocks are enabled
1: Clocks are disabled
In order for this bit to be set, it must be written as a 1 two consecutive times.
A write of a 0 will reset the count.
20:18
17
RESERVED
Energy-Detect / WoL Status Port B (ED_WOL_STS_B)
This bit indicates an energy detect or WoL event occurred on the Port B PHY.
In order to clear this bit, it is required that the event in the PHY be cleared as
well. The event sources are described in Section 6.3, "Power Management,"
on page 51.
16
Energy-Detect / WoL Status Port A (ED_WOL_STS_A)
This bit indicates an energy detect or WoL event occurred on the Port A PHY.
In order to clear this bit, it is required that the event in the PHY be cleared as
well. The event sources are described in Section 6.3, "Power Management,"
on page 51.
15
Energy-Detect / WoL Enable Port B (ED_WOL_EN_B)
When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will be
asserted upon an energy-detect or WoL event from Port B.
R/W
0b
14
Energy-Detect / WoL Enable Port A (ED_WOL_EN_A)
When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will be
asserted upon an energy-detect or WoL event from Port A.
R/W
0b
RESERVED
RO
-
13:10
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Bits
9:7
Description
Type
Default
R/W
NASR
Note
000b
R/W
NASR
Note
0b
RESERVED
RO
-
PME Indication (PME_IND)
The PME signal can be configured as a pulsed output or a static signal,
which is asserted upon detection of a wake-up event. When set, the PME
signal will pulse active for 50mS upon detection of a wake-up event. When
cleared, the PME signal is driven continuously upon detection of a wake-up
event.
R/W
0b
R/W
NASR
Note
0b
R/W
0b
PME Pin Map (PME_PIN_SEL)
This field is used to map the PME signal to one of the various device pins.
000: None
001: ERRLED
010: WAIT_ACK
011: SYNC0/LATCH0
100: SYNC1/LATCH1
101: Reserved
110: Reserved
111: Reserved
Note:
6
Even when mapped, the PME output must be enabled, otherwise
the mapped pin remains undriven.
PME Buffer Type (PME_TYPE)
When this bit is cleared, the PME output pin functions as an open-drain buffer for use in a wired-or configuration. When set, the PME output pin is a
push-pull driver.
0: PME pin open-drain output
1: PME pin push-pull driver
Note:
5:4
3
When the PME output pin is configured as an open-drain output,
the PME_POL field of this register is ignored and the output is
always active low.
0: PME driven continuously on detection of event
1: PME 50mS pulse on detection of event
The PME signal can be deactivated by clearing the above status bit(s) or by
clearing the appropriate enable(s).
2
PME Polarity (PME_POL)
This bit controls the polarity of the PME signal. When set, the PME output is
an active high signal. When cleared, it is active low.
Note:
When PME is configured as an open-drain output, this field is
ignored and the output is always active low.
0: PME active low
1: PME active high
1
PME Enable (PME_EN)
When set, this bit enables the external PME signal pin. When cleared, the
external PME signal is disabled.
Note:
This bit does not affect the PME_INT interrupt bit of the Interrupt
Status Register (INT_STS).
0: PME pin disabled
1: PME pin enabled
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Bits
Description
Type
Default
0
Device Ready (READY)
When set, this bit indicates that the device is ready to be accessed. Upon
power-up, RST# reset, return from power savings states, EtherCAT chip level
or module level reset, or digital reset, the host processor may interrogate this
field as an indication that the device has stabilized and is fully active.
RO
0b
This rising edge of this bit will assert the Device Ready (READY) bit in
INT_STS and can cause an interrupt if enabled.
Note:
6.4
Note:
With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
Note:
This bit is identical to bit 27 of the Hardware Configuration Register
(HW_CFG).
Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Reset Control Register
(RESET_CTL) is set.
Device Ready Operation
The device supports a Ready status register bit that indicates to the Host software when the device is fully ready for
operation. This bit may be read via the Power Management Control Register (PMT_CTRL) or the Hardware Configuration Register (HW_CFG).
Following power-up reset, RST# reset, EtherCAT chip level reset or digital reset (see Section 6.2, "Resets"), the Device
Ready (READY) bit indicates that the device has read, and is configured from, the contents of the EEPROM.
An EtherCAT reset via the Reset Control Register (RESET_CTL) will cause the EtherCAT core to reload from the
EEPROM, temporarily causing the Device Ready (READY) to be low.
Entry into any power savings state (see Section 6.3.4, "Chip Level Power Management") other than D0 will cause
Device Ready (READY) to be low. Upon wake-up, the Device Ready (READY) bit will go high once the device is
returned to power savings state D0 and the PLL has re-stabilized.
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7.0
SYSTEM INTERRUPTS
7.1
Functional Overview
This chapter describes the system interrupt structure of the device. The device provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated
internally by the various device sub-modules and can be configured to generate a single external host interrupt via the
IRQ interrupt output pin. The programmable nature of the host interrupt provides the user with the ability to optimize
performance dependent upon the application requirements. The IRQ interrupt buffer type, polarity and de-assertion
interval are modifiable. The IRQ interrupt can be configured as an open-drain output to facilitate the sharing of interrupts
with other devices. All internal interrupts are maskable and capable of triggering the IRQ interrupt.
7.2
Interrupt Sources
The device is capable of generating the following interrupt types:
•
•
•
•
•
•
•
Ethernet PHY Interrupts
Power Management Interrupts
General Purpose Timer Interrupt (GPT)
EtherCAT Interrupt
Software Interrupt (General Purpose)
Device Ready Interrupt
Clock Output Test Mode
All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure, as shown in
Figure 7-1. At the top level of the device interrupt structure are the Interrupt Status Register (INT_STS), Interrupt Enable
Register (INT_EN) and Interrupt Configuration Register (IRQ_CFG).
The Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) aggregate and enable/disable all interrupts from the various device sub-modules, combining them together to create the IRQ interrupt. These registers provide direct interrupt access/configuration to the General Purpose Timer, software and device ready interrupts. These
interrupts can be monitored, enabled/disabled and cleared, directly within these two registers. In addition, event indications are provided for the EtherCAT Slave, Power Management, and Ethernet PHY interrupts. These interrupts differ in
that the interrupt sources are generated and cleared in other sub-block registers. The INT_STS register does not provide details on what specific event within the sub-module caused the interrupt and requires the software to poll an additional sub-module interrupt register (as shown in Figure 7-1) to determine the exact interrupt source and clear it. For
interrupts which involve multiple registers, only after the interrupt has been serviced and cleared at its source will it be
cleared in the INT_STS register.
The Interrupt Configuration Register (IRQ_CFG) is responsible for enabling/disabling the IRQ interrupt output pin as
well as configuring its properties. The IRQ_CFG register allows the modification of the IRQ pin buffer type, polarity and
de-assertion interval. The de-assertion timer guarantees a minimum interrupt de-assertion period for the IRQ output
and is programmable via the Interrupt De-assertion Interval (INT_DEAS) field of the Interrupt Configuration Register
(IRQ_CFG). A setting of all zeros disables the de-assertion timer. The de-assertion interval starts when the IRQ pin deasserts, regardless of the reason.
Note:
The de-assertion timer does not apply to the PME interrupt. The PME interrupt is ORed into the IRQ logic
following the deassertion timer gating. Assertion of the PME interrupt does not affect the de-assertion timer.
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FIGURE 7-1:
FUNCTIONAL INTERRUPT HIERARCHY
Top Level Interrupt Registers
(System CSRs)
INT_CFG
INT_STS
INT_EN
PHY B Interrupt Registers
Bit 27 (PHY_INT_B)
of INT_STS register
PHY_INTERRUPT_SOURCE_B
PHY_INTERRUPT_MASK_B
PHY A Interrupt Registers
Bit 26 (PHY_INT _A)
of INT_STS register
PHY_INTERRUPT_SOURCE_A
PHY_INTERRUPT_MASK_A
Bit 17 (PME_INT)
of INT_STS register
Power Management Control Register
PMT_CTRL
EtherCAT Interrupt Registers
Bit 0 (ECAT_INT)
of INT_STS register
ECAT_AL_EVENT_REQUEST
ECAT_AL_EVENT_MASK
The following sections detail each category of interrupts and their related registers. Refer to the corresponding function’s
chapter for bit-level definitions of all interrupt registers.
7.2.1
ETHERNET PHY INTERRUPTS
The Ethernet PHYs each provide a set of identical interrupt sources. The top-level PHY A Interrupt Event (PHY_INT_A)
and PHY B Interrupt Event (PHY_INT_B) bits of the Interrupt Status Register (INT_STS) provides indication that a PHY
interrupt event occurred in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
PHY interrupts are enabled/disabled via their respective PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).
The source of a PHY interrupt can be determined and cleared via the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). Unique interrupts are generated based on the following events:
•
•
•
•
•
•
•
•
•
ENERGYON Activated
Auto-Negotiation Complete
Remote Fault Detected
Link Down (Link Status Negated)
Link Up (Link Status Asserted)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
Wake-on-LAN Event Detected
In order for an interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event must be enabled
in the corresponding PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY A Interrupt Event Enable
(PHY_INT_A_EN) and/or PHY B Interrupt Event Enable (PHY_INT_B_EN) bits of the Interrupt Enable Register
(INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).
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For additional details on the Ethernet PHY interrupts, refer to Section 10.2.8, "PHY Interrupts," on page 209.
7.2.2
POWER MANAGEMENT INTERRUPTS
Multiple Power Management Event interrupt sources are provided by the device. The top-level Power Management
Interrupt Event (PME_INT) bit of the Interrupt Status Register (INT_STS) provides indication that a Power Management
interrupt event occurred in the Power Management Control Register (PMT_CTRL).
The Power Management Control Register (PMT_CTRL) provides enabling/disabling and status of all Power Management conditions. These include energy-detect on the PHYs and Wake-On-LAN (Perfect DA, Broadcast, Wake-up frame
or Magic Packet) detection by PHYs A&B.
In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired Power Management interrupt event must be enabled in the Power Management Control Register (PMT_CTRL), the Power Management Event Interrupt Enable (PME_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ
output must be enabled via the IRQ Enable (IRQ_EN) bit 8 of the Interrupt Configuration Register (IRQ_CFG).
The power management interrupts are only a portion of the power management features of the device. For additional
details on power management, refer to Section 6.3, "Power Management," on page 51.
7.2.3
GENERAL PURPOSE TIMER INTERRUPT
A GP Timer (GPT_INT) interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable
Register (INT_EN). This interrupt is issued when the General Purpose Timer Count Register (GPT_CNT) wraps past
zero to FFFFh and is cleared when the GP Timer (GPT_INT) bit of the Interrupt Status Register (INT_STS) is written
with 1.
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT must be enabled
via the General Purpose Timer Enable (TIMER_EN) bit in the General Purpose Timer Configuration Register
(GPT_CFG), the GP Timer Interrupt Enable (GPT_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set
and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register
(IRQ_CFG).
For additional details on the General Purpose Timer, refer to Section 14.1, "General Purpose Timer," on page 394.
7.2.4
ETHERCAT INTERRUPT
The top-level EtherCAT Interrupt Event (ECAT_INT) of the Interrupt Status Register (INT_STS) provides indication that
an EtherCAT interrupt event occurred in the AL Event Request Register. The AL Event Mask Register provides
enabling/disabling of all EtherCAT interrupt conditions. The AL Event Request Register provides the status of all EtherCAT interrupts.
In order for an EtherCAT interrupt event to trigger the external IRQ interrupt pin, the desired EtherCAT interrupt must
be enabled in the AL Event Mask Register, the EtherCAT Interrupt Event Enable (ECAT_INT_EN) bit of the Interrupt
Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the
Interrupt Configuration Register (IRQ_CFG).
For additional details on the EtherCAT interrupts, refer to Section 11.0, "EtherCAT," on page 282.
7.2.5
SOFTWARE INTERRUPT
A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt
Enable Register (INT_EN). The Software Interrupt (SW_INT) bit of the Interrupt Status Register (INT_STS) is generated
when the Software Interrupt Enable (SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) changes from cleared
to set (i.e. on the rising edge of the enable). This interrupt provides an easy way for software to generate an interrupt
and is designed for general software usage.
In order for a Software interrupt event to trigger the external IRQ interrupt pin, the IRQ output must be enabled via the
IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).
7.2.6
DEVICE READY INTERRUPT
A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register
(INT_EN). The Device Ready (READY) bit of the Interrupt Status Register (INT_STS) indicates that the device is ready
to be accessed after a power-up or reset condition. Writing a 1 to this bit in the Interrupt Status Register (INT_STS) will
clear it.
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LAN9254
In order for a device ready interrupt event to trigger the external IRQ interrupt pin, the Device Ready Enable
(READY_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the
IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).
7.2.7
CLOCK OUTPUT TEST MODE
In order to facilitate system level debug, the crystal clock can be enabled onto the IRQ pin by setting the IRQ Clock
Select (IRQ_CLK_SELECT) bit of the Interrupt Configuration Register (IRQ_CFG).
The IRQ pin should be set to a push-pull driver by using the IRQ Buffer Type (IRQ_TYPE) bit for the best result.
7.3
Interrupt Registers
This section details the directly addressable interrupt related System CSRs. These registers control, configure and monitor the IRQ interrupt output pin and the various device interrupt sources. For an overview of the entire directly addressable register map, refer to Section 5.0, "Register Map," on page 40.
TABLE 7-1:
INTERRUPT REGISTERS
ADDRESS
ETHERCAT
DIRECT
MAPPED
MODE
054h
3054h
Interrupt Configuration Register (IRQ_CFG)
058h
3058h
Interrupt Status Register (INT_STS)
05Ch
305Ch
Interrupt Enable Register (INT_EN)
2020 Microchip Technology Inc.
REGISTER NAME (SYMBOL)
DS00003422A-page 63
LAN9254
7.3.1
INTERRUPT CONFIGURATION REGISTER (IRQ_CFG)
Offset:
054h / 3054h
Size:
32 bits
This read/write register configures and indicates the state of the IRQ signal.
Bits
Description
Type
Default
31:24
Interrupt De-assertion Interval (INT_DEAS)
This field determines the Interrupt Request De-assertion Interval in multiples
of 10 microseconds.
R/W
00h
RESERVED
RO
-
Interrupt De-assertion Interval Clear (INT_DEAS_CLR)
Writing a 1 to this register clears the de-assertion counter in the Interrupt
Controller, thus causing a new de-assertion interval to begin (regardless of
whether or not the Interrupt Controller is currently in an active de-assertion
interval).
R/W
SC
0h
RO
0b
RO
0b
RESERVED
RO
-
IRQ Enable (IRQ_EN)
This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ
output is disabled and permanently de-asserted. This bit has no effect on any
internal interrupt status bits.
R/W
0b
RO
-
Setting this field to zero causes the device to disable the INT_DEAS Interval,
reset the interval counter and issue any pending interrupts. If a new, non-zero
value is written to this field, any subsequent interrupts will obey the new setting.
This field does not apply to the PME_INT interrupt.
23:15
14
0: Normal operation
1: Clear de-assertion counter
13
Interrupt De-assertion Status (INT_DEAS_STS)
When set, this bit indicates that the interrupt controller is currently in a deassertion interval and potential interrupts will not be sent to the IRQ pin.
When this bit is clear, the interrupt controller is not currently in a de-assertion
interval and interrupts will be sent to the IRQ pin.
0: Interrupt controller not in de-assertion interval
1: Interrupt controller in de-assertion interval
12
Master Interrupt (IRQ_INT)
This read-only bit indicates the state of the internal IRQ line, regardless of the
setting of the IRQ_EN bit, or the state of the interrupt de-assertion function.
When this bit is set, one of the enabled interrupts is currently active.
0: No enabled interrupts active
1: One or more enabled interrupts active
11:9
8
0: Disable output on IRQ pin
1: Enable output on IRQ pin
7:5
RESERVED
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Bits
Description
Type
Default
4
IRQ Polarity (IRQ_POL)
When cleared, this bit enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When the IRQ is configured as
an open-drain output (via the IRQ_TYPE bit), this bit is ignored and the interrupt is always active low.
R/W
NASR
Note 1
0b
RESERVED
RO
-
IRQ Clock Select (IRQ_CLK_SELECT)
When this bit is set, the crystal clock may be output on the IRQ pin. This is
intended to be used for system debug purposes in order to observe the clock
and not for any functional purpose.
R/W
0b
R/W
NASR
Note 1
0b
0: IRQ active low output
1: IRQ active high output
3:2
1
Note:
0
When using this bit, the IRQ pin should be set to a push-pull driver.
IRQ Buffer Type (IRQ_TYPE)
When this bit is cleared, the IRQ pin functions as an open-drain output for
use in a wired-or interrupt configuration. When set, the IRQ is a push-pull
driver.
Note:
When configured as an open-drain output, the IRQ_POL bit is
ignored and the interrupt output is always active low.
0: IRQ pin open-drain output
1: IRQ pin push-pull driver
Note 1: Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Reset Control Register
(RESET_CTL) is set.
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7.3.2
INTERRUPT STATUS REGISTER (INT_STS)
Offset:
058h / 3058h
Size:
32 bits
This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt
conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register
reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where indicated as R/W1C, writing a 1 to the corresponding bits acknowledges and
clears the interrupt.
Bits
Description
Type
Default
31
Software Interrupt (SW_INT)
This interrupt is generated when the Software Interrupt Enable
(SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) is set high.
Writing a one clears this interrupt.
R/W1C
0b
30
Device Ready (READY)
This interrupt indicates that the device is ready to be accessed after a
power-up or reset condition.
R/W1C
0b
RESERVED
RO
-
27
PHY B Interrupt Event (PHY_INT_B)
This bit indicates an interrupt event from the PHY B. The source of the interrupt can be determined by polling the PHY x Interrupt Source Flags Register
(PHY_INTERRUPT_SOURCE_x).
RO
0b
26
PHY A Interrupt Event (PHY_INT_A)
This bit indicates an interrupt event from the PHY A. The source of the interrupt can be determined by polling the PHY x Interrupt Source Flags Register
(PHY_INTERRUPT_SOURCE_x).
RO
0b
RESERVED
RO
-
R/W1C
0b
RO
-
R/W1C
0b
RESERVED
RO
-
EtherCAT Interrupt Event (ECAT_INT)
This bit indicates an EtherCAT interrupt event. The source of the interrupt
can be determined by polling the AL Event Request Register.
RO
0b
29:28
25:20
19
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer Count Register
(GPT_CNT) wraps past zero to FFFFh.
18
RESERVED
17
Power Management Interrupt Event (PME_INT)
This interrupt is issued when a Power Management Event is detected as
configured in the Power Management Control Register (PMT_CTRL). This
interrupt functions independent of the PME signal and will still function if the
PME signal is disabled. Writing a '1' clears this bit regardless of the state of
the PME hardware signal. In order to clear this bit, all unmasked bits in the
Power Management Control Register (PMT_CTRL) must first be cleared.
Note:
16:1
0
DS00003422A-page 66
The Interrupt De-assertion interval does not apply to the PME
interrupt.
2020 Microchip Technology Inc.
LAN9254
7.3.3
INTERRUPT ENABLE REGISTER (INT_EN)
Offset:
05Ch / 305Ch
Size:
32 bits
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding
interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the
interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of Software Interrupt Enable (SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS)
bits, which mimic the layout of this register.
Bits
Description
Type
Default
31
Software Interrupt Enable (SW_INT_EN)
R/W
0b
30
Device Ready Enable (READY_EN)
R/W
0b
RESERVED
RO
-
27
PHY B Interrupt Event Enable (PHY_INT_B_EN)
R/W
0b
26
PHY A Interrupt Event Enable (PHY_INT_A_EN)
R/W
0b
RESERVED
RO
-
19
GP Timer Interrupt Enable (GPT_INT_EN)
R/W
0b
18
RESERVED
RO
-
17
Power Management Event Interrupt Enable (PME_INT_EN)
R/W
0b
RESERVED
RO
-
EtherCAT Interrupt Event Enable (ECAT_INT_EN)
R/W
0b
29:28
25:20
16:1
0
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8.0
HOST BUS INTERFACE
8.1
Functional Overview
The Host Bus Interface (HBI) module provides a high-speed asynchronous slave interface that facilitates communication between the device and a host system. The HBI allows access to the System CSRs and internal FIFOs and memories and handles byte swapping based on the endianness select.
The following is an overview of the functions provided by the HBI:
• Address bus input: Three addressing modes are supported. These are a Multiplexed Address / Data Mode, a
Demultiplexed Address Mode, and a Indexed Address Mode. The mode selection is done through a configuration
input.
• Selectable data bus width: Selected through a configuration input, the host data bus width is selectable.
LAN9252 compatibility Mode: 16 and 8-bit data modes are supported.
The HBI performs BYTE and WORD to DWORD assembly on write data and keeps track of the BYTE / WORD
count for reads. Individual BYTE access is not supported.
•
•
•
•
•
EtherCAT Direct Mapped Mode: 16 and 8-bit data modes are supported. BE1 and BE0 are used for byte selection.
For the non-EtherCAT Core registers, The HBI performs BYTE and WORD to DWORD assembly / disassembly.
Individual BYTE access (in 16-bit mode) is not supported. For the EtherCAT Core registers and Process RAM,
individual BYTE access is supported. BYTE to DWORD assembly / disassembly is not necessary.
Selectable read / write control modes: Two control modes are available. Separate read and write pins or an
enable and direction pin. The mode selection is done through a configuration input.
Selectable control line polarity / buffer type: The polarity of the wait / acknowledge chip select, read / write,
byte enables, and address latch signals, and the buffer type of the wait / acknowledge signal are selectable
through configuration inputs.
Dynamic Endianness control: The HBI supports the selection of big and little endian host byte ordering based
on the endianness signal. This highly flexible interface provides mixed endian access for registers and memory.
Depending on the addressing mode of the device, this signal is either configuration register controlled, pin controlled, or as part of the strobed address input.
Bus Wait State support: Used with EtherCAT Direct Mapped mode, the HBI provides a Wait / Acknowledge signal to indicate when read data is available or write cycles may be completed.
Direct FIFO access: A FIFO direct select signal directs all host write operations to the EtherCAT Process RAM
Write Data FIFO (Multiplexed Address Mode only) and all host read operations from the EtherCAT Process RAM
Read Data FIFO (Multiplexed Address Mode only). This signal is strobed as part of the address input.
8.1.1
ETHERCAT DIRECT MAPPED MODE PCB BACKWARDS COMPATIBILITY
While in EtherCAT Direct Mapped Mode, additional pins are required for full functionality. However with some caveats,
EtherCAT Direct Mapped Mode can be made to work with PCBs designed for the LAN9252.
WAIT_ACK: The WAIT_ACK pin on the LAN9252 functioned as the fiber mode signal detect as well as the Port B FXSD Enable. For copper twisted pair operation, this pin would either be tied to or pulled down to ground. WAIT_ACK is
disabled by default to avoid a short. Without the WAIT_ACK connected to the host processor, the host bus cycles must
assume worst case cycle timing.
BE1/BE0: When in 16-bit data width mode, the byte enables are required to select which byte or bytes are written or
read from the EtherCAT core. In multiplexed mode, these pins on the LAN9252 are unused and most likely not driven.
The BE1/BE0 pins have internal pull-downs such that if left undriven, they would assume an active state, This allows
16-bit only access to the device. Caution is required to not over-write the adjacent byte when only BYTE access is
desired.
8.2
8.2.1
Control Logic
READ / WRITE CONTROL SIGNALS
The device supports two distinct read / write signal methods:
• read (RD) and write (WR) strobes are input on separate pins.
• read and write signals are decoded from an enable input (ENB) and a direction input (RD_WR).
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LAN9254
8.2.2
CONTROL LINE POLARITY AND BUFFER TYPE
The device supports polarity control on the following:
•
•
•
•
•
•
chip select input (CS)
read strobe (RD) / direction input (RD_WR)
write strobe (WR) / enable input (ENB)
byte enable (BE0 and BE1)
address latch control (ALELO and ALEHI)
wait / acknowledge (WAIT_ACK)
The device supports buffer type control on the following:
• wait / acknowledge (WAIT_ACK)
8.2.3
CS QUALIFICATION OF ALE (MULTIPLEXED ADDRESS / DATA MODE ONLY)
Qualification of the ALELO and ALEHI signals with the CS signal is selectable. When qualification is enabled, CS must
be active during ALELO and ALEHI in order to strobe the address inputs. When qualification is not enabled, CS is a
don’t care during the address phase.
8.2.4
WAIT / ACKNOWLEDGE OPERATION
When operating in EtherCAT Direct Mapped mode (refer to Section 5.0, Register Map), the host system must meet the
device’s timing access requirements. For reads from the EtherCAT Core CSR or Process Data RAM, the read cycles
must wait until read data has been internally retrieved. All write cycles must wait for any prior write access to the EtherCAT Core CSR or Process Data RAM to internally complete. The host system may either wait the specified worst case
access time, or may use the WAIT_ACK signal.
WAIT_ACK is only used when operating in EtherCAT Direct Mapped mode. When not in EtherCAT Direct Mapped
mode, if WAIT_ACK is enabled it is always inactive (showing ACK).
WAIT_ACK may be set as an active low open drain output for wire-AND systems or as a three-stated push-pull output.
WAIT_ACK operation is described in Section 8.4.3.3.
8.3
8.3.1
Device Addressing, Endianess Control and Data FIFO Selection
MULTIPLEXED ADDRESS / DATA MODE
In Multiplexed Address / Data mode, the address, FIFO Direct Select and endianness select inputs are shared with the
data bus. Two methods are supported, Single Phase Address Latching, utilizing up to 16 address / data pins and Dual
Phase Address Latching, utilizing only the lower 8 data bits.
8.3.1.1
Single Phase Address Latching
In Single Phase mode, all address bits, the FIFO Direct Select signal and the endianness select are strobed into the
device using the trailing edge of the ALELO signal. The address latch is implemented on all 16 address / data pins. In
8-bit data mode, where pins AD[15:8] are used exclusively for addressing, it is not necessary to drive these upper
address lines with a valid address continually through read and write operations. However, this operation, referred to as
Partial Address Multiplexing, is acceptable since the device will never drive these pins.
Qualification of the ALELO signal with the CS signal is selectable. When qualification is enabled, CS must be active
during ALELO in order to strobe the address inputs. When qualification is not enabled, CS is a don’t care during the
address phase.
The address is retained for all future read and write operations. It is retained until either a reset event occurs or a new
address is loaded. This allows multiple read and write requests to take place to the same address, without requiring
multiple address latching operations.
8.3.1.2
Dual Phase Address Latching
In Dual Phase mode, the lower 8 address bits are strobed into the device using the inactive going edge of the ALELO
signal and the remaining upper address bits, the FIFO Direct Select signals and the endianness select are strobed into
the device using the trailing edge of the ALEHI signal. The strobes can be in either order. In 8-bit data mode, pins
AD[15:8] are not used. In 16-bit data mode, pins D[15:8] are used only for data.
2020 Microchip Technology Inc.
DS00003422A-page 69
LAN9254
Qualification of the ALELO and ALEHI signals with the CS signal is selectable. When qualification is enabled, CS must
be active during ALELO and ALEHI in order to strobe the address inputs. When qualification is not enabled, CS is a
don’t care during the address phase.
The address is retained for all future read and write operations. It is retained until either a reset event occurs or a new
address is loaded. This allows multiple read and write requests to take place to the same address, without requiring
multiple address latching operations.
8.3.1.3
Address Bit to Address / Data Pin Mapping
In 8-bit data mode, address bit 0 is multiplexed onto pin AD[0], address bit 1 onto pin AD[1], etc.
In LAN9252 compatible address mode, the highest address bit is bit 9 and is multiplexed onto pin AD[9] (single phase)
or AD[1] (dual phase). The address latched into the device is considered a BYTE address and covers 1K bytes (0 to
3FFh).
In EtherCAT Direct Mapped mode, the highest address bit is bit 13 and is multiplexed onto pin AD[13] (single phase) or
AD[5] (dual phase). The address latched into the device is considered a BYTE address and covers 16K bytes (0 to
3FFFh).
In 16-bit data mode, address bit 1 is multiplexed onto pin AD[0], address bit 2 onto pin AD[1], etc.
In LAN9252 compatible address mode, the highest address bit is bit 9 and is multiplexed onto pin AD[8] (single phase)
or AD[0] (dual phase). The address latched into the device is considered a WORD address and covers 512 words (0 to
1FFh).
In EtherCAT Direct Mapped mode, the highest address bit is bit 13 and is multiplexed onto pin AD[12] (single phase) or
AD[4] (dual phase). The address latched into the device is considered a WORD address and covers 8K words (0 to
1FFFh).
EtherCAT Direct Mapped mode increases the address bit count by 4.
When the address is sent to the rest of the device, it is converted to a BYTE address.
8.3.1.4
Endianness Select to Address / Data Pin Mapping
The endianness select is included into the multiplexed address to allow the host system to dynamically select the endianness based on the memory address used. This allows for mixed endian access for registers and memory.
The endianness selection is multiplexed to the data pin one bit above the last address bit as shown in Table 8-1.
TABLE 8-1:
ENDIANNESS SELECT TO ADDRESS / DATA PIN MAPPING
Address Mode
LAN9252 compatible address mode
EtherCAT Direct Mapped mode
Data Mode
Single Phase
Dual Phase
Single Phase
Dual Phase
8-bit
AD10
AD2
AD14
AD6
16-bit
AD9
AD1
AD13
AD5
8.3.1.5
FIFO Direct Select to Address / Data Pin Mapping
The FIFO Direct Select signal is included into the multiplexed address to allow the host system to address the EtherCAT
Process RAM Data FIFOs as if they were a large flat address space.
FIFO Direct Select is not used in EtherCAT Direct Mapped mode since the Process RAM FIFOs are not used.
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LAN9254
The FIFO Direct Select signal is multiplexed to the data pin two bits above the last address bit as shown in Table 8-2.
TABLE 8-2:
FIFO DIRECT SELECT TO ADDRESS / DATA PIN MAPPING
Address Mode
LAN9252 compatible address mode
EtherCAT Direct Mapped mode
Data Mode
Single Phase
Dual Phase
Single Phase
Dual Phase
8-bit
AD11
AD3
N/A
N/A
16-bit
AD10
AD2
N/A
N/A
8.3.2
DEMULTIPLEXED ADDRESS MODE
In Demultiplexed Address mode, the address and endianness select inputs are directly provided by the host. A FIFO
Direct Select signal is not provided by the host and is internally held inactive. The address mode is controlled by PDI
Control Register.
8.3.2.1
Address Bit Usage
The address input to the device is always considered a BYTE address. In 8-bit data mode, all address bits are used.
In 16-bit data mode, address bit 0 is unused.
8.3.3
INDEXED ADDRESS MODE
In Indexed Address mode, access to the internal registers and memory of the device are indirectly mapped using Index
and Data registers. The desired internal address is written into the device at a particular offset. The value written is then
used as the internal address when the associate Data register address is accessed.
Three Index / Data register sets are provided allowing for multi-threaded operation without the concern of one thread
corrupting the Index set by another thread.
The selection of the appropriate Index register which then selects the internal register is done using the host address
inputs directly (asynchronously).
A FIFO Direct Select signal is not provided by the host however, it is emulated when the host accesses the Data register
located at BYTE address 18h-1Bh. As discussed below in Section 8.3.4.2, "Index Register Bypass FIFO Access
(Indexed Address Mode Only)", the EtherCAT Process RAM Data FIFOs are accessed when reading or writing the Data
register located at BYTE address 18h-1Bh. Index Register Bypass FIFO Access is not used in EtherCAT Direct Mapped
mode since the Process RAM FIFOs are not used.
An endianness signal is not provided by the host, however, endianness can be configured per Index / Data pair and for
the Index Register Bypass FIFO Access method.
The host address register map is given below. In 8-bit data mode, the host address input (ADDR[4:0]) is a BYTE
address. In 16-bit data mode, ADDR0 is not provided and the host address input (ADDR[4:1]) is a WORD address.
TABLE 8-3:
HOST BUS INTERFACE INDEXED ADDRESS MODE REGISTER MAP
BYTE
ADDRESS
SYMBOL
00h-03h
HBI_IDX_0
Host Bus Interface Index Register 0
04h-07h
HBI_DATA_0
Host Bus Interface Data Register 0
08h-0Bh
HBI_IDX_1
Host Bus Interface Index Register 1
0Ch-0Fh
HBI_DATA_1
Host Bus Interface Data Register 1
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REGISTER NAME
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TABLE 8-3:
8.3.3.1
HOST BUS INTERFACE INDEXED ADDRESS MODE REGISTER MAP
BYTE
ADDRESS
SYMBOL
10h-13h
HBI_IDX_2
Host Bus Interface Index Register 2
14h-17h
HBI_DATA_2
Host Bus Interface Data Register 2
18h-1Bh
PROCESS_RAM_FIFO
(not used for when in
EtherCAT Direct
Mapped mode)
1Ch-1Fh
HBI_CFG
REGISTER NAME
Process RAM Write Data FIFO
Process RAM Read Data FIFO
Host Bus Interface Configuration Register
Host Bus Interface Index Register
The Index registers are writable as WORDs or as BYTEs, depending upon the data mode. There is no concern about
DWORD assembly rules when writing these registers. The Index registers are formatted as follows:
Bits
31:17
16
Description
Type
Default
RESERVED
RO
-
Byte High Enable
When in 16-bit data mode with EtherCAT Direct Mapped mode enabled, this
active low bit enables the upper byte of the WORD for accesses to the EtherCAT Core registers or Process Data RAM.
0 = upper byte enabled
1 = upper byte disabled
This bit is used for reads as well as writes.
R/W
0b
R/W
1234h
Note 2
This bit is unused for accesses to the non-EtherCAT Core registers since
they are always DWORD wide (via the DWORD assembly / disassemble
process).
15:0
Internal Address
The address used when the corresponding Data register is accessed.
Note:
The internal address provided by each Index register is always
considered to be a BYTE address.
For accesses to the non-EtherCAT Core registers, address 1:0 are unused
since these registers are always DWORD aligned.
When in 16-bit data mode with EtherCAT Direct Mapped mode enabled,
address 0 acts as an active low Byte Low Enable, enabling the lower byte of
the WORD for accesses to the EtherCAT Core registers or Process Data
RAM.
0 = lower byte enabled
1 = lower byte disabled
This bit is used for reads as well as writes.
Note 2: The default may be used to help determine the endianness of the register.
8.3.3.2
Host Bus Interface Data Registers Usage
The Host Bus Interface Data Registers provide a 4 byte window onto the internal registers.
Accesses to the non-EtherCAT Core registers are always DWORD aligned and sized.The lower two bits of the address
field in the index registers are not used.
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LAN9254
The HBI performs the DWORD assemble / disassemble with the internal access being a DWORD. Bits 1 and 0 (8-bit
data mode only) of the host bus address are used to select one of the four BYTEs (8-bit data mode) or one of the two
WORDs (16-bit data mode) of the data register. Software may choose to address these BYTEs (8-bit data mode) or
WORDs (16-bit data mode) as BYTEs/WORDs at the various addresses (e.g. @HBI_DATA_0, @HBI_DATA_0+1, etc.)
within the data register or it may choose to address these as a DWORD and let the host’s Bus Interface Unit (BIU) split
the larger DWORD data type into BYTEs or WORDs. In either case, the data register would be accessed multiple times
at increasing addresses (e.g. @HBI_DATA_0, @HBI_DATA_0+1, etc.).
When using EtherCAT Direct Mapped mode, accesses to the EtherCAT Core registers or Process Data RAM do not
require DWORD alignment. Bits 1 and 0 (8-bit data mode only) of the address field in the index registers are used as
part of the internal pointer.
Internal data access is done at the native host bus width, however the selected EtherCAT Core register or Process Data
RAM may be a DWORD, WORD or BYTE. Two methods exist to access the multiple WORDs/BYTEs when the register
is wider than the host bus.
• Access the lower WORD/BYTE by addressing the lower WORD/BYTE of the data register (e.g. @HBI_DATA_0).
Increment the address field in the index register.
Access the next WORD/BYTE by once again addressing the lower WORD/BYTE of the data register (e.g.
@HBI_DATA_0).
(repeat twice more for 8-bit data mode)
• Access the lower WORD/BYTE by addressing the lower WORD/BYTE of the data register (e.g. @HBI_DATA_0).
Access the next WORD/BYTE by addressing the next WORD/BYTE of the data register (e.g. @HBI_DATA_0+1
or +2).
(repeat twice more for 8-bit data mode)
With the first method, software would need to reassemble or split the data. With the second method, although software
does not need to increment the address field between data accesses, it would still need to reassemble or split the data.
The second method, however, allows S/W to address the data register as a DWORD or WORD and let the host’s Bus
Interface Unit (BIU) split larger data types (DWORDs or WORDs) into WORDs and BYTEs.
In order to access sequential locations of the EtherCAT Core registers or Process Data RAM when sequential locations
of the data register are addressed, hardware adds the lower 2 bits of the host address to the address field of the index
register, emulating the incrementing of the address field.
8.3.3.3
Host Bus Interface Configuration Register
The HBI Configuration register is used to specify the endianness of the interface. Endianess for each Index / Data pair
and for the Index Register Bypass FIFO Access method can be individually specified.
The endianness of this register is irrelevant since each byte is shadowed into 4 positions.
The HBI Configuration register is writable as a DWORD, as WORDs or as BYTEs, depending upon the data mode.
There is no concern about DWORD assembly rules when writing this register.The Configuration register is formatted as
follows:
Bits
Type
Default
RESERVED
RO
-
27
FIFO Endianness Shadow 3
This bit is a shadow of bit 3.
R/W
0b
26
Host Bus Interface Index / Data Register 2 Endianness Shadow 3
This bit is a shadow of bit 2.
R/W
0b
25
Host Bus Interface Index / Data Register 1 Endianness Shadow 3
This bit is a shadow of bit 1.
R/W
0b
24
Host Bus Interface Index / Data Register 0 Endianness Shadow 3
This bit is a shadow of bit 0.
R/W
0b
RESERVED
RO
-
FIFO Endianness Shadow 2
This bit is a shadow of bit 3.
R/W
0b
31:28
23:20
19
Description
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Bits
Description
Type
Default
18
Host Bus Interface Index / Data Register 2 Endianness Shadow 2
This bit is a shadow of bit 2.
R/W
0b
17
Host Bus Interface Index / Data Register 1 Endianness Shadow 2
This bit is a shadow of bit 1.
R/W
0b
16
Host Bus Interface Index / Data Register 0 Endianness Shadow 2
This bit is a shadow of bit 0.
R/W
0b
RESERVED
RO
-
11
FIFO Endianness Shadow 1
This bit is a shadow of bit 3.
R/W
0b
10
Host Bus Interface Index / Data Register 2 Endianness Shadow 1
This bit is a shadow of bit 2.
R/W
0b
9
Host Bus Interface Index / Data Register 1 Endianness Shadow 1
This bit is a shadow of bit 1.
R/W
0b
8
Host Bus Interface Index / Data Register 0 Endianness Shadow 1
This bit is a shadow of bit 0.
R/W
0b
RESERVED
RO
-
FIFO Endianness
This bit specifies the endianness of FIFO accesses when they are accessed
by means other than the Index / Data Register method.
R/W
0b
R/W
0b
R/W
0b
15:12
7:4
3
0 = Little Endian
1 = Big Endian
Note:
2
In order to avoid any ambiguity with the endianness of this
register, bits 3, 11, 19 and 27 are shadowed. If any of these bits
are set during a write, all of the bits will be set.
Host Bus Interface Index / Data Register 2 Endianness
This bit specifies the endianness of the Index and Data register set 2.
0 = Little Endian
1 = Big Endian
Note:
1
In order to avoid any ambiguity with the endianness of this
register, bits 2, 10, 18 and 26 are shadowed. If any of these bits
are set during a write, all of the bits will be set.
Host Bus Interface Index / Data Register 1 Endianness
This bit specifies the endianness of the Index and Data register set 1.
0 = Little Endian
1 = Big Endian
Note:
DS00003422A-page 74
In order to avoid any ambiguity with the endianness of this
register, bits 1, 9, 17 and 25 are shadowed. If any of these bits
are set during a write, all of the bits will be set.
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Bits
0
Description
Host Bus Interface Index / Data Register 0 Endianness
This bit specifies the endianness of the Index and Data register set 0.
Type
Default
R/W
0b
0 = Little Endian
1 = Big Endian
Note:
8.3.4
8.3.4.1
In order to avoid any ambiguity with the endianness of this
register, bits 0, 8, 16 and 24 are shadowed. If any of these bits
are set during a write, all of the bits will be set.
ETHERCAT PROCESS RAM DATA FIFO ACCESS
FIFO Direct Select Access (Multiplexed Address / Data Mode Only)
As mentioned in Section 8.3.1.5, a FIFO Direct Select signal is provided allows the host system to address the EtherCAT
Process RAM Data FIFOs as if they were a large flat address space. When the FIFO Direct Select signal, which was
latched during the address latch cycle, is active all host write operations are to the EtherCAT Process RAM Write Data
FIFO and all host read operations are from the EtherCAT Process RAM Read Data FIFO. Only the lower latched
address signals are decoded in order to select the proper BYTE or WORD. All other address inputs are ignored in this
mode. All other operations are the same (DWORD assembly, FIFO popping, etc.).
8.3.4.2
Index Register Bypass FIFO Access (Indexed Address Mode Only)
In addition to the indexed access, the Index Registers can be bypassed and the FIFOs accessed at address 18h-1Bh.
At this address, host write operations are to the EtherCAT Process RAM Write Data FIFO and host read operations are
from the EtherCAT Process RAM Read Data FIFO. There is no associated Index Register.
8.4
Data Cycles
Data cycles consist of read and write cycles to the internal device registers, and for Indexed Address mode, read and
write cycles to the Index and Configuration registers.
Data cycles are similar for all address modes. Differences are noted where appropriate.
8.4.1
Note:
INTERNAL REGISTER DATA ACCESS
Internal registers do not include the EtherCAT Core registers and Process Data RAM which are directly
accessible from the host while in EtherCAT Direct Mapped mode. Access to the EtherCAT Core is
described in Section 8.4.3.
The host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. The Host Bus Interface performs
the conversion from WORDs or BYTEs to DWORD, while in 8 or 16-bit data mode.Two or four contiguous accesses
within the same DWORD are required in order to perform a write or read.
For Indexed Address mode, each Data register (four total including one for the Index Register Bypass FIFO Access),
has a separate WORD or BYTE to DWORD conversion. Accesses may be mixed among these (and the HBI Index and
Configuration registers) without concern of data corruption.
8.4.1.1
Write Cycles
A write cycle occurs when CS and WR are active (or when CS and ENB are active with RD_WR indicating write).
On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into registers
(one of four sets for Indexed Address mode) in the HBI. Depending on the bus width, either a WORD or a BYTE is captured. For 8 or 16-bit data modes, this functions as the DWORD assembly with the affected WORD or BYTE determined
by the lower address inputs (the live host address inputs in the case of Indexed Address mode). BYTE swapping is also
done at this point based on the endianness. Endianness determination is described in Section 8.4.4.
WRITES FOLLOWING INITIALIZATION
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Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed.
WRITES DURING AND FOLLOWING POWER MANAGEMENT
During and following any power management mode other than D0, writes from the Host Bus are ignored until after a
read cycle is performed.
8 AND 16-BIT ACCESS
While in 8 or 16-bit data mode, the host is required to perform two or four, 16 or 8-bit writes to complete a single DWORD
transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as
the other write(s) is(are) performed to the remaining WORD or BYTEs.
Note:
Writing the same WORD or BYTEs into the same DWORD may cause undefined or undesirable operation.
The HBI hardware does not protect against this operation.
For Indexed Address mode, accessing the same internal register using two Index / Data register pairs may
cause undefined or undesirable operation. The HBI hardware does not protect against this operation.
For Indexed Address mode, mixing reads and writes into the same Data register may cause undefined or
undesirable operation. The HBI hardware does not protect against this operation.
A write BYTE / WORD counter (a separate counter for each of the four Data Registers in Indexed Address mode) keeps
track of the number of writes. At the trailing edge of the write cycle, the counter (one of four for Indexed Address mode
based on the captured host address) is incremented. Once all writes occur, a 32-bit write is performed to the internal
register using the address captured on the leading edge of the write cycle and the data captured on the trailing edge of
the write cycle. (For Indexed Address mode one of the four Data Registers sets is selected based on the captured host
address.)
The write BYTE / WORD counter(s) is(are) reset if the power management mode is set to anything other than D0.
8.4.1.2
Read Cycles
A read cycle occurs when CS and RD are active (or when CS and ENB are active with RD_WR indicating read).
At the beginning of the read cycle, the appropriate device register is selected and its data is driven onto the data pins.
Depending on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD
is determined by the endianness and the lower address inputs (the live host address inputs in the case of Indexed
Address mode). Endianness determination is described in Section 8.4.4.
POLLING FOR INITIALIZATION COMPLETE
Before device initialization, the HBI will not return valid data. To determine when the HBI is functional the following procedure should be followed:
For Multiplexed Address / Data mode, the Byte Order Test Register (BYTE_TEST) should be polled. Each poll should
consist of an address latch cycle(s) and a data cycle. Once the correct pattern is read, the interface can be considered
functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be
polled to determine when the device is fully configured.
For Demultiplexed Address mode, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware
Configuration Register (HW_CFG) can be polled to determine when the device is fully configured.
For Indexed Address mode, first the Host Bus Interface Index Register 0 should be polled, then the Byte Order Test
Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional.
At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured.
READS DURING AND FOLLOWING POWER MANAGEMENT
During any power management mode other than D0, reads from the Host Bus are ignored. If the power management
mode changes back to D0 during an active read cycle, the tail end of the read cycle is ignored. Internal registers are not
affected and the state of the HBI does not change.
8 AND 16-BIT ACCESS
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For certain register accesses, the host is required to perform two or four consecutive 16 or 8-bit reads to complete a
single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE
first, as long as the other read(s) is(are) performed from the remaining WORD or BYTEs.
Note:
Reading the same WORD or BYTEs from the same DWORD may cause undefined or undesirable operation. The HBI hardware does not protect against this operation. The HBI simply counts that four BYTEs
have been read.
For Indexed Address mode, accessing the same internal register using two Index / Data register pairs may
cause undefined or undesirable operation. The HBI hardware does not protect against this operation.
For Indexed Address mode, mixing reads and writes into the same Data register may cause undefined or
undesirable operation. The HBI hardware does not protect against this operation.
A read BYTE / WORD counter (a separate counter for each of the four Data Registers in Indexed Address mode) keeps
track of the number of reads. This(these) counter(s) is(are) separate from the write counter(s) above. At the trailing edge
of the read cycle, the counter (one of four for Indexed Address mode based on the captured host address) is incremented. On the last read for the DWORD, an internal read is performed to update any Change on Read CSRs or FIFOs.
The read BYTE / WORD counter(s) is(are) reset if the power management mode is set to anything other than D0.
SPECIAL CSR HANDLING
Live Bits
Any register bit that is updated by a hardware event is held at the beginning of the read cycle to prevent it from changing
during the read cycle.
Multiple BYTE / WORD Live Registers in 16 or 8-Bit Modes
Some registers have “live” fields or related fields that span across multiple BYTEs or WORDs. For 16 and 8-bit data
reads, it is possible for the value of these fields to change between host read cycles. In order to prevent reading intermediate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word
is read.
Registers that have this function, have a note in their register description. The registers are unlocked if the power management mode is set to anything other than D0.
Register Polling During Reset or Initialization
Some registers support polling during reset or device initialization to determine when the device is accessible. For these
registers, only one read may be performed without the need to read the other WORD or BYTEs. The same BYTE or
WORD of the register may be re-read repeatedly.
A register that is 16 or 8-bit readable or readable during reset or device initialization, is noted in its register description.
8.4.2
INDEXED ADDRESS MODE INDEX AND CONFIGURATION REGISTER DATA ACCESS
As described in Section 8.3.3, Indexed Address mode, contains Index and Configuration registers.
The host data bus can be 16 or 8-bits wide. The HBI Index registers and the HBI Configuration register are 32-bits wide
and are writable as WORDs or as BYTEs, depending upon the data mode. They do not have nor do they require
WORDs or BYTEs to DWORD conversion.
8.4.2.1
Write Cycles
A write cycle occurs when CS and WR are active (or when CS and ENB are active with RD_WR indicating write).
On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into the Configuration register or one for the Index registers.
Depending on the bus width, either a WORD or a BYTE is written. The affected WORD or BYTE is determined by the
endianness of the register (specified in the Host Bus Interface Configuration Register) and the lower address inputs.
Individual BYTE (in 16-bit data mode) access is not supported.
WRITES FOLLOWING INITIALIZATION
Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed.
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WRITES DURING AND FOLLOWING POWER MANAGEMENT
During and following any power management mode other than D0, writes from the Host Bus are ignored until after a
read cycle is performed.
8.4.2.2
Read Cycles
A read cycle occurs when CS and RD are active (or when CS and ENB are active with RD_WR indicating read). The
host address is used directly from the Host Bus.
At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depending on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is
determined by the endianness of the register (specified in the Host Bus Interface Configuration Register) and the lower
host address inputs.
8.4.3
Note:
ETHERCAT DIRECT MAPPED MODE
While in EtherCAT Direct Mapped mode, non-EtherCAT Core registers continue to be accessed using the
methods described in Section 8.4.1.1 and Section 8.4.2.2.
While in EtherCAT Direct Mapped mode, Indexed Address Mode Index and Configuration registers continue to be accessed using the methods described in Section 8.4.2.1 and Section 8.4.2.2.
While in EtherCAT Direct Mapped mode, the EtherCAT Core registers and Process Data RAM are mapped into the host
address space. The host data bus can be 16 or 8-bits wide and the EtherCAT Core interface is set to match. The Host
Bus Interface does not perform any BYTE to WORD conversion. While in 16-bit mode, BYTE or WORD access may be
performed.
8.4.3.1
EtherCAT Core Register and Process Data RAM Write Access
A write cycle starts when CS and WR are active (or when CS and ENB are active with RD_WR indicating write). The
host address and byte high enable must be valid at the start of the write cycle.
Depending on the configuration, the internal write access is either performed during (non-posted) or following (posted)
the host write cycle.
If non-posted write is selected, the internal write operation begins at the start of the write cycle with the WAIT_ACK pin
indicating wait. When the internal write operation is finished, the WAIT_ACK pin indicates acknowledge allowing the
host write cycle to complete. Note that non-posted writes require that the host data be valid at the start of the host write
cycle.
If posted write is selected, the internal operation begins at the end of the host write cycle. In this case, the external write
access is very fast but any access that follows immediately will be delayed by the pending write (as controlled by the
WAIT_ACK pin). The maximum device access time is higher in this case.
Write cycles may be WORD or BYTE wide. WORD assembly is not performed by the HBI for accesses to the EtherCAT
Core. All host accesses are sent to the EtherCAT Core interface.
Note:
In Indexed 16-bit mode, although the host bus may have byte enables available, they are not used by the
device. The byte enables are provided internally as bits in the index register. The host may actually perform
a WORD access however the byte enable bits specify the actually bytes affected.
WRITES FOLLOWING INITIALIZATION
Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed.
WRITES DURING AND FOLLOWING POWER MANAGMENT
During and following any power management mode other than D0, writes from the Host Bus are ignored until after a
read cycle is performed.
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8.4.3.2
EtherCAT Core Register and Process Data RAM Read Access
A read cycle occurs when CS and RD are active (or when CS and ENB are active with RD_WR indicating read). The
host address and byte high enable must be valid at the start of the read cycle.
The internal read operation begins at the start of the read cycle with the WAIT_ACK pin indicating wait. Following any
potential posted internal write, the read operation is performed and valid data is available from the EtherCAT Core interface. Read data is saved in the EtherCAT Core interface and returned to the HBI where it is multiplexed based on the
asynchronous host address.
The WAIT_ACK pin changes to indicate acknowledge allowing the host read cycle to complete. Configured within the
EtherCAT Core interface, WAIT_ACK deassertion for read accesses can be additionally delayed for 15 ns to provided
additional external DATA setup requirements with respect to WAIT_ACK.
Read cycles may be WORD or BYTE wide. WORD disassembly is not performed by the HBI for accesses to the EtherCAT Core. All host accesses are sent to the EtherCAT Core interface.
8.4.3.3
Wait / Acknowledge Operation
When operating in EtherCAT Direct Mapped mode, the host system must meet the device’s timing access requirements.
All read and write cycles must wait for any posted write access to internally complete. All reads and non-posted writes
must wait until the internal data cycle completes.
The host system may either wait the specified worst case access time, or may use the WAIT_ACK signal.
For consistency, reads and writes to the non-EtherCAT Core registers as well as to the Indexed Address Mode Index
and Configuration registers follow the same WAIT_ACK operation.
Read and write data cycles start with the leading edge of CS, which enables the WAIT_ACK output. The host may start
the read or write cycle at any point following or along with CS.
If a posted EtherCAT Core write operation is internally pending, the WAIT_ACK will initially indicate wait. In the absence
of a pending posted write, WAIT_ACK will initially indicate acknowledge (not busy).
For posted writes, if a prior posted write operation was not internally pending or once a prior posted write operation has
completed, WAIT_ACK will indicate acknowledge. Once acknowledge is indicated, the host may complete the write
cycle on its bus. The write cycle is internally captured and executed by the EtherCAT Core interface.
For non-posted writes and for reads, WAIT_ACK indicate wait when the host starts the data portion of the cycle. Once
the write or read cycle is completed internally, WAIT_ACK will indicate acknowledge and the host may complete its
cycle.
WAIT_ACK becomes undriven with the negation of CS.
8.4.4
HOST ENDIANNESS
The device supports big and little endian host byte ordering. the endianness selection is provided differently for the different addressing modes. For Multiplexed Address / Data mode, the endianness selection is latched during the address
latch cycle. For Demultiplexed Address mode, the endianness selection is an input pin along with the address. For
Indexed Address mode, the endianness selection is from the four endianness bits (one for each Index / Data pair and
one for Index Register Bypass FIFO Access method) in the Host Bus Interface Configuration Register.
When the endianness select is low, host access is little endian and when high, host access is big endian. For multiplexed
and demultiplexed modes, the endianness select may be connected to a high-order address line, making endian selection address-based. This highly flexible interface provides mixed endian access for registers and memory for both PIO
and host DMA access.
Most internal buses are 32-bit with little endian byte ordering used internally. Logic within the Host Bus Interface reorders bytes based on the appropriate endianness bit, and the state of the least significant host address bits.
Data path operations for the supported endian configurations and data bus sizes are illustrated in Figure 8-1 and
Figure 8-2.
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.
FIGURE 8-1:
LITTLE ENDIAN BYTE ORDERING
8-BIT LITTLE ENDIAN
16-BIT LITTLE ENDIAN
INTERNAL ORDER
INTERNAL ORDER
MSB
31
MSB
LSB
24
23
3
16
15
2
8
7
1
0
31
0
LSB
24
23
16
15
8
3
2
1
A=3
3
A=1
3
2
A=2
2
A= 0
1
0
A=1
1
15
7
0
0
0
HOST DATA BUS
0
A=0
8
7
7
0
HOST DATA BUS
.
FIGURE 8-2:
BIG ENDIAN BYTE ORDERING
8-BIT BIG ENDIAN
16-BIT BIG ENDIAN
INTERNAL ORDER
INTERNAL ORDER
MSB
31
MSB
LSB
24
23
3
16
15
2
8
1
7
0
0
31
1
1
A=0
7
8
0
A=2
3
15
1
A= 1
A=0
16
2
0
2
23
3
A=3
A=1
LSB
24
2
15
7
0
0
3
8
7
0
HOST DATA BUS
0
HOST DATA BUS
8.4.4.1
EtherCAT Direct Mapped Mode
While in EtherCAT Direct Mapped mode, the EtherCAT Core interface is 8-bit or 16-bit wide matching the host bus width
selection.
Endianess in 8-bit mode is not applicable (the upper 8 bits of the internal data bus are unused). When 16-bits in width,
little endian byte ordering is used internally. The Host Bus Interface swaps the low and high order bytes if the host
access is big endian.
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Note:
The byte enables BE1/BE0 always follow the host bus pins, therefore in big endian mode, the byte enables
are also swapped.
FIGURE 8-3:
BYTE ORDERING - ETHERCAT DIRECT MAPPED MODE, ETHERCAT CORE
8-BIT n/a ENDIAN
16-BIT LITTLE ENDIAN
16-BIT BIG ENDIAN
INTERNAL ORDER
INTERNAL ORDER
INTERNAL ORDER
MSB
7
0
15
MSB
LSB
8 7
0
1
0
be1
be0
15
LSB
8
7
0
be1
1
7
0
HOST DATA BUS
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15
0
8 7
HOST DATA BUS
0
1
be0
0
0
15
1
8
7
0
HOST DATA BUS
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8.5
Functional Timing Diagrams - Legacy Mode
The following sections present functional timing diagrams while in LAN9252 compatible Legacy mode (i.e. not in EtherCAT Direct Mapped mode). Byte Enables BE1/BE0 are not used in Legacy mode and are not shown. If enabled for output, WAIT_ACK is held inactive (ACK) and is shown as such.
8.5.1
MULTIPLEXED ADDRESSING MODE FUNCTIONAL TIMING DIAGRAMS
The following timing diagrams illustrate example multiplexed addressing mode read and write cycles for various
address/data configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are
selected to detail the main configuration differences (bus size, dual/single phase address latching) within the multiplexed
addressing mode of operation.
The following should be noted for the timing diagrams in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high ALEHI/ALELO, CS, RD,
and WR signals. The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI ALE Polarity,
HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on
page 69 for additional details.
• The diagrams in this section depict little endian byte ordering. However, dynamic big and little endianess are supported via the endianess signal. Endianess changes only the order of the bytes involved, and not the overall timing requirements. Refer to Section 8.3.1.4, "Endianness Select to Address / Data Pin Mapping," on page 70 for
additional information.
• The diagrams in Section 8.5.1.1, "Dual Phase Address Latching" and Section 8.5.1.2, "Single Phase Address
Latching" utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported, as shown in Section 8.5.1.3, "RD_WR / ENB Control Mode Examples". The HBI read/write mode is selectable via the HBI Read/
Write Mode bit of the PDI Configuration Register (HBI Modes). The polarities of the RD_WR and ENB signals are
selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes).
• Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI ALE Qualification bit of the
PDI Configuration Register (HBI Modes). Refer to Section 8.3.1.1, "Single Phase Address Latching," on page 69
and Section 8.3.1.2, "Dual Phase Address Latching," on page 69 for additional information.
• In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. Either or both ALELO
and ALEHI cycles may be skipped and the device retains the last latched address.
• In single phase address latching mode, the ALELO cycle may be skipped and the device retains the last latched
address.
Note:
In 8 and 16-bit modes, the ALELO cycle is normally not skipped since sequential BYTEs or WORDs are
accessed in order to satisfy a complete DWORD cycle. However, there are registers for which a single
BYTE or WORD access is allowed, in which case multiple accesses to these registers may be performed
without the need to re-latch the repeated address.
• For 16 and 8-bit modes, consecutive address cycles must be within the same DWORD until the DWORD is completely accessed (with the register exceptions noted above). Although BYTEs and WORDs can be accessed in
any order, the diagrams in this section depict accessing the lower address BYTE or WORD first.
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8.5.1.1
Dual Phase Address Latching
The figures in this section detail read and write operations in multiplexed addressing mode with dual phase address
latching for 16 and 8-bit modes.
16-BIT READ
The WORD address is latched sequentially from AD[7:0]. A read on D[15:8] and AD[15:0] follows. The cycle is repeated
for the other 16-bits of the DWORD.
FIGURE 8-4:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ
ALELO
ALEHI
CS
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Data 15:8
Address Low
Address High
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
16-BIT READ WITH SUPPRESSED ALEHI
The WORD address is latched sequentially from AD[7:0]. A read on D[15:8] and AD[7:0] follows. The lower address is
then updated to access the opposite WORD.
FIGURE 8-5:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ W/
O ALEHI
ALELO
ALEHI
CS
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Data 15:8
Address Low
2020 Microchip Technology Inc.
Address High
Data 7:0
Data 31:24
Address+1 Low
Data 23:16
DS00003422A-page 83
LAN9254
16-BIT WRITE
The WORD address is latched sequentially from AD[7:0]. A write on D[15:8] and AD[7:0] follows. The cycle is repeated
for the other 16-bits of the DWORD.
FIGURE 8-6:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT WRITE
ALELO
ALEHI
CS
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Data 15:8
Address Low
Address High
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
16-BIT WRITE WITH SUPRESSED ALEHI
The WORD address is latched sequentially from AD[7:0]. A write on D[15:8] and AD[7:0] follows. The lower address is
then updated to access the opposite WORD.
FIGURE 8-7:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT WRITE W/
O ALEHI
ALELO
ALEHI
CS
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
DS00003422A-page 84
Data 15:8
Address Low
Address High
Data 7:0
Data 31:24
Address+1 Low
Data 23:16
2020 Microchip Technology Inc.
LAN9254
16-BIT READ AND WRITES TO CONSTANT ADDRESS
The WORD address is latched sequentially from AD[7:0]. A mix of reads and writes on D[15:8] and AD[7:0] follows.
Note:
Generally, two 16-bit reads to opposite WORDs of the same DWORD are required, with at least the lower
address changing using ALELO. 16-bit reads and writes to the same WORD is a special case.
FIGURE 8-8:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READS
AND WRITES CONSTANT ADDRESS
ALELO
ALEHI
CS
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Address Low
Address High
Data 15:8
Data 15:8
Data 15:8
Data 15:8
Data 15:8
Data 7:0
Data 7:0
Data 7:0
Data 7:0
Data 7:0
8-BIT READ
The BYTE address is latched sequentially from AD[7:0]. A read on AD[7:0] follows. D[15:8] pins are not used or driven.
The cycle is repeated for the other BYTEs of the DWORD.
FIGURE 8-9:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READ
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Hi-Z
Address Low
Address High
Data 7:0
2020 Microchip Technology Inc.
Address+1 Low Address High
Data 15:8
Address+2 Low Address High
Data 23:16
Address+3 Low Address High
Data 31:24
DS00003422A-page 85
LAN9254
8-BIT READ WITH SUPRESSED ALEHI
The BYTE address is latched sequentially from AD[7:0]. A read on AD[7:0] follows. D[15:8] pins are not used or driven.
The lower address is then updated to access the other BYTEs.
FIGURE 8-10:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READ W/O
ALEHI
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Hi-Z
Address Low
Address High
Data 7:0
Address+1 Low
Data 15:8
Address+2 Low
Data 23:16
Address+3 Low
Data 31:24
8-BIT WRITE
The BYTE address is latched sequentially from AD[7:0]. A write on AD[7:0] follows. D[15:8] pins are not used or driven.
The cycle is repeated for the other BYTEs of the DWORD.
FIGURE 8-11:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT WRITE
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Hi-Z
Address Low
Address High
DS00003422A-page 86
Data 7:0
Address+1 Low Address High
Data 15:8
Address+2 Low Address High
Data 23:16
Address+3 Low Address High
Data 31:24
2020 Microchip Technology Inc.
LAN9254
8-BIT WRITE WITH SUPRESSED ALEHI
The BYTE address is latched sequentially from AD[7:0]. A write on AD[7:0] follows. D[15:8] pins are not used or driven.
The lower address is then updated to access the other BYTEs.
FIGURE 8-12:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT WRITE W/
O ALEHI
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
Hi-Z
D[15:8]
AD[7:0]
Address Low
Address High
Data 7:0
Address+1 Low
Data 15:8
Address+2 Low
Data 23:16
Address+3 Low
Data 31:24
8-BIT READS AND WRITES TO CONSTANT ADDRESS
The BYTE address is latched sequentially from AD[7:0]. A mix of reads and writes on AD[7:0] follows. D[15:8] pins are
not used or driven.
Note:
Generally, four 8-bit reads to opposite BYTEs of the same DWORD are required, with at least the lower
address changing using ALELO. 8-bit reads and writes to the same BYTE is a special case.
FIGURE 8-13:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READS
AND WRITES CONSTANT ADDRESS
ALELO
ALEHI
CS
Optional
RD
WR
WAIT_ACK
D[15:8]
AD[7:0]
Hi-Z
Address Low
Address High
2020 Microchip Technology Inc.
Data 7:0
Data 7:0
Data 7:0
Data 7:0
Data 7:0
DS00003422A-page 87
LAN9254
8.5.1.2
Single Phase Address Latching
The figures in this section detail multiplexed addressing mode with single phase addressing for 16 and 8-bit modes of
operation.
16-BIT READ
The WORD address is latched simultaneously from AD[7:0] and AD[15:8]. A read on AD[15:0] follows. The cycle is
repeated for the other 16-bits of the DWORD.
FIGURE 8-14:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT READ
ALELO
ALEHI
CS
Optional
Optional
RD
WR
WAIT_ACK
AD[15:8]
Address High
Data 15:8
Address High
Data 31:24
AD[7:0]
Address Low
Data 7:0
Address+1 Low
Data 23:16
16-BIT WRITE
The WORD address is latched simultaneously from AD[7:0] and AD[15:8]. A write on AD[15:0] follows. The cycle is
repeated for the other 16-bits of the DWORD.
FIGURE 8-15:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT WRITE
ALELO
ALEHI
CS
Optional
Optional
RD
WR
WAIT_ACK
DS00003422A-page 88
AD[15:8]
Address High
Data 15:8
Address High
Data 31:24
AD[7:0]
Address Low
Data 7:0
Address+1 Low
Data 23:16
2020 Microchip Technology Inc.
LAN9254
16-BIT READS AND WRITES TO CONSTANT ADDRESS
The WORD address is latched simultaneously from AD[7:0] and AD[15:8]. A mix of reads and writes on AD[15:0] follows.
Note:
Generally, two 16-bit reads to opposite WORDs of the same DWORD are required. 16-bit reads and writes
to the same WORD is a special case.
2020 Microchip Technology Inc.
DS00003422A-page 89
LAN9254
FIGURE 8-16:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT READS
AND WRITES CONSTANT ADDRESS
ALELO
ALEHI
CS
Optional
RD
WR
WAIT_ACK
AD[15:8]
Address High
Data 15:8
Data 15:8
Data 15:8
Data 15:8
Data 15:8
AD[7:0]
Address Low
Data 7:0
Data 7:0
Data 7:0
Data 7:0
Data 7:0
8-BIT READ
The BYTE address is latched simultaneously from AD[7:0] and AD[15:8]. A read on AD[7:0] follows. AD[15:8] pins are
not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals.
The cycle is repeated for the other BYTEs of the DWORD.
FIGURE 8-17:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READ
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
AD[15:8]
Address High
Address High
Address High
Address High
AD[7:0]
Address Low
RD
WR
WAIT_ACK
DS00003422A-page 90
Data 7:0
Address+1 Low
Data 15:8
Address+2 Low
Data 23:16
Address+3 Low
Data 31:24
2020 Microchip Technology Inc.
LAN9254
8-BIT WRITE
The BYTE address is latched simultaneously from AD[7:0] and AD[15:8]. A write on AD[7:0] follows. AD[15:8] pins are
not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals.
The cycle is repeated for the other BYTEs of the DWORD.
FIGURE 8-18:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT WRITE
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
AD[15:8]
Address High
AD[7:0]
Address Low
Address High
Data 7:0
Address+1 Low
Address High
Data 15:8
Address+2 Low
Address High
Data 23:16
Address+3 Low
Data 31:24
8-BIT READS AND WRITES TO CONSTANT ADDRESS
The BYTE address is latched simultaneously from AD[7:0] and AD[15:8]. A mix of reads and writes on AD[7:0] follows.
AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address
on these signals.
Note:
Generally, four 8-bit reads to opposite BYTEs of the same DWORD are required. 8-bit reads and writes to
the same BYTE is a special case.
FIGURE 8-19:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READS
AND WRITES CONSTANT ADDRESS
ALELO
ALEHI
CS
Optional
RD
WR
WAIT_ACK
AD[15:8]
Address High
AD[7:0]
Address Low
2020 Microchip Technology Inc.
Data 7:0
Data 7:0
Data 7:0
Data 7:0
Data 7:0
DS00003422A-page 91
LAN9254
8.5.1.3
RD_WR / ENB Control Mode Examples
The figures in this section detail read and write operations utilizing the alternative RD_WR and ENB signaling. The HBI
read/write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes).
Note:
The examples in this section detail 16-bit mode with dual phase latching. However, the RD_WR and ENB
signaling can be used identically in all other multiplexed addressing modes of operation as well as in 8-bit
modes.
The examples in this section show the ENB signal active-high and the RD_WR signal low for read and high
for write. The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes).
16-BIT
FIGURE 8-20:
MULTIPLEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE - 16BIT READ
ALELO
ALEHI
CS
Optional
Optional
RD_WR
ENB
WAIT_ACK
AD[15:8]
AD[7:0]
DS00003422A-page 92
Data 15:8
Address Low
Address High
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
2020 Microchip Technology Inc.
LAN9254
FIGURE 8-21:
MULTIPLEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE - 16BIT WRITE
ALELO
ALEHI
CS
Optional
Optional
RD_WR
ENB
WAIT_ACK
AD[15:8]
AD[7:0]
8.5.2
Data 15:8
Address Low
Address High
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
DEMULTIPLEXED ADDRESSING MODE FUNCTIONAL TIMING DIAGRAMS
The following timing diagrams illustrate example demultiplexed addressing mode read and write cycles for various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are selected to detail
the main configuration differences (bus size) within the demultiplexed addressing mode of operation.
The following should be noted for the timing diagrams in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high CS, RD, and WR signals.
The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI Chip Select Polarity, HBI Read,
Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on page 69 for additional details.
• The diagrams in this section depict little endian byte ordering. However, dynamic big and little endianness are supported via the endianness signal. Endianness changes only the order of the bytes involved, and not the overall
timing requirements. Refer to Section 8.4.4, "Host Endianness," on page 79 for additional information.
• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,
as shown in Section 8.5.2.1, "RD_WR / ENB Control Mode Examples". The HBI read/write mode is selectable via
the HBI Read/Write Mode bit of the PDI Configuration Register. The polarities of the RD_WR and ENB signals are
selectable via the HBI Read, Read/Write Polarity and the HBI Write, Enable Polarity configuration inputs.
• For 16 and 8-bit modes, consecutive address cycles must be within the same DWORD until the DWORD is completely accessed (with the register exceptions noted above). Although BYTEs and WORDs can be accessed in
any order, the diagrams in this section depict accessing the lower address BYTE or WORD first.
2020 Microchip Technology Inc.
DS00003422A-page 93
LAN9254
16-BIT READ
The WORD address and endianess is input concurrently with the control. Read data is driven on D[15:0] during RD
active. The cycle is repeated for the other 16-bits of the DWORD.
FIGURE 8-22:
DEMULTIPLEXED ADDRESSING - 16-BIT READ
CS
RD
WR
END_SEL
endianess
endianess
Address
Address+1
D[15:8]
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
A[15:1]
WAIT_ACK
16-BIT WRITE
The WORD address and endianess is input concurrently with the control. Data on D[15:0] is written on the trailing edge
of WR. The cycle is repeated for the other 16-bits of the DWORD.
FIGURE 8-23:
DEMULTIPLEXED ADDRESSING - 16-BIT WRITE
CS
RD
WR
END_SEL
A[15:1]
endianess
endianess
Address
Address+1
WAIT_ACK
DS00003422A-page 94
D[15:8]
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
2020 Microchip Technology Inc.
LAN9254
8-BIT READ
The BYTE address and endianess is input concurrently with the control. Read data is driven on D[7:0] during RD active.
D[15:8] pins are not used or driven. The cycle is repeated for the other BYTEs of the DWORD.
FIGURE 8-24:
DEMULTIPLEXED ADDRESSING - 8-BIT READ
CS
RD
WR
END_SEL
A[15:0]
endianess
endianess
endianess
endianess
Address
Address+1
Address+2
Address+3
Data 23:16
Data 31:24
WAIT_ACK
D[15:8]
D[7:0]
Hi-Z
Data 7:0
Data 15:8
8-BIT WRITE
The BYTE address and endianess is input concurrently with the control. Data on D[7:0] is written on the trailing edge of
WR. D[15:8] pins are not used or driven. The cycle is repeated for the other BYTEs of the DWORD.
FIGURE 8-25:
DEMULTIPLEXED ADDRESSING - 8-BIT WRITE
CS
RD
WR
END_SEL
A[15:0]
endianess
endianess
endianess
endianess
Address
Address+1
Address+2
Address+3
WAIT_ACK
D[15:8]
D[7:0]
2020 Microchip Technology Inc.
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
DS00003422A-page 95
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8.5.2.1
RD_WR / ENB Control Mode Examples
The figures in this section detail read and write operations utilizing the alternative RD_WR and ENB signaling. The HBI
read/write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes).
Note:
The examples in this section detail 16-bit mode. However, the RD_WR and ENB signaling can be used
identically in 8-bit modes.
The examples in this section show the ENB signal active-high and the RD_WR signal low for read and high
for write. The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes).
16-BIT
FIGURE 8-26:
DEMULTIPLEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE 16-BIT WRITE/READ
CS
RD_WR
ENB
END_SEL
A[15:1]
endianess
endianess
endianess
endianess
Address
Address+1
Address
Address+1
WAIT_ACK
DS00003422A-page 96
D[15:8]
Data 15:8
Data 31:24
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
Data 7:0
Data 23:16
2020 Microchip Technology Inc.
LAN9254
8.5.3
INDEXED ADDRESS MODE FUNCTIONAL TIMING DIAGRAMS
The following timing diagrams illustrate example indexed (non-multiplexed) addressing mode read and write cycles for
various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are
selected to detail the main configuration differences (bus size, Configuration / Index / Data cycles) within the indexed
addressing mode of operation.
The following should be noted for the timing diagrams in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high CS, RD, and WR signals.
The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI Chip Select Polarity, HBI Read,
Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on page 69 for additional details.
• The diagrams in this section depict little endian byte ordering. However, configurable big and little endianness are
supported via the endianness bits in the Host Bus Interface Configuration Register. Endianness changes only the
order of the bytes involved, and not the overall timing requirements. Refer to Section 8.4.4, "Host Endianness," on
page 79 for additional information.
• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,
as shown in Section 8.5.3.4, "RD_WR / ENB Control Mode Examples". The HBI read/write mode is selectable via
the HBI Read/Write Mode bit of the PDI Configuration Register. The polarities of the RD_WR and ENB signals are
selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity configuration inputs.
• For 16 and 8-bit modes, consecutive address cycles must be within the same DWORD until the DWORD is completely accessed (some internal registers are excluded from this requirement). Although BYTEs and WORDs can
be accessed in any order, the diagrams in this section depict accessing the lower address BYTE or WORD first.
8.5.3.1
Configuration Register Data Access
The figures in this section detail configuration register read and write operations in indexed address mode for 16 and 8bit modes.
16-BIT READ AND WRITE
For writes, the address is set to access the lower WORD of the Configuration Register. Data on D[15:0] is written on the
trailing edge of WR. The cycle repeats for the upper WORD of the Configuration Register, if desired by the host.
For reads, the address is set to access the lower WORD of the Configuration Register. Read data is driven on D[15:0]
during RD active. The cycle repeats for the upper WORD of the Configuration Register, if desired by the host.
FIGURE 8-27:
INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 16-BIT WRITE/
READ
A[4:1]
CONFIG,1'b0
CONFIG,1'b1
CONFIG,1'b0
CONFIG,1'b1
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
2020 Microchip Technology Inc.
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Data 7:0
Data 23:16
Data 7:0
Data 23:26
DS00003422A-page 97
LAN9254
8-Bit READ AND WRITE
For writes, the address is set to access the lower BYTE of the Configuration Register. Data on D[7:0] is written on the
trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Configuration
Register, if desired by the host.
For reads, the address is set to access the lower BYTE of the Configuration Register. Read data is driven on D[7:0]
during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Configuration
Register, if desired by the host.
FIGURE 8-28:
A[4:0]
INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 8-BIT WRITE/
READ
CONFIG,2'b00
CONFIG,2'b01
CONFIG,2'b10
CONFIG,2'b11
CONFIG,2'b00
CONFIG,2'b01
CONFIG,2'b10
CONFIG,2'b11
Data 7:0
Data 15:8
Data 23:16
Data 31:24
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
8.5.3.2
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
Index Register Data Access
The figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit
modes.
16-BIT READ AND WRITE
For writes, the address is set to access the lower WORD of one of the Index Registers. Data on D[15:0] is written on
the trailing edge of WR. The cycle repeats for the upper WORD of the Index Register, if desired by the host.
For reads, the address is set to access the lower WORD of one of the Index Registers. Read data is driven on D[15:0]
during RD active. The cycle repeats for the upper WORD of the Index Register, if desired by the host.
Note:
The upper BYTE of Index Register is reserved and don’t care.
FIGURE 8-29:
INDEXED ADDRESSING INDEX REGISTER ACCESS - 16-BIT WRITE/READ
A[4:1]
INDEX,1'b0
INDEX,1'b1
INDEX,1'b0
INDEX,1'b1
CS
RD
WR
WAIT_ACK
DS00003422A-page 98
D[15:8]
Index 15:8
8'hXX
Index 15:8
8'hXX
D[7:0]
Index 7:0
Index 23:16
Index 7:0
Index 23:16
2020 Microchip Technology Inc.
LAN9254
8-BIT READ AND WRITE
For writes, the address is set to access the lower BYTE of one of the Index Registers. Data on D[7:0] is written on the
trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Index Register, if desired by the host.
For reads, the address is set to access the lower BYTE of one of the Index Registers. Read data is driven on D[7:0]
during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Index Register,
if desired by the host.
Note:
The upper BYTE of Index Register is reserved and don’t care. Therefore reads and writes to that BYTE is
not useful.
FIGURE 8-30:
A[4:0]
INDEX,2'b00
INDEXED ADDRESSING INDEX REGISTER ACCESS - 8-BIT WRITE/READ
INDEX,2'b01
INDEX,2'b10
INDEX,2'b11
INDEX,2'b00
INDEX,2'b01
INDEX,2'b10
INDEX,2'b11
Index 7:0
Index 15:8
Index 23:16
8'hXX
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
Hi -Z
Index 7:0
Index 15:8
2020 Microchip Technology Inc.
Index 23:16
8'hXX
DS00003422A-page 99
LAN9254
8.5.3.3
Internal Register Data Access
The figures in this section detail typical internal register data read and write cycles in indexed address mode for 16 and
8-bit modes. This includes an index register write followed by either a data read or write.
16-BIT READ
One of the Index Registers is set as described above. The address is then set to access the lower WORD of the corresponding Data Register. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the
Data Register.
FIGURE 8-31:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READ
A[4:1]
INDEX,1'b0
INDEX,1'b1
DATA,1'b0
DATA,1'b1
CS
RD
WR
WAIT_ACK
D[15:8]
Index 15:8
8'hXX
Data 15:8
Data 31:24
D[7:0]
Index 7:0
Index 23:16
Data 7:0
Data 23:16
16-BIT WRITE
One of the Index Registers is set as described above. The address is then set to access the corresponding Data Register. Data on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the Data Register.
FIGURE 8-32:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT WRITE
A[4:1]
INDEX,1'b0
INDEX,1'b1
DATA,1'b0
DATA,1'b1
CS
RD
WR
WAIT_ACK
D[15:8]
Index 15:8
8'hXX
Data 15:8
Data 31:24
D[7:0]
Index 7:0
Index 23:16
Data 7:0
Data 23:16
DS00003422A-page 100
2020 Microchip Technology Inc.
LAN9254
16-BIT READ AND WRITES TO CONSTANT INTERNAL ADDRESS
One of the Index Registers is set as described above. A mix of reads and writes on D[15:0] follows, with each read or
write consisting of an access to both the lower and upper WORDs of the corresponding Data Register.
FIGURE 8-33:
A[4:1]
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READS
AND WRITES CONSTANT ADDRESS
INDEX,1'b0
INDEX,1'b1
DATA,1'b0
DATA,1'b1
DATA,1'b0
DATA,1'b1
DATA,1'b0
DATA,1'b1
DATA,1'b0
DATA,1'b1
DATA,1'b0
DATA,1'b1
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
Index 15:8
8'hXX
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Index 7:0
Index 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
8-BIT READ
One of the Index Registers is set as described above. The address is then set to access the lower BYTE of the corresponding Data Register. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle
repeats for the remaining BYTEs of the Data Register.
FIGURE 8-34:
A[4:0]
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT READ
INDEX,2'b00
INDEX,2'b01
INDEX,2'b10
INDEX,2'b11
DATA,2'b00
DATA,2'b01
DATA,2'b10
DATA,2'b11
Data 7:0
Data 15:8
Data 23:16
Data 31:24
CS
RD
WR
WAIT_ACK
D[15:8]
Hi-Z
D[7:0]
Index 7:0
Index 15:8
Index 23:16
8'hXX
8-BIT WRITE
One of the Index Registers is set as described above. The address is then set to access the corresponding Data Register. Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the
remaining BYTEs of the Data Register.
FIGURE 8-35:
A[4:0]
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT WRITE
INDEX,2'b00
INDEX,2'b01
INDEX,2'b10
INDEX,2'b11
DATA,2'b00
DATA,2'b01
DATA,2'b10
DATA,2'b11
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
Hi-Z
Index 7:0
Index 15:8
2020 Microchip Technology Inc.
Index 23:16
8'hXX
Data 7:0
Data 15:8
Data 23:16
Data 31:24
DS00003422A-page 101
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8-BIT READS AND WRITES TO CONSTANT INTERNAL ADDRESS
One of the Index Registers is set as described above. A mix of reads and writes on D[7:0] follows, with each read or
write consisting of an access to all four BYTES of the corresponding Data Register.
FIGURE 8-36:
A[4:0]
INDEX,2'b00
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT READS
AND WRITES CONSTANT ADDRESS
INDEX,2'b01
INDEX,2'b10
INDEX,2'b11
DATA,2'b00
DATA,2'b01
DATA,2'b10
DATA,2'b10
DATA,2'b11
Data 23:16
Data 31:24
DATA,2'b00
DATA,2'b01
DATA,2'b10
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
A[4:0]
Hi-Z
Index 7:0
Index 15:8
DATA,2'b10
Index 23:16
DATA,2'b11
8'hXX
Data 7:0
Data 15:8
Data 23:16
DATA,2'b00
DATA,2'b01
DATA,2'b10
DATA,2'b10
DATA,2'b11
Data 7:0
Data 15:8
Data 23:16
Data 23:16
Data 31:24
Data 7:0
Data 15:8
Data 23:16
CS
RD
WR
WAIT_ACK
D[15:8]
D[7:0]
Data 23:16
DS00003422A-page 102
Data 31:24
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8.5.3.4
RD_WR / ENB Control Mode Examples
The figures in this section detail read and write operations utilizing the alternative RD_WR and ENB signaling. The HBI
read/write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes).
Note:
The examples in this section detail 16-bit mode access to an Index Register. However, the RD_WR and
ENB signaling can be used identically for all other accesses including Index Register Bypass FIFO Access
as well as in 8-bit modes.
The examples in this section show the ENB signal active-high and the RD_WR signal low for read and high
for write. The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes).
16-BIT
FIGURE 8-37:
INDEXED ADDRESSING RD_WR / ENB CONTROL MODE EXAMPLE - 16-BIT
WRITE/READ
A[4:1]
INDEX,1'b0
INDEX,1'b1
INDEX,1'b0
INDEX,1'b1
CS
RD_WR
ENB
WAIT_ACK
D[15:8]
Index 15:8
8'hXX
Index 15:8
8'hXX
D[7:0]
Index 7:0
Index 23:16
Index 7:0
Index 23:16
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DS00003422A-page 103
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8.6
Functional Timing Diagrams - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
8.6.1
MULTIPLEXED ADDRESSING MODE FUNCTIONAL TIMING DIAGRAMS
The following timing diagrams illustrate example multiplexed addressing mode read and write cycles for various
address/data configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are
selected to detail the main configuration differences (bus size, dual/single phase address latching) within the multiplexed
addressing mode of operation.
The following should be noted for the timing diagrams in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high BE1/0, ALEHI/ALELO, CS,
RD, and WR signals. The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI BE1/BE0
Polarity, HBI ALE Polarity, HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register and Extended PDI Configuration Register (HBI Modes), respectively.
Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on page 69 for additional details.
• The diagrams in this section depict little endian byte ordering. However, dynamic big and little endianness are supported for 16-bit mode via the endianess signal. Endianness changes only the order of the bytes involved, and not
the overall timing requirements. Refer to Section 8.4.4, "Host Endianness," on page 79 for additional information.
• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,
similar to the multiplexed examples in Section 8.5.1.3, "RD_WR / ENB Control Mode Examples". The HBI read/
write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register. The polarities of the
RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity
configuration inputs.
• Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI ALE Qualification bit of the
PDI Configuration Register. Refer to Section 8.3.1.1, "Single Phase Address Latching," on page 69 and Section
8.3.1.2, "Dual Phase Address Latching," on page 69 for additional information.
• In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. Either or both ALELO
and ALEHI cycles may be skipped and the device retains the last latched address.
• In single phase address latching mode, the ALELO cycle may be skipped and the device retains the last latched
address.
Note:
While accessing non-EtherCAT Core registers the ALELO cycle is normally not skipped since sequential
BYTEs or WORDs are accessed in order to satisfy a complete DWORD cycle. However, there are registers
for which a single BYTE or WORD access is allowed, in which case multiple accesses to these registers
may be performed without the need to re-latch the repeated address.
• While accessing non-EtherCAT Core registers, for proper DWORD assembly, consecutive address cycles must be
within the same DWORD until the DWORD is completely accessed (with the register exceptions noted above).
Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict accessing the
lower address BYTE or WORD first.
• While accessing non-EtherCAT Core registers in 16-bit mode, all cycles are 16-bit wide with BE1/BE0 unused.
While accessing EtherCAT Core registers and the Process RAM in 16-bit mode, 8 or 16-bit transfers can be
selected via the BE1/BE0 pins.
DS00003422A-page 104
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8.6.1.1
Dual Phase Address Latching
The figures in this section detail read and write operations in multiplexed addressing mode with dual phase address
latching for 16 and 8-bit modes.
16-BIT MODE READ
The WORD address is latched sequentially from AD[7:0].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
D[15:8] and AD[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-38:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ
ALELO
ALEHI
CS
Optional
Optional
RD
WR
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active if prior
write pending)
D[15:8]
AD[7:0]
(initially active
due to rd)
Data 15:8
Address Low
Address High
2020 Microchip Technology Inc.
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
DS00003422A-page 105
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16-BIT MODE POSTED WRITE
The WORD address is latched sequentially from AD[7:0].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[15:8] and AD[7:0] is written on the trailing edge of WR.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-39:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT POSTED
WRITE
ALELO
ALEHI
CS
Optional
Optional
RD
WR
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active if prior write
pending)
D[15:8]
AD[7:0]
(initially active due
to write pending)
Data 15:8
Address Low
DS00003422A-page 106
Address High
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
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16-BIT MODE NON-POSTED WRITE
The WORD address is latched sequentially from AD[7:0].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (second example).
Data on D[15:8] and AD[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK
becomes inactive.
For EtherCAT Core registers and the Process RAM, the write cycle occurs during WR active. For-non EtherCAT Core
registers, the write cycle occurs upon WR inactive. Therefore Data is held until WR inactive.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-40:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT NONPOSTED WRITE
ALELO
ALEHI
CS
Optional
Optional
RD
WR
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active
due to write)
D[15:8]
AD[7:0]
Data 15:8
Address Low
Address High
2020 Microchip Technology Inc.
Data 7:0
Data 31:24
Address+1 Low Address High
Data 23:16
DS00003422A-page 107
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8-BIT MODE READ
The BYTE address is latched sequentially from AD[7:0].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
AD[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive. D[15:8] pins are not used
or driven.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-41:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT READ
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
(initially active if prior
write pending)
(initially active
due to rd)
(initially active
due to rd)
D[15:8]
AD[7:0]
(initially active
due to rd)
Hi-Z
Address Low
Address High
Data 7:0
Address+1 Low Address High
Data 15:8
Address+2 Low Address High
Data 23:16
Address+3 Low Address High
Data 31:24
8-BIT MODE POSTED WRITE
The BYTE address is latched sequentially from AD[7:0].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on AD[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-42:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT POSTED
WRITE
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
(initially active if prior
write pending)
(initially active due
to write pending)
(initially active due
to write pending)
D[15:8]
AD[7:0]
(initially active due
to write pending)
Hi-Z
Address Low
Address High
DS00003422A-page 108
Data 7:0
Address+1 Low Address High
Data 15:8
Address+2 Low Address High
Data 23:16
Address+3 Low Address High
Data 31:24
2020 Microchip Technology Inc.
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8-BIT MODE NON-POSTED WRITE
The BYTE address is latched sequentially from AD[7:0].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (second example).
Data on AD[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. D[15:8] pins are not used or driven.
For EtherCAT Core registers and the Process RAM, the write cycle occurs during WR active. For-non EtherCAT Core
registers, the write cycle occurs upon WR inactive. Therefore Data is held until WR inactive.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-43:
MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 8-BIT NONPOSTED WRITE
ALELO
ALEHI
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
(initially active
due to write)
(initially active
due to write)
D[15:8]
AD[7:0]
(initially active
due to write)
Hi-Z
Address Low
Address High
Data 7:0
2020 Microchip Technology Inc.
Address+1 Low Address High
Data 15:8
Address+2 Low Address High
Data 23:16
Address+3 Low Address High
Data 31:24
DS00003422A-page 109
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8.6.1.2
Single Phase Address Latching
The figures in this section detail read and write operations in multiplexed addressing mode with single phase address
latching for 16 and 8-bit modes.
16-BIT MODE READ
The WORD address is latched simultaneously from AD[7:0] and AD[15:8].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
AD[15:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-44:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT READ
ALELO
CS
Optional
Optional
RD
WR
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active if prior
write pending)
(initially active
due to rd)
AD[15:8]
Address High
Data 15:8
Address High
Data 31:24
AD[7:0]
Address Low
Data 7:0
Address+1 Low
Data 23:16
DS00003422A-page 110
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LAN9254
16-BIT MODE POSTED WRITE
The WORD address is latched simultaneously from AD[7:0] and AD[15:8].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on AD[15:8] is written on the trailing edge of WR.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-45:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT
POSTED WRITE
ALELO
CS
Optional
Optional
RD
WR
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active if prior write
pending)
(initially active due
to write pending)
AD[15:8]
Address High
Data 15:8
Address High
Data 31:24
AD[7:0]
Address Low
Data 7:0
Address+1 Low
Data 23:16
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DS00003422A-page 111
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16-BIT MODE NON-POSTED WRITE
The WORD address is latched simultaneously from AD[7:0] and AD[15:8].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (second example).
Data on AD[15:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive.
For EtherCAT Core registers and the Process RAM, the write cycle occurs during WR active. For-non EtherCAT Core
registers, the write cycle occurs upon WR inactive. Therefore Data is held until WR inactive.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-46:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 16-BIT NONPOSTED WRITE
ALELO
CS
Optional
Optional
RD
WR
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active
due to write)
AD[15:8]
Address High
Data 15:8
Address High
Data 31:24
AD[7:0]
Address Low
Data 7:0
Address+1 Low
Data 23:16
DS00003422A-page 112
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LAN9254
8-BIT MODE READ
The BYTE address is latched simultaneously from AD[7:0] and AD[15:8].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
AD[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive. AD[15:8] pins are not used
or driven for the data phase as the host could potentially continue to drive the upper address on these signals.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-47:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READ
ALELO
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
(initially active if prior
write pending)
AD[15:8]
Address High
AD[7:0]
Address Low
(initially active
due to rd)
(initially active
due to rd)
Address High
Data 7:0
(initially active
due to rd)
Address High
Address+1 Low
Data 15:8
Address High
Address+2 Low
Data 23:16
Address+3 Low
Data 31:24
8-BIT MODE POSTED WRITE
The BYTE address is latched simultaneously from AD[7:0] and AD[15:8].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on AD[7:0] is written on the trailing edge of WR. AD[15:8] pins are not used or driven for the data phase as the
host could potentially continue to drive the upper address on these signals.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-48:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT POSTED
WRITE
ALELO
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
(initially active if prior
write pending)
AD[15:8]
Address High
AD[7:0]
Address Low
(initially active due
to write pending)
(initially active due
to write pending)
Address High
Data 7:0
2020 Microchip Technology Inc.
Address+1 Low
(initially active due
to write pending)
Address High
Data 15:8
Address+2 Low
Address High
Data 23:16
Address+3 Low
Data 31:24
DS00003422A-page 113
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8-BIT MODE NON-POSTED WRITE
The BYTE address is latched simultaneously from AD[7:0] and AD[15:8].
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (second example).
Data on AD[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper
address on these signals.
For EtherCAT Core registers and the Process RAM, the write cycle occurs during WR active. For-non EtherCAT Core
registers, the write cycle occurs upon WR inactive. Therefore Data is held until WR inactive.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-49:
MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT NONPOSTED WRITE
ALELO
CS
Optional
Optional
Optional
Optional
RD
WR
WAIT_ACK
(initially active
due to write)
AD[15:8]
Address High
AD[7:0]
Address Low
DS00003422A-page 114
(initially active
due to write)
Address High
Data 7:0
Address+1 Low
(initially active
due to write)
Address High
Data 15:8
Address+2 Low
Address High
Data 23:16
Address+3 Low
Data 31:24
2020 Microchip Technology Inc.
LAN9254
8.6.2
DEMULTIPLEXED ADDRESSING MODE FUNCTIONAL TIMING DIAGRAMS
The following timing diagrams illustrate example demultiplexed addressing mode read and write cycles for various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are selected to detail
the main configuration differences (bus size) within the demultiplexed addressing mode of operation.
The following should be noted for the timing diagrams in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high BE1/0, CS, RD, and WR signals. The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI BE1/BE0 Polarity, HBI
Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration
Register and Extended PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control
Line Polarity and Buffer Type," on page 69 for additional details.
• The diagrams in this section depict little endian byte ordering. However, dynamic big and little endianness are supported for 16-bit mode via the endianness signal. Endianness changes only the order of the bytes involved, and
not the overall timing requirements. Refer to Section 8.4.4, "Host Endianness," on page 79 for additional information.
• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,
similar to the demultiplexed examples in Section 8.5.2.1, "RD_WR / ENB Control Mode Examples". The HBI read/
write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register. The polarities of the
RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity
configuration inputs.
• While accessing non-EtherCAT Core registers, for proper DWORD assembly, consecutive address cycles must be
within the same DWORD until the DWORD is completely accessed (with the register exceptions noted above).
Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict accessing the
lower address BYTE or WORD first.
• While accessing non-EtherCAT Core registers in 16-bit mode, all cycles are 16-bit wide with BE1/BE0 unused.
While accessing EtherCAT Core registers and the Process RAM in 16-bit mode, 8 or 16-bit transfers can be
selected via the BE1/BE0 pins.
2020 Microchip Technology Inc.
DS00003422A-page 115
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16-BIT MODE READ
The WORD address, byte enables and endianess is input concurrently with the control.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
D[15:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-50:
DEMULTIPLEXED ADDRESSING - 16-BIT READ
CS
RD
WR
END_SEL
endianess
endianess
A[15:1]
Address
Address+1
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active if prior
write pending)
DS00003422A-page 116
(initially active
due to rd)
D[15:8]
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
2020 Microchip Technology Inc.
LAN9254
16-BIT MODE POSTED WRITE
The WORD address, byte enables and endianess is input concurrently with the control.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[15:0] is written on the trailing edge of WR.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-51:
DEMULTIPLEXED ADDRESSING - 16-BIT POSTED WRITE
CS
RD
WR
END_SEL
endianess
endianess
A[15:1]
Address
Address+1
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active if prior
write pending)
2020 Microchip Technology Inc.
(initially active due
to write pending)
D[15:8]
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
DS00003422A-page 117
LAN9254
16-BIT MODE NON-POSTED WRITE
The WORD address, byte enables and endianess is input concurrently with the control.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (second example).
Data on D[15:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive.
For EtherCAT Core registers and the Process RAM, the write cycle occurs during WR active. For-non EtherCAT Core
registers, the write cycle occurs upon WR inactive. Therefore Data is held until WR inactive.
The cycle is repeated for the other 16-bits of the DWORD if required.
FIGURE 8-52:
DEMULTIPLEXED ADDRESSING - 16-BIT NON-POSTED WRITE
CS
RD
WR
END_SEL
endianess
endianess
A[15:1]
Address
Address+1
BE[1:0]
BE[1:0]
BE[1:0]
WAIT_ACK
(initially active
due to write)
DS00003422A-page 118
D[15:8]
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
2020 Microchip Technology Inc.
LAN9254
8-BIT MODE READ
The BYTES address is input concurrently with the control.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
D[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive. D[15:8] pins are not used
or driven.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-53:
DEMULTIPLEXED ADDRESSING - 8-BIT READ
CS
RD
WR
A[15:0]
Address
Address+1
Address+2
Address+3
WAIT_ACK
(initially active if prior
write pending)
(initially active
due to rd)
(initially active
due to rd)
D[15:8]
D[7:0]
2020 Microchip Technology Inc.
(initially active
due to rd)
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
DS00003422A-page 119
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8-BIT MODE POSTED WRITE
The BYTE address is input concurrently with the control.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-54:
DEMULTIPLEXED ADDRESSING - 8-BIT POSTED WRITE
CS
RD
WR
A[15:0]
Address
Address+1
Address+2
Address+3
WAIT_ACK
(initially active if prior
write pending)
(initially active due
to write pending)
D[15:8]
D[7:0]
DS00003422A-page 120
(initially active due
to write pending)
(initially active due
to write pending)
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
2020 Microchip Technology Inc.
LAN9254
8-BIT MODE NON-POSTED WRITE
The BYTE address is input concurrently with the control.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (second example).
Data on D[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. D[15:8] pins are not used or driven.
For EtherCAT Core registers and the Process RAM, the write cycle occurs during WR active. For-non EtherCAT Core
registers, the write cycle occurs upon WR inactive. Therefore Data is held until WR inactive.
The cycle is repeated for the other BYTEs of the DWORD if required.
FIGURE 8-55:
DEMULTIPLEXED ADDRESSING - 8-BIT NON-POSTED WRITE
CS
RD
WR
A[15:0]
Address
Address+1
Address+2
Address+3
WAIT_ACK
(initially active
due to write)
(initially active
due to write)
D[15:8]
D[7:0]
2020 Microchip Technology Inc.
(initially active
due to write)
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
DS00003422A-page 121
LAN9254
8.6.3
INDEXED ADDRESS MODE FUNCTIONAL TIMING DIAGRAMS
The following timing diagrams illustrate example indexed (non-multiplexed) addressing mode read and write cycles for
various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are
selected to detail the main configuration differences (bus size, Configuration / Index / Data cycles) within the indexed
addressing mode of operation.
The following should be noted for the timing diagrams in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high CS, RD, and WR signals.
The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI Chip Select Polarity, HBI Read,
Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on page 69 for additional details.
• The diagrams in this section depict little endian byte ordering. However, configurable big and little endianness are
supported for 16-bit mode via the endianness bits in the Host Bus Interface Configuration Register. Endianness
changes only the order of the bytes involved, and not the overall timing requirements. Refer to Section 8.4.4,
"Host Endianness," on page 79 for additional information.
• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,
similar to the Indexed examples in Section 8.5.3.4, "RD_WR / ENB Control Mode Examples". The HBI read/write
mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register. The polarities of the
RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity and HBI Write, Enable Polarity
configuration inputs.
• While accessing non-EtherCAT Core registers, for proper DWORD assembly, consecutive address cycles must be
within the same DWORD until the DWORD is completely accessed (some internal registers are excluded from this
requirement). Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict
accessing the lower address BYTE or WORD first.
• While accessing index and configuration registers in 16-bit mode, all cycles are 16-bit wide with the internal BE1/
BE0 unused. While accessing non-EtherCAT Core registers in 16-bit mode, all cycles are 16-bit wide with the
internal BE1/BE0 unused.While accessing EtherCAT Core registers and the Process RAM in 16-bit mode, 8 or 16bit transfers can be selected via the internal BE1/BE0.
8.6.3.1
Configuration Register Data Access
The figures in this section detail Configuration register read and write operations in indexed address mode for 16 and
8-bit modes.
16-BIT MODE READ AND WRITE
Posted Writes
For posted writes, the address is set to access the Configuration Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (third example).
Data on D[15:0] is written on the trailing edge of WR.
The cycle repeats for the other WORD of the Configuration Register, if desired by the host.
Non-Posted Writes
For non-posted writes, the address is set to access the Configuration Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (fifth example).
Data on D[15:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. The write cycle occurs upon WR inactive, therefore Data is held until WR inactive.
The cycle repeats for the other WORD of the Configuration Register, if desired by the host.
Reads
For reads, the address is set to access the Configuration Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (second example).
DS00003422A-page 122
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LAN9254
D[15:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive.
The cycle repeats for the other WORD of the Configuration Register, if desired by the host.
FIGURE 8-56:
INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 16-BIT
POSTED WRITE / NON-POSTED WRITE / READ
Posted Write
A[4:1]
CONFIG,1'b0
Non-Posted Write
CONFIG,1'b1
CONFIG,1'b0
Read
CONFIG,1'b1
CONFIG,1'b0
CONFIG,1'b1
CS
RD
WR
WAIT_ACK
(initially active if prior
w rite pending)
(initially active due
to write pending)
(initially active
due to write)
(initially active if
prior w rite pending)
(initially active
due to rd)
D[15:8]
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
8-BIT MODE READ AND WRITE
Posted Writes
For posted writes, the address is set to access the Configuration Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven.
The cycle repeats for the remaining BYTEs of the Configuration Register, if desired by the host. The first and last BYTEs
are shown here.
Non-Posted Writes
For non-posted writes, the address is set to access the Configuration Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (fourth example).
Data on D[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. D[15:8] pins are not used or driven. The write cycle occurs upon WR inactive, therefore Data is held until WR
inactive.
The cycle repeats for the remaining BYTEs of the Configuration Register, if desired by the host. The first and last BYTEs
are shown here.
Reads
For reads, the address is set to access the Configuration Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (sixth example).
D[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive. D[15:8] pins are not used
or driven.
2020 Microchip Technology Inc.
DS00003422A-page 123
LAN9254
The cycle repeats for the remaining BYTEs of the Configuration Register, if desired by the host. The first and last BYTEs
are shown here.
FIGURE 8-57:
INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 8-BIT POSTED
WRITE / NON-POSTED WRITE / READ
Posted Write
A[4:0]
CONFIG,2'b00
Non-Posted Write
CONFIG,2'b11
CONFIG,2'b00
Read
CONFIG,2'b11
CONFIG,2'b00
CONFIG,2'b11
CS
RD
WR
WAIT_ACK
(initially active if prior
w rite pending)
(initially active due
to write pending)
(initially active
due to write)
(initially active
due to rd)
Hi-Z
D[15:8]
D[7:0]
8.6.3.2
(initially active if
prior w rite pending)
Data 7:0
Data 31:24
Data 7:0
Data 31:24
Data 7:0
Data 31:24
Index Register Data Access
The figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit
modes.
16-BIT MODE READ AND WRITE
Posted Writes
For posted writes, the address is set to access one of the Index Registers.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[15:0] is written on the trailing edge of WR.
The cycle repeats for the other WORD of the Index Register, if desired by the host.
Non-Posted Writes
For non-posted writes, the address is set to access one of the Index Registers.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (fourth example).
Data on D[15:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. The write cycle occurs upon WR inactive, therefore Data is held until WR inactive.
The cycle repeats for the other WORD of the Index Register, if desired by the host.
Reads
For reads, the address is set to access one of the Index Registers.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (sixth example).
D[15:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive.
The cycle repeats for the other WORD of the Index Register, if desired by the host.
Note:
The upper BYTE of Index Register is reserved and don’t care.
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LAN9254
FIGURE 8-58:
INDEXED ADDRESSING INDEX REGISTER ACCESS - 16-BIT POSTED WRITE /
NON-POSTED WRITE / READ
Posted Write
A[4:1]
INDEX,1'b0
Non-Posted Write
INDEX,1'b1
INDEX,1'b0
Read
INDEX,1'b1
INDEX,1'b0
INDEX,1'b1
CS
RD
WR
WAIT_ACK
(initially active if prior
w rite pending)
(initially active due
to write pending)
(initially active
due to write)
(initially active if
prior w rite pending)
(initially active
due to rd)
D[15:8]
Data 15:8
8'hXX
Data 15:8
8'hXX
Data 15:8
8'hXX
D[7:0]
Data 7:0
Data 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
8-BIT MODE READ AND WRITE
Posted Writes
For posted writes, the address is set to access one of the Index Registers.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven.
The cycle repeats for the remaining BYTEs of the Index Register, if desired by the host. The first and second BYTEs
are shown here.
Non-Posted Writes
For non-posted writes, the address is set to access one of the Index Registers.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (fourth example).
Data on D[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. D[15:8] pins are not used or driven. The write cycle occurs upon WR inactive, therefore Data is held until WR
inactive.
The cycle repeats for the remaining BYTEs of the Index Register, if desired by the host. The first and second BYTEs
are shown here.
Reads
For reads, the address is set to access one of the Index Registers.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (sixth example).
D[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive. D[15:8] pins are not used
or driven.
The cycle repeats for the remaining BYTEs of the Index Register, if desired by the host. The first and second BYTEs
are shown here.
Note:
The upper BYTE of Index Register is reserved and don’t care. Therefore reads and writes to that BYTE is
not useful.
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DS00003422A-page 125
LAN9254
FIGURE 8-59:
INDEXED ADDRESSING INDEX REGISTER ACCESS - 8-BIT POSTED WRITE /
NON-POSTED WRITE / READ
Posted Write
A[4:0]
INDEX,2'b00
Non-Posted Write
INDEX,2'b01
INDEX,2'b00
Read
INDEX,2'b01
INDEX,2'b00
INDEX,2'b01
CS
RD
WR
WAIT_ACK
(initially active if prior
w rite pending)
(initially active due
to write pending)
(initially active
due to write)
(initially active
due to rd)
Hi-Z
D[15:8]
D[7:0]
8.6.3.3
(initially active if
prior w rite pending)
Data 7:0
Data 15:8
Data 7:0
Data 15:8
Data 7:0
Data 15:8
Internal Register Data Access
The figures in this section detail typical internal register data read and write cycles in indexed address mode for 16 and
8-bit modes. Although not shown here, a data read or write is usually preceded by an index register write.
16-BIT MODE READ AND WRITE
One of the Index Registers is set as described above.
Posted Writes
For posted writes, the address is then set to access the corresponding Data Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[15:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven.
The cycle repeats for the other WORD of the Data Register, if required.
Non-Posted Writes
For non-posted writes, the address is then set to access the corresponding Data Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (fourth example).
Data on D[15:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. D[15:8] pins are not used or driven. The write cycle occurs upon WR inactive, therefore Data is held until WR
inactive.
The cycle repeats for the other WORD of the Data Register, if required.
Reads
For reads, the address is then set to access the corresponding Data Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (sixth example).
D[15:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive.
The cycle repeats for the other WORD of the Data Register, if required.
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LAN9254
FIGURE 8-60:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT POSTED
WRITE / NON-POSTED WRITE / READ
Posted Write
A[4:1]
DATA,1'b0
Non-Posted Write
DATA,1'b1
DATA,1'b0
Read
DATA,1'b1
DATA,1'b0
DATA,1'b1
CS
RD
WR
WAIT_ACK
(initially active if prior
w rite pending)
(initially active due
to write pending)
(initially active
due to write)
(initially active if
prior w rite pending)
(initially active
due to rd)
D[15:8]
Data 15:8
Data 31:24
Data 15:8
Data 31:24
Data 15:8
Data 31:24
D[7:0]
Data 7:0
Data 23:16
Data 7:0
Data 23:16
Data 7:0
Data 23:16
8-BIT MODE READ AND WRITE
One of the Index Registers is set as described above.
Posted Writes
For posted writes, the address is then set to access the corresponding Data Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon WR inactive. CS and WR may become inactive simultaneously in which case WAIT_ACK active is not seen (second example).
Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven.
The cycle repeats for the remaining BYTEs of the Data Register, if required. The first and last BYTEs are shown here.
Non-Posted Writes
For non-posted writes, the address is then set to access the corresponding Data Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven inactive since there will never be a prior pending
write. WAIT_ACK is driven active upon WR active. CS and WR may become active simultaneously in which case
WAIT_ACK is always initially driven active (fourth example).
Data on D[7:0] is written starting on the leading edge of WR. WR may be made inactive once WAIT_ACK becomes
inactive. D[15:8] pins are not used or driven. The write cycle occurs upon WR inactive, therefore Data is held until WR
inactive.
The cycle repeats for the remaining BYTEs of the Data Register, if required. The first and last BYTEs are shown here.
Reads
For reads, the address is then set to access the corresponding Data Register.
WAIT_ACK is driven upon CS active. WAIT_ACK is initially driven active if there was a prior pending write, otherwise
it is initially driven inactive. WAIT_ACK is driven active upon RD active. CS and RD may become active simultaneously
in which case WAIT_ACK is always initially driven active (sixth example).
D[7:0] are driven active on during RD active and valid once WAIT_ACK becomes inactive. D[15:8] pins are not used
or driven.
The cycle repeats for the remaining BYTEs of the Data Register, if required. The first and last BYTEs are shown here.
2020 Microchip Technology Inc.
DS00003422A-page 127
LAN9254
FIGURE 8-61:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT POSTED
WRITE / NON-POSTED WRITE / READ
Posted Write
A[4:0]
DATA,2'b00
Non-Posted Write
DATA,2'b11
DATA,2'b00
Read
DATA,2'b11
DATA,2'b00
DATA,2'b11
CS
RD
WR
WAIT_ACK
(initially active if prior
w rite pending)
(initially active due
to write pending)
(initially active
due to write)
8.7
8.7.1
(initially active
due to rd)
Hi-Z
D[15:8]
D[7:0]
(initially active if
prior w rite pending)
Data 7:0
Data 31:24
Data 7:0
Data 31:24
Data 7:0
Data 31:24
Timing Requirements
MULTIPLEXED ADDRESSING MODE TIMING REQUIREMENTS
The following figures and tables specify the timing requirements during Multiplexed Address / Data mode. Since timing
requirements are similar across the multitude of operations (e.g. dual vs. single phase, 8 vs. 16-bit), many timing
requirements are illustrated onto the same figures and do not necessarily represent any particular functional operation.
The following should be noted for the timing specifications in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high ALEHI/ALELO, CS, RD,
WR, RD_WR and ENB signals. The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI
ALE Polarity, HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the
PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer
Type," on page 69 for additional details.
• Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI ALE Qualification bit of the
PDI Configuration Register. This is shown as a dashed line. Timing requirements between ALELO / ALEHI and
CS only apply when this mode is active.
• In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. ALEHI first is depicted
in solid line. ALELO first is depicted in dashed line.
• A read cycle may be followed by followed by an address cycle, a write cycle or another read cycle. A write cycle
may be followed by followed by an address cycle, a read cycle or another write cycle. These are shown in dashed
line.
DS00003422A-page 128
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LAN9254
8.7.1.1
Read Timing Requirements - Legacy Mode
The following sections present timing requirements while in LAN9252 compatible Legacy mode (i.e. not in EtherCAT
Direct Mapped mode). Byte Enables BE1/BE0 are not used in Legacy mode and are not shown. If enabled for output,
WAIT_ACK is held inactive (ACK) and is shown as such.
If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD
is deasserted. CS may be asserted and deasserted along with RD but not during RD active.
Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and
RD_WR indicating a read. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.5.1, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 82 for functional
descriptions.
FIGURE 8-62:
MULTIPLEXED ADDRESSING READ CYCLE TIMING
tcsale
tcsrd
trdcs
CS
twale
trdale
ALEHI
taleale
trdale
ALELO
tadrs
tadrh
AD[7:0] input
AD[15:8] input
RD_WR
trdwrs
talerd
trdwrh
t rd
trdcyc
trdrd
ENB, RD
trdwr
WR
taledv
trdon, tcson
t rddv, tcsdv
trddh, tcsdh
trddz, tcsdz
AD[15:8] output
AD[7:0] output
tcswa
tcswa
tcswaz
WAIT_ACK
2020 Microchip Technology Inc.
DS00003422A-page 129
LAN9254
TABLE 8-4:
MULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsale
CS Setup to ALELO, ALEHI Active
Note 3, Note 2
0
nS
tcsrd
CS Setup to RD or ENB Active
0
nS
trdcs
CS Hold from RD or ENB Inactive
0
nS
twale
ALELO, ALEHI Pulse Width
10
nS
tadrs
Address Setup to ALELO, ALEHI Inactive
10
nS
tadrh
Address Hold from ALELO, ALEHI Inactive
5
nS
taleale
ALELO Inactive to ALEHI Active
ALEHI Inactive to ALELO Active
Note 1, Note 2
0
nS
talerd
ALELO, ALEHI Inactive to RD or ENB Active
Note 2
5
nS
trdwrs
RD_WR Setup to ENB Active
Note 4
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 4
5
nS
trdon
RD or ENB to Data Buffer Turn On
0
nS
trddv
RD or ENB Active to Data Valid
trddh
Data Output Hold Time from RD or ENB Inactive
trddz
Data Buffer Turn Off Time from RD or ENB Inactive
tcson
CS to Data Buffer Turn On
tcsdv
CS Active to Data Valid
tcsdh
Data Output Hold Time from CS Inactive
tcsdz
Data Buffer Turn Off Time from CS Inactive
9
nS
taledv
ALELO, ALEHI Inactive to Data Valid
Note 2
35
nS
30
0
nS
nS
9
0
nS
nS
30
0
nS
nS
trd
RD or ENB Active Time
32
nS
trdcyc
RD or ENB Cycle Time
45
nS
trdale
RD or ENB De-assertion Time before Address Phase
13
nS
trdrd
RD or ENB De-assertion Time before Next RD or ENB
Note 5
13
nS
trdwr
RD De-assertion Time before Next WR
Note 5, Note 6
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
DS00003422A-page 130
2020 Microchip Technology Inc.
LAN9254
Note 1: Dual Phase Addressing
Note 2: Depends on ALEHI / ALELO order.
Note 3: ALELO and/or ALEHI qualified with the CS.
Note 4: RD_WR and ENB signaling.
Note 5: No interposed address phase.
Note 6: RD and WR signaling.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
2020 Microchip Technology Inc.
DS00003422A-page 131
LAN9254
8.7.1.2
Read Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when data is valid to be captured, otherwise the host must assume
the worst case data access time listed.
WAIT_ACK is output with CS active and if not already active due to a pending prior write, becomes active upon RD or
ENB. If CS and RD/ENB are concurrent, WAIT_ACK is driven active.
If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD
is deasserted. CS may be asserted and deasserted along with RD but not during RD active.
Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and
RD_WR indicating a read. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.1, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 104 for functional
descriptions.
FIGURE 8-63:
MULTIPLEXED ADDRESSING READ CYCLE TIMING
tcsale
tcsrd
trdcs
CS
twale
trdale
ALEHI
taleale
trdale
ALELO
tadrs
tadrh
AD[7:0] input
AD[15:8] input
tbes
tbeh
BE[1:0]
RD_WR
trdwrs
trdwrh
talerd
trdrd
ENB, RD
trdwr
WR
tcson
tread
trdon
twadv
trddh, tcsdh
trddz, tcsdz
AD[15:8] output
AD[7:0] output
tcswa
tcswa
trdwa
tdvwa
tcswaz
WAIT_ACK
(with pending
prior write)
DS00003422A-page 132
(delayed
WAIT_ACK)
2020 Microchip Technology Inc.
LAN9254
TABLE 8-5:
MULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsale
CS Setup to ALELO, ALEHI Active
Note 9, Note 8
0
nS
tcsrd
CS Setup to RD or ENB Active
0
nS
trdcs
CS Hold from RD or ENB Inactive
0
nS
twale
ALELO, ALEHI Pulse Width
10
nS
tadrs
Address Setup to ALELO, ALEHI Inactive
10
nS
tadrh
Address Hold from ALELO, ALEHI Inactive
5
nS
taleale
ALELO Inactive to ALEHI Active
ALEHI Inactive to ALELO Active
Note 7, Note 8
0
nS
talerd
ALELO, ALEHI Inactive to RD or ENB Active
Note 8
5
nS
tbes
Byte Enable Setup to RD or ENB Active
0
nS
tbeh
Byte Enable Hold from RD or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 10
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 10
5
nS
trdon
RD or ENB to Data Buffer Turn On
0
nS
trddh
Data Output Hold Time from RD or ENB Inactive
0
nS
trddz
Data Buffer Turn Off Time from RD or ENB Inactive
tcson
CS to Data Buffer Turn On
0
nS
tcsdh
Data Output Hold Time from CS Inactive
0
nS
tcsdz
Data Buffer Turn Off Time from CS Inactive
trdale
RD or ENB De-assertion Time before Address Phase
13
nS
trdrd
RD or ENB De-assertion Time before Next RD or ENB
Note 10
13
nS
trdwr
RD De-assertion Time before Next WR
Note 11, Note 12
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
trdwa
RD or ENB Active to WAIT_ACK Active
10
nS
2020 Microchip Technology Inc.
9
9
nS
nS
DS00003422A-page 133
LAN9254
TABLE 8-5:
MULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
tread
Description
Max
Units
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- no pending prior write
Note 13
235
nS
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- 8-bit pending prior write
Note 13
435
nS
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- 16-bit pending prior write
Note 13
495
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- no pending prior write
Note 13
315
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- 8-bit pending prior write
Note 13
515
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- 16-bit pending prior write
Note 13
575
nS
5
nS
twadv
WAIT_ACK Inactive to Data Valid - normal WAIT_ACK
tdvwa
Data Valid Before WAIT_ACK Inactive - delayed
WAIT_ACK
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
Min
Typ
15
nS
9
nS
Note 7: Dual Phase Addressing
Note 8: Depends on ALEHI / ALELO order.
Note 9: ALELO and/or ALEHI qualified with the CS.
Note 10: RD_WR and ENB signaling.
Note 11: No interposed address phase.
Note 12: RD and WR signaling.
Note 13: Add 20nS if delayed WAIT_ACK is enabled.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
DS00003422A-page 134
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LAN9254
8.7.1.3
Write Timing Requirements - Legacy Mode
The following sections present timing requirements while in LAN9252 compatible Legacy mode (i.e. not in EtherCAT
Direct Mapped mode). Byte Enables BE1/BE0 are not used in Legacy mode and are not shown. If enabled for output,
WAIT_ACK is held inactive (ACK) and is shown as such.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.5.1, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 82 for functional
descriptions.
FIGURE 8-64:
MULTIPLEXED ADDRESSING WRITE CYCLE TIMING
tcsale
tcswr
twrcs
CS
twale
twrale
ALEHI
taleale
twrale
ALELO
tadrs
tadrh
AD[7:0] input
AD[15:8] input
RD_WR
tds
tdh
trdwrh
trdwrs
talewr
twr
twrcyc
twrwr
ENB, WR
twrrd
RD
tcswa
tcswa
tcswaz
WAIT_ACK
2020 Microchip Technology Inc.
DS00003422A-page 135
LAN9254
TABLE 8-6:
MULTIPLEXED ADDRESSING WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsale
CS Setup to ALELO, ALEHI Active
Note 16, Note 15
0
nS
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
twale
ALELO, ALEHI Pulse Width
10
nS
tadrs
Address Setup to ALELO, ALEHI Inactive
10
nS
tadrh
Address Hold from ALELO, ALEHI Inactive
5
nS
taleale
ALELO Inactive to ALEHI Active
ALEHI Inactive to ALELO Active
Note 14, Note 15
0
nS
talewr
ALELO, ALEHI Inactive to WR or ENB Active
Note 15
5
nS
trdwrs
RD_WR Setup to ENB Active
Note 17
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 17
5
nS
tds
Data Setup to WR or ENB Inactive
10
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twr
WR or ENB Active Time
32
nS
twrcyc
WR or ENB Cycle Time
45
nS
twrale
WR or ENB De-assertion Time before Address Phase
13
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
Note 18
13
nS
twrrd
WR De-assertion Time before Next RD
Note 18, Note 19
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
Note 14: Dual Phase Addressing
Note 15: Depends on ALEHI / ALELO order.
Note 16: ALELO and/or ALEHI qualified with the CS.
Note 17: RD_WR and ENB signaling.
Note 18: No interposed address phase.
Note 19: RD and WR signaling.
DS00003422A-page 136
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LAN9254
8.7.1.4
Posted Write Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when the write cycle may be concluded, otherwise the host must
assume the worst case write access time listed.
WAIT_ACK is output with CS active and will be active if there was a pending prior write. Otherwise it will be inactive.
The write strobe (WR or ENB) may be made active. Once WAIT_ACK is inactive the write strobe may be made inactive.
WAIT_ACK becomes active upon an inactive WR or ENB. If CS and WD/ENB become inactive concurrently,
WAIT_ACK is released and the active state may not be seen.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.1, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 104 for functional
descriptions.
FIGURE 8-65:
MULTIPLEXED ADDRESSING POSTED WRITE CYCLE TIMING
tcsale
tcswr
twrcs
CS
twale
twrale
ALEHI
taleale
twrale
ALELO
tadrs
tadrh
AD[7:0] input
AD[15:8] input
tbes
tbeh
BE[1:0]
RD_WR
tds
tdh
trdwrh
trdwrs
talewr
twr
twrcyc
twrwr
ENB, WR
twrite
twawr
twrrd
RD
tcswa
tcswa
twrwa
tcswaz
WAIT_ACK
(with pending prior
write)
2020 Microchip Technology Inc.
DS00003422A-page 137
LAN9254
TABLE 8-7:
MULTIPLEXED ADDRESSING POSTED WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsale
CS Setup to ALELO, ALEHI Active
Note 22, Note 21
0
nS
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
twale
ALELO, ALEHI Pulse Width
10
nS
tadrs
Address Setup to ALELO, ALEHI Inactive
10
nS
tadrh
Address Hold from ALELO, ALEHI Inactive
5
nS
taleale
ALELO Inactive to ALEHI Active
ALEHI Inactive to ALELO Active
Note 20, Note 21
0
nS
talewr
ALELO, ALEHI Inactive to WR or ENB Active Note 21
5
nS
tbes
Byte Enable Setup to WR or ENB Active
0
nS
tbeh
Byte Enable Hold from WR or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active Note 23
5
nS
trdwrh
RD_WR Hold from ENB Inactive Note 23
5
nS
tds
Data Setup to WR or ENB Inactive
10
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twr
WR or ENB Active Time
- no pending prior write
32
nS
twrcyc
WR or ENB Cycle Time
- no pending prior write
45
nS
twrale
WR or ENB De-assertion Time before Address Phase
13
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
Note 24
13
nS
twrrd
WR De-assertion Time before Next RD
Note 24, Note 25
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
WR or ENB Active to WAIT_ACK Inactive
- pending prior 8-bit write
200
nS
WR or ENB Active to WAIT_ACK Inactive
- pending prior 16-bit write
280
nS
twrite
twawr
WAIT_ACK Inactive to WR or ENB Inactive
twrwa
WR or ENB Inactive to WAIT_ACK Active
Note 26
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
DS00003422A-page 138
0
nS
2020 Microchip Technology Inc.
LAN9254
Note 20: Dual Phase Addressing
Note 21: Depends on ALEHI / ALELO order.
Note 22: ALELO and/or ALEHI qualified with the CS.
Note 23: RD_WR and ENB signaling.
Note 24: No interposed address phase.
Note 25: RD and WR signaling.
Note 26: If not three-stated first.
8.7.1.5
Non-Posted Write Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when the write cycle may be concluded, otherwise the host must
assume the worst case write access time listed.
WAIT_ACK is output with CS active. It will be initially inactive and becomes active with write strobe (WR or ENB) active.
Once WAIT_ACK is inactive the write strobe may be made inactive.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.1, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 104 for functional
descriptions.
FIGURE 8-66:
MULTIPLEXED ADDRESSING NON-POSTED WRITE CYCLE TIMING
tcsale
tcswr
twrcs
CS
twale
twrale
ALEHI
taleale
twrale
ALELO
tadrs
tadrh
AD[7:0] input
AD[15:8] input
tbes
tbeh
BE[1:0]
RD_WR
tds
tdh
trdwrs
trdwrh
t alewr
twrwr
ENB, WR
twrite
twawr
twrrd
RD
tcswa
tcswa
twrwa
tcswaz
WAIT_ACK
2020 Microchip Technology Inc.
DS00003422A-page 139
LAN9254
TABLE 8-8:
MULTIPLEXED ADDRESSING NON-POSTED WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsale
CS Setup to ALELO, ALEHI Active
Note 29, Note 28
0
nS
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
twale
ALELO, ALEHI Pulse Width
10
nS
tadrs
Address Setup to ALELO, ALEHI Inactive
10
nS
tadrh
Address Hold from ALELO, ALEHI Inactive
5
nS
taleale
ALELO Inactive to ALEHI Active
ALEHI Inactive to ALELO Active
Note 27, Note 28
0
nS
talewr
ALELO, ALEHI Inactive to WR or ENB Active
Note 28
5
nS
tbes
Byte Enable Setup to WR or ENB Active
0
nS
tbeh
Byte Enable Hold from WR or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 30
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 30
5
nS
tds
Data Setup to WR or ENB Active
0
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twrale
WR or ENB De-assertion Time before Address Phase
13
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
Note 31
13
nS
twrrd
WR De-assertion Time before Next RD
Note 31, Note 32
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
twrwa
WR or ENB Active to WAIT_ACK Active
10
nS
WR or ENB Active to WAIT_ACK Inactive
- 8-bit write
200
nS
WR or ENB Active to WAIT_ACK Inactive
- 16-bit write
280
nS
twrite
twawr
WAIT_ACK Inactive to WR or ENB Inactive
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
0
nS
9
nS
Note 27: Dual Phase Addressing
Note 28: Depends on ALEHI / ALELO order.
DS00003422A-page 140
2020 Microchip Technology Inc.
LAN9254
Note 29: ALELO and/or ALEHI qualified with the CS.
Note 30: RD_WR and ENB signaling.
Note 31: No interposed address phase.
Note 32: RD and WR signaling.
8.7.2
DEMULTIPLEXED ADDRESSING MODE TIMING REQUIREMENTS
The following figures and tables specify the timing requirements during Demultiplexed Address mode. Since timing
requirements are similar across the multitude of operations (8 vs. 16-bit), many timing requirements are illustrated onto
the same figures and do not necessarily represent any particular functional operation.
The following should be noted for the timing specifications in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high CS, RD, and WR signals.
The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI Chip Select Polarity, HBI Read,
Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on page 69 for additional details.
• A read cycle may be followed by followed by a write cycle or another read cycle. A write cycle may be followed by
a read cycle or another write cycle. These are shown in dashed line.
8.7.2.1
Read Timing Requirements - Legacy Mode
The following sections present timing requirements while in LAN9252 compatible Legacy mode (i.e. not in EtherCAT
Direct Mapped mode). Byte Enables BE1/BE0 are not used in Legacy mode and are not shown. If enabled for output,
WAIT_ACK is held inactive (ACK) and is shown as such.
If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD
is deasserted. CS may be asserted and deasserted along with RD but not during RD active.
Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and
RD_WR indicating a read. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.5.2, "Demultiplexed Addressing Mode Functional Timing Diagrams," on page 93 for functional
descriptions.
FIGURE 8-67:
DEMULTIPLEXED ADDRESSING READ CYCLE TIMING
tcsrd
trdcs
tas
tah
CS
A[15:0], END_SEL
RD_WR
trdwrs
trdwrh
trd
trdcyc
trdrd
ENB, RD
trdwr
WR
tadv
trdon, tcson
trddv, tcsdv
trddh, tcsdh
trddz, tcsdz
D[15:8]
D[7:0]
tcswa
tcswaz
WAIT_ACK
2020 Microchip Technology Inc.
DS00003422A-page 141
LAN9254
TABLE 8-9:
DEMULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsrd
CS Setup to RD or ENB Active
0
nS
trdcs
CS Hold from RD or ENB Inactive
0
nS
tas
Address, END_SEL Setup to RD or ENB Active
0
nS
tah
Address, END_SEL Hold from RD or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 33
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 33
5
nS
trdon
RD or ENB to Data Buffer Turn On
0
nS
trddv
RD or ENB Active to Data Valid
trddh
Data Output Hold Time from RD or ENB Inactive
trddz
Data Buffer Turn Off Time from RD or ENB Inactive
tcson
CS to Data Buffer Turn On
tcsdv
CS Active to Data Valid
tcsdh
Data Output Hold Time from CS Inactive
tcsdz
Data Buffer Turn Off Time from CS Inactive
9
nS
tadv
Address, END_SEL to Data Valid
30
nS
trd
RD or ENB Active Time
32
nS
trdcyc
RD or ENB Cycle Time
45
nS
trdrd
RD or ENB De-assertion Time before Next RD or ENB
13
nS
trdwr
RD De-assertion Time before Next WR
Note 34
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
30
0
nS
nS
9
0
nS
nS
30
0
nS
nS
Note 33: RD_WR and ENB signaling.
Note 34: RD and WR signaling.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
DS00003422A-page 142
2020 Microchip Technology Inc.
LAN9254
8.7.2.2
Read Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when data is valid to be captured, otherwise the host must assume
the worst case data access time listed.
WAIT_ACK is output with CS active and if not already active due to a pending prior write, becomes active upon RD or
ENB. If CS and RD/ENB are concurrent, WAIT_ACK is driven active.
If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD
is deasserted. CS may be asserted and deasserted along with RD but not during RD active.
Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and
RD_WR indicating a read. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.2, "Demultiplexed Addressing Mode Functional Timing Diagrams," on page 115 for functional
descriptions.
FIGURE 8-68:
DEMULTIPLEXED ADDRESSING READ CYCLE TIMING
tcsrd
trdcs
CS
tas
A[15:0], BE[1:0],
END_SEL
tah
RD_WR
trdwrs
trdwrh
trdrd
ENB, RD
trdwr
WR
tcson
tread
trdon
twadv
trddh, tcsdh
trddz, tcsdz
D[15:8]
D[7:0]
tcswa
trdwa
tdvwa
tcswaz
WAIT_ACK
(with pending
prior write)
2020 Microchip Technology Inc.
(delayed
WAIT_ACK)
DS00003422A-page 143
LAN9254
TABLE 8-10:
DEMULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsrd
CS Setup to RD or ENB Active
0
nS
trdcs
CS Hold from RD or ENB Inactive
0
nS
tas
Address, Byte Enable, END_SEL Setup to RD or ENB
Active
0
nS
tah
Address, Byte Enable, END_SEL Hold from RD or ENB
Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 35
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 35
5
nS
trdon
RD or ENB to Data Buffer Turn On
0
nS
trddh
Data Output Hold Time from RD or ENB Inactive
0
nS
trddz
Data Buffer Turn Off Time from RD or ENB Inactive
tcson
CS to Data Buffer Turn On
0
nS
tcsdh
Data Output Hold Time from CS Inactive
0
nS
tcsdz
Data Buffer Turn Off Time from CS Inactive
trdrd
RD or ENB De-assertion Time before Next RD or ENB
13
nS
trdwr
RD De-assertion Time before Next WR
Note 36
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
trdwa
RD or ENB Active to WAIT_ACK Active
10
nS
DS00003422A-page 144
9
9
nS
nS
2020 Microchip Technology Inc.
LAN9254
TABLE 8-10:
tread
DEMULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES (CONTINUED)
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- no pending prior write
Note 37
235
nS
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- 8-bit pending prior write
Note 37
435
nS
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- 16-bit pending prior write
Note 37
495
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- no pending prior write
Note 37
315
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- 8-bit pending prior write
Note 37
515
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- 16-bit pending prior write
Note 37
575
nS
5
nS
twadv
WAIT_ACK Inactive to Data Valid - normal WAIT_ACK
tdvwa
Data Valid Before WAIT_ACK Inactive - delayed
WAIT_ACK
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
15
nS
9
nS
Note 35: RD_WR and ENB signaling.
Note 36: RD and WR signaling.
Note 37: Add 20nS if delayed WAIT_ACK is enabled.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
2020 Microchip Technology Inc.
DS00003422A-page 145
LAN9254
8.7.2.3
Write Timing Requirements - Legacy Mode
The following sections present timing requirements while in LAN9252 compatible Legacy mode (i.e. not in EtherCAT
Direct Mapped mode). Byte Enables BE1/BE0 are not used in Legacy mode and are not shown. If enabled for output,
WAIT_ACK is held inactive (ACK) and is shown as such.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.5.2, "Demultiplexed Addressing Mode Functional Timing Diagrams," on page 93 for functional
descriptions.
FIGURE 8-69:
DEMULTIPLEXED ADDRESSING WRITE CYCLE TIMING
tcswr
twrcs
tas
tah
CS
A[15:0], END_SEL
D[15:8]
D[7:0]
RD_WR
tds
trdwrs
tdh
trdwrh
twr
twrcyc
twrwr
ENB, WR
twrrd
RD
tcswa
tcswaz
WAIT_ACK
DS00003422A-page 146
2020 Microchip Technology Inc.
LAN9254
TABLE 8-11:
DEMULTIPLEXED ADDRESSING WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
tas
Address, END_SEL Setup to WR or ENB Active
0
nS
tah
Address, END_SEL Hold from WR or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 38
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 38
5
nS
tds
Data Setup to WR or ENB Inactive
10
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twr
WR or ENB Active Time
32
nS
twrcyc
WR or ENB Cycle Time
45
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
13
nS
twrrd
WR De-assertion Time before Next RD
Note 39
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
Note 38: RD_WR and ENB signaling.
Note 39: RD and WR signaling.
2020 Microchip Technology Inc.
DS00003422A-page 147
LAN9254
8.7.2.4
Posted Write Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when the write cycle may be concluded, otherwise the host must
assume the worst case write access time listed.
WAIT_ACK is output with CS active and will be active if there was a pending prior write. Otherwise it will be inactive.
The write strobe (WR or ENB) may be made active. Once WAIT_ACK is inactive the write strobe may be made inactive.
WAIT_ACK becomes active upon an inactive WR or ENB. If CS and WD/ENB become inactive concurrently,
WAIT_ACK is released and the active state may not be seen.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.2, "Demultiplexed Addressing Mode Functional Timing Diagrams," on page 115 for functional
descriptions.
FIGURE 8-70:
DEMULTIPLEXED ADDRESSING POSTED WRITE CYCLE TIMING
tcswr
twrcs
CS
tas
A[15:0], BE[1:0],
END_SEL
tah
D[15:8]
D[7:0]
RD_WR
trdwrs
twr
tds
tdh
trdwrh
twrwr
twrcyc
ENB, WR
twrite
twawr
twrrd
RD
tcswa
twrwa
tcswaz
WAIT_ACK
(with pending prior write)
DS00003422A-page 148
2020 Microchip Technology Inc.
LAN9254
TABLE 8-12:
DEMULTIPLEXED ADDRESSING POSTED WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
tas
Address, Byte Enable, END_SEL Setup to WR or ENB
Active
0
nS
tah
Address, Byte Enable, END_SEL Hold from WR or ENB
Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 40
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 40
5
nS
tds
Data Setup to WR or ENB Inactive
10
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twr
WR or ENB Active Time
- no pending prior write
32
nS
twrcyc
WR or ENB Cycle Time
- no pending prior write
45
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
13
nS
twrrd
WR De-assertion Time before Next RD
Note 41
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
WR or ENB Active to WAIT_ACK Inactive
- pending prior 8-bit write
200
nS
WR or ENB Active to WAIT_ACK Inactive
- pending prior 16-bit write
280
nS
twrite
twawr
WAIT_ACK Inactive to WR or ENB Inactive
twrwa
WR or ENB Inactive to WAIT_ACK Active
Note 42
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
0
nS
Note 40: RD_WR and ENB signaling.
Note 41: RD and WR signaling.
Note 42: If not three-stated first.
2020 Microchip Technology Inc.
DS00003422A-page 149
LAN9254
8.7.2.5
Non-Posted Write Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when the write cycle may be concluded, otherwise the host must
assume the worst case write access time listed.
WAIT_ACK is output with CS active. It will be initially inactive and becomes active with write strobe (WR or ENB) active.
Once WAIT_ACK is inactive the write strobe may be made inactive.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.2, "Demultiplexed Addressing Mode Functional Timing Diagrams," on page 115 for functional
descriptions.
FIGURE 8-71:
DEMULTIPLEXED ADDRESSING NON-POSTED WRITE CYCLE TIMING
tcswr
twrcs
CS
tas
A[15:0], BE[1:0],
END_SEL
tah
D[15:8]
D[7:0]
RD_WR
tds
tdh
trdwrs
trdwrh
twrwr
ENB, WR
twrite
twawr
twrrd
RD
tcswa
twrwa
tcswaz
WAIT_ACK
DS00003422A-page 150
2020 Microchip Technology Inc.
LAN9254
TABLE 8-13:
DEMULTIPLEXED ADDRESSING NON-POSTED WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
tas
Address, Byte Enable, END_SEL Setup to WR or ENB
Active
0
nS
tah
Address, Byte Enable, END_SEL Hold from WR or ENB
Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 43
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 43
5
nS
tds
Data Setup to WR or ENB Active
0
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
13
nS
twrrd
WR De-assertion Time before Next RD
Note 44
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
twrwa
WR or ENB Active to WAIT_ACK Active
10
nS
WR or ENB Active to WAIT_ACK Inactive
- 8-bit write
200
nS
WR or ENB Active to WAIT_ACK Inactive
- 16-bit write
280
nS
twrite
twawr
WAIT_ACK Inactive to WR or ENB Inactive
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
0
nS
9
nS
Note 43: RD_WR and ENB signaling.
Note 44: RD and WR signaling.
2020 Microchip Technology Inc.
DS00003422A-page 151
LAN9254
8.7.3
INDEXED ADDRESSING MODE TIMING REQUIREMENTS
The following figures and tables specify the timing requirements during Indexed Address mode. Since timing requirements are similar across the multitude of operations (e.g. 8 vs. 16-bit, Index vs. Configuration vs. Data registers, Index
Register Bypass FIFO Access), many timing requirements are illustrated onto the same figures and do not necessarily
represent any particular functional operation.
The following should be noted for the timing specifications in this section:
• The diagrams in this section depict active-low push-pull WAIT_ACK and active-high CS, RD, WR, RD_WR, and
ENB signals. The polarities of these signals are selectable via the HBI WAIT_ACK Polarity, HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI
Modes), respectively. Refer to Section 8.2.2, "Control Line Polarity and Buffer Type," on page 69 for additional
details.
• A read cycle may be followed by followed by a write cycle or another read cycle. A write cycle may be followed by
a read cycle or another write cycle. These are shown in dashed line.
8.7.3.1
Read Timing Requirements - Legacy Mode
The following sections present timing requirements while in LAN9252 compatible Legacy mode (i.e., not in EtherCAT
Direct Mapped mode). If enabled for output, WAIT_ACK is held inactive (ACK) and is shown as such.
If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD
is deasserted. CS may be asserted and deasserted along with RD but not during RD active.
Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and
RD_WR indicating a read. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.5.3, "Indexed Address Mode Functional Timing Diagrams," on page 97 for functional descriptions.
FIGURE 8-72:
INDEXED ADDRESSING READ CYCLE TIMING
tcsrd
trdcs
tas
tah
CS
A[4:0]
RD_WR
trdwrs
trdwrh
trd
trdcyc
trdrd
ENB, RD
trdwr
WR
tadv
trdon, tcson
trddv, tcsdv
trddh, tcsdh
trddz, tcsdz
D[15:8]
D[7:0]
tcswa
tcswaz
WAIT_ACK
DS00003422A-page 152
2020 Microchip Technology Inc.
LAN9254
TABLE 8-14:
INDEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsrd
CS Setup to RD or ENB Active
0
nS
trdcs
CS Hold from RD or ENB Inactive
0
nS
tas
Address Setup to RD or ENB Active
0
nS
tah
Address Hold from RD or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 45
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 45
5
nS
trdon
RD or ENB to Data Buffer Turn On
0
nS
trddv
RD or ENB Active to Data Valid
trddh
Data Output Hold Time from RD or ENB Inactive
trddz
Data Buffer Turn Off Time from RD or ENB Inactive
tcson
CS to Data Buffer Turn On
tcsdv
CS Active to Data Valid
tcsdh
Data Output Hold Time from CS Inactive
tcsdz
Data Buffer Turn Off Time from CS Inactive
9
nS
tadv
Address to Data Valid
30
nS
trd
RD or ENB Active Time
32
nS
trdcyc
RD or ENB Cycle Time
45
nS
trdrd
RD or ENB De-assertion Time before Next RD or ENB
13
nS
trdwr
RD De-assertion Time before Next WR
Note 46
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
30
0
nS
nS
9
0
nS
nS
30
0
nS
nS
Note 45: RD_WR and ENB signaling.
Note 46: RD and WR signaling.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
2020 Microchip Technology Inc.
DS00003422A-page 153
LAN9254
8.7.3.2
Read Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when data is valid to be captured, otherwise the host must assume
the worst case data access time listed.
WAIT_ACK is output with CS active and if not already active due to a pending prior write, becomes active upon RD or
ENB. If CS and RD/ENB are concurrent, WAIT_ACK is driven active.
If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD
is deasserted. CS may be asserted and deasserted along with RD but not during RD active.
Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and
RD_WR indicating a read. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.3, "Indexed Address Mode Functional Timing Diagrams," on page 122 for functional descriptions.
FIGURE 8-73:
INDEXED ADDRESSING READ CYCLE TIMING
tcsrd
trdcs
CS
tas
tah
A[4:0]
RD_WR
trdwrs
trdwrh
trdrd
ENB, RD
trdwr
WR
tcson
tread
trdon
twadv
trddh, tcsdh
trddz, tcsdz
D[15:8]
D[7:0]
tcswa
trdwa
tdvwa
tcswaz
WAIT_ACK
(with pending
prior write)
DS00003422A-page 154
(delayed
WAIT_ACK)
2020 Microchip Technology Inc.
LAN9254
TABLE 8-15:
INDEXED ADDRESSING READ CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcsrd
CS Setup to RD or ENB Active
0
nS
trdcs
CS Hold from RD or ENB Inactive
0
nS
tas
Address, END_SEL Setup to RD or ENB Active
0
nS
tah
Address, END_SEL Hold from RD or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 47
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 47
5
nS
trdon
RD or ENB to Data Buffer Turn On
0
nS
trddh
Data Output Hold Time from RD or ENB Inactive
0
nS
trddz
Data Buffer Turn Off Time from RD or ENB Inactive
tcson
CS to Data Buffer Turn On
0
nS
tcsdh
Data Output Hold Time from CS Inactive
0
nS
tcsdz
Data Buffer Turn Off Time from CS Inactive
trdrd
RD or ENB De-assertion Time before Next RD or ENB
13
nS
trdwr
RD De-assertion Time before Next WR
Note 48
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
trdwa
RD or ENB Active to WAIT_ACK Active
10
nS
2020 Microchip Technology Inc.
9
9
nS
nS
DS00003422A-page 155
LAN9254
TABLE 8-15:
tread
INDEXED ADDRESSING READ CYCLE TIMING VALUES (CONTINUED)
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- no pending prior write
Note 49
235
nS
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- 8-bit pending prior write
Note 49
435
nS
RD or ENB Active to WAIT_ACK Inactive
- 8-bit read
- 16-bit pending prior write
Note 49
495
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- no pending prior write
Note 49
315
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- 8-bit pending prior write
Note 49
515
nS
RD or ENB Active to WAIT_ACK Inactive
- 16-bit read
- 16-bit pending prior write
Note 49
575
nS
5
nS
twadv
WAIT_ACK Inactive to Data Valid - normal WAIT_ACK
tdvwa
Data Valid Before WAIT_ACK Inactive - delayed
WAIT_ACK
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
15
nS
9
nS
Note 47: RD_WR and ENB signaling.
Note 48: RD and WR signaling.
Note 49: Add 20nS if delayed WAIT_ACK is enabled.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
DS00003422A-page 156
2020 Microchip Technology Inc.
LAN9254
8.7.3.3
Write Timing Requirements - Legacy Mode
The following sections present timing requirements while in LAN9252 compatible Legacy mode (i.e. not in EtherCAT
Direct Mapped mode). If enabled for output, WAIT_ACK is held inactive (ACK) and is shown as such.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.5.3, "Indexed Address Mode Functional Timing Diagrams," on page 97 for functional descriptions.
FIGURE 8-74:
INDEXED ADDRESSING WRITE CYCLE TIMING
tcswr
twrcs
tas
tah
CS
A[4:0]
D[15:8]
D[7:0]
RD_WR
t ds
tdh
trdwrh
trdwrs
twr
twrcyc
twrwr
ENB, WR
twrrd
RD
tcswa
tcswaz
WAIT_ACK
2020 Microchip Technology Inc.
DS00003422A-page 157
LAN9254
TABLE 8-16:
INDEXED ADDRESSING WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
tas
Address Setup to WR or ENB Active
0
nS
tah
Address Hold from WR or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 50
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 50
5
nS
tds
Data Setup to WR or ENB Inactive
10
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twr
WR or ENB Active Time
32
nS
twrcyc
WR or ENB Cycle Time
45
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
13
nS
twrrd
WR De-assertion Time before Next RD
Note 51
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
Note 50: RD_WR and ENB signaling.
Note 51: RD and WR signaling.
DS00003422A-page 158
2020 Microchip Technology Inc.
LAN9254
8.7.3.4
Posted Write Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when the write cycle may be concluded, otherwise the host must
assume the worst case write access time listed.
WAIT_ACK is output with CS active and will be active if there was a pending prior write. Otherwise it will be inactive.
The write strobe (WR or ENB) may be made active. Once WAIT_ACK is inactive the write strobe may be made inactive.
WAIT_ACK becomes active upon an inactive WR or ENB. If CS and WD/ENB become inactive concurrently,
WAIT_ACK is released and the active state may not be seen.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.3, "Indexed Address Mode Functional Timing Diagrams," on page 122 for functional descriptions.
FIGURE 8-75:
INDEXED ADDRESSING POSTED WRITE CYCLE TIMING
tcswr
twrcs
CS
tas
tah
A[4:0]
D[15:8]
D[7:0]
RD_WR
t ds
tdh
trdwrh
trdwrs
twr
twrcyc
twrwr
ENB, WR
twrite
twawr
twrrd
RD
tcswa
twrwa
tcswaz
WAIT_ACK
(with pending prior
write)
2020 Microchip Technology Inc.
DS00003422A-page 159
LAN9254
TABLE 8-17:
INDEXED ADDRESSING POSTED WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
tas
Address Setup to WR or ENB Active
0
nS
tah
Address Hold from WR or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 52
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 52
5
nS
tds
Data Setup to WR or ENB Inactive
10
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twr
WR or ENB Active Time
- no pending prior write
32
nS
twrcyc
WR or ENB Cycle Time
- no pending prior write
45
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
13
nS
twrrd
WR De-assertion Time before Next RD
Note 53
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
WR or ENB Active to WAIT_ACK Inactive
- pending prior 8-bit write
200
nS
WR or ENB Active to WAIT_ACK Inactive
- pending prior 16-bit write
280
nS
twrite
twawr
WAIT_ACK Inactive to WR or ENB Inactive
twrwa
WR or ENB Inactive to WAIT_ACK Active
Note 54
10
nS
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
9
nS
0
nS
Note 52: RD_WR and ENB signaling.
Note 53: RD and WR signaling.
Note 54: If not three-stated first.
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8.7.3.5
Non-Posted Write Timing Requirements - EtherCAT Direct Mapped Mode
The following sections present functional timing diagrams while in EtherCAT Direct Mapped mode.
If enabled for output, WAIT_ACK is used to indicate when the write cycle may be concluded, otherwise the host must
assume the worst case write access time listed.
WAIT_ACK is output with CS active. It will be initially inactive and becomes active with write strobe (WR or ENB) active.
Once WAIT_ACK is inactive the write strobe may be made inactive.
If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when
WR is deasserted. CS may be asserted and deasserted along with WR but not during WR active.
Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and
RD_WR indicating a write. The cycle ends when ENB is deasserted. CS may be asserted and deasserted along with
ENB but not during ENB active.
Please refer to Section 8.6.3, "Indexed Address Mode Functional Timing Diagrams," on page 122 for functional descriptions.
FIGURE 8-76:
INDEXED ADDRESSING NON-POSTED WRITE CYCLE TIMING
tcswr
twrcs
CS
tas
tah
A[4:0]
D[15:8]
D[7:0]
RD_WR
tds
tdh
trdwrs
trdwrh
twrwr
ENB, WR
twrite
twawr
twrrd
RD
tcswa
twrwa
tcswaz
WAIT_ACK
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TABLE 8-18:
INDEXED ADDRESSING NON-POSTED WRITE CYCLE TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tcswr
CS Setup to WR or ENB Active
0
nS
twrcs
CS Hold from WR or ENB Inactive
0
nS
tas
Address Setup to WR or ENB Active
0
nS
tah
Address Hold from WR or ENB Inactive
0
nS
trdwrs
RD_WR Setup to ENB Active
Note 55
5
nS
trdwrh
RD_WR Hold from ENB Inactive
Note 55
5
nS
tds
Data Setup to WR or ENB Active
0
nS
tdh
Data Hold from WR or ENB Inactive
0
nS
twrwr
WR or ENB De-assertion Time before Next WR or ENB
13
nS
twrrd
WR De-assertion Time before Next RD
Note 56
13
nS
tcswa
CS Active to WAIT_ACK Valid
10
nS
twrwa
WR or ENB Active to WAIT_ACK Active
10
nS
WR or ENB Active to WAIT_ACK Inactive
- 8-bit write
200
nS
WR or ENB Active to WAIT_ACK Inactive
- 16-bit write
280
nS
twrite
twawr
WAIT_ACK Inactive to WR or ENB Inactive
tcswaz
WAIT_ACK Turn Off Time from CS Inactive
0
nS
9
nS
Note 55: RD_WR and ENB signaling.
Note 56: RD and WR signaling.
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LAN9254
9.0
SPI/SQI SLAVE
9.1
Functional Overview
The SPI/SQI Slave module provides a low pin count synchronous slave interface that facilitates communication between
the device and a host system. The SPI/SQI Slave allows access to the System CSRs and internal FIFOs and memories.
It supports single and multiple register read and write commands with incrementing, decrementing and static addressing. Single, Dual and Quad bit lanes are supported in SPI mode with a clock rate of up to 80 MHz. SQI mode always
uses four bit lanes and also operates at up to 80 MHz.
The following is an overview of the functions provided by the SPI/SQI Slave:
• Serial Read: 4-wire (clock, select, data in and data out) reads at up to 30 MHz. Serial command, address and
data. Single and multiple register reads with incrementing, decrementing or static addressing.
• Fast Read: 4-wire (clock, select, data in and data out) reads at up to 80 MHz. Serial command, address and data.
Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static
addressing.
• Dual / Quad Output Read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 MHz. Serial command and
address, parallel data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static addressing.
• Dual / Quad I/O Read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 MHz. Serial command, parallel
address and data. Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static addressing.
• SQI Read: 6-wire (clock, select, data in / out) writes at up to 80 MHz. Parallel command, address and data.
Dummy byte(s) for first access. Single and multiple register reads with incrementing, decrementing or static
addressing.
• Write: 4-wire (clock, select, data in and data out) writes at up to 80 MHz. Serial command, address and data. Single and multiple register writes with incrementing, decrementing or static addressing.
• Dual / Quad Data Write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 MHz. Serial command and
address, parallel data. Single and multiple register writes with incrementing, decrementing or static addressing.
• Dual / Quad Address / Data Write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 MHz. Serial command, parallel address and data. Single and multiple register writes with incrementing, decrementing or static
addressing.
• SQI Write: 6-wire (clock, select, data in / out) writes at up to 80 MHz. Parallel command, address and data. Single
and multiple register writes with incrementing, decrementing or static addressing.
9.1.1
ETHERCAT DIRECT MAPPED MODE PCB BACKWARDS COMPATIBILITY
While in EtherCAT Direct Mapped Mode, additional pins are required for full functionality. However with some caveats,
EtherCAT Direct Mapped Mode can be made to work with PCBs designed for the Microchip LAN9252.
WAIT_ACK: The WAIT_ACK pin on the LAN9252 functioned as the fiber mode signal detect as well as the Port B FXSD Enable. For copper twisted pair operation, this pin would either be tied to or pulled down to ground. WAIT_ACK is
disabled by default to avoid a short. Without the WAIT_ACK connected to the host processor, the host SPI bus cycles
must assume worst case cycle timing.
9.2
SPI/SQI Slave Operation
Input data on the SIO[3:0] pins is sampled on the rising edge of the SCK input clock. Output data is sourced on the
SIO[3:0] pins with the falling edge of the clock. The SCK input clock can be either an active high pulse or an active low
pulse. When the SCS# chip select input is high, the SIO[3:0] inputs are ignored and the SIO[3:0] outputs are threestated.
In SPI mode, the 8-bit instruction is started on the first rising edge of the input clock after SCS# goes active. The instruction is always input serially on SI/SIO0.
For read and write instructions, two address bytes follow the instruction byte. Depending on the instruction, the address
bytes are input either serially, or 2 or 4 bits per clock. Although some registers are accessed as DWORDs, the address
field is considered a byte address. Fourteen address bits specify the address. Bits 15 and 14 of the address field specifies that the address is auto-decremented (10b) or auto-incremented (01b) for continuous accesses.
2020 Microchip Technology Inc.
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For read commands (except the READ instruction), one or two transfer length bytes follow the address bytes. Depending on the instruction, the transfer length bytes are input either serially, or 2 or 4 bits per clock. Although some registers
are accessed as DWORDs, the transfer length field is considered a byte length. For the one byte transfer length format,
bit 7 is low and bits 6-0 specify the length up to 127 bytes. For the two byte transfer length format, bit 7 of the first byte
is high and bits 6-0 specify the lower 7 bits of the length. Bits 6-0 of the of the second byte field specify the upper 7 bits
of the length with a maximum transfer length of 16,383 bytes (16K-1). The transfer length does not include any Dummy
Bytes.
For read and write instructions, a programmable number of initial Dummy Byte cycles follow the address or transfer
length (if applicable) bytes (preceding the first data byte).
For read and write instructions, one or more data bytes follow the Dummy Bytes (if present, else they follow the address
or transfer length (if applicable) bytes). The data is input or output either serially, or 2 or 4 bits per clock.
A programmable number of Dummy Bytes (including zero) separates each data byte within a DWORD. A separately
programmable number of Dummy Bytes (including zero) separates each DWORD. The device does not drive the outputs during the initial Dummy Byte cycles (that follow the address bytes) or Dummy Bytes for write instructions. It does
drive the outputs during the subsequent Dummy Byte cycles for read commands. Dummy input bytes should be zero
for future compatibility. Dummy output bytes are undefined. The Dummy Byte(s) are input and output either serially, or
2 or 4 bits per clock.
The number of Dummy Bytes is individually programmable per read and write command type and is set with the Set
SPI Config (SPICFG) instruction. The SPICFG instruction itself does not utilize Dummy Bytes so that its format is consistent.
SQI mode is entered from SPI with the Enable Quad I/O (EQIO) instruction. Once in SQI mode, all further command,
addresses, dummy bytes and data bytes are 4 bits per clock. SQI mode can be exited using the Reset Quad I/O
(RSTQIO) instruction.
All instructions, addresses, transfer lengths, and data are transferred with the most-significant bit (msb) or di-bit (msd)
or nibble (msn) first. Addresses are transferred with the most-significant byte (MSB) first. Transfer lengths are transferred with the most-significant byte (LSB) first. Multiple BYTE Data is transferred with the least-significant byte (LSB)
first (little endian).
The SPI interface supports up to a 80 MHz input clock. Normal (non-high speed) reads instructions are limited to 30
MHz. The programmable Dummy Byte count may be used to pace the data rate or the initial read access time.
The SPI interface supports a minimum time of 50 ns between successive commands (a minimum SCS# inactive time of
50 ns).
The instructions supported in SPI mode are listed in Table 9-1. SQI instructions are listed in Table 9-2. Unsupported
instructions are must not be used.
TABLE 9-1:
Instruction
SPI INSTRUCTIONS
Description
Bit
Width
Note 1
Inst.
code
Addr.
Bytes
Length
Bytes
Initial
Dummy
Bytes
Note 2
Note 3
Per
BYTE or
DWORD
Dummy
Bytes
Note 4
Data
bytes
Note 5
Max
Freq.
Configuration
SETCFG
Set Configuration
1-0-1
01h
0
0
0
0
39
80
MHz
EQIO
Enable SQI
1-0-0
38h
0
0
0
0
0
80
MHz
RSTQIO
Reset SQI
1-0-0
FFh
0
0
0
0
0
80
MHz
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LAN9254
TABLE 9-1:
Instruction
SPI INSTRUCTIONS (CONTINUED)
Description
Bit
Width
Note 1
Inst.
code
Addr.
Bytes
Length
Bytes
Initial
Dummy
Bytes
Note 2
Note 3
Per
BYTE or
DWORD
Dummy
Bytes
Note 4
Data
bytes
Note 5
Max
Freq.
Read
READ
Read
1-1-1
03h
2
0
0 to 255
0 to 255
4 to
/
1 to
30
MHz
FASTREAD
Read at
higher speed
1-1-1
0Bh
2
1 or 2
1 to 255
0 to 255
4 to 16K
/
1 to 16K
80
MHz
SDOR
SPI Dual
Output Read
1-1-2
3Bh
2
1 or 2
1 to 255
0 to 255
4 to 16K
/
1 to 16K
80
MHz
SDIOR
SPI Dual
I/O Read
1-2-2
BBh
2
1 or 2
2 to 255
0 to 255
4 to 16K
/
1 to 16K
80
MHz
SQOR
SPI Quad
Output Read
1-1-4
6Bh
2
1 or 2
1 to 255
0 to 255
4 to 16K
/
1 to 16K
80
MHz
SQIOR
SPI Quad
I/O Read
1-4-4
EBh
2
1 or 2
4 to 255
0 to 255
4 to 16K
/
1 to 16K
80
MHz
Write
WRITE
Write
1-1-1
02h
2
0
0 to 255
0 to 255
4 to
/
1 to
80
MHz
SDDW
SPI Dual
Data Write
1-1-2
32h
2
0
0 to 255
0 to 255
4 to
/
1 to
80
MHz
SDADW
SPI Dual
Address /
Data Write
1-2-2
B2h
2
0
0 to 255
0 to 255
4 to
/
1 to
80
MHz
SQDW
SPI Quad
Data Write
1-1-4
62h
2
0
0 to 255
0 to 255
4 to
/
1 to
80
MHz
SQADW
SPI Quad
Address /
Data Write
1-4-4
E2h
2
0
0 to 255
0 to 255
4 to
/
1 to
80
MHz
Note 1: The bit width format is: instruction code bit width, address / transfer length / initial dummy bit width, data /
subsequent dummy bit width.
Note 2: Although they are set as the default, the minimum values are not enforced by the hardware and should be
used by software.
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The minimum values support operation in LAN9252 compatibility mode for operation up to 80 MHz.
In EtherCAT Direct Mapped Mode alternate minimum values should be used as described in Section 9.3,
EtherCAT Direct Mapped Mode.
Note 3: Th bit width of the initial Dummy Bytes follows that of the address.
Note 4: The bit width of the inter-data Dummy Bytes follows that of the data.
Note 5: In LAN9252 compatibility mode, the minimum number of Data Bytes is 4 since all registers must be DWORD
accessed. In EtherCAT Direct Mapped Mode, for non-EtherCAT core CSRs, the minimum number of Data
Bytes remains as 4. For EtherCAT core CSRs or the Process RAM, the minimum number of Data Bytes is 1.
TABLE 9-2:
Instruction
SQI INSTRUCTIONS
Description
Bit
Width
Note 6
Inst.
code
Addr.
Bytes
Length
Bytes
Initial
Dummy
Bytes
Note 7
Note 8
Per
BYTE or
DWORD
Dummy
Bytes
Note 9
Data
bytes
Note 10
Max
Freq.
Configuration
SETCFG
Set Configuration
4-0-4
01h
0
0
0
0
39
80
MHz
RSTQIO
Reset SQI
4-0-0
FFh
0
0
0
0
0
80
MHz
1 or 2
3 to 255
0 to 255
4 to 16K
/
1 to 16K
80
MHz
0
0 to 255
0 to 255
4 to
/
1 to
80
MHz
Read
FASTREAD
Read at
higher speed
4-4-4
0Bh
2
Write
WRITE
Write
4-4-4
02h
2
Note 6: The bit width format is: instruction code bit width, address / transfer length / initial dummy bit width, data /
subsequent dummy bit width.
Note 7: Although they are set as the default, the minimum values are not enforced by the hardware and should be
used by software.
The minimum values support operation in LAN9252 compatibility mode for operation up to 80 MHz.
In EtherCAT Direct Mapped Mode alternate minimum values should be used as described in Section 9.3,
EtherCAT Direct Mapped Mode.
Note 8: Th bit width of the initial Dummy Bytes follows that of the address.
Note 9: The bit width of the inter-data Dummy Bytes follows that of the data.
Note 10: In LAN9252 compatibility mode, the minimum number of Data Bytes is 4 since all registers must be DWORD
accessed. In EtherCAT Direct Mapped Mode, for non-EtherCAT core CSRs, the minimum number of Data
Bytes remains as 4. For EtherCAT core CSRs or the Process RAM, the minimum number of Data Bytes is 1.
DS00003422A-page 166
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9.2.1
DEVICE INITIALIZATION
Until the device has been initialized to the point where the various configuration inputs are valid, the SPI/SQI interface
does not respond to and is not affected by any external pin activity.
Once device initialization completes, the SPI/SQI interface will ignore the pins until a rising edge of SCS# is detected.
9.2.1.1
SPI/SQI Slave Read Polling for Initialization Complete
Before device initialization, the SPI/SQI interface will not return valid data. To determine when the SPI/SQI interface is
functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface
can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register
(HW_CFG) can be polled to determine when the device is fully configured.
Note:
9.2.2
The Host should only use single register reads (one data cycle per SCS# low) while polling the BYTE_TEST
register.
ACCESS DURING AND FOLLOWING POWER MANAGEMENT
During any power management mode other than D0, reads and writes are ignored and the SPI/SQI interface does not
respond to and is not affected by any external pin activity.
Once the power management mode changes back to D0, the SPI/SQI interface will ignore the pins until a rising edge
of SCS# is detected.
To determine when the SPI/SQI interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled.
Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY)
bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured.
Note:
9.2.3
The Host should only use single register reads (one data cycle per SCS# low) while polling the BYTE_TEST
register.
WAIT / ACKNOWLEDGMENT OPERATION
When operating in EtherCAT Direct Mapped mode (see Section 9.3, EtherCAT Direct Mapped Mode), the host system
must meet the device’s timing access requirements. For reads from the EtherCAT Core CSR or Process Data RAM, the
read cycles must wait until read data has been internally retrieved. All write cycles must wait for any prior write access
to the EtherCAT Core CSR or Process Data RAM to internally complete. The host system may either wait the specified
worst case access time, or may use the WAIT_ACK signal.
The WAIT_ACK pin is enabled via the combination of the SPI WAIT_ACK Polarity and SPI WAIT_ACK Buffer Type bits
of the PDI Configuration Register (SPI Modes).
WAIT_ACK is only used when operating in EtherCAT Direct Mapped mode. When not in EtherCAT Direct Mapped
mode, if WAIT_ACK is enabled it is always inactive (showing ACK). WAIT_ACK may be set as an active low open drain
output for wire-AND systems or as a three-stated push-pull output. This is controlled by the SPI WAIT_ACK Buffer Type
bit of the PDI Configuration Register (SPI Modes). As a push-pull output, its polarity is set by the SPI WAIT_ACK Polarity
bit of the PDI Configuration Register (SPI Modes). WAIT_ACK operation is described in Section 9.3.2.3, Wait States.
9.2.4
9.2.4.1
SPI CONFIGURATION COMMANDS
Set Configuration
The Set Configuration instruction sets the number of Dummy Bytes expected for each instruction. This instruction is supported in SPI and SQI bus protocols with clock frequencies up to 80 MHz.
The SPI/SQI slave interface is selected by first bringing SCS# active. The 8-bit SETCFG instruction, 01h, is input into
the SI/SIO[0] pin, one bit per clock, in SPI mode and into the SIO[3:0] pins, four bits per clock, in SQI mode.
The data follows the command byte. For SPI mode, the data is input into the SI/SIO[0] pin starting with the msb of the
first byte. For SQI mode the data is input nibble wide using SIO[3:0] starting with the msn of the first byte. The remaining
bits/nibbles are shifted in on subsequent clock edges.
The SCS# input is brought inactive to conclude the cycle.
2020 Microchip Technology Inc.
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The order of the Dummy Bytes along with their defaults follow. There are three values per instruction. The first is the
number of Dummy Bytes that will precede the first data byte. The second is the number of Dummy Bytes that occur
between bytes within a DWORD. The third is the number of Dummy Bytes that occur between DWORDs. Note there
are no Dummy Bytes after the last data byte of a command.
The hardware defaults shown support operation in LAN9252 compatibility mode for operation up to 80 MHz. In EtherCAT Direct Mapped Mode, alternate minimum values should be set as described in Section 9.3, EtherCAT Direct
Mapped Mode.
TABLE 9-3:
Byte Order
DUMMY BYTE ORDER AND DEFAULT
Initial
Instruction
Within a
DWORD
Between
DWORDs
Default
SPI
0
READ
1
0
-
-
-
0
-
-
0
1
-
-
-
0
-
-
0
1
-
-
-
0
-
-
0
2
-
-
-
0
-
-
0
1
-
-
-
0
-
-
0
4
-
-
-
0
-
-
0
0
-
-
-
0
-
-
0
0
-
-
-
0
-
-
0
2
3
FASTREAD
4
5
6
SDOR
7
8
9
SDIOR
10
11
12
SQOR
13
14
15
SQIOR
16
17
18
WRITE
19
20
21
22
23
DS00003422A-page 168
SDDW
2020 Microchip Technology Inc.
LAN9254
TABLE 9-3:
DUMMY BYTE ORDER AND DEFAULT (CONTINUED)
Byte Order
Within a
DWORD
Initial
Instruction
Between
DWORDs
Default
24
SDADW
25
0
-
-
-
0
-
-
0
0
-
-
-
0
-
-
0
0
-
-
-
0
-
-
0
3
-
-
-
0
-
-
0
0
-
-
-
0
-
-
0
26
27
SQDW
28
29
30
SQADW
31
32
SQI
33
FASTREAD
34
35
36
WRITE
37
38
Figure 9-1 illustrates the Set Configuration instruction for SPI mode. Figure 9-2 illustrates the Set Configuration instruction for SQI mode.
FIGURE 9-1:
SPI MODE SET CONFIGURATION
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
9
1
1
1
0
Instruction
SI
X
0
0
0
SO
0
0
0
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
1
7
1
6
1
8
1
7
1
9
1
8
Cfg Byte 0
0
1
D
7
D
6
D
5
D
4
D
3
D
2
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
Cfg Byte 1
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
2
6
...
2
5
2
6
X
...
X
Cfg 2 ... Cfg Byte 39
D
1
D
0
D
7
D
6
...
D
4
D
3
D
2
D
1
D
0
X
Z
SPI Set Configuration
2020 Microchip Technology Inc.
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LAN9254
FIGURE 9-2:
SQI MODE SET CONFIGURATION
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
...
...
1
6
Inst Cfg0 Cfg1 Cfg2 ...
SIO[3:0]
X
0
1
H
L
H
L
H
L
X
X
ﺫCfg25
H
L
H
L
H
L
H
...
L
H
L
X
SQI Set Configuration
9.2.4.2
Enable SQI
The Enable SQI instruction changes the mode of operation to SQI. This instruction is supported in SPI bus protocol only
with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit EQIO instruction, 38h, is input into the SI/
SIO[0] pin one bit per clock. The SCS# input is brought inactive to conclude the cycle.
Figure 9-3 illustrates the Enable SQI instruction.
FIGURE 9-3:
ENABLE SQI
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
X
8
X
Instruction
SI
X
0
0
1
1
SO
1
0
0
0
X
Z
SPI Enable SQI
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LAN9254
9.2.4.3
Reset SQI
The Reset SQI instruction changes the mode of operation to SPI. This instruction is supported in SPI and SQI bus protocols with clock frequencies up to 80 MHz.
The SPI/SQI slave interface is selected by first bringing SCS# active. The 8-bit RSTQIO instruction, FFh, is input into
the SI/SIO[0] pin, one bit per clock, in SPI mode and into the SIO[3:0] pins, four bits per clock, in SQI mode. The SCS#
input is brought inactive to conclude the cycle.
Figure 9-4 illustrates the Reset SQI instruction for SPI mode. Figure 9-5 illustrates the Reset SQI instruction for SQI
mode.
FIGURE 9-4:
SPI MODE RESET SQI
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
6
4
5
7
6
8
7
X
8
X
Instruction
SI
X
1
1
1
1
SO
1
1
1
1
X
Z
SPI Mode Reset SQI
FIGURE 9-5:
SQI MODE RESET SQI
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
X
2
X
Inst
SIO[3:0]
X
F
F
X
SQI Mode Reset SQI
2020 Microchip Technology Inc.
DS00003422A-page 171
LAN9254
9.2.5
SPI READ COMMANDS
Various read commands are support by the SPI/SQI slave. The following applies to all read commands.
MULTIPLE READS
Additional reads, beyond the first, are performed by continuing the clock pulses while SCS# is active. The upper two bits
of the address specify auto-incrementing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). The internal address is incremented, decremented, or maintained based on these bits. Maintaining a fixed internal address is
useful for register polling.
Towards the end of the current output shift the address is incremented or decremented, if appropriate, and another synchronized capture sequence is done.
Constant address and Auto-increment/decrement operation for multiple DWORDs operates as follows. Note that it is
the DWORD address that remains constant or is incremented or decremented. The byte address within the DWORD
always increments:
dec/inc=00: constant DWORD aligned address
read 4 bytes within the DWORD in incrementing byte order
internal address repeats each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
internal address : yyyy
byte address :
Second data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
internal address : yyyy
byte address :
Last data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
dec/inc=01: incrementing DWORD aligned starting address
read 4 bytes within each DWORD in incrementing byte order
internal address is incremented by 4 each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
next internal address : next DWORD
byte address :
+4
Second data output :
valid
+5
valid
+6
valid
+7
valid
next internal address : next DWORD
byte address :
+8
Last data output :
valid
+9
valid
+10
valid
+11
valid
dec/inc=10: decrementing DWORD aligned starting address
read 4 bytes within each DWORD in incrementing byte order
internal address is decremented by 4 each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
next internal address : previous DWORD
DS00003422A-page 172
2020 Microchip Technology Inc.
LAN9254
byte address :
Second data output :
-4
valid
next internal address : previous DWORD
byte address :
-8
Last data output :
valid
-3
valid
-2
valid
-1
valid
-7
valid
-6
valid
-5
valid
dec/inc=11: RESERVED
The above apply to full DWORD accesses starting at DWORD aligned addresses. See Section 9.3.2.1 for partial
DWORD accesses or non-DWORD aligned starting addresses utilized during EtherCAT Direct Mapped mode.
READ TERMINATION
To avoid internally prefetching additional data past the last data that will be output, two methods are utilized.
For the READ instruction, the SI input is used. During the last output byte, the SPI master must set SI high (input byte
= FFh), otherwise an internal prefetch will occur with the potential of loosing data.
For other read commands (FASTREAD, SDOR, SDIOR, SQOR, SQIOR), the transfer length in bytes is provided following the address.
DUMMY BYTES
In order to provide sufficient time to retrieve the register data (especially when reading from the EtherCAT Core CSRs
or Process RAM while in EtherCAT Direct Mapped mode) Dummy Byte cycles may be used. The number of Dummy
Bytes is set using the Set Configuration instruction and is specified per read command type.
There are three values per instruction. The first is the number of Dummy Bytes that will precede the first data byte. The
second is the number of Dummy Bytes that occur between bytes within a DWORD (intra-DWORD). The third is the number of Dummy Bytes that occur between DWORDs (inter-DWORD). There are no Dummy Bytes after the last data byte
of a command.
APPLICATION NOTE: The number of Dummy Bytes between DWORDs is strictly the third configuration value. It is
not in addition to or paralleled with a Dummy Byte count using the second configuration
value.
APPLICATION NOTE: The DWORD boundary applies to all read commands even if the command is BYTE oriented
(e.g. the READ command). The intra- and inter- number of Dummy Bytes can be set the
same if appropriate.
APPLICATION NOTE: For the READ command, a Dummy byte configuration which has second parameter (intraDWORD) equal to 0 and the third parameter (inter-DWORD) not equal to 0 is not supported.
Normally the second and third parameters would be the same value in this case.
APPLICATION NOTE: The DWORD boundary is based on the address of the last byte read, not on the running
byte count (i.e. it is not simply every fourth byte). This is important to consider during
EtherCAT Direct Mapped Mode where the starting address could be non-DWORD aligned.
Refer to Section 9.3.2.1 for how the address is updated.
APPLICATION NOTE: The number of clock cycles for a Dummy Byte varies based on the bit width(s) of the
instruction.
SPECIAL CSR HANDLING
Live Bits
Since data is read serially, the selected register’s value is saved at the beginning of each 32-bit read to prevent the host
from reading an intermediate value. The saving occurs multiple times in a multiple read sequence.
2020 Microchip Technology Inc.
DS00003422A-page 173
LAN9254
9.2.5.1
Read
The Read instruction inputs the instruction code, the address and the possible initial Dummy bytes one bit per clock and
outputs the data and any subsequent Dummy Byte(s) one bit per clock. This instruction is supported in SPI bus protocol
only with clock frequencies up to 30 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit READ instruction, 03h, is input into the SI/
SIO[0] pin, followed by the two address bytes and 0 to 255 Dummy Byte(s). The address bytes specify a BYTE address
within the device.
On the falling clock edge following the rising edge of the last address or Dummy bit, the SO/SIO[1] pin is driven starting
with the msb of the LSB of the selected register. The remaining register bits are shifted out on subsequent falling clock
edges. For multiple byte registers, the next byte follows the last bit of the preceding byte or Dummy Byte(s). For reads
of multiple registers, the first bit of the next register follows the last bit of the preceding register or Dummy Byte(s).
To avoid internally prefetching additional data past the last data that will be output, the SI input is used. During the last
output byte, the SPI master must set SI high (input byte = FFh), otherwise an internal prefetch will occur with the potential of loosing data. For all but the last output byte, SPI master must set SI low (input byte = 00h).
The SCS# input is brought inactive to conclude the cycle. The SO/SIO[1] pin is three-stated at this time.
Figure 9-6 illustrates a typical single and multiple register read. A DWORD aligned full DWORD register is shown. The
final DWORD is not followed by Dummy Bytes. A partial DWORD register read is also possible and would terminate
after the last data BYTE without subsequent Dummy Byte(s). It is also possible for a partial DWORD read to start on a
non-DWORD aligned boundary.
Application Note:A Dummy byte configuration which has second parameter (intra-DWORD) equal to 0 and the third
parameter (inter-DWORD) not equal to 0 is not supported. Normally the second and third parameters would be the same value in this case.
FIGURE 9-6:
SPI READ
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
Instruction
SI
X
0
0
0
0
0
0
1
6
1
5
1
7
1
6
1
8
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
2
5
Address
1
1
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
AL
7
Z
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
A
6
AL
15
...
...
...
...
2
6
0 to 255 Dummy
A
5
A
4
A
3
A
2
A
1
A
0
0
AL bits (optionally enabled)
SO
2
6
AL
14
AL
13
AL
12
AL
11
...
0
0
0
1 if last byte else 0
0
I.S. (opt enabled)
AL
10
AL
9
AL
8
0
Data
I.S. I.S. I.S. I.S. I.S. I.S. I.S. I.S.
31 30 27 26 19 18 17
0
D
7
D
6
D
5
D
5
D
3
0
...
...
...
0
0
D
1
D
0
x
x
...
x
x
X
X
Data (+Dummy)
0 to 255 Dummy
D
2
...
1 during last byte
else 0
X
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
...
X Z
For multiple byte register
SPI Read Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
SCK (active high)
X
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
Instruction
SI
X
0
0
0
0
0
0
1
6
1
5
1
7
1
6
1
8
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
Address
1
1
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
Z
SPI Read Multiple Registers
9.2.5.2
AL
7
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
AL
15
AL
14
...
2
6
...
...
...
0 to 255 Dummy
A
5
A
4
A
3
A
2
A
1
A
0
AL bits (optionally enabled)
SO
2
6
2
5
AL
13
AL
12
AL
11
0
0
...
0
0
0
0
I.S. (opt enabled)
AL
10
AL
9
AL
8
I.S. I.S. I.S. I.S. I.S. I.S. I.S. I.S.
31 30 27 26 19 18 17
0
0
Reg m
D
7
D
6
D
5
D
4
D
3
0
...
0
D
1
D
0
x
x
...
x
x
...
...
...
...
0
0
Reg m (+Dummy)
0 to 255 Dummy
D
2
...
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
...
0
0
...
...
...
0
0
1 during last byte
else 0
x
...
x
x
X
X
Reg n (+Dummy)
0 to 255 Dummy
x
...
X
D
7
D
6
D
5
D
4
D
3
...
X Z
For multiple byte registers
Initial
Intra-DWORD
Inter-DWO RD
Fast Read
The Read at higher speed instruction inputs the instruction code and the address, the transfer length, and the initial
Dummy Bytes one bit per clock and outputs the data and any subsequent Dummy Byte(s) one bit per clock. In SQI
mode, the instruction code, the address, the transfer length, and the initial Dummy Bytes are input four bits per clock
and the data and any subsequent Dummy Byte(s) are output four bits per clock. This instruction is supported in SPI and
SQI bus protocols with clock frequencies up to 80 MHz.
The SPI/SQI slave interface is selected by first bringing SCS# active. For SPI mode, the 8-bit FASTREAD instruction,
0Bh, is input into the SI/SIO[0] pin, followed by the two address bytes, one or two transfer length bytes, and 1 to 255
Dummy Byte(s). For SQI mode, the 8-bit FASTREAD instruction is input into the SIO[3:0] pins, followed by the two
DS00003422A-page 174
2020 Microchip Technology Inc.
LAN9254
address bytes, one or two transfer length bytes, and 3 to 255 Dummy Bytes. The address bytes specify a BYTE address
within the device. The transfer length bytes specify the data length in BYTEs and does not include any Dummy Bytes.
The transfer length field is either 7 or 14 bits with maximum transfer length of 127 or 16,383 bytes (16K-1).
On the falling clock edge following the rising edge of the last dummy bit (or nibble), the SO/SIO[1] pin is driven starting
with the msb of the LSB of the selected register. For SQI mode, SIO[3:0] are driven starting with the msn of the LSB of
the selected register. For a non-DWORD aligned starting address, 1-3 padding bytes (and possible Dummy Bytes per
padding byte) occur prior to the data bytes. Padding bytes are not counted in the transfer length.
The remaining register bits are shifted out on subsequent falling clock edges. For multiple byte registers, the next byte
follows the last bit (or nibble) of the preceding byte or Dummy Byte(s). For reads of multiple registers, the first bit (or
nibble) of the next register follows the last bit (or nibble) of the preceding register or Dummy Byte(s).
The SCS# input is brought inactive to conclude the cycle. The SO/SIO[3:0] pins are three-stated at this time.
Figure 9-7 illustrates a typical single and multiple register fast read for SPI mode. Figure 9-8 illustrates a typical single
and multiple register fast read for SQI mode. The transfer length field may be one or two bytes. A DWORD aligned full
DWORD register is shown. The final DWORD is not followed by Dummy Bytes. A partial DWORD register read is also
possible and would terminate after the last data BYTE without subsequent Dummy Byte(s). It is also possible for a partial
DWORD read to start on a non-DWORD aligned boundary.
FIGURE 9-7:
SPI FAST READ
SCS#
SCK (active low)
SCK (active high)
X
1
X
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
9
X
0
0
0
0
1
0
1
1
d
e
c
i
n
c
...
...
...
Address
Transfer Length
1
1
Instruction
SI
...
1
0
...
A
1
3
A
2
A
1
A
0
f
m
t
L
6
L
5
...
L9 |2 L8|1 L7|0
AL
7
Z
AL
6
AL
5
...
AL
10
AL
9
...
...
...
...
...
1 to 255 Dummy
0
0
...
0
0
X
0
I.S. (opt enabled)
AL bits (opt enabled)
SO
...
AL
8
I.S. I.S. I.S. I.S. I.S. I.S. I.S. I.S.
31 30 27 26 19 18 17
0
Z
0
Data
D
7
D
6
D
5
D
5
D
3
0
...
0
D
1
D
0
x
x
...
x
x
X
X
Data (+Dummy)
0 to 255 Dummy
D
2
...
X
0
X
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
...
X Z
For multiple byte register
SPI Fast Read Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
X
0
0
0
0
1
0
1
1
d
e
c
...
...
...
...
Address
Transfer Length
1
0
9
Instruction
SI
...
...
i
n
c
1
1
A
1
3
...
A
2
A
1
A
0
f
m
t
L
6
L
5
...
Z
AL
7
AL
6
AL
5
SPI Fast Read Multiple Registers
2020 Microchip Technology Inc.
...
AL
10
AL
9
...
1 to 255 Dummy
0
0
...
0
0
X
0
I.S. (opt enabled)
AL bits (opt enabled)
SO
L9 |2 L8|1 L7|0
...
AL
8
Z
I.S. I.S. I.S. I.S. I.S. I.S. I.S. I.S.
31 30 27 26 19 18 17
0
0
Reg m
D
7
D
6
D
5
D
4
D
3
0
...
0
D
1
D
0
x
x
...
x
x
...
...
...
...
X
0
Reg m (+Dummy)
0 to 255 Dummy
D
2
...
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
...
0
0
...
...
...
0
x
...
x
x
X
X
Reg n (+Dummy)
0 to 255 Dummy
x
...
X
0
X
D
7
D
6
D
5
D
4
D
3
...
X Z
For multiple byte registers
Initial
Intra-DWORD
Inter-DWO RD
DS00003422A-page 175
LAN9254
FIGURE 9-8:
SQI FAST READ
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
Inst Address
SIO[3:0]
X
0
B
H
1
L
1
H
0
L
0
8
7
1
0
9
8
1
1
1
2
1
0
9
1
1
...
...
...
...
1
2
Xfer Len
3 to 255 Dummy
H
0
0
L
0
H
1
L
1
...
0
0
0
Data
H
0
L
0
...
...
0 to 255 Dummy
x
x
...
x
x
X
X
Data (+Dummy)
H
1
L
1
H
2
L
2
...
X
For multiple byte register
SQI Fast Read Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
6
Inst Address
SIO[3:0]
X
0
B
H
1
L
1
H
0
SQI Fast Read Multiple Registers
9.2.5.3
7
L
0
8
7
1
0
9
8
1
1
1
2
1
0
9
1
1
...
...
...
...
1
2
...
...
Xfer Len
3 to 255 Dummy Reg m 0 to 255 Dummy
H
0
0
L
0
H
1
L
1
0
...
0
0
H
0
L
0
x
x
...
x
x
...
...
...
...
Reg m (+Dummy) 0 to 255 Dummy
Reg n (+Dummy)
H
1
H
0
L
1
H
2
L
2
...
x
x
...
x
x
L
0
H
1
L
1
...
X
X
X
For multiple byte register
Initial
Intra-DWORD
Inter-DWORD
Dual Output Read
The SPI Dual Output Read instruction inputs the instruction code and the address, the transfer length, and the initial
Dummy Bytes one bit per clock and outputs the data and any subsequent Dummy Byte(s) two bits per clock. This
instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported
in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDOR instruction, 3Bh, is input into the SIO[0]
pin, followed by the two address bytes, one or two transfer length bytes, and 1 to 255 Dummy Byte(s). The address
bytes specify a BYTE address within the device. The transfer length bytes specify the data length in BYTEs and does
not include any Dummy Bytes. The transfer length field is either 7 or 14 bits with maximum transfer length of 127 or
16,383 bytes (16K-1).
On the falling clock edge following the rising edge of the last dummy di-bit, the SIO[1:0] pins are driven starting with the
msbs of the LSB of the selected register. For a non-DWORD aligned starting address, 1-3 padding bytes (and possible
Dummy Bytes per padding byte) occur prior to the data bytes. Padding bytes are not counted in the transfer length.
The remaining register di-bits are shifted out on subsequent falling clock edges. For multiple byte registers, the next
byte follows the last bit (or nibble) of the preceding byte or Dummy Byte(s). For reads of multiple registers, the first bit
(or nibble) of the next register follows the last bit (or nibble) of the preceding register or Dummy Byte(s).
The SCS# input is brought inactive to conclude the cycle. The SIO[1:0] pins are three-stated at this time.
DS00003422A-page 176
2020 Microchip Technology Inc.
LAN9254
Figure 9-9 illustrates a typical single and multiple register dual output read. The transfer length field may be one or two
bytes. A DWORD aligned full DWORD register is shown. The final DWORD is not followed by Dummy Bytes. A partial
DWORD register read is also possible and would terminate after the last data BYTE without subsequent Dummy
Byte(s). It is also possible for a partial DWORD read to start on a non-DWORD aligned boundary.
FIGURE 9-9:
SPI DUAL OUTPUT READ
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
X
0
0
1
1
1
0
Address
1
1
d
e
c
i
n
c
...
A
1
3
...
...
...
...
1
1
Instruction
SIO0
...
...
A
2
Transfer Length
A
1
A
0
f
m
t
L
6
L
5
...
L9|2 L8|1 L7|0
AL
7
Z
AL
6
AL
5
...
AL
10
AL
9
Data
1 to 255 Dummy
0
0
...
0
0
0
D
6
I.S. (opt enabled)
AL bits (opt enabled)
SIO1
...
...
AL
8
D
2
0 to 25 5 Dummy
D
0
Data
I.S . I.S . I.S . I.S . I.S . I.S . I.S . I.S .
31 30 27 26 19 18 17
0
Z
D
4
D
7
D
5
D
3
...
...
x
x
...
x
x
0 to 25 5 Dummy
D
1
x
x
...
x
x
X
X
Data (+Dummy)
D
1
4
D
1
2
D
1
0
D
8
...
X
Data (+Dummy)
D
1
5
D
1
3
D
1
1
D
9
...
X Z
For multiple byte register
SPI Dual Output Read Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
SCK (active high)
X
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
9
1
1
X
0
0
1
1
1
0
1
1
d
e
c
i
n
c
...
...
...
Address
Transfer Length
1
0
Instruction
SIO0
...
1
1
A
1
3
...
A
2
A
1
A
0
f
m
t
L
6
L
5
...
Z
AL
7
AL
6
AL
5
...
SPI Dual Output Read Multiple Registers
9.2.5.4
AL
10
AL
9
...
...
...
...
...
...
...
...
...
Reg m
1 to 255 Dummy
0
0
...
0
0
0
D
6
I.S. (opt enabled)
AL bits (opt enabled)
SIO1
L9|2 L8|1 L7|0
...
AL
8
Z
I.S . I.S . I.S . I.S . I.S . I.S . I.S . I.S .
31 30 27 26 19 18 17
0
D
4
D
2
D
0
Reg m
D
7
D
5
D
3
D
1
0 to 25 5 Dummy
Reg m (+Dummy) 0 to 25 5 Dummy
Reg n (+Du mmy)
x
D
1
4
D
6
x
...
x
x
D
1
2
D
1
0
D
8
...
x
x
...
x
x
D
4
D
2
D
0
...
0 to 25 5 Dummy
Reg m (+Dummy) 0 to 25 5 Dummy
Reg n (+Du mmy)
x
D
1
5
D
7
x
...
x
x
D
1
3
D
1
1
D
9
...
x
x
...
x
x
D
5
D
3
D
1
...
X
X
X
X Z
For multiple byte register
Initial
Intra-DWORD
Inter-DWORD
Quad Output Read
The SPI Quad Output Read instruction inputs the instruction code, the address, the transfer length, and the initial
Dummy Bytes one bit per clock and outputs the data and any subsequent Dummy Byte(s) four bits per clock. This
instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported
in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQOR instruction, 6Bh, is input into the SIO[0]
pin, followed by the two address bytes, one or two transfer length bytes, and 1 to 255 Dummy Byte(s). The address
bytes specify a BYTE address within the device. The transfer length bytes specify the data length in BYTEs and does
not include any Dummy Bytes. The transfer length field is either 7 or 14 bits with maximum transfer length of 127 or
16,383 bytes (16K-1).
On the falling clock edge following the rising edge of the last dummy bit, the SIO[3:0] pins are driven starting with the
msn of the LSB of the selected register. For a non-DWORD aligned starting address, 1-3 padding bytes (and possible
Dummy Bytes per padding byte) occur prior to the data bytes. Padding bytes are not counted in the transfer length.
The remaining register nibbles are shifted out on subsequent falling clock edges. For multiple byte registers, the next
byte follows the last bit (or nibble) of the preceding byte or Dummy Byte(s). For reads of multiple registers, the first bit
(or nibble) of the next register follows the last bit (or nibble) of the preceding register or Dummy Byte(s).
The SCS# input is brought inactive to conclude the cycle. The SIO[3:0] pins are three-stated at this time.
2020 Microchip Technology Inc.
DS00003422A-page 177
LAN9254
Figure 9-10 illustrates a typical single and multiple register quad output read. The transfer length field may be one or
two bytes. A DWORD aligned full DWORD register is shown. The final DWORD is not followed by Dummy Bytes. A
partial DWORD register read is also possible and would terminate after the last data BYTE without subsequent Dummy
Byte(s). It is also possible for a partial DWORD read to start on a non-DWORD aligned boundary.
FIGURE 9-10:
SPI QUAD OUTPUT READ
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
X
0
1
1
0
1
0
Address
1
1
d
e
c
i
n
c
...
A
1
3
...
...
...
1
1
Instruction
SIO0
...
...
A
2
...
Transfer Length
A
1
f
m
t
A
0
L
6
L
5
...
L9|2 L8|1 L7|0
1 to 255 Dummy
0
AL
7
Z
AL
6
AL
5
...
AL
10
AL
9
0
...
0
0
0
AL
8
D
0
x
D
5
D
1
x
D
6
Z
D
2
x
D
7
Z
SPI Quad Output Read Single Register
D
3
...
...
x
...
X
D
1
2
D
8
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
...
X
Data
(+Dummy)
x
...
X Z
Data
(+Dummy)
x
0 to 255
Dummy
Data
SIO3
x
0 to 255
Dummy
Data
SIO2
...
X
Data
(+Dummy)
0 to 255
Dummy
Data
I.S . I.S . I.S . I.S. I.S. I.S . I.S . I.S .
31 30 27 26 19 18 17
0
Z
D
4
...
...
0 to 255
Dummy
Data
I.S. (opt enabled)
AL bits (opt enabled)
SIO1
...
...
...
X Z
Data
(+Dummy)
x
...
X Z
For multiple byte register
Intra- DWORD
Initial
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
9
1
1
1
0
Instruction
SIO0
X
0
1
1
0
1
0
...
...
1
1
Address
1
1
d
e
c
i
n
c
A
1
3
...
A
2
Transfer Length
A
1
f
m
t
A
0
L
6
L
5
...
Z
AL
7
AL
6
AL
5
...
AL
10
AL
9
L9|2 L8|1 L7|0
...
...
Reg
m
1 to 255 Dummy
0
0
...
0
0
0
I.S. (opt enabled)
AL bits (opt enabled)
SIO1
...
...
...
...
AL
8
Z
I.S . I.S . I.S . I.S. I.S. I.S . I.S . I.S .
31 30 27 26 19 18 17
0
D
4
D
0
0 to 255
Dummy
x
Reg
m
D
5
D
1
D
6
Z
D
2
x
SPI Quad Output Read Multiple Registers
DS00003422A-page 178
D
7
Z
Initial
D
3
x
...
x
...
x
...
D
8
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
... ...
x
... ...
x
x
x
x
... ...
x
x
x
D
4
D
0
...
X
D
5
D
1
...
X Z
Reg n
(+Dummy)
x
0 to 255
Dummy
... ...
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
x
D
1
2
...
...
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
Reg
m
SIO3
...
Reg m
(+Dummy)
0 to 255
Dummy
Reg
m
SIO2
... ...
... ...
D
6
D
2
...
X Z
Reg n
(+Dummy)
x
D
7
D
3
...
X Z
For multiple byte register
Intra- DWORD
Inter-DWORD
2020 Microchip Technology Inc.
LAN9254
9.2.5.5
Dual I/O Read
The SPI Dual I/O Read instruction inputs the instruction code one bit per clock and the address, The transfer length,
and the initial Dummy Bytes two bits per clock and outputs the data and any subsequent Dummy Byte(s) two bits per
clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not
supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDIOR instruction, BBh, is input into the SIO[0]
pin, followed by the two address bytes, one or two transfer length bytes, and 2 to 255 Dummy Bytes into the SIO[1:0]
pins. The address bytes specify a BYTE address within the device. The transfer length bytes specify the data length in
BYTEs and does not include any Dummy Bytes. The transfer length field is either 7 or 14 bits with maximum transfer
length of 127 or 16,383 bytes (16K-1).
On the falling clock edge following the rising edge of the last dummy di-bit, the SIO[1:0] pins are driven starting with the
msbs of the LSB of the selected register. For a non-DWORD aligned starting address, 1-3 padding bytes (and possible
Dummy Bytes per padding byte) occur prior to the data bytes. Padding bytes are not counted in the transfer length.
The remaining register di-bits are shifted out on subsequent falling clock edges. For multiple byte registers, the next
byte follows the last bit (or nibble) of the preceding byte or Dummy Byte(s). For reads of multiple registers, the first bit
(or nibble) of the next register follows the last bit (or nibble) of the preceding register or Dummy Byte(s).
The SCS# input is brought inactive to conclude the cycle. The SIO[1:0] pins are three-stated at this time.
Figure 9-11 illustrates a typical single and multiple register dual I/O read. The transfer length field may be one or two
bytes. A DWORD aligned full DWORD register is shown. The final DWORD is not followed by Dummy Bytes. A partial
DWORD register read is also possible and would terminate after the last data BYTE without subsequent Dummy
Byte(s). It is also possible for a partial DWORD read to start on a non-DWORD aligned boundary.
FIGURE 9-11:
SPI DUAL I/O READ
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
X
1
0
1
1
1
...
...
1
0
9
Instruction
SIO0
...
...
Address
0
1
1
i
n
c
...
A
1
2
A
2
Xfer Length
A
0
L
6
Address
SIO1
d
e
c
Z
...
A
1
3
A
3
...
...
L
4
...
L9|2 L7|0
Xfer Length
A
1
f
m
t
L
5
...
L10|
L8|1
3
...
...
Data
2 to 255 Dummy
0
0
...
0
0
D
6
0
...
0
0
D
2
0 to 255 Dummy
D
0
Data
2 to 255 Dummy
0
D
4
D
7
D
5
D
3
...
...
x
x
...
x
x
0 to 255 Dummy
D
1
x
x
...
x
x
X
X
Data (+Dummy)
D
1
4
D
1
2
D
1
0
D
8
...
X
Data (+Dummy)
D
1
5
D
1
3
D
1
1
D
9
...
X Z
For multiple byte register
SPI Dual I/O Read Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
8
9
Instruction
SIO0
X
1
0
1
1
1
0
1
0
9
...
...
...
...
1
0
Address
1
1
i
n
c
A
1
2
...
A
2
Xfer Length
A
0
L
6
Address
SIO1
Z
SPI Dual I/O Read Multiple Registers
2020 Microchip Technology Inc.
d
e
c
A
1
3
...
A
3
L
4
...
L9|2 L7|0
Xfer Length
A
1
f
m
t
L
5
...
...
...
...
...
L10|
L8|1
3
Reg m
2 to 255 Dummy
0
0
...
0
0
D
6
0
...
0
0
D
2
D
0
Reg m
2 to 255 Dummy
0
D
4
D
7
D
5
D
3
D
1
...
...
...
...
...
...
0 to 255 Dummy
Reg m (+Dummy) 0 to 255 Dummy
Reg n (+Dummy)
x
D
1
4
D
6
x
...
x
x
D
1
2
D
1
0
D
8
...
x
x
...
x
x
D
4
D
2
D
0
...
0 to 255 Dummy
Reg m (+Dummy) 0 to 255 Dummy
Reg n (+Dummy)
x
D
1
5
D
7
x
...
x
x
D
1
3
D
1
1
D
9
...
x
x
...
x
x
D
5
D
3
D
1
...
X
X
X
X Z
For multiple byte register
Initial
Intra-DWORD
Inter-DWORD
DS00003422A-page 179
LAN9254
9.2.5.6
Quad I/O Read
The SPI Quad I/O Read instruction inputs the instruction code one bit per clock and the address, the transfer length,
and the initial Dummy Bytes four bits per clock and outputs the data and any subsequent Dummy Byte(s) four bits per
clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not
supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQIOR instruction, EBh, is input into the
SIO[0] pin, followed by the two address bytes, one or two transfer length bytes, and 4 to 255 Dummy Bytes into the
SIO[3:0] pins. The address bytes specify a BYTE address within the device. The transfer length bytes specify the data
length in BYTEs and does not include any Dummy Bytes. The transfer length field is either 7 or 14 bits with maximum
transfer length of 127 or 16,383 bytes (16K-1).
On the falling clock edge following the rising edge of the last dummy nibble, the SIO[3:0] pins are driven starting with
the msn of the LSB of the selected register. For a non-DWORD aligned starting address, 1-3 padding bytes (and possible Dummy Bytes per padding byte) occur prior to the data bytes. Padding bytes are not counted in the transfer length.
The remaining register nibbles are shifted out on subsequent falling clock edges. For multiple byte registers, the next
byte follows the last bit (or nibble) of the preceding byte or Dummy Byte(s). For reads of multiple registers, the first bit
(or nibble) of the next register follows the last bit (or nibble) of the preceding register or Dummy Byte(s).
The SCS# input is brought inactive to conclude the cycle. The SIO[3:0] pins are three-stated at this time.
Figure 9-12 illustrates a typical single and multiple register quad I/O read. The transfer length field may be one or two
bytes. A DWORD aligned full DWORD register is shown. The final DWORD is not followed by Dummy Bytes. A partial
DWORD register read is also possible and would terminate after the last data BYTE without subsequent Dummy
Byte(s). It is also possible for a partial DWORD read to start on a non-DWORD aligned boundary.
FIGURE 9-12:
SPI QUAD I/O READ
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
8
X
1
1
1
0
SIO1
1
0
1
1
SIO2
Z
SIO3
Z
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
Xfer Len
A
1
2
L
4
A
8
A
9
A
4
A
5
i
n
c
A
1
0
A
6
d
e
c
A
1
1
A
7
A
0
A
1
A
2
A
3
L
1
1
L
0
L
5
L
6
f
m
t
L
7
L
1
2
L
1
L
2
L
3
1
7
1
8
1
6
Address
A
1
3
Z
1
1
1
0
9
Instruction
SIO0
1
0
9
L
8
L
1
3
L
9
0
L
1
0
1
7
...
...
...
...
1
8
4 to 255 Dummy
Data
0
D
4
...
0
0
0
D
0
4 to 255 Dummy
Data
0
D
5
...
0
0
0
D
1
4 to 255 Dummy
Data
0
D
6
...
0
0
0
D
2
4 to 255 Dummy
Data
0
D
7
...
0
SPI Quad I/O Read Single Register
0
0
D
3
...
...
0 to 255
Dummy
x
...
...
x
...
x
...
D
8
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
...
X
...
X Z
Data
(+Dummy)
x
0 to 255
Dummy
x
D
1
2
Data
(+Dummy)
0 to 255
Dummy
x
X
Data
(+Dummy)
0 to 255
Dummy
x
X
...
X Z
Data
(+Dummy)
x
...
X Z
For multiple byte register
Intra-DWORD
Initial
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
8
Instruction
SIO0
SIO1
SIO2
SIO3
X
1
1
1
0
1
0
1
Z
Z
Z
SPI Quad I/O Read Multiple Registers
DS00003422A-page 180
1
0
9
1
9
1
1
1
0
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
Xfer Len
A
1
2
L
4
A
1
3
i
n
c
d
e
c
A
9
A
1
0
A
1
1
A
4
A
5
A
6
A
7
A
0
A
1
A
2
A
3
L
5
L
6
f
m
t
L
0
L
1
L
2
L
3
L
1
1
L
1
2
L
1
3
0
1
8
1
6
Address
A
8
1
7
L
7
L
8
L
9
L
1
0
1
7
...
...
...
...
1
8
4 to 255 Dummy
Reg
m
0
D
4
0
...
0
0
D
0
4 to 255 Dummy
Reg
m
0
D
5
0
...
0
0
D
1
4 to 255 Dummy
Reg
m
0
D
6
0
...
0
0
D
2
4 to 255 Dummy
Reg
m
0
D
7
0
...
Initial
0
0
D
3
... ...
... ...
0 to 255
Dummy
x
...
Reg m
(+Dummy)
x
0 to 255
Dummy
x
...
...
x
...
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
... ...
x
... ...
x
x
x
x
... ...
x
x
x
D
4
D
0
...
X
D
5
D
1
...
X Z
Reg n
(+Dummy)
x
0 to 255
Dummy
... ...
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
x
D
8
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
x
D
1
2
...
...
D
6
D
2
...
X Z
Reg n
(+Dummy)
x
D
7
D
3
...
X Z
For multiple byte register
Intra-DWORD
Inter-DWORD
2020 Microchip Technology Inc.
LAN9254
9.2.6
SPI WRITE COMMANDS
Multiple write commands are support by the SPI/SQI slave. The following applies to all write commands.
MULTIPLE WRITES
Multiple writes are performed by continuing the clock pulses and input data while SCS# is active. The upper two bits of
the address specify auto-incrementing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). The internal
DWORD address is incremented, decremented, or maintained based on these bits. Maintaining a fixed internal address
may be useful for register “bit-banging” or other repeated writes.
Constant address and Auto-increment/decrement operation for multiple DWORDs operates as follows. Note that it is
the DWORD address that remains constant or is incremented or decremented. The byte address within the DWORD
always increments:
dec/inc=00: constant DWORD aligned address
write 4 bytes within the DWORD in incrementing byte order
internal address repeats each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data input :
yyyy
valid
+1
valid
+2
valid
+3
valid
internal address : yyyy
byte address :
Second data input :
yyyy
valid
+1
valid
+2
valid
+3
valid
internal address : yyyy
byte address :
Last data input :
yyyy
valid
+1
valid
+2
valid
+3
valid
dec/inc=01: incrementing DWORD aligned starting address
write 4 bytes within each DWORD in incrementing byte order
internal address is incremented by 4 each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data input :
yyyy
valid
+1
valid
+2
valid
+3
valid
next internal address : next DWORD
byte address :
+4
Second data input :
valid
+5
valid
+6
valid
+7
valid
next internal address : next DWORD
byte address :
+8
Last data input :
valid
+9
valid
+10
valid
+11
valid
dec/inc=10: decrementing DWORD aligned starting address
write 4 bytes within each DWORD in incrementing byte order
internal address is decremented by 4 each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data input :
yyyy
valid
next internal address : previous DWORD
byte address :
-4
Second data input :
valid
2020 Microchip Technology Inc.
+1
valid
+2
valid
+3
valid
-3
valid
-2
valid
-1
valid
DS00003422A-page 181
LAN9254
next internal address : previous DWORD
byte address :
-8
Last data input :
valid
-7
valid
-6
valid
-5
valid
dec/inc=11: RESERVED
The above apply to full DWORD accesses starting at DWORD aligned addresses. See Section 9.3.2.2 for partial
DWORD accesses or non-DWORD aligned starting addresses utilized during EtherCAT Direct Mapped mode.
DUMMY BYTES
In order to provide sufficient time for posted writes to be internally processed (especially when writing to the EtherCAT
Core CSRs or Process RAM while in EtherCAT Direct Mapped mode) Dummy Byte cycles may be used. The number
of Dummy Bytes is set using the Set Configuration instruction and is specified per write command type.
There are three values per instruction. The first is the number of Dummy Bytes that will precede the first data byte. The
second is the number of Dummy Bytes that occur between bytes within a DWORD (intra-DWORD). The third is the number of Dummy Bytes that occur between DWORDs (inter-DWORD). There are no Dummy Bytes after the last data byte
of a command.
APPLICATION NOTE: The number of Dummy Bytes between DWORDs is strictly the third configuration value. It is
not in addition to or paralleled with a Dummy Byte count using the second configuration
value.
APPLICATION NOTE: The DWORD boundary applies to all write commands even if the command is using BYTE
buffering mode. The intra- and inter- number of Dummy Bytes can be set the same if
appropriate.
APPLICATION NOTE: For BYTE buffering mode used in EtherCAT Direct Mapped Mode for EtherCAT core
accesses, a Dummy byte configuration which has second parameter (intra-DWORD) equal
to 0 and the third parameter (inter-DWORD) not equal to 0 is not supported. Normally the
second and third parameters would be the same value in this case.
APPLICATION NOTE: The DWORD boundary is based on the address of the last byte written, not on the running
byte count (i.e. it is not simply every fourth byte). This is important to consider during
EtherCAT Direct Mapped Mode where the starting address could be non-DWORD aligned.
Refer to Section 9.3.2.2 for how the address is updated.
APPLICATION NOTE: The number of clock cycles for a Dummy Byte varies based on the bit width(s) of the
instruction.
9.2.6.1
Write
The Write instruction inputs the instruction code, the address, the possible initial Dummy Bytes, the data and any subsequent Dummy Byte(s) one bit per clock. In SQI mode, the instruction code, the address, the possible initial Dummy
Byte(s), and the data bytes are input four bits per clock. This instruction is supported in SPI and SQI bus protocols with
clock frequencies up to 80 MHz.
The SPI/SQI slave interface is selected by first bringing SCS# active. For SPI mode, the 8-bit WRITE instruction, 02h,
is input into the SI/SIO[0] pin, followed by the two address bytes and 0 to 255 Dummy Byte(s). For SQI mode, the 8-bit
WRITE instruction, 02h, is input into the SIO[3:0] pins, followed by the two address bytes and 0 to 255 Dummy Byte(s).
The address bytes specify a BYTE address within the device.
The data follows the address bytes. For SPI mode, the data is input into the SI/SIO[0] pin starting with the msb of the
LSB. For SQI mode the data is input nibble wide using SIO[3:0] starting with the msn of the LSB. The remaining bits/
nibbles are shifted in on subsequent clock edges.
While in LAN9252 compatibility mode, the data write to the register occurs after the 32-bits are input. In the event that
32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected.
While in EtherCAT Direct Mapped Mode, data writes to the EtherCAT Core CSRs and Process RAM may occur after
BYTEs or completed DWORDs. Data writes to the non-EtherCAT Core CSRs continue to be DWORD aligned however
incomplete DWORD writes may result in a corrupted register value.
DS00003422A-page 182
2020 Microchip Technology Inc.
LAN9254
The SCS# input is brought inactive to conclude the cycle.
Figure 9-13 illustrates a typical single and multiple register write for SPI mode. Figure 9-14 illustrates a typical single
and multiple register write for SQI mode. A DWORD aligned full DWORD register is shown. The final DWORD is not
followed by Dummy Bytes. A partial DWORD register write is also possible and would terminate after the last data BYTE
without subsequent Dummy Byte(s). It is also possible for a partial DWORD write to start on a non-DWORD aligned
boundary.
FIGURE 9-13:
SPI WRITE
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
5
Instruction
SI
X
0
0
0
0
0
0
1
6
1
7
1
8
1
6
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
6
2
4
2
5
Address
1
0
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
AL
7
Z
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
AL
15
...
...
2
6
Data
0 to 255 Dummy
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
AL
14
AL
13
AL
12
AL
11
...
0
AL bits (optionally enabled)
SO
...
...
0
0
0
D
7
D
6
D
5
D
5
D
3
...
...
D
1
D
0
0
...
0
0
0
X
Data (+Dummy)
0 to 255 Dummy
D
2
X
D
1
5
D
1
4
D
1
3
D
1
2
...
D
1
1
X
I.S. (opt enabled)
AL
10
AL
9
AL
8
I.S. I.S. I.S. I.S. I.S. I.S. I.S. I.S.
31 30 27 26 19 18 17
0
Z
For multiple byte register
SPI Write Single Register
Initial
Intra-DWO RD
SCS#
SCK (active low)
SCK (active high)
X
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
5
Instruction
SI
X
0
0
0
0
0
0
1
6
1
7
1
8
1
6
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
6
2
4
2
5
Address
1
0
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
Z
AL
7
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
AL
15
2
6
...
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
AL
14
AL
13
AL
12
AL
11
...
0
0
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
0
...
...
Reg m (+Dummy)
0 to 255 Dummy
...
0
0
D
1
5
D
1
4
D
1
3
D
1
2
...
0 to 255 Dummy
...
D
1
1
...
0
0
...
0
0
X
X
Reg n (+Dummy)
D
7
D
6
D
5
D
4
D
3
...
X
I.S. (opt enabled)
AL
10
AL
9
AL
8
I.S. I.S. I.S. I.S. I.S. I.S. I.S. I.S.
31 30 27 26 19 18 17
0
Z
For multiple byte registers
SPI Write Multiple Registers
FIGURE 9-14:
0
...
...
...
Reg m
0 to 255 Dummy
AL bits (optionally enabled)
SO
...
...
Initial
Intra-DWO RD
Inter-DWORD
SQI WRITE
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
7
Inst Address
SIO[3:0]
X
0
2
H
1
L
1
H
0
8
...
8
...
...
0
...
0
0
0
Data 0 to 255 Dummy
H
0
L
0
0
0
...
X
...
...
0 to 255 Dummy
L
0
...
0
0
X
Data (+Dummy)
H
1
L
1
H
2
L
2
...
X
For multiple byte register
SQI Write Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
X
0
2
H
1
SQI Write Multiple Registers
2020 Microchip Technology Inc.
L
1
H
0
8
6
Inst Address
SIO[3:0]
7
L
0
7
...
8
...
...
...
...
...
0 to 255 Dummy Reg m 0 to 255 Dummy
0
0
...
0
0
H
0
L
0
0
0
...
...
0
0
...
...
...
Reg m (+Dummy) 0 to 255 Dummy
H
1
L
1
H
2
L
2
...
0
0
...
0
0
X
X
Reg n (+Dummy)
H
0
L
0
H
1
L
1
...
X
For multiple byte register
Initial
Intra-DWORD
Inter-DWORD
DS00003422A-page 183
LAN9254
9.2.6.2
Dual Data Write
The SPI Dual Data Write instruction inputs the instruction code, the address and possible initial Dummy Bytes one bit
per clock and inputs the data and any subsequent Dummy Byte(s) two bits per clock. This instruction is supported in
SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDDW instruction, 32h, is input into the SIO[0]
pin, followed by the two address bytes and 0 to 255 Dummy Byte(s). The address bytes specify a BYTE address within
the device.
The data follows the address bytes. The data is input into the SIO[1:0] pins starting with the msbs of the LSB. The
remaining di-bits are shifted in on subsequent clock edges.
While in LAN9252 compatibility mode, the data write to the register occurs after the 32-bits are input. In the event that
32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected.
While in EtherCAT Direct Mapped Mode, data writes to the EtherCAT Core CSRs and Process RAM may occur after
BYTEs or completed DWORDs. Data writes to the non-EtherCAT Core CSRs continue to be DWORD aligned however
incomplete DWORD writes may result in a corrupted register value.
The SCS# input is brought inactive to conclude the cycle.
Figure 9-15 illustrates a typical single and multiple register dual data write. A DWORD aligned full DWORD register is
shown. The final DWORD is not followed by Dummy Bytes. A partial DWORD register write is also possible and would
terminate after the last data BYTE without subsequent Dummy Byte(s). It is also possible for a partial DWORD write to
start on a non-DWORD aligned boundary.
FIGURE 9-15:
SPI DUAL DATA WRITE
SCS#
SCK (active low)
SCK (active high)
X
1
X
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
5
Instruction
SIO0
X
0
0
1
1
0
0
1
6
1
7
1
6
1
8
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
2
5
1
0
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
AL
7
Z
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
...
...
Data
0 to 255 Dummy
A
6
AL
15
...
...
2
6
Address
A
5
A
4
A
3
A
2
A
1
A
0
0
AL bits (optionally enabled)
SIO1
2
6
AL
14
AL
13
AL
12
AL
11
...
0
0
0
0
D
6
I.S. (opt enabled)
AL
10
AL
9
AL
8
D
4
D
2
0 to 255 Dummy
D
0
Data
I.S . I.S . I.S . I.S . I.S . I.S . I.S . I.S .
31 30 27 26 19 18 17
0
D
7
D
5
D
3
...
...
0
0
...
0
0
0 to 255 Dummy
D
1
0
0
...
0
0
X
X
Data (+Dummy)
D
1
4
D
1
2
D
1
0
D
8
...
X
Data (+Dummy)
D
1
5
D
1
3
D
1
1
D
9
...
X Z
For multiple byte register
SPI Dual Data Write Single Register
Initial
Intra-DWORD
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
9
1
1
1
0
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
Instruction
SIO0
X
0
0
1
1
0
0
1
6
1
5
1
7
1
6
1
8
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
0
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
Z
SPI Dual Data Write Multiple Registers
DS00003422A-page 184
AL
7
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
AL
15
AL
14
2
6
A
5
A
4
A
3
A
2
A
1
A
0
AL
13
AL
12
AL
11
0
0
...
Reg m
0
0
0
D
6
I.S. (opt enabled)
AL
10
AL
9
AL
8
...
...
...
...
...
...
0 to 255 Dummy
AL bits (optionally enabled)
SIO1
...
...
2
5
Address
1
2
6
I.S . I.S . I.S . I.S . I.S . I.S . I.S . I.S .
31 30 27 26 19 18 17
0
D
4
D
2
D
0
Reg m
D
7
D
5
D
3
D
1
...
...
0 to 255 Dummy
Reg m (+Dummy) 0 to 255 Dummy
Reg n (+Dummy)
0
D
1
4
D
6
0
...
0
0
D
1
2
D
1
0
D
8
...
0
0
...
0
0
D
4
D
2
D
0
...
0 to 255 Dummy
Reg m (+Dummy) 0 to 255 Dummy
Reg n (+Dummy)
0
D
1
5
D
7
0
...
0
0
D
1
3
D
1
1
D
9
...
0
0
...
0
0
D
5
D
3
D
1
...
X
X
X
X Z
For multiple byte register
Initial
Intra-DWORD
Inter-DWORD
2020 Microchip Technology Inc.
LAN9254
9.2.6.3
Quad Data Write
The SPI Quad Data Write instruction inputs the instruction code, the address and the possible initial Dummy Bytes one
bit per clock and inputs the data and any subsequent Dummy Byte(s) four bits per clock. This instruction is supported
in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQDW instruction, 62h, is input into the SIO[0]
pin, followed by the two address bytes and 0 to 255 Dummy Byte(s). The address bytes specify a BYTE address within
the device.
The data follows the address bytes. The data is input into the SIO[3:0] pins starting with the msn of the LSB. The remaining nibbles are shifted in on subsequent clock edges.
While in LAN9252 compatibility mode, the data write to the register occurs after the 32-bits are input. In the event that
32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected.
While in EtherCAT Direct Mapped Mode, data writes to the EtherCAT Core CSRs and Process RAM may occur after
BYTEs or completed DWORDs. Data writes to the non-EtherCAT Core CSRs continue to be DWORD aligned however
incomplete DWORD writes may result in a corrupted register value.
The SCS# input is brought inactive to conclude the cycle.
Figure 9-16 illustrates a typical single and multiple register quad data write. A DWORD aligned full DWORD register is
shown. The final DWORD is not followed by Dummy Bytes. A partial DWORD register write is also possible and would
terminate after the last data BYTE without subsequent Dummy Byte(s). It is also possible for a partial DWORD write to
start on a non-DWORD aligned boundary.
FIGURE 9-16:
SPI QUAD DATA WRITE
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
5
Instruction
SIO0
X
0
1
1
0 0
0
1
6
1
7
1
6
1
8
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
2
5
0
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
0 to 255 Dummy
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
AL bits (optionally enabled)
SIO1
AL
7
Z
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
AL
15
...
...
2
6
Address
1
...
...
2
6
AL
14
AL
13
AL
12
AL
11
...
0
0
0
I.S. (opt enabled)
AL
10
AL
9
AL
8
0 to 255
Dummy
Data
0
D
4
D
0
0
D
5
D
1
0
D
6
Z
D
2
0
D
7
Z
SPI Quad Data Write Single Register
D
3
...
...
0
...
X
D
1
2
D
8
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
...
X
Data
(+Dummy)
0
...
X Z
Data
(+Dummy)
0
0 to 255
Dummy
Data
SIO3
0
0 to 255
Dummy
Data
SIO2
...
X
Data
(+Dummy)
0 to 255
Dummy
Data
I.S . I.S . I.S . I.S. I.S. I.S . I.S . I.S .
31 30 27 26 19 18 17
0
...
...
...
X Z
Data
(+Dummy)
0
...
X Z
For multiple byte register
Intra- DWORD
Initial
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
Instruction
SIO0
X
0
1
1
0 0
0
1
6
1
5
1
7
1
6
1
8
1
7
1
9
1
8
2
0
1
9
2
1
2
0
2
2
2
1
2
3
2
2
2
4
2
3
2
5
2
4
0
d
e
c
i
n
c
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
Z
AL
7
AL
6
AL
5
AL
4
AL
3
AL
2
AL
1
AL
0
AL
15
AL
14
...
...
2
6
Reg
m
0 to 255 Dummy
A
5
A
4
A
3
A
2
A
1
A
0
AL bits (optionally enabled)
SIO1
2
5
Address
1
...
...
2
6
AL
13
AL
12
AL
11
0
0
...
0
0
0
I.S. (opt enabled)
AL
10
AL
9
AL
8
I.S . I.S . I.S . I.S. I.S. I.S . I.S . I.S .
31 30 27 26 19 18 17
0
D
4
D
0
0 to 255
Dummy
0
Reg
m
D
5
D
1
D
6
Z
D
2
0
SPI Quad Data Write Multiple Registers
2020 Microchip Technology Inc.
D
7
Z
Initial
D
3
0
...
0
...
0
...
D
8
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
... ...
0
... ...
0
0
0
0
... ...
0
0
0
D
4
D
0
...
X
D
5
D
1
...
X Z
Reg n
(+Dummy)
0
0 to 255
Dummy
... ...
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
0
D
1
2
...
...
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
Reg
m
SIO3
...
Reg m
(+Dummy)
0 to 255
Dummy
Reg
m
SIO2
... ...
... ...
D
6
D
2
...
X Z
Reg n
(+Dummy)
0
D
7
D
3
...
X Z
For multiple byte register
Intra- DWORD
Inter-DWORD
DS00003422A-page 185
LAN9254
9.2.6.4
Dual Address / Data Write
The SPI Dual Address / Data Write instruction inputs the instruction code one bit per clock and the address, the possible
initial Dummy Bytes, the data and any subsequent Dummy Byte(s) two bits per clock. This instruction is supported in
SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDADW instruction, B2h, is input into the
SIO[0] pin, followed by the two address bytes and 0 to 255 Dummy Byte(s) into the SIO[1:0] pins. The address bytes
specify a BYTE address within the device.
The data follows the address bytes. The data is input into the SIO[1:0] pins starting with the msbs of the LSB. The
remaining di-bits are shifted in on subsequent clock edges.
While in LAN9252 compatibility mode, the data write to the register occurs after the 32-bits are input. In the event that
32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected.
While in EtherCAT Direct Mapped Mode, data writes to the EtherCAT Core CSRs and Process RAM may occur after
BYTEs or completed DWORDs. Data writes to the non-EtherCAT Core CSRs continue to be DWORD aligned however
incomplete DWORD writes may result in a corrupted register value.
The SCS# input is brought inactive to conclude the cycle.
Figure 9-17 illustrates a typical single and multiple register dual address / data write. A DWORD aligned full DWORD
register is shown. The final DWORD is not followed by Dummy Bytes. A partial DWORD register write is also possible
and would terminate after the last data BYTE without subsequent Dummy Byte(s). It is also possible for a partial
DWORD write to start on a non-DWORD aligned boundary.
FIGURE 9-17:
SPI DUAL ADDRESS / DATA WRITE
SCS#
SCK (active low)
SCK (active high)
X
1
X
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
1
1
1
0
9
1
1
Instruction
SIO0
X
1
0
1
1
0
0
1
2
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
1
7
1
6
1
7
Address
1
0
i
n
c
A
1
2
A
1
0
A
8
A
6
d
e
c
Z
A
1
3
A
1
1
A
9
A
7
...
...
...
...
1
8
Data
0 to 255 Dummy
A
4
A
2
A
0
0
Address
SIO1
1
8
...
0
0
0
D
6
A
5
A
3
A
1
0
...
0
0
0
D
4
D
2
0 to 255 Dummy
D
0
Data
0 to 255 Dummy
D
7
D
5
D
3
...
...
0
0
...
0
0
0 to 255 Dummy
D
1
0
0
...
0
0
X
X
Data (+Dummy)
D
1
4
D
1
2
D
1
0
D
8
...
X
Data (+Dummy)
D
1
5
D
1
3
D
1
1
D
9
...
X Z
For multiple byte register
SPI Dual Address / Data Write Single Register
Initial
Intra-DWO RD
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
1
0
9
8
9
1
1
1
0
Instruction
SIO0
X
1
0
1
1
0
0
1
2
1
1
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
1
7
1
6
Address
1
0
i
n
c
A
1
2
A
1
0
A
8
A
6
A
4
Z
d
e
c
A
1
3
SPI Dual Address / Data Write Multiple Registers
DS00003422A-page 186
A
1
1
A
9
A
7
A
5
1
7
...
...
...
...
1
8
Reg m
0 to 255 Dummy
A
2
A
0
Address
SIO1
1
8
0
0
...
0
0
D
6
A
1
0
0
...
0
0
D
2
D
0
Reg m
0 to 255 Dummy
A
3
D
4
D
7
D
5
D
3
D
1
...
...
...
...
...
...
0 to 255 Dummy
Reg m (+Dummy) 0 to 255 Dummy
0
D
1
4
0
...
0
0
D
1
2
D
1
0
D
8
...
0
0
...
0
0
0 to 255 Dummy
Reg m (+Dummy) 0 to 255 Dummy
0
D
1
5
0
...
0
0
D
1
3
D
1
1
D
9
...
0
0
...
0
0
X
X
Reg n (+Dummy)
D
6
D
4
D
2
D
0
...
X
Reg n (+Dummy)
D
7
D
5
D
3
D
1
...
X Z
For multiple byte register
Initial
Intra-DWO RD
Inter-DWORD
2020 Microchip Technology Inc.
LAN9254
9.2.6.5
Quad Address / Data Write
The SPI Quad Address / Data Write instruction inputs the instruction code one bit per clock and the address, the possible
initial Dummy Bytes, the data and any subsequent Dummy Byte(s) four bits per clock. This instruction is supported in
SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQADW instruction, E2h, is input into the
SIO[0] pin, followed by the two address bytes and 0 to 255 Dummy Byte(s) into the SIO[3:0] pins. The address bytes
specify a BYTE address within the device.
The data follows the address bytes. The data is input into the SIO[3:0] pins starting with the msn of the LSB. The remaining nibbles are shifted in on subsequent clock edges.
While in LAN9252 compatibility mode, the data write to the register occurs after the 32-bits are input. In the event that
32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not affected.
While in EtherCAT Direct Mapped Mode, data writes to the EtherCAT Core CSRs and Process RAM may occur after
BYTEs or completed DWORDs. Data writes to the non-EtherCAT Core CSRs continue to be DWORD aligned however
incomplete DWORD writes may result in a corrupted register value.
The SCS# input is brought inactive to conclude the cycle.
Figure 9-18 illustrates a typical single and multiple register dual address / data write. A DWORD aligned full DWORD
register is shown. The final DWORD is not followed by Dummy Bytes. A partial DWORD register write is also possible
and would terminate after the last data BYTE without subsequent Dummy Byte(s). It is also possible for a partial
DWORD write to start on a non-DWORD aligned boundary.
FIGURE 9-18:
SPI QUAD ADDRESS / DATA WRITE
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
8
X
1
1
1
0 0
0
1
1
1
0
9
Instruction
SIO0
1
0
9
1
2
1
1
1
3
1
2
1
3
Address
1
0
A
1
2
A
8
A
4
1
4
...
...
...
...
1
4
0 to 255 Dummy
...
A
0
0
0
0 to 255 Dummy
SIO1
A
1
3
Z
A
9
A
5
...
A
1
0
0
0 to 255 Dummy
SIO2
i
n
c
Z
A
1
0
A
6
...
A
2
0
0
0 to 255 Dummy
SIO3
d
e
c
Z
A
1
1
A
7
...
A
3
SPI Quad Address / Data Write Single Register
0
0
0 to 255
Dummy
Data
D
4
D
0
0
D
1
0
D
2
0
D
3
...
...
0
...
X
D
1
2
D
8
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
...
X
Data
(+Dummy)
0
...
X Z
Data
(+Dummy)
0
0 to 255
Dummy
Data
D
7
0
0 to 255
Dummy
Data
D
6
...
X
Data
(+Dummy)
0 to 255
Dummy
Data
D
5
...
...
...
X Z
Data
(+Dummy)
0
...
X Z
For multiple byte register
Intra-DWORD
Initial
SCS#
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
8
Instruction
SIO0
X
SIO1
SIO2
SIO3
1
1
1
0 0
Z
Z
Z
0
1
1
0
9
0
9
1
1
1
0
1
2
1
1
1
4
1
2
1
3
...
...
...
...
1
4
Address
0 to 255 Dummy
A
1
2
Reg
m
0
D
4
A
1
3
i
n
c
d
e
c
A
8
A
9
A
1
0
A
1
1
A
4
A
5
A
6
A
7
SPI Quad Address / Data Write Multiple Registers
2020 Microchip Technology Inc.
1
3
A
0
A
1
A
2
A
3
0
...
0
0
D
0
0 to 255 Dummy
Reg
m
0
D
5
0
...
0
0
D
1
0 to 255 Dummy
Reg
m
0
D
6
0
...
0
0
D
2
0 to 255 Dummy
Reg
m
0
D
7
0
...
Initial
0
0
D
3
... ...
... ...
0 to 255
Dummy
0
...
Reg m
(+Dummy)
0
0 to 255
Dummy
0
...
...
0
...
D
1
3
D
9
D
1
4
D
1
0
D
1
5
D
1
1
... ...
0
... ...
0
0
0
0
... ...
0
0
0
D
4
D
0
...
X
D
5
D
1
...
X Z
Reg n
(+Dummy)
0
0 to 255
Dummy
... ...
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
X
Reg n
(+Dummy)
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
0
D
8
0 to 255
Dummy
Reg m
(+Dummy)
0 to 255
Dummy
0
D
1
2
...
...
D
6
D
2
...
X Z
Reg n
(+Dummy)
0
D
7
D
3
...
X Z
For multiple byte register
Intra-DWORD
Inter-DWORD
DS00003422A-page 187
LAN9254
9.2.7
INTERRUPT REQUEST (AL EVENT REQUEST) AND INTERRUPT STATUS (INST_STS)
REGISTER OUTPUT
During the address phase of the SPI Read, Fast Read, Dual Output Read, Quad Output Read, Write, Dual Data Write
and Quad Data Write commands, the lower 16 bits of the AL Event Request register may be shifted out onto the SO/
SIO[1] pin. The order is LSB first. This function is shown in the above diagrams.
Output of this data is enabled by the SPI AL Event Request & INT_STS Enable bit in the PDI Configuration Register. If
not enabled, the SPI interface remains three-stated during those times.
During the first Dummy Byte (if present) following the address phase of the SPI Read, Fast Read, Dual Output Read,
Quad Output Read, Write, Dual Data Write and Quad Data Write commands, bits 31:30, 27:26, 19:17 and 0 of the Interrupt Status Register (INT_STS) may be shifted out onto the SO/SIO[1] pin. This function is shown in the above diagrams.
9.3
EtherCAT Direct Mapped Mode
In EtherCAT Direct Mapped mode, the device address space is split between the EtherCAT Core CSRs and Process
RAM (addresses 0h to 2FFFh) and the non-EtherCAT Core CSRs (addresses 3000h through 3FFFh). Access to the
non-EtherCAT Core CSRs remains to be through the existing CSR bus interface. Access to the EtherCAT Core CSRs
and Process RAM is no longer through the various EtherCAT CSR and Process RAM Command, Address, Length and
Data registers but instead it is directly between the SPI slave and the EtherCAT Core.
SPI EtherCAT Direct Mapped mode is selected by the PDI Control Register per the values in Table 13-2, "PDI Mode
Selection".
9.3.1
NON-ETHERCAT CORE CSRS
The non-EtherCAT Core CSRs continue to be accessed as they would be in LAN9252 compatibility mode.
SPI commands must not be started if there is a pending prior EtherCAT Core write. Upon the activation of SCS#, in the
absence of a pending prior write, WAIT_ACK will indicate acknowledge (not busy). If an EtherCAT Core write operation
is internally pending, the WAIT_ACK will initially indicate wait. The host may deactivate SCS# and retry the cycle at a
later time, or it may simply wait until WAIT_ACK indicates not busy. Once not busy, WAIT_ACK will indicate acknowledge through the rest of the cycle.
Note:
Non-EtherCAT Core CSR accesses do not create wait states using the wait indication on WAIT_ACK.
However, the minimum Initial Dummy Byte values listed in Table 9-1 and Table 9-2 must still be used.
These are the default values per Table 9-3. Higher values may be used if Dummy Bytes are used for EtherCAT Core CSRs and Process RAM accesses per the Time or Dummy Cycle Based section.
Waiting the equivalent time in lieu of using the Initial Dummy bytes is also not acceptable.
Registers are DWORD aligned and are a DWORD in length. Non- DWORD aligned / non-DWORD length access is not
supported. The address provided to the CSRs and interface logic is forced to be DWORD aligned.
9.3.1.1
Reads
The data read(s) from the register(s) occur(s) initially and then after every 32-bits. Registers that are affected by a read
operation are updated every 32-bits (once the current DWORD output shift has started). Multiple reads are DWORD
oriented.
To avoid internally prefetching additional data past the last data that will be output, two methods are utilized. For the
READ instruction, the SI input is used as described in Section 9.2.5.1. For other read commands (FASTREAD, SDOR,
SDIOR, SQOR, SQIOR), the data length in bytes is used as described in Section 9.2.5.2 through Section 9.2.5.6.
Auto-Increment / Decrement
Auto-increment/decrement operation for multiple DWORDs remains as described in Section 9.2.5.
9.3.1.2
Writes
The data write(s) to the register(s) occur(s) after each 32-bits are shifted in. In the event that 32-bits are not written when
SCS# is returned high, a write may occur and the register may be corrupted. Multiple writes are DWORD oriented.
DS00003422A-page 188
2020 Microchip Technology Inc.
LAN9254
Auto-Increment / Decrement
Auto-increment/decrement operation for multiple DWORDs remains as described in Section 9.2.6.
9.3.2
ETHERCAT CORE CSRS AND PROCESS RAM
Registers / Process RAM accesses may have any alignment and length (up to the limit of the read transfer length field
if applicable).
9.3.2.1
Reads
Depending on the read command used, the data reads from the EtherCAT Core occur every 8-bits or every DWORD.
It is the responsibility of the Host to only shift the output data when it is available, as described below.
READ Command:
The initial data request occurs once the address portion of the command has been shifted in. Subsequent data requests
occur when the previous data shift output starts. The READ instruction lacks the information to indicate how many bytes
of a DWORD the host will shift out. Therefore for the READ instruction, data is requested one byte at a time.
To avoid requesting additional data past the last data that will be output, the SI input is used as a read termination as
described in Section 9.2.5.1.
FASTREAD, SDOR, SDIOR, SQOR, SQIOR Commands:
The initial data request occurs once the transfer length portion of the command has been shifted in. In order to provide
a consistent time to pre-fetch the next DWORD, 0 to 3 padding bytes (and potentially Dummy Bytes per padding byte)
are pre-pended before the first valid data, achieving a DWORD aligned output. The number of bytes is based on the
starting address. Subsequent data requests occur when the current data or the first padding byte shift output starts.
The FASTREAD, SDOR, SDIOR, SQOR and SQIOR instructions contain the transfer length and, along with the starting
address, is used to calculate the number of bytes initially requested. The remaining byte count is used to calculate the
number of bytes subsequently requested, avoiding requesting additional data past the last data that will be output.
Special Handling of First Bit(s):
An active high SCK consists of a series of pulses and will stop low (on a falling edge) following the last address, transfer
length or Dummy Byte input. This falling edge corresponds to that which outputs the first data bit(s). However, it is likely
that valid data has not yet been read from the EtherCAT Core.
To account for this, the first bit(s) are output asynchronously once data is read from the EtherCAT Core. This is illustrated
in Figure 9-19.
2020 Microchip Technology Inc.
DS00003422A-page 189
LAN9254
FIGURE 9-19:
ACTIVE HIGH SCK FIRST DATA BIT(S)
SCS#
SCK (active low)
X
SCK (active high)
X
...
...
...
...
...
...
Note 3
SIO
X
INST
ADDRESS
...
...
X
X
Note 1
X
Note 2
D
7
Note 4
DATA 1
1 or 4 bytes
Notes 5, 6
X
D
7
DATA 2
X
ECAT_read_req
ECAT Read Data
DATA 1
X
DATA 2
Note 1: Active high SCK - First data bit is output asynchronously since falling edge already occurred.
Note 2: INST is either READ, FASTREAD, SDOR, SDIOR, SQOR or SQIOR.
Note 3: ADDRESS could be followed by the transfer length and / or Dummy bytes. The last clock before the data output is the one of concern.
Note 4: BYTE access shown (READ command). DWORD access (FASTREAD, SDOR, SDIOR, SQOR and SQIOR commands) could be pre-pended by pad
bytes but the same falling edge is still the one of concern.
Note 5: Falling edge of concern occurs per byte for READ command and per DWORD for FASTREAD, SDOR, SDIOR, SQOR and SQIOR commands.
Note 6: DATA could be followed by Dummy bytes. The last clock before the next byte (READ) or DWORD (others) output is the one of concern.
Auto-Increment / Decrement
Constant address and Auto-increment/decrement read operations are either BYTE or DWORD oriented depending on
the command used (READ vs FASTREAD, SDOR, SDIOR, SQOR, SQIOR).
For DWORD oriented, the DWORD address remains constant or is incremented or decremented while the byte address
within the DWORD always increments. For Auto-increment operation non-DWORD alignment and partial DWORDs are
supported. For Auto-decrement and Constant address operation only DWORD aligned starting addresses and full
DWORD transfers are supported.
READ Command (BYTE oriented):
dec/inc=00: constant BYTE address
read BYTE
internal address repeats each BYTE
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
next internal address : yyyy
byte address :
Second data output :
yyyy
valid
next internal address : yyyy
byte address :
Last data output :
yyyy
valid
dec/inc=01: incrementing BYTE address
read BYTE
internal address is incremented to next BYTE
DS00003422A-page 190
2020 Microchip Technology Inc.
LAN9254
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
next internal address : next BYTE
byte address :
+1
Second data output :
valid
next internal address : next BYTE
byte address :
+2
Last data output :
valid
dec/inc=10: decrementing BYTE address
read BYTE
internal address is decremented to previous BYTE
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
next internal address : previous BYTE
byte address :
-1
Second data output :
valid
next internal address : previous BYTE
byte address :
-2
Last data output :
valid
dec/inc=11: RESERVED
FASTREAD, SDOR, SDIOR, SQOR, SQIOR Commands (DWORD oriented):
dec/inc=00: constant DWORD aligned address
read 4 bytes within the DWORD in incrementing byte order
internal address repeats each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
internal address : yyyy
byte address :
Second data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
internal address : yyyy
byte address :
Last data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
dec/inc=01: incrementing DWORD address
read up to 4 bytes within each DWORD in incrementing byte order
internal address is incremented to next DWORD each DWORD
starting address : yyyy
2020 Microchip Technology Inc.
DS00003422A-page 191
LAN9254
internal address : DWORD address of yyyy
byte address* :
yyyy
+1
yyyy
valid
valid
pad*
pad*
valid
valid
valid
pad*
+3
+2
+1
yyyy
valid
valid
valid
valid
next internal address : next DWORD
byte address :
+4
+3
+2
+1
Second data output :
valid
+5
+4
+3
+2
valid
+6
+5
+4
+3
valid
+7
+6
+5
+4
valid
next internal address : next DWORD
byte address :
+8
+7
+6
+5
Last data output** :
valid
+9
+8
+7
+6
valid/na**
+10
+9
+8
+7
valid/na**
+11
+10
+9
+8
valid/na**
First data output* :
valid
pad*
pad*
pad*
+2
+1
yyyy
*first data output could start with pad bytes if non-DWORD aligned starting address
-- transfer length does not include any pad bytes
**last data output could be less than 4 bytes
dec/inc=10: decrementing DWORD aligned starting address
read 4 bytes within each DWORD in incrementing byte order
internal address is decremented by 4 each DWORD
starting address : yyyy
internal address : yyyy
byte address :
First data output :
yyyy
valid
+1
valid
+2
valid
+3
valid
next internal address : previous DWORD
byte address :
-4
Second data output :
valid
-3
valid
-2
valid
-1
valid
next internal address : previous DWORD
byte address :
-8
Last data output :
valid
-7
valid
-6
valid
-5
valid
dec/inc=11: RESERVED
DS00003422A-page 192
2020 Microchip Technology Inc.
LAN9254
9.3.2.2
Writes
The data write(s) to the EtherCAT Core occur either every 8-bits or after the last BYTE of a DWORD is shifted in. The
latter achieves better throughput but requires more post command processing time, potentially delaying the next command.
Multiple writes can be BYTE or DWORD oriented.
Based on the SPI command’s increment / decrement bits, the SPI interface can dynamically accumulate and write up
to 32 bits, multiple times, in one SPI bus cycle. In the case where less than 4 bytes are shifted in before the bus cycle
ends, the SPI interface commits whatever amount of data it received.
BYTE buffering is used normally.
DWORD buffering is indicated by using the normally reserved auto decrement / increment value of ‘b11.
It is the responsibility of the Host to only shift in the next data when the device is ready. This is described in the following
subsection.
Auto-Increment / Decrement
Constant address and Auto-increment/decrement write operations are either BYTE or DWORD oriented depending on
the buffering type used (BYTE buffering vs DWORD buffering).
For DWORD buffering, the DWORD address remains constant or is incremented or decremented while the byte address
within the DWORD always increments. Only Auto-increment operation is supported with DWORD buffering.
dec/inc=00: constant BYTE address
write BYTE
internal address repeats each BYTE
starting address : yyyy
internal address : yyyy
byte address :
First data input :
yyyy
valid
next internal address : yyyy
byte address :
Second data input :
yyyy
valid
next internal address : yyyy
byte address :
Last data input :
yyyy
valid
dec/inc=01: incrementing BYTE address
write BYTE
internal address is incremented to next BYTE
starting address : yyyy
internal address : yyyy
byte address :
First data input :
yyyy
valid
next internal address : next BYTE
byte address :
+1
Second data input :
valid
next internal address : next BYTE
byte address :
+2
Last data input :
valid
dec/inc=10: decrementing BYTE address
write BYTE
internal address is decremented to previous BYTE
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starting address : yyyy
internal address : yyyy
byte address :
First data input :
yyyy
valid
next internal address : previous BYTE
byte address :
-1
Second data input :
valid
next internal address : previous BYTE
byte address :
-2
Last data input :
valid
dec/inc=11: incrementing DWORD address
write up to 4 bytes within each DWORD in incrementing byte order
internal address is incremented to next DWORD each DWORD
starting address : yyyy
internal address : DWORD address of yyyy
byte address* :
yyyy
yyyy
yyyy
yyyy
First data input* :
valid
valid
valid
valid
+1
+1
+1
na*
valid
valid
valid
na*
+2
+2
na*
na*
valid
valid
na*
na*
+3
na*
na*
na*
valid
na*
na*
na*
next internal address : next DWORD
byte address :
+4
+3
+2
+1
Second data input :
valid
+5
+4
+3
+2
valid
+6
+5
+4
+3
valid
+7
+6
+5
+4
valid
next internal address : next DWORD
byte address :
+8
+7
+6
+5
Last data input** :
valid
+9
+8
+7
+6
valid/na**
+10
+9
+8
+7
valid/na**
+11
+10
+9
+8
valid/na**
*first data could be less than 4 bytes if non-DWORD aligned starting address
**last data output could be less than 4 bytes
9.3.2.3
Wait States
EtherCAT Direct Mapped mode requires the host bus to obey the access arbitration controlled by the EtherCAT Core
PDI.
Subsequent SPI commands must not be started if there is a pending prior EtherCAT Core write.
Read cycles are first arbitrated and data is returned. This requires a delay for all reads. In order to guarantee valid data
is returned, the shifting out of the read data must not occur before the worst case access time. Sequential data is
prefetched during the initial read data shift. however the shifting out of the subsequent read data must not occur before
the worst case access time.
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Write cycles are posted and executed after the data has been shifted in. For multiple writes, subsequent write cycles
may start to be shifted in but the bus speed must be limited such that the subsequent write cycle does not complete until
after the worst case write arbitration time. When DWORD Buffering is used, BYTES within the same DWORD may be
shifted in without any delay. However with DWORD Buffering, in the case of a partial DWORD being written on the final
write, SCS# must not return high until the prior write has completed.
Besides simply waiting the required time or using a sufficiently slow SPI clock speed, two other methods are available
for the host. Dummy Byte cycles are available for all read and write commands to pace the data rate.The wait / acknowledge (WAIT_ACK) pin may be used as an indication when read data may be shifted out or when the write data shift in
may complete.
Time or Dummy Cycle Based
Dummy Byte cycles are available for all read and write commands. A programmable number of Dummy Bytes can be
set per command type as well as for the first, per BYTE or per DWORD of data. The number of Dummy Bytes to be
used depends on the SPI clock speed as well as the SPI command used.
Note:
Dummy Byte cycles may coexist with the Wait / Acknowledge operation described in the following subsection. It is intended that the Dummy Bytes are shifted while Wait is indicated. The Dummy Bytes are a means
to fill the required time indicated by the Wait indication. Waiting for Wait to be negated before shifting the
Dummy Bytes would nullify the need for the them.
The following timing constraints must be followed:
Note:
The timing values in this section are preliminary and subject to change.
SPI commands must not be started if there is a pending prior EtherCAT Core write. The worst case internal write cycle
time is 250ns for a single byte plus 80ns per additional byte.
Read first BYTE - From rising edge of SCK that samples last address bit (or last transfer length bit if applicable) to data
ready - READ command 370ns, other read commands 610ns. A falling edge on SCK may occur prior to this time in
which case data is output when it becomes ready. See Section 9.3.2.1.
Note:
The “other” read commands are optimized for multiple BYTE reads. Although they have a longer initial
access time as well as the overhead of the transfer length byte(s) they may outperform the standard READ
command.
Read next BYTE - From rising edge of SCK that follows the falling edge of SCK that outputs first data bit of current
BYTE to next BYTE ready - READ command 370ns, other read commands 0ns (“read next DWORD” timing still must
be meet). Some or all of this wait time might overlap with the time it takes to shift out the current BYTE.
Read next DWORD - From rising edge of SCK that follows the falling edge of SCK that outputs first data bit of current
DWORD to next DWORD ready - READ command n/a, other read commands 610ns. Some or all of this wait time might
overlap with the time it takes to shift out the current DWORD.
Write first BYTE (BYTE Buffering mode) - to rising edge of SCK that samples last data bit - 0ns.
Write first DWORD (DWORD Buffering mode) - to rising edge of SCK that samples last data bit - 0ns.
Write next BYTE (BYTE Buffering mode) - from rising edge of SCK that samples last data bit of current BYTE to rising
edge of SCK that samples last data bit of next BYTE - 250ns. Some or all of this wait time might overlap with the time
it takes to shift in the next BYTE.
Write next full DWORD (DWORD Buffering mode) - from rising edge of SCK that samples last data bit of current
DWORD to rising edge of SCK that samples last data bit of next full DWORD - 490ns. Some or all of this wait time might
overlap with the time it takes to shift in the next DWORD,
Write last partial DWORD (DWORD Buffering mode) - from rising edge of SCK that samples last data bit of current
DWORD to rising edge of SCS# which forces write of last partial DWORD - 490ns. Some or all of this wait time might
overlap with the time it takes to shift in the partial DWORD.
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Wait / Acknowledge Operation
The host system may either wait the specified above worst case access time, or may use the WAIT_ACK signal.
Note:
Wait / Acknowledge may coexist with the Dummy Byte cycles operation described above.
Read and write cycles start with the leading edge of SCS#, which enables the WAIT_ACK output.
If an EtherCAT Core write operation is internally pending, the WAIT_ACK will initially indicate wait. In the absence of a
pending prior write, WAIT_ACK will initially indicate acknowledge (not busy).
SPI commands must not be started if there is a pending prior EtherCAT Core write. The worst case internal write cycle
time is 250ns for a single byte plus 80ns per additional byte. The host may deactivate SCS# and retry the cycle at a later
time, or it may simply wait until WAIT_ACK indicates not busy.
For reads from the EtherCAT Core CSRs and Process RAM (addresses 0h to 2FFFh), following the shift in of the
address, WAIT_ACK will change to indicate wait as the SPI interface retrieves the read data from the EtherCAT Core.
Once the read data is available, WAIT_ACK will indicate acknowledge and the host may shift out the data.
Note:
Per “Special Handling of First Bit(s)” in Section 9.3.2.1, the first falling SCK edge of each data may occur
before data is ready, in which case data will be output asynchronously when ready.
Following the shift out of the first bit of data (on the rising edge following the falling edge that outputs the data),
WAIT_ACK will indicate wait once again, as the SPI interface pre-fetches the next read data.(assuming there is a next
pre-fetch otherwise WAIT_ACK will remain indicating acknowledge).
FIGURE 9-20:
SPI WAIT ACK ETHERCAT CORE READ
SCS#
SCK (active low)
X
SCK (active high)
X
SIO
...
...
INST
X
Note 4
...
...
...
...
...
ADDRESS
D
7
X
Note 5
Note 6
...
D
0
DATA 1
X
X
D
7
DATA 2
X
D
0
X
Note 8
ECAT_write_req
(internal signal)
ECAT_read_req
(internal signal)
Notes 2, 7
Note 3
ECAT_ack
(internal signal)
WAIT_ACK
Z
Note 1
Z
Note 1: WAIT_ACK initially high due to no pending internal write.
Note 2: Next read request along with next WAIT_ACK starts on rising edge after first data shift started.
Note 3: 3 rd read request not performed, therefore WAIT_ACK remains inactive.
Note 4: INST is either READ, FASTREAD, SDOR, SDIOR, SQOR or SQIOR.
Note 5: ADDRESS could be followed by the transfer length and / or Dummy bytes. WAIT_ACK becomes active on the last address or transfer length input.
Any Dummy bytes occur in parallel with WAIT_ACK.
Note 6: BYTE access shown (READ command). DWORD access (FASTREAD, SDOR, SDIOR, SQOR and SQIOR commands) could be pre -pended by pad bytes.
Note 7: WAIT_ACK occurs per byte (READ) or per DWORD (others).
Note 8: DATA could be followed by Dummy bytes which would occur in parallel with WAIT_ACK.
Note: Active High Push-Pull WAIT_ACK shown.
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For writes to the EtherCAT Core CSRs and Process RAM (addresses 0h to 2FFFh), depending on the write buffering
mode, WAIT_ACK will change to indicate wait following the shift in of the last data bit of each BYTE or of each (potentially partial) DWORD. Following the last data bit shift in, an internal write operation is initiated. Once the internal write
operation has completed, WAIT_ACK will indicate acknowledge. The host may start the next data input during the internal write wait time, however it may only complete the BYTE / DWORD when acknowledge is indicated.
FIGURE 9-21:
SPI WAIT ACK ETHERCAT CORE WRITE
SCS#
SCK (active low)
X
SCK (active high)
X
...
...
...
...
...
...
...
...
Note 2
SIO
X
INST
Note 5
ECAT_write_req
(internal signal)
ADDRESS
D
7
DATA 1
Note 6
D
0
D
7
X
X
Note 3
DATA 2
D
0
X
Note 4
Note 7,8
Note 9
ECAT_read_req
(internal signal)
ECAT_ack
(internal signal)
WAIT_ACK
Z
Note 1
Z
Note 1: WAIT_ACK initially high due to no pending internal write.
Note 2: Host can start next data write shift during internal write.
Note 3: Host must wait before finishing next data write.
Note 4: Host can finish SPI cycle with final internal write pending.
Note 5: INST is either WRITE, SDDW, SDADW, DQDW or SQADW.
Note 6: ADDRESS could be followed by Dummy bytes.
Note 7: DATA could be followed by Dummy bytes which would occur in parallel with
WAIT_ACK.
Note 8: BYTE Buffering mode shown. DWORD Buffering mode is the same except internal write and WAIT occurs at the end of a DWO
RD (bit D24).
Note 9: For DWORD Buffering mode, internal write occurs on SCS# inactive if last bit is not D24.
Note: Active High Push -Pull WAIT_ACK shown.
WAIT_ACK becomes undriven with the negation of SCS#.
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9.4
Controller Access Errors
The following access errors are detected by the SPI interface:
• A SPI command started while a prior write was pending (EtherCAT Direct Mapped Mode only).
• For non-EtherCAT Core CSR access, the number of clock cycles during the data phase of the transfer does not
align to a DWORD multiple (incomplete DWORDs were transferred).
• For EtherCAT Core CSR and Process RAM access, the number of clock cycles during the data phase of the transfer does not align to a byte multiple (incomplete BYTEs were transferred) (EtherCAT Direct Mapped Mode only).
• For a READ instruction, the data phase was not terminated by setting SI high for the last byte.
• For a READ instruction, additional bytes were read after setting SI high for the last byte.
• For the FASTREAD, SDOR, SDIOR, SQOR, SQIOR instructions, the incorrect number of bytes were read
(not matching the byte length provided).
• For a EtherCAT Core CSR and Process RAM read access (EtherCAT Direct Mapped Mode only):
a) For the initial access, a rising SCK following the last address, transfer length or Dummy Byte input occurred
while the interface was busy fetching the data.
b) For subsequent accesses, a rising SCK following the last current data or Dummy Byte output occurred while the
interface was busy fetching the next data.
(Testing on the rising SCK allows for a falling edge on the address, transfer length, Dummy Bytes or last bit of the
current data before the next data is ready for the active high SCK case - see Section 9.3.2.1).
• For a write access, the last data clock cycle of the current BYTE (BYTE Buffering) or DWORD (DWORD Buffering)
occurred while a prior write was pending (EtherCAT Direct Mapped Mode only).
• For a write access, SCS# became inactive (committing the current partial DWORD write) while a prior write was
pending (EtherCAT Direct Mapped Mode only).
The PDI Error Counter Register will be incremented and the reason of the access error can be read in the PDI Error
Code Register. The PDI Error Code Register bit definitions are detailed in Section 11.16.40.
Note:
A transfer may contain multiple errors. Sequential errors are counted individually as they occur. The error
status is updated as each error occurs, overwriting any previous error status. Simultaneous errors that
occur at the end of the transfer (“Incomplete BYTE or DWORD”, “Read finished without setting SI high for
the last byte” and “Actual read length did not match byte length provided”) cause the PDI Error Counter
Register to increment only once more. The error status will still overwrite any previous error status. however, for multiple simultaneous errors, the error status may indicate multiple conditions.
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9.5
SPI/SQI Timing Requirements
SPI/SQI interface pin timing is described below. Data access time for EtherCAT Direct Mapped Mode is described in
Section 9.3.2.3, Wait States.
FIGURE 9-22:
SPI/SQI INPUT TIMING
tscshl
SCS#
tscss
SCK
(active high)
thigh
tlow
tscsh
thigh
tlow
tscsh
tscss
SCK
(active low)
tsu
thd
SI/SIO[3:0]
FIGURE 9-23:
SPI/SQI OUTPUT TIMING
SCS#
thigh
tlow
SCK
ton
tv
tho
SO/SIO[3:0]
FIGURE 9-24:
SPI/SQI WAIT_ACK TIMING
SCS#
SCK
(active high)
SCK
(active low)
WAIT_ACK
(push pull)
WAIT_ACK
(open drain)
twait_on
tscs_wait
tsck_wait
wait
twait_on
tscs_wait
ack
tsck_wait
wait
tdv_ack
SO/SIO[3:0]
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TABLE 9-4:
SPI/SQI TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
30 / 80
MHz
fsck
SCK clock frequency Note 11
thigh
SCK high time
5.5
ns
tlow
SCK low time
5.5
ns
tscss
SCS# setup time to SCK
5
ns
tscsh
SCS# hold time from SCK
5
ns
tscshl
SCS# inactive time
50
ns
tsu
Data input setup time to SCK
3
ns
thd
Data input hold time from SCK
4
ns
ton
Data output turn on time from SCK
0
ns
3.3V VDDIO
30pF: 9
10pF: 8.5
Data output valid time from SCK Note 12
tv
Application Note: Depending on the clock frequency and pulse width, data may not be valid until
following the next rising edge of SCK. This is normal with high speed SPI slaves (SPI flashes, etc.).
The host SPI controller would need to delay the
sampling of the data by either a fixed time or by
using the falling edge of SCK.
tho
Data output hold time from SCK
tdis
Data output disable time from SCS# inactive
1.8V VDDIO
30pF: 13
10pF: 12
0
ns
ns
20
ns
twait_on
WAIT_ACK turn on time from SCS# active
tscs_wait
WAIT_ACK valid from SCS# active
15
ns
tdis_wait
WAIT_ACK disable time from SCS# inactive
20
ns
tsck_wait
WAIT_ACK assertion from SCK
15
ns
tdv_ack
Read Data asynchronous output valid before
WAIT_ACK de-assertion
0
15
ns
ns
Note 11: The Read instruction is limited to 30 MHz maximum.
Note 12: Depends on loading and supply voltage.
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10.0
ETHERNET PHYS
10.1
Functional Overview
The device contains PHYs A and B, which are identical in functionality. PHY A connects to either port 0 or 2 of the EtherCAT Core. PHY B connects to port 1 of the EtherCAT core. These PHYs interface with their respective MAC via an
internal MII interface.
The PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet specification and can be configured for
full/half duplex 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation. However, only full duplex,
100BASE-TX operation is used for EtherCAT. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set and are fully configurable.
10.1.1
PHY ADDRESSING
Each individual PHY is assigned a default PHY address. The address for PHY A is set to 0 or 2, based on the device
mode. The address for PHY B is fixed to 1.
In addition, the addresses for the PHYs can be changed via the PHY Address (PHYADD) field in the PHY x Special
Modes Register (PHY_SPECIAL_MODES_x).
10.2
PHYs A & B
The device integrates two IEEE 802.3 PHY functions. The PHYs are configured for 100 Mbps copper (100BASE-TX)
Ethernet operation and include Auto-Negotiation and HP Auto-MDIX.
Note:
10.2.1
Because PHYs A and B are functionally identical, this section will describe them as “PHY x”, or simply
“PHY”. Wherever a lowercase “x” has been appended to a port or signal name, it can be replaced with “A”
or “B” to indicate the PHY A or PHY B respectively. In some instances, a “1” or a “2” may be appropriate
instead. All references to “PHY” in this section can be used interchangeably for both the PHYs A and B.
FUNCTIONAL DESCRIPTION
Functionally, each PHY can be divided into the following sections:
•
•
•
•
•
•
•
•
•
•
100BASE-TX Transmit and 100BASE-TX Receive
Auto-Negotiation
HP Auto-MDIX
PHY Management Control and PHY Interrupts
PHY Power-Down Modes
Wake on LAN (WoL)
Resets
Link Integrity Test
Cable Diagnostics
Loopback Operation
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A block diagram of the main components of each PHY can be seen in Figure 10-1.
FIGURE 10-1:
PHY BLOCK DIAGRAM
AutoNegotiation
100
Transmitter
To Port x
EtherCAT MAC
MII
TXPx/TXNx
MII
MAC
Interface
HP Auto-MDIX
RXPx/RXNx
To External
Port x Ethernet Pins
100
Reciever
To EtherCAT
core
MDI O
PHY Management
Control
Regist ers
PLL
Interrupts
To System
Interrupt Controller
10.2.2
From
System Clocks Controller
100BASE-TX TRANSMIT
The 100BASE-TX transmit data path is shown in Figure 10-2. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
FIGURE 10-2:
100BASE-TX TRANSMIT DATA PATH
Internal
MII Transmit Clock
100M
PLL
Internal
MII 25 MHz by 4 bits
MII MAC
Interface
Port x
MAC
25MHz
by 4 bits
4B/5B
Encoder
25MHz by
5 bits
Scrambler
and PISO
125 Mbps Serial
NRZI
Converter
NRZI
MLT-3
Converter
MLT-3
100M
TX Driver
MLT-3
Magnetics
MLT-3
RJ45
10.2.2.1
MLT-3
CAT-5
100BASE-TX Transmit Data Across the Internal MII Interface
For a transmission, the EtherCAT Core MAC drives the transmit data onto the internal MII TXD bus and asserts the internal MII TXEN to indicate valid data. The data is in the form of 4-bit wide 25 MHz data.
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10.2.2.2
4B/5B Encoder
The transmit data passes from the MII block to the 4B/5B Encoder. This block encodes the data from 4-bit nibbles to 5bit symbols (known as “code-groups”) according to Table 10-1. Each 4-bit data-nibble is mapped to 16 of the 32 possible
code-groups. The remaining 16 code-groups are either used for control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The
remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /
I/, a transmit error code-group is /H/, etc.
TABLE 10-1:
4B/5B CODE TABLE
Code Group
Sym
Receiver Interpretation
11110
0
0
0000
01001
1
1
10100
2
10101
0
0000
0001
1
0001
2
0010
2
0010
3
3
0011
3
0011
01010
4
4
0100
4
0100
01011
5
5
0101
5
0101
01110
6
6
0110
6
0110
01111
7
7
0111
7
0111
10010
8
8
1000
8
1000
10011
9
9
1001
9
1001
10110
A
A
1010
A
1010
10111
B
B
1011
B
1011
11010
C
C
1100
C
1100
11011
D
D
1101
D
1101
11100
E
E
1110
E
1110
11101
F
F
1111
F
1111
11111
/I/
IDLE
Sent after /T/R/ until the MII Transmitter
Enable signal (TXEN) is received
11000
/J/
First nibble of SSD, translated to “0101”
following IDLE, else MII Receive Error
(RXER)
Sent for rising MII Transmitter Enable
signal (TXEN)
10001
/K/
Second nibble of SSD, translated to
“0101” following J, else MII Receive Error
(RXER)
Sent for rising MII Transmitter Enable
signal (TXEN)
01101
/T/
First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of MII Receive Error (RXER)
Sent for falling MII Transmitter Enable
signal (TXEN)
00111
/R/
Second nibble of ESD, causes de-assertion of CRS if following /T/, else assertion
of MII Receive Error (RXER)
Sent for falling MII Transmitter Enable
signal (TXEN)
00100
/H/
Transmit Error Symbol
Sent for rising MII Transmit Error (TXER)
2020 Microchip Technology Inc.
DATA
Transmitter Interpretation
DATA
DS00003422A-page 203
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TABLE 10-1:
4B/5B CODE TABLE (CONTINUED)
Code Group
Sym
00110
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
11001
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00001
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00010
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00011
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00101
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
01000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
01100
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
10000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
10.2.2.3
Receiver Interpretation
Transmitter Interpretation
Scrambler and PISO
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band
peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire
channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being
radiated by the physical wiring.
The seed for the scrambler is generated from the PHY address, ensuring that each PHY will have its own scrambler
sequence. For more information on PHY addressing, refer to Section 10.1.1, "PHY Addressing".
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
10.2.2.4
NRZI and MLT-3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI
data stream. The NRZI is then encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents
a code bit “1” and the logic output remaining at the same level represents a code bit “0”.
10.2.2.5
100M Transmit Driver
The MLT-3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal on output pins TXPx
and TXNx, to the twisted pair media across a 1:1 ratio isolation transformer. The transmitter drives into the 100 impedance of the CAT-5 cable. Cable termination and impedance matching require external components.
10.2.2.6
100M Phase Lock Loop (PLL)
The 100M PLL locks onto the reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and
the 100BASE-TX Transmitter.
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10.2.3
100BASE-TX RECEIVE
The 100BASE-TX receive data path is shown in Figure 10-3. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
FIGURE 10-3:
100BASE-TX RECEIVE DATA PATH
100M
PLL
Internal
MII Receive Clock
Port x
MAC
MII MAC
Interface
Internal
MII 25MHz by 4 bits
25MHz
by 4 bits
4B/5B
Decoder
25MHz by
5 bits
Descrambler
and SIPO
125 Mbps Serial
NRZI
Converter
A/D
Converter
MLT-3
Converter
NRZI
MLT-3
Magnetics
MLT-3
MLT-3
RJ45
DSP: Timing
recovery, Equalizer
and BLW Correction
MLT-3
CAT-5
6 bit Data
10.2.3.1
100M Receive Input
The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quantizer, 6 digital bits are
generated to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such
that the full dynamic range of the ADC can be used.
10.2.3.2
Equalizer, BLW Correction and Clock/Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer
can restore the signal for any good-quality CAT-5 cable between 1m and 100m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)
on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive
the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP,
selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to
extract the serial data from the received signal.
10.2.3.3
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an
NRZI data stream.
10.2.3.4
Descrambler
The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel
Out (SIPO) conversion of the data.
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During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once
synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols
within a window of 4000 bytes (40 us). This window ensures that a maximum packet size of 1514 bytes, allowed by the
IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,
receive operation is aborted and the descrambler re-starts the synchronization process.
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)
pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of
frame.
10.2.3.5
5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is presented on the internal MII RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the
MAC preamble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid
data is available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the
End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to deassert carrier sense and receive data valid signal.
Note:
10.2.3.6
These symbols are not translated into data.
Receive Data Valid Signal
The internal MII’s Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented
on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized
and RXD is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.
RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface.
10.2.3.7
Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0
through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RXER signal is asserted
and arbitrary data is driven onto the internal MII’s RXD[3:0] lines. Should an error be detected during the time that the /
J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and the value 1110b is driven onto the RXD[3:0]
lines. Note that the internal MII’s data valid signal (RXDV) is not yet asserted when the bad SSD occurs.
10.2.3.8
100M Receive Data Across the Internal MII Interface
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are clocked to the controller at a rate of 25 MHz. RXCLK is the output clock for the internal MII bus. It is recovered from the received data to
clock the RXD bus. If there is no received signal, it is derived from the system reference clock.
10.2.4
10BASE-T TRANSMIT
10BASE-T is not used for EtherCAT.
10.2.5
AUTO-NEGOTIATION
The purpose of the Auto-Negotiation function is to automatically configure the transceiver to the optimum link parameters based on the capabilities of its link partner. Auto-Negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by
both sides. Auto-Negotiation is fully defined in clause 28 of the IEEE 802.3 specification and is enabled by setting the
Auto-Negotiation Enable (PHY_AN) of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x).
The advertised capabilities of the PHY are stored in the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x). The transceiver supports “Next Page” capability which is used to negotiate Energy Efficient Ethernet functionality
as well as to support software controlled pages. Many of the default advertised capabilities of the PHY are determined
via configuration straps as shown in Section 10.2.18.5, "PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 233. Refer to Section 3.3, "Configuration Straps," on page 36 for additional details on how to use the
device configuration straps.
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Once Auto-Negotiation has completed, information about the resolved link and the results of the negotiation process
are reflected in the Speed Indication bits in the PHY x Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x), as well as the PHY x Auto-Negotiation Link Partner Base Page Ability Register
(PHY_AN_LP_BASE_ABILITY_x). The Auto-Negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller.
The following blocks are activated during an Auto-Negotiation session:
•
•
•
•
•
•
•
Auto-Negotiation (digital)
100M ADC (analog)
100M PLL (analog)
100M equalizer/BLW/clock recovery (DSP)
10M SQUELCH (analog)
10M PLL (analog)
10M Transmitter (analog)
When enabled, Auto-Negotiation is started by the occurrence of any of the following events:
• Power-On Reset (POR)
• Hardware reset (RST#)
• PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the PHY x Basic Control Register
(PHY_BASIC_CONTROL_x))
• PHY Power-down reset (Section 10.2.9, "PHY Power-Down Modes," on page 212)
• PHY Link status down (bit 2 of the PHY x Basic Status Register (PHY_BASIC_STATUS_x) is cleared)
• Setting the PHY x Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 high (auto-neg restart)
• EtherCAT System Reset
Note:
Refer to Section 6.2, "Resets," on page 46 for information on these and other system resets.
On detection of one of these events, the transceiver begins Auto-Negotiation by transmitting bursts of Fast Link Pulses
(FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal Link Pulses and can pass
uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered
pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent,
contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28.
In summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It
advertises its technology ability according to the bits set in the PHY x Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x).
There are 4 possible matches of the technology abilities. In the order of priority these are:
•
•
•
•
100M Full Duplex (Highest priority)
100M Half Duplex (Not used for EtherCAT)
10M Full Duplex (Not used for EtherCAT)
10M Half Duplex (Lowest priority) (Not used for EtherCAT)
If the full capabilities of the transceiver are advertised (100M, full-duplex), and if the link partner is capable of 10M and
100M, then Auto-Negotiation selects 100M as the highest performance mode. If the link partner is capable of half and
full-duplex modes, then Auto-Negotiation selects full-duplex as the highest performance mode.
Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any difference in the main content of the link code words at this time will cause Auto-Negotiation to re-start. Auto-Negotiation
will also re-start if not all of the required FLP bursts are received.
Writing the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) bits [8:5] allows software control of the
capabilities advertised by the transceiver. Writing the PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) does not automatically re-start Auto-Negotiation. The Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY x
Basic Control Register (PHY_BASIC_CONTROL_x) must be set before the new abilities will be advertised. Auto-Negotiation can also be disabled via software by clearing the Auto-Negotiation Enable (PHY_AN) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x).
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10.2.5.1
Pause Flow Control
Pause flow control is not used for EtherCAT.
10.2.5.2
Parallel Detection
Parallel detection is not used for EtherCAT.
10.2.5.3
Restarting Auto-Negotiation
Auto-Negotiation can be re-started at any time by setting the Restart Auto-Negotiation (PHY_RST_AN) bit of the PHY
x Basic Control Register (PHY_BASIC_CONTROL_x). Auto-Negotiation will also re-start if the link is broken at any time.
A broken link is caused by signal loss. This may occur because of a cable break, or because of an interruption in the
signal transmitted by the Link Partner. Auto-Negotiation resumes in an attempt to determine the new link configuration.
If the management entity re-starts Auto-Negotiation by setting the Restart Auto-Negotiation (PHY_RST_AN) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x), the device will respond by stopping all transmission/receiving operations. Once the internal break_link_time is completed in the Auto-Negotiation state-machine (approximately
1200ms), Auto-Negotiation will re-start. In this case, the link partner will have also dropped the link due to lack of a
received signal, so it too will resume Auto-Negotiation.
10.2.5.4
Disabling Auto-Negotiation
Auto-Negotiation can be disabled by clearing the Auto-Negotiation Enable (PHY_AN) bit of the PHY x Basic Control
Register (PHY_BASIC_CONTROL_x). The transceiver will then force its speed of operation to reflect the information in
the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) (Speed Select LSB (PHY_SPEED_SEL_LSB) and
Duplex Mode (PHY_DUPLEX)). These bits are ignored when Auto-Negotiation is enabled.
10.2.5.5
Half Vs. Full-Duplex
Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If
data is received while the transceiver is transmitting, a collision results.
In full-duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode, CRS responds
only to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled.
EtherCAT requires the use of full-duplex operation.
10.2.6
HP AUTO-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP interconnect cable without
consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable or a cross-over patch cable,
as shown in Figure 10-4, the transceiver is capable of configuring the TXPx/TXNx and RXPx/RXNx twisted pair pins for
correct transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs
are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and
termination of an Auto-MDIX design.
The default enable state of Auto-MDIX is controlled by the AMDIX Disable PHY A and AMDIX Disable PHY B bits in the
Hardware Configuration Register (HW_CFG).
Software based control of the Auto-MDIX function may be performed using the Auto-MDIX Control (AMDIXCTRL) bit of
the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL
is set to 1, the Auto-MDIX capability is determined by the Auto-MDIX Enable (AMDIXEN) and Auto-MDIX State (AMDIXSTATE) bits of the PHY x Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x).
Note:
When operating in 10BASE-T or 100BASE-TX manual modes, the Auto-MDIX crossover time can be
extended via the Extend Manual 10/100 Auto-MDIX Crossover Time bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). Refer to Section 10.2.18.12, on page 242
for additional information.
When Energy Detect Power-Down is enabled, the Auto-MDIX crossover time can be extended via the
EDPD Extend Crossover bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register
(PHY_EDPD_CFG_x). Refer to Section 10.2.18.12, on page 242 for additional information
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FIGURE 10-4:
DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION
RJ‐45 8‐pin straight‐through for
10BASE‐T/100BASE‐TX signaling
RJ‐45 8‐pin cross‐over for
10BASE‐T/100BASE‐TX signaling
TXPx
1
1
TXPx
TXPx
1
1
TXPx
TXNx
2
2
TXNx
TXNx
2
2
TXNx
RXPx
3
3
RXPx
RXPx
3
3
RXPx
Not Used
4
4
Not Used
Not Used
4
4
Not Used
Not Used
5
5
Not Used
RXNx
6
6
RXNx
Not Used
5
5
Not Used
RXNx
6
6
RXNx
Not Used
7
7
Not Used
Not Used
7
7
Not Used
Not Used
8
8
Not Used
Not Used
8
8
Not Used
Direct Connect Cable
10.2.7
Cross‐Over Cable
PHY MANAGEMENT CONTROL
The PHY Management Control block is responsible for the management functions of the PHY, including register access
and interrupt generation. A Serial Management Interface (SMI) is used to support registers as required by the IEEE
802.3 (Clause 22), as well as the vendor specific registers allowed by the specification. The SMI interface consists of
the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals allow access to
all PHY registers. Refer to Section 10.2.18, "PHY Registers," on page 225 for a list of all supported registers and register
descriptions. Non-supported registers will be read as FFFFh.
10.2.8
PHY INTERRUPTS
The PHY contains the ability to generate various interrupt events. Reading the PHY x Interrupt Source Flags Register
(PHY_INTERRUPT_SOURCE_x) shows the source of the interrupt. The PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) enables or disables each PHY interrupt.
The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is sent to
the System Interrupt Controller and is reflected via the PHY A Interrupt Event (PHY_INT_A) and PHY B Interrupt Event
(PHY_INT_B) bits of the Interrupt Status Register (INT_STS). For more information on the device interrupts, refer to
Section 7.0, "System Interrupts," on page 60.
The PHY interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both modes
will assert the internal interrupt signal sent to the System Interrupt Controller when the corresponding mask bit is set.
These modes differ only in how they de-assert the internal interrupt signal. These modes are detailed in the following
subsections.
Note:
The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative
interrupt mode requires setup after a power-up or hard reset.
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10.2.8.1
Primary Interrupt Mode
The Primary interrupt mode is the default interrupt mode. The Primary interrupt mode is always selected after power-up
or hard reset. In this mode, to enable an interrupt, set the corresponding mask bit in the PHY x Interrupt Mask Register
(PHY_INTERRUPT_MASK_x) (see Table 10-2). When the event to assert an interrupt is true, the internal interrupt signal will be asserted. When the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be
de-asserted.
TABLE 10-2:
Mask
INTERRUPT MANAGEMENT TABLE
Interrupt Source Flag
Interrupt Source
Event to Assert
interrupt
Event to
De-assert interrupt
30.9
29.9
Link Up
LINKSTAT
See Note 1
Link Status
Rising LINKSTAT
Falling LINKSAT or
Reading register 29
30.8
29.8
Wake on LAN
WOL_INT
See Note 2
Enabled
WOL event
Rising WOL_INT
Falling WOL_INT or
Reading register 29
30.7
29.7
ENERGYON
17.1
ENERGYON
Rising 17.1
(Note 3)
Falling 17.1 or
Reading register 29
30.6
29.6
Auto-Negotiation complete
1.5
Auto-Negotiate Complete
Rising 1.5
Falling 1.5 or
Reading register 29
30.5
29.5
Remote Fault
Detected
1.4
Remote
Fault
Rising 1.4
Falling 1.4, or
Reading register 1 or
Reading register 29
30.4
29.4
Link Down
1.2
Link Status
Falling 1.2
Reading register 1 or
Reading register 29
30.3
29.3
Auto-Negotiation LP Acknowledge
5.14
Acknowledge
Rising 5.14
Falling 5.14 or
Reading register 29
30.2
29.2
Parallel Detection Fault
6.4
Parallel
Detection
Fault
Rising 6.4
Falling 6.4 or
Reading register 6, or
Reading register 29, or
Re-Auto Negotiate or
Link down
30.1
29.1
Auto-Negotiation Page
Received
6.1
Page
Received
Rising 6.1
Falling 6.1 or
Reading register 6, or
Reading register 29, or
Re-Auto Negotiate, or
Link down.
Note 1: LINKSTAT is the internal link status and is not directly available in any register bit.
Note 2: WOL_INT is defined as bits 7:4 in the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) ANDed
with bits 3:0 of the same register, with the resultant 4 bits OR’ed together.
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Note 3: If the mask bit is enabled and the internal interrupt signal has been de-asserted while ENERGYON is still
high, the internal interrupt signal will assert for 256 ms, approximately one second after ENERGYON goes
low when the Cable is unplugged. To prevent an unexpected assertion of the internal interrupt signal, the
ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine.
Note:
10.2.8.2
The Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the INT7 bit
in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will also read as a ‘1’ at
power-up. If no signal is present, then both Energy On (ENERGYON) and INT7 will clear within a few milliseconds.
Alternate Interrupt Mode
The Alternate interrupt mode is enabled by setting the ALTINT bit of the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) to “1”. In this mode, to enable an interrupt, set the corresponding bit of the in the PHY
x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) (see Table 10-3). To clear an interrupt, clear the interrupt
source and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause
the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If
the condition to de-assert is true, then the Interrupt Source Flag is cleared and the internal interrupt signal is also deasserted. If the condition to de-assert is false, then the Interrupt Source Flag remains set, and the internal interrupt signal
remains asserted.
TABLE 10-3:
Mask
ALTERNATIVE INTERRUPT MODE MANAGEMENT TABLE
Interrupt Source Flag
Interrupt Source
Event to
Assert
interrupt
Condition
to
De-assert
Bit to Clear
interrupt
30.9
29.9
Link Up
LINKSTAT
See
Note 4
Link Status
Rising LINKSTAT
LINKSTAT
low
29.9
30.8
29.8
Wake on LAN
WOL_INT
See
Note 5
Enabled
WOL event
Rising
WOL_INT
WOL_INT
low
29.8
30.7
29.7
ENERGYON
17.1
ENERGYON
Rising 17.1
17.1 low
29.7
30.6
29.6
Auto-Negotiation complete
1.5
Auto-Negotiate Complete
Rising 1.5
1.5 low
29.6
30.5
29.5
Remote Fault
Detected
1.4
Remote
Fault
Rising 1.4
1.4 low
29.5
30.4
29.4
Link Down
1.2
Link Status
Falling 1.2
1.2 high
29.4
30.3
29.3
Auto-Negotiation LP Acknowledge
5.14
Acknowledge
Rising 5.14
5.14 low
29.3
30.2
29.2
Parallel Detection Fault
6.4
Parallel
Detection
Fault
Rising 6.4
6.4 low
29.2
30.1
29.1
Auto-Negotiation Page
Received
6.1
Page
Received
Rising 6.1
6.1 low
29.1
Note 4: LINKSTAT is the internal link status and is not directly available in any register bit.
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Note 5: WOL_INT is defined as bits 7:4 in the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) ANDed
with bits 3:0 of the same register, with the resultant 4 bits OR’ed together.
Note:
10.2.9
The Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the INT7 bit
in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will also read as a ‘1’ at
power-up. If no signal is present, then both Energy On (ENERGYON) and INT7 will clear within a few milliseconds.
PHY POWER-DOWN MODES
There are two PHY power-down modes: General Power-Down Mode and Energy Detect Power-Down Mode. These
modes are described in the following subsections.
Note:
For more information on the various power management features of the device, refer to Section 6.3,
"Power Management," on page 51.
The power-down modes of each PHY are controlled independently.
The PHY power-down modes do not reload or reset the PHY registers.
10.2.9.1
General Power-Down
This power-down mode is controlled by the Power Down (PHY_PWR_DWN) bit of the PHY x Basic Control Register
(PHY_BASIC_CONTROL_x). In this mode the entire transceiver, except the PHY management control interface, is
powered down. The transceiver will remain in this power-down state as long as the Power Down (PHY_PWR_DWN) bit
is set. When the Power Down (PHY_PWR_DWN) bit is cleared, the transceiver powers up and is automatically reset.
10.2.9.2
Energy Detect Power-Down
This power-down mode is enabled by setting the Energy Detect Power-Down (EDPWRDOWN) bit of the PHY x Mode
Control/Status Register (PHY_MODE_CONTROL_STATUS_x). In this mode, when no energy is present on the line, the
entire transceiver is powered down (except for the PHY management control interface, the SQUELCH circuit and the
ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASET, or Auto-Negotiation signals.
In this mode, when the Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) signal is low, the transceiver is powered down and nothing is transmitted. When energy is received,
via link pulses or packets, the Energy On (ENERGYON) bit goes high, and the transceiver powers up. The transceiver
automatically resets itself into the state prior to power-down, and asserts the INT7 bit of the PHY x Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x). The first and possibly second packet to activate ENERGYON may be
lost.
When the Energy Detect Power-Down (EDPWRDOWN) bit of the PHY x Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is low, energy detect power-down is disabled.
When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs
in EDPD via the EDPD TX NLP Enable bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register
(PHY_EDPD_CFG_x). When enabled, the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer
Select field of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x). When in
EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPD RX
Single NLP Wake Enable bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x) will enable the device to wake on reception of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared,
the maximum interval for detecting reception of two NLPs to wake from EDPD is configurable via the EDPD RX NLP
Max Interval Detect Select field of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x).
The energy detect power down feature is part of the broader power management features of the device and can be used
to trigger the power management event output pin (PME) or the general interrupt request pin (IRQ). This is accomplished by enabling the energy detect power-down feature of the PHY as described above, and setting the corresponding energy detect enable (bit 14 for PHY A, bit 15 for PHY B) of the Power Management Control Register (PMT_CTRL).
Refer to Power Management for additional information.
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10.2.10
WAKE ON LAN (WOL)
The PHY supports layer 2 WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames.
Each type of supported wake event (Perfect DA, Broadcast, Magic Packet, or Wakeup frames) may be individually
enabled via Perfect DA Wakeup Enable (PFDA_EN), Broadcast Wakeup Enable (BCST_EN), Magic Packet Enable
(MPEN), and Wakeup Frame Enable (WUEN) bits of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x),
respectively. The WoL event is indicated via the INT8 bit of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
The WoL feature is part of the broader power management features of the device and can be used to trigger the power
management event output pin (PME) or the general interrupt request pin (IRQ). This is accomplished by enabling the
WoL feature of the PHY as described above, and setting the corresponding WoL enable (bit 14 for PHY A, bit 15 for
PHY B) of the Power Management Control Register (PMT_CTRL). Refer to Section 6.3, "Power Management," on
page 51 for additional information.
The PHY x Wakeup Control and Status Register (PHY_WUCSR_x) also provides a WoL Configured bit, which may be
set by software after all WoL registers are configured. Because all WoL related registers are not affected by software
resets, software can poll the WoL Configured bit to ensure all WoL registers are fully configured. This allows the software
to skip reprogramming of the WoL registers after reboot due to a WoL event.
The following subsections detail each type of WoL event. For additional information on the main system interrupts, refer
to Section 7.0, "System Interrupts," on page 60.
10.2.10.1
Perfect DA (Destination Address) Detection
When enabled, the Perfect DA detection mode allows the detection of a frame with the destination address matching
the address stored in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address
B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). The frame
must also pass the FCS and packet length check.
As an example, the Host system must perform the following steps to enable the device to detect a Perfect DA WoL
event:
1.
2.
3.
Set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address
C Register (PHY_RX_ADDRC_x).
Set the Perfect DA Wakeup Enable (PFDA_EN) bit of the PHY x Wakeup Control and Status Register
(PHY_WUCSR_x) to enable Perfect DA detection.
Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable
WoL events.
When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be
set, and the Perfect DA Frame Received (PFDA_FR) bit of the PHY x Wakeup Control and Status Register
(PHY_WUCSR_x) will be set.
10.2.10.2
Broadcast Detection
When enabled, the Broadcast detection mode allows the detection of a frame with the destination address value of FF
FF FF FF FF FF. The frame must also pass the FCS and packet length check.
As an example, the Host system must perform the following steps to enable the device to detect a Broadcast WoL event:
1.
2.
Set the Broadcast Wakeup Enable (BCST_EN) bit of the PHY x Wakeup Control and Status Register
(PHY_WUCSR_x) to enable Broadcast detection.
Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable
WoL events.
When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be
set, and the Broadcast Frame Received (BCAST_FR) bit of the PHY x Wakeup Control and Status Register
(PHY_WUCSR_x) will be set.
10.2.10.3
Magic Packet Detection
When enabled, the Magic Packet detection mode allows the detection of a Magic Packet frame. A Magic Packet is a
frame addressed to the device - either a unicast to the programmed address, or a broadcast - which contains the pattern
48’h FF_FF_FF_FF_FF_FF after the destination and source address field, followed by 16 repetitions of the desired MAC
address (loaded into the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address
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B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x)) without any
breaks or interruptions. In case of a break in the 16 address repetitions, the logic scans for the 48’h
FF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must
be preceded by the synchronization stream. The frame must also pass the FCS check and packet length checking.
As an example, if the desired address is 00h 11h 22h 33h 44h 55h, then the logic scans for the following data sequence
in an Ethernet frame:
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…FCS
As an example, the Host system must perform the following steps to enable the device to detect a Magic Packet WoL
event:
1.
2.
3.
Set the desired MAC address to cause the wake event in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and PHY x MAC Receive Address
C Register (PHY_RX_ADDRC_x).
Set the Magic Packet Enable (MPEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x)
to enable Magic Packet detection.
Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable
WoL events.
When a match is triggered, bit 8 of the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will be
set, and the Magic Packet Received (MPR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) will
be set.
10.2.10.4
Wakeup Frame Detection
When enabled, the Wakeup Frame detection mode allows the detection of a pre-programmed Wakeup Frame. Wakeup
Frame detection provides a way for system designers to detect a customized pattern within a packet via a programmable wake-up frame filter. The filter has a 128-bit byte mask that indicates which bytes of the frame should be compared
by the detection logic. A CRC-16 is calculated over these bytes. The result is then compared with the filter’s respective
CRC-16 to determine if a match exists. When a wake-up pattern is received, the Remote Wakeup Frame Received
(WUFR) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x) is set.
If enabled, the filter can also include a comparison between the frame’s destination address and the address specified
in the PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register
(PHY_RX_ADDRB_x), and PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x). The specified address can
be a unicast or a multicast. If address matching is enabled, only the programmed unicast or multicast address will be
considered a match. Non-specific multicast addresses and the broadcast address can be separately enabled. The
address matching results are logically OR’d (i.e., specific address match result OR any multicast result OR broadcast
result).
Whether or not the filter is enabled and whether the destination address is checked is determined by configuring the
PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x). Before enabling the filter, the application program
must provide the detection logic with the sample frame and corresponding byte mask. This information is provided by
writing the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x), PHY x Wakeup Filter Configuration
Register B (PHY_WUF_CFGB_x), and PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x). The starting
offset within the frame and the expected CRC-16 for the filter is determined by the Filter Pattern Offset and Filter CRC16 fields, respectively.
If remote wakeup mode is enabled, the remote wakeup function checks each frame against the filter and recognizes the
frame as a remote wakeup frame if it passes the filter’s address filtering and CRC value match.
The pattern offset defines the location of the first byte that should be checked in the frame. The byte mask is a 128-bit
field that specifies whether or not each of the 128 contiguous bytes within the frame, beginning with the pattern offset,
should be checked. If bit j in the byte mask is set, the detection logic checks the byte (pattern offset + j) in the frame,
otherwise byte (pattern offset + j) is ignored.
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At the completion of the CRC-16 checking process, the CRC-16 calculated using the pattern offset and byte mask is
compared to the expected CRC-16 value associated with the filter. If a match occurs, a remote wake-up event is signaled. The frame must also pass the FCS check and packet length checking.
Table 10-4 indicates the cases that produce a wake-up event. All other cases do not generate a wake-up event.
TABLE 10-4:
WAKEUP GENERATION CASES
Filter
Enabled
Frame
Type
CRC
Matches
Address
Match
Enabled
Any
Mcast
Enabled
Bcast
Enabled
Frame
Address
Matches
Yes
Unicast
Yes
No
X
X
X
Yes
Unicast
Yes
Yes
X
X
Yes
Yes
Multicast
Yes
X
Yes
X
X
Yes
Multicast
Yes
Yes
No
X
Yes
Yes
Broadcast
Yes
X
X
Yes
X
As an example, the Host system must perform the following steps to enable the device to detect a Wakeup Frame WoL
event:
Declare Pattern:
1.
2.
Update the PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x) to indicate the valid bytes to match.
Calculate the CRC-16 value of valid bytes offline and update the PHY x Wakeup Filter Configuration Register B
(PHY_WUF_CFGB_x). CRC-16 is calculated as follows:
At the start of a frame, CRC-16 is initialized with the value FFFFh. CRC-16 is updated when the pattern offset
and mask indicate the received byte is part of the checksum calculation. The following algorithm is used to update
the CRC-16 at that time:
Let:
^ denote the exclusive or operator.
Data [7:0] be the received data byte to be included in the checksum.
CRC[15:0] contain the calculated CRC-16 checksum.
F0 … F7 be intermediate results, calculated when a data byte is determined to be part of the CRC-16.
Calculate:
F0 = CRC[15] ^ Data[0]
F1 = CRC[14] ^ F0 ^ Data[1]
F2 = CRC[13] ^ F1 ^ Data[2]
F3 = CRC[12] ^ F2 ^ Data[3]
F4 = CRC[11] ^ F3 ^ Data[4]
F5 = CRC[10] ^ F4 ^ Data[5]
F6 = CRC[09] ^ F5 ^ Data[6]
F7 = CRC[08] ^ F6 ^ Data[7]
The CRC-32 is updated as follows:
CRC[15] = CRC[7] ^ F7
CRC[14] = CRC[6]
CRC[13] = CRC[5]
CRC[12] = CRC[4]
CRC[11] = CRC[3]
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CRC[10] = CRC[2]
CRC[9] = CRC[1] ^ F0
CRC[8] = CRC[0] ^ F1
CRC[7] = F0 ^ F2
CRC[6] = F1 ^ F3
CRC[5] = F2 ^ F4
CRC[4] = F3 ^ F5
CRC[3] = F4 ^ F6
CRC[2] = F5 ^ F7
CRC[1] = F6
CRC[0] = F7
3.
Determine the offset pattern with offset 0 being the first byte of the destination address. Update the offset in the
Filter Pattern Offset field of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x).
Determine Address Matching Conditions:
4.
5.
6.
Determine the address matching scheme based on Table 10-4 and update the Filter Broadcast Enable, Filter Any
Multicast Enable, and Address Match Enable bits of the PHY x Wakeup Filter Configuration Register A
(PHY_WUF_CFGA_x) accordingly.
If necessary (see step 4), set the desired MAC address to cause the wake event in the PHY x MAC Receive
Address A Register (PHY_RX_ADDRA_x), PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x), and
PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x).
Set the Filter Enable bit of the PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) to enable
the filter.
Enable Wakeup Frame Detection:
7.
8.
Set the Wakeup Frame Enable (WUEN) bit of the PHY x Wakeup Control and Status Register (PHY_WUCSR_x)
to enable Wakeup Frame detection.
Set bit 8 (WoL event indicator) in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) to enable
WoL events.
When a match is triggered, the Remote Wakeup Frame Received (WUFR) bit of the PHY x Wakeup Control and Status
Register (PHY_WUCSR_x) will be set. To provide additional visibility to software, the Filter Triggered bit of the PHY x
Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x) will be set.
10.2.11
RESETS
In addition to the chip-level hardware reset (RST#), EtherCAT system reset, and Power-On Reset (POR), the PHY supports three block specific resets. These are discussed in the following sections. For detailed information on all device
resets and the reset sequence refer to Section 6.2, "Resets," on page 46.
Note:
Only a hardware reset (RST#), Power-On Reset (POR) or EtherCAT system reset will automatically reload
the configuration strap values into the PHY registers.
The Digital Reset (DIGITAL_RST) bit in the Reset Control Register (RESET_CTL) does not reset the
PHYs.
For all other PHY resets, PHY registers will need to be manually configured via software.
10.2.11.1
PHY Software Reset via RESET_CTL
The PHYs can be reset via the Reset Control Register (RESET_CTL). These bits are self clearing after approximately
102 us. This reset does not reload the configuration strap values into the PHY registers.
10.2.11.2
PHY Software Reset via PHY_BASIC_CTRL_x
The PHY can also be reset by setting the Soft Reset (PHY_SRST) bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete. This reset does not reload the
configuration strap values into the PHY registers.
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10.2.11.3
PHY Power-Down Reset
After the PHY has returned from a power-down state, a reset of the PHY is automatically generated. The PHY powerdown modes do not reload or reset the PHY registers. Refer to Section 10.2.9, "PHY Power-Down Modes," on page 212
for additional information.
10.2.12
LINK INTEGRITY TEST
The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor state diagram. The
link status is multiplexed with the 10 Mbps link status to form the Link Status bit in the PHY x Basic Status Register
(PHY_BASIC_STATUS_x) and to drive the LINK LED functions.
The DSP indicates a valid MLT-3 waveform present on the RXPx and RXNx signals as defined by the ANSI X3.263 TPPMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is
asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When
received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time DATA_VALID is asserted
until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately
negate the Link signal and enter the Link-Down state.
10.2.13
CABLE DIAGNOSTICS
The PHYs provide cable diagnostics which allow for open/short and length detection of the Ethernet cable. The cable
diagnostics consist of two primary modes of operation:
• Time Domain Reflectometry (TDR) Cable Diagnostics
TDR cable diagnostics enable the detection of open or shorted cabling on the TX or RX pair, as well as cable
length estimation to the open/short fault.
• Matched Cable Diagnostics
Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables.
Refer to the following sub-sections for details on proper operation of each cable diagnostics mode.
Note:
10.2.13.1
Cable diagnostics are not used for 100BASE-FX mode.
Time Domain Reflectometry (TDR) Cable Diagnostics
The PHYs provide TDR cable diagnostics which enable the detection of open or shorted cabling on the TX or RX pair,
as well as cable length estimation to the open/short fault. To utilize the TDR cable diagnostics, Auto-MDIX and Auto
Negotiation must be disabled, and the PHY must be forced to 100 Mbps full-duplex mode. These actions must be performed before setting the TDR Enable bit in the PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x).
With Auto-MDIX disabled, the TDR will test the TX or RX pair selected by register bit 27.13 (Auto-MDIX State (AMDIXSTATE)). Proper cable testing should include a test of each pair. When TDR testing is complete, prior register settings
may be restored. Figure 10-5 provides a flow diagram of proper TDR usage.
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FIGURE 10-5:
TDR USAGE FLOW DIAGRAM
Start
Disable ANEG and Force 100Mb FullDuplex
Write PHY Reg 0: 0x2100
Disable AMDIX and Force MDI (or MDIX)
Write PHY Reg 27: 0x8000 (MDI)
- OR Write PHY Reg 27: 0xA000 (MDIX)
Enable TDR
Write PHY Reg 25: 0x8000
Check TDR Control/Status Register
Read PHY Reg 25
NO
Reg 25.8 == 0
TDR Channel Status Complete?
YES
Reg 25.8 == 1
Save:
TDR Channel Type (Reg 25.10:9)
TDR Channel Length (Reg 25.7:0)
Repeat Testing
in MDIX Mode
MDIX Case Tested?
YES
Done
The TDR operates by transmitting pulses on the selected twisted pair within the Ethernet cable (TX in MDI mode, RX
in MDIX mode). If the pair being tested is open or shorted, the resulting impedance discontinuity results in a reflected
signal that can be detected by the PHY. The PHY measures the time between the transmitted signal and received reflection and indicates the results in the TDR Channel Length field of the PHY x TDR Control/Status Register (PHY_TDR_CONTROL_STAT_x). The TDR Channel Length field indicates the “electrical” length of the cable, and can be multiplied
by the appropriate propagation constant in Table 10-5 to determine the approximate physical distance to the fault.
Note:
The TDR function is typically used when the link is inoperable. However, an active link will drop when operating the TDR.
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Since the TDR relies on the reflected signal of an improperly terminated cable, there are several factors that can affect
the accuracy of the physical length estimate. These include:
1.
2.
3.
4.
Cable Type (CAT 5, CAT5e, CAT6): The electrical length of each cable type is slightly different due to the twistsper-meter of the internal signal pairs and differences in signal propagation speeds. If the cable type is known, the
length estimate can be calculated more accurately by using the propagation constant appropriate for the cable
type (see Table 10-5). In many real-world applications the cable type is unknown, or may be a mix of different
cable types and lengths. In this case, use the propagation constant for the “unknown” cable type.
TX and RX Pair: For each cable type, the EIA standards specify different twist rates (twists-per-meter) for each
signal pair within the Ethernet cable. This results in different measurements for the RX and TX pair.
Actual Cable Length: The difference between the estimated cable length and actual cable length grows as the
physical cable length increases, with the most accurate results at less than approximately 100 m.
Open/Short Case: The Open and Shorted cases will return different TDR Channel Length values (electrical
lengths) for the same physical distance to the fault. Compensation for this is achieved by using different propagation constants to calculate the physical length of the cable.
For the Open case, the estimated distance to the fault can be calculated as follows:
Distance to Open fault in meters TDR Channel Length * POPEN
Where: POPEN is the propagation constant selected from Table 10-5
For the Shorted case, the estimated distance to the fault can be calculated as follows:
Distance to Open fault in meters TDR Channel Length * PSHORT
Where: PSHORT is the propagation constant selected from Table 10-5
TABLE 10-5:
TDR PROPAGATION CONSTANTS
TDR Propagation
Constant
Cable Type
Unknown
CAT 6
CAT 5E
CAT 5
POPEN
0.769
0.745
0.76
0.85
PSHORT
0.793
0.759
0.788
0.873
The typical cable length measurement margin of error for Open and Shorted cases is dependent on the selected cable
type and the distance of the open/short from the device. Table 10-6 and Table 10-7 detail the typical measurement error
for Open and Shorted cases, respectively.
TABLE 10-6:
TYPICAL MEASUREMENT ERROR FOR OPEN CABLE (+/- METERS)
Physical Distance
to Fault
Selected Propagation Constant
POPEN =
Unknown
POPEN =
CAT 6
CAT 6 Cable, 0-100 m
9
6
CAT 5E Cable, 0-100 m
5
CAT 5 Cable, 0-100 m
13
CAT 6 Cable, 101-160 m
14
CAT 5E Cable, 101-160 m
8
CAT 5 Cable, 101-160 m
20
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POPEN =
CAT 5E
POPEN =
CAT 5
5
3
6
6
6
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TABLE 10-7:
TYPICAL MEASUREMENT ERROR FOR SHORTED CABLE (+/- METERS)
SELECTED PROPAGATION CONSTANT
PHYSICAL DISTANCE
TO FAULT
10.2.13.2
PSHORT =
Unknown
PSHORT =
CAT 6
CAT 6 Cable, 0-100 m
8
5
CAT 5E Cable, 0-100 m
5
CAT 5 Cable, 0-100 m
11
CAT 6 Cable, 101-160 m
14
CAT 5E Cable, 101-160 m
7
CAT 5 Cable, 101-160 m
11
PSHORT =
CAT 5E
PSHORT =
CAT 5
5
2
6
6
3
Matched Cable Diagnostics
Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables of up to 120 meters. If there is an
active 100 Mb link, the approximate distance to the link partner can be estimated using the PHY x Cable Length Register
(PHY_CABLE_LEN_x). If the cable is properly terminated, but there is no active 100 Mb link (the link partner is disabled,
nonfunctional, the link is at 10 Mb, etc.), the cable length cannot be estimated and the PHY x Cable Length Register
(PHY_CABLE_LEN_x) should be ignored. The estimated distance to the link partner can be determined via the Cable
Length (CBLN) field of the PHY x Cable Length Register (PHY_CABLE_LEN_x) using the lookup table provided in
Table 10-8. The typical cable length measurement margin of error for a matched cable case is +/- 20 m. The matched
cable length margin of error is consistent for all cable types from 0 to 120 m.
TABLE 10-8:
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MATCH CASE ESTIMATED CABLE LENGTH (CBLN) LOOKUP
CBLN Field Value
Estimated Cable Length
0-3
0
4
6
5
17
6
27
7
38
8
49
9
59
10
70
11
81
12
91
13
102
14
113
15
123
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Note:
10.2.14
10.2.14.1
For a properly terminated cable (Match case), there is no reflected signal. In this case, the TDR Channel
Length field is invalid and should be ignored.
SIGNAL QUALITY INDEX
Background
MLT-3 modulation is used for data transmission in 100BASE-TX, with logical signal values of {-1, 0, +1}. These logic
levels correspond to maximum positive and negative DSP slicer reference levels. Positive and negative compare
thresholds are set between these maximums and zero, such that the analog received data samples may be quantized
to -1, 0 and +1.
Ideally, each receive data sample would be the maximum distance from the compare thresholds, with error values of 0.
But because of noise and imperfection in real applications, the sampled data may be off from its ideal. The closer to the
compare threshold, the worse the signal quality.
The slicer error is a measurement of how far the processed data off from its ideal location. The largest instantaneous
slicer error 100BASE-TX is +/-32.
A higher absolute slicer error means a degraded signal receiving condition.
Note:
The following register sequence must be issued to precondition PHYs A and B to enable the slicer error
into the Signal Quality Index logic.
// writing bit[10] of reg-20 from 1 -> 0 -> 1 will enable the testmode in PHY
Register PHY_TSTCNTL_A/B Data = 0x0400
Register PHY_TSTCNTL_A/B Data = 0x0000
Register PHY_TSTCNTL_A/B Data = 0x0400
// Maps err_nm1_real[5:0] to co_testbus_out[5:0] and rxclk125 to co_clk_out
Register PHY_TSTWRITE_A/B Data = 0x7200
// Enables the test bus outputs in PHY
Register PHY_TSTCNTL_A/B Data = 0x4401
10.2.14.2
Note:
OPEN Alliance TC1 DCQ Mean Square Error
All register referenced in this section are in MMD Device Address 30. Refer to Section 10.2.18, "PHY Registers" for additional information.
This section defines the implementation of section 6.1.1 of the TC1 specification. The PHY can provide detailed information of the dynamic signal quality by means of a MSE value. This mode is enabled by setting the sqi_enable bit, in
the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x).
With this method, the slicer error is converted into a squared value and then filtered by a programmable low pass filter.
This is similar to taking the average of absolute slicer error over a long moving time window.
For each data sample, the difference between the absolute slicer error and the current filtered value is added back into
the current filtered value.
The sqi_squ_mode_en bit in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) must be set to choose square
mode.
The sqi_kp field in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) sets the weighting of the add back as
a divide by 2^sqi_kp, effectively setting the filter bandwidth. As the sqi_kp value is increased, the weighing is decreased,
and the mean slicer error value takes a longer time to settle to a stable value. Also as the sqi_kp value is increased,
there will be less variation in the mean slicer error value reported.
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The scale611 field in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) is used to set a divide by factor (divide
by 2^scale611) such that the MSE value is linearly scaled to the range of 0 to 511. If the divide by factor is too small, the
MSE value is capped at a maximum of 511.
The filtered error value is saved every 65,536 symbols (524,288 ns).
In order to capture the MSE Value, the DCQ Read Capture bit in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) needs to be written as a high. The DCQ Read Capture bit will immediately self-clear and the result will be
available in the PHY x DCQ Mean Square Error Register (PHY_DCQ_MSE_x).
In addition to the current MSE Value the worst case MSE value since the last read of PHY x DCQ Mean Square Error
Register (PHY_DCQ_MSE_x) is stored in PHY x DCQ Mean Square Error Worst Case Register (PHY_DCQ_MSE_WC_x).
10.2.14.3
Note:
OPEN Alliance TC1 DCQ Signal Quality Index
All register referenced in this section are in MMD Device Address 30. Refer to Section 10.2.18, "PHY Registers" for additional information.
This section defines the implementation of section 6.1.2 of the TC1 specification.
This mode builds upon the above DCQ Mean Square Error method by mapping the MSE value onto a simple quality
index.
This mode is enabled by setting the sqi_enable bit, in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x).
Note:
As above, the sqi_squ_mode_en bit in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) must
be set to choose square mode.
As above, the scale611 field in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) is used to set
the divide by factor (divide by 2^scale611) such that the MSE value is linearly scaled to the range of 0 to 511.
The MSE value is compared to the thresholds set in the PHY x DCQ SQI Table Registers (PHY_DCQ_SQI_TBL_x) to
provide a Signal Quality Index value between 0 (worst value) and 7 (best value) as follows:
TABLE 10-9:
MSE TO SIGNAL QUALITY INDEX MAPPING
MSE Value
Greater Than
Less Than or Equal To
Signal Quality Index Value
SQI_TBL7.SQI_VALUE
7
SQI_TBL7.SQI_VALUE
SQI_TBL6.SQI_VALUE
6
SQI_TBL6.SQI_VALUE
SQI_TBL5.SQI_VALUE
5
SQI_TBL5.SQI_VALUE
SQI_TBL4.SQI_VALUE
4
SQI_TBL4.SQI_VALUE
SQI_TBL3.SQI_VALUE
3
SQI_TBL3.SQI_VALUE
SQI_TBL2.SQI_VALUE
2
SQI_TBL2.SQI_VALUE
SQI_TBL1.SQI_VALUE
1
SQI_TBL1.SQI_VALUE
0
In order to capture the SQI value, the DCQ Read Capture bit in the PHY x DCQ Configuration Register (PHY_DCQ_CFG_x) needs to be written as a high. The DCQ Read Capture bit will immediately self-clear and the result will be available
in the PHY x DCQ SQI Register (PHY_DCQ_SQI_x).
DS00003422A-page 222
2020 Microchip Technology Inc.
LAN9254
In addition to the current SQI the worst case (lowest) Signal Quality Index since the last read is available in the SQI
Worst Case field.
The correlation between the Signal Quality Index values stored in the PHY x DCQ SQI Register (PHY_DCQ_SQI_x)
and an according signal to noise ratio (SNR) based on AWG noise (bandwidth of 80MHz @ 100Mbps) is shown in
Table 10-10. The bit error rates to be expected in the case of white noise as interference signal is shown in the table as
well for information purposes.
A link loss only occurs if the Signal Quality Index value is 0.
TABLE 10-10: SIGNAL QUALITY INDEX VALUE CORRELATION
SQI Value
SNR Value @ MDI - AWG Noise
0
< 18 dB
1
18 dB
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