LAN9313/LAN9313i
Three Port 10/100 Managed Ethernet Switch with MII
Highlights
• High performance and full featured 3 port switch
with VLAN, QoS packet prioritization, Rate Limiting, IGMP monitoring and management functions
• Serial management via SPI/I2C or SMI
• Unique Virtual PHY feature simplifies software
development by mimicking the multiple switch
ports as a single port PHY
• Integrated IEEE 1588 Hardware Time Stamp Unit
Target Applications
•
•
•
•
•
•
•
Cable, satellite, and IP set-top boxes
Digital televisions
Digital video recorders
VoIP/Video phone systems
Home gateways
Test/Measurement equipment
Industrial automation systems
•
Key Benefits
• Ethernet Switch Fabric
- 32K buffer RAM
- 1K entry forwarding table
- Port based IEEE 802.1Q VLAN support (16
groups)
•
- Programmable IEEE 802.1Q tag insertion/removal
- IEEE 802.1d spanning tree protocol support
- QoS/CoS Packet prioritization
- 4 dynamic QoS queues per port
- Input priority determined by VLAN tag, DA lookup,
TOS, DIFFSERV or port default value
- Programmable class of service map based on input
priority
- Remapping of 802.1Q priority field on per port basis
- Programmable rate limiting at the ingress/egress
ports with random early discard, per port / priority
- IGMP v1/v2/v3 monitoring for Multicast
packet filtering
- Programmable filter by MAC address
• Switch Management
- Port mirroring/monitoring/sniffing: ingress
and/or egress traffic on any ports or port pairs
- Fully compliant statistics (MIB) gathering
counters
- Control registers configurable on-the-fly
• Ports
- 2 internal 10/100 PHYs with HP Auto-MDIX
support
- 1 MII - PHY mode or MAC mode
- Fully compliant with IEEE 802.3 standards
- 10BASE-T and 100BASE-TX support
2008-2016 Microchip Technology Inc.
•
•
•
- Full and half duplex support
- Full duplex flow control
- Backpressure (forced collision) half duplex
flow control
- Automatic flow control based on programmable levels
- Automatic 32-bit CRC generation and checking
- 2K Jumbo packet support
- Programmable interframe gap, flow control
pause value
- Full transmit/receive statistics
- Auto-negotiation
- Automatic MDI/MDI-X
- Loop-back mode
Serial Management
- SPI/I2C (slave) access to all internal registers
- MIIM (MDIO) access to PHY related registers
- SMI (extended MIIM) access to all internal
registers
IEEE 1588 Hardware Time Stamp Unit
- Global 64-bit tunable clock
- Master or slave mode per port
- Time stamp on TX or RX of Sync and
Delay_req packets per port, Timestamp on
GPIO
- 64-bit timer comparator event generation
(GPIO or IRQ)
Other Features
- General Purpose Timer
- Serial EEPROM interface (I2C master or
Microwire™ master) for non-managed configuration
- Programmable GPIOs/LEDs
Single 3.3V power supply
Available in Commercial & Industrial Temp.
Ranges
DS00002288A-page 1
LAN9313/LAN9313i
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00002288A-page 2
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LAN9313/LAN9313i
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 7
3.0 Pin Description and Configuration ................................................................................................................................................ 15
4.0 Clocking, Resets, and Power Management .................................................................................................................................. 30
5.0 System Interrupts .......................................................................................................................................................................... 41
6.0 Switch Fabric ................................................................................................................................................................................ 45
7.0 Ethernet PHYs .............................................................................................................................................................................. 68
8.0 Serial Management ....................................................................................................................................................................... 83
9.0 MII Management ......................................................................................................................................................................... 104
10.0 IEEE 1588 Hardware Time Stamp Unit .................................................................................................................................... 113
11.0 General Purpose Timer & Free-Running Clock ........................................................................................................................ 119
12.0 GPIO/LED Controller ................................................................................................................................................................ 120
13.0 Register Descriptions ................................................................................................................................................................ 124
14.0 Operational Characteristics ....................................................................................................................................................... 254
15.0 Package Outlines ...................................................................................................................................................................... 261
Appendix A: Data sheet Revision History ......................................................................................................................................... 264
The Microchip Web Site .................................................................................................................................................................... 266
Customer Change Notification Service ............................................................................................................................................. 266
Customer Support ............................................................................................................................................................................. 266
Product Identification System ........................................................................................................................................................... 267
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DS00002288A-page 3
LAN9313/LAN9313i
1.0
PREFACE
1.1
General Terms
100BT
100BASE-T (100Mbps Fast Ethernet, IEEE 802.3u)
ADC
Analog-to-Digital Converter
ALR
Address Logic Resolution
BLW
Baseline Wander
BM
Buffer Manager - Part of the switch fabric
BPDU
Bridge Protocol Data Unit - Messages which carry the Spanning Tree
Protocol information
Byte
8-bits
CSMA/CD
Carrier Sense Multiple Access / Collision Detect
CSR
Control and Status Registers
CTR
Counter
DA
Destination Address
DWORD
32-bits
EPC
EEPROM Controller
FCS
Frame Check Sequence - The extra checksum characters added to the end
of an Ethernet frame, used for error detection and correction.
FIFO
First In First Out buffer
FSM
Finite State Machine
GPIO
General Purpose I/O
Host
External system (Includes processor, application software, etc.)
IGMP
Internet Group Management Protocol
Inbound
Refers to data input to the LAN9313/LAN9313i from the host
Level-Triggered Sticky Bit
This type of status bit is set whenever the condition that it represents is
asserted. The bit remains set until the condition is no longer true, and the
status bit is cleared by writing a zero.
lsb
Least Significant Bit
LSB
Least Significant Byte
MDI
Medium Dependant Interface
MDIX
Media Independent Interface with Crossover
MII
Media Independent Interface
MIIM
Media Independent Interface Management
MIL
MAC Interface Layer
MLT-3
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method
where a change in the logic level represents a code bit “1” and the logic
output remaining at the same level represents a code bit “0”.
msb
Most Significant Bit
MSB
Most Significant Byte
NRZI
Non Return to Zero Inverted. This encoding method inverts the signal for a
“1” and leaves the signal unchanged for a “0”
N/A
Not Applicable
NC
No Connect
OUI
Organizationally Unique Identifier
Outbound
Refers to data output from the LAN9313/LAN9313i to the host
PIO cycle
Program I/O cycle. An SRAM-like read or write cycle on the HBI.
PISO
Parallel In Serial Out
DS00002288A-page 4
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
PLL
Phase Locked Loop
PTP
Precision Time Protocol
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not guaranteed when reading reserved bits. Unless otherwise noted, do
not read or write to reserved addresses.
RTC
Real-Time Clock
SA
Source Address
SFD
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble
of an Ethernet frame.
SIPO
Serial In Parallel Out
SMI
Serial Management Interface
SQE
Signal Quality Error (also known as “heartbeat”)
SSD
Start of Stream Delimiter
UDP
User Datagram Protocol - A connectionless protocol run on top of IP
networks
UUID
Universally Unique IDentifier
WORD
16-bits
1.2
Buffer Types
Table 1-1 describes the pin buffer type notation used in Section 3.0, "Pin Description and Configuration," on page 15
and throughout this document.
TABLE 1-1:
BUFFER TYPES
Buffer Type
Description
IS
Schmitt-triggered Input
O8
Output with 8mA sink and 8mA source
OD8
Open-drain output with 8mA sink
O12
Output with 12mA sink and 12mA source
OD12
PU
Open-drain output with 12mA sink
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Note:
PD
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the LAN9313/LAN9313i. When
connected to a load that must be pulled high, an external resistor must be added.
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pulldowns are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the LAN9313/LAN9313i. When
connected to a load that must be pulled low, an external resistor must be added.
AI
Analog input
AO
Analog output
AIO
Analog bi-directional
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
P
Power pin
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DS00002288A-page 5
LAN9313/LAN9313i
1.3
Register Nomenclature
Table 1-2 describes the register bit attribute notation used throughout this document.
TABLE 1-2:
REGISTER BIT TYPES
Register Bit Type Notation
Register Bit Description
R
Read: A register or bit with this attribute can be read.
W
Read: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
WO
Write only: If a register or bit is write-only, reads will return unspecified data.
WC
WAC
Write One to Clear: writing a one clears the value. Writing a zero has no effect
Write Anything to Clear: writing anything clears the value.
RC
Read to Clear: Contents is cleared after the read. Writes have no effect.
LL
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
SS
Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
RO/LH
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After
it is read, the bit will either remain high if the high condition remains, or will go low if
the high condition has been removed. If the bit has not been read, the bit will remain
high regardless of a change to the high condition. This mode is used in some Ethernet
PHY registers.
NASR
Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros to ensure future
compatibility. The value of reserved bits is not guaranteed on a read.
Many of these register bit notations can be combined. Some examples of this are shown below:
• R/W: Can be written. Will return current setting on a read.
• R/WAC: Will return current setting on a read. Writing anything clears the bit.
DS00002288A-page 6
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LAN9313/LAN9313i
2.0
INTRODUCTION
2.1
General Description
The LAN9313/LAN9313i is a full featured, 3 port 10/100 managed Ethernet switch designed for embedded applications
where performance, flexibility, ease of integration and system cost control are required. The LAN9313/LAN9313i combines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media
access controllers (MACs), PHY transceivers, and serial management. The LAN9313/LAN9313i complies with the IEEE
802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol specification and 802.1D/802.1Q network management protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications.
At the core of the LAN9313/LAN9313i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch
fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames.
The switch fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple
packets while forwarding operations are completed, and a 1K entry forwarding table provides ample room for MAC
address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to
grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the buffer
manager block within the switch fabric. All aspects of the switch fabric are managed via the switch fabric configuration
and status registers, which are indirectly accessible via the system control and status registers.
The LAN9313/LAN9313i provides 3 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all
internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9313/LAN9313i provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the third MAC are used to connect the
LAN9313/LAN9313i switch fabric to an external MAC or PHY. All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control. 2K jumbo packet (2048 byte) support allows for oversized
packet transfers, effectively increasing throughput while deceasing CPU load. All MAC and PHY related settings are
fully configurable via their respective registers within the LAN9313/LAN9313i.
The integrated SPI, I2C and SMI slave controllers allow for full serial management of the LAN9313/LAN9313i via the
integrated SPI/I2C serial interface or MII interface respectively. The inclusion of these interfaces allows for greater flexibility in the incorporation of the LAN9313/LAN9313i into various designs. It is this flexibility which allows the
LAN9313/LAN9313i to operate in 2 different modes and under various management conditions. In MAC mode, the
LAN9313/LAN9313i can be connected to an external PHY via the MII interface. In PHY mode, the LAN9313/LAN9313i
can be connected to an external MAC via the MII interface. In both MAC and PHY modes, the LAN9313/LAN9313i can
be unmanaged, SMI managed, I2C managed or SPI managed. This flexibility in management makes the
LAN9313/LAN9313i a candidate for virtually all switch applications.
The LAN9313/LAN9313i contains an I2C/Microwire master EEPROM controller for connection to an optional EEPROM.
This allows for the storage and retrieval of static data. The internal EEPROM Loader can be optionally configured to
automatically load stored configuration settings from the EEPROM into the LAN9313/LAN9313i at reset, allowing the
LAN9313/LAN9313i to operate unmanaged.
In addition to the primary functionality described above, the LAN9313/LAN9313i provides additional features designed
for extended functionality. These include a configurable 16-bit General Purpose Timer (GPT), a 32-bit 25MHz free running counter, a 12-bit configurable GPIO/LED interface, and IEEE 1588 time stamping on all ports and select GPIOs.
The IEEE time stamp unit provides a 64-bit tunable clock for accurate PTP timing and a timer comparator to allow time
based interrupt generation.
The LAN9313/LAN9313i’s performance, features and small size make it an ideal solution for many applications in the
consumer electronics and industrial automation markets. Targeted applications include: set top boxes (cable, satellite
and IP), digital televisions, digital video recorders, voice over IP and video phone systems, home gateways, and test
and measurement equipment.
2008-2016 Microchip Technology Inc.
DS00002288A-page 7
Block Diagram
FIGURE 2-1:
INTERNAL LAN9313/LAN9313I BLOCK DIAGRAM
IEEE 1588
Time Stamp
Virtual PHY
Registers
MDIO
10/100
MAC
10/100
MAC
Port 0
10/100
PHY
Port 1
To Ethernet
Dynamic
QoS
4 Queues
Dynamic
QoS
4 Queues
MII
IEEE 1588
Time Stamp
Switch Engine
Buffer Manager
Frame
Buffers
Port 2
10/100
PHY
MDIO
10/100
MAC
Dynamic
QoS
4 Queues
MII
To Ethernet
SMI (slave)
Controller
Switch
Registers
(CSRs)
IEEE 1588
Time Stamp
Clock/Events
Register
Access
MUX
System
Registers
(CSRs)
Switch Fabric
GPIO/LED
Controller
System
Interrupt
Controller
System
Clocks/
Reset/PME
Controller
LAN9313/LAN9313i
2008-2016 Microchip Technology Inc.
To optional GPIOs/LEDs
IRQ
PHY Management
Interface (PMI)
IEEE 1588
Time Stamp
Registers
MDIO
MII
Registers
Search
Engine
MDIO
External
25MHz Crystal
GP Timer
Free-Run
Clk
SPI (slave)
I2C (slave)
Controller
MII
Mode
MUX
MDIO
MII
To optional PHY, MAC,
or SMI Master
Management Mode
Configuration Straps
MDIO
SPI/I2C
To optional CPU
serial management
(via I2C/SPI slave)
EEPROM Loader
EEPROM Controller
I2C (master)
Microwire (master)
I2C/Microwire
To optional EEPROM
(via I2C/Microwire master)
LAN9313/LAN9313i
DS00002288A-page 8
2.2
LAN9313/LAN9313i
2.2.1
SYSTEM CLOCKS/RESET/PME CONTROLLER
A clock module contained within the LAN9313/LAN9313i generates all the system clocks required by the device. This
module interfaces directly with the external 25MHz crystal/oscillator to generate the required clock divisions for each
internal module, with the exception of the 1588 clocks, which are generated in the 1588 Time Stamp Clock/Events module. A 16-bit general purpose timer and 32-bit free-running clock are provided by this module for general purpose use.
The Port 1 & 2 PHYs provide general power-down and energy detect power-down modes, which allow a reduction in
PHY power consumption.
The LAN9313/LAN9313i reset events are categorized as chip-level resets, multi-module resets, and single-module
resets.
A chip-level reset is initiated by assertion of any of the following input events:
• Power-On Reset
• nRST Pin Reset
A multi-module reset is initiated by assertion of the following:
• Digital Reset - DIGITAL_RST (bit 0) in the Reset Control Register (RESET_CTL)
- Resets all LAN9313/LAN9313i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual
PHY)
A single-module reset is initiated by assertion of the following:
• Port 2 PHY Reset - PHY2_RST (bit 2) in the Reset Control Register (RESET_CTL) or Reset (bit 15) in the Port x
PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- Resets the Port 2 PHY
• Port 1 PHY Reset - PHY1_RST (bit 1) in the Reset Control Register (RESET_CTL) or Reset (bit 15) in the Port x
PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- Resets the Port 1 PHY
• Virtual PHY Reset - VPHY_RST (bit 0) in the Reset Control Register (RESET_CTL) or Reset (bit 15) in the Virtual
PHY Basic Control Register (VPHY_BASIC_CTRL)
- Resets the Virtual PHY
2.2.2
SYSTEM INTERRUPT CONTROLLER
The LAN9313/LAN9313i provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. At the top level are the Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN).
These registers aggregate and control all interrupts from the various LAN9313/LAN9313i sub-modules. The
LAN9313/LAN9313i is capable of generating interrupt events from the following:
•
•
•
•
•
•
1588 Time Stamp
Switch Fabric
Ethernet PHYs
GPIOs
General Purpose Timer
Software (general purpose)
A dedicated programmable IRQ interrupt output pin is provided for external indication of any LAN9313/LAN9313i interrupts. The IRQ pin is controlled via the Interrupt Configuration Register (IRQ_CFG), which allows configuration of the
IRQ buffer type, polarity, and de-assertion interval.
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DS00002288A-page 9
LAN9313/LAN9313i
2.2.3
SWITCH FABRIC
The Switch Fabric consists of the following major function blocks:
• 10/100 MACs
There is one 10/100 Ethernet MAC per switch fabric port, which provides basic 10/100 Ethernet functionality,
including transmission deferral, collision back-off/retry, TX/RX FCS checking/generation, TX/RX pause flow control, and transmit back pressure. The 10/100 MACs act as an interface between the switch engine and the 10/100
PHYs (for ports 1 and 2). The port 0 10/100 MAC interfaces the switch engine to the external MAC/PHY (see Section 2.3, "Modes of Operation"). Each 10/100 MAC includes RX and TX FIFOs and per port statistic counters.
• Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all forwarding/filtering
rules and supports untagged, VLAN tagged, and priority tagged frames. The switch engine provides an extensive
feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS)
packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a
range of prioritization implementations. A 1K entry forwarding table provides ample room for MAC address forwarding tables.
• Buffer Manager
This block controls the free buffer space, multi-level transmit queues, transmission scheduling, and packet dropping of the switch fabric. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations
are completed. Each port is allocated 1a cluster of 4 dynamic QoS queues which allow each queue size to grow
and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buffer Manager block.
• Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the switch fabric to be
managed. These registers are indirectly accessible via the system control and status registers
2.2.4
ETHERNET PHYS
The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are
identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their
respective port. These PHYs interface with their respective MAC via an internal MII interface. The Virtual PHY provides
the virtual functionality of a PHY and allows connection of an external MAC to port 0 of the switch fabric as if it was
connected to a single port PHY. All PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can
be configured for full/half duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers
follow the IEEE 802.3 (clause 22.2.4) specified MII management register set.
2.2.5
PHY MANAGEMENT INTERFACE (PMI)
The PHY Management Interface (PMI) is used to serially access the internal PHYs as well as the external PHY on the
MII pins (in MAC mode only, see Section 2.3, "Modes of Operation"). The PMI implements the IEEE 802.3 management
protocol, providing read/write commands for PHY configuration.
2.2.6
SPI/I2C SLAVE CONTROLLER
This module provides an SPI/I2C slave interface which can be used for CPU serial management of the
LAN9313/LAN9313i.
The SPI slave controller allows CPU access to all system CSRs for configuration and management. The SPI slave controller supports single register and multiple register read and write commands. Multiple read and multiple write commands support incrementing, decrementing, and static addressing.
The I2C slave controller implements the low level I2C slave serial interface (start and stop condition detection, data bit
transmission/reception, and acknowledge generation/reception), handles the slave command protocol, and performs
system register reads and writes. The I2C slave controller conforms to the Philips I2C-Bus Specification.
A list of management modes and configurations settings for these modes is discussed in Section 2.3, "Modes of Operation"
DS00002288A-page 10
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LAN9313/LAN9313i
2.2.7
SMI SLAVE CONTROLLER
This module provides a SMI slave interface which can be used for CPU management of the LAN9313/LAN9313i via the
MII pins, and allows CPU access to all system CSRs. SMI uses the same pins and protocol of the IEEE MII management
function, and differs only in that SMI provides access to all internal registers by using a non-standard extended addressing map. The SMI protocol co-exists with the MII management protocol by using the upper half of the PHY address
space (16 through 31).
A list of management modes and configurations settings for these modes is discussed in Section 2.3, "Modes of Operation"
2.2.8
EEPROM CONTROLLER/LOADER
The EEPROM Controller is an I2C/Microwire master module which interfaces an optional external EEPROM with the
system register bus and the EEPROM Loader. Multiple types (I2C/Microwire) and sizes of external EEPROMs are supported. Configuration of the EEPROM type and size are accomplished via the eeprom_type_strap and eeprom_size_strap[1:0] configuration straps respectively. Various commands are supported for each EEPROM type, allowing for
the storage and retrieval of static data. The I2C interface conforms to the Philips I2C-Bus Specification.
The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs. The
EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the
LAN9313/LAN9313i at reset, allowing the LAN9313/LAN9313i to operate unmanaged. The EEPROM Loader runs upon
a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the Reset Control Register (RESET_CTL)),
or upon the issuance of a RELOAD command via the EEPROM Command Register (E2P_CMD).
2.2.9
1588 TIME STAMP
The IEEE 1588 Time Stamp modules provide hardware support for the IEEE 1588 Precision Time Protocol (PTP), allowing clock synchronization with remote Ethernet devices, packet time stamping, and time driven event generation. Time
stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII
bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9313/LAN9313i
as a whole may function as a boundary clock.
A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related functions. The
IEEE 1588 Clock/Events block provides IEEE 1588 clock comparison based interrupt generation and time stamp related
GPIO event generation. Two LAN9313/LAN9313i GPIO pins (GPIO[8:9]) can be used to trigger a time stamp capture
when configured as an input, or output a signal from the GPIO based on an IEEE 1588 clock target compare event when
configured as an output. All features of the IEEE 1588 hardware time stamp unit can be monitored and configured via
their respective IEEE 1588 configuration and status registers (CSRs).
2.2.10
GPIO/LED CONTROLLER
The LAN9313/LAN9313i provides 12 configurable general-purpose input/output pins which are controlled via this module. These pins can be individually configured via the GPIO/LED CSRs to function as inputs, push-pull outputs, or open
drain outputs and each is capable of interrupt generation with configurable polarity. Two of the GPIO pins (GPIO[9:8])
can be used for IEEE 1588 timestamp functions, allowing GPIO driven 1588 time clock capture when configured as an
input, or GPIO output generation based on an IEEE 1588 clock target compare event.
In addition, 8 of the GPIO pins can be alternatively configured as LED outputs. These pins, GPIO[7:0] (nP1LED[3:0] and
nP2LED[3:0]), may be enabled to drive Ethernet status LEDs for external indication of various attributes of the switch
ports.
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DS00002288A-page 11
LAN9313/LAN9313i
2.3
Modes of Operation
The LAN9313/LAN9313i is designed to integrate into various embedded environments. To accomplish compatibility with
a wide range of applications, the LAN9313/LAN9313i can operate in 2 different modes (MAC mode and PHY mode) and
under various management conditions (unmanaged, SMI managed, I2C managed, or SPI managed). The mode and
management type of the LAN9313/LAN9313i is determined by the MII_mode_strap and mngt_mode_strap[1:0] configuration straps respectively. These modes and management types are detailed in the following sections. Figure 2-2 displays a typical system configuration for each mode and management type supported by the LAN9313/LAN9313i.
2.3.1
MAC MODE
The LAN9313/LAN9313i MAC mode utilizes an external PHY, which is connected to the MII pins, to provide a third
Ethernet network connection. In this mode, the LAN9313/LAN9313i acts as a MAC, providing a communication path
between the switch fabric and the external PHY. In MAC mode, the LAN9313/LAN9313i may be unmanaged, SMI managed, I2C managed, or SPI managed as detailed in Section 2.3.3, "Management Modes".
When an EEPROM is connected, the EEPROM loader can be used to load the initial device configuration from the external EEPROM via the I2C/Microwire interface. Once operational, if managed, the CPU can use the I2C/Microwire interface to read or write the EEPROM.
2.3.2
PHY MODE
The LAN9313/LAN9313i PHY mode utilizes an external MAC to provide a network path for the host CPU. The external
MII pins of the LAN9313/LAN9313i must be connected to an external MAC, providing a communication path to the
switch fabric. In PHY mode, the LAN9313/LAN9313i may be unmanaged, SMI managed, I2C managed, or SPI managed as detailed in Section 2.3.3, "Management Modes".
When an EEPROM is connected, the EEPROM loader can be used to load the initial device configuration from the external EEPROM via the I2C/Microwire interface. Once operational, if managed, the CPU can use the I2C/Microwire interface to read or write the EEPROM.
2.3.3
MANAGEMENT MODES
The LAN9313/LAN9313i provides various modes of management in both MAC and PHY modes of operation. Two separate interfaces may be used to manage the LAN9313/LAN9313i: the I2C/SPI slave interface or the SMI/MIIM(Media
Independent Interface Management) slave interface.
The I2C/SPI interface runs as either an I2C slave or SPI slave and is used as a register access path for an external CPU.
The SMI/MIIM interface runs as either an SMI/MIIM slave or MIIM master. The master mode is used to access an external PHYs registers under CPU control (assuming the CPU is using I2C or SPI). The slave mode is used for register
access by the CPU or external MAC and provides access to either the internal Port 1&2 PHY registers or to all non-PHY
registers (using addresses 16-31 and a non-standard extended address map). MIIM and SMI use the same pins and
protocol and differ only in that SMI provides access to all internal registers while MIIM provides access to only the Port
1&2 PHY registers. A special mode provides access to the Virtual PHY, which mimics the register operation of a single
port standalone PHY. This is used for software compatibility during unmanaged operation.
The selection of LAN9313/LAN9313i modes is determined at startup via the MII_mode_strap and mngt_mode_strap[1:0] configuration straps as detailed in Table 2-1. System configuration diagrams for each mode of the
LAN9313/LAN9313i are provided in Figure 2-2.
DS00002288A-page 12
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 2-1:
LAN9313/LAN9313I MODES
I2C/Microwire
EEPROM Interface
I2C/SPI Slave
Interface
SMI/MIIM Interface
MII_mode_
strap Value
MNGT_MODE_S
TRAP[1:0] Value
MAC Mode
Unmanaged
Used to load initial
configuration from
EEPROM
Not used
Not used
0
00
MAC Mode
SMI Managed
Used to load initial
configuration from
EEPROM and for
CPU R/W access to
EEPROM
Not used
SMI/MIIM slave, used
for CPU access to
internal PHYs and
non-PHY registers
0
01
MAC Mode
I2C Managed
Used to load initial
configuration from
EEPROM and for
CPU R/W access to
EEPROM
I2C slave
MIIM master,
used for CPU access
to external PHY
registers
0
10
MAC Mode
SPI Managed
Used to load initial
configuration from
EEPROM and for
CPU R/W access to
EEPROM
SPI slave
MIIM master,
used for CPU access
to external PHY
registers
0
11
PHY Mode
Unmanaged
Used to load initial
configuration from
EEPROM
Not used
Virtual MIIM slave,
used for external
MAC access to
Virtual PHY registers
1
00
PHY Mode
SMI Managed
Used to load initial
configuration from
EEPROM and for
CPU R/W access to
EEPROM
Not used
SMI/MIIM slave, used
for CPU access to
internal PHYs, Virtual
PHY, and non-PHY
registers
1
01
PHY Mode
Managed
Used to load initial
configuration from
EEPROM and for
CPU R/W access to
EEPROM
I2C slave
Virtual MIIM slave,
used for external
MAC access to
Virtual PHY registers
1
10
PHY Mode
SPI Managed
Used to load initial
configuration from
EEPROM and for
CPU R/W access to
EEPROM
SPI slave
Virtual MIIM slave,
used for external
MAC access to
Virtual PHY registers
1
11
Mode
I2C
2008-2016 Microchip Technology Inc.
DS00002288A-page 13
LAN9313/LAN9313i
FIGURE 2-2:
SYSTEM BLOCK DIAGRAMS - MAC/PHY MODES OF OPERATION
LAN9313/LAN9313i MAC Modes
Unmanaged
SMI Managed
LAN9313
To Ethernet
Magnetics
EEPROM
I2C/Microwire
To Ethernet
LAN9313
To Ethernet
I2C/
Microwire
Magnetics
EEPROM
(optional)
EEPROM
I2C/Microwire
To Ethernet
Magnetics
Magnetics
MII
Magnetics
To Ethernet
10/100
PHY
Magnetics
I2C Managed
LAN9313
To Ethernet
Magnetics
EEPROM
I C/Microwire
SMI/MIIM
I2C/SPI slave
Magnetics
I2C/
Microwire
Magnetics
I2C
EEPROM
I C/Microwire
Magnetics
10/100
PHY
I2C/
Microwire
2
To Ethernet
MII
EEPROM
(optional)
SPI
I2C/SPI slave
Magnetics
MIIM
To Ethernet
Microprocessor/
Microcontroller
LAN9313
To Ethernet
EEPROM
(optional)
MIIM/
SMI
MII
10/100
PHY
SPI Managed
2
To Ethernet
EEPROM
(optional)
MIIM/
SMI
MII
MIIM
To Ethernet
I2C/
Microwire
MIIM/
SMI
MIIM
Microprocessor/
Microcontroller
To Ethernet
Magnetics
10/100
PHY
Microprocessor/
Microcontroller
LAN9313/LAN9313i PHY Modes
Unmanaged
SMI Managed
LAN9313
To Ethernet
Magnetics
EEPROM
I2C/Microwire
To Ethernet
Magnetics
MII
LAN9313
To Ethernet
I2C/
Microwire
Magnetics
EEPROM
(optional)
EEPROM
I2C/Microwire
To Ethernet
Magnetics
MIIM/
SMI
MII
SMI/MIIM
10/100
MAC
10/100
MAC
I2C Managed
LAN9313
Magnetics
EEPROM
I2C/Microwire
I2C/SPI slave
Magnetics
MII
I2C/
Microwire
IC
Magnetics
EEPROM
I2C/Microwire
To Ethernet
I2C/SPI slave
Magnetics
MII
MIIM
DS00002288A-page 14
LAN9313
To Ethernet
EEPROM
(optional)
MIIM/
SMI
10/100
MAC
Microprocessor/
Microcontroller
SPI Managed
2
To Ethernet
EEPROM
(optional)
MIIM/
SMI
MIIM
To Ethernet
I2C/
Microwire
I2C/
Microwire
EEPROM
(optional)
SPI
MIIM/
SMI
MIIM
Microprocessor/
Microcontroller
10/100
MAC
Microprocessor/
Microcontroller
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
3.0
PIN DESCRIPTION AND CONFIGURATION
3.1
Pin Diagrams
3.1.1
128-VTQFP PIN DIAGRAM
EEDI/EE_SDA
PHY_ADDR_SEL
NC
VDD3 3IO
nP1LED0/GPIO0
nP1LED1/GPIO1
nP1LED2/GPIO2
nP1LED3/GPIO3
VDD1 8CORE
VDD3 3IO
nP2LED0/GPIO4
nP2LED1/GPIO5
nP2LED2/GPIO6
nP2LED3/GPIO7
GPIO8
VDD3 3IO
VSS
GPIO9
GPIO10
GPIO11
NC
TEST1
VDD1 8CORE
VDD3 3IO
VDD3 3IO
nRS T
SCK/S CL
nSCS
SO
SI /SDA
VDD3 3IO
VDD1 8CORE
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LAN9313 128-VTQFP PIN ASSIGNMENTS (TOP VIEW)
96
FIGURE 3-1:
VSS
97
64
VDD33IO
EEDO/EEPROM_TYPE
98
63
IRQ
EECLK/EE_SCL/
EEPROM_SIZE_1
99
62
TXER
61
RXD0
60
MII _DUPLEX
59
NC
VDD33IO
100
EECS/EEPROM_SIZE_0
101
NC
102
NC
103
VDD18CORE
LAN9313
128-VTQFP
58
NC
104
57
NC
TOP VIEW
127
34
SPEED_MII
VSS
128
33
VDD33IO
32
MANUAL _FC_2
TXN2
DUPLEX_POL_MII
35
31
126
BP_EN_MII
FD_FC_2
TXP2
30
36
FD_FC_MII
125
29
BP _EN_2
VDD33A2
MANUAL_FC_MII
37
28
124
MNGT_MODE 0
DUPLEX _2
RXN2
27
38
VDD33IO
123
26
VDD33IO
RXP2
MNGT_MODE 1
39
25
122
MII_MODE
VDD18CORE
VDD33A2
24
40
TXCLK
121
23
SPEED_2
VDD18TX2
TXD0
41
22
120
TXD1
AUTO _NEG_ 2
VDD33BIAS
21
42
VDD33IO
119
20
AUTO _MDIX _2
EXRES
TXD2
43
19
118
TXD3
LED_ EN
VDD18TX1
18
44
VSS
117
17
LED_ FUN1
VDD33A1
COL
45
16
116
CRS
VDD33IO
RXP1
15
46
MDC
115
14
LED_ FUN0
RXN1
VDD18CORE
47
13
114
VDD33IO
VSS
VDD33A1
12
48
MDIO
113
11
MANUAL _FC_1
VSS
RXDV
49
10
112
RXCLK
FD_FC_1
VSS
9
50
RXER
111
8
BP _EN_1
TXP1
RXD3
51
7
110
VDD33IO
DUPLEX _1
TXN1
6
52
RXD2
109
5
SPEED_1
NC
RXD1
VDD33IO
53
4
54
108
TXEN
107
TEST2
3
VDD18PLL
VDD18CORE
AUTO _NEG_ 1
2
AUTO _MDIX _1
55
1
56
106
NC
105
NC
XI
XO
2008-2016 Microchip Technology Inc.
DS00002288A-page 15
LAN9313/LAN9313i
3.1.2
128-XVTQFP PIN DIAGRAM
EEDI/EE_SDA
PHY_ADDR_SEL
NC
VDD33IO
nP1LED0/GPIO0
nP1LED1/GPIO1
nP1LED2/GPIO2
nP1LED3/GPIO3
VDD18CORE
VDD33IO
nP2LED0/GPIO4
nP2LED1/GPIO5
nP2LED2/GPIO6
nP2LED3/GPIO7
GPIO8
VDD33IO
VSS
GPIO9
GPIO10
GPIO11
NC
TEST1
VDD18CORE
VDD33IO
VDD33IO
nRST
SCK/SCL
nSCS
SO
SI/SDA
VDD33IO
VDD18CORE
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LAN9313/LAN9313I 128-XVTQFP PIN ASSIGNMENTS (TOP VIEW)
96
FIGURE 3-2:
VSS
97
64
VDD33IO
EEDO/EEPROM_TYPE
98
63
IRQ
EECLK/EE_SCL/
EEPROM_SIZE_1
99
62
TXER
LAN9313/LAN9313i
128-XVTQFP
61
RXD0
60
MII _DUPLEX
59
NC
TOP VIEW
58
NC
VDD33 IO
100
EECS/EEPROM_SIZE_0
101
NC
102
NC
103
VDD18CORE
104
57
NC
XI
105
56
AUTO_MDIX _1
XO
106
55
AUTO_NEG _1
VDD18PLL
107
54
VDD33IO
TEST2
108
53
SPEED_1
NC
109
52
DUPLEX_1
TXN1
110
51
BP _EN_1
TXP1
111
50
FD_FC_1
VSS
112
49
MANUAL _FC_1
VSS
113
48
VSS
VDD33A1
114
47
LED_FUN0
RXN1
115
46
VDD33IO
RXP1
116
45
LED_FUN1
VDD33A1
117
44
LED_EN
VDD18TX1
118
43
AUTO_MDIX _2
EXRES
119
42
AUTO_NEG _2
VDD33BIAS
120
41
SPEED_2
VDD18TX2
121
40
VDD18CORE
VDD33A2
122
39
VDD33IO
RXP2
123
38
DUPLEX_2
RXN2
124
37
BP _EN_2
VDD33A2
125
36
FD_FC_2
TXP2
126
35
MANUAL _FC_2
TXN2
127
34
SPEED_MII
VSS
128
33
VDD33IO
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD33IO
VDD18CORE
MDC
CRS
COL
VSS
TXD3
TXD2
VDD33IO
TXD1
TXD0
TXCLK
MII_MODE
MNGT_MODE1
VDD33IO
MNGT_MODE0
MANUAL_FC_MII
FD_FC_MII
BP_EN_MII
DUPLEX_POL_MII
8
RXD3
MDIO
7
VDD33IO
11
6
RXD2
RXDV
5
RXD1
10
4
TXEN
RXCLK
3
VDD18CORE
9
2
NC
RXER
1
NC
VSS
NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND
DS00002288A-page 16
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
3.2
Pin Descriptions
This section contains the descriptions of the LAN9313/LAN9313i pins. The pin descriptions have been broken into functional groups as follows:
•
•
•
•
•
•
•
•
•
•
•
LAN Port 1 Pins
LAN Port 2 Pins
LAN Port 1 & 2 Power and Common Pins
LAN Port 0(External MII) Pins
Dedicated Configuration Strap Pins
EEPROM Pins
Serial Management Pins
Miscellaneous Pins
PLL Pins
Core and I/O Power and Ground Pins
No-Connect Pins
Note:
A list of buffer type definitions is provided in Section 1.2, "Buffer Types," on page 5.
TABLE 3-1:
Pin
89-92
LAN PORT 1 PINS
Name
Symbol
Buffer
Type
Port 1 LED
Indicators
nP1LED[3:0]
OD12
General
Purpose I/O
Data
GPIO[3:0]
Description
LED Indicators: When configured as LED outputs
via the LED Configuration Register (LED_CFG),
these pins are open-drain, active low outputs and the
pull-ups and input buffers are disabled. The
functionality of each pin is determined via the
LED_CFG[9:8] bits.
IS/O12/O General Purpose I/O Data: When configured as
GPIO via the LED Configuration Register
D12
(LED_CFG), these general purpose signals are fully
(PU)
programmable as either push-pull outputs, opendrain outputs or Schmitt-triggered inputs by writing
the General Purpose I/O Configuration Register
(GPIO_CFG) and General Purpose I/O Data &
Direction Register (GPIO_DATA_DIR). The pull-ups
are enabled in GPIO mode. The input buffers are
disabled when set as an output.
Note:
See Section 12.0, "GPIO/LED Controller,"
on page 120 for additional details.
Port 1 Ethernet
TX Negative
TXN1
AIO
110
Ethernet TX Negative: Negative output of Port 1
Ethernet transmitter. See Note 3-1 for additional
information.
Port 1 Ethernet
TX Positive
TXP1
AIO
111
Ethernet TX Positive: Positive output of Port 1
Ethernet transmitter. See Note 3-1 for additional
information.
Port 1 Ethernet
RX Negative
RXN1
AIO
115
Ethernet RX Negative: Negative input of Port 1
Ethernet receiver. See Note 3-1 for additional
information.
Port 1 Ethernet
RX Positive
RXP1
AIO
116
Ethernet RX Positive: Positive input of Port 1
Ethernet receiver. See Note 3-1 for additional
information.
Note 3-1
The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled
and a reverse connection is detected or manually selected, the RX and TX pins will be swapped
internally.
2008-2016 Microchip Technology Inc.
DS00002288A-page 17
LAN9313/LAN9313i
TABLE 3-2:
Pin
83-86
LAN PORT 2 PINS
Name
Symbol
Buffer
Type
Port 2 LED
Indicators
nP2LED[3:0]
OD12
General
Purpose I/O
Data
GPIO[7:4]
Description
LED indicators: When configured as LED outputs
via the LED Configuration Register (LED_CFG),
these pins are open-drain, active low outputs and the
pull-ups and input buffers are disabled. The
functionality of each pin is determined via the
LED_CFG[9:8] bits.
IS/O12/O General Purpose I/O Data: When configured as
GPIO via the LED Configuration Register
D12
(LED_CFG), these general purpose signals are fully
(PU)
programmable as either push-pull outputs, opendrain outputs or Schmitt-triggered inputs by writing
the General Purpose I/O Configuration Register
(GPIO_CFG) and General Purpose I/O Data &
Direction Register (GPIO_DATA_DIR). The pull-ups
are enabled in GPIO mode. The input buffers are
disabled when set as an output.
Note:
See Section 12.0, "GPIO/LED Controller,"
on page 120 for additional details.
Port 2 Ethernet
TX Negative
TXN2
AIO
127
Ethernet TX Negative: Negative output of Port 2
Ethernet transmitter. See Note 3-2 for additional
information.
Port 2 Ethernet
TX Positive
TXP2
AIO
126
Ethernet TX Positive: Positive output of Port 2
Ethernet transmitter. See Note 3-2 for additional
information.
Port 2 Ethernet
RX Negative
RXN2
AIO
124
Ethernet RX Negative: Negative input of Port 2
Ethernet receiver. See Note 3-2 for additional
information.
Port 2 Ethernet
RX Positive
RXP2
AIO
123
Ethernet RX Positive: Positive input of Port 2
Ethernet receiver. See Note 3-2 for additional
information.
Note 3-2
TABLE 3-3:
The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled
and a reverse connection is detected or manually selected, the RX and TX pins will be swapped
internally.
LAN PORT 1 & 2 POWER AND COMMON PINS
Name
Symbol
Buffer
Type
Bias Reference
EXRES
AI
Bias Reference: Used for internal bias circuits.
Connect to an external 12.4K ohm, 1% resistor to
ground.
VDD33A1
P
+3.3V Port 1 Analog Power Supply
114,117
+3.3V Port 1
Analog Power
Supply
VDD33A2
122,125
+3.3V Port 2
Analog Power
Supply
VDD33BIAS
120
+3.3V Master
Bias Power
Supply
Pin
119
DS00002288A-page 18
Description
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
P
+3.3V Port 2 Analog Power Supply
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
P
+3.3V Master Bias Power Supply
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 3-3:
LAN PORT 1 & 2 POWER AND COMMON PINS (CONTINUED)
Pin
Name
Symbol
Buffer
Type
VDD18TX2
P
121
Port 2
Transmitter
+1.8V Power
Supply
Description
Port 2 Transmitter +1.8V Power Supply: This pin
is supplied from the internal PHY voltage regulator.
This pin must be tied to the VDD18TX1 pin for
proper operation.
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
118
TABLE 3-4:
Pin
Port 1
Transmitter
+1.8V Power
Supply
VDD18TX1
P
Port 1 Transmitter +1.8V Power Supply: This pin
must be connected directly to the VDD18TX2 pin for
proper operation.
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
LAN PORT 0(EXTERNAL MII) PINS
Name
Symbol
MII Transmit
Data
TXD[3:0]
Buffer
Type
Descrption
IS/O8
(PD)
Note 3-3
MII Transmit Data: The functionality of these signals
is dependant on the mode of the
LAN9313/LAN9313i:
• In MAC mode, this is the data from the
LAN9313/LAN9313i switch to an external PHY.
See Note 3-3.
• In PHY mode, this is the data from an external
MAC to the LAN9313/LAN9313i switch.
19,20,22,23
MII Transmitter
Enable
TXEN
IS/O8
(PD)
Note 3-3
MII Transmit Enable: Indicates valid data on
TXD[3:0].
• In MAC mode, this signal is output to an external
PHY. See Note 3-3.
• In PHY mode, this signal is input from an external MAC.
4
MII Receive
Error
RXER
IS/O8
(PD)
Note 3-3
MII Receive Error: Indicates a receive error in the
packet.
• In MAC mode, this signal is input from an external PHY.
• In PHY mode, this signal is output to an external
MAC. This signal is always driven low when in
PHY mode. See Note 3-3.
9
MII Transmit
Error
62
2008-2016 Microchip Technology Inc.
TXER
IS/O8
(PD)
Note 3-3
MII Transmit Error: Indicates a transmit error in the
packet.
• In MAC mode, this signal is output to an external
PHY and indicates an invalid symbol is to be
transmitted. This signal is always driven low
when in MAC mode. See Note 3-3.
• In PHY mode, this signal is input from an external MAC and indicates the current packet should
be aborted.
DS00002288A-page 19
LAN9313/LAN9313i
TABLE 3-4:
Pin
LAN PORT 0(EXTERNAL MII) PINS (CONTINUED)
Name
Symbol
MII Collision
COL
17
MII carrier
Sense
CRS
16
MII Transmit
Clock
TXCLK
24
MII Receive
Data
RXD[3:0]
Buffer
Type
IS/O8
(PU)
Note 3-4
MII Collision: Indicates a collision event.
IS/O8
(PD)
Note 3-3
MII Carrier Sense: Indicates a network carrier.
IS/O12
(PD)
Note 3-3
MII Transmit Clock:
IS/O8
(PD)
Note 3-3
MII Receive Data:
IS/O8
(PD)
Note 3-3
MII Receive Data Valid: Indicates valid data on
RXD[3:0].
8,6,5,61
MII Receive
Data Valid
RXDV
Descrption
• In MAC mode, this signal is input from an external PHY.
• In PHY mode, this signal is output to an external
MAC. See Note 3-4.
• In MAC mode, this signal is input from an external PHY.
• In PHY mode, this signal is output to an external
MAC. See Note 3-3.
• In MAC mode, this is the transmitter clock input
from an external PHY.
• In PHY mode, this is the transmitter clock output
to an external MAC. See Note 3-3.
• In MAC mode, this is the data from an external
PHY to the LAN9313/LAN9313i switch.
• In PHY mode, this is the data from the
LAN9313/LAN9313i switch to an external MAC.
See Note 3-3.
• In MAC mode, this signal is input from an external PHY.
• In PHY mode, this signal is output to an external
MAC. See Note 3-3.
11
MII Receive
Clock
RXCLK
10
MII
Management
Data
12
DS00002288A-page 20
MDIO
IS/O12
(PD)
Note 3-3
MII Receive Clock:
IS/O8
Note 3-5
MII Management Data:
• In MAC mode, this is the receiver clock input
from an external PHY.
• In PHY mode, this is the receiver clock output to
an external MAC. See Note 3-3.
• In SMI/MII slave management modes, this signal
is the management data to/from an external
master.
• In MII master management modes, this signal is
the management data to/from an external PHY.
See Note 3-5
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 3-4:
Pin
LAN PORT 0(EXTERNAL MII) PINS (CONTINUED)
Name
Symbol
MII
Management
Clock
MDC
MII Port
Duplex
MII_DUPLEX
Buffer
Type
IS/O8
Descrption
MII Management Clock:
Note 3-6
• In SMI/MII slave management modes, this is the
management clock input from an external master.
• In MII master management modes, this is the
management clock output to an external PHY.
See Note 3-6.
15
IS
(PU)
Note 3-7
MII Port Duplex: This pin sets the duplex of the MII
port. Its’ value can be changed at any time (live
value) and can be overridden by disabling the AutoNegotiation (VPHY_AN) bit in the Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL) of the Virtual
PHY.
In MAC mode, this signal is typically tied to the
duplex indication from the external PHY.
60
In PHY mode, this signal is typically tied high or low
as needed.
The polarity of this signal depends upon the
duplex_pol_strap_mii strap. If duplex_pol_strap_mii
is 0, a MII_DULPEX value of 0 indicates full duplex,
and 1 indicates half duplex. If duplex_pol_strap_mii
is 1, a MII_DULPEX value of 1 indicates full duplex,
and 0 indicates half duplex.
Note 3-3
When used as an output, the pin(s) input buffer(s) and pull-down(s) are disabled.
Note 3-4
When used as an output, the pin input buffer and pull-up are disabled.
Note 3-5
An external pull-up is required when the SMI or MII management interface is used. This ensures that
the IDLE state of the MDIO signal is logic 1. An external pull-up is recommended when the SMI or
MII management interface is not used to avoid a floating signal.
Note 3-6
When used as an output, the pin input buffer is disabled. An external pull-down is recommended
when the SMI or MII management interface is not used to avoid a floating signal.
Note 3-7
This signal is pulled high through an internal pull-up resistor at all times.
TABLE 3-5:
Pin
DEDICATED CONFIGURATION STRAP PINS
Name
Symbol
LED Enable
Strap
LED_EN
56
IS
(PU)
Note 3-8
44
45,47
Buffer
Type
LED Function
Strap
LED_FUN[1:0]
IS
(PU)
Note 3-8
Port 1 AutoMDIX Enable
Strap
AUTO_MDIX_1
2008-2016 Microchip Technology Inc.
IS
(PU)
Note 3-8
Description
LED Enable Strap: Configures the default value for
the LED_EN bits in the LED Configuration Register
(LED_CFG). When latched low, all 8 LED/GPIO pins
are configured as GPIOs. When latched high, all 8
LED/GPIO pins are configured as LEDs. See Note 39.
LED Function Straps: Configures the default value
for the LED_FUN bits in the LED Configuration
Register (LED_CFG). When latched low, the
corresponding bit will be cleared. When latched high,
the corresponding bit will be set. See Note 3-9.
Port 1 Auto-MDIX Enable Strap: Configures the
default value for the Auto-MDIX functionality on Port
1. When latched low, Auto-MDIX is disabled. When
latched high, Auto-MDIX is enabled. See Note 3-9.
DS00002288A-page 21
LAN9313/LAN9313i
TABLE 3-5:
Pin
55
DEDICATED CONFIGURATION STRAP PINS (CONTINUED)
Name
Symbol
Port 1 Auto
Negotiation
Enable Strap
AUTO_NEG_1
Port 1 Speed
Select Strap
SPEED_1
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
53
Port 1 Duplex
Select Strap
DUPLEX_1
IS
(PU)
Note 3-8
52
51
Buffer
Type
Port 1
Backpressure
Enable Strap
BP_EN_1
Port 1 FullDuplex Flow
Control Enable
Strap
FD_FC_1
Port 1 Manual
Flow Control
Enable Strap
MANUAL_FC_1
Port 2 AutoMDIX Enable
Strap
AUTO_MDIX_2
Port 2 Auto
Negotiation
Enable Strap
AUTO_NEG_2
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
50
IS
(PU)
Note 3-8
49
43
42
DS00002288A-page 22
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
Description
Port 1 Auto Negotiation Enable Strap: Configures
the default value for the Auto-Negotiation (PHY_AN)
enable bit in the PHY_BASIC_CTRL_1 register (See
Section 13.2.2.1). When latched low, autonegotiation is disabled. When latched high, autonegotiation is enabled.
See Note 3-9.
Port 1 Speed Select Strap: Configures the default
value for the Speed Select LSB
(PHY_SPEED_SEL_LSB) bit in the
PHY_BASIC_CTRL_1 register (See
Section 13.2.2.1). When latched low, 10 Mbps is
selected. When latched high, 100 Mbps is selected.
See Note 3-9.
Port 1 Duplex Select Strap: Configures the default
value for the Duplex Mode (PHY_DUPLEX) bit in the
PHY_BASIC_CTRL_1 register (See
Section 13.2.2.1). When latched low, half-duplex is
selected. When latched high, full-duplex is selected.
See Note 3-9.
Port 1 Backpressure Enable Strap: Configures the
default value for the Port 1 Backpressure Enable
(BP_EN_1) bit of the Port 1 Manual Flow Control
Register (MANUAL_FC_1). When latched low,
backpressure is disabled. When latched high,
backpressure is enabled. See Note 3-9.
Port 1 Full-Duplex Flow Control Enable Strap:
Configures the default value of the Port 1 Full-Duplex
Transmit Flow Control Enable (TX_FC_1) and Port 1
Full-Duplex Receive Flow Control Enable (RX_FC_1)
bits in the Port 1 Manual Flow Control Register
(MANUAL_FC_1), which are used when manual fullduplex control is selected. When latched low, fullduplex Pause packet detection and generation are
disabled. When latched high, full-duplex Pause
packet detection and generation are enabled. See
Note 3-9.
Port 1 Manual Flow Control Enable Strap:
Configures the default value of the Port 1 Full-Duplex
Manual Flow Control Select (MANUAL_FC_1) bit in
the Port 1 Manual Flow Control Register
(MANUAL_FC_1). When latched low, flow control is
determined by auto-negotiation. When latched high,
flow control is determined by the Port 1 Full-Duplex
Transmit Flow Control Enable (TX_FC_1) and Port 1
Full-Duplex Receive Flow Control Enable (RX_FC_1)
bits. See Note 3-9.
Port 2 Auto-MDIX Enable Strap: Configures the
default value for the Auto-MDIX functionality on Port
2. When latched low, Auto-MDIX is disabled. When
latched high, Auto-MDIX is enabled. See Note 3-9.
Port 2 Auto Negotiation Enable Strap: Configures
the default value for the Auto-Negotiation (PHY_AN)
enable bit in the PHY_BASIC_CTRL_2 register (See
Section 13.2.2.1). When latched low, autonegotiation is disabled. When latched high, autonegotiation is enabled. See Note 3-9.
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 3-5:
Pin
DEDICATED CONFIGURATION STRAP PINS (CONTINUED)
Name
Symbol
Port 2 Speed
Select Strap
SPEED_2
IS
(PU)
Note 3-8
41
Port 2 Duplex
Select Strap
DUPLEX_2
IS
(PU)
Note 3-8
38
37
Buffer
Type
Port 2
Backpressure
Enable Strap
BP_EN_2
Port 2 FullDuplex Flow
Control Enable
Strap
FD_FC_2
Port 2 Manual
Flow Control
Enable Strap
MANUAL_FC_2
Port 0
(External MII)
Speed Select
Strap
SPEED_MII
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
36
IS
(PU)
Note 3-8
35
34
IS
(PU)
Note 3-8
Description
Port 2 Speed Select Strap: Configures the default
value for the Speed Select LSB
(PHY_SPEED_SEL_LSB) bit in the
PHY_BASIC_CTRL_2 register (See
Section 13.2.2.1). When latched low, 10 Mbps is
selected. When latched high, 100 Mbps is selected.
See Note 3-9.
Port 2 Duplex Select Strap: Configures the default
value for the Duplex Mode (PHY_DUPLEX) bit in the
PHY_BASIC_CTRL_2 register (See
Section 13.2.2.1). When latched low, half-duplex is
selected. When latched high, full-duplex is selected.
See Note 3-9.
Port 2 Backpressure Enable Strap: Configures the
default value for the Port 2 Backpressure Enable
(BP_EN_2) bit of the Port 2 Manual Flow Control
Register (MANUAL_FC_2). When latched low,
backpressure is disabled. When latched high,
backpressure is enabled. See Note 3-9.
Port 2 Full-Duplex Flow Control Enable Strap:
Configures the default value of the Port 2 Full-Duplex
Transmit Flow Control Enable (TX_FC_2) and Port 2
Full-Duplex Receive Flow Control Enable (RX_FC_2)
bits in the Port 2 Manual Flow Control Register
(MANUAL_FC_2), which are used when manual fullduplex control is selected. When latched low, fullduplex Pause packet detection and generation are
disabled. When latched high, full-duplex Pause
packet detection and generation are enabled. See
Note 3-9.
Port 2 Manual Flow Control Enable Strap:
Configures the default value of the Port 2 Full-Duplex
Manual Flow Control Select (MANUAL_FC_2) bit in
the Port 2 Manual Flow Control Register
(MANUAL_FC_2). When latched low, flow control is
determined by auto-negotiation. When latched high,
flow control is determined by the Port 2 Full-Duplex
Transmit Flow Control Enable (TX_FC_2) and Port 2
Full-Duplex Receive Flow Control Enable (RX_FC_2)
bits. See Note 3-9.
Port 0(External MII) Speed Select Strap: Together
with the DUPLEX_POL_MII and MII_DUPLEX pins,
configures the base ability values in the Virtual PHY
Auto-Negotiation Link Partner Base Page Ability
Register (VPHY_AN_LP_BASE_ABILITY).
This pin also configures the speed for Port 0 when
the Virtual Auto-Negotiation fails. When latched low,
10Mbps is selected. When latched high, 100Mbps is
selected.
Refer to Section 13.1.7.6 and Table 13-6 for more
information.
See Note 3-9.
2008-2016 Microchip Technology Inc.
DS00002288A-page 23
LAN9313/LAN9313i
TABLE 3-5:
Pin
DEDICATED CONFIGURATION STRAP PINS (CONTINUED)
Name
Symbol
Port 0
(External MII)
Duplex Polarity
Strap
DUPLEX_POL_MII
Buffer
Type
IS
(PU)
Note 3-8
Description
Port 0(External MII) Duplex Polarity Strap:
Configures the polarity of the MII_DUPLEX pin for
Port 0.
If MII_DUPLEX = DUPLEX_POL_MII, full-duplex is
selected.
32
If MII_DUPLEX != DUPLEX_POL_MII, half-duplex is
selected.
Refer to Section 13.1.7.6 and Table 13-6 for more
information.
See Note 3-9.
31
30
29
Port 0
(External MII)
Backpressure
Enable Strap
BP_EN_MII
Port 0
(External MII)
Full-Duplex
Flow Control
Enable Strap
FD_FC_MII
Port 0
(External MII)
Manual Flow
Control Enable
Strap
MANUAL_FC_MII
Serial
Management
Mode Strap
MNGT_MODE[1:0]
MII Mode Strap
MII_MODE
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
IS
(PU)
Note 3-8
26,28
Port 0(External MII) Backpressure Enable Strap:
Configures the default value for the Port 0
Backpressure Enable (BP_EN_MII) bit of the Port
0(External MII) Manual Flow Control Register
(MANUAL_FC_MII). When latched low,
backpressure is disabled. When latched high,
backpressure is enabled.
See Note 3-9.
Port 0(External MII) Full-Duplex Flow Control
Enable Strap: Configures the default of the
TX_FC_MII and RX_FC_MII bits in the Port
0(External MII) Manual Flow Control Register
(MANUAL_FC_MII). When latched low, flow control
is disabled on RX/TX. When latched high, flow
control is enabled on RX/TX. See Note 3-9.
Port 0(External MII) Manual Flow Control Enable
Strap: Configures the default value of the
MANUAL_FC_MII bit in the Port 0(External MII)
Manual Flow Control Register (MANUAL_FC_MII).
When latched low, flow control is determined by
Virtual Auto-Negotiation. When latched high, flow
control is determined by TX_FC_MII and RX_FC_MII
bits in the Port 0(External MII) Manual Flow Control
Register (MANUAL_FC_MII). See Note 3-9, and
Note 3-10.
Serial Management Mode Strap: Configures the
serial management mode.
00
01
10
11
=
=
=
=
Unmanaged mode
SMI Managed Mode
I2C Managed Mode
SPI Managed Mode
See Note 3-9.
25
IS
(PU)
Note 3-8
MII Mode Strap: Configures the mode of the
external MII port.
0 = MAC Mode
1 = PHY Mode
See Note 3-9.
DS00002288A-page 24
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
PHY Address
Strap
PHY_ADDR_SEL
Buffer
Type
IS
(PU)
Note 3-8
95
Description
PHY Address Strap: Configures the default MII
management address values for the PHYs (Virtual,
Port 1, and Port 2) as detailed in Section 7.1.1, "PHY
Addressing," on page 68.
PORT 2 PHY
ADDRESS
Symbol
PORT 1 PHY
ADDRESS
Name
VIRTUAL PHY
ADDRESS
Pin
DEDICATED CONFIGURATION STRAP PINS (CONTINUED)
PHY_ADDR_SEL
VALUE
TABLE 3-5:
0
0
1
2
1
1
2
3
See Note 3-9.
Note: For more information on configuration straps, refer to Section 4.2.4, "Configuration Straps," on
page 33. Additional strap pins, which share functionality with the EEPROM pins, are described
in Table 3-6.
Note 3-8
This signal is pulled high through an internal pull-up resistor at all times.
Note 3-9
Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap
pins are identified by an underlined symbol name. Some configuration straps can be overridden by
values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 33 for more
information.
Note 3-10
In MAC mode, this strap is not used. In this mode, the Virtual PHY is not applicable, and full-duplex
flow control must be controlled manually by the host, based upon the external PHYs Auto-negotiation
results.
TABLE 3-6:
Pin
96
EEPROM PINS
Buffer
Type
Description
EEDI
IS
(PD)
EEPROM Microwire Data Input (EEDI): In
Microwire EEPROM mode (EEPROM_TYPE = 0),
this pin is the Microwire EEPROM serial data input.
EE_SDA
IS/OD8
EEPROM I2C Serial Data Input/Output (EE_SDA):
In I2C EEPROM mode (EEPROM_TYPE = 1), this
pin is the I2C EEPROM serial data input/output.
Name
Symbol
EEPROM
Microwire Data
Input
EEPROM I2C
Serial Data
Input/Output
Note:
2008-2016 Microchip Technology Inc.
If I2C is selected, an external pull-up is
required when using an EEPROM and is
recommended if no EEPROM is attached.
DS00002288A-page 25
LAN9313/LAN9313i
TABLE 3-6:
Pin
EEPROM PINS (CONTINUED)
Name
Symbol
Buffer
Type
EEPROM
Microwire Data
Output
EEDO
O8
Description
EEPROM Microwire Data Output: In Microwire
EEPROM mode (EEPROM_TYPE = 0), this pin is
the Microwire EEPROM serial data output.
Note:
In I2C mode (EEPROM_TYPE=1), this pin
is not used and is driven low.
Note:
When not using a Microwire or I2C
EEPROM, an external pull-down resistor is
recommended on this pin.
98
EEPROM Type
Strap
EEPROM_TYPE
IS
Note 3-11
EEPROM Type Strap: Configures the EEPROM
type. See Note 3-12
0 = Microwire Mode
1 = I2C Mode
Note:
EEPROM
Microwire
Serial Clock
EECLK
O8
EEPROM I2C
Serial Clock
EE_SCL
IS/OD8
EEPROM Microwire Serial Clock (EECLK): In
Microwire EEPROM mode (EEPROM_TYPE = 0),
this pin is the Microwire EEPROM clock output.
EEPROM I2C Serial Clock (EE_SCL): In I2C
EEPROM mode (EEPROM_TYPE=1), this pin is the
I2C EEPROM clock input/open-drain output.
Note:
99
EEPROM Size
Strap 1
EEPROM_SIZE_1
EEPROM
Microwire Chip
Select
EECS
IS
Note 3-13
O8
EEPROM Size
Strap 0
EEPROM_SIZE_0
IS
Note 3-11
If I2C is selected, an external pull-up is
required when using an EEPROM and is
recommended if no EEPROM is attached.
EEPROM Size Strap 1: Configures the high bit of
the EEPROM size range as specified in Section 8.2,
"I2C/Microwire Master EEPROM Controller," on
page 83. This bit is not used for I2C EEPROMs. See
Note 3-12.
EEPROM Microwire Chip Select: In Microwire
EEPROM mode (EEPROM_TYPE = 0), this pin is
the Microwire EEPROM chip select output.
Note:
101
When not using a Microwire or I2C
EEPROM, an external pull-down resistor is
recommended on this pin.
In I2C mode (EEPROM_TYPE=1), this pin
is not used and is driven low.
EEPROM Size Strap 0: Configures the low bit of the
EEPROM size range as specified in Section 8.2,
"I2C/Microwire Master EEPROM Controller," on
page 83. See Note 3-12.
Note 3-11
The IS buffer type is valid only during the time specified in Section 14.5.2, "Reset and Configuration
Strap Timing," on page 257.
Note 3-12
Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap
pins are identified by an underlined symbol name. Refer to Section 4.2.4, "Configuration Straps," on
page 33 for more information.
Note 3-13
The IS buffer type is valid only during the time specified in Section 14.5.2, "Reset and Configuration
Strap Timing," on page 257 and when in I2C mode.
DS00002288A-page 26
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 3-7:
Pin
SERIAL MANAGEMENT PINS
Name
Symbol
SPI Slave
Serial Data
Input
SI
Buffer
Type
IS
(PU)
Description
SPI Slave Serial Data Input: In SPI slave mode,
this pin is the SPI serial data input.
Note:
67
68
69
I2C Slave
Serial Data
Input/Output
(I2C Slave
Mode)
SDA
SPI Slave
Serial Data
Output
SO
O8
SPI Slave Serial Data Output: In I2C slave, SMI
slave, and unmanaged modes, this pin is not used
and is driven low.
SPI Slave Chip
Select
nSCS
IS
(PU)
SPI Slave Chip Select: SPI slave mode chip select
input. When low, the LAN9313/LAN9313i SPI slave
is selected for SPI transfers. When high, the SPI
serial data output (SO) is 3-stated. In I2C slave, SMI
slave, and unmanaged modes, this pin is not used.
SPI Slave
Serial Clock
SCK
IS
(PU)
SPI Slave Serial Clock: In SPI slave mode, this pin
is the SPI clock input.
IS/OD8
I2C Serial Data Input/Output: In I2C slave mode,
this pin is the I2C serial data input/output.
Note:
Note:
70
I2C Slave
Serial Clock
SCL
IS
In SMI slave and unmanaged modes, this
pin is unused and pulled-up internally.
MISCELLANEOUS PINS
Name
Symbol
General
Purpose I/O
Data
GPIO[11:8]
77-79,
82
Buffer
Type
Description
IS/OD12/ General Purpose I/O Data: These general purpose
signals are fully programmable as either push-pull
O12
outputs, open-drain outputs, or Schmitt-triggered
(PU)
Note 3-14 inputs by writing the General Purpose I/O
Configuration Register (GPIO_CFG) and General
Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For more information, refer to
Section 12.0, "GPIO/LED Controller," on page 120.
Note:
63
In SMI slave and unmanaged modes, this
pin is unused and pulled-up internally.
Refer to Section 8.0, "Serial Management," on page 83 for additional information regarding the serial management configuration and functionality.
TABLE 3-8:
Pin
In SMI slave and unmanaged modes, this
pin is unused and pulled-up internally.
I2C Slave Serial Clock: In I2C slave mode, this pin
is the I2C clock input.
Note:
Note:
In SMI slave and unmanaged modes, this
pin is unused and pulled-up internally.
Interrupt
Output
2008-2016 Microchip Technology Inc.
IRQ
O8/OD8
The remaining GPIO[7:0] pins share
functionality with the LED output pins, as
described in Table 3-1 and Table 3-2.
Interrupt Output: Interrupt request output. The
polarity, source and buffer type of this signal is
programmable via the Interrupt Configuration
Register (IRQ_CFG). For more information, refer to
Section 5.0, "System Interrupts," on page 41.
DS00002288A-page 27
LAN9313/LAN9313i
TABLE 3-8:
Pin
MISCELLANEOUS PINS (CONTINUED)
Buffer
Type
Name
Symbol
System Reset
Input
nRST
IS
(PU)
System Reset Input: This active low signal allows
external hardware to reset the LAN9313/LAN9313i.
The LAN9313/LAN9313i also contains an internal
power-on reset circuit. Thus, this signal may be left
unconnected if an external hardware reset is not
needed. When used, this signal must adhere to the
reset timing requirements as detailed in Section
14.5.2, "Reset and Configuration Strap Timing," on
page 257.
Test 1
TEST1
AI
Test 1: This pin must be tied to VDD33IO for proper
operation.
Test 2
TEST2
AI
Test 2: This pin must be tied to VDD33IO for proper
operation.
71
75
108
Note 3-14
TABLE 3-9:
Pin
107
Description
The input buffers are enabled when configured as GPIO inputs only.
PLL PINS
Name
Symbol
Buffer
Type
PLL +1.8V
Power Supply
VDD18PLL
P
Description
PLL +1.8V Power Supply: This pin must be
connected to VDD18CORE for proper operation.
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
Crystal Input
XI
ICLK
Crystal Input: External 25MHz crystal input. This
signal can also be driven by a single-ended clock
oscillator. When this method is used, XO should be
left unconnected.
Crystal Output
XO
OCLK
Crystal Output: External 25MHz crystal output.
105
106
TABLE 3-10:
CORE AND I/O POWER AND GROUND PINS
Pin
Name
Symbol
Buffer
Type
7,13,21,27,3
3,39,46,
54,64,66,
72,73,81,
87,93,100
+3.3V I/O
Power
VDD33IO
P
3,14,40,65,7
4,88,104
Description
+3.3V Power Supply for I/O Pins and Internal
Regulator
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
Digital Core
+1.8V Power
Supply Output
VDD18CORE
P
Digital Core +1.8V Power Supply Output: +1.8V
power from the internal core voltage regulator. All
VDD18CORE pins must be tied together for proper
operation.
Refer to the LAN9313/LAN9313i reference
schematic for additional connection information.
18,48,80,
97,112,113,1
28
Common
Ground
VSS
P
Common Ground
Note 3-15
Note 3-15
Plus external pad for 128-XVTQFP package only.
DS00002288A-page 28
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 3-11:
NO-CONNECT PINS
Pin
Name
Symbol
Buffer
Type
1,2,
57-59,
76,94,102,
103,109
No Connect
NC
-
2008-2016 Microchip Technology Inc.
Description
No Connect: These pins must be left floating for
normal device operation.
DS00002288A-page 29
LAN9313/LAN9313i
4.0
CLOCKING, RESETS, AND POWER MANAGEMENT
4.1
Clocks
The LAN9313/LAN9313i includes a clock module which provides generation of all system clocks as required by the various sub-modules of the device. The LAN9313/LAN9313i requires a fixed-frequency 25MHz clock source for use by the
internal clock oscillator and PLL. This is typically provided by attaching a 25MHz crystal to the XI and XO pins as specified in Section 14.6, "Clock Circuit," on page 259. Optionally, this clock can be provided by driving the XI input pin with
a single-ended 25MHz clock source. If a single-ended source is selected, the clock input must run continuously for normal device operation. The internal PLL generates a fixed 200MHz base clock which is used to derive all
LAN9313/LAN9313i sub-system clocks.
In addition to the sub-system clocks, the clock module is also responsible for generating the clocks used for the general
purpose timer and free-running clock. Refer to Section 11.0, "General Purpose Timer & Free-Running Clock," on
page 119 for additional details.
Note:
4.2
Crystal specifications are provided in Table 14-10, “LAN9313/LAN9313i Crystal Specifications,” on
page 259.
Resets
The LAN9313/LAN9313i provides multiple hardware and software reset sources, which allow varying levels of the
LAN9313/LAN9313i to be reset. All resets can be categorized into three reset types as described in the following sections:
• Chip-Level Resets
- Power-On Reset (POR)
- nRST Pin Reset
• Multi-Module Resets
- Digital Reset (DIGITAL_RST)
• Single-Module Resets
- Port 2 PHY Reset
- Port 1 PHY Reset
- Virtual PHY Reset
The LAN9313/LAN9313i supports the use of configuration straps to allow automatic custom configurations of various
LAN9313/LAN9313i parameters. These configuration strap values are set upon de-assertion of all chip-level resets and
can be used to easily set the default parameters of the chip at power-on or pin (nRST) reset. Refer to Section 4.2.4,
"Configuration Straps," on page 33 for detailed information on the usage of these straps.
Note:
The LAN9313/LAN9313i EEPROM Loader is run upon a power-on reset, nRST pin reset, and digital reset.
Refer to Section 8.2.4, "EEPROM Loader," on page 93 for additional information.
Table 4-1 summarizes the effect of the various reset sources on the LAN9313/LAN9313i. Refer to the following sections
for detailed information on each of these reset types.
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2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Sys Interrupts
Switch Fabric
Ethernet PHYs
PMI
SPI/I2C Slave
SMI Slave
EEPROM
Controller
1588 Time Stamp
GPIO/LED
Controller
Config. Straps
Latched
EEPROM Loader
Run
RESET SOURCES AND AFFECTED LAN9313/LAN9313I CIRCUITRY
System
Clocks/Reset/PME
TABLE 4-1:
POR
X
X
X
X
X
X
X
X
X
X
X
X
nRST Pin
X
X
X
X
X
X
X
X
X
X
X
X
Digital Reset
X
X
X
X
X
X
X
X
X
Reset Source
4.2.1
Port 2 PHY
X
Port 1 PHY
X
Virtual PHY
X
X
CHIP-LEVEL RESETS
A chip-level reset event activates all internal resets, effectively resetting the entire LAN9313/LAN9313i. Configuration
straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A chip-level reset is initiated by assertion of any of the following input events:
• Power-On Reset (POR)
• nRST Pin Reset
Chip-level reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST).
The returned data will be invalid until the serial interface resets are complete. Once the returned data is the correct byte
ordering value, the serial interface resets have completed. The completion of the entire chip-level reset must then be
determined by polling the READY bit of the Hardware Configuration Register (HW_CFG) until it is set. When set, the
READY bit indicates that the reset has completed and the device is ready to be accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Byte Order Test Register (BYTE_TEST), and
Reset Control Register (RESET_CTL), read access to any internal resources is forbidden while the READY bit is
cleared. Writes to any address are invalid until the READY bit is set.
4.2.1.1
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the LAN9313/LAN9313i, or if the power is removed and
reapplied to the LAN9313/LAN9313i. This event resets all circuitry within the device. Configuration straps are latched,
and the EEPROM Loader is run as a result of this reset.
A POR reset typically takes approximately 23mS, plus additional time (91uS for I2C, 28uS for Microwire) per byte of data
loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will complete
in approximately 6.0 seconds for I2C EEPROM, and 80mS for Microwire EEPROM.
4.2.1.2
nRST Pin Reset
Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this
reset input is optional, but when used, it must be driven for the period of time specified in Section 14.5.2, "Reset and
Configuration Strap Timing," on page 257. Configuration straps are latched, and the EEPROM Loader is run as a result
of this reset.
A nRST pin reset typically takes approximately 760uS, plus additional time (91uS for I2C, 28uS for Microwire) per byte
of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will
complete in approximately 6.0 seconds for I2C EEPROM, and 58mS for Microwire EEPROM.
Note:
The nRST pin is pulled-high internally. If unused, this signal can be left unconnected. Do not rely on internal
pull-up resistors to drive signals external to the device.
Please refer to Table 3-8, "Miscellaneous Pins" for a description of the nRST pin.
2008-2016 Microchip Technology Inc.
DS00002288A-page 31
LAN9313/LAN9313i
4.2.2
MULTI-MODULE RESETS
Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration straps are not latched
upon multi-module resets. A multi-module reset is initiated by assertion of the following:
• Digital Reset (DIGITAL_RST)
Multi-module reset/configuration completion can be determined by first polling the Byte Order Test Register
(BYTE_TEST). The returned data will be invalid until the serial interface resets are complete. Once the returned data is
the correct byte ordering value, the serial interface resets have completed. The completion of the entire chip-level reset
must then be determined by polling the READY bit of the Hardware Configuration Register (HW_CFG) until it is set.
When set, the READY bit indicates that the reset has completed and the device is ready to be accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Byte Order Test Register (BYTE_TEST), and
Reset Control Register (RESET_CTL), read access to any internal resources is forbidden while the READY bit is
cleared. Writes to any address are invalid until the READY bit is set.
Note:
4.2.2.1
The digital reset does not reset register bits designated as NASR.
Digital Reset (DIGITAL_RST)
A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register (RESET_CTL). A digital reset
will reset all LAN9313/LAN9313i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY).
The EEPROM Loader will automatically run following this reset. Configuration straps are not latched as a result of a
digital reset.
A digital reset typically takes approximately 760uS, plus additional time (91uS for I2C, 28uS for Microwire) per byte of
data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will
complete in approximately 6.0 seconds for I2C EEPROM, and 58mS for Microwire EEPROM.
4.2.3
SINGLE-MODULE RESETS
A single-module reset will reset only the specified module. Single-module resets do not latch the configuration straps or
initiate the EEPROM Loader. A single-module reset is initiated by assertion of the following:
• Port 2 PHY Reset
• Port 1 PHY Reset
• Virtual PHY Reset
4.2.3.1
Port 2 PHY Reset
A Port 2 PHY reset is performed by setting the PHY2_RST bit of the Reset Control Register (RESET_CTL) or the Reset
bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port 2 PHY reset, the
PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9313/LAN9313i are affected by this
reset.
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY power-down mode.
This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to
Section 7.2.9, "PHY Power-Down Modes," on page 78 for additional information.
Port 2 PHY reset completion can be determined by polling the PHY2_RST bit in the Reset Control Register
(RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.
Under normal conditions, the PHY2_RST and Reset bit will clear approximately 110uS after the Port 2 PHY reset occurrence.
Note:
When using the Reset bit to reset the Port 2 PHY, register bits designated as NASR are not reset.
Refer to Section 7.2.10, "PHY Resets," on page 79 for additional information on Port 2 PHY resets.
4.2.3.2
Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the PHY1_RST bit of the Reset Control Register (RESET_CTL) or the Reset
bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port 1 PHY reset, the
PHY1_RST and Reset bits are automatically cleared. No other modules of the LAN9313/LAN9313i are affected by this
reset.
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LAN9313/LAN9313i
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY power-down mode.
This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to
Section 7.2.9, "PHY Power-Down Modes," on page 78 for additional information.
Port 1 PHY reset completion can be determined by polling the PHY1_RST bit in the Reset Control Register
(RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.
Under normal conditions, the PHY1_RST and Reset bit will clear approximately 110uS after the Port 1 PHY reset occurrence.
Note:
When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not reset.
Refer to Section 7.2.10, "PHY Resets," on page 79 for additional information on Port 1 PHY resets.
4.2.3.3
Virtual PHY Reset
A Virtual PHY reset is performed by setting the VPHY_RST bit of the Reset Control Register (RESET_CTL) or Reset in
the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). No other modules of the LAN9313/LAN9313i are
affected by this reset.
Virtual PHY reset completion can be determined by polling the VPHY_RST bit in the Reset Control Register
(RESET_CTL) or the Reset bit in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) until it clears. Under
normal conditions, the VPHY_RST and Reset bit will clear approximately 1uS after the Virtual PHY reset occurrence.
Refer to Section 7.3.3, "Virtual PHY Resets," on page 81 for additional information on Virtual PHY resets.
4.2.4
CONFIGURATION STRAPS
Configuration straps allow various features of the LAN9313/LAN9313i to be automatically configured to user defined
values. Configuration straps can be organized into two main categories: hard-straps and soft-straps. Both hard-straps
and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST). The primary difference between these
strap types is that soft-strap default values can be overridden by the EEPROM Loader, while hard-straps cannot.
Configuration straps which have a corresponding external pin include internal resistors in order to prevent the signal
from floating when unconnected. If a particular configuration strap is connected to a load, an external pull-up or pulldown resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior
to latching. The internal resistor can also be overridden by the addition of an external resistor.
Note:
4.2.4.1
The system designer must ensure that configuration strap pins meet the timing requirements specified in
Section 14.5.2, "Reset and Configuration Strap Timing," on page 257. If configuration strap pins are not at
the correct voltage level prior to being latched, the LAN9313/LAN9313i may capture incorrect strap values.
Soft-Straps
Soft-strap values are latched on the release of POR or nRST and are overridden by values from the EEPROM Loader
(when an EEPROM is present). These straps are used as direct configuration values or as defaults for CPU registers.
Some, but not all, soft-straps have an associated pin. Those that do not have an associated pin, have a tie off default
value. All soft-strap values can be overridden by the EEPROM Loader. Table 4-2 provides a list of all soft-straps and
their associated pin or default value. Straps which have an associated pin are also fully defined in Section 3.0, "Pin
Description and Configuration," on page 15. Refer to Section 8.2.4, "EEPROM Loader," on page 93 for information on
the operation of the EEPROM Loader and the loading of strap values.
Upon setting the DIGITAL_RST bit in the Reset Control Register (RESET_CTL) or upon issuing a RELOAD command
via the EEPROM Command Register (E2P_CMD), these straps return to their original latched (non-overridden) values
if an EEPROM is no longer attached or has been erased. The associated pins are not re-sampled. (i.e. The value latched
on the pin during the last POR or nRST will be used, not the value on the pin during the digital reset or RELOAD command issuance). If it is desired to re-latch the current configuration strap pin values, a POR or nRST must be issued.
2008-2016 Microchip Technology Inc.
DS00002288A-page 33
LAN9313/LAN9313i
TABLE 4-2:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS
Strap Name
LED_en_strap[7:0]
Description
Pin / Default Value
LED Enable Straps: Configures the default value for the
LED_EN
LED_EN bits in the LED Configuration Register (LED_CFG).
A high value configures the associated LED/GPIO pin as a
LED. A low value configures the associated LED/GPIO pin
as a GPIO.
Note:
One pin configures the default for all 8 LED/GPIOs,
but 8 separate bits are loaded by the EEPROM
Loader, allowing individual control over each
LED/GPIO.
LED_fun_strap[1:0]
LED Function Straps: Configures the default value for the LED_FUN[1:0]
LED_FUN bits in the LED Configuration Register
(LED_CFG). When configured low, the corresponding bit will
be cleared. When configured high, the corresponding bit will
be set.
auto_mdix_strap_1
Port 1 Auto-MDIX Enable Strap: Configures the default
AUTO_MDIX_1
value for the Auto-MDIX functionality on Port 1 when the
AMDIXCTL bit in the Port x PHY Special Control/Status
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared. When
configured low, Auto-MDIX is disabled. When configured
high, Auto-MDIX is enabled.
manual_mdix_strap_1
Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1)
for Port 1 when the auto_mdix_strap_1 is low and the
AMDIXCTL bit of the Port x PHY Special Control/Status
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared.
autoneg_strap_1
Port 1 Auto Negotiation Enable Strap: Configures the
AUTO_NEG_1
default value for the Auto-Negotiation (PHY_AN) enable bit
in the PHY_BASIC_CTRL_1 register (See Section 13.2.2.1).
When configured low, auto-negotiation is disabled. When
configured high, auto-negotiation is enabled.
Note:
If AMDIXCTL is set, this strap had no effect.
0b
This strap also affects the default value of the following bits:
• PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
• MODE[2:0] bits of the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
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LAN9313/LAN9313i
TABLE 4-2:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
speed_strap_1
Description
Pin / Default Value
Port 1 Speed Select Strap: Configures the default value for SPEED_1
the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in the
PHY_BASIC_CTRL_1 register (See Section 13.2.2.1). When
configured low, 10 Mbps is selected. When configured high,
100 Mbps is selected.
This strap also affects the default value of the following bits:
• PHY_SPEED_SEL_LSB bit of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
• MODE[2:0] bits of the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
duplex_strap_1
Port 1 Duplex Select Strap: Configures the default value for DUPLEX_1
the Duplex Mode (PHY_DUPLEX) bit in the
PHY_BASIC_CTRL_1 register (See Section 13.2.2.1). When
configured low, half-duplex is selected. When configured
high, full-duplex is selected.
This strap also affects the default value of the following bits:
• PHY_DUPLEX bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex (bit 6) of the Port x PHY AutoNegotiation Advertisement Register (PHY_AN_ADV_x)
• MODE[2:0] bits of the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
BP_EN_strap_1
Port 1 Backpressure Enable Strap: Configures the default BP_EN_1
value for the Port 1 Backpressure Enable (BP_EN_1) bit of
the Port 1 Manual Flow Control Register (MANUAL_FC_1).
When configured low, backpressure is disabled. When
configured high, backpressure is enabled.
FD_FC_strap_1
Port 1 Full-Duplex Flow Control Enable Strap: Configures FD_FC_1
the default value of the Port 1 Full-Duplex Transmit Flow
Control Enable (TX_FC_1) and Port 1 Full-Duplex Receive
Flow Control Enable (RX_FC_1) bits in the Port 1 Manual
Flow Control Register (MANUAL_FC_1), which are used
when manual full-duplex control is selected. When
configured low, full-duplex Pause packet detection and
generation are disabled. When configured high, full-duplex
Pause packet detection and generation are enabled.
2008-2016 Microchip Technology Inc.
DS00002288A-page 35
LAN9313/LAN9313i
TABLE 4-2:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
manual_FC_strap_1
Description
Pin / Default Value
Port 1 Manual Flow Control Enable Strap: Configures the MANUAL_FC_1
default value of the Port 1 Full-Duplex Manual Flow Control
Select (MANUAL_FC_1) bit in the Port 1 Manual Flow
Control Register (MANUAL_FC_1). When configured low,
flow control is determined by auto-negotiation (if enabled),
and symmetric PAUSE is advertised (bit 10 of the Port x PHY
Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
is set).
When configured high, flow control is determined by the Port
1 Full-Duplex Transmit Flow Control Enable (TX_FC_1) and
Port 1 Full-Duplex Receive Flow Control Enable (RX_FC_1)
bits, and symmetric PAUSE is not advertised (bit 10 of the
Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x) is cleared).
auto_mdix_strap_2
Port 2 Auto-MDIX Enable Strap: Configures the default
AUTO_MDIX_2
value for the Auto-MDIX functionality on Port 2 when the
AMDIXCTL bit in the Port x PHY Special Control/Status
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared. When
configured low, Auto-MDIX is disabled. When configured
high, Auto-MDIX is enabled.
Note:
If AMDIXCTL is set, this strap had no effect.
manual_mdix_strap_2
Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1)
for Port 2 when the auto_mdix_strap_2 is low and the
AMDIXCTL bit of the Port x PHY Special Control/Status
Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared.
0b
autoneg_strap_2
Port 2 Auto Negotiation Enable Strap: Configures the
AUTO_NEG_2
default value for the Auto-Negotiation (PHY_AN) enable bit
in the PHY_BASIC_CTRL_2 register (See Section 13.2.2.1).
When configured low, auto-negotiation is disabled. When
configured high, auto-negotiation is enabled.
This strap also affects the default value of the following bits:
• PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
• MODE[2:0] bits of the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
DS00002288A-page 36
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LAN9313/LAN9313i
TABLE 4-2:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
speed_strap_2
Description
Pin / Default Value
Port 2 Speed Select Strap: Configures the default value for SPEED_2
the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in the
PHY_BASIC_CTRL_2 register (See Section 13.2.2.1). When
configured low, 10 Mbps is selected. When configured high,
100 Mbps is selected.
This strap also affects the default value of the following bits:
• PHY_SPEED_SEL_LSB bit of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex
(bit 5) bits of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
• MODE[2:0] bits of the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
duplex_strap_2
Port 2 Duplex Select Strap: Configures the default value for DUPLEX_2
the Duplex Mode (PHY_DUPLEX) bit in the
PHY_BASIC_CTRL_2 register (See Section 13.2.2.1). When
configured low, half-duplex is selected. When configured
high, full-duplex is selected.
This strap also affects the default value of the following bits:
• PHY_DUPLEX bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex (bit 6) of the Port x PHY AutoNegotiation Advertisement Register (PHY_AN_ADV_x)
• MODE[2:0] bits of the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
BP_EN_strap_2
Port 2 Backpressure Enable Strap: Configures the default BP_EN_2
value for the Port 2 Backpressure Enable (BP_EN_2) bit of
the Port 2 Manual Flow Control Register (MANUAL_FC_2).
When configured low, backpressure is disabled. When
configured high, backpressure is enabled.
FD_FC_strap_2
Port 2 Full-Duplex Flow Control Enable Strap: Configures FD_FC_2
the default value of the Port 2 Full-Duplex Transmit Flow
Control Enable (TX_FC_2) and Port 2 Full-Duplex Receive
Flow Control Enable (RX_FC_2) bits in the Port 2 Manual
Flow Control Register (MANUAL_FC_2), which are used
when manual full-duplex control is selected. When
configured low, full-duplex Pause packet detection and
generation are disabled. When configured high, full-duplex
Pause packet detection and generation are enabled.
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DS00002288A-page 37
LAN9313/LAN9313i
TABLE 4-2:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
manual_FC_strap_2
Description
Pin / Default Value
Port 2 Manual Flow Control Enable Strap: Configures the MANUAL_FC_2
default value of the Port 2 Full-Duplex Manual Flow Control
Select (MANUAL_FC_2) bit in the Port 2 Manual Flow
Control Register (MANUAL_FC_2). When configured low,
flow control is determined by auto-negotiation (if enabled),
and symmetric PAUSE is advertised (bit 10 of the Port x PHY
Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
is set).
When configured high, flow control is determined by the Port
2 Full-Duplex Transmit Flow Control Enable (TX_FC_2) and
Port 2 Full-Duplex Receive Flow Control Enable (RX_FC_2)
bits, and symmetric PAUSE is not advertised (bit 10 of the
Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x) is cleared).
speed_strap_mii
Port 0(External MII) Speed Select Strap: Together with the SPEED_MII
duplex_pol_strap_mii and MII_DUPLEX pins, configures the
base ability values in the Virtual PHY Auto-Negotiation Link
Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY).
This pin configures the speed for Port 0 when the Virtual
Auto-Negotiation fails. When configured low, 10Mbps is
selected. When configured high, 100Mbps is selected.
Refer to Section 13.1.7.6 and Table 13-6 for more
information.
duplex_pol_strap_mii
Port 0(External MII) Duplex Polarity Strap: Configures the DUPLEX_POL_MII
polarity of the MII_DUPLEX pin for Port 0.
If MII_DUPLEX = DUPLEX_POL_MII, full-duplex is selected.
If MII_DUPLEX != DUPLEX_POL_MII, half-duplex is
selected.
Refer to Section 13.1.7.6 and Table 13-6 for more
information.
BP_EN_strap_mii
Port 0(External MII) Backpressure Enable Strap:
BP_EN_MII
Configures the default value for the Port 0 Backpressure
Enable (BP_EN_MII) bit of the Port 0(External MII) Manual
Flow Control Register (MANUAL_FC_MII). When configured
low, backpressure is disabled. When configured high,
backpressure is enabled.
FD_FC_strap_mii
Port 0(External MII) Full-Duplex Flow Control Enable
FD_FC_MII
Strap: Configures the default of the TX_FC_MII and
RX_FC_MII bits in the Port 0(External MII) Manual Flow
Control Register (MANUAL_FC_MII) which are used when
manual full-duplex flow control is selected. When configured
low, flow control is disabled on RX/TX. When configured
high, flow control is enabled on RX/TX.
manual_FC_strap_mii
Port 0(External MII) Manual Flow Control Enable Strap: MANUAL_FC_MII
Configures the default value of the MANUAL_FC_MII bit in
the Port 0(External MII) Manual Flow Control Register
(MANUAL_FC_MII). When configured low, flow control is
determined by Virtual Auto-Negotiation (if enabled). When
configured high, flow control is determined by TX_FC_MII
and RX_FC_MII bits in the Port 0(External MII) Manual Flow
Control Register (MANUAL_FC_MII).
Note:
DS00002288A-page 38
In MAC mode, this strap is not used. In this mode,
the Virtual PHY is not applicable, and full-duplex
flow control must be controlled manually by the
host, based upon the external PHYs Autonegotiation results.
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 4-2:
SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
SQE_test_disable_strap_mii
4.2.4.2
Description
SQE Heartbeat Disable Strap: Configures the Signal
Quality Error (Heartbeat) test function by controlling the
default value of the SQEOFF (bit 0) of the Virtual PHY
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS). When configured
low, SQEOFF defaults to 0 and SQE test is enabled. When
configured high, SQEOFF defaults to 1 and SQE test is
disabled.
Pin / Default Value
0b
Hard-Straps
Hard-straps are latched upon Power-On Reset (POR) or pin reset (nRST) only. Unlike soft-straps, hard-straps always
have an associated pin and cannot be overridden by the EEPROM Loader. These straps are used as either direct configuration values or as register defaults. Table 4-3 provides a list of all hard-straps and their associated pin. These
straps, along with their pin assignments are also fully defined in Section 3.0, "Pin Description and Configuration," on
page 15.
TABLE 4-3:
HARD-STRAP CONFIGURATION STRAP DEFINITIONS
Strap Name
mngt_mode_strap[1:0]
Description
Serial Management Mode Strap: Configures the default
serial management mode.
00
01
10
11
=
=
=
=
Pin
MNGT_MODE[1:0]
Unmanaged mode
SMI Managed Mode
I2C Managed Mode
SPI Managed Mode
Refer to Section 2.3, "Modes of Operation," on page 12 for
additional information on the various modes of the
LAN9313/LAN9313i.
eeprom_type_strap
EEPROM Type Strap: Configures the EEPROM type.
EEPROM_TYPE
0 = Microwire Mode
1 = I2C Mode
eeprom_size_strap[1:0]
EEPROM Size Strap [1:0]: Configures the EEPROM size
range as specified in Section 8.2, "I2C/Microwire Master
EEPROM Controller," on page 83.
MII_mode_strap
MII Mode Strap: Configures the default mode of the external MII_MODE
MII port.
EEPROM_SIZE_[1:0]
0 = MAC Mode
1 = PHY Mode
Refer to Section 2.3, "Modes of Operation," on page 12 for
additional information on the various modes of the
LAN9313/LAN9313i.
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DS00002288A-page 39
LAN9313/LAN9313i
TABLE 4-3:
HARD-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
4.3
Pin
VIRTUAL PHY
ADDRESS
PORT 1 PHY
ADDRESS
PORT 2 PHY
ADDRESS
PHY Address Select Strap: Configures the default MII
PHY_ADDR_SEL
management address values for the PHYs and Virtual PHY
as detailed in Section 7.1.1, "PHY Addressing," on page 68.
PHY_ADDR_SEL_STRAP
VALUE
phy_addr_sel_strap
Description
0
0
1
2
1
1
2
3
Power Management
The LAN9313/LAN9313i Port 1 and Port 2 PHYs support several power management and wakeup features.
4.3.1
PORT 1 & 2 PHY POWER MANAGEMENT
The Port 1 & 2 PHYs provide independent general power-down and energy-detect power-down modes which reduce
PHY power consumption. General power-down mode provides power savings by powering down the entire PHY, except
the PHY management control interface. General power-down mode must be manually enabled and disabled as
described in Section 7.2.9.1, "PHY General Power-Down," on page 78.
In energy-detect power-down mode, the PHY will resume from power-down when energy is seen on the cable (typically
from link pulses). If the ENERGYON interrupt (INT7) of either PHYs Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) is unmasked, then the corresponding PHY will generate an interrupt. These interrupts are reflected in
the Interrupt Status Register (INT_STS) bit 27 (PHY_INT2) for the Port 2 PHY, and bit 26 (PHY_INT1) for the Port 1
PHY. These interrupts can be used to trigger the IRQ interrupt output pin, as described in Section 5.2.3, "Ethernet PHY
Interrupts," on page 43. Refer to Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 78 for details on the operation and configuration of the PHY energy-detect power-down mode.
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LAN9313/LAN9313i
5.0
SYSTEM INTERRUPTS
5.1
Functional Overview
This chapter describes the system interrupt structure of the LAN9313/LAN9313i. The LAN9313/LAN9313i provides a
multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable
system interrupts are generated internally by the various LAN9313/LAN9313i sub-modules and can be configured to
generate a single external host interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt
provides the user with the ability to optimize performance dependent upon the application requirements. The IRQ interrupt buffer type, polarity, and de-assertion interval are modifiable. The IRQ interrupt can be configured as an open-drain
output to facilitate the sharing of interrupts with other devices. All internal interrupts are maskable and capable of triggering the IRQ interrupt.
5.2
Interrupt Sources
The LAN9313/LAN9313i is capable of generating the following interrupt types:
•
•
•
•
•
•
•
1588 Time Stamp Interrupts (Port 2,1,0 and GPIO 9,8)
Switch Fabric Interrupts (Buffer Manager, Switch Engine, and Port 2,1,0 MACs)
Ethernet PHY Interrupts (Port 1,2 PHYs)
GPIO Interrupts (GPIO[11:0])
General Purpose Timer Interrupt (GPT)
Software Interrupt (General Purpose)
Device Ready Interrupt
All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure, as shown in
Figure 5-1. At the top level of the LAN9313/LAN9313i interrupt structure are the Interrupt Status Register (INT_STS),
Interrupt Enable Register (INT_EN), and Interrupt Configuration Register (IRQ_CFG).
The Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) aggregate and enable/disable all interrupts from the various LAN9313/LAN9313i sub-modules, combining them together to create the IRQ interrupt. These
registers provide direct interrupt access/configuration to the General Purpose Timer, software, and device ready interrupts. These interrupts can be monitored, enabled/disabled, and cleared, directly within these two registers. In addition,
interrupt event indications are provided for the 1588 Time Stamp, Switch Fabric, Port 1 & 2 Ethernet PHYs, and GPIO
interrupts. These interrupts differ in that the interrupt sources are generated and cleared in other sub-block registers.
The INT_STS register does not provide details on what specific event within the sub-module caused the interrupt, and
requires the software to poll an additional sub-module interrupt register (as shown in Figure 5-1) to determine the exact
interrupt source and clear it. For interrupts which involve multiple registers, only after the interrupt has been serviced
and cleared at its source will it be cleared in the INT_STS register.
The Interrupt Configuration Register (IRQ_CFG) is responsible for enabling/disabling the IRQ interrupt output pin as
well as configuring its properties. The IRQ_CFG register allows the modification of the IRQ pin buffer type, polarity, and
de-assertion interval. The de-assertion timer guarantees a minimum interrupt de-assertion period for the IRQ output and
is programmable via the INT_DEAS field of the Interrupt Configuration Register (IRQ_CFG). A setting of all zeros disables the de-assertion timer. The de-assertion interval starts when the IRQ pin de-asserts, regardless of the reason.
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LAN9313/LAN9313i
FIGURE 5-1:
FUNCTIONAL INTERRUPT REGISTER HIERARCHY
Top Level Interrupt Registers
(System CSRs)
INT_CFG
INT_STS
INT_EN
Bit 29 (1588_EVNT)
of INT_STS register
1588 Time Stamp Interrupt Register
1588_INT_STS_EN
Switch Fabric Interrupt Registers
Bit 28 (SWITCH_INT)
of INT_STS register
SW_IMR
SW_IPR
Buffer Manager Interrupt Registers
Bit 6 (BM)
of SW_IPR register
BM_IMR
BM_IPR
Switch Engine Interrupt Registers
Bit 5 (SWE)
of SW_IPR register
SWE_IMR
SWE_IPR
Port [2,1,0] MAC Interrupt Registers
Bits [2,1,0] (MAC_[2,1,MII])
of SW_IPR register
MAC_IMR_[2,1,MII]
MAC_IPR_[2,1,MII]
Port 2 PHY Interrupt Registers
Bit 27 (PHY_INT2)
of INT_STS register
PHY_INTERRUPT_SOURCE_2
PHY_INTERRUPT_MASK_2
Port 1 PHY Interrupt Registers
Bit 26 (PHY_INT1)
of INT_STS register
PHY_INTERRUPT_SOURCE_1
PHY_INTERRUPT_MASK_1
Bit 12 (GPIO)
of INT_STS register
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GPIO Interrupt Register
GPIO_INT_STS_EN
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LAN9313/LAN9313i
The following sections detail each category of interrupts and their related registers. Refer to Section 13.0, "Register
Descriptions," on page 124 for bit-level definitions of all interrupt registers.
5.2.1
1588 TIME STAMP INTERRUPTS
Multiple 1588 Time Stamp interrupt sources are provided by the LAN9313/LAN9313i. The top-level 1588_EVNT (bit 29)
of the Interrupt Status Register (INT_STS) provides indication that a 1588 interrupt event occurred in the 1588 Interrupt
Status and Enable Register (1588_INT_STS_EN).
The 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) provides enabling/disabling and status of all 1588
interrupt conditions. These include TX/RX 1588 clock capture indication on Ports 2,1,0, 1588 clock capture for
GPIO[8:9] events, as well as 1588 timer interrupt indication.
In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt event must be
enabled in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN), bit 29 (1588_EVNT_EN) of the Interrupt
Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the 1588 Time Stamp interrupts, refer to Section 10.6, "IEEE 1588 Interrupts," on page 118.
5.2.2
SWITCH FABRIC INTERRUPTS
Multiple Switch Fabric interrupt sources are provided by the LAN9313/LAN9313i in a three-tiered register structure as
shown in Figure 5-1. The top-level SWITCH_INT (bit 28) of the Interrupt Status Register (INT_STS) provides indication
that a Switch Fabric interrupt event occurred in the Switch Engine Interrupt Pending Register (SWE_IPR).
In turn, the Switch Engine Interrupt Pending Register (SWE_IPR) and Switch Engine Interrupt Mask Register
(SWE_IMR) provide status and enabling/disabling of all Switch Fabric sub-modules interrupts (Buffer Manager, Switch
Engine, and Port 2,1,0 MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager, Switch Engine,
and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-modules. These low-level registers
provide the following interrupt sources:
• Buffer Manager (Buffer Manager Interrupt Mask Register (BM_IMR) and Buffer Manager Interrupt Pending Register (BM_IPR))
- Status B Pending
- Status A Pending
• Switch Engine (Switch Engine Interrupt Mask Register (SWE_IMR) and Switch Engine Interrupt Pending Register (SWE_IPR))
- Interrupt Pending
• Port 2,1,0 MACs (Port x MAC Interrupt Mask Register (MAC_IMR_x) and Port x MAC Interrupt Pending Register
(MAC_IPR_x))
- No currently supported interrupt sources. These registers are reserved for future use.
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must be configured:
• The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask register (Buffer
Manager Interrupt Mask Register (BM_IMR) for the Buffer Manager, Switch Engine Interrupt Mask Register
(SWE_IMR) for the Switch Engine, and/or Port x MAC Interrupt Mask Register (MAC_IMR_x) for the Port 2,1,0
MACs)
• The desired Switch Fabric sub-module interrupt event must be enabled in the Switch Engine Interrupt Mask Register (SWE_IMR)
• Bit 28 (SWITCH_INT_EN) of the Interrupt Enable Register (INT_EN) must be set
• IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG)
For additional details on the Switch Fabric interrupts, refer to Section 6.6, "Switch Fabric Interrupts," on page 67.
5.2.3
ETHERNET PHY INTERRUPTS
The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1 (bit 26) and
PHY_INT2 (bit 27) of the Interrupt Status Register (INT_STS) provides indication that a PHY interrupt event occurred
in the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
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Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared via the Port x PHY Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x). The Port 1 and Port 2 PHYs are each capable of generating unique
interrupts based on the following events:
•
•
•
•
•
•
•
ENERGYON Activated
Auto-Negotiation Complete
Remote Fault Detected
Link Down (Link Status Negated)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event
must be enabled in the corresponding Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the
PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the Interrupt Enable Register (INT_EN) must be set, and
IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the Ethernet PHY interrupts, refer to Section 7.2.8.1, "PHY Interrupts," on page 78.
5.2.4
GPIO INTERRUPTS
Each GPIO[11:0] of the LAN9313/LAN9313i is provided with its own interrupt. The top-level GPIO (bit 12) of the Interrupt
Status Register (INT_STS) provides indication that a GPIO interrupt event occurred in the General Purpose I/O Interrupt
Status and Enable Register (GPIO_INT_STS_EN). The General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) provides enabling/disabling and status of each GPIO[11:0] interrupt.
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt must be enabled
in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN), bit 12 (GPIO_EN) of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the GPIO interrupts, refer to Section 12.2.2, "GPIO Interrupts," on page 121.
5.2.5
GENERAL PURPOSE TIMER INTERRUPT
A General Purpose Timer (GPT) interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt
Enable Register (INT_EN) (bit 19). This interrupt is issued when the General Purpose Timer Configuration Register
(GPT_CFG) wraps past zero to FFFFh, and is cleared when bit 19 of the Interrupt Status Register (INT_STS) is written
with 1.
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT must be enabled
via the bit 29 (TIMER_EN) in the General Purpose Timer Configuration Register (GPT_CFG), bit 19 of the Interrupt
Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the General Purpose Timer, refer to Section 11.1, "General Purpose Timer," on page 119.
5.2.6
SOFTWARE INTERRUPT
A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt
Enable Register (INT_EN). The SW_INT interrupt (bit 31) of the Interrupt Status Register (INT_STS) is generated when
SW_INT_EN (bit 31) of the Interrupt Enable Register (INT_EN) is set. This interrupt provides an easy way for software
to generate an interrupt, and is designed for general software usage.
5.2.7
DEVICE READY INTERRUPT
A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register
(INT_EN). The READY interrupt (bit 30) of the Interrupt Status Register (INT_STS) indicates that the
LAN9313/LAN9313i is ready to be accessed after a power-up or reset condition. Writing a 1 to this bit in the Interrupt
Status Register (INT_STS) will clear it.
In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the Interrupt Enable Register
(INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register
(IRQ_CFG).
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LAN9313/LAN9313i
6.0
SWITCH FABRIC
6.1
Functional Overview
At the core of the LAN9313/LAN9313i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch
fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames.
The switch fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple
packets while forwarding operations are completed, and a 1K entry forwarding table provides room for MAC address
forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and
shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the buffer manager
block within the switch fabric. All aspects of the switch fabric are managed via the switch fabric configuration and status
registers (CSR), which are indirectly accessible via the system control and status registers.
The switch fabric consists of four major block types:
• Switch Fabric CSRs - These registers provide access to various switch fabric parameters for configuration and
monitoring.
• 10/100 Ethernet MACs - A total of three MACs are included in the switch fabric which provide basic 10/100 Ethernet functionality for each switch fabric port.
• Switch Engine (SWE) - This block is the core of the switch fabric and provides VLAN layer 2 switching for all three
switch ports.
• Buffer Manager (BM) - This block provides control of the free buffer space, transmit queues, and scheduling.
Refer to FIGURE 2-1: Internal LAN9313/LAN9313i Block Diagram on page 8 for details on the interconnection of the
switch fabric blocks within the LAN9313/LAN9313i.
6.2
Switch Fabric CSRs
The switch fabric CSRs provide register level access to the various parameters of the switch fabric. Switch fabric related
registers can be classified into two main categories based upon their method of access: direct and indirect.
The directly accessible switch fabric registers are part of the main system CSRs of the LAN9313/LAN9313i and are
detailed in Section 13.1.5, "Switch Fabric," on page 150. These registers provide switch fabric manual flow control
(Ports 0-2), data/command registers (for access to the indirect switch fabric registers), and switch MAC address configuration.
The indirectly accessible switch fabric registers reside within the switch fabric and must be accessed indirectly via the
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) and Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD), or the set of Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA). The indirectly accessible switch fabric CSRs provide full access to the many configurable parameters of the
switch engine, buffer manager, and each switch port. The switch fabric CSRs are detailed in Section 13.3, "Switch Fabric
Control and Status Registers," on page 189.
For detailed descriptions of all switch fabric related registers, refer to Section 13.0, "Register Descriptions," on
page 124.
6.2.1
SWITCH FABRIC CSR WRITES
To perform a write to an individual switch fabric register, the desired data must first be written into the Switch Fabric CSR
Interface Data Register (SWITCH_CSR_DATA). The write cycle is initiated by performing a single write to the Switch
Fabric CSR Interface Command Register (SWITCH_CSR_CMD) with CSR_BUSY (bit 31) set, the CSR_ADDRESS
field (bits 15:0) set to the desired register address, the R_nW (bit 30) cleared, the AUTO_INC and AUTO_DEC fields
cleared, and the desired CSR byte enable bits selected (bits 19:16). The completion of the write cycle is indicated by
the clearing of the CSR_BUSY bit.
A second write method may be used which utilizes the auto increment/decrement function of the Switch Fabric CSR
Interface Command Register (SWITCH_CSR_CMD) for writing sequential register addresses. When using this method,
the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) must first be written with the auto increment(AUTO_INC) or auto decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register
address, the R_nW bit cleared, and the desired CSR byte enable bits selected (typically all set). The write cycles are
then initiated by writing the desired data into the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA).
The completion of the write cycle is indicated by the clearing of the CSR_BUSY bit, at which time the address in the
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LAN9313/LAN9313i
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) is incremented or decremented accordingly.
The user may then initiate a subsequent write cycle by writing the desired data into the Switch Fabric CSR Interface
Data Register (SWITCH_CSR_DATA).
The third write method is to use the direct data range write function. Writes within the Switch Fabric CSR Interface Direct
Data Register (SWITCH_CSR_DIRECT_DATA) address range automatically set the appropriate register address, set
all four byte enable bits (CSR_BE[3:0]), clears the R_nW bit, and sets the CSR_BUSY bit of the Switch Fabric CSR
Interface Command Register (SWITCH_CSR_CMD). The completion of the write cycle is indicated by the clearing of
the CSR_BUSY bit. Since the address range of the switch fabric CSRs exceeds that of the Switch Fabric CSR Interface
Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range, a sub-set of the switch fabric CSRs are mapped
to the Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range as detailed in
Table 13-3, “Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map,” on page 158.
Figure 6-1 illustrates the process required to perform a switch fabric CSR write.
FIGURE 6-1:
SWITCH FABRIC CSR WRITE ACCESS FLOW DIAGRAM
CSR Write
CSR Write Auto
Increment /
Decrement
Idle
Idle
Idle
Write Data
Register
Write
Command
Register
Write
Direct
Data
Register
Range
Write
Command
Register
Write Data
Register
CSR Write Direct
Address
CSR_BUSY = 0
Read
Command
Register
CSR_BUSY = 1
CSR_BUSY = 0
Read
Command
Register
CSR_BUSY = 0
CSR_BUSY = 1
6.2.2
Read
Command
Register
CSR_BUSY = 1
SWITCH FABRIC CSR READS
To perform a read of an individual switch fabric register, the read cycle must be initiated by performing a single write to
the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) with CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the desired register address, the R_nW (bit 30) set, and the AUTO_INC and AUTO_DEC
fields cleared. Valid data is available for reading when the CSR_BUSY bit is cleared, indicating that the data can be read
from the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA).
A second read method may be used which utilizes the auto increment/decrement function of the Switch Fabric CSR
Interface Command Register (SWITCH_CSR_CMD) for reading sequential register addresses. When using this
method, the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) must first be written with the auto
increment(AUTO_INC) or auto decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address, and the R_nW bit set. The completion of a read cycle is indicated by the clearing of the CSR_BUSY bit,
at which time the data can be read from the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA). When
the data is read, the address in the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) is incremented or decremented accordingly, and another read cycle is started automatically. The user should clear the
AUTO_INC and AUTO_DEC bits before reading the last data to avoid an unintended read cycle.
DS00002288A-page 46
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LAN9313/LAN9313i
Figure 6-2 illustrates the process required to perform a switch fabric CSR read.
FIGURE 6-2:
SWITCH FABRIC CSR READ ACCESS FLOW DIAGRAM
CSR Read
CSR Read Auto
Increment /
Decrement
Idle
Idle
Write
Command
Register
Write
Command
Register
CSR_BUSY = 1
Read
Command
Register
CSR_BUSY = 0
Read Data
Register
CSR_BUSY = 1
Read
Command
Register
CSR_BUSY = 0
last
data?
No
Read Data
Register
Yes
Write
Command
Register
Read Data
Register
6.2.3
FLOW CONTROL ENABLE LOGIC
Each switch fabric port (0,1,2) is provided with two flow control enable inputs per port, one for transmission and one for
reception. Flow control on transmission allows the transmitter to generate back pressure in half-duplex mode, and pause
packets in full-duplex. Flow control in reception enables the reception of pause packets to pause transmissions.
The state of these enables is based on the state of the ports duplex and Auto-negotiation settings and the values of the
corresponding Manual Flow Control register (Port 1 Manual Flow Control Register (MANUAL_FC_1), Port 2 Manual
Flow Control Register (MANUAL_FC_2), or Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII)).
Figure 6-1 details the switch fabric flow control enable logic.
When in half-duplex mode, the transmit flow control (back pressure) enable is determined directly by the BP_EN_x bit
of the ports manual flow control register. When Auto-negotiation is disabled, or the MANUAL_FC_x bit of the ports manual flow control register is set, the switch port flow control enables during full-duplex are determined by the TX_FC_x
and RX_FC_x bits of the ports manual flow control register. When Auto-negotiation is enabled and the MANUAL_FC_x
bit is cleared, the switch port flow control enables during full-duplex are determined by Auto-negotiation.
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The flow control values in the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) and
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) are not affected by the values of
the manual flow control register. Refer to Section 7.2.5.1, "PHY Pause Flow Control," on page 76 and Section 7.3.1.3, "Virtual PHY Pause Flow Control," on page 81 for additional information on PHY and Virtual
PHY flow control settings respectively.
TX FLOW CONTROL
ENABLE
X
TX_FC_x
X
X
RX_FC_x
TX_FC_x
LP PAUSE
ABILITY
(Note 6-2)
X
AN ASYM PAUSE
ADVERTISEMENT
(Note 6-2)
BP_EN_x
AN PAUSE
ADVERTISEMENT
(Note 6-2)
0
RX_FC_x
DUPLEX
X
LP AN ABLE
BP_EN_x
AN COMPLETE
0
AN ENABLE
X
MANUAL_FC_X
RX FLOW CONTROL
ENABLE
SWITCH FABRIC FLOW CONTROL ENABLE LOGIC
CASE
TABLE 6-1:
LP ASYM PAUSE
ABILITY
(Note 6-2)
Note:
-
1
X
X
X
Half
X
X
X
-
X
0
X
X
Half
X
X
X
-
1
X
X
X
Full
X
X
-
X
0
X
X
Full
X
X
1
0
1
0
X
X
X
X
X
X
0
0
2
0
1
1
0
Half (Note 6-1)
X
X
X
X
0
BP_EN_x
3
0
1
1
1
Half
X
X
X
X
0
BP_EN_x
4
0
1
1
1
Full
0
0
X
X
0
0
5
0
1
1
1
Full
0
1
0
X
0
0
6
0
1
1
1
Full
0
1
1
0
0
0
7
0
1
1
1
Full
0
1
1
1
0
1
8
0
1
1
1
Full
1
0
0
X
0
0
9
0
1
1
1
Full
1
X
1
X
1
1
10
0
1
1
1
Full
1
1
0
0
0
0
11
0
1
1
1
Full
1
1
0
1
1
0
Note 6-1
If Auto-negotiation is enabled and complete, but the link partner is not Auto-negotiation capable, halfduplex is forced via the parallel detect function.
Note 6-2
For the Port 1 and Port 2 PHYs, these are the bits from the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) and Port x PHY Auto-Negotiation Link Partner Base Page
Ability Register (PHY_AN_LP_BASE_ABILITY_x). For the Virtual PHY, these are the local/partner
swapped outputs from the bits in the Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV) and Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY). Refer to Section 7.3.1, "Virtual PHY Auto-Negotiation," on page 79
for more information.
Per Figure 6-1, the following cases are possible:
• Case 1 - Auto-negotiation is still in progress. Since the result is not yet established, flow control is disabled.
• Case 2 - Auto-negotiation is enabled and unsuccessful (link partner not Auto-negotiation capable). The link partner ability is undefined, effectively a don’t-care value, in this case. The duplex setting will default to half-duplex in
this case. Flow control is determined by the BP_EN_x bit.
• Case 3 - Auto-negotiation is enabled and successful with half-duplex as a result. The link partner ability is undefined since it only applies to full-duplex operation. Flow control is determined by the BP_EN_x bit.
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• Cases 4-11 -Auto-negotiation is enabled and successful with full-duplex as the result. In these cases, the advertisement registers and the link partner ability controls the RX and TX enables. These cases match IEEE 802.3
Annex 28B.3.
• Cases 4,5,6,8,10 - No flow control enabled
• Case 7 - Asymmetric pause towards partner (away from switch port)
• Case 9 - Symmetric pause
• Case 11 - Asymmetric pause from partner (towards switch port)
6.3
10/100 Ethernet MACs
The switch fabric contains three 10/100 MAC blocks, one for each switch port (0,1,2). The 10/100 MAC provides the
basic 10/100 Ethernet functionality, including transmission deferral and collision back-off/retry, receive/transmit FCS
checking and generation, receive/transmit pause flow control, and transmit back pressure. The 10/100 MAC also
includes RX and TX FIFOs and per port statistic counters.
6.3.1
RECEIVE MAC
The receive MAC (IEEE 802.3) sublayer decomposes Ethernet packets acquired via the internal MII interface by stripping off the preamble sequence and Start of Frame Delimiter (SFD). The receive MAC checks the FCS, the MAC Control
Type, and the byte count against the drop conditions. The packet is stored in the RX FIFO as it is received.
The receive MAC determines the validity of each received packet by checking the Type field, FCS, and oversize or
undersize conditions. All bad packets will be either immediately dropped or marked (at the end) as bad packets.
Oversized packets are normally truncated at 1519 or 1523 (VLAN tagged) octets and marked as erroneous. The MAC
can be configured to accept packets up to 2048 octets (inclusive), in which case the oversize packets are truncated at
2048 bytes and marked as erroneous.
Undersized packets are defined as packets with a length less than the minimum packet size. The minimum packet size
is defined to be 64 bytes, exclusive of preamble sequence and SFD.
The FCS and length/type fields of the frame is checked to detect if the packet has a valid MAC control frame. When the
MAC receives a MAC control frame with a valid FCS and determines the operation code is a pause command (Flow
Control frame), the MAC will load its internal pause counter with the Number_of_Slots variable from the MAC control
frame just received. Anytime the internal pause counter is zero, the transmit MAC will be allowed to transmit (XON). If
the internal pause counter is not zero, the receive MAC will not allow the transmit MAC to transmit (XOFF). When the
transmit MAC detects an XOFF condition it will continue to transmit the current packet, terminating transmission after
the current packet has been transmitted until receiving the XON condition from the receive MAC. The pause counter will
begin to decrement at then end of the current transmission, or immediately if no transmission is underway. If another
pause command is received while the transmitter is already in pause, the new pause time indicated by the Flow Control
packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as
discussed in Section 6.2.3, "Flow Control Enable Logic," on page 47. Pause frames are consumed by the MAC and not
sent to the switch engine. Non-pause control frames are optionally filtered or forwarded.
When the receive FIFO is full and additional data continues to be received, an overrun condition occurs and the frame
is discarded (FIFO space recovered) or marked as a bad frame.
The receive MAC can be disabled from receiving all frames by clearing the RX Enable bit of the Port x MAC Receive
Configuration Register (MAC_RX_CFG_x).
The size of the RX FIFO is 256 bytes. If a bad packet with less than 64 bytes is received, it will be flushed from the FIFO
automatically and the FIFO space recovered. Packets equal to or larger than 64 bytes with an error will be marked and
reported to the switch engine. The switch engine will subsequently drop the packet.
6.3.1.1
Receive Counters
The receive MAC gathers statistics on each packet and increments the related counter registers. The following receive
counters are supported for each switch fabric port. Refer to Table 13-12, “Indirectly Accessible Switch Control and Status Registers,” on page 189 and Section 13.3.2.3 through Section 13.3.2.22 for detailed descriptions of these counters.
•
•
•
•
•
Total undersized packets (Section 13.3.2.3, on page 200)
Total packets 64 bytes in size (Section 13.3.2.4, on page 200)
Total packets 65 through 127 bytes in size (Section 13.3.2.5, on page 201)
Total packets 128 through 255 bytes in size (Section 13.3.2.6, on page 201)
Total packets 256 through 511 bytes in size (Section 13.3.2.7, on page 202)
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Total packets 512 through 1023 bytes in size (Section 13.3.2.8, on page 202)
Total packets 1024 through maximum bytes in size (Section 13.3.2.9, on page 203)
Total oversized packets (Section 13.3.2.10, on page 203)
Total OK packets (Section 13.3.2.11, on page 204)
Total packets with CRC errors (Section 13.3.2.12, on page 204)
Total multicast packets (Section 13.3.2.13, on page 204)
Total broadcast packets (Section 13.3.2.14, on page 205)
Total MAC Pause packets (Section 13.3.2.15, on page 205)
Total fragment packets (Section 13.3.2.16, on page 205)
Total jabber packets (Section 13.3.2.17, on page 206)
Total alignment errors (Section 13.3.2.18, on page 206)
Total bytes received from all packets (Section 13.3.2.19, on page 207)
Total bytes received from good packets (Section 13.3.2.20, on page 207)
Total packets with a symbol error (Section 13.3.2.21, on page 208)
Total MAC control packets (Section 13.3.2.22, on page 208)
6.3.2
TRANSMIT MAC
The transmit MAC generates an Ethernet MAC frame from TX FIFO data. This includes generating the preamble and
SFD, calculating and appending the frame checksum value, optionally padding undersize packets to meet the minimum
packet requirement size (64 bytes), and maintaining a standard inter-frame gap time during transmit.
The transmit MAC can operate at 10/100Mbps, half- or full-duplex, and with or without flow control depending on the
state of the transmission. In half-duplex mode the transmit MAC meets CSMA/CD IEEE 802.3 requirements. The transmit MAC will re-transmit if collisions occur during the first 64 bytes (normal collisions), or will discard the packet if collisions occur after the first 64 bytes (late collisions). The transmit MAC follows the standard truncated binary exponential
back-off algorithm, collision and jamming procedures.
The transmit MAC pre-pends the standard preamble and SFD to every packet from the FIFO. The transmit MAC also
follows as default, the standard Inter-Frame Gap (IFG). The default IFG is 96 bit times and can be adjusted via the IFG
Config field of the Port x MAC Transmit Configuration Register (MAC_TX_CFG_x).
Packet padding and cyclic redundant code (FCS) calculation may be optionally performed by the transmit MAC. The
auto-padding process automatically adds enough zeros to packets shorter than 64 bytes. The auto-padding and FCS
generation is controlled via the TX Pad Enable bit of the Port x MAC Transmit Configuration Register (MAC_TX_CFG_x).
The transmit FIFO acts as a temporary buffer between the transmit MAC and the switch engine. The FIFO logic manages the re-transmission for normal collision conditions or discards the frames for late or excessive collisions.
When in full-duplex mode, the transmit MAC uses the flow-control algorithm specified in IEEE 802.3. MAC pause frames
are used primarily for flow control packets, which pass signalling information between stations. MAC pause frames have
a unique type of 8808h, and a pause op-code of 0001h. The MAC pause frame contains the pause value in the data
field. The flow control manager will auto-adapt the procedure based on traffic volume and speed to avoid packet loss
and unnecessary pause periods.
When in half-duplex mode, the MAC uses a back pressure algorithm. The back pressure algorithm is based on a forced
collision and an aggressive back-off algorithm.
6.3.2.1
Transmit Counters
The transmit MAC gathers statistics on each packet and increments the related counter registers. The following transmit
counters are supported for each switch fabric port. Refer to Table 13-12, “Indirectly Accessible Switch Control and Status Registers,” on page 189 and Section 13.3.2.25 through Section 13.3.2.42 for detailed descriptions of these counters.
•
•
•
•
•
•
Total packets deferred (Section 13.3.2.25, on page 209)
Total pause packets (Section 13.3.2.26, on page 210)
Total OK packets (Section 13.3.2.27, on page 210)
Total packets 64 bytes in size (Section 13.3.2.28, on page 210)
Total packets 65 through 127 bytes in size (Section 13.3.2.29, on page 211)
Total packets 128 through 255 bytes in size (Section 13.3.2.30, on page 211)
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•
•
•
•
•
•
•
•
•
•
•
•
Total packets 256 through 511 bytes in size (Section 13.3.2.31, on page 211)
Total packets 512 through 1023 bytes in size (Section 13.3.2.32, on page 212)
Total packets 1024 through maximum bytes in size (Section 13.3.2.33, on page 212)
Total undersized packets (Section 13.3.2.34, on page 212)
Total bytes transmitted from all packets (Section 13.3.2.35, on page 213)
Total broadcast packets (Section 13.3.2.36, on page 213)
Total multicast packets (Section 13.3.2.37, on page 213)
Total packets with a late collision (Section 13.3.2.38, on page 214)
Total packets with excessive collisions (Section 13.3.2.39, on page 214)
Total packets with a single collision (Section 13.3.2.40, on page 214)
Total packets with multiple collisions (Section 13.3.2.41, on page 215)
Total collision count (Section 13.3.2.42, on page 215)
6.4
Switch Engine (SWE)
The switch engine (SWE) is a VLAN layer 2 (link layer) switching engine supporting 3 ports. The SWE supports the following types of frame formats: untagged frames, VLAN tagged frames, and priority tagged frames. The SWE supports
both the 802.3 and Ethernet II frame formats.
The SWE provides the control for all forwarding/filtering rules. It handles the address learning and aging, and the destination port resolution based upon the MAC address and VLAN of the packet. The SWE implements the standard bridge
port states for spanning tree and provides packet metering for input rate control. It also implements port mirroring, broadcast throttling, and multicast pruning and filtering. Packet priorities are supported based on the IPv4 TOS bits and IPv6
Traffic Class bits using a DIFFSERV Table mapping, the non-DIFFSERV mapped IPv4 precedence bits, VLAN priority
using a per port Priority Regeneration Table, DA based static priority, and Traffic Class mapping to one of 4 QoS transmit
priority queues.
The following sections detail the various features of the switch engine.
6.4.1
MAC ADDRESS LOOKUP TABLE
The Address Logic Resolution (ALR) maintains a 1024 entry MAC Address Table. The ALR searches the table for the
destination MAC address. If the search finds a match, the associated data is returned indicating the destination port or
ports, whether to filter the packet, the packets priority (used if enabled), and whether to override the ingress and egress
spanning tree port state. Figure 6-3 displays the ALR table entry structure. Refer to the Switch Engine ALR Write Data
0 Register (SWE_ALR_WR_DAT_0) and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) for
detailed descriptions of these bits.
FIGURE 6-3:
ALR TABLE ENTRY STRUCTURE
56
55
54
53
Valid
Age /
Override
Static
Filter
Bit
6.4.1.1
52
51
Priority
50
49
48
Port
47
...
0
MAC Address
Learning/Aging/Migration
The ALR adds new MAC addresses upon ingress along with the associated receive port.
If the source MAC address already exists, the entry is refreshed. This action serves two purposes. First, if the source
port has changed due to a network reconfiguration (migration), it is updated. Second, each instance the entry is
refreshed, the aging status bit is set, keeping the entry active. Learning can be disabled per port via the Enable Learning
on Ingress field of the Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG).
During each aging period, the ALR scans the learned MAC addresses. For entries which have the aging status bit set,
the ALR simply clears the bit. As mentioned above, if a MAC address is subsequently refreshed, the aging bit will be
set again and the process would repeat. If a learned entry already had its aging status bit cleared (by a previous scan),
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the ALR will instead remove the learned entry. Therefore, if two scans occur before a MAC address is refreshed, the
entry will be aged and removed. Each aging period is approximately 5 minutes. Therefore an entry will be aged and
removed at a minimum of 5 minutes, and a maximum of 10 minutes.
6.4.1.2
Static Entries
If a MAC address entry is manually added by the host CPU, it can be (and typically is) marked as static. Static entries
are not subjected to the aging process. Static entries also cannot be changed by the learning process (including migration).
6.4.1.3
Multicast Pruning
The destination port that is returned as a result of a destination MAC address lookup may be a single port or any combination of ports. The latter is used to setup multicast address groups. An entry with a multicast MAC address would be
entered manually by the host CPU with the appropriate destination port(s). Typically, the Static bit should also be set to
prevent automatic aging of the entry.
6.4.1.4
Address Filtering
Filtering can be performed on a destination MAC address. Such an entry would be entered manually by the host CPU
with the Filter bit active. Typically, the Static bit should also be set to prevent automatic aging of the entry.
6.4.1.5
Spanning Tree Port State Override
A special spanning tree port state override setting can be applied to MAC address entries. When the host CPU manually
adds an entry with both the Static and Age bits set, packets with a matching destination address will bypass the spanning
tree port state and will be forwarded. This feature is typically used to allow the reception of the BPDU packets while a
port is in the non-forwarding state. Refer to Section 6.4.5, "Spanning Tree Support," on page 57 for additional details.
6.4.1.6
MAC Destination Address Lookup Priority
If enabled in the Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG), the transmit
priority for static MAC address entries is taken from the associated data of that entry.
6.4.1.7
Host Access
The ALR contains a learning engine that is used by the host CPU to add, delete, and modify the MAC Address Table.
This engine is accessed by using the Switch Engine ALR Command Register (SWE_ALR_CMD), Switch Engine ALR
Command Status Register (SWE_ALR_CMD_STS), Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0), and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1).
The following procedure should be followed in order to add, delete, and modify the ALR entries:
1.
Write the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and Switch Engine ALR Write Data
1 Register (SWE_ALR_WR_DAT_1) with the desired MAC address and control bits.
Note:
2.
3.
4.
An entry can be deleted by setting the Valid and Static bits to 0.
Write the Switch Engine ALR Command Register (SWE_ALR_CMD) register with 0004h (Make Entry)
Poll the Make Pending bit in the Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) until it
is cleared.
Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0000h.
The ALR contains a search engine that is used by the host to read the MAC Address Table. This engine is accessed by
using the Switch Engine ALR Command Register (SWE_ALR_CMD), Switch Engine ALR Read Data 0 Register
(SWE_ALR_RD_DAT_0), and Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1).
Note:
The entries read are not necessarily in the same order as they were learned or manually added.
The following procedure should be followed in order to read the ALR entries:
1.
2.
Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0002h (Get First Entry).
Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0000h (Clear the Get First Entry Bit)
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3.
4.
5.
6.
7.
8.
Poll the Valid and End of Table bits in the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
until either are set.
If the Valid bit is set, then the entry is valid and the data from the Switch Engine ALR Read Data 0 Register
(SWE_ALR_RD_DAT_0) and Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) can be stored.
If the End of Table bit is set, then exit.
Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0001h (Get Next Entry).
Write the Switch Engine ALR Command Register (SWE_ALR_CMD) with 0000h (Clear the Get Next Entry bit)
Go to step 3.
Note:
6.4.2
Refer to Section 13.3.3.1, on page 216 through Section 13.3.3.6, on page 220 for detailed definitions of
these registers.
FORWARDING RULES
Upon ingress, packets are filtered or forwarded based on the following rules:
• If the destination port equals the source port (local traffic), the packet is filtered.
• If the source port is not in the forwarding state, the packet is filtered (unless the Spanning Tree Port State Override
is in effect).
• If the destination port is not in the forwarding state, the packet is filtered (unless the Spanning Tree Port State
Override is in effect).
• If the Filter bit for the Destination Address is set in the ALR table, the packet is filtered.
• If the packet has a unicast destination MAC address which is not found in the ALR table and the Drop Unknown bit
is set, the packet is filtered.
• If the packet has a multicast destination MAC address which is not found in the ALR table and the Filter Multicast
bit is set, the packet is filtered.
• If the packet has a broadcast destination MAC address and the Broadcast Storm Control level has been reached,
the packet is discarded.
• If Drop on Yellow is set, the packet is colored Yellow, and randomly selected, it is discarded.
• If Drop on Red is set and the packet is colored Red, it is discarded.
• If the destination address was not found in the ALR table (an unknown or a broadcast) and the Broadcast Buffer
Level is exceeded, the packet is discarded.
• If there is insufficient buffer space, the packet is discarded.
When the switch is enabled for VLAN support, these following rules also apply:
• If the packet is untagged or priority tagged and the Admit Only VLAN bit for the ingress port is set, the packet is filtered.
• If the packet is tagged and has a VID equal to FFFh, it is filtered.
• If Enable Membership Checking on Ingress is set, Admit Non Member is cleared, and the source port is not a
member of the incoming VLAN, the packet is filtered.
• If Enable Membership Checking on Ingress is set and the destination port is not a member of the incoming VLAN,
the packet is filtered.
• If the destination address was not found in the ALR table (as unknown or broadcast) and the VLAN broadcast
domain containment resulted in zero valid destination ports, the packet is filtered.
Note:
6.4.3
For the last three cases, if the VID is not in the VLAN table, the VLAN is considered foreign and the membership result is NULL. A NULL membership will result in the packet being filtered if Enable Membership
Checking is set. A NULL membership will also result in the packet being filtered if the destination address
is not found in the ALR table (since the packet would have no destinations).
TRANSMIT PRIORITY QUEUE SELECTION
The transmit priority queue may be selected from five options. As shown in Figure 6-4, the priority may be based on:
• the static value for the destination address in the ALR table
• the precedence bits in the IPv4 TOS octet
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• the DIFFSERV mapping table indexed by the IPv4 TOS octet or the IPv6 Traffic Class octet
• the VLAN tag priority field using the per port Priority Regeneration table
• the port default
The last four options listed are sent through the Traffic Class table which maps the selected priority to one of the four
output queues. The static value from the ALR table directly specifies the queue.
FIGURE 6-4:
SWITCH ENGINE TRANSMIT QUEUE SELECTION
Packet is from Host
Packet is Tagged
Packet is IPv 4
Packet is IP
VL Higher Priority
Use Precedence
Use IP
VLAN Enable
IPv4(TOS)
IPv6(TC)
6b
programmable
DIFFSERV table
3b
IPv4 Precedence
3b
Source Port
VLAN Priority
ALR Static Bit
DA Highest Priority
3b
2b
3b
ALR Priority
programmable
port default
table
priority
calculation
programmable
Traffic Class
table
static DA
override
2b
priority queue
3b
programmable
Priority
Regeneration
table
per port
2b
The transmit queue priority is based on the packet type and device configuration as shown in Figure 6-5. Refer to Section 13.3.3.16, "Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)," on page 225
for definitions of the configuration bits.
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FIGURE 6-5:
SWITCH ENGINE TRANSMIT QUEUE CALCULATION
Get Queue
Packet from Host
Y
N
DA Highest
Priority
N
Y
wait for ALR result
Y
ALR Static Bit
N
N
VL Higher
Priority
Y
VLAN Enable &
Packet is
Tagged
Y
N
Y
Packet is IPv 4/v6
& Use IP
N
Y
Packet is IPv 4
N
Y
Use Precedence
Resolved Priority =
IP Precedence
VLAN Enable &
Packet is
Tagged
Y
N
N
Resolved Priority =
DIFFSERV[TOS]
Queue =
ALR Priority
Resolved Priority =
DIFFSERV[TC]
Resolved Priority =
Default Priority[Source
Port]
Resolved Priority =
Priority Regen[VLAN
Priority]
Queue =
Traffic Class[Resolved Priority]
Get Queue Done
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6.4.3.1
Port Default Priority
As detailed in Figure 6-5, the default priority is based on the ingress ports priority bits in its port VID value. The PVID
table is read and written by using the Switch Engine VLAN Command Register (SWE_VLAN_CMD), Switch Engine
VLAN Write Data Register (SWE_VLAN_WR_DATA), Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA), and Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS). Refer to Section 13.3.3.8, on
page 221 through Section 13.3.3.11, on page 224 for detailed VLAN register descriptions.
6.4.3.2
IP Precedence Based Priority
The transmit priority queue can be chosen based on the Precedence bits of the IPv4 TOS octet. This is supported for
tagged and non-tagged packets for both type field and length field encapsulations. The Precedence bits are the three
most significant bits of the IPv4 TOS octet.
6.4.3.3
DIFFSERV Based Priority
The transmit priority queue can be chosen based on the DIFFSERV usage of the IPv4 TOS or IPv6 Traffic Class octet.
This is supported for tagged and non-tagged packets for both type field and length field encapsulations.
The DIFFSERV table is used to determine the packet priority from the 6-bit Differentiated Services (DS) field. The DS
field is defined as the six most significant bits of the IPv4 TOS octet or the IPv6 Traffic Class octet and is used as an
index into the DIFFSERV table. The output of the DIFFSERV table is then used as the priority. This priority is then
passed through the Traffic Class table to select the transmit priority queue.
Note:
The DIFFSERV table is not initialized upon reset or power-up. If DIFFSERV is enabled, then the full table
must be initialized by the host.
The DIFFSERV table is read and written by using the Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG), Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA), Switch
Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA), and Switch Engine DIFFSERV
Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS). Refer to Section 13.3.3.12, on page 224 through
Section 13.3.3.15, on page 225 for detailed DIFFSERV register descriptions.
6.4.3.4
VLAN Priority
As detailed in Figure 6-5, the transmit priority queue can be taken from the priority field of the VLAN tag. The VLAN
priority is sent through a per port Priority Regeneration table, which is used to map the VLAN priority into a user defined
priority.
The Priority Regeneration table is programmed by using the Switch Engine Port 0 Ingress VLAN Priority Regeneration
Table Register (SWE_INGRSS_REGEN_TBL_MII), Switch Engine Port 1 Ingress VLAN Priority Regeneration Table
Register (SWE_INGRSS_REGEN_TBL_1), and Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2). Refer to Section 13.3.3.33, on page 234 through Section 13.3.3.35, on
page 235 for detailed descriptions of these registers.
6.4.4
VLAN SUPPORT
The switch engine supports 16 active VLANs out of a possible 4096. The VLAN table contains the 16 active VLAN
entries, each consisting of the VID, the port membership, and un-tagging instructions.
TABLE 6-2:
VLAN TABLE ENTRY STRUCTURE
17
16
15
14
13
12
Member
Port 2
Un-tag
Port 2
Member
Port 1
Un-tag
Port 1
Member
MII
Un-tag
MII
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11
...
0
VID
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On ingress, if a packet has a VLAN tag containing a valid VID (not 000h or FFFh), the VID table is searched. If the VID
is found, the VLAN is considered active and the membership and un-tag instruction is used. If the VID is not found, the
VLAN is considered foreign and the membership result is NULL. A NULL membership will result in the packet being
filtered if Enable Membership Checking is set. A NULL membership will also result in the packet being filtered if the destination address is not found in the ALR table (since the packet would have no destinations).
On ingress, if a packet does not have a VLAN tag or if the VLAN tag contains VID with a value of 0 (priority tag), the
packet is assigned a VLAN based on the Port Default VID (PVID) and Priority. The PVID is then used to access the
above VLAN table.
The VLAN membership of the packet is used for ingress and egress checking and for VLAN broadcast domain containment. The un-tag instructions are used at egress on ports defined as hybrid ports.
Refer to Section 13.3.3.8, on page 221 through Section 13.3.3.11, on page 224 for detailed VLAN register descriptions.
6.4.5
SPANNING TREE SUPPORT
Hardware support for the Spanning Tree Protocol (STP) and the Rapid Spanning Tree Protocol (RSTP) includes a per
port state register as well as the override bit in the MAC Address Table entries (Section 6.4.1.5, on page 52) and the
host CPU port special tagging (Section 6.4.10, on page 61).
The Switch Engine Port State Register (SWE_PORT_STATE) is used to place a port into one of the modes as shown
in Table 6-3. Normally only Port 1 and Port 2 are placed into modes other than forwarding. Port 0 should normally be
left in forwarding mode.
TABLE 6-3:
Port State
SPANNING TREE STATES
Hardware Action
01 - Blocking (also Received packets on the port are
used for disabled) discarded.
Transmissions to the port are blocked.
Learning on the port is disabled.
Software Action
The MAC Address Table should be programmed with
entries that the host CPU needs to receive (e.g. the
BPDU address). The static and override bits should
be set.
The host CPU should not send any packets to the
port in this state.
The host CPU should discard received packets from
this port when in the Disabled state.
Note:
11 - Listening
Received packets on the port are
discarded.
Transmissions to the port are blocked.
10 - Learning
The MAC Address Table should be programmed with
entries that the host CPU needs to receive (e.g. the
BPDU address). The static and override bits should
be set.
Learning on the port is disabled.
The host CPU may send packets to the port in this
state.
Received packets on the port are
discarded.
The MAC Address Table should be programmed with
entries that the host CPU needs to receive (e.g. the
BPDU address). The static and override bits should
be set.
Transmissions to the port are blocked.
00 - Forwarding
There is no hardware distinction between
the Blocking and Disabled states.
Learning on the port is enabled.
The host CPU may send packets to the port in this
state.
Received packets on the port are
forwarded normally.
The MAC Address Table should be programmed with
entries that the host CPU needs to receive (e.g. the
BPDU address). The static and override bits should
be set.
Transmissions to the port are sent
normally.
Learning on the port is enabled.
2008-2016 Microchip Technology Inc.
The host CPU may send packets to the port in this
state.
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6.4.6
INGRESS FLOW METERING AND COLORING
The LAN9313/LAN9313i supports hardware ingress rate limiting by metering packet streams and marking packets as
either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR), Committed Burst
Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not exceed the CBS, Yellow if it exceeds
to CBS but not the EBS, or Red otherwise.
Ingress flow metering and coloring is enabled via the Ingress Rate Enable bit in the Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG). Once enabled, each incoming packet is classified into a stream.
Streams are defined as per port (3 streams), per priority (8 streams), or per port & priority (24 streams) as selected via
the Rate Mode bits in the Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG). Each
stream can have a different CIR setting. All streams share common CBS and EBS settings. CIR, CBS, and EBS are
programmed via the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD) and Switch Engine
Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA).
Each stream is metered according to RFC 2697. At the rate set by the CIR, two token buckets are credited per stream.
First, the Committed Burst bucket is incremented up to the maximum set by the CBS. Once the Committed Burst bucket
is full, the Excess Burst bucket is incremented up to the maximum set by the EBS. The CIR rate is specified in time per
byte. The value programmed is in approximately 20 nS per byte increments. Typical values are listed in Table 6-4. When
a port is receiving at 10Mbps, any setting faster than 39 has the effect of not limiting the rate.
TABLE 6-4:
TYPICAL INGRESS RATE SETTINGS
CIR Setting
Time Per Byte
Bandwidth
0-3
80 nS
100 Mbps
4
100 nS
80 Mbps
5
120 nS
67 Mbps
6
140 nS
57 Mbps
7
160 nS
50 Mbps
9
200 nS
40 Mbps
12
260 nS
31 Mbps
19
400 nS
20 Mbps
39
800 nS
10 Mbps
79
1600 nS
5 Mbps
160
3220 nS
2.5 Mbps
402
8060 nS
1 Mbps
804
16100 nS
500 Kbps
1610
32220 nS
250 Kbps
4028
80580 nS
100 Kbps
8056
161140 nS
50 Kbps
After each packet is received, the bucket is decremented. If the Committed Burst bucket has sufficient tokens, it is debited and the packet is colored Green. If the Committed Burst bucket lacks sufficient tokens for the packet, the Excess
Burst bucket is checked. If the Excess Burst bucket has sufficient tokens, it is debited, the packet is colored Yellow and
is subjected to random discard. If the Excess Burst bucket lacks sufficient tokens for the packet, the packet is colored
Red and is discarded.
Note:
All of the token buckets are initialized to the default value of 1536. If lower values are programmed into the
CBS and EBS parameters, the token buckets will need to be normally depleted below these values before
the values have any affect on limiting the maximum value of the token buckets.
Refer to Section 13.3.3.25, on page 230 through Section 13.3.3.29, on page 233 for detailed register descriptions.
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LAN9313/LAN9313i
6.4.6.1
Ingress Flow Calculation
Based on the flow monitoring mode, an ingress flow definition can include the ingress priority. This is calculated similarly
to the transmit queue with the exception that the Priority Regeneration and the Traffic Class table are not used. As
shown in Figure 6-6, the priority can be based on:
•
•
•
•
The precedence bits in the IPv4 TOS octet
The DIFFSERV mapping table indexed by the IPv4 TOS octet or the IPv6 Traffic Class octet
The VLAN tag priority field (but not through the per port Priority Regeneration table)
The port default
FIGURE 6-6:
SWITCH ENGINE INGRESS FLOW PRIORITY SELECTION
Packet is from Host
Packet is Tagged
Packet is IPv 4
Packet is IP
VL Higher Priority
Use Precedence
Use IP
VLAN Enable
IPv4(TOS)
IPv6(TC)
6b
Programmable
DIFFSERV Table
3b
3b
IPv4 Precedence
3b
Source Port
VLAN Priority
2b
Priority
Calculation
3b
flow priority
Programmable
Port Default
Table
3b
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The ingress flow calculation is based on the packet type and the device configuration as shown in Figure 6-7.
FIGURE 6-7:
SWITCH ENGINE INGRESS FLOW PRIORITY CALCULATION
Get Flow Priority
Packet from Host
Y
N
N
VL Higher
Priority
Y
Vlan Enable &
Packet is
Tagged
Y
N
Y
Packet is IPv 4/v6
& Use IP
N
Y
Vlan Enable &
Packet is
Tagged
Packet is IPv 4
N
Y
Use Precedence
Flow Priority =
IP Precedence
Y
N
N
Flow Priority =
DIFFSERV[TOS]
Flow Priority =
DIFFSERV[TC]
Flow Priority =
Default Priority[Source
Port]
Flow Priority =
VLAN Priority
Get Flow Priority Done
6.4.7
BROADCAST STORM CONTROL
In addition to ingress rate limiting, the LAN9313/LAN9313i supports hardware broadcast storm control on a per port
basis. This feature is enabled via the Switch Engine Broadcast Throttling Register (SWE_BCST_THROT). The allowed
rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval. Packets
that exceed this limit are dropped. Typical values are listed in Table 6-5. When a port is receiving at 10Mbps, any setting
above 34 has the effect of not limiting the rate.
TABLE 6-5:
TYPICAL BROADCAST RATE SETTINGS
Broadcast Throttle Level
Bandwidth
252
75 Mbps
168
50 Mbps
134
40 Mbps
67
20 Mbps
34
10 Mbps
17
5 Mbps
8
2.4 Mbps
4
1.2 Mbps
3
900 Kbps
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TABLE 6-5:
TYPICAL BROADCAST RATE SETTINGS (CONTINUED)
Broadcast Throttle Level
Bandwidth
2
600 Kbps
1
300 Kbps
In addition to the rate limit, the Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) specifies the maximum number of buffers that can be used by broadcasts, multicasts, and unknown unicasts.
6.4.8
IPV4 IGMP SUPPORT
The LAN9313/LAN9313i provides Internet Group Management Protocol (IGMP) hardware support using two mechanisms: IGMP monitoring and Multicast Pruning.
On ingress, if IGMP packet monitoring is enabled in the Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG), IGMP multicast packets are trapped and redirected to the IGMP monitoring port (typically set
to the port to which the host CPU is connected). IGMP packets are identified as IPv4 packets with a protocol of 2. Both
Ethernet and IEEE 802.3 frame formats are supported as are VLAN tagged packets.
Once the IGMP packets are received by the host CPU, the host software can decide which port or ports need to be
members of the multicast group. This group is then added to the ALR table as detailed in Section 6.4.1.3, "Multicast
Pruning," on page 52. The host software should also forward the original IGMP packet if necessary.
Normally, packets are never transmitted back to the receiving port. For IGMP monitoring, this may optionally be enabled
via the Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG). This function would be
used if the monitoring port wished to participate in the IGMP group without the need to perform special handling in the
transmit portion of the driver software.
Note:
Most forwarding rules are skipped when a packet is monitored. However, a packet is still filtered if:
• The source port is not in the forwarding state (unless Spanning Tree Port State Override is in effect.
• VLAN’s are enabled, the packet is untagged or priority tagged, and the Admit Only VLAN bit for the ingress port
is set.
• VLAN’s are enabled and the packet is tagged and had a VID equal to FFFh.
• VLAN’s are enabled, Enabled Membership Checking on Ingress is set, Admit Non Member is cleared, and the
source port is not a member of the incoming VLAN.
6.4.9
PORT MIRRORING
The LAN9313/LAN9313i supports port mirroring where packets received or transmitted on a port or ports can also be
copied onto another “sniffer” port.
Port mirroring is configured using the Switch Engine Port Mirroring Register (SWE_PORT_MIRROR). Multiple mirrored
ports can be defined, but only one sniffer port can be defined.
When receive mirroring is enabled, packets that are forwarded from a port designated as a mirrored port are also transmitted by the sniffer port. For example, Port 2 is setup to be a mirrored port and Port 0 is setup to be the sniffer port. If
a packet is received on Port 2 with a destination of Port 1, it is forwarded to both Port 1 and Port 0.
When transmit mirroring is enabled, packets that are forwarded to a port designated as a mirrored port are also transmitted by the sniffer port. For example, Port 2 is setup to be a mirrored port and Port 0 is setup to be the sniffer port. If
a packet is received on Port 1 with a destination of Port 2, it is forwarded to both Port 2 and Port 0.
Note:
6.4.10
A packet will never be transmitted out of the receiving port. A receive packet is not normally mirrored if it is
filtered. This can optionally be enabled.
HOST CPU PORT SPECIAL TAGGING
The Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) and Buffer Manager Egress Port Type
Register (BM_EGRSS_PORT_TYPE) are used to enable a special VLAN tag that is used by the host CPU. This special
tag is used to specify the port(s) where packets from the CPU should be sent, and to indicate which port received the
packet that was forwarded to the CPU.
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6.4.10.1
Packets from the Host CPU
The Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) configures the switch to use the special
VLAN tag in packets from the host CPU as a destination port indicator. A setting of 11b should be used on the port that
is connected to the host CPU (typically Port 0). A setting of 00b should be used on the normal network ports.
The special VLAN tag is a normal VLAN tag where the VID field is used as the destination port indicator. If VID bit 3 is
zero, then bits 0 and 1 specify the destination port (0, 1, 2) or broadcast (3). If VID bit 3 is one, then the normal ALR
lookup is performed and learning is performed on the source address. The PRI field from the VLAN tag is used as the
packet priority.
Upon egress from the destination port(s), the special tag is removed. If a regular VLAN tag needs to be sent as part of
the packet, then it should be part of the packet data from the host CPU port or set as an unused bit in the VID field.
Note:
• When specifying Port 0 as the destination port, the VID will be set to 0. A VID of 0 is normally considered a priority tagged packet. Such a packet will be filtered if Admit Only VLAN is set on the host CPU port. Either avoid setting Admit Only VLAN on the host CPU port or set an unused bit in the VID field.
• The maximum size tagged packet that can normally be sent into a switch port (from the MII port) is 1522 bytes.
Since the special tag consumes four bytes of the packet length, the outgoing packet is limited to 1518 bytes, even
if it contains a regular VLAN tag as part of the packet data. If a larger outgoing packet is required, the Jumbo2K
bit in the Port x MAC Receive Configuration Register (MAC_RX_CFG_x) of Port 0 should be set.
6.4.10.2
Packets to the Host CPU
The Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) configures the switch to add the special
VLAN tag in packets to the host CPU as a source port indicator. A setting of 11b should be used only on the port that is
connected to the host CPU (typically Port 0). Other settings can be used on the normal network ports as needed.
The special VLAN tag is a normal VLAN tag where bits 0 and 1 of the VID field specify the source port (0, 1, or 2).
Upon egress from the host CPU port, the special tag is added. If a regular VLAN tag already exists, it is not deleted.
Instead it will follow the special tag.
6.4.11
COUNTERS
A counter is maintained per port that contains the number of MAC address that were not learned or were overwritten by
a different address due to MAC Address Table space limitations. These counters are accessible via the following registers:
• Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)
• Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)
• Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)
A counter is maintained per port that contains the number of packets filtered at ingress. This count includes packets
filtered due to broadcast throttling, but does not include packets dropped due to ingress rate limiting. These counters
are accessible via the following registers:
• Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)
• Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)
• Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)
6.5
Buffer Manager (BM)
The buffer manager (BM) provides control of the free buffer space, the multiple priority transmit queues, transmission
scheduling, and packet dropping. VLAN tag insertion and removal is also performed by the buffer manager. The following sections detail the various features of the buffer manager.
6.5.1
PACKET BUFFER ALLOCATION
The packet buffer consists of 32KB of RAM that is dynamically allocated in 128 byte blocks as packets are received. Up
to 16 blocks may be used per packet, depending on the packet length. The blocks are linked together as the packet is
received. If a packet is filtered, dropped, or contains a receive error, the buffers are reclaimed.
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6.5.1.1
Buffer Limits and Flow Control Levels
The BM keeps track of the amount of buffers used per each ingress port. These counts are used to generate flow control
(half-duplex backpressure or full-duplex pause frames) and to limit the amount of buffer space that can be used by any
individual receiver (hard drop limit). The flow control and drop limit thresholds are dynamic and adapt based on the current buffer usage. Based on the number of active receiving ports, the drop level and flow control pause and resume
thresholds adjust between fixed settings and two user programmable levels via the Buffer Manager Drop Level Register
(BM_DROP_LVL), Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL), and Buffer Manager
Flow Control Resume Level Register (BM_FC_RESUME_LVL) respectively.
The BM also keeps a count of the number of buffers that are queued for multiple ports (broadcast queue). This count is
compared against the Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL), and if the configured drop
level is reached or exceeded, subsequent packets are dropped.
6.5.2
RANDOM EARLY DISCARD (RED)
Based on the ingress flow monitoring detailed in Section 6.4.6, "Ingress Flow Metering and Coloring," on page 58, packets are colored as Green, Yellow, or Red. Packets colored Red are always discarded if the Drop on Red bit in the Buffer
Manager Configuration Register (BM_CFG) is set. If the Drop on Yellow bit in the Buffer Manager Configuration Register
(BM_CFG) is set, packets colored Yellow are randomly discarded based on the moving average number of buffers used
by the ingress port.
The probability of a discard is programmable into the Random Discard Weight table via the Buffer Manager Random
Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD), Buffer Manager Random Discard Table Write
Data Register (BM_RNDM_DSCRD_TBL_WDATA), and Buffer Manager Random Discard Table Read Data Register
(BM_RNDM_DSCRD_TBL_RDATA). The Random Discard Weight table contains sixteen entries, each 10-bits wide.
Each entry corresponds to a range of the average number of buffers used by the ingress port. Entry 0 is for 0 to 15
buffers, entry 1 is for 16 to 31 buffers, etc. The probability for each entry us set in 1/1024’s. For example, a setting of 1
is 1-in-1024, or approximately 0.1%. A setting of all ones (1023) is 1023-in-1024, or approximately 99.9%.
Refer to Section 13.3.4.10, "Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)," on page 243 for additional details on writing and reading the Random Discard Weight table.
6.5.3
TRANSMIT QUEUES
Once a packet has been completely received, it is queued for transmit. There are four queues per transmit port, one for
each level of transmit priority. Each queue is virtual (if there are no packets for that port/priority, the queue is empty),
and dynamic (a queue may be any length if there is enough memory space). When a packet is read from the memory
and sent out to the corresponding port, the used buffers are released.
6.5.4
TRANSMIT PRIORITY QUEUE SERVICING
When a transmit queue is non-empty, it is serviced and the packet is read from the buffer RAM and sent to the transmit
MAC. If there are multiple queues that require servicing, one of two methods may be used: fixed priority ordering, or
weighted round-robin ordering. If the Fixed Priority Queue Servicing bit in the Buffer Manager Configuration Register
(BM_CFG) is set, a strict order, fixed priority is selected. Transmit queue 3 has the highest priority, followed by 2, 1, and
0. If the Fixed Priority Queue Servicing bit in the Buffer Manager Configuration Register (BM_CFG) is cleared, a
weighted round-robin order is followed. Assuming all four queues are non-empty, the service is weighted with a 9:4:2:1
ratio (queue 3,2,1,0). The servicing is blended to avoid burstiness (e.g. queue 3, then queue 2, then queue 3, etc.).
6.5.5
EGRESS RATE LIMITING (LEAKY BUCKET)
For egress rate limiting, the leaky bucket algorithm is used on each output priority queue. For each output port, the bandwidth that is used by each priority queue can be limited. If any egress queue receives packets faster than the specified
egress rate, packets will be accumulated in the packet memory. After the memory is used, packet dropping or flow control will be triggered.
Note:
Egress rate limiting occurs before the Transmit Priority Queue Servicing, such that a lower priority queue
will be serviced if a higher priority queue is being rate limited.
The egress limiting is enabled per priority queue. After a packet is selected to be sent, its length is recorded. The switch
then waits a programmable amount of time, scaled by the packet length, before servicing that queue once again. The
amount of time per byte is programmed into the Buffer Manager Egress Rate registers (refer to Section 13.3.4.14
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through Section 13.3.4.19 for detailed register definitions). The value programmed is in approximately 20 nS per byte
increments. Typical values are listed in Table 6-6. When a port is transmitting at 10 Mbps, any setting above 39 has the
effect of not limiting the rate.
TABLE 6-6:
TYPICAL EGRESS RATE SETTINGS
Egress Rate
Setting
Time Per Byte
Bandwidth @
64 Byte Packet
Bandwidth @ 512
Byte Packet
Bandwidth @
1518 Byte Packet
0-3
80 nS
76 Mbps (Note 6-3)
96 Mbps (Note 6-3)
99 Mbps (Note 6-3)
4
100 nS
66 Mbps
78 Mbps
80 Mbps
5
120 nS
55 Mbps
65 Mbps
67 Mbps
6
140 nS
48 Mbps
56 Mbps
57 Mbps
7
160 nS
42 Mbps
49 Mbps
50 Mbps
9
200 nS
34 Mbps
39 Mbps
40 Mbps
12
260 nS
26 Mbps
30 Mbps
31 Mbps
19
400 nS
17 Mbps
20 Mbps
20 Mbps
39
800 nS
8.6 Mbps
10 Mbps
10 Mbps
78
1580 nS
4.4 Mbps
5 Mbps
5 Mbps
158
3180 nS
2.2 Mbps
2.5 Mbps
2.5 Mbps
396
7940 nS
870 Kbps
990 Kbps
1 Mbps
794
15900 nS
440 Kbps
490 Kbps
500 Kbps
1589
31800 nS
220 Kbps
250 Kbps
250 Kbps
3973
79480 nS
87 Kbps
98 Kbps
100 Kbps
7947
158960 nS
44 Kbps
49 Kbps
50 Kbps
Note 6-3
6.5.6
These are the unlimited max bandwidths when IFG and preamble are taken into account.
ADDING, REMOVING, AND CHANGING VLAN TAGS
Based on the port configuration and the received packet formation, a VLAN tag can be added to, removed from, or modified in a packet. There are four received packet type cases: non-tagged, priority-tagged, normal-tagged, and CPU special-tagged. There are also four possible settings for an egress port: dumb, access, hybrid, and CPU. In addition, each
VLAN table entry can specify the removal of the VLAN tag (the entry’s un-tag bit).
The tagging/un-tagging rules are specified as follows:
• Dumb Port - This port type generally does not change the tag.
When a received packet is non-tagged, priority-tagged, or normal-tagged, the packet passes untouched.
When a packet is received special-tagged from a CPU port, the special tag is removed.
• Access Port - This port type generally does not support tagging.
When a received packet in non-tagged, the packet passes untouched.
When a received packet is priority-tagged or normal-tagged, the tag is removed.
When a received packet is special-tagged from a CPU port, the special tag is removed.
• CPU Port - Packets transmitted from this port type generally contain a special tag. Special tags are described in
detail in Section 6.4.10, "Host CPU Port Special Tagging," on page 61.
• Hybrid Port - Generally, this port type supports a mix of normal-tagged and non-tagged packets. It is the most
complex, but most flexible port type.
For clarity, the following details the incoming un-tag instruction. As described in Section 6.4.4, "VLAN Support," on
page 56, the un-tag instruction is one of three un-tag bits from the applicable entry in the VLAN table, selected by the
ingress port number. The entry in the VLAN table is either the VLAN from the received packet or the ingress ports default
VID.
• When a received packet is non-tagged, a new VLAN tag is added if two conditions are met. First, the Insert Tag bit
for the egress port in the Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) must be set.
Second, the un-tag instruction associated with the ingress ports default VID must be cleared. The VLAN tag that is
added will have a VID and Priority taken from the ingress ports default VID and priority.
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• When a received packet is priority-tagged, either the tag is removed or it is modified.
If the un-tag instruction associated with the ingress ports default VID is set, then the tag is removed.
Otherwise, the tag is modified. The VID of the new VLAN tag is changed to the ingress ports default VID. If the Change
Priority bit in the Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) for the egress port is set, then
the Priority field of the new VLAN tag is also changed to the ingress ports default priority.
• When a received packet is normal-tagged, either the tag is removed, modified, or passed.
If the un-tag instruction associated with the VID in the received packet is set, then the tag is removed.
Else, if the Change Tag bit in the Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) for the egress
port is clear, the packet is untouched.
Else, if both the Change VLAN ID and the Change Priority bits in the Buffer Manager Egress Port Type Register
(BM_EGRSS_PORT_TYPE) for the egress port are clear, the packet passes untouched.
Otherwise, the tag is modified. If the Change VLAN ID bit for the egress port is set, the VOD of the new VLAN tag is
changed to the egress ports default ID. If the Change Priority bit for the egress port is set, the Priority field of the new
VLAN is changed to the egress ports default priority.
• When a packet is received special-tagged from a CPU port, the special tag is removed.
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Hybrid tagging is summarized in Figure 6-8.
FIGURE 6-8:
HYBRID PORT TAGGING AND UN-TAGGING
Receive Tag
Type
Non-tagged
Insert Tag
[egress_port]
Normal Tagged Priority Tagged
Default VID
[ingress_port]
Un-tag Bit
N
Y
Special Tagged
Y
N
Default VID
[ingress_port]
Un-tag Bit
Change Priority
[egress_port]
Y
N
N
Y
Add Tag
VID = Default VID
[ingress_port]
Priority = Default Priority
[ingress_port]
Modify Tag
VID = Default VID
[ingress_port]
Priority = Default Priority
[ingress_port]
Send Packet Untouched
Received VID
Un-tag Bit
Modify Tag
VID = Default VID
[ingress_port]
Priority = Unchanged
Strip Tag
Strip Tag
Y
N
Change Tag
[egress_port]
N
Y
Y
Y
Change Priority
[egress_port]
Modify Tag
VID = Default VID
[egress_port]
Priority = Default Priority
[egress_port]
Change VLAN ID
[egress_port]
N
Modify Tag
VID = Default VID
[egress_port]
Priority = Unchanged
N
Y
Change Priority
[egress_port]
Modify Tag
VID = Unchanged
Priority = Default Priority
[egress_port]
N
Send Packet Untouched
Strip Tag
The default VLAN ID and priority of each port may be configured via the following registers:
• Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII)
• Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1)
• Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2)
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6.5.7
COUNTERS
A counter is maintained per port that contains the number of packets dropped due to buffer space limits and ingress rate
limit discarding (Red and random Yellow dropping). These counters are accessible via the following registers:
• Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)
• Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)
• Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)
A counter is maintained per port that contains the number of packets dropped due solely to ingress rate limit discarding
(Red and random Yellow dropping). This count value can be subtracted from the drop counter, as described above, to
obtain the drop counts due solely to buffer space limits. The ingress rate drop counters are accessible via the following
registers:
• Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)
• Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)
• Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
6.6
Switch Fabric Interrupts
The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and
MACs. These interrupts are detailed in Section 5.2.2, "Switch Fabric Interrupts," on page 43.
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7.0
ETHERNET PHYS
7.1
Functional Overview
The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are
identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their
respective port. These PHYs interface with their respective MAC via an internal MII interface. The Virtual PHY provides
the virtual functionality of a PHY and allows connection of an external MAC to port 0 of the switch fabric as if it was
connected to a single port PHY. All PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can
be configured for full/half duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers
follow the IEEE 802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly via the
external MII interface signals, or directly via the memory mapped Virtual PHY registers. In addition, the Port 1 PHY and
Port 2 PHY can be configured via the PHY Management Interface (PMI). Refer to Section 13.2, "Ethernet PHY Control
and Status Registers" for details on the Ethernet PHY registers.
The LAN9313/LAN9313i Ethernet PHYs are discussed in detail in the following sections:
• Section 7.2, "Port 1 & 2 PHYs," on page 68
• Section 7.3, "Virtual PHY," on page 79
7.1.1
PHY ADDRESSING
Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap configuration strap as
shown in Table 7-1. In addition, the Port 1 PHY and Port 2 PHY addresses can be changed via the PHY Address (PHYADD) field in the Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x). For proper operation, all
LAN9313/LAN9313i PHY addresses must be unique. No check is performed to assure each PHY is set to a different
address. Configuration strap values are latched upon the de-assertion of a chip-level reset as described in Section 4.2.4,
"Configuration Straps," on page 33.
TABLE 7-1:
DEFAULT PHY SERIAL MII ADDRESSING
PHY_ADDR_SEL_STRAP
Virtual PHY Default
Address Value
Port 1 PHY Default
Address Value
Port 2 PHY Default
Address Value
0
0
1
2
1
1
2
3
7.2
Port 1 & 2 PHYs
Functionally, each PHY can be divided into the following sections:
•
•
•
•
•
•
100BASE-TX Transmit and 100BASE-TX Receive
10BASE-T Transmit and 10BASE-T Receive
PHY Auto-negotiation
HP Auto-MDIX
MII MAC Interface
PHY Management Control
Note 7-1
Because the Port 1 PHY and Port 2 PHY are functionally identical, this section will describe them as
the “Port x PHY”, or simply “PHY”. Wherever a lowercase “x” has been appended to a port or signal
name, it can be replaced with “1” or “2” to indicate the Port 1 or Port 2 PHY respectively. All
references to “PHY” in this section can be used interchangeably for both the Port 1 & 2 PHYs. This
nomenclature excludes the Virtual PHY.
A block diagram of the Port x PHYs main components can be seen in Figure 7-1.
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FIGURE 7-1:
PORT X PHY BLOCK DIAGRAM
AutoNegotiation
10/100
Transmitter
TXPx/TXNx
MII
MAC
Interface
MII
To Port x
Switch Fabric MAC
HP Auto-MDIX
RXPx/RXNx
To External
Port x Ethernet Pins
10/100
Reciever
MDIO
To MII Mux
PHY Management
Control
Interrupts
LEDs
To System
Interrupt Controller
To GPIO/LED
Controller
Registers
7.2.1
PLL
From
System Clocks Controller
100BASE-TX TRANSMIT
The 100BASE-TX transmit data path is shown in Figure 7-2. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
FIGURE 7-2:
100BASE-TX TRANSMIT DATA PATH
Internal
MII Transmit Clock
100M
PLL
Internal
MII 25 MHz by 4 bits
MII MAC
Interface
Port x
MAC
25MHz
by 4 bits
4B/5B
Encoder
25MHz by
5 bits
Scrambler
and PISO
125 Mbps Serial
NRZI
Converter
NRZI
MLT-3
Converter
MLT-3
100M
TX Driver
MLT-3
Magnetics
MLT-3
RJ45
MLT-3
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7.2.1.1
MII MAC Interface
For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".
Note:
The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
7.2.1.2
4B/5B Encoder
The transmit data passes from the MII block to the 4B/5B Encoder. This block encodes the data from 4-bit nibbles to 5bit symbols (known as “code-groups”) according to Table 7-2. Each 4-bit data-nibble is mapped to 16 of the 32 possible
code-groups. The remaining 16 code-groups are either used for control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The
remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is
/I/, a transmit error code-group is /H/, etc.
TABLE 7-2:
4B/5B CODE TABLE
Code Group
SYM
Receiver Interpretation
11110
0
0
0000
01001
1
1
10100
2
2
10101
3
01010
4
DATA
Transmitter Interpretation
0
0000
0001
1
0001
0010
2
0010
3
0011
3
0011
4
0100
4
0100
01011
5
5
0101
5
0101
01110
6
6
0110
6
0110
01111
7
7
0111
7
0111
10010
8
8
1000
8
1000
10011
9
9
1001
9
1001
10110
A
A
1010
A
1010
DATA
10111
B
B
1011
B
1011
11010
C
C
1100
C
1100
11011
D
D
1101
D
1101
11100
E
E
1110
E
1110
11101
F
F
1111
F
1111
11111
/I/
IDLE
Sent after /T/R/ until the MII Transmitter
Enable signal (TXEN) is received
11000
/J/
First nibble of SSD, translated to “0101”
following IDLE, else MII Receive Error
(RXER)
Sent for rising MII Transmitter Enable
signal (TXEN)
10001
/K/
Second nibble of SSD, translated to
Sent for rising MII Transmitter Enable
“0101” following J, else MII Receive Error signal (TXEN)
(RXER)
01101
/T/
First nibble of ESD, causes de-assertion Sent for falling MII Transmitter Enable
of CRS if followed by /R/, else assertion of signal (TXEN)
MII Receive Error (RXER)
00111
/R/
Second nibble of ESD, causes deassertion of CRS if following /T/, else
assertion of MII Receive Error (RXER)
Sent for falling MII Transmitter Enable
signal (TXEN)
00100
/H/
Transmit Error Symbol
Sent for rising MII Transmit Error (TXER)
00110
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
11001
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
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TABLE 7-2:
4B/5B CODE TABLE (CONTINUED)
Code Group
SYM
00000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00001
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00010
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00011
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
00101
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
01000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
01100
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
10000
/V/
INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV)
INVALID
7.2.1.3
Receiver Interpretation
Transmitter Interpretation
Scrambler and PISO
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band
peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire
channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being
radiated by the physical wiring. The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
The seed for the scrambler is generated from the PHY address, ensuring that each PHY will have its own scrambler
sequence. For more information on PHY addressing, refer to Section 7.1.1, "PHY Addressing".
7.2.1.4
NRZI and MLT-3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI
data stream. The NRZI is then encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents
a code bit “1” and the logic output remaining at the same level represents a code bit “0”.
7.2.1.5
100M Transmit Driver
The MLT-3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal on output pins TXPx
and TXNx (where “x” is replaced with “1” for the Port 1 PHY, or “2” for the Port 2 PHY), to the twisted pair media across
a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals pass through the same transformer so that
common “magnetics” can be used for both. The transmitter drives into the 100 impedance of the CAT-5 cable. Cable
termination and impedance matching require external components.
7.2.1.6
100M Phase Lock Loop (PLL)
The 100M PLL locks onto the reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the
100BASE-TX Transmitter.
7.2.2
100BASE-TX RECEIVE
The 100BASE-TX receive data path is shown in Figure 7-3. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
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FIGURE 7-3:
100BASE-TX RECEIVE DATA PATH
Internal
MII Receive Clock
100M
PLL
Port x
MAC
Internal
MII 25MHz by 4 bits
MII MAC
Interface
25MHz
by 4 bits
4B/5B
Decoder
25MHz by
5 bits
Descrambler
and SIPO
125 Mbps Serial
NRZI
Converter
A/D
Converter
NRZI
MLT-3
MLT-3
Converter
Magnetics
MLT-3
MLT-3
RJ45
DSP: Timing
recovery, Equalizer
and BLW Correction
MLT-3
CAT-5
6 bit Data
7.2.2.1
A/D Converter
The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx (where “x” is replaced with “1” for the Port
1 PHY, or “2” for the Port 2 PHY) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate
of 125M samples per second. Using a 64-level quantizer, 6 digital bits are generated to represent each sample. The
DSP adjusts the gain of the A/D Converter (ADC) according to the observed signal levels such that the full dynamic
range of the ADC can be used.
7.2.2.2
DSP: Equalizer, BLW Correction and Clock/Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel (magnetics, connectors, and CAT- 5 cable). The equalizer can restore
the signal for any good-quality CAT-5 cable between 1m and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)
on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive
the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP,
selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to
extract the serial data from the received signal.
7.2.2.3
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an
NRZI data stream.
7.2.2.4
Descrambler and SIPO
The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel
Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once
synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
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Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE symbols within a
window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE
802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period, receive
operation is aborted and the descrambler re-starts the synchronization process.
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)
pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of
frame.
7.2.2.5
5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table shown in Table 7-2. The translated data is presented on the internal MII RXD[3:0] signal lines to the switch fabric MAC. The SSD, /J/K/, is translated
to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the PHY to assert the RXDV
signal, indicating that valid data is available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols
causes the PHY to de-assert carrier sense and RXDV. These symbols are not translated into data.
7.2.2.6
Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0
through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RXER signal is asserted
and arbitrary data is driven onto the internal receive data bus (RXD) to the switch fabric MAC. Should an error be
detected during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted and the value
1110b is driven onto the internal receive data bus (RXD) to the switch fabric MAC. Note that the internal MII’s data valid
signal (RXDV) is not yet asserted when the bad SSD occurs.
7.2.2.7
MII MAC Interface
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block where they are sent via MII to the switch
fabric MAC. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".
Note:
7.2.3
The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
10BASE-T TRANSMIT
Data to be transmitted comes from the switch fabric MAC. The 10BASE-T transmitter receives 4-bit nibbles from the
internal MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchesterencoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.
10BASE-T transmissions use the following blocks:
• MII MAC Interface (digital)
• 10M TX Driver (digital/analog)
• 10M PLL (analog)
7.2.3.1
MII MAC Interface
For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".
Note:
7.2.3.2
The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
10M TX Driver and PLL
The 4-bit wide data is sent to the 10M TX Driver block. The nibbles are converted to a 10Mbps serial NRZI data stream.
The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted (TXEN is low), the 10M TX Driver block outputs
Normal Link Pulses (NLPs) to maintain communications with the remote link partner. The manchester encoded data is
sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the
TXPx and TXNx outputs (where “x” is replaced with “1” for the Port 1 PHY, or “2” for the Port 2 PHY).
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7.2.4
10BASE-T RECEIVE
The 10BASE-T receiver gets the Manchester-encoded analog signal from the cable via the magnetics. It recovers the
receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to
4-bit data nibbles which are passed to the controller across the internal MII at a rate of 2.5MHz.
10BASE-T reception uses the following blocks:
•
•
•
•
Filter and SQUELCH (analog)
10M RX (digital/analog)
MII MAC Interface (digital)
10M PLL (analog)
7.2.4.1
Filter and Squelch
The Manchester signal from the cable is fed into the PHY on inputs RXPx and RXNx (where “x” is replaced with “1” for
Port 1, or “2” for Port 2) via 1:1 ratio magnetics. It is first filtered to reduce any out-of-band noise. It then passes through
a SQUELCH circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential voltage
levels below 300mV and detect and recognize differential voltages above 585mV.
7.2.4.2
10M RX and PLL
The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded data. The polarity
of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice
versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in Port x PHY
Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). The 10M PLL locks onto the
received Manchester signal and generates the received 20MHz clock from it. Using this clock, the Manchester encoded
data is extracted and converted to a 10MHz NRZI data stream. It is then converted from serial to 4-bit wide parallel data.
The RX10M block also detects valid 10BASE-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link.
7.2.4.3
MII MAC Interface
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block where they are sent via MII to the switch
fabric MAC. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".
Note:
7.2.4.4
The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
Jabber Detection
Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length,
usually due to a fault condition, that results in holding the TXEN input for an extended period of time. Special logic is
used to detect the jabber state and abort the transmission to the line, within 45ms. Once TXEN is deasserted, the logic
resets the jabber condition.
7.2.5
PHY AUTO-NEGOTIATION
The purpose of the auto-negotiation function is to automatically configure the PHY to the optimum link parameters based
on the capabilities of its link partner. Auto-negotiation is a mechanism for exchanging configuration information between
two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Autonegotiation is fully defined in clause 28 of the IEEE 802.3 specification and is enabled by setting bit 12 (PHY_AN) of the
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x).
The advertised capabilities of the PHY are stored in the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x). The PHY contains the ability to advertise 100BASE-TX and 10BASE-T in both full or half-duplex
modes. Besides the connection speed, the PHY can advertise remote fault indication and symmetric or asymmetric
pause flow control as defined in the IEEE 802.3 specification. The LAN9313/LAN9313i does not support “Next Page”
capability. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in
Section 13.2.2.5, "Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 180. Refer to
Section 4.2.4, "Configuration Straps," on page 33 for additional details on how to use the LAN9313/LAN9313i configuration straps.
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Once auto-negotiation has completed, information about the resolved link and the results of the negotiation process are
reflected in the speed indication bits in the Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x), as well as the Port x PHY Auto-Negotiation Link Partner Base Page Ability Register
(PHY_AN_LP_BASE_ABILITY_x).
The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller.
The following blocks are activated during an Auto-negotiation session:
•
•
•
•
•
•
•
Auto-negotiation (digital)
100M ADC (analog)
100M PLL (analog)
100M equalizer/BLW/clock recovery (DSP)
10M SQUELCH (analog)
10M PLL (analog)
10M TX Driver (analog)
Auto-negotiation is started by the occurrence of any of the following events:
• Power-On Reset (POR)
• Hardware reset (nRST)
• PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x))
• PHY Power-down reset (Section 7.2.9, "PHY Power-Down Modes," on page 78)
• PHY Link status down (bit 2 of the Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) is cleared)
• Setting the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 high (auto-neg restart)
• Digital Reset (via bit 0 of the Reset Control Register (RESET_CTL))
• Issuing an EEPROM Loader RELOAD command (Section 8.2.4, "EEPROM Loader," on page 93)
Note:
Refer to Section 4.2, "Resets," on page 30 for information on these and other system resets.
On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast Link Pulses (FLP).
These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered pulses,
which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent, contain
the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28.
In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It advertises its technology ability according to the bits set in the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x).
There are 4 possible matches of the technology abilities. In the order of priority these are:
•
•
•
•
100M Full Duplex (highest priority)
100M Half Duplex
10M Full Duplex
10M Half Duplex (lowest priority)
If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable of 10M and 100M,
then auto-negotiation selects 100M as the highest performance mode. If the link partner is capable of half and full-duplex
modes, then auto-negotiation selects full-duplex as the highest performance mode.
Once a speed and duplex match has been determined, the link code words are repeated with the acknowledge bit set.
Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if all of the required FLP bursts are not received.
Writing the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) bits [8:5] allows software control of
the capabilities advertised by the PHY. Writing the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) does not automatically re-start auto-negotiation. The Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x), bit 9 must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software
by clearing bit 12 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x).
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7.2.5.1
PHY Pause Flow Control
The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frames per the IEEE 802.3 specification. The PHYs advertised pause flow control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric Pause)
of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x). This allows the PHY to advertise its flow
control abilities and auto-negotiate the flow control settings with its link partner. The default values of these bits are
determined via configuration straps as defined in Section 13.2.2.5, "Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 180.
The pause flow control settings may also be manually set via the manual flow control registers Port 1 Manual Flow Control Register (MANUAL_FC_1) and Port 2 Manual Flow Control Register (MANUAL_FC_2). These registers allow the
switch fabric ports flow control settings to be manually set when auto-negotiation is disabled or the Manual Flow Control
Select bit 0 is set. The currently enabled duplex and flow control settings can also be monitored via these registers. The
flow control values in the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) are not affected by
the values of the manual flow control register. Refer to Section 6.2.3, "Flow Control Enable Logic," on page 47 for additional information.
7.2.5.2
Parallel Detection
If the LAN9313/LAN9313i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is
able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case
the link is presumed to be half-duplex per the IEEE 802.3 standard. This ability is known as “Parallel Detection.” This
feature ensures interoperability with legacy link partners. If a link is formed via parallel detection, then bit 0 in the Port x
PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is cleared to indicate that the link partner is not capable
of auto-negotiation. If a fault occurs during parallel detection, bit 4 of the Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is set.
The Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) is used to
store the Link Partner Ability information, which is coded in the received FLPs. If the link partner is not auto-negotiation
capable, then this register is updated after completion of parallel detection to reflect the speed capability of the link partner.
7.2.5.3
Restarting Auto-Negotiation
Auto-negotiation can be re-started at any time by setting bit 9 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). Auto-negotiation will also re-start if the link is broken at any time. A broken link is caused by signal loss.
This may occur because of a cable break, or because of an interruption in the signal transmitted by the Link Partner.
Auto-negotiation resumes in an attempt to determine the new link configuration.
If the management entity re-starts Auto-negotiation by writing to bit 9 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x), the LAN9313/LAN9313i will respond by stopping all transmission/receiving operations. Once the
internal break link time of approximately 1200ms has passed in the Auto-negotiation state-machine, the auto-negotiation will re-start. In this case, the link partner will have also dropped the link due to lack of a received signal, so it too will
resume auto-negotiation.
7.2.5.4
Disabling Auto-Negotiation
Auto-negotiation can be disabled by clearing bit 12 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). The PHY will then force its speed of operation to reflect the speed (bit 13) and duplex (bit 8) of the Port x PHY
Basic Control Register (PHY_BASIC_CONTROL_x). The speed and duplex bits in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) should be ignored when auto-negotiation is enabled.
7.2.5.5
Half Vs. Full-Duplex
Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If
data is received while the PHY is transmitting, a collision results.
In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS responds only to
receive activity. The CSMA/CD protocol does not apply and collision detection is disabled.
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7.2.6
HP AUTO-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP interconnect cable without
consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable or a cross-over patch cable,
as shown in Figure 7-4 (See Note 7-1 on page 68), the PHY is capable of configuring the TXPx/TXNx and RXPx/RXNx
twisted pair pins for correct transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs
are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and
termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through bit 15 (AMDIXCTRL) of the Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is cleared, Auto-MDIX can be selected
via the auto_mdix_strap_x configuration strap. The MDIX can also be configured manually via the manual_mdix_strap_x if both the AMDIXCTRL bit and the auto_mdix_strap_x configuration strap are low. Refer to Section 3.2, "Pin
Descriptions," on page 17 for more information on the configuration straps.
When bit 15 (AMDIXCTRL) of the Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) is set to 1, the Auto-MDIX capability is determined by bits 13 and 14 of the Port x PHY Special
Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x).
FIGURE 7-4:
DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION
RJ-45 8-pin straight-through
for 10BASE-T/100BASE-TX
signaling
TXPx
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
signaling
1
TXPx
TXPx
1
1
TXPx
2
2
TXNx
TXNx
2
2
TXNx
RXPx
3
3
RXPx
RXPx
3
3
RXPx
Not Used
4
4
Not Used
Not Used
4
4
Not Used
Not Used
5
5
Not Used
Not Used
5
5
Not Used
RXNx
6
6
RXNx
RXNx
6
6
RXNx
Not Used
7
7
Not Used
Not Used
8
8
Not Used
TXNx
1
Not Used
7
7
Not Used
Not Used
8
8
Not Used
Direct Connect Cable
7.2.7
Cross-Over Cable
MII MAC INTERFACE
The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch
fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3.
For a transmission, the switch fabric MAC drives the transmit data onto the internal MII TXD bus and asserts TXEN to
indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASET.
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the output clock for the internal MII bus.
It is recovered from the received data to clock the RXD bus. If there is no received signal, it is derived from the system
reference clock.
7.2.8
PHY MANAGEMENT CONTROL
The PHY Management Control block is responsible for the management functions of the PHY, including register access
and interrupt generation. A Serial Management Interface (SMI) is used to support registers 0 through 6 as required by
the IEEE 802.3 (Clause 22), as well as the vendor specific registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals interface
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to the MDIO and MDC pins of the LAN9313/LAN9313i (or the PMI block in I2C and SPI modes of operation) and allow
access to all PHY registers. Refer to Section 13.2.2, "Port 1 & 2 PHY Registers," on page 175 for a list of all supported
registers and register descriptions. Non-supported registers will be read as FFFFh.
7.2.8.1
PHY Interrupts
The PHY contains the ability to generate various interrupt events as described in Table 7-3. Reading the Port x PHY
Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) shows the source of the interrupt, and clears the
interrupt signal. The Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) enables or disables each PHY
interrupt. The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is
sent to the System Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) bit 26 (PHY_INT1)
for the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the LAN9313/LAN9313i interrupts, refer to Section 5.0, "System Interrupts," on page 41.
TABLE 7-3:
PHY INTERRUPT SOURCES
Interrupt Source
7.2.9
PHY_INTERRUPT_MASK_x &
PHY_INTERRUPT_SOURCE_x Register Bit #
ENERGYON Activated
7
Auto-Negotiation Complete
6
Remote Fault Detected
5
Link Down (Link Status Negated)
4
Auto-Negotiation LP Acknowledge
3
Parallel Detection Fault
2
Auto-Negotiation Page Received
1
PHY POWER-DOWN MODES
There are two power-down modes for the PHY:
• PHY General Power-Down
• PHY Energy Detect Power-Down
Note:
• For more information on the various power management features of the LAN9313/LAN9313i, refer to Section 4.3,
"Power Management," on page 40.
• The power-down modes of each PHY (Port 1 PHY and Port 2 PHY) are controlled independently.
• The PHY power-down modes do not reload or reset the PHY registers.
7.2.9.1
PHY General Power-Down
This power-down mode is controlled by bit 11 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x).
In this mode the entire PHY, except the PHY management control interface, is powered down. The PHY will remain in
this power-down state as long as bit 11 is set. When bit 11 is cleared, the PHY powers up and is automatically reset.
7.2.9.2
PHY Energy Detect Power-Down
This power-down mode is enabled by setting bit 13 (EDPWRDOWN) of the Port x PHY Mode Control/Status Register
(PHY_MODE_CONTROL_STATUS_x). When in this mode, if no energy is detected on the line, the entire PHY is powered down except for the PHY management control interface, the SQUELCH circuit, and the ENERGYON logic. The
ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or auto-negotiation signals and is responsible for driving the ENERGYON signal (bit 1) of the Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x).
In this mode, when the ENERGYON signal is cleared, the PHY is powered down and no data is transmitted from the
PHY. When energy is received, via link pulses or packets, the ENERGYON signal goes high, and the PHY powers up.
The PHY automatically resets itself into its previous state prior to power-down, and asserts the INT7 interrupt (bit 7) of
the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The first and possibly second packet
to activate ENERGYON may be lost.
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When bit 13 (EDPWRDOWN) of the Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
is low, energy detect power-down is disabled.
7.2.10
PHY RESETS
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the PHY supports three block specific
resets. These are discussed in the following sections. For detailed information on all LAN9313/LAN9313i resets and the
reset sequence refer to Section 4.2, "Resets," on page 30.
The DIGITAL_RST bit in the Reset Control Register (RESET_CTL) does not reset the PHYs. Only a hardware reset (nRST) or an EEPROM RELOAD command will automatically reload the configuration strap values into the PHY registers. For all other PHY resets, these values will need to be manually configured via
software.
Note:
7.2.10.1
PHY Software Reset via RESET_CTL
The PHY can be reset via the Reset Control Register (RESET_CTL). The Port 1 PHY is reset by setting bit 1
(PHY1_RST), and the Port 2 PHY is reset by setting bit 2 (PHY2_RST). These bits are self clearing after approximately
102uS. This reset does not reload the configuration strap values into the PHY registers.
7.2.10.2
PHY Software Reset via PHY_BASIC_CTRL_x
The PHY can also be reset by setting bit 15 (PHY_RST) of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete. This reset does not reload the configuration strap values into the PHY registers.
7.2.10.3
PHY Power-Down Reset
After the PHY has returned from a power-down state, a reset of the PHY is automatically generated. The PHY powerdown modes do not reload or reset the PHY registers. Refer to Section 7.2.9, "PHY Power-Down Modes," on page 78
for additional information.
7.2.11
LEDS
Each PHY provides LED indication signals to the GPIO/LED block of the LAN9313/LAN9313i. This allows external LEDs
to be used to indicate various PHY related functions such as TX/RX activity, speed, duplex, or link status. Refer to Section 12.0, "GPIO/LED Controller," on page 120 for additional information on the configuration of these signals.
7.2.12
REQUIRED ETHERNET MAGNETICS
The magnetics selected for use with the LAN9313/LAN9313i should be an Auto-MDIX style magnetic, which is widely
available from several vendors. Please review the Microchip Application note 8.13 “Suggested Magnetics” for the latest
qualified and suggested magnetics. A list of vendors and part numbers are provided within the application note.
7.3
Virtual PHY
The Virtual PHY provides a basic MII management interface (MDIO) to the MII management pins per the IEEE 802.3
(clause 22) so that a MAC with an unmodified driver can be supported as if the MAC was attached to a single port PHY.
This functionality is designed to allow easy and quick integration of the LAN9313/LAN9313i into designs with minimal
driver modifications. The Virtual PHY provides a full bank of registers which comply with the IEEE 802.3 specification.
This enables the Virtual PHY to provide various status and control bits similar to those provided by a real PHY. These
include the output of speed selection, duplex, loopback, isolate, collision test, and auto-negotiation status. For a list of
all Virtual PHY registers and related bit descriptions, refer to Section 13.2.1, "Virtual PHY Registers," on page 175.
7.3.1
VIRTUAL PHY AUTO-NEGOTIATION
The purpose of the auto-negotiation function is to automatically configure the Virtual PHY to the optimum link parameters based on the capabilities of its link partner. Because the Virtual PHY has no actual link partner, the auto-negotiation
process is emulated with deterministic results.
Auto-negotiation is enabled by setting bit 12 (VPHY_AN) of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) and is restarted by the occurrence of any of the following events:
• Power-On Reset (POR)
• Hardware reset (nRST)
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• PHY Software reset (via bit 3 of the Reset Control Register (RESET_CTL), or bit 15 of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL))
• Setting the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL), bit 9 high (auto-neg restart)
• Digital Reset (via bit 10 of the Reset Control Register (RESET_CTL))
• Issuing an EEPROM Loader RELOAD command (Section 8.2.4, "EEPROM Loader," on page 93)
The emulated auto-negotiation process is much simpler than the real process and can be categorized into three steps:
1.
2.
3.
Bit 5 (Auto-Negotiation Complete) is set in the Virtual PHY Basic Status Register (VPHY_BASIC_STATUS).
Bit 1 (Page Received) is set in the Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP).
The auto-negotiation result (speed and duplex) is determined and registered.
The auto-negotiation result (speed and duplex) is determined using the Highest Common Denominator (HCD) of the
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) and Virtual PHY Auto-Negotiation Link Partner
Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) as specified in the IEEE 802.3 standard. The technology
ability bits of these registers are ANDed, and if there are multiple bits in common, the priority is determined as follows:
•
•
•
•
100Mbps Full Duplex (highest priority)
100Mbps Half Duplex
10Mbps Full Duplex
10Mbps Half Duplex (lowest priority)
For example, if the full capabilities of the Virtual PHY are advertised (100Mbps, Full Duplex), and if the link partner is
capable of 10Mbps and 100Mbps, then auto-negotiation selects 100Mbps as the highest performance mode. If the link
partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest performance
operation. In the event that there are no bits in common, an emulated Parallel Detection is used.
The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) defaults to having all four ability bits set.
These values can be reconfigured via software. Once the auto-negotiation is complete, any change to the Virtual PHY
Auto-Negotiation Advertisement Register (VPHY_AN_ADV) will not take affect until the auto-negotiation process is rerun. The emulated link partner default advertised abilities in the Virtual PHY Auto-Negotiation Link Partner Base Page
Ability Register (VPHY_AN_LP_BASE_ABILITY) are dependant on the MII_DUPLEX pin and the duplex_pol_strap_mii
and speed_strap_mii configuration straps as described in Table 13-6 of Section 13.1.7.6, "Virtual PHY Auto-Negotiation
Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)," on page 167. Neither the Virtual PHY or the
emulated link partner support next page capability, remote faults, or 100BASE-T4.
Note:
The MII_DUPLEX, duplex_pol_strap_mii, and speed_strap_mii inputs are considered to be static. Autonegotiation is not automatically re-evaluated if these inputs are changed.
If there is at least one common selection between the emulated link partner and the Virtual PHY advertised abilities,
then the auto-negotiation succeeds, the Link Partner Auto-Negotiation Able bit 0 of the Virtual PHY Auto-Negotiation
Expansion Register (VPHY_AN_EXP) is set, and the technology ability bits in the Virtual PHY Auto-Negotiation Link
Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) are set to indicate the emulated link partners abilities.
Note:
7.3.1.1
For the Virtual PHY, the auto-negotiation register bits (and management of such) are used by the PMI. So
the perception of local and link partner is reversed. The local device is the PMI, while the link partner is the
switch fabric. This is consistent with the intention of the Virtual PHY.
Parallel Detection
In the event that there are no common bits between the advertised ability and the emulated link partners ability, autonegotiation fails and emulated parallel detect is used. In this case, the Link Partner Auto-Negotiation Able (bit 0) in the
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) will be cleared, and the communication set to halfduplex. The speed is determined by the speed_strap_mii configuration strap. Only one of the technology ability bits in
the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) will be set,
indicating the emulated parallel detect result.
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7.3.1.2
Disabling Auto-Negotiation
Auto-negotiation can be disabled in the Virtual PHY by clearing bit 12 (VPHY_AN) of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). The Virtual PHY will then force its speed of operation to reflect the speed (bit 13) and
duplex (bit 8) of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). The speed and duplex bits in the Virtual
PHY Basic Control Register (VPHY_BASIC_CTRL) should be ignored when auto-negotiation is enabled.
7.3.1.3
Virtual PHY Pause Flow Control
The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs advertised pause flow
control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric Pause) of the Virtual PHY Auto-Negotiation
Advertisement Register (VPHY_AN_ADV). This allows the Virtual PHY to advertise its flow control abilities and autonegotiate the flow control settings with the emulated link partner. The default values of these bits are as shown in Section
13.1.7.5, "Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page 166.
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised pause flow control
abilities of the Virtual PHY in (bits 10 & 11) of the Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV). Thus, the emulated link partner always accommodates the asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in Table 13-5, “Emulated Link Partner Pause Flow Control Ability Default
Values,” on page 168.
The pause flow control settings may also be manually set via the Port 0(External MII) Manual Flow Control Register
(MANUAL_FC_MII). This register allows the switch fabric port 0 flow control settings to be manually set when autonegotiation is disabled or the Manual Flow Control Select bit 0 is set. The currently enabled duplex and flow control settings can also be monitored via this register. The flow control values in the Virtual PHY Auto-Negotiation Advertisement
Register (VPHY_AN_ADV) are not affected by the values of the manual flow control register. Refer to Section 6.2.3,
"Flow Control Enable Logic," on page 47 for additional information.
7.3.2
VIRTUAL PHY IN MAC MODES
In the MAC modes of operation, an external PHY is connected to the MII interface of the LAN9313/LAN9313i. Because
there is an external PHY present, the Virtual PHY is not needed for external configuration. However, the port 0 switch
fabric MAC still requires the proper duplex setting. Therefore, in MAC mode, if the auto-negotiation bit (VPHY_AN) of
the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set, the duplex is based on the MII_DUPLEX pin and
duplex_pol_strap_mii configuration strap. If these signals are equal, the port 0 switch fabric MAC is configured for fullduplex, otherwise it is set for half-duplex. The MII_DUPLEX pin is typically connected to the duplex indication of the
external PHY. The duplex is not latched since the auto-negotiation process is not used. The duplex can be manually
selected by clearing the auto-negotiation bit (VPHY_AN) and controlling the duplex mode (VPHY_DUPLEX) bit in the
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL).
Note:
7.3.2.1
In MAC modes, the Virtual PHY registers are accessible through their memory mapped registers via the
SMI, SPI, or I2C serial management interfaces only. The Virtual PHY registers are not accessible through
MII management.
Full-Duplex Flow Control
In the MAC modes of operation, the Virtual PHY is not applicable. Therefore, full-duplex flow control should be controlled
manually by the host via the Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII), based on the external PHYs auto-negotiation results.
7.3.3
VIRTUAL PHY RESETS
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY supports two block
specific resets. These are is discussed in the following sections. For detailed information on all LAN9313/LAN9313i
resets, refer to Section 4.2, "Resets," on page 30.
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7.3.3.1
Virtual PHY Software Reset via RESET_CTL
The Virtual PHY can be reset via the Reset Control Register (RESET_CTL) by setting bit 3 (VPHY_RST). This bit is self
clearing after approximately 102uS.
7.3.3.2
Virtual PHY Software Reset via VPHY_BASIC_CTRL
The Virtual PHY can also be reset by setting bit 15 (VPHY_RST) of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). This bit is self clearing and will return to 0 after the reset is complete.
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8.0
SERIAL MANAGEMENT
8.1
Functional Overview
This chapter details the serial management functionality provided by the LAN9313/LAN9313i, which includes the
EEPROM I2C/Microwire master, EEPROM Loader, SPI slave, and I2C slave controllers.
The I2C/Microwire EEPROM controller is an I2C/Microwire master module which interfaces an optional external
EEPROM with the system register bus and the EEPROM Loader. Multiple types (I2C/Microwire) and sizes of external
EEPROMs are supported. Configuration of the EEPROM type and size are accomplished via the eeprom_type_strap
and eeprom_size_strap[1:0] configuration straps respectively. Various commands are supported for each EEPROM
type, allowing for the storage and retrieval of static data. The I2C interface conforms to the Philips I2C-Bus Specification.
The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the
LAN9313/LAN9313i at reset, allowing the LAN9313/LAN9313i to operate unmanaged. The EEPROM Loader module
interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs.
The SPI/I2C slave controller can be used for CPU serial management and allows CPU access to all system CSRs. The
SPI slave controller supports single register and multiple register read and write commands. The I2C slave controller
implements the low level I2C slave serial interface (start and stop condition detection, data bit transmission/reception,
and acknowledge generation/reception), handles the slave command protocol, and performs system register reads and
writes. The I2C slave controller conforms to the Philips I2C-Bus Specification.
8.2
I2C/Microwire Master EEPROM Controller
Based on the configuration strap eeprom_type_strap, the I2C/Microwire EEPROM controller supports either Microwire
or I2C compatible EEPROMs. The I2C/Microwire serial management pins functionality and characteristics differ dependant on the selected EEPROM type as summarized in Table 8-1.
TABLE 8-1:
EEPROM
Type/Mode
I2C/MICROWIRE MASTER SERIAL MANAGEMENT PINS CHARACTERISTICS
EE_SDA/EEDI Pin
I2C Master
EE_SDA
EEPROM Mode Input enabled
(to I2C master)
eeprom_type_strap =
1
Open-drain output
(from I2C master)
Pull-down disabled
Microwire
EEDI
Master
Input enabled
EEPROM Mode (to Microwire master)
eeprom_type_strap =
0
Note:
8.2.1
Output disabled
Pull-down enabled
EEDO Pin
EECS Pin
EE_SCL/EECLK Pin
NOT USED
NOT USED
EE_SCL
Input enabled
(used for straps)
Input enabled
(used for straps)
EEDO
EECS
EECLK
Input enabled
(used for straps)
Input enabled
(used for straps)
Input enabled
(used for straps)
Output enabled (from
Microwire master)
Output enabled (from
Microwire master)
Output enabled (from
Microwire master)
Input enabled
(to I2C master and
used
for straps)
Output enabled (driven Output enabled (driven
Open-drain output
low)
low)
(from I2C master)
When the EEPROM Loader is running, it has exclusive use of the I2C/Microwire EEPROM controller. Refer
to Section 8.2.4, "EEPROM Loader" for more information.
EEPROM CONTROLLER OPERATION
I2C and Microwire master EEPROM operations are performed using the EEPROM Command Register (E2P_CMD) and
EEPROM Data Register (E2P_DATA).
In Microwire EEPROM mode, the following operations are supported:
•
•
•
•
ERASE (Erase Location)
ERAL (Erase All)
EWDS (Erase/Write Disable)
EWEN (Erase/Write Enable)
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•
•
•
•
READ (Read Location)
WRITE (Write Location)
WRAL (Write All)
RELOAD (EEPROM Loader Reload - See Section 8.2.4, "EEPROM Loader")
Note:
• In I2C EEPROM mode, only a sub-set of the above commands (READ, WRITE, and RELOAD) are supported.
• The EEPROM Loader uses the READ command only.
The supported commands of each mode are detailed in Section 13.1.3.1, "EEPROM Command Register (E2P_CMD),"
on page 133. Details specific to each EEPROM controller mode (I2C and Microwire) are explained in Section 8.2.2, "I2C
EEPROM" and Section 8.2.3, "Microwire EEPROM" respectively.
When issuing a WRITE, or WRAL command, the desired data must first be written into the EEPROM Data Register
(E2P_DATA). The WRITE or WRAL command may then be issued by setting the EPC_COMMAND field of the
EEPROM Command Register (E2P_CMD) to the desired command value. If the operation is a WRITE, the EPC_ADDRESS field in the EEPROM Command Register (E2P_CMD) must also be set to the desired location. The command
is executed when the EPC_BUSY bit of the EEPROM Command Register (E2P_CMD) is set. The completion of the
operation is indicated when the EPC_BUSY bit is cleared.
When issuing a READ command, the EPC_COMMAND and EPC_ADDRESS fields of the EEPROM Command Register (E2P_CMD) must be configured with the desired command value and the read address, respectively. The READ
command is executed by setting the EPC_BUSY bit of the EEPROM Command Register (E2P_CMD). The completion
of the operation is indicated when the EPC_BUSY bit is cleared, at which time the data from the EEPROM may be read
from the EEPROM Data Register (E2P_DATA).
Other EEPROM operations (EWDS, EWEN, ERASE, ERAL, RELOAD) are performed by writing the appropriate command into the EPC_COMMAND field of the EEPROM Command Register (E2P_CMD). The command is executed by
setting the EPC_BUSY bit of the EEPROM Command Register (E2P_CMD). In all cases, the software must wait for the
EPC_BUSY bit to clear before modifying the EEPROM Command Register (E2P_CMD).
Note:
The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM,
the EWEN command must first be issued.
If an operation is attempted and the EEPROM device does not respond within 30mS, the LAN9313/LAN9313i will timeout, and the EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) will be set.
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2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Figure 8-1 illustrates the process required to perform an EEPROM read or write operation.
FIGURE 8-1:
EEPROM ACCESS FLOW DIAGRAM
EEPROM Write
EEPROM Read
Idle
Idle
Write
E2P_DATA
Register
Write
E2P_CMD
Register
Write
E2P_CMD
Register
Read
E2P_CMD
Register
EPC_BUSY = 0
EPC_BUSY = 0
8.2.2
Read
E2P_CMD
Register
Read
E2P_DATA
Register
I2C EEPROM
The I2C master implements a low level serial interface (start and stop condition generation, data bit transmission and
reception, acknowledge generation and reception) for connection to I2C EEPROMs, and consists of a data wire
(EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the master, while the data wire is bi-directional.
Both signals are open-drain and require external pull-up resistors.
The serial clock is also used as an input as it can be held low by the slave device in order to wait-state the data cycle.
Once the slave has data available or is ready to receive, it will release the clock. Assuming the masters clock low time
is also expired, the clock will rise and the cycle will continue. In the event that the slave device holds the clock low for
more than 30mS, the current command sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command
Register (E2P_CMD) is set. Both the clock and data signals have Schmitt trigger inputs and digital input filters. The digital filters reject pulses that are less than 100nS.
Note:
Since the I2C master is designed to access EEPROM only, multi-master arbitration is not supported.
Based on the configuration strap eeprom_size_strap, various sized I2C EEPROMs are supported. The varying size
ranges are supported by additional bits in the address field (EPC_ADDRESS) of the EEPROM Command Register
(E2P_CMD). Within each size range, the largest EEPROM uses all the address bits, while the smaller EEPROMs treat
the upper address bits as don’t cares. The EEPROM controller drives all the address bits as requested regardless of
the actual size of the EEPROM. The supported size ranges for I2C operation are shown in Table 8-2.
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
I2C EEPROM SIZE RANGES
TABLE 8-2:
EEPROM_SIZE_STRAP[0]
# of Address Bytes
EEPROM Size
EEPROM Types
0
1 (Note 8-1)
16 x 8 through 2048 x 8
24xx00, 24xx01, 24xx02,
24xx04, 24xx08, 24xx16
1
2
4096 x 8 through 65536 x 8
24xx32, 24xx64, 24xx128,
24xx256, 24xx512
Bits in the control byte are used as the upper address bits.
Note 8-1
2
The I C master interface runs at the standard-mode rate of 100KHz and is fully compliant with the Philips I2C-Bus Specification. Refer to the he Philips I2C-Bus Specification for detailed timing information.
8.2.2.1
I2C Protocol Overview
I2C is a bi-directional 2-wire data protocol. A device that sends data is defined as a transmitter and a device that receives
data is defined as a receiver. The bus is controlled by a master which generates the EE_SCL clock, controls bus access,
and generates the start and stop conditions. Either the master or slave may operate as a transmitter or receiver as determined by the master.
The following bus states exist:
• Idle: Both EE_SDA and EE_SCL are high when the bus is idle.
• Start & Stop Conditions: A start condition is defined as a high to low transition on the EE_ SDA line while EE_
SCL is high. A stop condition is defined as a low to high transition on the EE_SDA line while EE_SCL is high. The
bus is considered to be busy following a start condition and is considered free 4.7uS/1.3uS (for 100KHz and
400KHz operation, respectively) following a stop condition. The bus stays busy following a repeated start condition (instead of a stop condition). Starts and repeated starts are otherwise functionally equivalent.
• Data Valid: Data is valid, following the start condition, when EE_SDA is stable while EE_SCL is high. Data can
only be changed while the clock is low. There is one valid bit per clock pulse. Every byte must be 8 bits long and is
transmitted msb first.
• Acknowledge: Each byte of data is followed by an acknowledge bit. The master generates a ninth clock pulse for
the acknowledge bit. The transmitter releases EE_SDA (high). The receiver drives EE_SDA low so that it remains
valid during the high period of the clock, taking into account the setup and hold times. The receiver may be the
master or the slave depending on the direction of the data. Typically the receiver acknowledges each byte. If the
master is the receiver, it does not generate an acknowledge on the last byte of a transfer. This informs the slave to
not drive the next byte of data so that the master may generate a stop or repeated start condition.
Figure 8-2 displays the various bus states of a typical I2C cycle.
I2C CYCLE
FIGURE 8-2:
data
can
change
data
stable
data
can
change
data
can
change
data
stable
data
can
change
EE_SDA
S
Sr
P
EE_SCL
Start Condition
DS00002288A-page 86
Data Valid
or Ack
Re-Start
Condition
Data Valid
or Ack
Stop Condition
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
8.2.2.2
I2C EEPROM Device Addressing
The I2C EEPROM is addressed for a read or write operation by first sending a control byte followed by the address byte
or bytes. The control byte is preceded by a start condition. The control byte and address byte(s) are each acknowledged
by the EEPROM slave. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set.
The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The control code is
1010b. For single byte addressing EEPROMs, the chip/block select bits are used for address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set low. The direction bit is set low to indicate the address
is being written.
Figure 8-3 illustrates typical I2C EEPROM addressing bit order for single and double byte addressing.
I2C EEPROM ADDRESSING
FIGURE 8-3:
Control Byte
A
A
A
A A
A A A A A A A A
C
0 C
0 9 8
K 7 6 5 4 3 2 1 0 K
S 1 0 1 0 1
A A A A A A A
Address Low
Byte
A
A
A A
A A A A A A A A
C
C
K 5 4 3 2 1 0 9 8 K 7 6 5 4 3 2 1 0 K
S 1 0 1 0 0 0 0 0 C 1 1 1 1 1 1
Chip / Block R/~W
Select Bits
Chip / Block R/~W
Select Bits
Single Byte Addressing
8.2.2.3
Address High
Byte
Control Byte
Address Byte
Double Byte Addressing
I2C EEPROM Byte Read
Following the device addressing, a data byte may be read from the EEPROM by outputting a start condition and control
byte with a control code of 1010b, chip/block select bits as described in Section 8.2.2.2, and the R/~W bit high. The
EEPROM will respond with an acknowledge, followed by 8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set.
The I2C master then sends a no-acknowledge, followed by a stop condition.
Figure 8-4 illustrates typical I2C EEPROM byte read for single and double byte addressing.
FIGURE 8-4:
I2C EEPROM BYTE READ
Data Byte
Control Byte
A
A
A
A A
D D D D D D D D A
C S 1 0 1 0 1
1 C
P
9
8
7 6 5 4 3 2 1 0 C
K
0
K
K
Chip / Block
Select Bits
R/~W
Single Byte Addressing Read
Control Byte
Data Byte
A
A
D D D D D D D D A
C S 1 0 1 0 0 0 0 1 C
P
7 6 5 4 3 2 1 0 C
K
K
K
Chip / Block R/~W
Select Bits
Double Byte Addressing Read
For a register level description of a read operation, refer to Section 8.2.1, "EEPROM Controller Operation," on page 83.
8.2.2.4
I2C EEPROM Sequential Byte Reads
Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting a start condition
and control byte with a control code of 1010b, chip/block select bits as described in Section 8.2.2.2, and the R/~W bit
high. The EEPROM will respond with an acknowledge, followed by 8-bits of data. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register
(E2P_CMD) is set. The I2C master then sends an acknowledge, and the EEPROM responds with the next 8-bits of data.
This continues until the last desired byte is read, at which point the I2C master sends a no-acknowledge, followed by a
stop condition.
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LAN9313/LAN9313i
Figure 8-5 illustrates typical I2C EEPROM sequential byte reads for single and double byte addressing.
I2C EEPROM SEQUENTIAL BYTE READS
FIGURE 8-5:
Data Byte
Control Byte
Data Byte
A
A
A
A
A
A A
D D D D D D D D
D D D D D D D D
C S 1 0 1 0 1
C
C
1 C
K
0 9 8
K 7 6 5 4 3 2 1 0 K 7 6 5 4 3 2 1 0 K
Data Byte
...
D D D D D D D D A
P
7 6 5 4 3 2 1 0 C
K
Chip / Block R/~W
Select Bits
Single Byte Addressing Sequential Reads
Data Byte
Control Byte
Data Byte
A
A
A
A
D D D D D D D D
D D D D D D D D
C S 1 0 1 0 0 0 0 1 C
C
C
K
K 7 6 5 4 3 2 1 0 K 7 6 5 4 3 2 1 0 K
Data Byte
...
D D D D D D D D A
P
7 6 5 4 3 2 1 0 C
K
Chip / Block R/~W
Select Bits
Double Byte Addressing Sequential Reads
Sequential reads are used by the EEPROM Loader. Refer to Section 8.2.4, "EEPROM Loader" for additional information.
For a register level description of a read operation, refer to Section 8.2.1, "EEPROM Controller Operation," on page 83.
8.2.2.5
I2C EEPROM Byte Writes
Following the device addressing, a data byte may be written to the EEPROM by outputting the data after receiving the
acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM slave and the I2C master finishes
the write cycle with a stop condition. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted
and the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set.
Following the data byte write cycle, the I2C master will poll the EEPROM to determine when the byte write is finished.
A start condition is sent followed by a control byte with a control code of 1010b, chip/block select bits low, and the R/~W
bit low. If the EEPROM is finished with the byte write, it will respond with an acknowledge. Otherwise, it will respond with
a no-acknowledge and the I2C master will repeat the poll. If the acknowledge does not occur within 30mS, a time-out
occurs. Once the I2C master receives the acknowledge, it concludes by sending a start condition, followed by a stop
condition, which will place the EEPROM into standby.
Figure 8-6 illustrates typical I2C EEPROM byte write.
FIGURE 8-6:
I2C EEPROM BYTE WRITE
Conclude
Data Cycle
Data Byte
Poll Cycle
Poll Cycle
Poll Cycle
Control Byte
Control Byte
Control Byte
A
A
A
A
D D D D D D D D
C
C P S 1 0 1 0 0 0 0 0 C S 1 0 1 0 0 0 0 0 C
7
6
5
4
3
2
1
0
K
K
K
K
Chip / Block R/~W
Select Bits
...
Chip / Block R/~W
Select Bits
A
S 1 0 1 0 0 0 0 0 C S P
K
Chip / Block R/~W
Select Bits
For a register level description of a write operation, refer to Section 8.2.1, "EEPROM Controller Operation," on page 83.
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LAN9313/LAN9313i
8.2.3
MICROWIRE EEPROM
Based on the configuration strap eeprom_type_strap, various sized Microwire EEPROMs are supported. The varying
size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the EEPROM Command Register
(E2P_CMD). Within each size range, the largest EEPROM uses all the address bits, while the smaller EEPROMs treat
the upper address bits as don’t cares. The EEPROM controller drives all the address bits as requested regardless of
the actual size of the EEPROM. The supported size ranges for Microwire operation are shown in Table 8-3.
TABLE 8-3:
MICROWIRE EEPROM SIZE RANGES
EEPROM_SIZE_STRAP[1:0]
# of Address Bits
EEPROM Size
EEPROM Types
00
7
128 x 8
93xx46A
01
9
256 x 8 and 512 x 8
93xx56A, 93xx66A
10
11
1024 x 8 and 2048 x 8
93xx76A, 93xx86A
11
RESERVED
Refer to Section 14.5.4, "Microwire Timing," on page 258 for detailed Microwire timing information.
8.2.3.1
Microwire Master Commands
Table 8-4, Table 8-5, and Table 8-6 detail the Microwire command set, including the number of clock cycles required, for
7, 9, and 11 address bits respectively. These commands are detailed in the following sections as well as in Section
13.1.3.1, "EEPROM Command Register (E2P_CMD)," on page 133.
TABLE 8-4:
INST
MICROWIRE COMMAND SET FOR 7 ADDRESS BITS
Start Bit
OPCODE
Address
Data to
EEPROM
Data from
EEPROM
# Of
Clocks
ERASE
1
11
A6 A5 A4 A3 A2 A1 A0
-
(RDY/~BSY)
10
ERAL
1
00
1 0 X X X X X
-
(RDY/~BSY)
10
EWDS
1
00
0 0 X X X X X
-
Hi-Z
10
EWEN
1
00
1 1 X X X X X
-
Hi-Z
10
READ
1
10
A6 A5 A4 A3 A2 A1 A0
-
D7 - D0
18
WRITE
1
01
A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/~BSY)
18
WRAL
1
00
0 1 X X X X X
D7 - D0
(RDY/~BSY)
18
TABLE 8-5:
MICROWIRE COMMAND SET FOR 9 ADDRESS BITS
OPCODE
Address
Data to
EEPROM
Data from
EEPROM
# Of
Clocks
1
11
A8 A7 A6 A5 A4 A3 A2 A1 A0
-
(RDY/~BSY)
12
1
00
1 0 X X X X X X X
-
(RDY/~BSY)
12
EWDS
1
00
0 0 X X X X X X X
-
Hi-Z
12
EWEN
1
00
1 1 X X X X X X X
-
Hi-Z
12
INST
Start Bit
ERASE
ERAL
READ
1
10
A8 A7 A6 A5 A4 A3 A2 A1 A0
-
D7 - D0
20
WRITE
1
01
A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/~BSY)
20
WRAL
1
00
0 1 X X X X X X X
D7 - D0
(RDY/~BSY)
20
TABLE 8-6:
MICROWIRE COMMAND SET FOR 11 ADDRESS BITS
INST
Start Bit
OPCODE
Address
Data to
EEPROM
Data from
EEPROM
# Of
Clocks
ERASE
1
11
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
-
(RDY/~BSY)
14
ERAL
1
00
1 0 X X X X X X X X X
-
(RDY/~BSY)
14
EWDS
1
00
0 0 X X X X X X X X X
-
Hi-Z
14
EWEN
1
00
1 1 X X X X X X X X X
-
Hi-Z
14
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LAN9313/LAN9313i
TABLE 8-6:
MICROWIRE COMMAND SET FOR 11 ADDRESS BITS (CONTINUED)
INST
Start Bit
OPCODE
Address
Data to
EEPROM
Data from
EEPROM
# Of
Clocks
READ
1
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
-
D7 - D0
22
WRITE
1
01
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/~BSY)
22
WRAL
1
00
0 1 X X X X X X X X X
D7 - D0
(RDY/~BSY)
22
8.2.3.2
ERASE (Erase Location)
If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit is set if the EEPROM does not
respond within 30mS.
FIGURE 8-7:
EEPROM ERASE CYCLE
EECS
EECLK
EEDO
1
1
1
Ax
A0
EEDI
8.2.3.3
ERAL (Erase All)
If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.
The EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the EEPROM does not respond within
30mS.
FIGURE 8-8:
EEPROM ERAL CYCLE
EECS
EECLK
EEDO
1
0
0
1
0
EEDI
DS00002288A-page 90
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
8.2.3.4
EWDS (Erase/Write Disable)
After this command is issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations,
the EWEN command must be issued.
FIGURE 8-9:
EEPROM EWDS CYCLE
EECS
EECLK
EEDO
1
0
0
0
0
EEDI
8.2.3.5
EWEN (Erase/Write Enable)
This command enables the EEPROM for erase and write operations. The EEPROM will allow erase and write operations until the EWDS command is sent, or until power is cycled.
Note:
The EEPROM will power-up in the erase/write disabled state. Any erase or write operations will fail until an
EWEN command is issued.
FIGURE 8-10:
EEPROM EWEN CYCLE
EECS
EECLK
EEDO
1
0
0
1
1
EEDI
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LAN9313/LAN9313i
8.2.3.6
READ (Read Location)
This command will cause a read of the EEPROM location pointed to by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The result of the read is available in the EEPROM Data Register (E2P_DATA).
FIGURE 8-11:
EEPROM READ CYCLE
EECS
EECLK
EEDO
1
1
0
Ax
A0
EEDI
8.2.3.7
D7
D0
WRITE (Write Location)
If erase/write operations are enabled in the EEPROM, this command will cause the contents of the EEPROM Data Register (E2P_DATA) to be written to the EEPROM location pointed to by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the
EEPROM does not respond within 30mS.
FIGURE 8-12:
EEPROM WRITE CYCLE
EECS
EECLK
EEDO
1
0
1
Ax
A0
D7
D0
EEDI
DS00002288A-page 92
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LAN9313/LAN9313i
8.2.3.8
WRAL (Write All)
If erase/write operations are enabled in the EEPROM, this command will cause the contents of the EEPROM Data Register (E2P_DATA) to be written to every EEPROM memory location. The EPC_TIMEOUT bit of the EEPROM Command
Register (E2P_CMD) is set if the EEPROM does not respond within 30mS.
FIGURE 8-13:
EEPROM WRAL CYCLE
EECS
EECLK
EEDO
1
0
0
0
D7
1
D0
EEDI
8.2.4
EEPROM LOADER
The EEPROM Loader interfaces to the I2C/Microwire EEPROM controller, the PHYs, and to the system CSRs (via the
Register Access MUX). All system CSRs are accessible to the EEPROM Loader.
The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the Reset
Control Register (RESET_CTL)), or upon the issuance of a RELOAD command via the EEPROM Command Register
(E2P_CMD). Refer to Section 4.2, "Resets," on page 30 for additional information on the LAN9313/LAN9313i resets.
The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An overview of the
EEPROM content format is shown in Table 8-7. Each section of EEPROM contents is discussed in detail in the following
sections.
TABLE 8-7:
EEPROM CONTENTS FORMAT OVERVIEW
EEPROM Address
0
Value
EEPROM Valid Flag
A5h
1
MAC Address Low Word [7:0]
1st
2
MAC Address Low Word [15:8]
2nd Byte on the Network
3
MAC Address Low Word [23:16]
3rd Byte on the Network
4
MAC Address Low Word [31:24]
4th Byte on the Network
5
MAC Address High Word [7:0]
5th Byte on the Network
6
MAC Address High Word [15:8]
6th Byte on the Network
7
8 - 11
Configuration Strap Values Valid Flag
Configuration Strap Values
Byte on the Network
A5h
See Table 8-8
12
Burst Sequence Valid Flag
13
Number of Bursts
See Section 8.2.4.5, "Register
Data"
Burst Data
See Section 8.2.4.5, "Register
Data"
14 and above
8.2.4.1
Description
A5h
EEPROM Loader Operation
Upon a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the Reset Control Register
(RESET_CTL)), or upon the issuance of a RELOAD command via the EEPROM Command Register (E2P_CMD), the
EPC_BUSY bit in the EEPROM Command Register (E2P_CMD) will be set. While the EEPROM Loader is active, the
READY bit of the Hardware Configuration Register (HW_CFG) is cleared and no writes to the LAN9313/LAN9313i
should be attempted. The operational flow of the EEPROM Loader can be seen in Figure 8-14.
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
FIGURE 8-14:
EEPROM LOADER FLOW DIAGRAM
DIGITAL_RST, nRST,
POR, RELOAD
EPC_BUSY = 1
Read Byte 0
Byte 0 = A5h
N
Load PHY registers with
current straps
Y
Read Bytes 1-6
EPC_BUSY = 0
Write Bytes 1-6 into
switch MAC Address
Registers
Read Bytes 7-11
Byte 7 = A5h
N
Load PHY registers with
current straps
Y
Write Bytes 8-11 into
Configuration Strap
registers
Update PHY registers
Update VPHY registers
Update LED_CFG,
MANUAL_FC_1,
MANUAL_FC_2 and
MANUAL_FC_mii
registers
Read Byte 12
Byte 12 = A5h
N
Y
Perform register data
load loop
DS00002288A-page 94
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LAN9313/LAN9313i
8.2.4.2
EEPROM Valid Flag
Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader starts by reading
the first byte of data from the EEPROM. If the value of A5h is not read from the first byte, the EEPROM Loader will load
the current configuration strap values into the PHY registers (see Section 8.2.4.4.1) and then terminate, clearing the
EPC_BUSY bit in the EEPROM Command Register (E2P_CMD). Otherwise, the EEPROM Loader will continue reading
sequential bytes from the EEPROM.
8.2.4.3
MAC Address
The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the Switch Fabric MAC Address High
Register (SWITCH_MAC_ADDRH) and Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL). The
EEPROM bytes are written into the MAC address registers in the order specified in Table 8-7.
8.2.4.4
Soft-Straps
7th
The
byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this byte has a value
of A5h, the next 4 bytes of data (8-11) are written into the configuration strap registers per the assignments detailed in
Table 8-8. If the flag byte is not A5h, these next 4 bytes are skipped (they are still read to maintain the data burst, but
are discarded). However, the current configuration strap values are still loaded into the PHY registers (see
Section 8.2.4.4.1). Refer to Section 4.2.4, "Configuration Straps," on page 33 for more information on the
LAN9313/LAN9313i configuration straps.
TABLE 8-8:
EEPROM CONFIGURATION BITS
Byte/Bit
7
6
5
4
3
2
1
0
Byte 8
BP_EN_
strap_1
FD_FC_
strap_1
manual_
FC_strap_1
manual_mdix_
strap_1
auto_mdix_str
ap_1
speed_
strap_1
duplex_
strap_1
autoneg_
strap_1
Byte 9
BP_EN_
strap_2
FD_FC_
strap_2
manual_
FC_strap_2
manual_mdix_
strap_2
auto_mdix_str
ap_2
speed_
strap_2
duplex_
strap_2
autoneg_
strap_2
BP_EN_
strap_mii
FD_FC_
strap_mii
manual_FC_s
trap_mii
speed_
strap_mii
duplex_pol_
strap_mii
SQE_test_
disable_strap_
mii
Byte 10
LED_fun_strap[1:0]
Byte 11
8.2.4.4.1
LED_en_strap[7:0]
PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency between the updated
configuration strap registers and the PHY registers, the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x), Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x), and Port x PHY Basic Control
Register (PHY_BASIC_CONTROL_x) are written when the EEPROM Loader is run.
The Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) is written with the new defaults as detailed
in Section 13.2.2.5, "Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 180.
The Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) is written with the new defaults as detailed in Section 13.2.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on page 184.
The Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is written with the new defaults as detailed in Section 13.2.2.1, "Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)," on page 176. Additionally, the Restart
Auto-negotiation bit is set in this register. This re-runs the Auto-negotiation using the new default values of the Port x
PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) register to determine the new Auto-negotiation
results.
Note:
8.2.4.4.2
Each of these PHY registers is written in its entirety, overwriting any previously changed bits.
Virtual PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency between the updated
configuration strap registers and the Virtual PHY registers, the Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV), Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS), and Virtual
PHY Basic Control Register (VPHY_BASIC_CTRL) are written when the EEPROM Loader is run.
The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) is written with the new defaults as detailed
in Section 13.1.7.5, "Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page 166.
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LAN9313/LAN9313i
The Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is written with the new
defaults as detailed in Section 13.1.7.8, "Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)," on page 170.
The Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is written with the new defaults as detailed in Section
13.1.7.1, "Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)," on page 162. Additionally, the Restart Autonegotiation bit is set in this register. This re-runs the Auto-negotiation using the new default values of the Virtual PHY
Auto-Negotiation Advertisement Register (VPHY_AN_ADV) register to determine the new Auto-negotiation results.
Note:
Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.
8.2.4.4.3
LED and Manual Flow Control Register Synchronization
Since the defaults of the LED Configuration Register (LED_CFG), Port 1 Manual Flow Control Register (MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), and Port 0(External MII) Manual Flow Control Register
(MANUAL_FC_MII) are based on configuration straps, the EEPROM Loader reloads these registers with their new
default values.
8.2.4.5
Register Data
Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the
LAN9313/LAN9313i parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine
registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space).
This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a value of A5h, the data
that follows is recognized as a sequence of bursts. Otherwise, the EEPROM Loader is finished, will go into a wait state,
and clear the EPC_BUSY bit in the EEPROM Command Register (E2P_CMD). This can optionally generate an interrupt.
The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte is the total number
of bursts. Following this is a series of bursts, each consisting of a starting address, count, and the count x 4 bytes of
data. This results in the following formula for formatting register data:
8-bits number_of_bursts
repeat (number_of_bursts)
16-bits {starting_address[9:2] / count[7:0]}
repeat (count)
8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0]
Note:
The starting address is a DWORD address. Appending two 0 bits will form the register address.
As an example, the following is a 3 burst sequence, with 1, 2, and 3 DWORDs starting at register addresses 40h, 80h,
and C0h respectively:
A5h, (Burst Sequence Valid Flag)
3h, (number_of_bursts)
16{10h, 1h}, (starting_address1 divided by 4 / count1)
11h, 12h, 13h, 14h, (4 x count1 of data)
16{20h, 2h}, (starting_address2 divided by 4 / count2)
21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data)
16{30h, 3h}, (starting_address3 divided by 4 / count3)
31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data)
In order to avoid overwriting the Switch CSR register interface or the PHY Management Interface (PMI), the EEPROM
Loader waits until the CSR Busy bit of the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) and
the MII Busy bit of the PHY Management Interface Access Register (PMI_ACCESS) are cleared before performing any
register write.
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LAN9313/LAN9313i
The EEPROM Loader checks that the EEPROM address space is not exceeded. If so, it will stop and set the EEPROM
Loader Address Overflow bit in the EEPROM Command Register (E2P_CMD). The address limit is based on the
eeprom_size_strap which specifies a range of sizes. The address limit is set to the largest value of the specified range.
8.2.4.6
EEPROM Loader Finished Wait-State
Once finished with the last burst, the EEPROM Loader will go into a wait-state and the EPC_BUSY bit of the EEPROM
Command Register (E2P_CMD) will be cleared.
8.2.4.7
Reset Sequence and EEPROM Loader
In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and maintain consistency with the PHY and Virtual PHY registers, the following sequence is used:
1.
After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9313/LAN9313i as specified in Section 14.5.2, "Reset and Configuration Strap Timing," on page 257.
After the PLL is stable, the main chip reset is released and the EEPROM Loader reads the EEPROM and configures (overrides) the strap inputs.
The EEPROM Loader writes select Port 1/2 and Virtual PHY registers, as specified in Section 8.2.4.4.1 and
Section 8.2.4.4.2, respectively.
2.
3.
Note:
8.3
Step 3 is also performed in the case of a RELOAD command or digital reset.
SPI/I2C Slave Controller
The SPI/I2C slave controller functionality is dependant on the management mode of the LAN9313/LAN9313i. When in
MAC/PHY I2C managed modes, the I2C controller is enabled. When in MAC/PHY SPI managed modes, the SPI controller is enabled. The SPI/I2C serial management pins functionality and characteristics differ dependant on the selected
modes as summarized in Table 8-9.
TABLE 8-9:
SPI / I2C SLAVE SERIAL MANAGEMENT PINS CHARACTERISTICS
Mode (S)
SI/SDA Pin
SO Pin
nSCS Pin
SCK/SCL Pin
MAC/PHY Modes
Unmanaged
NOT USED
NOT USED
NOT USED
NOT USED
Input disabled
Input disabled
Input disabled
MAC/PHY Modes
SMI Managed
Output disabled
Output enabled
(driven low)
Pull-up enabled
Pull-up enabled
MAC/PHY Modes
SPI Managed
SI
SO
nSCS
SCK
Input to SPI slave
Three-state output
from SPI slave
Input to SPI slave
Input to SPI slave
Pull-up enabled
Pull-up enabled
NOT USED
NOT USED
SCL
Output enabled
(driven low)
Input disabled
Input to I2C slave
Pull-up enabled
Pull-up disabled
Pull-up enabled
Output disabled
Pull-up enabled
MAC/PHY Modes
I2C Managed
SDA
Input to
I2C
slave
Open-drain output
from I2C slave
Pull-up disabled
Details on the various management modes and their configuration settings are provided in Section 2.3, "Modes of Operation," on page 12.
8.4
SPI Slave Operation
When in MAC/PHY SPI managed mode, the SPI slave interface is used for CPU management of the
LAN9313/LAN9313i. All system CSRs are accessible to the CPU in these modes. SPI mode is selected when the
mngt_mode_strap[1:0] inputs are set to 11b. The SPI slave interface supports single register and multiple register read
and write commands. Multiple read and multiple write commands support incrementing, decrementing, and static
addressing.
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Input data on the SI pin is sampled on the rising edge of the SCK input clock. Output data is sourced on the SO pin with
the falling edge of the clock. The SCK input clock can be either an active high pulse or an active low pulse. When the
nSCS chip select input is high, the SI input pin is ignored and the SO output pin is three-stated.
A read or write command is started on the first rising edge of the input clock after nSCS goes low. An 8-bit instruction is
then driven onto the line followed by an 8-bit register address field. All registers are accessed as DWORDs. Appending
two 0 bits to the address field will form the register address. This is followed by one or more 32-bit data fields. All registers are accessed as DWORDs. All instructions, addresses and data are transferred with the most-significant bit (msb)
first. Data is transferred with the most-significant byte (MSB) first (little endian).
The SPI interface supports up to a 10MHz input clock. A detailed SPI timing diagram is provided in Section 14.5.5, "SPI
Slave Timing," on page 259.
The SPI instructions supported by the LAN9313/LAN9313i are listed in Table 8-10. Unsupported instructions are must
not be used.
TABLE 8-10:
SUPPORTED SPI INSTRUCTIONS
Instruction
Format
READ
0000 0011
Read register at the specified address.
Multiple reads maintain the same address.
READ_INC
0000 0111
Read register(s) starting at the specified address.
Multiple reads auto-increment address.
READ_DEC
0000 1011
Read register(s) starting at the specified address.
Multiple reads auto-decrement address.
WRITE
0000 0010
Write register at the specified address.
Multiple writes maintain the same address.
WRITE_INC
0000 0110
Write register(s) starting at the specified address.
Multiple writes auto-increment address.
WRITE_DEC
0000 1010
Write register(s) starting at the specified address.
Multiple writes auto-decrement address.
8.4.1
Description
SPI READ SEQUENCE
The SPI slave interface of the LAN9313/LAN9313i is selected for reads by first bringing nSCS low. The SI pin should
then driven with an 8-bit read instruction, followed by the 8-bit address. On the falling clock edge which follows the rising
edge of the last address bit, the SO output is driven starting with the msb of the selected register. The remaining register
bits are shifted out on subsequent falling clock edges.
Multiple reads are performed by continuing the clock pulses while nSCS is low. Depending on the instruction (as shown
in Table 8-10), the internal address is incremented, decremented, or maintained. Maintaining a fixed internal address is
useful for register polling. For auto-incrementing instructions, once the internal address reaches its maximum, it rolls
over to 0. For auto-decrementing instructions, once the internal address reaches 0, it rolls over to its maximum.
The nSCS input is brought high to conclude the cycle. The SO output pin is three-stated at this time.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read to prevent the
host from reading an intermediate value. The latching occurs multiple times in a multiple read sequence. In addition,
any register that is affected by a read operation (e.g. a clear on read bit) is not cleared until after all 32-bits are output.
In the event that 32-bits are not read when the nSCS is returned high, the read is considered invalid and the register is
not affected. Multiple registers may be cleared in a multiple read cycle, each one being cleared as it is read.
SPI reads from unused register addresses return as all zeros.
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LAN9313/LAN9313i
Figure 8-15 illustrates a typical single and multiple register read.
FIGURE 8-15:
SPI READS
nSCS
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
7
5
6
8
7
1
0
9
1
1
1
2
9
1
0
1
1
A9
A8
A7
8
1
2
Instruction
SI
X
0
0
0
0
0
1
3
1
4
1
3
1
5
1
6
1
7
1
4
1
5
1
6
A4
A3
A2
1
8
1
9
1
7
1
8
Address
0
1
1
A6
A5
X
...
...
...
4
5
1
9
4
6
4
5
4
7
4
6
4
8
4
7
X
4
8
X
D0 X
Z
X
Data
SO
D
31
Z
D
30
D
29
...
D2
D1
Single Register Read
nSCS
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
7
5
6
8
7
1
0
9
8
9
1
1
1
0
1
2
1
1
Instruction
SI
X
0
0
0
0
dec
inc
1
3
1
2
1
4
1
3
1
5
1
6
1
7
1
4
1
5
1
6
A4
A3
A2
1
8
1
7
1
9
1
8
Address
1
1
A9
A8
A7
A6
A5
X
...
...
...
1
9
Data 1...
SO
D
31
Z
D
30
...
...
...
D
29
X
…Data m
...
D2
D1
Data m+1...
D0
D
31
D
30
D
29
...
X
X
X
…Data n
D2
D1
D0 X Z
Multiple Register Reads
8.4.1.1
SPI Read Polling for Reset Complete
During reset, the SPI slave interface will not return valid data. To determine when the reset condition is complete, the
Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the READY bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device initialization is complete. Refer to Section 4.2, "Resets," on page 30 for additional information.
8.4.2
SPI WRITE SEQUENCE
The SPI slave interface of the LAN9313/LAN9313i is selected for writes by first bringing nSCS low. The SI pin should
then driven with an 8-bit write instruction, followed by the 8-bit address and then the data.
Multiple writes are performed by continuing the clock pulses and input data while nSCS is low. Depending on the instruction (as shown in Table 8-10), the internal address is incremented, decremented, or maintained. Maintaining an fixed
internal address is useful for “bit-banging”. For auto-incrementing instructions, once the internal address reaches its
maximum, it rolls over to 0. For auto-decrementing instructions, once the internal address reaches 0, it rolls over to its
maximum.
The nSCS input is brought high to conclude the cycle. The SO output is three-stated throughout the entire write
sequence.
The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written when the nSCS
is returned high, the write is considered invalid and the register is not affected. Multiple registers may be written in a
multiple write cycle, each one being written after 32-bits.
SPI writes must not be performed to unused register addresses.
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
Figure 8-16 illustrates a typical single and multiple register write.
FIGURE 8-16:
SPI WRITES
nSCS
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
7
5
8
6
7
1
0
9
8
1
1
1
2
9
1
0
1
1
A9
A8
A7
1
2
Instruction
SI
X
0
0
0
0
0
1
3
1
4
1
3
1
5
1
6
1
7
1
8
1
9
1
4
1
5
1
6
1
7
1
8
A4
A3
A2
D
31
D
30
1
8
1
9
Address
0
1
1
A6
SO
A5
...
...
...
4
5
1
9
4
6
4
5
4
7
4
8
X
4
6
4
7
4
8
D2
D1
D0
X
Data
D
29
X
Z
Single Register Write
nSCS
SCK (active low)
X
SCK (active high)
X
1
2
1
3
2
4
3
5
4
6
7
5
6
8
7
1
0
9
8
9
1
1
1
0
1
2
1
1
Instruction
SI
X
0
0
0
0
dec
inc
1
3
1
2
1
4
1
3
1
5
1
4
1
6
1
5
1
7
1
6
1
7
Address
1
1
A9
A8
SO
A7
A6
A5
1
8
...
...
...
1
9
Data 1...
A4
A3
A2
D
31
D
30
D
29
...Data m
D2
D1
...
...
...
...Data m+1
D0
D
31
D
30
D
29
X
X
...Data n
D2
D1
D0
X
Z
Multiple Register Writes
8.5
I2C Slave Operation
When in MAC/PHY I2C managed mode, the I2C slave interface is used for CPU management of the
LAN9313/LAN9313i. All system CSRs are accessible to the CPU in these modes. I2C mode is selected when the mngt_mode_strap[1:0] inputs are set to 10b. The I2C slave controller implements the low level I2C slave serial interface (start
and stop condition detection, data bit transmission and reception, and acknowledge generation and reception), handles
the slave command protocol, and performs system register reads and writes. The I2C slave controller conforms to the
Philips I2C-Bus Specification.
The I2C slave serial interface consists of a data wire (SDA) and a serial clock (SCL). The serial clock is driven by the
master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up resistors. Both signals include Schmitt trigger inputs and digital input filters. The digital filters reject pulses that are less than 100nS.
The I2C slave serial interface supports the standard-mode speed of up to 100KHz and the fast-mode speed of 400KHz.
Refer to the Philips I2C-Bus Specification for detailed I2C timing information.
8.5.1
I2C SLAVE COMMAND FORMAT
The I2C slave serial interface supports single register and multiple register read and write commands. A read or write
command is started by the master first sending a start condition, followed by a control byte. The control byte consists of
a 7-bit slave address and a 1-bit read/write indication (R/~W). The slave address used by the LAN9313/LAN9313i is
0001010b, written as SA6 (first bit on the wire) through SA0 (last bit on the wire). Assuming the slave address in the
control byte matches this address, the control byte is acknowledged by the LAN9313/LAN9313i. Otherwise, the entire
sequence is ignored until the next start condition. The I2C command format can be seen in Figure 8-17.
If the read/write indication (R/~W) in the control byte is a 0 (indicating a potential write), the next byte sent by the master
is the register address. After the address byte is acknowledged by the LAN9313/LAN9313i, the master may either send
data bytes to be written, or it may send another start condition (to start the reading of data), or a stop condition. The
latter two will terminate the current write (without writing any data), but will have the affect of setting the internal register
address which will be used for subsequent reads.
If the read/write indication in the control byte is a 1 (indicating a read), the LAN9313/LAN9313i will start sending data
following the control byte acknowledgement.
DS00002288A-page 100
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LAN9313/LAN9313i
Note:
All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the register
address. Addresses and data are transferred msb first. Data is transferred MSB first (little endian).
FIGURE 8-17:
I2C SLAVE ADDRESSING
Control Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
Address Byte
S
A
0
0
A
C
K
R/~W
8.5.2
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
*
Start or
Stop or
Data [31]
I2C SLAVE READ SEQUENCE
Following the device addressing, as detailed in Section 8.5.1, a register is read from the LAN9313/LAN9313i when the
master sends a start condition and control byte with the R/~W bit set. Assuming the slave address in the control byte
matches the LAN9313/LAN9313i address, the control byte is acknowledged by the LAN9313/LAN9313i. Otherwise, the
entire sequence is ignored until the next start condition. Following the acknowledge, the LAN9313/LAN9313i sends 4
bytes of data. The first 3 bytes are acknowledged by the master and on the fourth, the master sends a no-acknowledge
followed by the stop condition. The no-acknowledge informs the LAN9313/LAN9313i not to send the next 4 bytes (as it
would in the case of a multiple read). The internal register address is unchanged following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal address is incremented and the next register is shifted out. Once the internal address reaches its maximum, it rolls over to 0. The multiple read is concluded when the master sends a no-acknowledge followed by a stop condition. The no-acknowledge
informs the LAN9313/LAN9313i not to send the next 4 bytes. The internal register address in incremented for each read
including the final.
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the first three bytes
of the register, the LAN9313/LAN9313i will stop sending subsequent bytes. If the master sends an unexpected start or
stop condition, the LAN9313/LAN9313i will stop sending immediately and will respond to the next sequence as needed.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read to prevent the
host from reading an intermediate value. The latching occurs multiple times in a multiple read sequence. In addition,
any register that is affected by a read operation (e.g. a clear on read bit) is not cleared until after all 32-bits are output.
In the event that 32-bits are not read (master sends a no-acknowledge on one of the first three bytes or a start or stop
condition occurs unexpectedly), the read is considered invalid and the register is not affected. Multiple registers may be
cleared in a multiple read cycle, each one being cleared as it is read. I2C reads from unused register addresses return
all zeros.
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
Figure 8-18 illustrates a typical single and multiple register read.
I2C SLAVE READS
FIGURE 8-18:
Control Byte
S
A
6
S
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
Control Byte
Address Byte
S
A
0
A
C
K
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
C
K
A
2
S
A
6
S
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
Data Byte... ...Data Byte
Data Byte
S
A
0
1
A
C
K
D
3
1
D
3
0
D
2
9
D
2
8
S
2
7
D
2
6
D
2
5
D
2
4
A
C
K
D
2
3
D
2
2
D
2
1
D
2
0
...
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
R/~W
Single Register Read
Control Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
Control Byte
Address Byte
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
...Data m Byte
Data 1 Byte
S
A
0
1
A
C
K
D
3
1
D
3
0
...
D
2
5
D
2
4
A
C
K
...
D
4
D
3
D
2
D
1
Data m+1 Byte... ...Data n Byte
D
0
A
C
K
D
3
1
D
3
0
D
2
9
D
2
8
D
2
7
D
2
6
...
D
4
D
3
D
2
D
1
D
0
A
C
K
P
R/~W
Multiple Register Reads
8.5.2.1
I2C Slave Read Polling for Reset Complete
During reset, the I2C slave interface will not return valid data. To determine when the reset condition is complete, the
Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the READY bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device initialization is complete. Refer to Section 4.2, "Resets," on page 30 for additional information.
8.5.3
I2C SLAVE WRITE SEQUENCE
Following the device addressing, as detailed in Section 8.5.1, a register is written to the LAN9313/LAN9313i when the
master continues to send data bytes. Each byte is acknowledged by the LAN9313/LAN9313i. Following the fourth byte
of the sequence, the master may either send another start condition or halt the sequence with a stop condition. The
internal register address is unchanged following a single write.
Multiple writes are performed when the master sends additional bytes following the fourth acknowledge. The internal
address is automatically incremented and the next register is written. once the internal address reaches it maximum
value, it rolls over to 0. The multiple write is concluded when the master sends another start condition or stop condition.
The internal register address is incremented for each write including the final. This is not relevant for subsequent writes,
since a new register address would be included on a new write cycle. However, this does affect the internal register
address if it were to be used for reads without first resetting the register address.
For both single and multiple writes, if the master sends an unexpected start or stop condition, the LAN9313/LAN9313i
will stop immediately and will respond to the next sequence as needed.
The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written (master sends a
start, or a stop condition occurs unexpectedly), the write is considered invalid and the register is not affected. Multiple
registers may be written in a multiple write cycle, each one being written after 32-bits. I2C writes must not be performed
to unused register addresses.
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LAN9313/LAN9313i
Figure 8-19 illustrates a typical single and multiple register write.
I2C SLAVE WRITES
FIGURE 8-19:
Address Byte
Control Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
Data Byte... ...Data Byte
Data Byte
A
2
A D D D D S D D D A D D D D
C 3 3 2 2 2 2 2 2 C 2 2 2 2
K 1 0 9 8 7 6 5 4 K 3 2 1 0
...
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Single Register Write
Control Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
Address Byte
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
...Data m Byte
Data 1 Byte
A
3
A
2
A D D
C 3 3
K 1 0
...
D
2
5
D
2
4
A
C
K
...
D
5
D
4
D
3
D
2
D
1
Data m+1 Byte...
D
0
A
C
K
D
3
1
D
3
0
D
2
9
D
2
8
D
2
7
D
2
6
D
2
5
...Data n Byte
...
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
Multiple Register Writes
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
9.0
MII MANAGEMENT
9.1
Functional Overview
This chapter details the MII management functionality provided by the LAN9313/LAN9313i, which includes the SMI
Slave Controller, PHY Management Interface (PMI), and the MII Mode Multiplexer. The SMI Slave Controller is used
for CPU management of the LAN9313/LAN9313i via the MII pins, and allows CPU access to all system CSRs. The PHY
Management Interface (PMI) is used to access the internal PHYs and optional external PHY, dependant on the management mode. The PMI implements the IEEE 802.3 management protocol. The MII Mode Multiplexer is used to direct
the connections of the MII data path and MII management path based on the selected mode of the device.
9.2
SMI Slave Controller
The SMI slave controller uses the same pins and protocol as the IEEE 802.3 MII management function, and differs only
in that SMI provides access to all internal registers by using a non-standard extended addressing map. The SMI protocol
co-exists with the MII management protocol by using the upper half of the PHY address space (16 through 31). All direct
and indirect registers of the LAN9313/LAN9313i can be accessed. The SMI management mode is selected when the
mngt_mode_strap[1:0] inputs are set to 01b. A list of management modes and their configuration settings are discussed
in Section 2.3, "Modes of Operation," on page 12.
The MII management protocol is limited to 16-bit data accesses. The protocol is also limited to 5 PHY address bits and
5 register address bits. The SMI frame format can be seen in Table 9-1. The LAN9313/LAN9313i uses the PHY Address
field bits 3:0 as the system register address bits 9:6, and the Register Address field as the system register address bits
5:1. Therefore, Register Address field bit 0 is used as the upper/lower word select. The LAN9313/LAN9313i requires
two back-to-back accesses to each register (with alternate settings of Register Address field bit 0) which are combined
to form a 32-bit access. The access may be performed in any order.
Note:
When accessing the LAN9313/LAN9313i, the pair of cycles must be atomic. In this case, the first host SMI
cycle is performed to the low/high word and the second host SMI cycle is performed to the high/low word,
forming a 32-bit transaction with no cycles to the LAN9313/LAN9313i in between. With the exception of
Register Address field bit 0, all address and control bits must be the same for both 16-bit cycles of a 32-bit
transaction.
Input data on the MDIO pin is sampled on the rising edge of the MDC input clock. Output data is sourced on the MDIO
pin with the rising edge of the clock. The MDIO pin is three-stated unless actively driving read data.
A read or a write is performed using the frame format shown in Table 9-1. All addresses and data are transferred msb
first. Data bytes are transferred little endian. When Register Address bit 0 is 1, bytes 3 & 2 are selected with byte 3
occurring first. When Register Address bit 0 is 0, bytes 1 & 0 are selected with byte 1 occurring first.
TABLE 9-1:
SMI FRAME FORMAT
PHY
Address
Note 9-1
Register
Address
Note 9-1
TurnAround
Time
Note 9-2
Idle
Note 9
-3
Preamble
Start
Op
Code
READ
32 1’s
01
10
1AAAA
9876
AAAAA
54321
Z0
DDDDDDDDDDDDDDDD
1111110000000000
5432109876543210
Z
WRITE
32 1’s
01
01
1AAAA
9876
AAAAA
54321
10
DDDDDDDDDDDDDDDD
1111110000000000
5432109876543210
Z
Data
Note 9-1
PHY Address bit 4 is 1 for SMI commands. PHY Address 3:0 form system register address bits 9:6.
The Register Address field forms the system register address bits 5:1
Note 9-2
The turn-around time (TA) is used to avoid contention during a read cycle. For a read, the
LAN9313/LAN9313i drives the second bit of the turn-around time to 0, and then drives the msb of
the read data in the following clock cycle. For a write, the external host drives the first bit of the turnaround time to 1, the second bit of the turn-around time to 0, and then the msb of the write data in
the following clock cycle.
Note 9-3
In the IDLE condition, the MDIO output is three-stated and pulled high externally.
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LAN9313/LAN9313i
Note:
9.2.1
The SMI interface supports up to a 2.5MHz input clock. The MII/SMI timing adheres to the IEEE 802.3
specification. Refer to the IEEE 802.3 specification for detailed MII timing information.
READ SEQUENCE
In a read sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY Address, and the
5-bit Register Address. The next clock is the first bit of the turnaround time in which the LAN9313/LAN9313i continues
to three-state MDIO. On the next rising edge of MDC, the LAN9313/LAN9313i drives MDIO low. For the next 16 rising
edges, the LAN9313/LAN9313i drives the output data. On the final clock, the LAN9313/LAN9313i once again threestates MDIO.
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. No ordering requirements exist. The processor can access either the low or high word first, as long as the next read is performed
from the other word. If a read to the same word is performed, the combined data read pair is invalid and should be reread. This is not a fatal error. The LAN9313/LAN9313i will simply reset the read counters, and restart a new cycle on
the next read.
Note:
Select registers are readable as 16-bit registers, as noted in their register descriptions. For these registers,
only one 16-bit read may be performed without the need to read the other word.
Register values are latched (registered) at the beginning of each 16-bit read to prevent the host from reading an intermediate value. In addition, any register that is affected by a read operation, such as a clear on read bit, is not cleared
until after the end of the second read. In the event that 32-bits are not read, the read in considered invalid and the register is not affected.
Any register that may change between two consecutive host read cycles and spans across two WORDs, such as a
counter, is latched (registered) at the beginning of the first read and held until after the second read has completed. This
prevents the host from reading inconsistent data from the first and second half of a register. For example, if a counters
value is 01FFh, the first half will be read as 01h. If the counter then changes to 0200h, the host would read 00h, resulting
an the incorrect value of 0100h instead of either 01FFh or 0200h.
Note:
9.2.1.1
SMI reads from unused register addresses return all zeros. This differs from unused PHY registers which
leave MDIO un-driven.
SMI Read Polling for Reset Complete
During reset, the SMI slave interface will not return valid data. To determine when the reset condition is complete, the
Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the READY bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device initialization is complete. Refer to Section 4.2, "Resets," on page 30 for additional information.
Note:
9.2.2
In the event that a reset condition terminates between halves of 16-bit read pair, the LAN9313/LAN9313i
will not expect another 16-bit read to complete the DWORD cycle. Only specific registers may be read
during a reset. Refer to Section 4.2, "Resets," on page 30 for additional information.
WRITE SEQUENCE
In a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY Address, 5-bit
Register Address, 2-bit turn-around time, and finally the 16-bits of data. The MDIO pin is three-stated throughout the
write sequence.
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. No ordering requirement exists. The host may access either the low or high word first, as long as the next write is performed to
the opposite word. If a write to the same word is performed, the device disregards the transfer.
Note:
SMI writes must not be performed to unused register addresses.
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LAN9313/LAN9313i
9.3
PHY Management Interface (PMI)
The PHY Management Interface (PMI) is used to access the internal PHYs as well as the external PHY on the MII pins
(in MAC modes only). The PMI operates at 2.5MHz, and implements the IEEE 802.3 management protocol, providing
read/write commands for PHY configuration.
A read or write is performed using the frame format shown in Table 9-2. All addresses and data are transferred msb first.
Data bytes are transferred little endian.
TABLE 9-2:
MII MANAGEMENT FRAME FORMAT
PHY
Address
Register
Address
TurnAround
Time
Note 9-4
Data
Idle
Note 9
-5
Preamble
Start
Op
Code
READ
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
WRITE
32 1’s
01
01
AAAAA
RRRRR
10
DDDDDDDDDDDDDDDD
Z
Note 9-4
The turn-around time (TA) is used to avoid bus contention during a read cycle. For a read, the
external PHY drives the second bit of the turn-around time to 0, and then drives the msb of the read
data in the following cycle. For a write, the LAN9313/LAN9313i drives the first bit of the turnaround
time to 1, the second bit of the turnaround time to 0, and then the msb of the write data in the
following clock cycle.
Note 9-5
In the IDLE condition, the MDIO output is three-stated and pulled high externally.
The internal PHYs and optional external PHY (in MAC modes) are accessed via the PHY Management Interface Access
Register (PMI_ACCESS) and PHY Management Interface Data Register (PMI_DATA). These registers allow read and
write operations to all PHY registers. Refer to Section 13.1.6, "PHY Management Interface (PMI)," on page 159 for
detailed information on these registers.
9.3.1
EEPROM LOADER PHY REGISTER ACCESS
The PMI is also used by the EEPROM Loader to load the PHY registers with various configuration strap values. The
PHY Management Interface Access Register (PMI_ACCESS) and PHY Management Interface Data Register (PMI_DATA) are also accessible as part of the Register Data burst sequence of the EEPROM Loader. Refer to Section 8.2.4,
"EEPROM Loader," on page 93 for additional information.
9.4
MII Mode Multiplexer
The MII mode multiplexer is used to direct the MII data/management path connections. One master (MAC via the MII
pins, or PMI) is connected to the slaves (PHY via MII pins, Port 1/2 PHYs, Virtual PHY, and SMI slave) dependant on
the selected management mode of the LAN9313/LAN9313i. The MII mode multiplexer also performs the multiplexing
of the read data signals from the slaves and controls the output enable of the MII pins.
The following sections detail the operation of the MII mode multiplexer in each management mode. A list of management
modes and their configuration settings are discussed in Section 2.3, "Modes of Operation," on page 12.
9.4.1
MAC MODE UNMANAGED
In MAC mode unmanaged, no external accesses to the LAN9313/LAN9313i are required. The MII multiplexer is disabled and the MII management pins are not driven.
The Virtual PHY interface is accessible via the EEPROM Loader. Refer to Section 8.2.4, "EEPROM Loader," on page 93
for additional information.
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LAN9313/LAN9313i
Figure 9-1 details the MII multiplexer management path connections for this mode.
FIGURE 9-1:
MII MUX MANAGEMENT PATH CONNECTIONS - MAC MODE UNMANAGED
MII Pins
MDI
MDIO_DIR
SMI Slave
MDCLK
Parallel
Master
MDO
MDIO_ DIR
MDO
MDIO
MDI
MDC_DIR
MDI
MDC_ OUT
Virtual PHY
MDCLK
MDI
Parallel
Slave
MDO
MDIO_ DIR
MDC
MDC_IN
Management
Mode Selection
PHY2
MDO
MDIO_ DIR
MDCLK
MDI
PHY1
MDO
MDIO_ DIR
MDCLK
Management
Mode Selection
MDO MDCLK
MDI MDO_EnN
PMI
Parallel Slave
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LAN9313/LAN9313i
9.4.2
MAC MODE SMI MANAGED
In MAC mode SMI managed, the internal PHYs and SMI slave block are accessed via the MII management pins. The
Virtual PHY and PMI are not used in this mode.
The Virtual PHY interface is accessible via the SMI slave or the EEPROM Loader. Refer to Section 9.2, "SMI Slave Controller," on page 104 and Section 8.2.4, "EEPROM Loader," on page 93 for additional information.
Figure 9-2 details the MII multiplexer management path connections for this mode.
FIGURE 9-2:
MII MUX MANAGEMENT PATH CONNECTIONS - MAC MODE SMI MANAGED
MII Pins
MDI
MDIO_DIR
SMI Slave
MDCLK
Parallel
Master
MDO
MDIO_ DIR
MDO
MDIO
MDI
MDC_DIR
MDI
MDC_ OUT
Virtual PHY
MDCLK
MDI
Parallel
Slave
MDO
MDIO_ DIR
MDC
MDC_IN
Management
Mode Selection
PHY2
MDO
MDIO_ DIR
MDCLK
MDI
PHY1
MDO
MDIO_ DIR
MDCLK
Management
Mode Selection
MDO MDCLK
MDI MDO_EnN
PMI
Parallel Slave
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LAN9313/LAN9313i
9.4.3
MAC MODE I2C/SPI MANAGED
In MAC mode I2C or SPI managed, the internal PHYs and the external PHY are accessed via the PMI. The SMI slave
and the Virtual PHY are not used in these modes.
The Virtual PHY and PMI interfaces are accessible via the I2C/SPI slave interfaces or the EEPROM Loader. Refer to
Section 8.3, "SPI/I2C Slave Controller," on page 97 and Section 8.2.4, "EEPROM Loader," on page 93 for additional
information.
Figure 9-3 details the MII multiplexer management path connections for this mode.
FIGURE 9-3:
MII MUX MANAGEMENT PATH CONNECTIONS - MAC MODE I2C/SPI MANAGED
MII Pins
MDI
MDIO_DIR
SMI Slave
MDCLK
Parallel
Master
MDO
MDIO_ DIR
MDO
MDIO
MDI
MDC_DIR
MDI
MDC_ OUT
Virtual PHY
MDCLK
MDI
Parallel
Slave
MDO
MDIO_ DIR
MDC
MDC_IN
Management
Mode Selection
PHY2
MDO
MDIO_ DIR
MDCLK
MDI
PHY1
MDO
MDIO_ DIR
MDCLK
Management
Mode Selection
MDO MDCLK
MDI MDO_EnN
PMI
Parallel Slave
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LAN9313/LAN9313i
9.4.4
PHY MODE UNMANAGED
In PHY mode unmanaged, the Virtual PHY is accessed via the external MII management pins. The Port 1/2 PHYs, SMI
slave, and the PMI are not used in this mode.
The Virtual PHY interface is accessible via the EEPROM Loader. Refer to Section 8.2.4, "EEPROM Loader," on page 93
for additional information.
Figure 9-4 details the MII multiplexer management path connections for this mode.
FIGURE 9-4:
MII MUX MANAGEMENT PATH CONNECTIONS - PHY MODE UNMANAGED
MII Pins
MDI
MDIO_DIR
SMI Slave
MDCLK
Parallel
Master
MDO
MDIO_ DIR
MDO
MDIO
MDI
MDC_DIR
MDI
MDC_ OUT
Virtual PHY
MDCLK
MDI
Parallel
Slave
MDO
MDIO_ DIR
MDC
MDC_IN
Management
Mode Selection
PHY2
MDO
MDIO_ DIR
MDCLK
MDI
PHY1
MDO
MDIO_ DIR
MDCLK
Management
Mode Selection
MDO MDCLK
MDI MDO_EnN
PMI
Parallel Slave
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LAN9313/LAN9313i
9.4.5
PHY MODE SMI MANAGED
In PHY mode SMI managed, the internal PHYs, Virtual PHY, and SMI slave block are accessed via the MII management
pins. The PMI is not used in this mode.
The Virtual PHY interface is accessible via the SMI slave or the EEPROM Loader. Refer to Section 9.2, "SMI Slave Controller," on page 104 and Section 8.2.4, "EEPROM Loader," on page 93 for additional information.
Figure 9-2 details the MII multiplexer management path connections for this mode.
FIGURE 9-5:
MII MUX MANAGEMENT PATH CONNECTIONS - PHY MODE SMI MANAGED
MII Pins
MDI
MDIO_DIR
SMI Slave
MDCLK
Parallel
Master
MDO
MDIO_ DIR
MDO
MDIO
MDI
MDC_DIR
MDI
MDC_ OUT
Virtual PHY
MDCLK
MDI
Parallel
Slave
MDO
MDIO_ DIR
MDC
MDC_IN
Management
Mode Selection
PHY2
MDO
MDIO_ DIR
MDCLK
MDI
PHY1
MDO
MDIO_ DIR
MDCLK
Management
Mode Selection
MDO MDCLK
MDI MDO_EnN
PMI
Parallel Slave
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LAN9313/LAN9313i
9.4.6
PHY MODE I2C/SPI MANAGED
In PHY mode I2C or SPI managed, the Port 1/2 PHYs are accessed via the PMI, and the Virtual PHY is accessed via
the external MII management pins. The SMI slave is not used in these modes.
The Virtual PHY and PMI parallel interfaces are accessible via the I2C/SPI slave interfaces or the EEPROM Loader.
Refer to Section 8.3, "SPI/I2C Slave Controller," on page 97 and Section 8.2.4, "EEPROM Loader," on page 93 for additional information.
Figure 9-3 details the MII multiplexer management path connections for this mode.
FIGURE 9-6:
MII MUX MANAGEMENT PATH CONNECTIONS - PHY MODE I2C/SPI MANAGED
MII Pins
MDI
MDIO_DIR
SMI Slave
MDCLK
Parallel
Master
MDO
MDIO_ DIR
MDO
MDIO
MDI
MDC_DIR
MDI
MDC_ OUT
Virtual PHY
MDCLK
MDI
Parallel
Slave
MDO
MDIO_ DIR
MDC
MDC_IN
Management
Mode Selection
PHY2
MDO
MDIO_ DIR
MDCLK
MDI
PHY1
MDO
MDIO_ DIR
MDCLK
Management
Mode Selection
MDO MDCLK
MDI MDO_EnN
PMI
Parallel Slave
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LAN9313/LAN9313i
10.0
IEEE 1588 HARDWARE TIME STAMP UNIT
10.1
Functional Overview
The LAN9313/LAN9313i provides hardware support for the IEEE 1588 Precision Time Protocol (PTP), allowing clock
synchronization with remote Ethernet devices, packet time stamping, and time driven event generation. Time stamping
is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any
port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9313/LAN9313i as a whole
may function as a boundary clock.
A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related functions. An
IEEE 1588 Clock/Events block provides IEEE 1588 clock comparison based interrupt generation and time stamp related
GPIO event generation. Two LAN9313/LAN9313i GPIO pins (GPIO[8:9]) can be used to trigger a time stamp capture
when configured as an input, or output a signal from the GPIO based on an IEEE 1588 clock target compare event when
configured as an output. Section 10.1.2, "Block Diagram" describes the various IEEE 1588 related blocks and how they
interface to other LAN9313/LAN9313i functions.
All features of the IEEE 1588 hardware time stamp unit can be monitored and configured via their respective configuration and status registers. A detailed description of all IEEE 1588 CSRs is included in Section 13.1.4, "IEEE 1588," on
page 136.
10.1.1
IEEE 1588
IEEE 1588 specifies a Precision Time Protocol (PTP) used by master and slave clock devices to pass time information
in order to achieve clock synchronization. Five network message types are defined:
•
•
•
•
•
Sync
Delay_Req
Follow_Up
Delay_Resp
Management
Only the first four message types (Sync, Delay_Req, Follow_Up, Delay_Resp) are used for clock synchronization. Using
these messages, the protocol software may calculate the offset and network delay between time stamps, adjusting the
slave clock frequency as needed. Refer to the IEEE 1588 protocol for message definitions and proper usage.
A PTP domain is segmented into PTP sub-domains, which are then segmented into PTP communication paths. Within
each PTP communication path there is a maximum of one master clock, which is the source of time for each slave clock.
The determination of which clock is the master and which clock(s) is(are) the slave(s) is not fixed, but determined by
the IEEE 1588 protocol. Similarly, each PTP sub-domain may have only one master clock, referred to as the Grand Master Clock.
PTP communication paths are conceptually equivalent to Ethernet collision domains and may contain devices which
extend the network. However, unlike Ethernet collision domains, the PTP communication path does not stop at a network switch, bridge, or router. This leads to a loss of precision when the network switch/bridge/router introduces a variable delay. Boundary clocks are defined which conceptually bypass the switch/bridge/router (either physically or via
device integration). Essentially, a boundary clock acts as a slave to an upstream master, and as a master to a down
stream slave. A boundary clock may contain multiple ports, but a maximum of one slave port is permitted.
For more information on the IEEE 1588 protocol, refer to the National Institute of Standards and Technology IEEE 1588
website:
https://www.nist.gov/el/intelligent-systems-division-73500/introduction-ieee-1588
10.1.2
BLOCK DIAGRAM
The LAN9313/LAN9313i IEEE 1588 implementation is illustrated in Figure 10-1, and consists of the following major
function blocks:
• IEEE 1588 Time Stamp
These three identical blocks provide time stamping functions on all switch fabric ports.
• IEEE 1588 Clock
This block provides a 64-bit tunable clock that is used as the time source for all IEEE 1588 time stamp related
functions.
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LAN9313/LAN9313i
• IEEE 1588 Clock/Events
This block provides IEEE 1588 clock comparison-based interrupt generation and time stamp related GPIO event
generation.
FIGURE 10-1:
IEEE 1588 BLOCK DIAGRAM
IEEE 1588
Time Stamp
MII
Port 0
10/100
PHY
Port 1
Ethernet
IEEE 1588
Time Stamp
MII
To External MAC/PHY
Switch Fabric
10/100
PHY
Port 2
Ethernet
MII
IEEE 1588 Time Stamp
RX
Sync / Delay_Req
Msg Detect RX
RX: Delay_Req for Master, Sync for Slave
TX
Sync / Delay_Req
Msg Detect TX
TX: Sync for Master, Delay_Req for Slave
IEEE 1588 Clock
Clock Capture RX
Src UUID Capture RX
Sequence ID Capture RX
IRQ Flag
Clock Capture TX
Src UUID Capture TX
Sequence ID Capture TX
IRQ Flag
32 Bit Addend
+
32 Bit Accumulator
inc
64 Bit Clock
carry
host
host
IEEE 1588 Clock Events
GPIO[8:9]
(Outputs)
GPIO[8:9]
(Inputs)
64 Bit Reload / Add
load / add
64 Bit Clock Target
compare >=
IRQ Flag
Clock Capture GPIO8
IRQ Flag
Clock Capture GPIO9
IRQ Flag
10.2
host
IRQ Flags
IRQ Enables
X9
To INT_STS register
IEEE 1588 Time Stamp
The LAN9313/LAN9313i contains three identical IEEE 1588 Time Stamp blocks as shown in Figure 10-1. These blocks
are responsible for capturing the source UUID, sequence ID, and current 64-bit IEEE 1588 clock time upon detection
of a Sync or Delay_Req message type on their respective port. The mode of the clock (master or slave) determines
which message is detected on receive and transmit. For slave clock operation, Sync messages are detected on receive
and Delay_Req messages on transmit. For master clock operation, Delay_Req messages are detected on receive and
Sync messages on transmit. Follow_Up, Delay_Resp and Management packet types do not cause capture. Each port
may be individually configured as an IEEE 1588 master or slave clock via the master/slave bits (M_nS_1 for Port 1,
MnS_2 for Port2, and M_nS_MII for Port 0) in the 1588 Configuration Register (1588_CONFIG). Table 10-1 summarizes
the message type detection under slave and master IEEE 1588 clock operation.
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TABLE 10-1:
IEEE 1588 MESSAGE TYPE DETECTION
IEEE 1588 Clock Mode
Receive
Transmit
Slave
(M_nS_x = 0)
Sync
Delay_Req
Master
(M_nS_x = 1)
Delay_Req
Sync
For ports 1 and 2, receive is defined as data from the PHY (from the outside world) and transmit is defined as data to
the PHY. This is consistent with the point-of-view of where the partner clock resides (LAN9313/LAN9313i receives packets from the partner via the PHY, etc.). For the time stamp module connected to the external MII port (Port 0), the definition of transmit and receive is reversed. Receive is defined as data from the switch fabric, while transmit is defined as
data to the switch fabric. This is consistent with the point-of-view of where the partner clock resides (LAN9313/LAN9313i
receives packets from the partner via the switch fabric, etc.).
As defined by IEEE 1588, and shown in Figure 10-2, the message time stamp point is defined as the leading edge of
the first data bit following the Start of Frame Delimiter (SFD). However, since the packet contents are not yet known, the
time stamp can not yet be loaded into the capture register. Therefore, the time stamp is first stored into a temporary
internal holding register at the start of every packet.
FIGURE 10-2:
IEEE 1588 MESSAGE TIME STAMP POINT
Message Timestamp
Point
Ethernet
Start of Frame
Delimiter
Preamble
Octet
1
0
1
0
1
0
1
0
1
First Octet
following
Start of Frame
1 1 1
0
0
0 0 0 0 0 0 0
bit time
Clock synchronization and hardware processing between the network data and the time stamp capture hardware
causes the time stamp point to be slightly delayed. The host software can account for this delay, as it is fairly deterministic. Table 10-2 details the time stamp capture delay as a function of the mode of operation. Refer to Section 7.0, "Ethernet PHYs," on page 68 for details on these modes.
TABLE 10-2:
TIME STAMP CAPTURE DELAY
Mode of Operation
Delay (+/- 10 ns)
100 Mbps
30 nS
10 Mbps
120 nS
Once the packet type is matched, according to Table 10-1, and the Frame Check Sequence (FCS) is verified, the following occurs:
• The time stamp is loaded into the corresponding ports’ capture registers:
- On Reception: Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x) and Port
x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x)
- On Transmission: Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x) and
Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x)
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• The Sequence ID and Source UUID are loaded into the corresponding ports’ registers:
- On Reception: Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register
(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x) and Port x 1588 Source UUID Low-DWORD Receive Capture Register
(1588_SRC_UUID_LO_RX_CAPTURE_x)
- On Transmission: Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register
(1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) and Port x 1588 Source UUID Low-DWORD Transmit Capture Register
(1588_SRC_UUID_LO_TX_CAPTURE_x)
• The corresponding maskable interrupt flag is set in the 1588 Interrupt Status and Enable Register
(1588_INT_STS_EN). (Refer to Section 10.6, "IEEE 1588 Interrupts," on page 118 for information on IEEE 1588
interrupts.)
Note:
10.2.1
Packets that do not contain an integral number of octets are not considered valid and do not cause a capture.
CAPTURE LOCKING
The corresponding ports’ clock capture, sequence ID, and source UUID registers can be optionally locked when a capture event occurs, preventing them from being overwritten until the host clears the corresponding interrupt flag in the
1588 Interrupt Status and Enable Register (1588_INT_STS_EN).
This is accomplished by setting the corresponding lock enable bit(s) in the 1588 Configuration Register (1588_CONFIG). Each port has two lock enable control bits within this register, which allow the receive and transmit portions of each
port to be locked independently. In addition, a lock enable bit is provided for each time stamp enabled GPIO (LOCK_ENABLE_GPIO_8 and LOCK_ENABLE_GPIO_9) which prevents the corresponding GPIO clock capture registers from
being overwritten when the GPIO interrupt in 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) is set.
Refer to Section 13.1.4.22, "1588 Configuration Register (1588_CONFIG)," on page 144 for additional information on
the capture locking related bits.
10.2.2
PTP MESSAGE DETECTION
In order to provide the most flexibility, loose packet type matching is used by the LAN9313/LAN9313i. This assumes
that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP
message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224.0.1.129 through 224.0.1.132.
These map to Ethernet MAC addresses 01:00:5e:00:01:81 through 01:00:5e:00:01:84. Each of these addresses has
one enable bit per port in the 1588 Configuration Register (1588_CONFIG) which enables/disables the corresponding
address as a PTP address on the specified port.
In addition to the fixed addresses, a user defined (host programmable) PTP address may be input via the 1588 Auxiliary
MAC Address High-WORD Register (1588_AUX_MAC_HI) and 1588 Auxiliary MAC Address Low-DWORD Register
(1588_AUX_MAC_LO). The user defined address may be disabled/enabled as a PTP address on each port via the dedicated enable bits in the 1588 Configuration Register (1588_CONFIG). A summary of the supported PTP multicast
addresses and corresponding enable bits can be seen in Table 10-3.
TABLE 10-3:
PTP MULTICAST ADDRESSES
Corresponding
MAC Address
Related Enable Bits in the
1588_CONFIG Register
224.0.1.129
(Primary)
01:00:5e:00:01:81
MAC_PRI_EN_1 (Port 1)
MAC_PRI_EN_2 (Port 2)
MAC_PRI_EN_MII (Port 0)
224.0.1.130
(Alternate 1)
01:00:5e:00:01:82
MAC_ALT1_EN_1 (Port 1)
MAC_ALT1_EN_2 (Port 2)
MAC_ALT1_EN_MII (Port 0)
224.0.1.131
(Alternate 2)
01:00:5e:00:01:83
MAC_ALT2_EN_1 (Port 1)
MAC_ALT2_EN_2 (Port 2)
MAC_ALT2_EN_MII (Port 0)
224.0.1.132
(Alternate 3)
01:00:5e:00:01:84
MAC_ALT3_EN_1 (Port 1)
MAC_ALT3_EN_2 (Port 2)
MAC_ALT3_EN_MII (Port 0)
PTP Address
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TABLE 10-3:
PTP MULTICAST ADDRESSES (CONTINUED)
Corresponding
MAC Address
Related Enable Bits in the
1588_CONFIG Register
User Defined Address
(1588_AUX_MAC_HI &
1588_AUX_MAC_LO registers)
MAC_USER_EN_1 (Port 1)
MAC_USER_EN_2 (Port 2)
MAC_USER_EN_MII (Port 0)
PTP Address
User Defined
Once a packet is determined to match a PTP destination address, it is further qualified as a Sync or Delay_Req message
type. On Ethernet, PTP uses UDP messages. Within the UDP payload is the PTP control byte (offset 32 starting at 0).
This byte determines the message type: 0x00 for a Sync message, 0x01 for a Delay_Req message. The UDP payload
starts at packet byte offset 42 (from 0) for untagged packets and at byte offset 46 for tagged packets.
Note:
• Both tagged and untagged packets are supported. Only Ethernet II packet encoding and IPv4 are supported.
• For proper routing of the PTP packets, the host must program an entry into the switch engine Address Logic Resolution (ALR) Table. The MAC address should be one of the reserved Multicast addresses in Table 10-3, with
Port 0(External MII) as a destination.The Static and Valid bits must also be set. Refer to Section 6.0, "Switch Fabric," on page 45 for more information.
10.3
IEEE 1588 Clock
The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9313/LAN9313i. It is readable and writable by the host via the 1588 Clock High-DWORD Register (1588_CLOCK_HI) and 1588 Clock LowDWORD Register (1588_CLOCK_LO).
In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads are required to
fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a wrong intermediate value could be
read. To prevent this, a snapshot register technique is used. When the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) register is written with “1”, the current value of the 1588 clock is saved, allowing it to be
properly read.
When writing a new value to the IEEE 1588 clock, two 32-bit write cycles are required (one for each clock register)
before the registers are affected. The writes may be in any order. However, caution must be observed when changing
the clock value in a live environment as it will disrupt linear time. If the clock must be adjusted during operation of the
1588 protocol, it is preferred to adjust the Addend value, effectively speeding-up or slowing-down the clock until the correct time is achieved.
The 64-bit IEEE 1588 clock consists of the 32-bit 1588 Clock Addend Register (1588_CLOCK_ADDEND) that is added
to a 32-bit Accumulator every 100 MHz clock. Upon overflow of the Accumulator, the 64- bit IEEE 1588 clock is incremented. The Addend / Accumulator pair form a high precision frequency divider which can be used to compensate for
the inaccuracy of the reference crystal. The nominal frequency of the 64-bit IEEE 1588 clock and the value of the
Addend are calculated as follows:
FreqClock = (Addend / 232) * 100 MHz
Addend = (FreqClock * 232) / 100 MHz
Typical values for the Addend are shown in Table 10-4. These values should be adjusted based on the accuracy of the
IEEE 1588 clock compared to the master clock per the PTP protocol. The adjustment precision column of the table
shows the percentage change for the specified IEEE 1588 clock frequency if the Addend was to be incremented or decremented by 1.
TABLE 10-4:
TYPICAL IEEE 1588 CLOCK ADDEND VALUES
IEEE 1588 Clock
(FreqClock)
1588_CLOCK_ADDEND
(Addend)
Adjustment Precision %
33 MHz
547AE147h
7.1*10-8
50 MHz
80000000h
4.7*10-8
66 MHz
A8F5C28Fh
3.5*10-8
75 MHz
C0000000h
3.1*10-8
90 MHz
E6666666h
2.6*10-8
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10.4
IEEE 1588 Clock/Events
The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock related events. A
64-bit comparator is included in this block which compares the 64-bit IEEE 1588 clock with a 64-bit Clock Target loaded
in the 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD
Register (1588_CLOCK_TARGET_LO).
When the IEEE 1588 clock equals the Clock Target, a clock event occurs which triggers the following:
• The maskable interrupt 1588_TIMER_INT is set in the 1588 Interrupt Status and Enable Register
(1588_INT_STS_EN).
• The RELOAD_ADD bit in the 1588 Configuration Register (1588_CONFIG) is checked to determine the new
Clock Target behavior:
- RELOAD_ADD = 1:
The new Clock Target is loaded from the 64-bit Reload / Add Registers (1588 Clock Target Reload High-DWORD Register
(1588_CLOCK_TARGET_RELOAD_HI) and 1588 Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO)).
- RELOAD_ADD = 0:
The Clock Target is incremented by the 1588 Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO).
Note:
Writing the IEEE 1588 clock may cause the interrupt event to occur if the new IEEE 1588 clock value is set
equal to the current Clock Target.
The Clock Target reload function (RELOAD_ADD = 1) allows the host to pre-load the next trigger time. The add function
(RELOAD_ADD = 0), allows for a repeatable event. When the Clock Target overflows, it will wrap around past 0, as will
the 64-bit IEEE 1588 clock. Since the Clock Target and Reload / Add Registers are 64-bits, they require two 32-bit write
cycles, one to each half, before the registers are affected. The writes may be in any order.
10.5
IEEE 1588 GPIOs
In addition to time stamping PTP packets, the IEEE 1588 clock value can be saved into a set of clock capture registers
based on the GPIO[9:8] inputs. When configured as outputs, GPIO[9:8] can be used to output a signal based on an
IEEE 1588 clock target compare event. Refer to Section 12.2.1, "GPIO IEEE 1588 Timestamping," on page 120 for
information on using GPIO[9:8] for IEEE 1588 time stamping functions.
10.6
IEEE 1588 Interrupts
The IEEE 1588 hardware time stamp unit provides multiple interrupt conditions. These include time stamp indication on
the transmitter and receiver side of each port, individual GPIO[9:8] input time stamp interrupts, and a clock comparison
event interrupt. All IEEE 1588 interrupts are located in the 1588 Interrupt Status and Enable Register
(1588_INT_STS_EN) and are fully maskable via their respective enable bits. Refer to Section 13.1.4.23, "1588 Interrupt
Status and Enable Register (1588_INT_STS_EN)," on page 148 for bit-level definitions of all IEEE 1588 interrupts and
enables.
All IEEE 1588 interrupts are ANDed with their individual enables and then ORed, as shown in Figure 10-1, generating
the 1588_EVNT bit of the Interrupt Status Register (INT_STS).
When configured as an input, GPIO[9:8] have the added functionality of clearing the Clock Target interrupt bit
(1588_TIMER_INT) of the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) on an active edge. GPIO
inputs must be active for greater than 40 nS to be recognized as clear events. For more information on IEEE 1588 GPIO
interrupts, refer to Section 12.2.2, "GPIO Interrupts," on page 121.
Refer to Section 5.0, "System Interrupts," on page 41 for additional information on the LAN9313/LAN9313i interrupts.
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LAN9313/LAN9313i
11.0
GENERAL PURPOSE TIMER & FREE-RUNNING CLOCK
This chapter details the LAN9313/LAN9313i General Purpose Timer (GPT) and the Free-Running Clock.
11.1
General Purpose Timer
The LAN9313/LAN9313i provides a 16-bit programmable General Purpose Timer that can be used to generate periodic
system interrupts. The resolution of this timer is 100uS.
The GPT loads the General Purpose Timer Count Register (GPT_CNT) with the value in the GPT_LOAD field of the
General Purpose Timer Configuration Register (GPT_CFG) when the TIMER_EN bit of the General Purpose Timer Configuration Register (GPT_CFG) is asserted (1). On a chip-level reset, or when the TIMER_EN bit changes from asserted
(1) to de-asserted (0), the GPT_LOAD field is initialized to FFFFh. The General Purpose Timer Count Register
(GPT_CNT) is also initialized to FFFFh on reset. Software can write a pre-load value into the GPT_LOAD field at any
time (e.g. before or after the TIMER_EN bit is asserted).
Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to the GPT_LOAD
field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status bit (GPT_INT) in the Interrupt Status Register (INT_STS), asserts the IRQ interrupt (if GPT_INT_EN is set in the Interrupt Status Register (INT_STS)),
and continues counting. GPT_INT is a sticky bit. Once this bit is asserted, it can only be cleared by writing a 1 to the bit.
Refer to Section 5.2.5, "General Purpose Timer Interrupt," on page 44 for additional information on the GPT interrupt.
11.2
Free-Running Clock
The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock. The current FRC
value can be read via the Free Running 25MHz Counter Register (FREE_RUN). On assertion of a chip-level reset, this
counter is cleared to zero. On de-assertion of a reset, the counter is incremented once for every 25MHz clock cycle.
When the maximum count has been reached, the counter rolls over to zeros. The FRC does not generate interrupts.
Note:
The free running counter can take up to 160nS to clear after a reset event.
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12.0
GPIO/LED CONTROLLER
12.1
Functional Overview
The GPIO/LED Controller provides 12 configurable general purpose input/output pins, GPIO[11:0]. These pins can be
individually configured to function as inputs, push-pull outputs, or open drain outputs and each is capable of interrupt
generation with configurable polarity. Two of the GPIO pins (GPIO[9:8]) can be used for IEEE 1588 timestamp functions,
allowing GPIO driven 1588 time clock capture when configured as an input, or GPIO output generation based on an
IEEE 1588 clock target compare event.
In addition, 8 of the GPIO pins can be alternatively configured as LED outputs. These pins, GPIO[7:0] (nP1LED[3:0] and
nP2LED[3:0]), may be enabled to drive Ethernet status LEDs for external indication of various attributes of the switch
ports.
GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers (CSRs), accessible
through the I2C/SPI serial interfaces or the MII/SMI interfaces. These registers are defined in Section 13.1.2,
"GPIO/LED," on page 130.
12.2
GPIO Operation
The GPIO controller is comprised of 12 programmable input/output pins. These pins are individually configurable via
the GPIO CSRs. On application of a chip-level reset:
• All GPIOs are set as inputs (GPDIR[11:0] cleared in General Purpose I/O Data & Direction Register (GPIO_DATA_DIR))
• All GPIO interrupts are disabled (GPIO[11:0]_INT_EN cleared in General Purpose I/O Interrupt Status and Enable
Register (GPIO_INT_STS_EN)
• All GPIO interrupts are configured to low logic level triggering (GPIO_INT_POL[11:0] cleared in General Purpose
I/O Configuration Register (GPIO_CFG))
Note:
GPIO[7:0] may be configured as LED outputs by default, dependant on the LED_en_stap[7:0] configuration
straps. Refer to Section 12.3, "LED Operation" for additional information.
The direction and buffer type of all 12 GPIOs are configured via the General Purpose I/O Configuration Register (GPIO_CFG) and General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). The direction of each GPIO, input or
output, should be configured first via its respective GPIO direction bit (GPDIR[11:0]) in the General Purpose I/O Data &
Direction Register (GPIO_DATA_DIR). When configured as an output, the output buffer type for each GPIO is selected
by the GPIOBUF[11:0] bits in the General Purpose I/O Configuration Register (GPIO_CFG). Push/pull and open-drain
output buffers are supported for each GPIO. When functioning as an open-drain driver, the GPIO output pin is driven
low when the corresponding data register bit (GPIOD in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)) is cleared to 0, and is not driven when set to 1.
When a GPIO is enabled as an output, the value output to the GPIO pin is set via the corresponding GPIOD[11:0] bit in
the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). For GPIOs configured as inputs, the corresponding GPIOD[11:0] bit reflects the current state of the GPIO input.
Note:
12.2.1
For GPIO[9:8], the pin direction is a function of both the GPDIR[9:8] bits of the General Purpose I/O Data
& Direction Register (GPIO_DATA_DIR) and the 1588_GPIO_OE[9:8] bits in the General Purpose I/O Configuration Register (GPIO_CFG).
GPIO IEEE 1588 TIMESTAMPING
Two of the GPIO pins, GPIO[9:8], have the option to be used for IEEE 1588 time stamp functions. This allows a time
stamp capture to be triggered when the GPIO is configured as an input, or output a signal from the GPIO based on an
IEEE 1588 clock target compare event when configured as an output. Refer to Section 10.0, "IEEE 1588 Hardware Time
Stamp Unit," on page 113 for additional information on the IEEE 1588 time stamping functions of the
LAN9313/LAN9313i.
12.2.1.1
IEEE 1588 GPIO Inputs
When the GPIO[9:8] pins are configured as inputs, an active edge will capture the IEEE 1588 clock into the high and
low 1588 capture registers (1588_CLOCK_HI_CAPTURE_GPIO_x, and 1588_CLOCK_LO_CAPTURE_GPIO_x
where “x” represents the number of the respective 1588 enabled GPIO) and set the corresponding interrupt flags
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GPIO[9:8]_INT and 1588_GPIO[9:8]_INT in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) respectively. The GPIO[9:8]
inputs can also be configured to clear the Clock Target interrupt (1588_TIMER_INT) in the 1588 Interrupt Status and
Enable Register (1588_INT_STS_EN) by setting the corresponding GPIO_1588_TIMER_INT_CLEAR_EN[9:8] bit in
the General Purpose I/O Configuration Register (GPIO_CFG). GPIO inputs must be active for greater than 40nS to be
recognized as capture or interrupt clear events.
12.2.1.2
IEEE 1588 GPIO Outputs
The GPIO[9:8] pins can be configured as IEEE 1588 enabled outputs by setting the corresponding 1588_GPIO_OE[9:8]
bits in the General Purpose I/O Configuration Register (GPIO_CFG). These bits override the GPDIR[9:8] bits of the
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) and allow for GPIO output generation based on the
IEEE 1588 clock target compare event. Clock target compare events occur when the value loaded into the 1588 Clock
Target High-DWORD Register (1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD Register
(1588_CLOCK_TARGET_LO) matches the current IEEE 1588 clock value in the 1588 Clock High-DWORD Register
(1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO).
Upon detection of a clock target compare event, GPIO[9:8] can be configured to output a 100nS pulse, toggle its output,
or reflect the 1588_TIMER_INT bit in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) by enabling
the GPIO_EVENT_9 or GPIO_EVENT_8 bits of the 1588 Configuration Register (1588_CONFIG). The clock event
polarity, which determines whether the IEEE 1588 GPIO output is active high or active low, is controlled via the GPIO_EVENT_POL_9 and GPIO_EVENT_POL_8 bits of the General Purpose I/O Configuration Register (GPIO_CFG).
Note:
12.2.2
The 1588_GPIO_OE[9:8] bits do not override the GPIO buffer type bits GPIOBUF[9:8] in the General Purpose I/O Configuration Register (GPIO_CFG).
GPIO INTERRUPTS
Each GPIO of the LAN9313/LAN9313i provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O
Interrupt Status and Enable Register (GPIO_INT_STS_EN). Reading the GPIO_INT[11:0] bits of this register provides
the current status of the corresponding interrupt, and each interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit. The GPIO/LED Controller aggregates the enabled interrupt values into an internal signal which is
sent to the System Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) bit 12 (GPIO). For
more information on the LAN9313/LAN9313i interrupts, refer to Section 5.0, "System Interrupts," on page 41.
12.2.2.1
GPIO Interrupt Polarity
The interrupt polarity can be set for each individual GPIO via the GPIO_INT_POL[11:0] bits in the General Purpose I/O
Configuration Register (GPIO_CFG). When set, a high logic level on the GPIO pin will set the corresponding interrupt
bit in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). When cleared, a low logic
level on the GPIO pin will set the corresponding interrupt bit. Because GPIO[9:8] have added IEEE 1588 functionality,
the GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in Section 12.2.1.2.
12.2.2.2
IEEE 1588 GPIO Interrupts
In addition to the standard GPIO interrupts in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN), the IEEE 1588 timestamp enabled GPIO[9:8] pins contain the ability to generate and clear specific
IEEE 1588 related interrupts. When GPIO 9 or GPIO 8 are enabled as inputs and an active edge occurs, the IEEE 1588
clock capture is indicated by the 1588_GPIO9_INT and 1588_GPIO8_INT interrupts respectively in the 1588 Interrupt
Status and Enable Register (1588_INT_STS_EN). These interrupts are enabled by setting the corresponding 1588_GPIO9_EN and 1588_GPIO8_EN bits in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN). GPIO
inputs must be active for greater than 40nS to be recognized as capture events.
When GPIO 8 and GPIO 9 are enabled, the 1588 Timer Interrupt bit (1588_TIMER_INT) of the 1588 Interrupt Status
and Enable Register (1588_INT_STS_EN) can be cleared by an active edge on GPIO[9:8]. A clear is only registered
when the GPIO input is active for greater than 40nS.
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12.3
LED Operation
Eight pins, GPIO[7:0], are shared with LED functions (nP1LED[3:0] and nP2LED[3:0]). These pins are configured as
LED outputs by setting the corresponding LED_EN bit in the LED Configuration Register (LED_CFG). When configured
as a LED, the pin is an open-drain, active-low output and the GPIO related input buffer and pull-up are disabled. The
LED outputs are always active low. As a result, a low signal on the LED pin equates to the LED “on”, and a high signal
equates to the LED “off”.
The functions associated with each LED pin are configurable via the LED_FUN[1:0] bits of the LED Configuration Register (LED_CFG). These bits allow the configuration of each LED pin to indicate various port related functions. These
functions are described in Table 12-1 followed by a detailed definition of each indication type.
The default values of the LED_FUN[1:0] and LED_EN[7:0] bits of the LED Configuration Register (LED_CFG) are determined by the LED_fun_strap[1:0] and LED_en_strap[7:0] configuration straps. For more information on the LED Configuration Register (LED_CFG) and its related straps, refer to Section 13.1.2.4, "LED Configuration Register
(LED_CFG)," on page 133.
TABLE 12-1:
LED OPERATION AS A FUNCTION OF LED_CFG[9:8]
LED_CFG[9:8] (LED_FUN[1:0])
00b
01b
10b
11b
nP2LED3
(GPIO7)
RX
Port 0
RX
Port 0
Activity
Port 2
-
nP2LED2
(GPIO6)
Link / Activity
Port 2
100Link / Activity
Port 2
Link
Port 2
-
nP2LED1
(GPIO5)
Full-duplex / Collision
Port 2
Full-duplex / Collision
Port 2
Full-duplex / Collision
Port 2
TXEN
Port 2
nP2LED0
(GPIO4)
Speed
Port 2
10Link / Activity
Port 2
Speed
Port 2
RXDV
Port 2
nP1LED3
(GPIO3)
TX
Port 0
TX
Port 0
Activity
Port 1
TXEN
Port 0
nP1LED2
(GPIO2)
Link / Activity
Port 1
100Link / Activity
Port 1
Link
Port 1
RXDV
Port 0
nP1LED1
(GPIO1)
Full-duplex / Collision
Port 1
Full-duplex / Collision
Port 1
Full-duplex / Collision
Port 1
TXEN
Port 1
nP1LED0
(GPIO0)
Speed
Port 1
10Link / Activity
Port 1
Speed
Port 1
RXDV
Port 1
The various LED indication functions shown in Table 12-1 are described below:
• TX Port 0 - The signal is pulsed low for 80mS to indicate activity from the switch fabric to the external MII pins.
This signal is then driven high for a minimum of 80mS, after which the process will repeat if TX activity is again
detected.
• RX Port 0 - The signal is pulsed low for 80mS to indicate activity from the external MII pins to the switch fabric.
This signal is then driven high for a minimum of 80mS, after which the process will repeat if RX activity is again
detected.
• Link / Activity - A steady low output indicates that the port has a valid link, while a steady high indicates no link on
the port. The signal is pulsed high for 80mS to indicate transmit or receive activity on the port. The signal is then
driven low for a minimum of 80mS, after which the process will repeat if RX or TX activity is again detected.
• Full-duplex / Collision - A steady low output indicates the port is in full-duplex mode, while a steady high indicates
no link on the port. In half-duplex mode, the signal is pulsed low for 80mS to indicate a network collision. The signal is then driven high for a minimum of 80mS, after which the process will repeat if another collision is detected.
• Speed - A steady low output indicates the selected speed is 100Mbps. A steady high output indicates the selected
speed is 10Mbps. The signal will be held high if the port does not have a valid link.
• 100Link / Activity - A steady low output indicates the port has a valid link and the speed is 100Mbps. The signal is
pulsed high for 80mS to indicate TX or RX activity on the port. The signal is then driven low for a minimum of
80mS, after which the process will repeat if RX or TX activity is again detected. The signal will be held high if the
port does not have a valid link.
DS00002288A-page 122
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
• 10Link / Activity - A steady low output indicates the port has a valid link and the speed is 10Mbps. The signal is
pulsed high for 80mS to indicate transmit or receive activity on the port. The signal is then driven low for a minimum of 80mS, after which the process will repeat if RX or TX activity is again detected. This signal will be held
high if the port does not have a valid link.
• Activity - The signal is pulsed low for 80mS to indicate transmit or receive activity. The signal is then driven high for
a minimum of 80mS, after which the process will repeat if RX or TX activity is again detected. The signal will be
held high if the port does not have a valid link.
• Link - A steady low indicates the port has a valid link.
• TXEN Port 0 - Non-stretched TXEN signal from the switch fabric to the external MII pins.
• RXDV Port 0 - Non-stretched RXDV signal from the external MII pins to the switch fabric.
• TXEN - Non-stretched TXEN signal from the switch fabric to the PHY.
• RXDV - Non-stretched RXDV signal from the PHY to the switch fabric.
2008-2016 Microchip Technology Inc.
DS00002288A-page 123
LAN9313/LAN9313i
13.0
REGISTER DESCRIPTIONS
This section describes the various LAN9313/LAN9313i control and status registers (CSR’s). These registers are broken
into 3 categories. The following sections detail the functionality and accessibility of all the LAN9313/LAN9313i registers
within each category:
• Section 13.1, "System Control and Status Registers," on page 125
• Section 13.2, "Ethernet PHY Control and Status Registers," on page 175
• Section 13.3, "Switch Fabric Control and Status Registers," on page 189
Figure 13-1 contains an overall base register memory map of the LAN9313/LAN9313i. This memory map is not drawn
to scale, and should be used for general reference only.
Note:
• Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 6.
• Not all LAN9313/LAN9313i registers are memory mapped or directly addressable. For details on the accessibility
of the various LAN9313/LAN9313i registers, refer the register sub-sections listed above.
FIGURE 13-1:
LAN9313/LAN9313I BASE REGISTER MEMORY MAP
3FFh
...
RESERVED
2E0h
2DCh
...
Switch CSR Direct Data
Registers
200h
1DCh
Virtual PHY Registers
1C0h
1B0h
1ACh
Switch Interface Registers
19Ch
System CSRs
1588 Registers
100h
0A8h
0A4h
PHY Management Interface
Registers
050h
04Ch
RESERVED
Base + 000h
DS00002288A-page 124
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.1
System Control and Status Registers
The System CSR’s are directly addressable memory mapped registers with a base address offset range of 050h to
2DCh. These registers are accessed through the I2C/SPI serial interfaces or the MIIM/SMI serial interface. For more
information on the various LAN9313/LAN9313i modes and their corresponding address configurations, see Section 2.3,
"Modes of Operation," on page 12.
Table 13-1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are reset to their
default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 8 sub-categories. Each of these sub-categories contains the System CSR
descriptions of the associated registers. The register descriptions are categorized as follows:
•
•
•
•
•
•
•
•
Section 13.1.1, "Interrupts," on page 128
Section 13.1.2, "GPIO/LED," on page 130
Section 13.1.3, "EEPROM," on page 133
Section 13.1.4, "IEEE 1588," on page 136
Section 13.1.5, "Switch Fabric," on page 150
Section 13.1.6, "PHY Management Interface (PMI)," on page 159
Section 13.1.7, "Virtual PHY," on page 161
Section 13.1.8, "Miscellaneous," on page 171
TABLE 13-1:
SYSTEM CONTROL AND STATUS REGISTERS
Address
Offset
Symbol
000h - 04Ch
RESERVED
Register Name
Reserved for Future Use
050h
ID_REV
Chip ID and Revision Register, Section 13.1.8.1
054h
IRQ_CFG
Interrupt Configuration Register, Section 13.1.1.1
058h
INT_STS
Interrupt Status Register, Section 13.1.1.2
05Ch
INT_EN
Interrupt Enable Register, Section 13.1.1.3
060h
RESERVED
Reserved for Future Use
064h
BYTE_TEST
Byte Order Test Register, Section 13.1.8.2
068h - 070h
RESERVED
Reserved for Future Use
074h
HW_CFG
078h - 088h
RESERVED
08Ch
GPT_CFG
General Purpose Timer Configuration Register,
Section 13.1.8.4
General Purpose Timer Count Register, Section 13.1.8.5
Hardware Configuration Register, Section 13.1.8.3
Reserved for Future Use
090h
GPT_CNT
094h - 098h
RESERVED
Reserved for Future Use
09Ch
FREE_RUN
Free Running Counter Register, Section 13.1.8.6
0A0h
RESERVED
Reserved for Future Use
0A4h
PMI_DATA
0A8h
PMI_ACCESS
0ACh - 0FCh
RESERVED
100h
1588_CLOCK_HI_RX_CAPTURE_1
Port 1 1588 Clock High-DWORD Receive Capture Register,
Section 13.1.4.1
104h
1588_CLOCK_LO_RX_CAPTURE_1
Port 1 1588 Clock Low-DWORD Receive Capture Register,
Section 13.1.4.2
108h
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1
10Ch
1588_SRC_UUID_LO_RX_CAPTURE_1
110h
1588_CLOCK_HI_TX_CAPTURE_1
Port 1 1588 Clock High-DWORD Transmit Capture Register,
Section 13.1.4.5
114h
1588_CLOCK_LO_TX_CAPTURE_1
Port 1 1588 Clock Low-DWORD Transmit Capture Register,
Section 13.1.4.6
2008-2016 Microchip Technology Inc.
PHY Management Interface Data Register, Section 13.1.6.1
PHY Management Interface Access Register,
Section 13.1.6.2
Reserved for Future Use
Port 1 1588 Sequence ID, Source UUID High-WORD
Receive Capture Register, Section 13.1.4.3
Port 1 1588 Source UUID Low-DWORD Receive Capture
Register, Section 13.1.4.4
DS00002288A-page 125
LAN9313/LAN9313i
TABLE 13-1:
SYSTEM CONTROL AND STATUS REGISTERS (CONTINUED)
Address
Offset
Symbol
118h
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1
11C
1588_SRC_UUID_LO_TX_CAPTURE_1
Port 1 1588 Source UUID Low-DWORD Transmit Capture
Register, Section 13.1.4.8
120h
1588_CLOCK_HI_RX_CAPTURE_2
Port 2 1588 Clock High-DWORD Receive Capture Register,
Section 13.1.4.1
124h
1588_CLOCK_LO_RX_CAPTURE_2
Port 2 1588 Clock Low-DWORD Receive Capture Register,
Section 13.1.4.2
128h
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2
12Ch
1588_SRC_UUID_LO_RX_CAPTURE_2
130h
1588_CLOCK_HI_TX_CAPTURE_2
Port 2 1588 Clock High-DWORD Transmit Capture Register,
Section 13.1.4.5
134h
1588_CLOCK_LO_TX_CAPTURE_2
Port 2 1588 Clock Low-DWORD Transmit Capture Register,
Section 13.1.4.6
138h
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2
13Ch
1588_SRC_UUID_LO_TX_CAPTURE_2
Port 2 1588 Source UUID Low-DWORD Transmit Capture
Register, Section 13.1.4.8
140h
1588_CLOCK_HI_RX_CAPTURE_MII
Port 0 1588 Clock High-DWORD Receive Capture Register,
Section 13.1.4.1
144h
1588_CLOCK_LO_RX_CAPTURE_MII
Port 0 1588 Clock Low-DWORD Receive Capture Register,
Section 13.1.4.2
148h
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII
14Ch
1588_SRC_UUID_LO_RX_CAPTURE_MII
150h
1588_CLOCK_HI_TX_CAPTURE_MII
Port 0 1588 Clock High-DWORD Transmit Capture Register,
Section 13.1.4.5
154h
1588_CLOCK_LO_TX_CAPTURE_MII
Port 0 1588 Clock Low-DWORD Transmit Capture Register,
Section 13.1.4.6
158h
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII
15Ch
1588_SRC_UUID_LO_TX_CAPTURE_MII
160h
1588_CLOCK_HI_CAPTURE_GPIO_8
GPIO 8 1588 Clock High-DWORD Capture Register,
Section 13.1.4.9
164h
1588_CLOCK_LO_CAPTURE_GPIO_8
GPIO 8 1588 Clock Low-DWORD Capture Register,
Section 13.1.4.10
168h
1588_CLOCK_HI_CAPTURE_GPIO_9
GPIO 9 1588 Clock High-DWORD Capture Register,
Section 13.1.4.11
16Ch
1588_CLOCK_LO_CAPTURE_GPIO_9
GPIO 9 1588 Clock Low-DWORD Capture Register,
Section 13.1.4.12
Register Name
Port 1 1588 Sequence ID, Source UUID High-WORD
Transmit Capture Register, Section 13.1.4.7
Port 2 1588 Sequence ID, Source UUID High-WORD
Receive Capture Register, Section 13.1.4.3
Port 2 1588 Source UUID Low-DWORD Receive Capture
Register, Section 13.1.4.4
Port 2 1588 Sequence ID, Source UUID High-WORD
Transmit Capture Register, Section 13.1.4.7
Port 0 1588 Sequence ID, Source UUID High-WORD
Receive Capture Register, Section 13.1.4.3
Port 0 1588 Source UUID Low-DWORD Receive Capture
Register, Section 13.1.4.4
Port 0 1588 Sequence ID, Source UUID High-WORD
Transmit Capture Register, Section 13.1.4.7
Port 0 1588 Source UUID Low-DWORD Transmit Capture
Register, Section 13.1.4.8
170h
1588_CLOCK_HI
1588 Clock High-DWORD Register, Section 13.1.4.13
1588 Clock Low-DWORD Register, Section 13.1.4.14
174h
1588_CLOCK_LO
178h
1588_CLOCK_ADDEND
17Ch
1588_CLOCK_TARGET_HI
1588 Clock Target High-DWORD Register, Section 13.1.4.16
180h
1588_CLOCK_TARGET_LO
1588 Clock Target Low-DWORD Register, Section 13.1.4.17
184h
1588_CLOCK_TARGET_RELOAD_HI
1588 Clock Target Reload High-DWORD Register,
Section 13.1.4.18
188h
1588_CLOCK_TARGET_RELOAD_LO
1588 Clock Target Reload/Add Low-DWORD Register,
Section 13.1.4.19
18Ch
1588_AUX_MAC_HI
1588 Auxiliary MAC Address High-WORD Register,
Section 13.1.4.20
190h
1588_AUX_MAC_LO
1588 Auxiliary MAC Address Low-DWORD Register,
Section 13.1.4.21
DS00002288A-page 126
1588 Clock Addend Register, Section 13.1.4.15
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 13-1:
Address
Offset
SYSTEM CONTROL AND STATUS REGISTERS (CONTINUED)
Symbol
Register Name
194h
1588_CONFIG
198h
1588_INT_STS_EN
1588 Configuration Register, Section 13.1.4.22
19Ch
1588_CMD
1A0h
MANUAL_FC_1
Port 1 Manual Flow Control Register, Section 13.1.5.1
1A4h
MANUAL_FC_2
Port 2 Manual Flow Control Register, Section 13.1.5.2
1A8h
MANUAL_FC_MII
1ACh
SWITCH_CSR_DATA
Switch Fabric CSR Interface Data Register, Section 13.1.5.4
1B0h
SWITCH_CSR_CMD
Switch Fabric CSR Interface Command Register,
Section 13.1.5.5
1588 Interrupt Status Enable Register, Section 13.1.4.23
1588 Command Register, Section 13.1.4.24
Port 0 Flow Control Register, Section 13.1.5.3
1B4h
E2P_CMD
EEPROM Command Register, Section 13.1.3.1
1B8h
E2P_DATA
EEPROM Data Register, Section 13.1.3.2
1BCh
LED_CFG
LED Configuration Register, Section 13.1.2.4
1C0h
VPHY_BASIC_CTRL
Virtual PHY Basic Control Register, Section 13.1.7.1
1C4h
VPHY_BASIC_STATUS
Virtual PHY Basic Status Register, Section 13.1.7.2
1C8h
VPHY_ID_MSB
Virtual PHY Identification MSB Register, Section 13.1.7.3
1CCh
VPHY_ID_LSB
Virtual PHY Identification LSB Register, Section 13.1.7.4
1D0h
VPHY_AN_ADV
Virtual PHY Auto-Negotiation Advertisement Register,
Section 13.1.7.5
1D4h
VPHY_AN_LP_BASE_ABILITY
1D8h
VPHY_AN_EXP
1DCh
VPHY_SPECIAL_CONTROL_STATUS
1E0h
GPIO_CFG
1E4h
GPIO_DATA_DIR
1E8h
GPIO_INT_STS_EN
Virtual PHY Auto-Negotiation Link Partner Base Page Ability
Register, Section 13.1.7.6
Virtual PHY Auto-Negotiation Expansion Register,
Section 13.1.7.7
Virtual PHY Special Control/Status Register, Section 13.1.7.8
General Purpose I/O Configuration Register,
Section 13.1.2.1
General Purpose I/O Data & Direction Register,
Section 13.1.2.2
General Purpose I/O Interrupt Status and Enable Register,
Section 13.1.2.3
1ECh
RESERVED
1F0h
SWITCH_MAC_ADDRH
Switch MAC Address High Register, Section 13.1.5.6
1F4h
SWITCH_MAC_ADDRL
Switch MAC Address Low Register, Section 13.1.5.7
1F8h
RESET_CTL
Reset Control Register, Section 13.1.8.7
1FCh
RESERVED
Reserved for Future Use
200h-2DCh
SWITCH_CSR_DIRECT_DATA
2E0h-3FFh
RESERVED
2008-2016 Microchip Technology Inc.
Reserved for Future Use
Switch Engine CSR Interface Direct Data Register,
Section 13.1.5.8
Reserved for Future Use
DS00002288A-page 127
LAN9313/LAN9313i
13.1.1
INTERRUPTS
This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt
output pin and the various LAN9313/LAN9313i interrupt sources. For more information on the LAN9313/LAN9313i interrupts, refer to Section 5.0, "System Interrupts," on page 41.
13.1.1.1
Interrupt Configuration Register (IRQ_CFG)
Offset:
054h
Size:
32 bits
This read/write register configures and indicates the state of the IRQ signal.
Bits
Description
Type
Default
31:24
Interrupt De-assertion Interval (INT_DEAS)
This field determines the Interrupt Request De-assertion Interval in multiples
of 10 microseconds.
R/W
00h
RESERVED
RO
-
Interrupt De-assertion Interval Clear (INT_DEAS_CLR)
Writing a 1 to this register clears the de-assertion counter in the Interrupt
Controller, thus causing a new de-assertion interval to begin (regardless of
whether or not the Interrupt Controller is currently in an active de-assertion
interval).
R/W
SC
0h
RO
SC
0b
RO
0b
Setting this field to zero causes the device to disable the INT_DEAS Interval,
reset the interval counter and issue any pending interrupts. If a new, nonzero value is written to this field, any subsequent interrupts will obey the new
setting.
23:15
14
0: Normal operation
1: Clear de-assertion counter
13
Interrupt De-assertion Status (INT_DEAS_STS)
When set, this bit indicates that interrupts are currently in a de-assertion
interval, and will not be sent to the IRQ pin. When this bit is clear, interrupts
are not currently in a de-assertion interval, and will be sent to the IRQ pin.
0: No interrupts in de-assertion interval
1: Interrupts in de-assertion interval
12
Master Interrupt (IRQ_INT)
This read-only bit indicates the state of the internal IRQ line, regardless of
the setting of the IRQ_EN bit, or the state of the interrupt de-assertion
function. When this bit is set, one of the enabled interrupts is currently active.
0: No enabled interrupts active
1: One or more enabled interrupts active
11:9
8
RESERVED
RO
-
IRQ Enable (IRQ_EN)
This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ
output is disabled and permanently de-asserted. This bit has no effect on any
internal interrupt status bits.
R/W
0b
0: Disable output on IRQ pin
1: Enable output on IRQ pin
7:5
4
RESERVED
IRQ Polarity (IRQ_POL)
When cleared, this bit enables the IRQ line to function as an active low
output. When set, the IRQ output is active high. When the IRQ is configured
as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the
interrupt is always active low.
RO
-
R/W
NASR
0b
Note 13-1
0: IRQ active low output
1: IRQ active high output
3:1
RESERVED
DS00002288A-page 128
RO
-
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Bits
Description
Type
Default
0
IRQ Buffer Type (IRQ_TYPE)
When this bit is cleared, the IRQ pin functions as an open-drain output for
use in a wired-or interrupt configuration. When set, the IRQ is a push-pull
driver.
R/W
NASR
0b
Note 13-1
When configured as an open-drain output, the IRQ_POL bit is
ignored and the interrupt output is always active low.
0: IRQ pin open-drain output
1: IRQ pin push-pull driver
Note:
Note 13-1
13.1.1.2
Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Reset Control
Register (RESET_CTL) is set.
Interrupt Status Register (INT_STS)
Offset:
058h
Size:
32 bits
This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt
conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register
reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where indicated as R/WC, writing a 1 to the corresponding bits acknowledges and
clears the interrupt.
Bits
Description
Type
Default
31
Software Interrupt (SW_INT)
This interrupt is generated when the SW_INT_EN bit of the Interrupt Enable
Register (INT_EN) is set high. Writing a one clears this interrupt.
R/WC
0b
30
Device Ready (READY)
This interrupt indicates that the LAN9313/LAN9313i is ready to be accessed
after a power-up or reset condition.
R/WC
0b
29
1588 Interrupt Event (1588_EVNT)
This bit indicates an interrupt event from the IEEE 1588 module. This bit
should be used in conjunction with the 1588 Interrupt Status and Enable
Register (1588_INT_STS_EN) to determine the source of the interrupt event
within the 1588 module.
RO
0b
28
Switch Fabric Interrupt Event (SWITCH_INT)
This bit indicates an interrupt event from the Switch Fabric. This bit should
be used in conjunction with the Switch Global Interrupt Pending Register
(SW_IPR) to determine the source of the interrupt event within the Switch
Fabric.
RO
0b
27
Port 2 PHY Interrupt Event (PHY_INT2)
This bit indicates an interrupt event from the Port 2 PHY. The source of the
interrupt can be determined by polling the Port x PHY Interrupt Source Flags
Register (PHY_INTERRUPT_SOURCE_x).
RO
0b
26
Port 1 PHY Interrupt Event (PHY_INT1)
This bit indicates an interrupt event from the Port 1 PHY. The source of the
interrupt can be determined by polling the Port x PHY Interrupt Source Flags
Register (PHY_INTERRUPT_SOURCE_x).
RO
0b
25:20
19
18:13
12
11:0
RESERVED
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer Count Register
(GPT_CNT) wraps past zero to FFFFh.
RO
-
R/WC
0b
RESERVED
RO
-
GPIO Interrupt Event (GPIO)
This bit indicates an interrupt event from the General Purpose I/O. The
source of the interrupt can be determined by polling the General Purpose I/O
Interrupt Status and Enable Register (GPIO_INT_STS_EN)
RO
0b
RESERVED
RO
-
2008-2016 Microchip Technology Inc.
DS00002288A-page 129
LAN9313/LAN9313i
13.1.1.3
Interrupt Enable Register (INT_EN)
Offset:
05Ch
Size:
32 bits
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding
interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the
interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of
SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS) bits, which mimic the
layout of this register.
Bits
Description
Type
Default
31
Software Interrupt Enable (SW_INT_EN)
R/W
0b
30
Device Ready Enable (READY_EN)
R/W
0b
29
1588 Interrupt Event Enable (1588_EVNT_EN)
R/W
0b
28
Switch Engine Interrupt Event Enable (SWITCH_INT_EN)
R/W
0b
27
Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)
R/W
0b
26
Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)
R/W
0b
RESERVED
RO
-
GP Timer Interrupt Enable (GPT_INT_EN)
R/W
0b
RESERVED
RO
-
25:20
19
18:13
GPIO Interrupt Event Enable (GPIO_EN)
R/W
0b
11:0
RESERVED
RO
-
13.1.2
GPIO/LED
12
This section details the General Purpose I/O (GPIO) and LED related System CSR’s.
13.1.2.1
General Purpose I/O Configuration Register (GPIO_CFG)
Offset:
1E0h
Size:
32 bits
This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins is configured here
as well as the IEEE 1588 timestamping and clock compare event output properties of the GPIO[9:8] pins.
Bits
31:30
29:28
Description
Type
Default
RESERVED
RO
-
GPIO 1588 Timer Interrupt Clear Enable 9-8
(GPIO_1588_TIMER_INT_CLEAR_EN[9:8])
These bits enable inputs on GPIO9 and GPIO8 to clear the
1588_TIMER_INT bit of the 1588 Interrupt Status and Enable Register
(1588_INT_STS_EN). The polarity of these inputs is determined by
GPIO_INT_POL[9:8].
R/W
00b
Note:
The GPIO must be configured as an input for this function to
operate. For the clear function, GPIO inputs are edge sensitive and
must be active for greater than 40 nS to be recognized.
DS00002288A-page 130
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Bits
Description
Type
Default
27:16
GPIO Interrupt Polarity 11-0 (GPIO_INT_POL[11:0])
These bits set the interrupt polarity of the 12 GPIO pins. The configured level
(high/low) will set the corresponding GPIO_INT bit in the General Purpose
I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN).
R/W
0h
R/W
0h
R/W
1b
R/W
1b
R/W
0h
0: Sets low logic level trigger on corresponding GPIO pin
1: Sets high logic level trigger on corresponding GPIO pin
GPIO_INT_POL[9:8] also determines the polarity of the GPIO IEEE 1588
time clock capture events and the GPIO 1588 Timer Interrupt Clear inputs.
Refer to Section 12.2, "GPIO Operation," on page 120 for additional
information.
15:14
1588 GPIO Output Enable 9-8 (1588_GPIO_OE[9:8])
These bits configure GPIO 9 and GPIO 8 to output 1588 clock compare
events.
0: Disables the output of 1588 clock compare events
1: Enables the output of 1588 clock compare events
Note:
13
These bits override the direction bits in the General Purpose I/O
Data & Direction Register (GPIO_DATA_DIR) register. However, the
GPIO buffer type (GPIOBUF[11:0]) in the General Purpose I/O
Configuration Register (GPIO_CFG) is not overridden.
GPIO 9 Clock Event Polarity (GPIO_EVENT_POL_9)
This bit determines if the 1588 clock event output on GPIO 9 is active high
or low.
0: 1588 clock event output active low
1: 1588 clock event output active high
12
GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8)
This bit determines if the 1588 clock event output on GPIO 8 is active high
or low.
0: 1588 clock event output active low
1: 1588 clock event output active high
11:0
GPIO Buffer Type 11-0 (GPIOBUF[11:0])
This field sets the buffer types of the 12 GPIO pins.
0: Corresponding GPIO pin configured as an open-drain driver
1: Corresponding GPIO pin configured as a push/pull driver
As an open-drain driver, the output pin is driven low when the corresponding
data register is cleared, and is not driven when the corresponding data
register is set.
As an open-drain driver used for 1588 Clock Events, the corresponding
GPIO_EVENT_POL_8 and GPIO_EVENT_POL_9 bits determine when the
corresponding pin is driven per the following table:
GPIOx Clock Event Polarity
1588 Clock Event
Pin State
0
no
not driven
0
yes
driven low
1
no
driven low
1
yes
not driven
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LAN9313/LAN9313i
13.1.2.2
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)
Offset:
1E4h
Size:
32 bits
This read/write register configures the direction of the 12 GPIO pins and contains the GPIO input and output data bits.
Bits
Description
Type
Default
31:28
RESERVED
RO
-
27:16
GPIO Direction 11-0 (GPIODIR[11:0])
These bits set the input/output direction of the 12 GPIO pins.
R/W
0h
RESERVED
RO
-
GPIO Data 11-0 (GPIOD[11:0])
When a GPIO pin is enabled as an output, the value written to this field is
output on the corresponding GPIO pin. Upon a read, the value returned
depends on the current direction of the pin. If the pin is an input, the data
reflects the current state of the corresponding GPIO pin. If the pin is an
output, the data is the value that was last written into this register. For GPIOs
11-10 and 7-0, the pin direction is determined by the GPDIR bits of this
register. For GPIOs 9 and 8, the pin direction is determined by the GPDIR
bits and the 1588_GPIO_OE bits in the General Purpose I/O Configuration
Register (GPIO_CFG).
R/W
0h
0: GPIO pin is configured as an input
1: GPIO pin is configured as an output
15:12
11:0
13.1.2.3
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
Offset:
1E8h
Size:
32 bits
This read/write register contains the GPIO interrupt status bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are
cascaded into bit 12 (GPIO) of the Interrupt Status Register (INT_STS). Writing a 1 to any of the interrupt enable bits
will enable the corresponding interrupt as a source. Status bits will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register. Bit 12 (GPIO_EN) of the Interrupt Enable Register
(INT_EN) must also be set in order for an actual system level interrupt to occur. Refer to Section 5.0, "System Interrupts," on page 41 for additional information.
Bits
Description
Type
Default
31:28
RESERVED
RO
-
27:16
GPIO Interrupt Enable[11:0] (GPIO[11:0]_INT_EN)
When set, these bits enable the corresponding GPIO interrupt.
R/W
0h
Note:
15:12
11:0
The GPIO interrupts must also be enabled via bit 12 (GPIO_EN) of
the Interrupt Enable Register (INT_EN) in order to cause the
interrupt pin (IRQ) to be asserted.
RESERVED
GPIO Interrupt[11:0] (GPIO[11:0]_INT)
These signals reflect the interrupt status as generated by the GPIOs. These
interrupts are configured through the General Purpose I/O Configuration
Register (GPIO_CFG).
Note:
RO
-
R/WC
0h
As GPIO interrupts, GPIO inputs are level sensitive and must be
active greater than 40 nS to be recognized as interrupt inputs.
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LAN9313/LAN9313i
13.1.2.4
LED Configuration Register (LED_CFG)
Offset:
1BCh
Size:
32 bits
This read/write register configures the GPIO[7:0] pins as LED[7:0] pins and sets their functionality.
Bits
31:10
9:8
Description
Type
Default
RESERVED
RO
-
LED Function 1-0 (LED_FUN[1:0])
These bits control the function associated with each LED pin as shown in
Table 12-1 of Section 12.3, "LED Operation," on page 122.
R/W
Note 13-2
R/W
Note 13-3
Note:
7:0
In order for these assignments to be valid, the particular pin must
be enabled as an LED output pin via the LED_EN[7:0] bits of this
register.
LED Enable 7-0 (LED_EN[7:0])
This field toggles the functionality of the GPIO[7:0] pins between GPIO and
LED.
0: Enables the associated pin as a GPIO signal
1: Enables the associated pin as a LED output
Note 13-2
The default value of this field is determined by the configuration strap LED_fun_strap[1:0].
Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration
straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration
Straps," on page 33 for more information.
Note 13-3
The default value of this field is determined by the configuration strap LED_en_strap[7:0].
Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration
straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration
Straps," on page 33 for more information.
13.1.3
EEPROM
This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been
connected to the LAN9313/LAN9313i. Refer to chapter Section 8.2, "I2C/Microwire Master EEPROM Controller," on
page 83 for additional information on the various modes (I2C and Microwire) of the EEPROM Controller (EPC).
13.1.3.1
EEPROM Command Register (E2P_CMD)
Offset:
1B4h
Size:
32 bits
This read/write register is used to control the read and write operations of the serial EEPROM.
Bits
Description
Type
Default
31
EEPROM Controller Busy (EPC_BUSY)
When a 1 is written into this bit, the operation specified in the
EPC_COMMAND field of this register is performed at the specified EEPROM
address. This bit will remain set until the selected operation is complete. In
the case of a read, this indicates that the Host can read valid data from the
EEPROM Data Register (E2P_DATA). The E2P_CMD and E2P_DATA
registers should not be modified until this bit is cleared. In the case where a
write is attempted and an EEPROM is not present, the EPC_BUSY bit
remains set until the EEPROM Controller Timeout (EPC_TIMEOUT) bit is
set. At this time the EPC_BUSY bit is cleared.
R/W
SC
0b
Note:
EPC_BUSY is set immediately following power-up, or pin reset, or
DIGITAL_RST reset. After the EEPROM Loader has finished
loading, the EPC_BUSY bit is cleared. Refer to chapter Section
8.2.4, "EEPROM Loader," on page 93 for more information.
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LAN9313/LAN9313i
Bits
Description
Type
Default
30:28
EEPROM Controller Command (EPC_COMMAND)
This field is used to issue commands to the EEPROM controller. The
EEPROM controller will execute a command when the EPC_BUSY bit is set.
A new command must not be issued until the previous command completes.
The field is encoded as follows:
R/W
000b
RO
-
Note:
[30]
[29]
[28]
Operation
0
0
0
READ
0
0
1
EWDS
0
1
0
EWEN
0
1
1
WRITE
1
0
0
WRAL
1
0
1
ERASE
1
1
0
ERAL
1
1
1
RELOAD
Only the READ, WRITE and RELOAD commands are valid for I2C mode. If
an unsupported command is attempted, the EPC_BUSY bit will be cleared
and EPC_TIMEOUT will be set.
The EEPROM operations are defined as follows:
READ (Read Location)
This command will cause a read of the EEPROM location pointed to by the
EPC_ADDRESS bit field. The result of the read is available in the EEPROM Data
Register (E2P_DATA).
EWDS (Erase/Write Disable)
(Microwire mode only) - When this command is issued, the EEPROM will ignore erase
and write commands. To re-enable erase/writes operations, issue the EWEN
command.
EWEN (Erase/Write Enable)
(Microwire mode only) - Enables the EEPROM for erase and write operations. The
EEPROM will allow erase and write operations until the EWDS command is sent, or
until the power is cycled. The Microwire EEPROM device will power-up in the
erase/write disabled state. Any erase or write operations will fail until an EWEN
command is issued.
WRITE (Write Location)
If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the EEPROM Data Register (E2P_DATA) to be written to the EEPROM
location selected by the EPC_ADDRESS field. For Microwire, erase/write operations
must be enabled in the EEPROM.
WRAL (Write All)
(Microwire mode only) - If erase/write operations are enabled in the EEPROM, this
command will cause the contents of the EEPROM Data Register (E2P_DATA) to be
written to every EEPROM memory location.
ERASE (Erase Location)
(Microwire mode only) - If erase/write operations are enabled in the EEPROM, this
command will erase the location selected by the EPC_ADDRESS field.
ERAL (Erase All)
(Microwire mode only) - If erase/write operations are enabled in the EEPROM, this
command will initiate a bulk erase of the entire EEPROM.
RELOAD (EEPROM Loader Reload)
Instructs the EEPROM Loader to reload the device from the EEPROM. If a value of
A5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and the RELOAD operation will fail. The CFG_LOADED bit indicates
a successful load. Following this command, the device will enter the not ready state.
The READY bit in the Hardware Configuration Register (HW_CFG) should be polled
to determine then the RELOAD is complete.
27:19
RESERVED
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LAN9313/LAN9313i
Bits
Description
Type
Default
18
EEPROM Loader Address Overflow (LOADER_OVERFLOW)
This bit indicates that the EEPROM Loader tried to read past the end of the
EEPROM address space. This indicates misconfigured EEPROM data.
RO
0b
R/WC
0b
R/WC
0b
R/W
0000h
This bit is cleared when the EEPROM Loader is restarted with a RELOAD
command, or a Digital Reset(DIGITAL_RST).
17
EEPROM Controller Timeout (EPC_TIMEOUT)
This bit is set when a timeout occurs, indicating the last operation was
unsuccessful. If an EEPROM ERASE, ERAL, WRITE or WRAL operation is
performed and no response is received from the EEPROM within 30mS, the
EEPROM controller will timeout and return to its idle state.
For the I2C mode, the bit is also set if the EEPROM fails to respond with the
appropriate ACKs, if the EEPROM slave device holds the clock low for more
than 30ms, or if an unsupported EPC_COMMAND is attempted.
This bit is cleared when written high.
Note:
16
When in Microwire mode, if an EEPROM device is not connected,
an internal pull-down on the EEDI pin will keep the EEDI signal low
and allow timeouts to occur. If EEDI is pulled high externally, EPC
commands will not time out if an EEPROM device is not connected.
In this case the EPC_BUSY bit will be cleared as soon as the
command sequence is complete. It should also be noted that the
ERASE, ERAL, WRITE and WRAL commands are the only EPC
commands that will timeout if an EEPROM device is not present
AND the EEDI signal is pulled low.
Configuration Loaded (CFG_LOADED)
When set, this bit indicates that a valid EEPROM was found and the
EEPROM Loader completed normally. This bit is set upon a successful load.
It is cleared on power-up, pin and DIGITAL_RST resets, or at the start of a
RELOAD.
This bit is cleared when written high.
15:0
13.1.3.2
EEPROM Controller Address (EPC_ADDRESS)
This field is used by the EEPROM Controller to address a specific memory
location in the serial EEPROM. This address must be byte aligned.
EEPROM Data Register (E2P_DATA)
Offset:
1B8h
Size:
32 bits
This read/write register is used in conjunction with the EEPROM Command Register (E2P_CMD) to perform read and
write operations with the serial EEPROM.
Bits
Description
Type
Default
31:8
RESERVED
RO
-
7:0
EEPROM Data (EEPROM_DATA)
This field contains the data read from or written to the EEPROM.
R/W
00h
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LAN9313/LAN9313i
13.1.4
IEEE 1588
This section details the IEEE 1588 timestamp related registers. Each port of the LAN9313/LAN9313i has a 1588 timestamp block with 8 related registers, 4 for transmit capture and 4 for receive capture. These sets of registers are identical
in functionality for each port, and thus their register descriptions have been consolidated. In these cases, the register
names will be amended with a lowercase “x” in place of the port designation. The wildcard “x” should be replaced with
“1”, “2”, or “MII” for the Port 1, Port 2, and Port 0(External MII) respectively. A list of all the 1588 related registers can be
seen in Table 13-1. For more information on the IEEE 1588, refer to Section 10.0, "IEEE 1588 Hardware Time Stamp
Unit," on page 113.
13.1.4.1
Port x 1588 Clock High-DWORD Receive Capture Register
(1588_CLOCK_HI_RX_CAPTURE_x)
Offset:
Port 1: 100h
Port 2: 120h
Port 0: 140h
Size:
32 bits
Bits
Description
Type
Default
31:0
Timestamp High (TS_HI)
This field contains the high 32-bits of the timestamp taken on the receipt of
a 1588 Sync or Delay_Req packet.
RO
00000000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
13.1.4.2
Port x 1588 Clock Low-DWORD Receive Capture Register
(1588_CLOCK_LO_RX_CAPTURE_x)
Offset:
Port 1: 104h
Port 2: 124h
Port 0: 144h
Size:
32 bits
Bits
Description
Type
Default
31:0
Timestamp Low (TS_LO)
This field contains the low 32-bits of the timestamp taken on the receipt of a
1588 Sync or Delay_Req packet.
RO
00000000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
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LAN9313/LAN9313i
13.1.4.3
Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register
(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)
Offset:
Bits
Port 1: 108h
Port 2: 128h
Port 0: 148h
Size:
32 bits
Description
Type
Default
31:16
Sequence ID (SEQ_ID)
This field contains the Sequence ID from the 1588 Sync or Delay_Req
packet.
RO
0000h
15:0
Source UUID High (SRC_UUID_HI)
This field contains the high 16-bits of the Source UUID from the 1588 Sync
or Delay_Req packet.
RO
0000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
13.1.4.4
Port x 1588 Source UUID Low-DWORD Receive Capture Register
(1588_SRC_UUID_LO_RX_CAPTURE_x)
Offset:
Port 1: 10Ch
Port 2: 12Ch
Port 0: 14Ch
Size:
32 bits
Bits
Description
Type
Default
31:0
Source UUID Low (SRC_UUID_LO)
This field contains the low 32-bits of the Source UUID from the 1588 Sync
or Delay_Req packet.
RO
00000000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
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LAN9313/LAN9313i
13.1.4.5
Port x 1588 Clock High-DWORD Transmit Capture Register
(1588_CLOCK_HI_TX_CAPTURE_x)
Offset:
Bits
31:0
Port 1: 110h
Port 2: 130h
Port 0: 150h
Size:
32 bits
Description
Timestamp High (TS_HI)
This field contains the high 32-bits of the timestamp taken on the
transmission of a 1588 Sync or Delay_Req packet.
Type
Default
RO
00000000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
13.1.4.6
Port x 1588 Clock Low-DWORD Transmit Capture Register
(1588_CLOCK_LO_TX_CAPTURE_x)
Offset:
Port 1: 114h
Port 2: 134h
Port 0: 154h
Size:
32 bits
Bits
Description
Type
Default
31:0
Timestamp Low (TS_LO)
This field contains the low 32-bits of the timestamp taken on the transmission
of a 1588 Sync or Delay_Req packet.
RO
00000000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
DS00002288A-page 138
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LAN9313/LAN9313i
13.1.4.7
Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register
(1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)
Offset:
Bits
Port 1: 118h
Port 2: 138h
Port 0: 158h
Size:
32 bits
Description
Type
Default
31:16
Sequence ID (SEQ_ID)
This field contains the Sequence ID from the 1588 Sync or Delay_Req
packet.
RO
0000h
15:0
Source UUID High (SRC_UUID_HI)
This field contains the high 16-bits of the Source UUID from the 1588 Sync
or Delay_Req packet.
RO
0000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
13.1.4.8
Port x 1588 Source UUID Low-DWORD Transmit Capture Register
(1588_SRC_UUID_LO_TX_CAPTURE_x)
Offset:
Port 1: 11Ch
Port 2: 13Ch
Port 0: 15Ch
Size:
32 bits
Bits
Description
Type
Default
31:0
Source UUID Low (SRC_UUID_TX_LO)
This field contains the low 32-bits of the Source UUID from the 1588 Sync
or Delay_Req packet.
RO
00000000h
Note:
• The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the 1588
Configuration Register (1588_CONFIG).
• There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to
Section 13.1.4 for additional information.
• For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
13.1.4.9
GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8)
Offset:
160h
Size:
32 bits
This read only register combined with the GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) form the 64-bit GPIO 8 timestamp capture.
Bits
Description
Type
Default
31:0
Timestamp High (TS_HI)
This field contains the high 32-bits of the timestamp upon activation of GPIO
8.
RO
00000000h
13.1.4.10
GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8)
Offset:
164h
Size:
32 bits
This read only register combined with the GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8) form the 64-bit GPIO 8 timestamp capture.
Bits
Description
Type
Default
31:0
Timestamp Low (TS_LO)
This field contains the low 32-bits of the timestamp upon activation of GPIO
8.
RO
00000000h
13.1.4.11
GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9)
Offset:
168h
Size:
32 bits
This read only register combined with the GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) form the 64-bit GPIO 9 timestamp capture.
Bits
Description
Type
Default
31:0
Timestamp High (TS_HI)
This field contains the high 32-bits of the timestamp upon activation of GPIO
9.
RO
00000000h
13.1.4.12
GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9)
Offset:
16Ch
Size:
32 bits
This read only register combined with the GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9) form the 64-bit GPIO 9 timestamp capture.
Bits
Description
Type
Default
31:0
Timestamp Low (TS_LO)
This field contains the low 32-bits of the timestamp upon activation of GPIO
9.
RO
00000000h
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LAN9313/LAN9313i
13.1.4.13
1588 Clock High-DWORD Register (1588_CLOCK_HI)
Offset:
170h
Size:
32 bits
This read/write register combined with 1588 Clock Low-DWORD Register (1588_CLOCK_LO) form the 64-bit 1588
Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has a base frequency of 100MHz,
which can be adjusted via the 1588 Clock Addend Register (1588_CLOCK_ADDEND) accordingly. Refer to Section
10.0, "IEEE 1588 Hardware Time Stamp Unit," on page 113 for additional information.
Bits
31:0
Description
Clock High (CLOCK_HI)
This field contains the high 32-bits of the 64-bit 1588 Clock.
Type
Default
R/W
00000000h
Note:
• Both this register and the 1588 Clock Low-DWORD Register (1588_CLOCK_LO) must be written for either to be
affected.
• The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) is set.
13.1.4.14
1588 Clock Low-DWORD Register (1588_CLOCK_LO)
Offset:
174h
Size:
32 bits
This read/write register combined with 1588 Clock High-DWORD Register (1588_CLOCK_HI) form the 64-bit 1588
Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has a base frequency of 100MHz,
which can be adjusted via the 1588 Clock Addend Register (1588_CLOCK_ADDEND) accordingly. Refer to Section
10.0, "IEEE 1588 Hardware Time Stamp Unit," on page 113 for additional information.
Bits
31:0
Description
Clock Low (CLOCK_LO)
This field contains the low 32-bits of the 64-bit 1588 Clock.
Type
Default
R/W
00000000h
Note:
• Both this register and the 1588 Clock High-DWORD Register (1588_CLOCK_HI) must be written for either to be
affected.
• The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) is set.
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LAN9313/LAN9313i
13.1.4.15
1588 Clock Addend Register (1588_CLOCK_ADDEND)
Offset:
178h
Size:
32 bits
This read/write register is responsible for adjusting the 64-bit 1588 Clock frequency. Refer to Section 10.0, "IEEE 1588
Hardware Time Stamp Unit," on page 113 for details on how to properly use this register.
Bits
Description
Type
Default
31:0
Clock Addend (CLOCK_ADDEND)
This 32-bit value is added to the 1588 frequency divisor accumulator every
cycle. This allows the base 100MHz frequency of the 64-bit 1588 Clock to
be adjusted accordingly.
R/W
00000000h
13.1.4.16
1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)
Offset:
17Ch
Size:
32 bits
This read/write register combined with 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) form
the 64-bit 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can
be used to trigger an interrupt upon at match. Refer to Section 10.0, "IEEE 1588 Hardware Time Stamp Unit," on
page 113 for additional information.
Bits
Description
Type
Default
31:0
Clock Target High (CLOCK_TARGET_HI)
This field contains the high 32-bits of the 64-bit 1588 Clock Compare value.
R/W
00000000h
Note:
13.1.4.17
Both this register and the 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) must
be written for either to be affected.
1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)
Offset:
180h
Size:
32 bits
This read/write register combined with 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) form
the 64-bit 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can
be used to trigger an interrupt upon at match. Refer to Section 10.0, "IEEE 1588 Hardware Time Stamp Unit," on
page 113 for additional information.
Bits
Description
Type
Default
31:0
Clock Target Low (CLOCK_TARGET_LO)
This field contains the low 32-bits of the 64-bit 1588 Clock Compare value.
R/W
00000000h
Note:
Both this register and the 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) must be
written for either to be affected.
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LAN9313/LAN9313i
13.1.4.18
1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)
Offset:
184h
Size:
32 bits
This read/write register combined with 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) form the 64-bit 1588 Clock Target Reload value. The 1588 Clock Target Reload is the value that is
reloaded to the 1588 Clock Compare value when a clock compare event occurs and the Reload/Add (RELOAD_ADD)
bit of the 1588 Configuration Register (1588_CONFIG) is set. Refer to Section 10.0, "IEEE 1588 Hardware Time Stamp
Unit," on page 113 for additional information.
Bits
31:0
Note:
13.1.4.19
Description
Clock Target Reload High (CLOCK_TARGET_RELOAD_HI)
This field contains the high 32-bits of the 64-bit 1588 Clock Target Reload
value that is reloaded to the 1588 Clock Compare value.
Type
Default
R/W
00000000h
Both this register and the 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) must be written for either to be affected.
1588 Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO)
Offset:
188h
Size:
32 bits
This read/write register combined with 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) form the 64-bit 1588 Clock Target Reload value. The 1588 Clock Target Reload is the value that is reloaded
or added to the 1588 Clock Compare value when a clock compare event occurs. Whether this value is reloaded or added
is determined by the Reload/Add (RELOAD_ADD) bit of the 1588 Configuration Register (1588_CONFIG). Refer to
Section 10.0, "IEEE 1588 Hardware Time Stamp Unit," on page 113 for additional information.
Bits
Description
Type
Default
31:0
Clock Target Reload Low (CLOCK_TARGET_RELOAD_LO)
This field contains the low 32-bits of the 64-bit 1588 Clock Target Reload
value that is reloaded to the 1588 Clock Compare value. Alternatively, these
32-bits are added to the 1588 Clock Compare value when configured
accordingly.
R/W
00000000h
Note:
Both this register and the 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) must be written for either to be affected.
2008-2016 Microchip Technology Inc.
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LAN9313/LAN9313i
13.1.4.20
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)
Offset:
18Ch
Size:
32 bits
This read/write register combined with the 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO)
forms the 48-bit Auxiliary (user defined) MAC address. The Auxiliary MAC address can be enabled for each port of the
LAN9313/LAN9313i via their respective User Defined MAC Address Enable bit in the 1588 Configuration Register
(1588_CONFIG). Refer to Section 10.0, "IEEE 1588 Hardware Time Stamp Unit," on page 113 for additional information.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:0
Auxiliary MAC Address High (AUX_MAC_HI)
This field contains the high 16-bits of the Auxiliary MAC address used for
PTP packet detection.
R/W
0000h
13.1.4.21
1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO)
Offset:
190h
Size:
32 bits
This read/write register combined with the 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)
forms the 48-bit Auxiliary (user defined) MAC address. The Auxiliary MAC address can be enabled for each port of the
LAN9313/LAN9313i via their respective User Defined MAC Address Enable bit in the 1588 Configuration Register
(1588_CONFIG). Refer to Section 10.0, "IEEE 1588 Hardware Time Stamp Unit," on page 113 for additional information.
Bits
Description
Type
Default
31:0
Auxiliary MAC Address Low (AUX_MAC_LO)
This field contains the low 32-bits of the Auxiliary MAC address used for PTP
packet detection.
R/W
00000000h
13.1.4.22
1588 Configuration Register (1588_CONFIG)
Offset:
194h
Size:
32 bits
This read/write register is responsible for the configuration of the 1588 timestamps for all ports.
Bits
Description
Type
Default
31
Master/Slave Port 2 (M_nS_2)
When set, Port 2 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 2 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
R/W
0b
30
Primary MAC Address Enable Port 2 (MAC_PRI_EN_2)
This bit enables/disables the primary MAC address on Port 2.
R/W
1b
R/W
0b
0: Disables primary MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 2
29
Alternate MAC Address 1 Enable Port 2 (MAC_ALT1_EN_2)
This bit enables/disables the alternate MAC address 1 on Port 2.
0: Disables alternate MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 2
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LAN9313/LAN9313i
Bits
28
Description
Alternate MAC Address 2 Enable Port 2 (MAC_ALT2_EN_2)
This bit enables/disables the alternate MAC address 2 on Port 2.
Type
Default
R/W
0b
R/W
0b
R/W
0b
R/W
1b
R/W
1b
0: Disables alternate MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 2
27
Alternate MAC Address 3 Enable Port 2 (MAC_ALT3_EN_2)
This bit enables/disables the alternate MAC address 3 on Port 2.
0: Disables alternate MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 2
26
User Defined MAC Address Enable Port 2 (MAC_USER_EN_2)
This bit enables/disables the auxiliary MAC address on Port 2. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 2
1: Enables auxiliary MAC address as a PTP address on Port 2
25
Lock Enable RX Port 2 (LOCK_RX_2)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 2 is already set due to a previous capture.
0: Disables RX Port 2 Lock
1: Enables RX Port 2 Lock
24
Lock Enable TX Port 2 (LOCK_TX_2)
This bit enables/disables the TX lock. This lock prevents a 1588 capture from
overwriting the Clock, UUDI and Sequence ID values if the 1588 TX interrupt
for Port 2 is already set due to a previous capture.
0: Disables TX Port 2 Lock
1: Enables TX Port 2 Lock
23
Master/Slave Port 1 (M_nS_1)
When set, Port 1 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 1 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
R/W
0b
22
Primary MAC Address Enable Port 1 (MAC_PRI_EN_1)
This bit enables/disables the primary MAC address on Port 1.
R/W
1b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
0: Disables primary MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 1
21
Alternate MAC Address 1 Enable Port 1 (MAC_ALT1_EN_1)
This bit enables/disables the alternate MAC address 1 on Port 1.
0: Disables alternate MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 1
20
Alternate MAC Address 2 Enable Port 1 (MAC_ALT2_EN_1)
This bit enables/disables the alternate MAC address 2 on Port 1.
0: Disables alternate MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 1
19
Alternate MAC Address 3 Enable Port 1 (MAC_ALT3_EN_1)
This bit enables/disables the alternate MAC address 3 on Port 1.
0: Disables alternate MAC address on Port 1
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 1
18
User Defined MAC Address Enable Port 1 (MAC_USER_EN_1)
This bit enables/disables the auxiliary MAC address on Port 1. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 1
1: Enables auxiliary MAC address as a PTP address on Port 1
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LAN9313/LAN9313i
Bits
17
Description
Lock Enable RX Port 1 (LOCK_RX_1)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 1 is ready set due to a previous capture.
Type
Default
R/W
1b
R/W
1b
R/W
0b
R/W
1b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
1b
0: Disables RX Port 1 Lock
1: Enables RX Port 1 Lock
16
Lock Enable TX Port 1 (LOCK_TX_1)
This bit enables/disables the TX lock. This lock prevents a 1588 capture from
overwriting the Clock, UUDI and Sequence ID values if the 1588 TX interrupt
for Port 1 is ready set due to a previous capture.
0: Disables TX Port 1 Lock
1: Enables TX Port 1 Lock
15
Master/Slave Port 0(External MII)(M_nS_MII)
When set, Port 0 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 0 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
Note:
14
For Port 0, receive is defined as data from the switch fabric, while
transmit is defined as data to the switch fabric.
Primary MAC Address Enable Port 0(External MII) (MAC_PRI_EN_MII)
This bit enables/disables the primary MAC address on Port 0.
0: Disables primary MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 0
13
Alternate MAC Address 1 Enable Port 0(External MII)
(MAC_ALT1_EN_MII)
This bit enables/disables the alternate MAC address 1 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0
12
Alternate MAC Address 2 Enable Port 0(External MII)
(MAC_ALT2_EN_MII)
This bit enables/disables the alternate MAC address 2 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0
11
Alternate MAC Address 3 Enable Port 0(External MII)
(MAC_ALT3_EN_MII)
This bit enables/disables the alternate MAC address 3 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0
10
User Defined MAC Address Enable Port 0(External MII)
(MAC_USER_EN_MII)
This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 0
1: Enables auxiliary MAC address as a PTP address on Port 0
9
Lock Enable RX Port 0(External MII) (LOCK_RX_MII)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables RX Port 0 Lock
1: Enables RX Port 0 Lock
Note:
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
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LAN9313/LAN9313i
Bits
Description
Type
Default
8
Lock Enable TX Port 0(External MII) (LOCK_TX_MII)
This bit enables/disables the TX lock. This lock prevents a 1588 capture from
overwriting the Clock, UUDI and Sequence ID values if the 1588 TX interrupt
for Port 0 is ready set due to a previous capture.
R/W
1b
0: Disables TX Port 0 Lock
1: Enables TX Port 0 Lock
Note:
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
7
RESERVED
RO
-
6
Lock Enable GPIO 9 (LOCK_GPIO_9)
This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO9 interrupt in the 1588
Interrupt Status and Enable Register (1588_INT_STS_EN) is already set due
to a previous capture.
R/W
1b
R/W
1b
R/W
00b
R/W
00b
0: Disables GPIO 9 Lock
1: Enables GPIO 9 Lock
5
Lock Enable GPIO 8 (LOCK_GPIO_8)
This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO8 interrupt in the 1588
Interrupt Status and Enable Register (1588_INT_STS_EN) is already set due
to a previous capture.
0: Disables GPIO 8 Lock
1: Enables GPIO 8 Lock
4:3
GPIO 9 Clock Event Mode (GPIO_EVENT_9)
These bits determine the output on GPIO 9 when a clock target compare
event occurs.
00:
01:
10:
11:
2:1
100ns pulse output
Toggle output
1588_TIMER_INT bit value in the 1588_INT_STS_EN register output
RESERVED
Note:
The 1588_GPIO_OE[9] bit in the General Purpose I/O
Configuration Register (GPIO_CFG) must be set in order for the
GPIO output to be controlled by the 1588 block.
Note:
The polarity of the pulse or level is set by the
GPIO_EVENT_POL_9 bit in the General Purpose I/O Configuration
Register (GPIO_CFG). The GPIOBUF[9] bit still determines the
GPIO buffer type.
GPIO 8 Clock Event Mode (GPIO_EVENT_8)
These bits determine the output on GPIO 8 when a clock target compare
event occurs.
00:
01:
10:
11:
100ns pulse output
Toggle output
1588_TIMER_INT bit value in the 1588_INT_STS_EN register output
RESERVED
Note:
The 1588_GPIO_OE[8] bit in the General Purpose I/O
Configuration Register (GPIO_CFG) must be set in order for the
GPIO output to be controlled by the 1588 block.
Note:
The polarity of the pulse or level is set by the
GPIO_EVENT_POL_8 bit in the General Purpose I/O Configuration
Register (GPIO_CFG). The GPIOBUF[8] bit still determines the
GPIO buffer type.
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LAN9313/LAN9313i
Bits
Description
Type
Default
0
Reload/Add (RELOAD_ADD)
This bit determines the course of action when a clock target compare event
occurs. When set, the 1588 Clock Target High-DWORD Register
(1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD Register
(1588_CLOCK_TARGET_LO) are loaded from the 1588 Clock Target Reload
High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) and 1588
Clock Target Reload/Add Low-DWORD Register
(1588_CLOCK_TARGET_RELOAD_LO) when a clock target compare event
occurs. When low, the Clock Target Low and High Registers are incremented
by the Clock Target Reload Low Register when a clock target compare event
occurs.
R/W
0b
0: Reload upon a clock target compare event
1: Increment upon a clock target compare event
13.1.4.23
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
Offset:
198h
Size:
32 bits
This read/write register contains the IEEE 1588 interrupt status and enable bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are
cascaded into bit 29 (1588_EVNT) of the Interrupt Status Register (INT_STS). Writing a 1 to any of the interrupt enable
bits will enable the corresponding interrupt as a source. Status bits will still reflect the status of the interrupt source
regardless of whether the source is enabled as an interrupt in this register. Bit 29 (1588_EVNT_EN) of the Interrupt
Enable Register (INT_EN) must also be set in order for an actual system level interrupt to occur. Refer to Section 5.0,
"System Interrupts," on page 41 for additional information.
Bits
31:25
Description
Type
Default
RESERVED
RO
-
24
1588 Port 2 RX Interrupt Enable (1588_PORT2_RX_EN)
R/W
0b
23
1588 Port 2 TX Interrupt Enable (1588_PORT2_TX_EN)
R/W
0b
22
1588 Port 1 RX Interrupt Enable (1588_PORT1_RX_EN)
R/W
0b
21
1588 Port 1 TX Interrupt Enable (1588_PORT1_TX_EN)
R/W
0b
20
1588 Port 0(External MII) RX Interrupt Enable (1588_MII_RX_EN)
R/W
0b
19
1588 Port 0(External MII) TX Interrupt Enable (1588_MII_TX_EN)
R/W
0b
18
GPIO9 1588 Interrupt Enable (1588_GPIO9_EN)
R/W
0b
17
GPIO8 1588 Interrupt Enable (1588_GPIO8_EN)
R/W
0b
16
1588 Timer Interrupt Enable (1588_TIMER_EN)
R/W
0b
RESERVED
RO
-
15:9
8
1588 Port 2 RX Interrupt (1588_PORT2_RX_INT)
This interrupt indicates that a packet received by Port 2 matches the
configured PTP packet and the 1588 clock was captured.
R/WC
0b
7
1588 Port 2 TX Interrupt (1588_PORT2_TX_INT)
This interrupt indicates that a packet transmitted by Port 2 matches the
configured PTP packet and the 1588 clock was captured.
R/WC
0b
6
1588 Port 1 RX Interrupt (1588_PORT1_RX_INT)
This interrupt indicates that a packet received by Port 1 matches the
configured PTP packet and the 1588 clock was captured.
R/WC
0b
5
1588 Port 1 TX Interrupt (1588_PORT1_TX_INT)
This interrupt indicates that a packet transmitted by Port 1 matches the
configured PTP packet and the 1588 clock was captured.
R/WC
0b
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LAN9313/LAN9313i
Bits
Description
Type
Default
4
1588 Port 0(External MII) RX Interrupt (1588_MII_RX_INT)
This interrupt indicates that a packet from the switch fabric to the External
MII the matches the configured PTP packet and the 1588 clock was
captured.
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
R/WC
0b
Note:
3
1588 Port 0(External MII) TX Interrupt (1588_MII_TX_INT)
This interrupt indicates that a packet from the External MII to the switch
fabric matches the configured PTP packet and the 1588 clock was captured.
Note:
2
As 1588 capture inputs, GPIO inputs are edge sensitive and must
be active for greater than 40 nS to be recognized as interrupt
inputs.
1588 Timer Interrupt (1588_TIMER_INT)
This interrupt indicates that the 1588 clock equaled or passed the Clock
Target value in the 1588 Clock Target High-DWORD Register
(1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD Register
(1588_CLOCK_TARGET_LO).
Note:
13.1.4.24
As 1588 capture inputs, GPIO inputs are edge sensitive and must
be active for greater than 40 nS to be recognized as interrupt
inputs.
1588 GPIO8 Interrupt (1588_GPIO8_INT)
This interrupt indicates that an event on GPIO8 occurred and the 1588 clock
was captured. These interrupts are configured through the General Purpose
I/O Configuration Register (GPIO_CFG) register.
Note:
0
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
1588 GPIO9 Interrupt (1588_GPIO9_INT)
This interrupt indicates that an event on GPIO9 occurred and the 1588 clock
was captured. These interrupts are configured through the General Purpose
I/O Configuration Register (GPIO_CFG) register.
Note:
1
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
This bit is also cleared by an active edge on GPIO[9:8] if enabled.
For the clear function, GPIO inputs are edge sensitive and must be
active for greater than 40 nS to be recognized as a clear input.
Refer to Section 12.2, "GPIO Operation," on page 120 for additional
information.
1588 Command Register (1588_CMD)
Offset:
19Ch
Size:
32 bits
This register is used to issue 1588 commands. Using the clock snapshot bit allows the host to properly read the current
IEEE 1588 clock values from the 1588 Clock High-DWORD Register (1588_CLOCK_HI) and 1588 Clock Low-DWORD
Register (1588_CLOCK_LO). Refer to section Section 10.3, "IEEE 1588 Clock," on page 117 for additional information.
Bits
31:1
0
Description
Type
Default
RESERVED
RO
-
Clock Snapshot (1588_CLOCK_SNAPSHOT)
Setting this bit causes the current 1588 Clock High-DWORD Register
(1588_CLOCK_HI) and 1588 Clock Low-DWORD Register
(1588_CLOCK_LO) values to be saved so they can be read.
WO
SC
0b
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LAN9313/LAN9313i
13.1.5
SWITCH FABRIC
This section details the memory mapped System CSR’s which are related to the Switch Fabric. The flow control of all
three ports of the switch fabric can be configured via the memory mapped System CSR’s MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_MII. The MAC address used by the switch for Pause frames is configured via the
SWITCH_MAC_ADDRH and SWITCH_MAC_ADDRL registers. In addition, the SWITCH_CSR_CMD, SWITCH_CSR_DATA and SWITCH_CSR_DIRECT_DATA registers serve as a memory mapped accessible interface to the full range
of otherwise inaccessible switch control and status registers. A list of all the switch fabric CSRs can be seen in Table 1312. For additional information on the switch fabric, including a full explanation on how to use the switch fabric CSR interface registers, refer to Section 6.0, "Switch Fabric," on page 45. For detailed descriptions of the Switch Fabric CSR’s
that are accessible via these interface registers, refer to section Section 13.3, "Switch Fabric Control and Status Registers".
13.1.5.1
Port 1 Manual Flow Control Register (MANUAL_FC_1)
Offset:
1A0h
Size:
32 bits
This read/write register allows for the manual configuration of the switch Port 1 flow control. This register also provides
read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer to Section
6.2.3, "Flow Control Enable Logic," on page 47 for additional information.
Note:
The flow control values in the PHY_AN_ADV_1 register (see Section 13.2.2.5, on page 180) within the
PHY are not affected by the values of this register.
Bits
31:7
6
Description
Type
Default
RESERVED
RO
-
Port 1 Backpressure Enable (BP_EN_1)
This bit enables/disables the generation of half-duplex backpressure on
switch Port 1.
R/W
Note 13-4
RO
Note 13-5
RO
Note 13-5
RO
Note 13-5
R/W
Note 13-6
R/W
Note 13-6
0: Disable backpressure
1: Enable backpressure
5
Port 1 Current Duplex (CUR_DUP_1)
This bit indicates the actual duplex setting of switch Port 1.
0: Full-Duplex
1: Half-Duplex
4
Port 1 Current Receive Flow Control Enable (CUR_RX_FC_1)
This bit indicates the actual receive flow setting of switch Port 1.
0: Flow control receive is currently disabled
1: Flow control receive is currently enabled
3
Port 1 Current Transmit Flow Control Enable (CUR_TX_FC_1)
This bit indicates the actual transmit flow setting of switch Port 1.
0: Flow control transmit is currently disabled
1: Flow control transmit is currently enabled
2
Port 1 Full-Duplex Receive Flow Control Enable (RX_FC_1)
When the MANUAL_FC_1 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables the detection of full-duplex Pause packets on switch Port 1.
0: Disable flow control receive
1: Enable flow control receive
1
Port 1 Full-Duplex Transmit Flow Control Enable (TX_FC_1)
When the MANUAL_FC_1 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables full-duplex Pause packets to be generated on switch Port 1.
0: Disable flow control transmit
1: Enable flow control transmit
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LAN9313/LAN9313i
Bits
Description
Type
Default
0
Port 1 Full-Duplex Manual Flow Control Select (MANUAL_FC_1)
This bit toggles flow control selection between manual and auto-negotiation.
R/W
Note 13-7
0: If auto-negotiation is enabled, the auto-negotiation function
determines the flow control of switch Port 1 (RX_FC_1 and TX_FC_1
values ignored). If auto-negotiation is disabled, the RX_FC_1 and
TX_FC_1 values are used.
1: TX_FC_1 and RX_FC_1 bits determine the flow control of switch Port
1 when in full-duplex mode
Note 13-4
The default value of this field is determined by the BP_EN_strap_1 configuration strap. The strap
values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the values, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-5
The default value of this bit is determined by multiple strap settings. The strap values are loaded
during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the
values, this register is updated with the new values. Refer to Section 6.2.3, "Flow Control Enable
Logic," on page 47 for additional information.
Note 13-6
The default value of this field is determined by the FD_FC_strap_1 configuration strap. The strap
values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the values, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-7
The default value of this field is determined by the manual_FC_strap_1 configuration strap. The strap
values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the values, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
13.1.5.2
Port 2 Manual Flow Control Register (MANUAL_FC_2)
Offset:
1A4h
Size:
32 bits
This read/write register allows for the manual configuration of the switch Port 2 flow control. This register also provides
read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer to Section
6.2.3, "Flow Control Enable Logic," on page 47 for additional information.
Note:
The flow control values in the PHY_AN_ADV_2 register (see Section 13.2.2.5, on page 180) within the
PHY are not affected by the values of this register.
Bits
31:7
6
Description
Type
Default
RESERVED
RO
-
Port 2 Backpressure Enable (BP_EN_2)
This bit enables/disables the generation of half-duplex backpressure on
switch Port 2.
R/W
Note 13-8
RO
Note 13-9
RO
Note 13-9
0: Disable backpressure
1: Enable backpressure
5
Port 2 Current Duplex (CUR_DUP_2)
This bit indicates the actual duplex setting of switch Port 2.
0: Full-Duplex
1: Half-Duplex
4
Port 2 Current Receive Flow Control Enable (CUR_RX_FC_2)
This bit indicates the actual receive flow setting of switch Port 2.
0: Flow control receive is currently disabled
1: Flow control receive is currently enabled
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Bits
3
Description
Port 2 Current Transmit Flow Control Enable (CUR_TX_FC_2)
This bit indicates the actual transmit flow setting of switch Port 2.
Type
Default
RO
Note 13-9
R/W
Note 13-10
R/W
Note 13-10
R/W
Note 13-11
0: Flow control transmit is currently disabled
1: Flow control transmit is currently enabled
2
Port 2 Full-Duplex Receive Flow Control Enable (RX_FC_2)
When the MANUAL_FC_2 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables the detection of full-duplex Pause packets on switch Port 2.
0: Disable flow control receive
1: Enable flow control receive
1
Port 2 Full-Duplex Transmit Flow Control Enable (TX_FC_2)
When the MANUAL_FC_2 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables full-duplex Pause packets to be generated on switch Port 2.
0: Disable flow control transmit
1: Enable flow control transmit
0
Port 2 Full-Duplex Manual Flow Control Select (MANUAL_FC_2)
This bit toggles flow control selection between manual and auto-negotiation.
0: If auto-negotiation is enabled, the auto-negotiation function
determines the flow control of switch Port 2 (RX_FC_2 and TX_FC_2
values ignored). If auto-negotiation is disabled, the RX_FC_2 and
TX_FC_2 values are used.
1: TX_FC_2 and RX_FC_2 bits determine the flow control of switch Port
2 when in full-duplex mode
Note 13-8
The default value of this field is determined by the BP_EN_strap_2 configuration strap. The strap
values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the values, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-9
The default value of this bit is determined by multiple strap settings. The strap values are loaded
during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the
values, this register is updated with the new values. Refer to Section 6.2.3, "Flow Control Enable
Logic," on page 47 for additional information.
Note 13-10 The default value of this field is determined by the FD_FC_strap_2 configuration strap. The strap
values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the values, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-11
The default value of this field is determined by the manual_FC_strap_2 configuration strap. The strap
values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the values, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
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LAN9313/LAN9313i
13.1.5.3
Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII)
Offset:
1A8h
Size:
32 bits
This read/write register allows for the manual configuration of the switch Port 0(External MII) flow control. This register
also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer
to Section 6.2.3, "Flow Control Enable Logic," on page 47 for additional information.
Note:
The flow control values in the Section 13.1.7.5, "Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV)," on page 166 are not affected by the values of this register.
Bits
31:7
6
Description
Type
Default
RESERVED
RO
-
Port 0 Backpressure Enable (BP_EN_MII)
This bit enables/disables the generation of half-duplex backpressure on
switch Port 0.
R/W
Note 13-12
RO
Note 13-13
RO
Note 13-13
RO
Note 13-13
R/W
Note 13-14
R/W
Note 13-14
0: Disable backpressure
1: Enable backpressure
5
Port 0 Current Duplex (CUR_DUP_MII)
This bit indicates the actual duplex setting of the switch Port 0.
0: Full-Duplex
1: Half-Duplex
4
Port 0 Current Receive Flow Control Enable (CUR_RX_FC_MII)
This bit indicates the actual receive flow setting of switch Port 0
0: Flow control receive is currently disabled
1: Flow control receive is currently enabled
3
Port 0 Current Transmit Flow Control Enable (CUR_TX_FC_MII)
This bit indicates the actual transmit flow setting of switch Port 0.
0: Flow control transmit is currently disabled
1: Flow control transmit is currently enabled
2
Port 0 Receive Flow Control Enable (RX_FC_MII)
When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is disabled,
this bit enables/disables the detection of full-duplex Pause packets on switch
Port 0.
0: Disable flow control receive
1: Enable flow control receive
1
Port 0 Transmit Flow Control Enable (TX_FC_MII)
When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is disabled,
this bit enables/disables full-duplex Pause packets to be generated on switch
Port 0.
0: Disable flow control transmit
1: Enable flow control transmit
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Bits
Description
Type
Default
0
Port 0 Full-Duplex Manual Flow Control Select (MANUAL_FC_MII)
This bit toggles flow control selection between manual and auto-negotiation.
R/W
Note 13-16
Note 13-15
0: If auto-negotiation is enabled, the auto-negotiation function
determines the flow control of switch Port 0 (RX_FC_MII and TX_FC_MII
values ignored). If auto-negotiation is disabled, the RX_FC_MII and
TX_FC_MII values are used.
1: TX_FC_MII and RX_FC_MII bits determine the flow control of switch
Port 0 when in full-duplex mode
Note:
In MAC mode, this bit is forced high. The Virtual PHY is not
applicable in this mode and full-duplex flow control should be
controlled manually by the host based on the external PHYs AutoNegotiation results.
Note 13-12 The default value of this field is determined by the BP_EN_strap_mii configuration strap. The strap
value is loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the value, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-13 The default value of this bit is determined by multiple strap settings. The strap values are loaded
during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the
values, this register is updated with the new values. Refer to Section 6.2.3, "Flow Control Enable
Logic," on page 47 for additional information.
Note 13-14 The default value of this field is determined by the FD_FC_strap_mii configuration strap. The strap
value is loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the value, this register is updated with the new values. See Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-15 This bit is RO when in MAC mode.
Note 13-16 The default value of this field is determined by the manual_FC_strap_mii configuration strap. The
strap value is loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM
Loader re-writes the value, this register is updated with the new values. In MAC mode, this bit is not
re-written by the EEPROM Loader and has a default value of “1”. See Section 4.2.4, "Configuration
Straps," on page 33 for more information.
13.1.5.4
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)
Offset:
1ACh
Size:
32 bits
This read/write register is used in conjunction with the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) to perform read and write operations with the Switch Fabric CSR’s. Refer to Section 13.3, "Switch Fabric Control and Status Registers," on page 189 for details on the registers indirectly accessible via this register.
Bits
Description
Type
Default
31:0
Switch CSR Data (CSR_DATA)
This field contains the value read from or written to the Switch Fabric CSR.
The Switch Fabric CSR is selected via the CSR Address (CSR_ADDR[15:0])
bits of the Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD).
R/W
00000000h
Upon a read, the value returned depends on the R/nW bit in the Switch
Fabric CSR Interface Command Register (SWITCH_CSR_CMD). If R/nW is
set, the data is from the switch fabric. If R/nW is cleared, the data is the
value that was last written into this register.
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LAN9313/LAN9313i
13.1.5.5
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
Offset:
1B0h
Size:
32 bits
This read/write register is used in conjunction with the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) to control the read and write operations to the various Switch Fabric CSR’s. Refer to Section 13.3, "Switch Fabric
Control and Status Registers," on page 189 for details on the registers indirectly accessible via this register.
Bits
Description
Type
Default
31
CSR Busy (CSR_BUSY)
When a 1 is written to this bit, the read or write operation (as determined by
the R_nW bit) is performed to the specified Switch Fabric CSR in CSR
Address (CSR_ADDR[15:0]). This bit will remain set until the operation is
complete, at which time the bit will clear. In the case of a read, the clearing
of this bit indicates to the Host that valid data can be read from the Switch
Fabric CSR Interface Data Register (SWITCH_CSR_DATA). The
SWITCH_CSR_CMD and SWITCH_CSR_DATA registers should not be
modified until this bit is cleared.
R/W
SC
0b
30
Read/Write (R_nW)
This bit determines whether a read or write operation is performed by the
Host to the specified Switch Engine CSR.
R/W
0b
R/W
0b
R/W
0b
RO
-
0: Write
1: Read
29
Auto Increment (AUTO_INC)
This bit enables/disables the auto increment feature.
When this bit is set, a write to the Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA) register will automatically set the CSR Busy
(CSR_BUSY) bit. Once the write command is finished, the CSR Address
(CSR_ADDR[15:0]) will automatically increment.
When this bit is set, a read from the Switch Fabric CSR Interface Data
Register (SWITCH_CSR_DATA) will automatically increment the CSR
Address (CSR_ADDR[15:0]) and set the CSR Busy (CSR_BUSY) bit. This
bit should be cleared by software before the last read from the
SWITCH_CSR_DATA register.
0: Disable Auto Increment
1: Enable Auto Increment
Note:
28
This bit has precedence over the Auto Decrement (AUTO_DEC) bit
Auto Decrement (AUTO_DEC)
This bit enables/disables the auto decrement feature.
When this bit is set, a write to the Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA) will automatically set the CSR Busy (CSR_BUSY)
bit. Once the write command is finished, the CSR Address
(CSR_ADDR[15:0]) will automatically decrement.
When this bit is set, a read from the Switch Fabric CSR Interface Data
Register (SWITCH_CSR_DATA) will automatically decrement the CSR
Address (CSR_ADDR[15:0]) and set the CSR Busy (CSR_BUSY) bit. This
bit should be cleared by software before the last read from the
SWITCH_CSR_DATA register.
0: Disable Auto Decrement
1: Enable Auto Decrement
27:20
RESERVED
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Bits
Description
Type
Default
19:16
CSR Byte Enable (CSR_BE[3:0])
This field is a 4-bit byte enable used for selection of valid bytes during write
operations. Bytes which are not selected will not be written to the
corresponding Switch Engine CSR.
R/W
0h
R/W
00h
CSR_BE[3]
CSR_BE[2]
CSR_BE[1]
CSR_BE[0]
corresponds
corresponds
corresponds
corresponds
to
to
to
to
register
register
register
register
data
data
data
data
bits
bits
bits
bits
[31:24]
[23:16]
[15:8]
[7:0]
Typically all four byte enables should be set for auto increment and auto
decrement operations.
15:0
13.1.5.6
CSR Address (CSR_ADDR[15:0])
This field selects the 16-bit address of the Switch Fabric CSR that will be
accessed with a read or write operation. Refer to Table 13-12, “Indirectly
Accessible Switch Control and Status Registers,” on page 189 for a list of
Switch Fabric CSR addresses.
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)
Offset:
1F0h
Size:
32 bits
This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This register is used
in conjunction with Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL). The contents of this register
are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is
detected. The least significant byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM. The second
byte (bits [15:8]) is loaded from address 06h of the EEPROM. The Host can update the contents of this field after the
initialization process has completed.
Refer to Section 13.1.5.7, "Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)" for information on how
this address is loaded by the EEPROM Loader. Section 8.2.4, "EEPROM Loader," on page 93 contains additional
details on using the EEPROM Loader.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:0
Physical Address[47:32]
This field contains the upper 16-bits (47:32) of the physical address of the
Switch Fabric MACs.
R/W
FFFFh
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LAN9313/LAN9313i
13.1.5.7
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
Offset:
1F4h
Size:
32 bits
This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This register is used
in conjunction with Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH). The contents of this register
are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is
detected. The least significant byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most
significant byte (bits [31:24]) is loaded from address 04h of the EEPROM. The Host can update the contents of this field
after the initialization process has completed.
Refer to Section 8.2.4, "EEPROM Loader," on page 93 for information on using the EEPROM Loader.
Bits
31:0
Description
Physical Address[31:0]
This field contains the lower 32-bits (31:0) of the physical address of the
Switch Fabric MACs.
Type
Default
R/W
FF0F8000h
Table 13-2 illustrates the byte ordering of the SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH registers with
respect to the reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and the SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH registers.
TABLE 13-2:
SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, AND EEPROM BYTE ORDERING
EEPROM Address
Register Location Written
Order of Reception on Ethernet
01h
SWITCH_MAC_ADDRL[7:0]
1st
02h
SWITCH_MAC_ADDRL[15:8]
2nd
03h
SWITCH_MAC_ADDRL[23:16]
3rd
04h
SWITCH_MAC_ADDRL[31:24]
4th
05h
SWITCH_MAC_ADDRH[7:0]
5th
06h
SWITCH_MAC_ADDRH[15:8]
6th
For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the SWITCH_MAC_ADDRL and
SWITCH_MAC_ADDRH registers would be programmed as shown in Figure 13-2. The values required to automatically
load this configuration from the EEPROM are also shown.
FIGURE 13-2:
EXAMPLE SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, AND EEPROM
SETUP
31
24 23
xx
16 15
xx
87
BCh
0
9Ah
SWITCH_MAC_ADDRH
31
24 23
78h
16 15
56h
87
34h
SWITCH_MAC_ADDRL
Note:
0
12h
06h
BCh
05h
9Ah
04h
78h
03h
56h
02h
34h
01h
12h
00h
A5h
EEPROM
By convention, the right nibble of the left most byte of the Ethernet address (in this example, the 2 of the
12h) is the most significant nibble and is transmitted/received first.
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13.1.5.8
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
Offset:
200h - 2DCh
Size:
32 bits
This write-only register set is used to perform directly addressed write operations to the Switch Fabric CSR’s. Using this
set of registers, writes can be directly addressed to select Switch Fabric registers, as specified in Table 13-3.
Writes within the Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range
automatically set the appropriate address, set the four byte enable bits, clear the R/nW bit and set the Busy bit in the
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD). The completion of the write cycle is indicated
when the Busy bit is cleared. The address that is set in the Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD) is mapped via Table 13-3. For more information on this method of writing to the Switch Fabric
CSR’s, refer to Section 6.2.3, "Flow Control Enable Logic," on page 47.
Bits
Description
Type
Default
31:0
Switch CSR Data (CSR_DATA)
This field contains the value to be written to the corresponding Switch Fabric
register.
WO
00000000h
Note:
This set of registers is for write operations only. Reads can be performed via the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) and Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA) registers only.
TABLE 13-3:
SWITCH FABRIC CSR TO SWITCH_CSR_DIRECT_DATA ADDRESS RANGE MAP
Register Name
Switch Fabric CSR
Register #
SWITCH_CSR_DIRECT_DATA
Address
General Switch CSRs
SW_RESET
0001h
200h
SW_IMR
0004h
204h
Switch Port 0 CSRs
MAC_RX_CFG_MII
0401h
208h
MAC_TX_CFG_MII
0440h
20Ch
MAC_TX_FC_SETTINGS_MII
0441h
210h
MAC_IMR_MII
0480h
214h
Switch Port 1 CSRs
MAC_RX_CFG_1
0801h
218h
MAC_TX_CFG_1
0840h
21Ch
MAC_TX_FC_SETTINGS_1
0841h
220h
0880h
224h
MAC_IMR_1
Switch Port 2 CSRs
MAC_RX_CFG_2
0C01h
228h
MAC_TX_CFG_2
0C40h
22Ch
MAC_TX_FC_SETTINGS_2
0C41h
230h
MAC_IMR_2
0C80h
234h
Switch Engine CSRs
SWE_ALR_CMD
1800h
238h
SWE_ALR_WR_DAT_0
1801h
23Ch
SWE_ALR_WR_DAT_1
1802h
240h
SWE_ALR_CFG
1809h
244h
SWE_VLAN_CMD
180Bh
248h
SWE_VLAN_WR_DATA
180Ch
24Ch
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LAN9313/LAN9313i
TABLE 13-3:
SWITCH FABRIC CSR TO SWITCH_CSR_DIRECT_DATA ADDRESS RANGE MAP
Switch Fabric CSR
Register #
SWITCH_CSR_DIRECT_DATA
Address
SWE_DIFFSERV_TBL_CMD
1811h
250h
SWE_DIFFSERV_TBL_WR_DATA
1812h
254h
Register Name
SWE_GLB_INGRESS_CFG
1840h
258h
SWE_PORT_INGRESS_CFG
1841h
25Ch
SWE_ADMT_ONLY_VLAN
1842h
260h
SWE_PORT_STATE
1843h
264h
SWE_PRI_TO_QUE
1845h
268h
26Ch
SWE_PORT_MIRROR
1846h
SWE_INGRESS_PORT_TYP
1847h
270h
SWE_BCST_THROT
1848h
274h
SWE_ADMT_N_MEMBER
1849h
278h
SWE_INGRESS_RATE_CFG
184Ah
27Ch
SWE_INGRESS_RATE_CMD
184Bh
280h
SWE_INGRESS_RATE_WR_DATA
184Dh
284h
SWE_INGRESS_REGEN_TBL_MII
1855h
288h
SWE_INGRESS_REGEN_TBL_1
1856h
28Ch
SWE_INGRESS_REGEN_TBL_2
1857h
290h
1880h
294h
SWE_IMR
Buffer Manager (BM) CSRs
BM_CFG
1C00h
298h
BM_DROP_LVL
1C01h
29Ch
BM_FC_PAUSE_LVL
1C02h
2A0h
BM_FC_RESUME_LVL
1C03h
2A4h
BM_BCST_LVL
1C04h
2A8h
BM_RNDM_DSCRD_TBL_CMD
1C09h
2ACh
BM_RNDM_DSCRD_TBL_WDATA
1C0Ah
2B0h
BM_EGRSS_PORT_TYPE
1C0Ch
2B4h
BM_EGRSS_RATE_00_01
1C0Dh
2B8h
BM_EGRSS_RATE_02_03
1C0Eh
2BCh
BM_EGRSS_RATE_10_11
1C0Fh
2C0h
BM_EGRSS_RATE_12_13
1C10h
2C4h
BM_EGRSS_RATE_20_21
1C11h
2C8h
BM_EGRSS_RATE_22_23
1C12h
2CCh
BM_VLAN_MII
1C13h
2D0h
BM_VLAN_1
1C14h
2D4h
BM_VLAN_2
1C15h
2D8h
BM_IMR
1C20h
2DCh
13.1.6
PHY MANAGEMENT INTERFACE (PMI)
The PMI registers are used to indirectly access the PHY registers. Refer to Section 13.2, "Ethernet PHY Control and
Status Registers," on page 175 for additional information on the PHY registers. Refer to Section 9.3, "PHY Management
Interface (PMI)," on page 106 for information on the PMI.
Note:
The Virtual PHY registers are NOT accessible via these registers.
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13.1.6.1
PHY Management Interface Data Register (PMI_DATA)
Offset:
0A4h
Size:
32 bits
This register is used in conjunction with the PHY Management Interface Access Register (PMI_ACCESS) to perform
read and write operations to the PHYs.
Note:
The Virtual PHY registers are NOT accessible via these registers.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:0
MII Data
This field contains the value read from or written to the PHYs. For a write
operation, this register should be first written with the desired data. For a
read operation, the PMI_ACCESS register is first written and once the
command is finished, this register will contain the return data.
R/W
00000000h
Note:
13.1.6.2
Upon a read, the value returned depends on the MII Write bit
(MIIWnR) in the PHY Management Interface Access Register
(PMI_ACCESS). If MIIWnR is 0, the data is from the PHY. If
MIIWnR is 1, the data is the value that was last written into this
register.
PHY Management Interface Access Register (PMI_ACCESS)
Offset:
0A8h
Size:
32 bits
This register is used to control the management cycles to the PHYs. A PHY access is initiated when this register is written. This register is used in conjunction with the PHY Management Interface Data Register (PMI_DATA) to perform read
and write operations to the PHYs.
Note:
The Virtual PHY registers are NOT accessible via these registers.
Type
Default
31:16
Bits
RESERVED
RO
-
15:11
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to Section 7.1.1,
"PHY Addressing," on page 68 for information on PHY address assignments.
R/W
00000b
10:6
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to Section 13.2,
"Ethernet PHY Control and Status Registers," on page 175 for detailed
descriptions on all PHY registers.
R/W
00000b
5:2
RESERVED
RO
-
MII Write (MIIWnR)
Setting this bit informs the PHY that the access will be a write operation
using the PHY Management Interface Data Register (PMI_DATA). If this bit
is cleared, the access will be a read operation, returning data into the PHY
Management Interface Data Register (PMI_DATA).
R/W
0b
1
Description
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LAN9313/LAN9313i
Bits
Description
Type
Default
0
MII Busy (MIIBZY)
This bit must be read as 0 before writing to the PHY Management Interface
Data Register (PMI_DATA) or PHY Management Interface Access Register
(PMI_ACCESS) registers. This bit is automatically set when this register is
written. During a PHY register access, this bit will be set, signifying a read
or write access is in progress. This is a self-clearing (SC) bit that will return
to 0 when the PHY register access has completed.
RO
SC
0b
During a PHY register write, the PHY Management Interface Data Register
(PMI_DATA) must be kept valid until this bit is cleared.
During a PHY register read, the PHY Management Interface Data Register
(PMI_DATA) register is invalid until the MAC has cleared this bit.
13.1.7
VIRTUAL PHY
This section details the Virtual PHY System CSR’s. These registers provide status and control information similar to that
of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY registers are addressable via the memory
map, as described in Table 13-1, as well as serially via the MII management protocol (IEEE 802.3 clause 22). When
accessed serially, these registers are accessed through the MII management pins (in PHY modes only) via the MII serial
management protocol specified in IEEE 802.3 clause 22. See Section 2.3, "Modes of Operation," on page 12 for a
detailed description of the various LAN9313/LAN9313i modes. When being accessed serially, the Virtual PHY will
respond when the PHY address equals the address assigned by the phy_addr_sel_strap configuration strap, as defined
in Section 7.1.1, "PHY Addressing," on page 68. A list of all Virtual PHY register indexes for serial access can be seen
in Table 13-4. For more information on the Virtual PHY access modes, refer to section Section 13.2. For Virtual PHY
functionality and operation information, see Section 7.3, "Virtual PHY," on page 79.
Note:
• All Virtual PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is
included under the LAN9313/LAN9313i memory mapped offset of each Virtual PHY register as a reference. For
additional information, refer to the IEEE 802.3 Specification.
• When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII management of
PHY’s.
TABLE 13-4:
VIRTUAL PHY MII SERIALLY ADRESSABLE REGISTER INDEX
Index #
Symbol
0
VPHY_BASIC_CTRL
1
VPHY_BASIC_STATUS
2
VPHY_ID_MSB
Virtual PHY Identification MSB Register, Section 13.1.7.3
3
VPHY_ID_LSB
Virtual PHY Identification LSB Register, Section 13.1.7.4
4
VPHY_AN_ADV
Virtual PHY Auto-Negotiation Advertisement Register,
Section 13.1.7.5
5
VPHY_AN_LP_BASE_ABILITY
6
VPHY_AN_EXP
31
VPHY_SPEC_CTRL_STATUS
2008-2016 Microchip Technology Inc.
Register Name
Virtual PHY Basic Control Register, Section 13.1.7.1
Virtual PHY Basic Status Register, Section 13.1.7.2
Virtual PHY Auto-Negotiation Link Partner Base Page Ability
Register, Section 13.1.7.6
Virtual PHY Auto-Negotiation Expansion Register,
Section 13.1.7.7
Virtual PHY Special Control/Status Register, Section 13.1.7.8
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LAN9313/LAN9313i
13.1.7.1
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
Offset:
Index (decimal):
1C0h
0
Size:
32 bits
This read/write register is used to configure the Virtual PHY.
Note:
This register is re-written in its entirety by the EEPROM Loader following the release or reset or a RELOAD
command. Refer to Section 8.2.4, "EEPROM Loader," on page 93 for more information.
Bits
31:16
15
Description
Type
Default
RESERVED
(See Note 13-17)
RO
-
Reset (VPHY_RST)
When set, this bit resets all the Virtual PHY registers to their default state.
This bit is self clearing.
R/W
SC
0b
R/W
0b
R/W
0b
R/W
1b
0: Normal Operation
1: Reset
14
Loopback (VPHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
from the external MAC are not sent to the switch fabric. Instead, they are
looped back onto the receive path.
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
13
Speed Select LSB (VPHY_SPEED_SEL_LSB)
This bit is used to set the speed of the Virtual PHY when the AutoNegotiation (VPHY_AN) bit is disabled.
0: 10 Mbps
1: 100 Mbps
12
Auto-Negotiation (VPHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the Speed Select
LSB (VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bits
are overridden.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
11
Power Down (VPHY_PWR_DWN)
This bit is not used by the Virtual PHY and has no effect.
R/W
0b
10
Isolate (VPHY_ISO)
This bit controls the MII input/output pins. When set and in PHY mode, the
MII output pins are not driven, MII pull-ups and pull-downs are disabled and
the input pins are ignored. When in MAC mode, this bit is ignored and has
no effect. (Note 13-18)
R/W
0b
R/W
SC
0b
R/W
0b
0: Non-Isolated (Normal operation)
1: Isolated
9
Restart Auto-Negotiation (VPHY_RST_AN)
When set, this bit updates the emulated Auto-Negotiation results.
0: Normal operation
1: Auto-Negotiation restarted
8
Duplex Mode (VPHY_DUPLEX)
This bit is used to set the duplex when the Auto-Negotiation (VPHY_AN) bit
is disabled.
0: Half Duplex
1: Full Duplex
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LAN9313/LAN9313i
Bits
7
Description
Type
Default
R/W
0b
Speed Select MSB (VPHY_SPEED_SEL_MSB)
This bit is not used by the Virtual PHY and has no effect. The value returned
is always 0.
RO
0b
RESERVED
RO
-
Collision Test (VPHY_COL_TEST)
This bit enables/disables the collision test mode. When set, the collision
signal to the external MAC is active during transmission from the external
MAC.
It is recommended that this bit be used only when in loopback
mode.
0: Collision test mode disabled
1: Collision test mode enabled
Note:
6
5:0
Note 13-17 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-18 The isolation does not apply to the MII management pins (MDIO).
13.1.7.2
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)
Offset:
Index (decimal):
1C4h
1
Size:
32 bits
This register is used to monitor the status of the Virtual PHY.
Bits
31:16
15
Description
Type
Default
RESERVED
(See Note 13-19)
RO
-
100BASE-T4
This bit displays the status of 100BASE-T4 compatibility.
RO
0b
Note 13-20
RO
1b
RO
1b
RO
1b
RO
1b
RO
0b
Note 13-20
0: PHY not able to perform 100BASE-T4
1: PHY able to perform 100BASE-T4
14
100BASE-X Full Duplex
This bit displays the status of 100BASE-X full duplex compatibility.
0: PHY not able to perform 100BASE-X full duplex
1: PHY able to perform 100BASE-X full duplex
13
100BASE-X Half Duplex
This bit displays the status of 100BASE-X half duplex compatibility.
0: PHY not able to perform 100BASE-X half duplex
1: PHY able to perform 100BASE-X half duplex
12
10BASE-T Full Duplex
This bit displays the status of 10BASE-T full duplex compatibility.
0: PHY not able to perform 10BASE-T full duplex
1: PHY able to perform 10BASE-T full duplex
11
10BASE-T Half Duplex
This bit displays the status of 10BASE-T half duplex compatibility.
0: PHY not able to perform 10BASE-T half duplex
1: PHY able to perform 10BASE-T half duplex
10
100BASE-T2 Full Duplex
This bit displays the status of 100BASE-T2 full duplex compatibility.
0: PHY not able to perform 100BASE-T2 full duplex
1: PHY able to perform 100BASE-T2 full duplex
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LAN9313/LAN9313i
Bits
9
Description
100BASE-T2 Half Duplex
This bit displays the status of 100BASE-T2 half duplex compatibility.
Type
Default
RO
0b
Note 13-20
RO
0b
Note 13-21
0: PHY not able to perform 100BASE-T2 half duplex
1: PHY able to perform 100BASE-T2 half duplex
8
Extended Status
This bit displays whether extended status information is in register 15 (per
IEEE 802.3 clause 22.2.4).
0: No extended status information in Register 15
1: Extended status information in Register 15
7
RESERVED
RO
-
6
MF Preamble Suppression
This bit indicates whether the Virtual PHY accepts management frames with
the preamble suppressed.
RO
0b
RO
1b
Note 13-22
RO
0b
Note 13-23
RO
1b
RO
1b
Note 13-23
RO
0b
Note 13-23
RO
1b
Note 13-24
0: Management frames with preamble suppressed not accepted
1: Management frames with preamble suppressed accepted
5
Auto-Negotiation Complete
This bit indicates the status of the Auto-Negotiation process.
0: Auto-Negotiation process not completed
1: Auto-Negotiation process completed
4
Remote Fault
This bit indicates if a remote fault condition has been detected.
0: No remote fault condition detected
1: Remote fault condition detected
3
Auto-Negotiation Ability
This bit indicates the status of the Virtual PHY’s auto-negotiation.
0: Virtual PHY is unable to perform auto-negotiation
1: Virtual PHY is able to perform auto-negotiation
2
Link Status
This bit indicates the status of the link.
0: Link is down
1: Link is up
1
Jabber Detect
This bit indicates the status of the jabber condition.
0: No jabber condition detected
1: Jabber condition detected
0
Extended Capability
This bit indicates whether extended register capability is supported.
0: Basic register set capabilities only
1: Extended register set capabilities
Note 13-19 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-20 The Virtual PHY supports 100BASE-X (half and full duplex) and 10BASE-T (half and full duplex) only.
All other modes will always return as 0 (unable to perform).
Note 13-21 The Virtual PHY does not support Register 15 or 1000 Mb/s operation. Thus this bit is always
returned as 0.
Note 13-22 The Auto-Negotiation Complete bit is first cleared on a reset, but set shortly after (when the AutoNegotiation process is run). Refer to Section 7.3.1, "Virtual PHY Auto-Negotiation," on page 79 for
additional details.
Note 13-23 The Virtual PHY never has remote faults, its link is always up, and does not detect jabber.
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LAN9313/LAN9313i
Note 13-24 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY supports
Registers 0-6 (per the IEEE 802.3 specification).
13.1.7.3
Virtual PHY Identification MSB Register (VPHY_ID_MSB)
Offset:
Index (decimal):
1C8h
2
Size:
32 bits
This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI). The LSB of the
Virtual PHY OUI is contained in the Virtual PHY Identification LSB Register (VPHY_ID_LSB).
Bits
Description
Type
Default
31:16
RESERVED
(See Note 13-25)
RO
-
15:0
PHY ID
This field contains the MSB of the Virtual PHY OUI (Note 13-26).
R/W
0000h
Note 13-25 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-26 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
13.1.7.4
Virtual PHY Identification LSB Register (VPHY_ID_LSB)
Offset:
Index (decimal):
1CCh
3
Size:
32 bits
This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI). The MSB of the
Virtual PHY OUI is contained in the Virtual PHY Identification MSB Register (VPHY_ID_MSB).
Bits
Description
Type
Default
31:16
RESERVED
(See Note 13-27)
RO
-
15:10
PHY ID
This field contains the lower 6-bits of the Virtual PHY OUI (Note 13-28).
R/W
000000b
9:4
Model Number
This field contains the 6-bit manufacturer’s model number of the Virtual PHY
(Note 13-28).
R/W
000000b
3:0
Revision Number
This field contain the 4-bit manufacturer’s revision number of the Virtual PHY
(Note 13-28).
R/W
0000b
Note 13-27 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-28 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
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LAN9313/LAN9313i
13.1.7.5
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)
Offset:
Index (decimal):
1D0h
4
Size:
32 bits
This read/write register contains the advertised ability of the Virtual PHY and is used in the Auto-Negotiation process
with the link partner.
Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset
or a RELOAD command. Refer to Section 8.2.4, "EEPROM Loader," on page 93 for more
information.
Bits
31:16
15
Description
Type
Default
RESERVED
(See Note 13-29)
RO
-
Next Page
This bit determines the advertised next page capability and is always 0.
RO
0b
Note 13-30
0: Virtual PHY does not advertise next page capability
1: Virtual PHY advertises next page capability
RESERVED
RO
-
13
Remote Fault
This bit is not used since there is no physical link partner.
RO
0b
Note 13-31
12
RESERVED
RO
-
11
Asymmetric Pause
This bit determines the advertised asymmetric pause capability.
R/W
0b
R/W
Note 13-32
RO
0b
Note 13-33
R/W
1b
R/W
1b
R/W
1b
14
0: No Asymmetric PAUSE toward link partner advertised
1: Asymmetric PAUSE toward link partner advertised
10
Pause
This bit determines the advertised symmetric pause capability.
0: No Symmetric PAUSE toward link partner advertised
1: Symmetric PAUSE toward link partner advertised
9
100BASE-T4
This bit determines the advertised 100BASE-T4 capability and is always 0.
0: 100BASE-T4 ability not advertised
1: 100BASE-T4 ability advertised
8
100BASE-X Full Duplex
This bit determines the advertised 100BASE-X full duplex capability.
0: 100BASE-X full duplex ability not advertised
1: 100BASE-X full duplex ability advertised
7
100BASE-X Half Duplex
This bit determines the advertised 100BASE-X half duplex capability.
0: 100BASE-X half duplex ability not advertised
1: 100BASE-X half duplex ability advertised
6
10BASE-T Full Duplex
This bit determines the advertised 10BASE-T full duplex capability.
0: 10BASE-T full duplex ability not advertised
1: 10BASE-T full duplex ability advertised
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LAN9313/LAN9313i
Bits
5
Description
10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
Type
Default
R/W
1b
R/W
00001b
Note 13-34
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
4:0
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13-29 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-30 The Virtual PHY does not support next page capability. This bit value will always be 0.
Note 13-31 The Remote Fault bit is not useful since there is no actual link partner to send a fault to.
Note 13-32 The Pause bit defaults to 1 if the manual_FC_strap_mii strap is low, and 0 if the
manual_FC_strap_mii strap is high. Configuration strap values are latched upon the de-assertion of
a chip-level reset as described in Section 4.2.4, "Configuration Straps," on page 33.
Note 13-33 Virtual 100BASE-T4 is not supported.
Note 13-34 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this field.
13.1.7.6
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY)
Offset:
Index (decimal):
1D4h
5
Size:
32 bits
This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-Negotiation process with the Virtual PHY. Because the Virtual PHY does not physically connect to an actual link partner, the values in
this register are emulated as described below.
Bits
31:16
15
Description
Type
Default
RESERVED
(See Note 13-35)
RO
-
Next Page
This bit indicates the emulated link partner PHY next page capability and is
always 0.
RO
0b
Note 13-36
RO
1b
Note 13-36
0b
Note 13-36
0: Link partner PHY does not advertise next page capability
1: Link partner PHY advertises next page capability
14
Acknowledge
This bit indicates whether the link code word has been received from the
partner and is always 1.
0: Link code word not yet received from partner
1: Link code word received from partner
13
Remote Fault
Since there is no physical link partner, this bit is not used and is always
returned as 0.
RO
12
RESERVED
RO
-
11
Asymmetric Pause
This bit indicates the emulated link partner PHY asymmetric pause capability.
RO
Note 13-37
0: No Asymmetric PAUSE toward link partner
1: Asymmetric PAUSE toward link partner
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Bits
Description
Type
Default
10
Pause
This bit indicates the emulated link partner PHY symmetric pause capability.
RO
Note 13-37
RO
0b
Note 13-36
RO
Note 13-38
RO
Note 13-38
RO
Note 13-38
RO
Note 13-38
RO
00001b
0: No Symmetric PAUSE toward link partner
1: Symmetric PAUSE toward link partner
9
100BASE-T4
This bit indicates the emulated link partner PHY 100BASE-T4 capability. This
bit is always 0.
0: 100BASE-T4 ability not supported
1: 100BASE-T4 ability supported
8
100BASE-X Full Duplex
This bit indicates the emulated link partner PHY 100BASE-X full duplex
capability.
0: 100BASE-X full duplex ability not supported
1: 100BASE-X full duplex ability supported
7
100BASE-X Half Duplex
This bit indicates the emulated link partner PHY 100BASE-X half duplex
capability.
0: 100BASE-X half duplex ability not supported
1: 100BASE-X half duplex ability supported
6
10BASE-T Full Duplex
This bit indicates the emulated link partner PHY 10BASE-T full duplex
capability.
0: 10BASE-T full duplex ability not supported
1: 10BASE-T full duplex ability supported
5
10BASE-T Half Duplex
This bit indicates the emulated link partner PHY 10BASE-T half duplex
capability.
0: 10BASE-T half duplex ability not supported
1: 10BASE-T half duplex ability supported
4:0
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13-35 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-36 The emulated link partner does not support next page, always instantly sends its link code word,
never sends a fault, and does not support 100BASE-T4.
Note 13-37 The emulated link partner’s asymmetric/symmetric pause ability is based upon the values of the
Asymmetric Pause and Pause bits of the Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV). Thus the emulated link partner always accommodates the request of the Virtual
PHY, as shown in Table 13-5. See Section 7.3.1, "Virtual PHY Auto-Negotiation," on page 79 for
additional information.
TABLE 13-5:
EMULATED LINK PARTNER PAUSE FLOW CONTROL ABILITY DEFAULT VALUES
VPHY Symmetric
Pause
VPHY Asymmetric
Pause
Link Partner
Symmetric Pause
Link Partner
Asymmetric Pause
No Flow Control Enabled
0
0
0
0
Symmetric Pause
1
0
1
0
Asymmetric Pause Towards Switch
0
1
1
1
Asymmetric Pause Towards MAC
1
1
0
1
Note 13-38 The emulated link partner’s ability is based on the MII_DUPLEX pin, duplex_pol_strap_mii, and
speed_strap_mii, as well as on the Auto-Negotiation success. Table 13-6 defines the default
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LAN9313/LAN9313i
capabilities of the emulated link partner as a function of these signals. Configuration strap values are
latched upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration
Straps," on page 33. For more information on the Virtual PHY auto-negotiation, see Section 7.3.1,
"Virtual PHY Auto-Negotiation," on page 79.
TABLE 13-6:
EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY
Advertised Link Partner Ability
(Bits 8,7,6,5)
SPEED_MII
MII_DUPLEX = DUPLEX_POL_MII
MII_DUPLEX != DUPLEX_POL_MII
13.1.7.7
0
10BASE-T Full-Duplex (0010)
1
100BASE-X Full-Duplex (1000)
0
10BASE-T Half-Duplex (0001)
1
100BASE-X Half-Duplex (0100)
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)
Offset:
Index (decimal):
1D8h
6
Size:
32 bits
This register is used in the Auto-Negotiation process.
Bits
Description
Type
Default
31:16
RESERVED
(See Note 13-39)
RO
-
15:5
RESERVED
RO
-
Parallel Detection Fault
This bit indicates whether a Parallel Detection Fault has been detected. This
bit is always 0.
RO
0b
Note 13-40
RO
0b
Note 13-41
RO
0b
Note 13-41
RO/LH
1b
Note 13-42
RO
1b
Note 13-43
4
0: A fault hasn’t been detected via the Parallel Detection function
1: A fault has been detected via the Parallel Detection function
3
Link Partner Next Page Able
This bit indicates whether the link partner has next page ability. This bit is
always 0.
0: Link partner does not contain next page capability
1: Link partner contains next page capability
2
Local Device Next Page Able
This bit indicates whether the local device has next page ability. This bit is
always 0.
0: Local device does not contain next page capability
1: Local device contains next page capability
1
Page Received
This bit indicates the reception of a new page.
0: A new page has not been received
1: A new page has been received
0
Link Partner Auto-Negotiation Able
This bit indicates the Auto-negotiation ability of the link partner.
0: Link partner is not Auto-Negotiation able
1: Link partner is Auto-Negotiation able
Note 13-39 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-40 Since the Virtual PHY link partner is emulated, there is never a Parallel Detection Fault and this bit
is always 0.
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Note 13-41 Next page ability is not supported by the Virtual PHY or emulated link partner.
Note 13-42 The page received bit is clear when read. It is first cleared on reset, but set shortly thereafter when
the Auto-Negotiation process is run.
Note 13-43 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no common
bits between the advertised ability and the link partner ability).
13.1.7.8
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Offset:
Index (decimal):
1DCh
31
Size:
32 bits
This read/write register contains a current link speed/duplex indicator and SQE control.
Bits
Type
Default
RESERVED
(See Note 13-44)
RO
-
15
RESERVED
RO
-
14
Switch Looopback MII
When set, transmissions from the switch fabric Port 0(External MII) are not
sent to the External MII. Instead, they are looped back into the switch engine.
R/W
0b
RESERVED
RO
-
Switch Collision Test MII
When set, the collision signal to the switch fabric Port 0(External MII) is
active during transmission from the switch engine.
R/W
0b
31:16
Description
From the MAC viewpoint, this is effectively a FAR LOOPBACK.
If loopback is enabled during half-duplex operation, then the Enable Receive
Own Transmit bit in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x) must be set for this port. Otherwise, the switch fabric will
ignore receive activity when transmitting in half-duplex mode.
This mode works even if the Isolate bit of the Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL) is set.
13:8
7
It is recommended that this bit be used only when using loopback mode.
6:5
RESERVED
RO
-
4:2
Current Speed/Duplex Indication
This field indicates the current speed and duplex of the Virtual PHY link.
RO
Note 13-45
[4]
[3]
[2]
0
0
0
Speed
Duplex
0
0
1
10Mbps
half-duplex
0
1
0
100Mbps
half-duplex
0
1
1
1
0
0
1
0
1
10Mbps
full-duplex
1
1
0
100Mbps
full-duplex
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
0
SQEOFF
This bit enables/disables the Signal Quality Error (Heartbeat) test.
RO
-
R/W
NASR
Note 13-47
Note 13-46
0: SQE test enabled
1: SQE test disabled
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Note 13-44 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD
boundary. When accessed serially (through the MII management protocol), the register is 16-bits
wide.
Note 13-45 The default value of this field is the result of the Auto-Negotiation process if the Auto-Negotiation
(VPHY_AN) bit of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set. Otherwise,
this field reflects the Speed Select LSB (VPHY_SPEED_SEL_LSB) and Duplex Mode
(VPHY_DUPLEX) bit settings of the VPHY_BASIC_CTRL register. Refer to Section 7.3.1, "Virtual
PHY Auto-Negotiation," on page 79 for information on the Auto-Negotiation determination process of
the Virtual PHY.
Note 13-46 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via the Reset
Control Register (RESET_CTL). The NASR designation is only applicable when the Reset
(VPHY_RST) bit of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set.
Note 13-47 The default value of this field is determined via the SQE_test_disable_strap_mii configuration strap.
Refer to Section 4.2.4, "Configuration Straps," on page 33 for additional information.
13.1.8
MISCELLANEOUS
This section details the remainder of the System CSR’s. These registers allow for monitoring and configuration of various LAN9313/LAN9313i functions such as the Chip ID/revision, byte order testing, hardware configuration, general purpose timer, and free running counter.
13.1.8.1
Chip ID and Revision (ID_REV)
Offset:
050h
Size:
32 bits
This read-only register contains the ID and Revision fields for the LAN9313/LAN9313i.
Bits
Description
Type
Default
31:16
Chip ID
This field indicates the chip ID.
RO
9313h
15:0
Chip Revision
This field indicates the design revision.
RO
Note 13-48
Note 13-48 Default value is dependent on device revision.
13.1.8.2
Byte Order Test Register (BYTE_TEST)
Offset:
064h
Size:
32 bits
This read-only register can be used to determine the byte ordering of the current configuration.
Note:
This register can be read while the LAN9313/LAN9313i is in the not ready state. This register can also be
polled while the device is in the reset state without causing any damaging effects. The returned data will
be invalid since the serial interfaces are also in the reset state at this time. However, the returned data will
not match the normal valid data pattern during reset.
Note:
In SMI mode, either half of this register can be read without the need to read the other half.
Bits
31:0
Description
Byte Test (BYTE_TEST)
This field reflects the current byte ordering
2008-2016 Microchip Technology Inc.
Type
Default
RO
87654321h
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13.1.8.3
Hardware Configuration Register (HW_CFG)
Offset:
074h
Size:
32 bits
This register allows the configuration of various hardware features.
Note:
This register can be polled while the LAN9313/LAN9313i is in the reset or not ready state (READY bit is
cleared). Returned data will be invalid during the reset state since the serial interfaces are also in reset at
this time.
Note:
In SMI mode, either half of this register can be read without the need to read the other half.
Bits
31:28
27
Description
Type
Default
RESERVED
RO
-
Device Ready (READY)
When set, this bit indicates that the LAN9313/LAN9313i is ready to be
accessed. Upon power-up, nRST reset, or digital reset, the host processor
may interrogate this field as an indication that the LAN9313/LAN9313i has
stabilized and is fully active.
RO
0b
This bit can cause an interrupt if enabled.
Note:
With the exception of the HW_CFG, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address are
invalid until this bit is set.
26
AMDIX_EN Strap State Port 2
This bit reflects the state of the auto_mdix_strap_2 strap that connects to the
PHY. The strap value is loaded with the level of the auto_mdix_strap_2
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status
Indication Register (Section 13.2.2.10).
RO
Note 13-49
25
AMDIX_EN Strap State Port 1
This bit reflects the state of the auto_mdix_strap_1 strap that connects to the
PHY. The strap value is loaded with the level of the auto_mdix_strap_1
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status
Indication Register (Section 13.2.2.10).
RO
Note 13-50
RESERVED
RO
-
24:0
Note 13-49 The default value of this field is determined by the configuration strap auto_mdix_strap_2. See
Section 4.2.4, "Configuration Straps," on page 33 for more information.
Note 13-50 The default value of this field is determined by the configuration strap auto_mdix_strap_1. See
Section 4.2.4, "Configuration Straps," on page 33 for more information.
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LAN9313/LAN9313i
13.1.8.4
General Purpose Timer Configuration Register (GPT_CFG)
Offset:
08Ch
Size:
32 bits
This read/write register configures the LAN9313/LAN9313i General Purpose Timer (GPT). The GPT can be configured
to generate host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the
General Purpose Timer Count Register (GPT_CNT). Refer to Section 11.1, "General Purpose Timer," on page 119 for
additional information.
Bits
31:30
29
Description
Type
Default
RESERVED
RO
-
General Purpose Timer Enable (TIMER_EN)
This bit enables the GPT. When set, the GPT enters the run state. When
cleared, the GPT is halted. On the 1 to 0 transition of this bit, the GPT_LOAD
field of this register will be preset to FFFFh.
R/W
0b
0: GPT Disabled
1: GPT Enabled
28:16
RESERVED
RO
-
15:0
General Purpose TImer Pre-Load (GPT_LOAD)
This value is pre-loaded into the GPT. This is the starting value of the GPT.
The timer will begin decrementing from this value when enabled.
R/W
FFFFh
13.1.8.5
General Purpose Timer Count Register (GPT_CNT)
Offset:
090h
Size:
32 bits
This read-only register reflects the current general purpose timer (GPT) value. The register should be used in conjunction with the General Purpose Timer Configuration Register (GPT_CFG) to configure and monitor the GPT. Refer to
Section 11.1, "General Purpose Timer," on page 119 for additional information.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:0
General Purpose Timer Current Count (GPT_CNT)
This 16-bit field represents the current value of the GPT.
RO
FFFFh
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LAN9313/LAN9313i
13.1.8.6
Free Running 25MHz Counter Register (FREE_RUN)
Offset:
09Ch
Size:
32 bits
This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section 11.2, "Free-Running Clock," on page 119 for additional information.
Bits
Description
Type
Default
31:0
Free Running Counter (FR_CNT)
This field reflects the current value of the free-running 32-bit counter. At
reset, the counter starts at zero and is incremented by one every 25MHz
cycle. When the maximum count has been reached, the counter will rollover
to zero and continue counting.
RO
00000000h
Note:
13.1.8.7
The free running counter can take up to 160nS to clear after a reset
event.
Reset Control Register (RESET_CTL)
Offset:
1F8h
Size:
32 bits
This register contains software controlled resets.
Note:
This register can be read while the LAN9313/LAN9313i is in the not ready state. This register can also be
polled while the device is in the reset state without causing any damaging effects. However, the returned
data will be invalid since the serial interfaces are also in the reset state at this time.
Note:
In SMI mode, either half of this register can be read without the need to read the other half.
Bits
31:4
3
Description
Type
Default
RESERVED
RO
-
Virtual PHY Reset (VPHY_RST)
Setting this bit resets the Virtual PHY. When the Virtual PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is set.
R/W
SC
0b
Note:
This bit is not accessible via the EEPROM Loader.
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LAN9313/LAN9313i
Bits
Description
Type
Default
2
Port 2 PHY Reset (PHY2_RST)
Setting this bit resets the Port 2 PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port 2 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
R/W
SC
0b
R/W
SC
0b
R/W
SC
0b
Note:
1
Port 1 PHY Reset (PHY1_RST)
Setting this bit resets the Port 1 PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port 1 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note:
0
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
Digital Reset (DIGITAL_RST)
Setting this bit resets the complete chip except the PLL, Virtual PHY, Port 1
PHY, and Port 2 PHY. The EEPROM Loader will automatically reload the
configuration following this reset, but will not reset the Virtual PHY, Port 1
PHY, or Port 2 PHY. If desired, the above PHY resets can be issued once
the device is configured. All system CSRs are reset except for any NASR
type bits. Any in progress EEPROM commands (including RELOAD) are
terminated.
When the chip is released from reset, this bit is automatically cleared. The
BYTE_TEST register should be polled to determine when the reset is
complete. All writes to this bit are ignored while this bit is set.
Note:
13.2
This bit is not accessible via the EEPROM Loader.
Ethernet PHY Control and Status Registers
This section details the various LAN9313/LAN9313i Ethernet PHY control and status registers. The LAN9313/LAN9313i
contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE 802.3 (clause 22.2.4)
specified MII management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3
specified register index (in decimal) is included with each register definition, allowing for addressing of these registers
via the MII serial management protocol. For additional information on the MII management protocol, refer to the IEEE
802.3 Specification.
Each individual PHY is assigned a unique PHY address as detailed in Section 7.1.1, "PHY Addressing," on page 68.
13.2.1
VIRTUAL PHY REGISTERS
The Virtual PHY provides a basic MII management interface for communication with an standard external MAC as if it
was attached to a single port PHY. The Virtual PHY registers differ from the Port 1 & 2 PHY registers in that they are
addressable via the memory map, as described in Table 13-1, as well as serially. These modes of access are described
in Section 13.1.7, "Virtual PHY," on page 161.
Because the Virtual PHY registers are also memory mapped, their definitions have been included in the System Control
and Status Registers Section 13.1.7, "Virtual PHY," on page 161. A list of the Virtual PHY MII addressable registers and
their corresponding register index numbers is also included in Table 13-4.
Note:
13.2.2
When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII management
of PHY’s.
PORT 1 & 2 PHY REGISTERS
The Port 1 and Port 2 PHY’s are comparable in functionality and have an identical set of non-memory mapped registers.
The Port 1 and Port 2 PHY registers are not memory mapped. These registers are indirectly accessed through the PHY
Management Interface Access Register (PMI_ACCESS) and PHY Management Interface Data Register (PMI_DATA)
registers (in MAC or PHY I2C and SPI managed modes only) or through the MII management pins (in MAC or PHY SMI
managed modes only) via the MII serial management protocol specified in IEEE 802.3 clause 22. See Section 2.3,
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LAN9313/LAN9313i
"Modes of Operation," on page 12 for a details on the various LAN9313/LAN9313i modes. Because the Port 1 & 2 PHY
registers are functionally identical, their register descriptions have been consolidated. A lowercase “x” has been
appended to the end of each PHY register name in this section, where “x” should be replaced with “1” or “2” for the Port
1 PHY or the Port 2 PHY registers respectively. A list of the Port 1 & 2 PHY MII addressable registers and their corresponding register index numbers is included in Table 13-7. Each individual PHY is assigned a unique PHY address as
detailed in Section 7.1.1, "PHY Addressing," on page 68.
TABLE 13-7:
PORT 1 & 2 PHY MII SERIALLY ADRESSABLE REGISTERS
Index #
Symbol
0
PHY_BASIC_CONTROL_x
Port x PHY Basic Control Register, Section 13.2.2.1
1
PHY_BASIC_STATUS_x
Port x PHY Basic Status Register, Section 13.2.2.2
2
PHY_ID_MSB_x
Port x PHY Identification MSB Register, Section 13.2.2.3
3
PHY_ID_LSB_x
Port x PHY Identification LSB Register, Section 13.2.2.4
4
PHY_AN_ADV_x
Port x PHY Auto-Negotiation Advertisement Register,
Section 13.2.2.5
5
PHY_AN_LP_BASE_ABILITY_x
6
PHY_AN_EXP_x
17
PHY_MODE_CONTROL_STATUS_x
Port x PHY Mode Control/Status Register, Section 13.2.2.8
18
PHY_SPECIAL_MODES_x
Port x PHY Special Modes Register, Section 13.2.2.9
27
PHY_SPECIAL_CONTROL_STAT_IND_x
Port x PHY Special Control/Status Indication Register,
Section 13.2.2.10
29
PHY_INTERRUPT_SOURCE_x
Port x PHY Interrupt Source Flags Register, Section 13.2.2.11
30
PHY_INTERRUPT_MASK_x
31
PHY_SPECIAL_CONTROL_STATUS_x
13.2.2.1
Register Name
Port x PHY Auto-Negotiation Link Partner Base Page Ability
Register, Section 13.2.2.6
Port x PHY Auto-Negotiation Expansion Register,
Section 13.2.2.7
Port x PHY Interrupt Mask Register, Section 13.2.2.12
Port x PHY Special Control/Status Register, Section 13.2.2.13
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
Index (decimal):
0
Size:
16 bits
This read/write register is used to configure the Port x PHY.
Note:
This register is re-written in its entirety by the EEPROM Loader following the release of reset or a RELOAD
command. Refer to Section 8.2.4, "EEPROM Loader," on page 93 for additional information.
Bits
15
Description
Reset (PHY_RST)
When set, this bit resets all the Port x PHY registers to their default state,
except those marked as NASR type. This bit is self clearing.
Type
Default
R/W
SC
0b
0: Normal operation
1: Reset
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LAN9313/LAN9313i
Bits
Description
Type
Default
14
Loopback (PHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
from the switch fabric are not sent to network. Instead, they are looped back
into the switch fabric.
R/W
0b
R/W
Note 13-51
R/W
Note 13-52
R/W
0b
Note:
If loopback is enabled during half-duplex operation, then the Enable
Receive Own Transmit bit in the Port x MAC Receive Configuration
Register (MAC_RX_CFG_x) must be set for the specified port.
Otherwise, the switch fabric will ignore receive activity when
transmitting in half-duplex mode.
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
13
Speed Select LSB (PHY_SPEED_SEL_LSB)
This bit is used to set the speed of the Port x PHY when the Auto-Negotiation
(PHY_AN) bit is disabled.
0: 10 Mbps
1: 100 Mbps
12
Auto-Negotiation (PHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the Speed Select
LSB (PHY_SPEED_SEL_LSB) and Duplex Mode (PHY_DUPLEX) bits are
overridden.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
11
Power Down (PHY_PWR_DWN)
This bit controls the power down mode of the Port x PHY. After this bit is
cleared the PHY may auto-negotiate with it’s partner station. This process
can take up to a few seconds to complete. Once Auto-Negotiation is
complete, bit 5 (Auto-Negotiation Complete) of the Port x PHY Basic Status
Register (PHY_BASIC_STATUS_x) will be set.
Note:
The PHY_AN bit of this register must be cleared before setting this
bit.
0: Normal operation
1: General power down mode
10
RESERVED
RO
-
9
Restart Auto-Negotiation (PHY_RST_AN)
When set, this bit restarts the Auto-Negotiation process.
R/W
SC
0b
R/W
Note 13-53
R/W
0b
RO
-
0: Normal operation
1: Auto-Negotiation restarted
8
Duplex Mode (PHY_DUPLEX)
This bit is used to set the duplex when the Auto-Negotiation (PHY_AN) bit
is disabled.
0: Half Duplex
1: Full Duplex
7
Collision Test Mode (PHY_COL_TEST)
This bit enables/disables the collision test mode of the Port x PHY. When
set, the collision signal is active during transmission. It is recommended that
this feature be used only in loopback mode.
0: Collision test mode disabled
1: Collision test mode enabled
6:0
RESERVED
Note 13-51 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
(autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY) and the speed select strap
(speed_strap_1 for Port 1 PHY, speed_strap_2 for Port 2 PHY). Essentially, if the Auto-Negotiation
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LAN9313/LAN9313i
strap is set, the default value is 1, otherwise the default is determined by the value of the speed
select strap. Refer to Section 4.2.4, "Configuration Straps," on page 33 for more information.
Note 13-52 The default value of this bit is determined by the value of the Auto-Negotiation strap
(autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY). Refer to Section 4.2.4,
"Configuration Straps," on page 33 for more information.
Note 13-53 The default value of this bit is determined by the logical AND of the negation of the Auto-Negotiation
strap (autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY) and the duplex select strap
(duplex_strap_1 for Port 1 PHY, duplex_strap_2 for Port 2 PHY). Essentially, if the Auto-Negotiation
strap is set, the default value is 0, otherwise the default is determined by the value of the duplex
select strap. Refer to Section 4.2.4, "Configuration Straps," on page 33 for more information.
13.2.2.2
Port x PHY Basic Status Register (PHY_BASIC_STATUS_x)
Index (decimal):
1
Size:
16 bits
This register is used to monitor the status of the Port x PHY.
Bits
15
Description
100BASE-T4
This bit displays the status of 100BASE-T4 compatibility.
Type
Default
RO
0b
Note 13-54
RO
1b
RO
1b
RO
1b
RO
1b
RO
0b
Note 13-54
RO
0b
Note 13-54
0: PHY not able to perform 100BASE-T4
1: PHY able to perform 100BASE-T4
14
100BASE-X Full Duplex
This bit displays the status of 100BASE-X full duplex compatibility.
0: PHY not able to perform 100BASE-X full duplex
1: PHY able to perform 100BASE-X full duplex
13
100BASE-X Half Duplex
This bit displays the status of 100BASE-X half duplex compatibility.
0: PHY not able to perform 100BASE-X half duplex
1: PHY able to perform 100BASE-X half duplex
12
10BASE-T Full Duplex
This bit displays the status of 10BASE-T full duplex compatibility.
0: PHY not able to perform 10BASE-T full duplex
1: PHY able to perform 10BASE-T full duplex
11
10BASE-T Half Duplex
This bit displays the status of 10BASE-T half duplex compatibility.
0: PHY not able to perform 10BASE-T half duplex
1: PHY able to perform 10BASE-T half duplex
10
100BASE-T2 Full Duplex
This bit displays the status of 100BASE-T2 full duplex compatibility.
0: PHY not able to perform 100BASE-T2 full duplex
1: PHY able to perform 100BASE-T2 full duplex
9
100BASE-T2 Half Duplex
This bit displays the status of 100BASE-T2 half duplex compatibility.
0: PHY not able to perform 100BASE-T2 half duplex
1: PHY able to perform 100BASE-T2 half duplex
8:6
5
RESERVED
RO
-
Auto-Negotiation Complete
This bit indicates the status of the Auto-Negotiation process.
RO
0b
0: Auto-Negotiation process not completed
1: Auto-Negotiation process completed
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LAN9313/LAN9313i
Bits
4
Description
Remote Fault
This bit indicates if a remote fault condition has been detected.
Type
Default
RO/LH
0b
RO
1b
RO/LL
0b
RO/LH
0b
RO
1b
0: No remote fault condition detected
1: Remote fault condition detected
3
Auto-Negotiation Ability
This bit indicates the status of the PHY’s auto-negotiation.
0: PHY is unable to perform auto-negotiation
1: PHY is able to perform auto-negotiation
2
Link Status
This bit indicates the status of the link.
0: Link is down
1: Link is up
1
Jabber Detect
This bit indicates the status of the jabber condition.
0: No jabber condition detected
1: Jabber condition detected
0
Extended Capability
This bit indicates whether extended register capability is supported.
0: Basic register set capabilities only
1: Extended register set capabilities
Note 13-54 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex) only. All
other modes will always return as 0 (unable to perform).
13.2.2.3
Port x PHY Identification MSB Register (PHY_ID_MSB_x)
Index (decimal):
2
Size:
16 bits
This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the Port x PHY. The LSB of
the PHY OUI is contained in the Port x PHY Identification LSB Register (PHY_ID_LSB_x).
Bits
15:0
Description
PHY ID
This field is assigned to the 3rd through 18th bits of the OUI, respectively
(OUI = 00800Fh).
2008-2016 Microchip Technology Inc.
Type
Default
R/W
0007h
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13.2.2.4
Port x PHY Identification LSB Register (PHY_ID_LSB_x)
Index (decimal):
3
Size:
16 bits
This read/write register contains the LSB of the Organizationally Unique Identifier (OUI) for the Port x PHY. The MSB of
the PHY OUI is contained in the Port x PHY Identification MSB Register (PHY_ID_MSB_x).
Bits
Type
Default
PHY ID
This field is assigned to the 19th through 24th bits of the PHY OUI,
respectively. (OUI = 00800Fh).
R/W
110000b
9:4
Model Number
This field contains the 6-bit manufacturer’s model number of the PHY.
R/W
001101b
3:0
Revision Number
This field contain the 4-bit manufacturer’s revision number of the PHY.
R/W
0001b
15:10
13.2.2.5
Description
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
Index (decimal):
4
Size:
16 bits
This read/write register contains the advertised ability of the Port x PHY and is used in the Auto-Negotiation process
with the link partner.
Note:
This register is re-written by the EEPROM Loader following the release of reset or a RELOAD command.
Refer to Section 8.2.4, "EEPROM Loader," on page 93 for additional information.
Bits
15:14
13
Description
Type
Default
RESERVED
RO
-
Remote Fault
This bit determines if remote fault indication will be advertised to the link
partner.
R/W
0b
R/W
0b
R/W
0b
Note 13-55
R/W
Note 13-55
Note 13-56
0: Remote fault indication not advertised
1: Remote fault indication advertised
12
RESERVED
Note:
11
This bit should be written as 0.
Asymmetric Pause
This bit determines the advertised asymmetric pause capability.
0: No Asymmetric PAUSE toward link partner advertised
1: Asymmetric PAUSE toward link partner advertised
10
Symmetric Pause
This bit determines the advertised symmetric pause capability.
0: No Symmetric PAUSE toward link partner advertised
1: Symmetric PAUSE toward link partner advertised
9
RESERVED
RO
-
8
100BASE-X Full Duplex
This bit determines the advertised 100BASE-X full duplex capability.
R/W
1b
0: 100BASE-X full duplex ability not advertised
1: 100BASE-X full duplex ability advertised
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LAN9313/LAN9313i
Bits
7
Description
100BASE-X Half Duplex
This bit determines the advertised 100BASE-X half duplex capability.
Type
Default
R/W
1b
R/W
Note 13-57
Table 13-8
R/W
Note 13-58
Table 13-9
R/W
00001b
0: 100BASE-X half duplex ability not advertised
1: 100BASE-X half duplex ability advertised
6
10BASE-T Full Duplex
This bit determines the advertised 10BASE-T full duplex capability.
0: 10BASE-T full duplex ability not advertised
1: 10BASE-T full duplex ability advertised
5
10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
4:0
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13-55 The Pause and Asymmetric Pause bits are loaded into the PHY registers by the EEPROM Loader.
Note 13-56 The default value of this bit is determined by the Manual Flow Control Enable Strap
(manual_FC_strap_x). When the Manual Flow Control Enable Strap is 0, this bit defaults to 1
(symmetric pause advertised). When the Manual Flow Control Enable Strap is 1, this bit defaults to
0 (symmetric pause not advertised). Configuration strap values are latched upon the de-assertion of
a chip-level reset as described in Section 4.2.4, "Configuration Straps," on page 33. Refer to Section
4.2.4, "Configuration Straps," on page 33 for configuration strap definitions.
Note 13-57 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
(autoneg_strap_x) with the logical AND of the negated speed select strap (speed_strap_x) and
(duplex_strap_x). Table 13-8 defines the default behavior of this bit. Configuration strap values are
latched upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration
Straps," on page 33. Refer to Section 4.2.4, "Configuration Straps," on page 33 for configuration strap
definitions.
TABLE 13-8:
10BASE-T FULL DUPLEX ADVERTISEMENT DEFAULT VALUE
autoneg_strap_x
speed_strap_x
duplex_strap_x
Default 10BASE-T Full Duplex (Bit 6) Value
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
Note 13-58 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
(autoneg_strap_x) and the negated speed strap (speed_strap_x). Table 13-9 defines the default
behavior of this bit. Configuration strap values are latched upon the de-assertion of a chip-level reset
as described in Section 4.2.4, "Configuration Straps," on page 33. Refer to Section 4.2.4,
"Configuration Straps," on page 33 for configuration strap definitions.
2008-2016 Microchip Technology Inc.
DS00002288A-page 181
LAN9313/LAN9313i
TABLE 13-9:
10BASE-T HALF DUPLEX ADVERTISEMENT BIT DEFAULT VALUE
autoneg_strap_x
speed_strap_x
Default 10BASE-T Half Duplex (Bit 5) Value
0
0
1
0
1
0
1
0
1
1
1
1
13.2.2.6
Port x PHY Auto-Negotiation Link Partner Base Page Ability Register
(PHY_AN_LP_BASE_ABILITY_x)
Index (decimal):
5
Size:
16 bits
This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-Negotiation process between the link partner and the Port x PHY.
Bits
15
Description
Next Page
This bit indicates the link partner PHY page capability.
Type
Default
RO
0b
RO
0b
RO
0b
0: Link partner PHY does not advertise next page capability
1: Link partner PHY advertises next page capability
14
Acknowledge
This bit indicates whether the link code word has been received from the
partner.
0: Link code word not yet received from partner
1: Link code word received from partner
13
Remote Fault
This bit indicates whether a remote fault has been detected.
0: No remote fault
1: Remote fault detected
12
RESERVED
RO
-
11
Asymmetric Pause
This bit indicates the link partner PHY asymmetric pause capability.
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
0: No Asymmetric PAUSE toward link partner
1: Asymmetric PAUSE toward link partner
10
Pause
This bit indicates the link partner PHY symmetric pause capability.
0: No Symmetric PAUSE toward link partner
1: Symmetric PAUSE toward link partner
9
100BASE-T4
This bit indicates the link partner PHY 100BASE-T4 capability.
0: 100BASE-T4 ability not supported
1: 100BASE-T4 ability supported
8
100BASE-X Full Duplex
This bit indicates the link partner PHY 100BASE-X full duplex capability.
0: 100BASE-X full duplex ability not supported
1: 100BASE-X full duplex ability supported
7
100BASE-X Half Duplex
This bit indicates the link partner PHY 100BASE-X half duplex capability.
0: 100BASE-X half duplex ability not supported
1: 100BASE-X half duplex ability supported
DS00002288A-page 182
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Bits
6
Description
10BASE-T Full Duplex
This bit indicates the link partner PHY 10BASE-T full duplex capability.
Type
Default
RO
0b
RO
0b
RO
00001b
Note 13-59
0: 10BASE-T full duplex ability not supported
1: 10BASE-T full duplex ability supported
5
10BASE-T Half Duplex
This bit indicates the link partner PHY 10BASE-T half duplex capability.
0: 10BASE-T half duplex ability not supported
1: 10BASE-T half duplex ability supported
4:0
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13-59 The Port 1 & 2 PHY’s support only IEEE 802.3.
13.2.2.7
Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x)
Index (decimal):
6
Size:
16 bits
This read/write register is used in the Auto-Negotiation process between the link partner and the Port x PHY.
Bits
15:5
4
Description
RESERVED
Parallel Detection Fault
This bit indicates whether a Parallel Detection Fault has been detected.
Type
Default
RO
-
RO/LH
0b
RO
0b
RO
0b
RO/LH
0b
RO
0b
0: A fault hasn’t been detected via the Parallel Detection function
1: A fault has been detected via the Parallel Detection function
3
Link Partner Next Page Able
This bit indicates whether the link partner has next page ability.
0: Link partner does not contain next page capability
1: Link partner contains next page capability
2
Local Device Next Page Able
This bit indicates whether the local device has next page ability.
0: Local device does not contain next page capability
1: Local device contains next page capability
1
Page Received
This bit indicates the reception of a new page.
0: A new page has not been received
1: A new page has been received
0
Link Partner Auto-Negotiation Able
This bit indicates the Auto-negotiation ability of the link partner.
0: Link partner is not Auto-Negotiation able
1: Link partner is Auto-Negotiation able
2008-2016 Microchip Technology Inc.
DS00002288A-page 183
LAN9313/LAN9313i
13.2.2.8
Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
Index (decimal):
17
Size:
16 bits
This read/write register is used to control and monitor various Port x PHY configuration options.
Bits
15:14
13
Description
Type
Default
RESERVED
RO
-
Energy Detect Power-Down (EDPWRDOWN)
This bit controls the Energy Detect Power-Down mode.
R/W
0b
RESERVED
RO
-
Energy On (ENERGYON)
This bit indicates whether energy is detected on the line. It is cleared if no
valid energy is detected within 256ms. This bit is unaffected by a software
reset and is reset to 1 by a hardware reset.
RO
1b
R/W
0b
0: Energy Detect Power-Down is disabled
1: Energy Detect Power-Down is enabled
12:2
1
0: No valid energy detected on the line
1: Energy detected on the line
0
13.2.2.9
RESERVED
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Index (decimal):
18
Size:
16 bits
This read/write register is used to control the special modes of the Port x PHY.
Note:
This register is re-written by the EEPROM Loader following the release of reset or a RELOAD command.
Refer to Section 8.2.4, "EEPROM Loader," on page 93 for more information.
Bits
Description
Type
15:8
RESERVED
7:5
PHY Mode (MODE[2:0])
This field controls the PHY mode of operation. Refer to Table 13-10 for a
definition of each mode.
4:0
PHY Address (PHYADD)
The PHY Address field determines the MMI address to which the PHY will
respond and is also used for initialization of the cipher (scrambler) key. Each
PHY must have a unique address. Refer to Section 7.1.1, "PHY Addressing,"
on page 68 for additional information.
Note:
Default
RO
-
R/W
NASR
Note 13-61
Note 13-60
R/W
NASR
Note 13-62
Note 13-60
No check is performed to ensure that this address is unique from
the other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual
PHY).
Note 13-60 Register bits designated as NASR are reset when the Port x PHY Reset is generated via the Reset
Control Register (RESET_CTL). The NASR designation is only applicable when the Reset
(PHY_RST) bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is set.
Note 13-61 The default value of this field is determined by a combination of the configuration straps
autoneg_strap_x, speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then the default
MODE[2:0] value is 111b. Else, the default value of this field is determined by the remaining straps.
MODE[2]=0, MODE[1]=(speed_strap_1 for Port 1 PHY, speed_strap_2 for Port 2 PHY), and
MODE[0]=(duplex_strap_1 for Port 1 PHY, duplex_strap_2 for Port 2 PHY). Configuration strap
values are latched upon the de-assertion of a chip-level reset as described in Section 4.2.4,
DS00002288A-page 184
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
"Configuration Straps," on page 33. Refer to Section 4.2.4, "Configuration Straps," on page 33 for
configuration strap definitions.
Note 13-62 The default value of this field is determined by the phy_addr_sel_strap configuration strap. Refer to
Section 7.1.1, "PHY Addressing," on page 68 for additional information.
TABLE 13-10: MODE[2:0] DEFINITIONS
Affected Register Bit Values
MODE[2:0]
Mode Definitions
PHY_BASIC_CONTROL_x
PHY_AN_ADV_x
[13,12,10,8]
[8,7,6,5]
000
10BASE-T Half Duplex. Auto-negotiation disabled.
0000
N/A
001
10BASE-T Full Duplex. Auto-negotiation disabled.
0001
N/A
010
100BASE-TX Half Duplex. Auto-negotiation
disabled. CRS is active during Transmit & Receive.
1000
N/A
011
100BASE-TX Full Duplex. Auto-negotiation
disabled. CRS is active during Receive.
1001
N/A
100
100BASE-TX Half Duplex is advertised. Autonegotiation enabled.
CRS is active during Transmit & Receive.
1100
0100
101
Repeater mode. Auto-negotiation enabled.
100BASE-TX Half Duplex is advertised.
CRS is active during Receive.
1100
0100
110
Power Down mode. In this mode the PHY wake-up
in Power-Down mode.
N/A
N/A
111
All capable. Auto-negotiation enabled.
X10X
1111
13.2.2.10
Port x PHY Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x)
Index (decimal):
27
Size:
16 bits
This read/write register is used to control various options of the Port x PHY.
Bits
Description
Type
Default
15
Auto-MDIX Control (AMDIXCTRL)
This bit is responsible for determining the source of Auto-MDIX control for
Port x. When set, the Manual MDIX and Auto MDIX straps
(manual_mdix_strap_1/auto_mdix_strap_1 for Port 1 PHY,
manual_mdix_strap_2/auto_mdix_strap_2 for Port 2 PHY) are overridden,
and Auto-MDIX functions are controlled using bit 14 (AMDIXEN) and bit 13
(AMDIXSTATE) of this register. When cleared, Auto-MDIX functionality is
controlled by the Manual MDIX and Auto MDIX straps by default. Refer to
Section 4.2.4, "Configuration Straps," on page 33 for configuration strap
definitions.
R/W
NASR
0b
Note 13-63
0: Port x Auto-MDIX determined by strap inputs
1: Port x Auto-MDIX determined by bits 14 and 13
14
13
12
Auto-MDIX Enable (AMDIXEN)
When bit 15 (AMDIXCTRL) of this register is set, this bit is used in
conjunction with bit 13 (Auto-MDIX State) to control the Port x Auto-MDIX
functionality as shown in Table 13-11.
Auto-MDIX State (AMDIXSTATE)
When bit 15 (AMDIXCTRL) of this register is set, this bit is used in
conjunction with bit 14 (Auto-MDIX Enable) to control the Port x Auto-MDIX
functionality as shown in Table 13-11.
RESERVED
2008-2016 Microchip Technology Inc.
R/W
NASR
0b
Note 13-63
R/W
NASR
0b
Note 13-63
RO
-
DS00002288A-page 185
LAN9313/LAN9313i
Bits
11
Description
SQE Test Disable (SQEOFF)
This bit controls the disabling of the SQE test (Heartbeat). SQE test is
enabled by default.
Type
Default
R/W
NASR
0b
Note 13-63
0: SQE test enabled
1: SQE test disabled
10
Receive PLL Lock Control (VCOOFF_LP)
This bit controls the locking of the receive PLL. Setting this bit to 1 forces
the receive PLL 10M to lock on the reference clock at all times. When in this
mode, 10M data packets cannot be received.
R/W
NASR
0b
Note 13-63
0: Receive PLL 10M can lock on reference or line as needed (normal
operation)
1: Receive PLL 10M locked onto reference clock at all times
9:5
4
RESERVED
RO
-
10Base-T Polarity State (XPOL)
This bit shows the polarity state of the 10Base-T.
RO
0b
RO
-
0: Normal Polarity
1: Reversed Polarity
3:0
RESERVED
Note 13-63 Register bits designated as NASR are reset when the Port x PHY Reset is generated via the Reset
Control Register (RESET_CTL). The NASR designation is only applicable when the Reset
(PHY_RST) bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is set.
TABLE 13-11: AUTO-MDIX ENABLE AND AUTO-MDIX STATE BIT FUNCTIONALITY
Auto-MDIX Enable
(Bit 14)
Auto-MDIX State
(Bit 13)
Mode
0
0
Manual mode, no crossover
0
1
Manual mode, crossover
1
0
Auto-MDIX mode
1
1
RESERVED (do not use this state)
13.2.2.11
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
Index (decimal):
29
Size:
16 bits
This read-only register is used to determine to source of various Port x PHY interrupts. All interrupt source bits in this
register are read-only and latch high upon detection of the corresponding interrupt (if enabled). A read of this register
clears the interrupts. These interrupts are enabled or masked via the Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x).
Bits
15:8
7
Description
Type
RESERVED
INT7
This interrupt source bit indicates when the ENERGYON bit of the Port x
PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
has been set.
Default
RO
-
RO/LH
0b
0: Not source of interrupt
1: ENERGYON generated
DS00002288A-page 186
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Bits
6
Description
INT6
This interrupt source bit indicates Auto-Negotiation is complete.
Type
Default
RO/LH
0b
RO/LH
0b
RO/LH
0b
RO/LH
0b
RO/LH
0b
RO/LH
0b
RO
-
0: Not source of interrupt
1: Auto-Negotiation complete
5
INT5
This interrupt source bit indicates a remote fault has been detected.
0: Not source of interrupt
1: Remote fault detected
4
INT4
This interrupt source bit indicates a Link Down (link status negated).
0: Not source of interrupt
1: Link Down (link status negated)
3
INT3
This interrupt source bit indicates an Auto-Negotiation LP acknowledge.
0: Not source of interrupt
1: Auto-Negotiation LP acknowledge
2
INT2
This interrupt source bit indicates a Parallel Detection fault.
0: Not source of interrupt
1: Parallel Detection fault
1
INT1
This interrupt source bit indicates an Auto-Negotiation page received.
0: Not source of interrupt
1: Auto-Negotiation page received
0
13.2.2.12
RESERVED
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
Index (decimal):
30
Size:
16 bits
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in conjunction with the
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
Bits
15:8
7
Description
Type
Default
RESERVED
RO
-
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
R/W
0b
R/W
0b
R/W
0b
0: Interrupt source is masked
1: Interrupt source is enabled
6
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
5
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
2008-2016 Microchip Technology Inc.
DS00002288A-page 187
LAN9313/LAN9313i
Bits
4
Description
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
Type
Default
R/W
0b
R/W
0b
R/W
0b
R/W
0b
RO
-
0: Interrupt source is masked
1: Interrupt source is enabled
3
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
2
INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
1
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
0
13.2.2.13
RESERVED
Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x)
Index (decimal):
31
Size:
16 bits
This read/write register is used to control and monitor various options of the Port x PHY.
Bits
15:13
12
Description
Type
Default
RESERVED
RO
-
Autodone
This bit indicates the status of the Auto-Negotiation on the Port x PHY.
RO
0b
0: Auto-Negotiation is not completed, is disabled, or is not active
1: Auto-Negotiation is completed
11:5
RESERVED - Write as 0000010b, ignore on read
R/W
0000010b
4:2
Speed Indication
This field indicates the current Port x PHY speed configuration.
RO
000b
R/W
0b
STATE
1:0
DESCRIPTION
000
RESERVED
001
10BASE-T Half-duplex
010
100BASE-TX Half-duplex
011
RESERVED
100
RESERVED
101
10BASE-T Full-duplex
110
100BASE-TX Full-duplex
111
RESERVED
RESERVED
DS00002288A-page 188
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3
Switch Fabric Control and Status Registers
This section details the various LAN9313/LAN9313i switch control and status registers that reside within the switch fabric. The switch control and status registers allow configuration of each individual switch port, the switch engine, and buffer manager. Switch fabric related interrupts and resets are also controlled and monitored via the switch CSRs.
The switch CSRs are not memory mapped. All switch CSRs are accessed indirectly via the Switch Fabric CSR Interface
Command Register (SWITCH_CSR_CMD), Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA), and
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) in the system CSR memory
mapped address space. All accesses to the switch CSRs must be performed through these registers. Refer to Section
13.1.5, "Switch Fabric" for additional information.
Note:
The flow control settings of the switch ports are configured via the Switch Fabric registers: Port 1 Manual
Flow Control Register (MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), and Port
0(External MII) Manual Flow Control Register (MANUAL_FC_MII) located in the system CSR address
space.
Table 13-12 lists the Switch CSRs and their corresponding addresses in order. The switch fabric registers can be categorized into the following sub-sections:
•
•
•
•
Section 13.3.1, "General Switch CSRs," on page 197
Section 13.3.2, "Switch Port 0, Port 1, and Port 2 CSRs," on page 199
Section 13.3.3, "Switch Engine CSRs," on page 216
Section 13.3.4, "Buffer Manager CSRs," on page 239
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
Register Name
0000h
SW_DEV_ID
Switch Device ID Register, Section 13.3.1.1
General Switch CSRs
0001h
SW_RESET
Switch Reset Register, Section 13.3.1.2
0002h-0003h
RESERVED
Reserved for Future Use
0004h
SW_IMR
Switch Global Interrupt Mask Register, Section 13.3.1.3
0005h
SW_IPR
Switch Global Interrupt Pending Register, Section 13.3.1.4
0006h-03FFh
RESERVED
Reserved for Future Use
Switch Port 0 CSRs
0400h
MAC_VER_ID_MII
Port 0 MAC Version ID Register, Section 13.3.2.1
0401h
MAC_RX_CFG_MII
Port 0 MAC Receive Configuration Register, Section 13.3.2.2
0402h-040Fh
RESERVED
0410h
MAC_RX_UNDSZE_CNT_MII
Reserved for Future Use
Port 0 MAC Receive Undersize Count Register, Section 13.3.2.3
0411h
MAC_RX_64_CNT_MII
0412h
MAC_RX_65_TO_127_CNT_MII
Port 0 MAC Receive 65 to 127 Byte Count Register,
Section 13.3.2.5
0413h
MAC_RX_128_TO_255_CNT_MII
Port 0 MAC Receive 128 to 255 Byte Count Register,
Section 13.3.2.6
0414h
MAC_RX_256_TO_511_CNT_MII
Port 0 MAC Receive 256 to 511 Byte Count Register,
Section 13.3.2.7
0415h
MAC_RX_512_TO_1023_CNT_MII
Port 0 MAC Receive 512 to 1023 Byte Count Register,
Section 13.3.2.8
0416h
MAC_RX_1024_TO_MAX_CNT_MII
Port 0 MAC Receive 1024 to Max Byte Count Register,
Section 13.3.2.9
0417h
MAC_RX_OVRSZE_CNT_MII
Port 0 MAC Receive Oversize Count Register, Section 13.3.2.10
0418h
MAC_RX_PKTOK_CNT_MII
Port 0 MAC Receive OK Count Register, Section 13.3.2.11
0419h
MAC_RX_CRCERR_CNT_MII
Port 0 MAC Receive CRC Error Count Register,
Section 13.3.2.12
041Ah
MAC_RX_MULCST_CNT_MII
Port 0 MAC Receive Multicast Count Register, Section 13.3.2.13
2008-2016 Microchip Technology Inc.
Port 0 MAC Receive 64 Byte Count Register, Section 13.3.2.4
DS00002288A-page 189
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
041Bh
MAC_RX_BRDCST_CNT_MII
041Ch
MAC_RX_PAUSE_CNT_MII
Port 0 MAC Receive Pause Frame Count Register,
Section 13.3.2.15
041Dh
MAC_RX_FRAG_CNT_MII
Port 0 MAC Receive Fragment Error Count Register,
Section 13.3.2.16
041Eh
MAC_RX_JABB_CNT_MII
Port 0 MAC Receive Jabber Error Count Register,
Section 13.3.2.17
041Fh
MAC_RX_ALIGN_CNT_MII
Port 0 MAC Receive Alignment Error Count Register,
Section 13.3.2.18
0420h
MAC_RX_PKTLEN_CNT_MII
0421h
MAC_RX_GOODPKTLEN_CNT_MII
Port 0 MAC Receive Good Packet Length Count Register,
Section 13.3.2.20
0422h
MAC_RX_SYMBL_CNT_MII
Port 0 MAC Receive Symbol Error Count Register,
Section 13.3.2.21
0423h
MAC_RX_CTLFRM_CNT_MII
0424h-043Fh
RESERVED
0440h
MAC_TX_CFG_MII
0441h
MAC_TX_FC_SETTINGS_MII
Register Name
Port 0 MAC Receive Broadcast Count Register,
Section 13.3.2.14
Port 0 MAC Receive Packet Length Count Register,
Section 13.3.2.19
Port 0 MAC Receive Control Frame Count Register,
Section 13.3.2.22
Reserved for Future Use
Port 0 MAC Transmit Configuration Register, Section 13.3.2.23
Port 0 MAC Transmit Flow Control Settings Register,
Section 13.3.2.24
0442h-0450h
RESERVED
0451h
MAC_TX_DEFER_CNT_MII
Port 0 MAC Transmit Deferred Count Register, Section 13.3.2.25
Reserved for Future Use
0452h
MAC_TX_PAUSE_CNT_MII
Port 0 MAC Transmit Pause Count Register, Section 13.3.2.26
0453h
MAC_TX_PKTOK_CNT_MII
Port 0 MAC Transmit OK Count Register, Section 13.3.2.27
0454h
MAC_TX_64_CNT_MII
0455h
MAC_TX_65_TO_127_CNT_MII
Port 0 MAC Transmit 64 Byte Count Register, Section 13.3.2.28
Port 0 MAC Transmit 65 to 127 Byte Count Register,
Section 13.3.2.29
0456h
MAC_TX_128_TO_255_CNT_MII
Port 0 MAC Transmit 128 to 255 Byte Count Register,
Section 13.3.2.30
0457h
MAC_TX_256_TO_511_CNT_MII
Port 0 MAC Transmit 256 to 511 Byte Count Register,
Section 13.3.2.31
0458h
MAC_TX_512_TO_1023_CNT_MII
Port 0 MAC Transmit 512 to 1023 Byte Count Register,
Section 13.3.2.32
0459h
MAC_TX_1024_TO_MAX_CNT_MII
Port 0 MAC Transmit 1024 to Max Byte Count Register,
Section 13.3.2.33
045Ah
MAC_TX_UNDSZE_CNT_MII
Port 0 MAC Transmit Undersize Count Register,
Section 13.3.2.34
045Bh
RESERVED
045Ch
MAC_TX_PKTLEN_CNT_MII
Port 0 MAC Transmit Packet Length Count Register,
Section 13.3.2.35
045Dh
MAC_TX_BRDCST_CNT_MII
Port 0 MAC Transmit Broadcast Count Register,
Section 13.3.2.36
045Eh
MAC_TX_MULCST_CNT_MII
045Fh
MAC_TX_LATECOL_MII
0460h
MAC_TX_EXCOL_CNT_MII
Port 0 MAC Transmit Excessive Collision Count Register,
Section 13.3.2.39
0461h
MAC_TX_SNGLECOL_CNT_MII
Port 0 MAC Transmit Single Collision Count Register,
Section 13.3.2.40
DS00002288A-page 190
Reserved for Future Use
Port 0 MAC Transmit Multicast Count Register, Section 13.3.2.37
Port 0 MAC Transmit Late Collision Count Register,
Section 13.3.2.38
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
Register Name
0462h
MAC_TX_MULTICOL_CNT_MII
Port 0 MAC Transmit Multiple Collision Count Register,
Section 13.3.2.41
0463h
MAC_TX_TOTALCOL_CNT_MII
Port 0 MAC Transmit Total Collision Count Register,
Section 13.3.2.42
0464-047Fh
RESERVED
0480h
MAC_IMR_MII
Port 0 MAC Interrupt Mask Register, Section 13.3.2.43
Reserved for Future Use
Port 0 MAC Interrupt Pending Register, Section 13.3.2.44
0481h
MAC_IPR_MII
0482h-07FFh
RESERVED
0800h
MAC_VER_ID_1
Port 1 MAC Version ID Register, Section 13.3.2.1
Port 1 MAC Receive Configuration Register, Section 13.3.2.2
Reserved for Future Use
Switch Port 1 CSRs
0801h
MAC_RX_CFG_1
0802h-080Fh
RESERVED
0810h
MAC_RX_UNDSZE_CNT_1
0811h
MAC_RX_64_CNT_1
0812h
MAC_RX_65_TO_127_CNT_1
Port 1 MAC Receive 65 to 127 Byte Count Register,
Section 13.3.2.5
0813h
MAC_RX_128_TO_255_CNT_1
Port 1 MAC Receive 128 to 255 Byte Count Register,
Section 13.3.2.6
0814h
MAC_RX_256_TO_511_CNT_1
Port 1 MAC Receive 256 to 511 Byte Count Register,
Section 13.3.2.7
0815h
MAC_RX_512_TO_1023_CNT_1
Port 1 MAC Receive 512 to 1023 Byte Count Register,
Section 13.3.2.8
0816h
MAC_RX_1024_TO_MAX_CNT_1
Port 1 MAC Receive 1024 to Max Byte Count Register,
Section 13.3.2.9
0817h
MAC_RX_OVRSZE_CNT_1
0818h
MAC_RX_PKTOK_CNT_1
0819h
MAC_RX_CRCERR_CNT_1
Port 1 MAC Receive CRC Error Count Register,
Section 13.3.2.12
081Ah
MAC_RX_MULCST_CNT_1
Port 1 MAC Receive Multicast Count Register, Section 13.3.2.13
081Bh
MAC_RX_BRDCST_CNT_1
Port 1 MAC Receive Broadcast Count Register,
Section 13.3.2.14
081Ch
MAC_RX_PAUSE_CNT_1
Port 1 MAC Receive Pause Frame Count Register,
Section 13.3.2.15
081Dh
MAC_RX_FRAG_CNT_1
Port 1 MAC Receive Fragment Error Count Register,
Section 13.3.2.16
081Eh
MAC_RX_JABB_CNT_1
Port 1 MAC Receive Jabber Error Count Register,
Section 13.3.2.17
081Fh
MAC_RX_ALIGN_CNT_1
Port 1 MAC Receive Alignment Error Count Register,
Section 13.3.2.18
0820h
MAC_RX_PKTLEN_CNT_1
Port 1 MAC Receive Packet Length Count Register,
Section 13.3.2.19
0821h
MAC_RX_GOODPKTLEN_CNT_1
Port 1 MAC Receive Good Packet Length Count Register,
Section 13.3.2.20
0822h
MAC_RX_SYMBL_CNT_1
Port 1 MAC Receive Symbol Error Count Register,
Section 13.3.2.21
0823h
MAC_RX_CTLFRM_CNT_1
Port 1 MAC Receive Control Frame Count Register,
Section 13.3.2.22
0824h-083Fh
RESERVED
0840h
MAC_TX_CFG_1
0841h
MAC_TX_FC_SETTINGS_1
2008-2016 Microchip Technology Inc.
Reserved for Future Use
Port 1 MAC Receive Undersize Count Register, Section 13.3.2.3
Port 1 MAC Receive 64 Byte Count Register, Section 13.3.2.4
Port 1 MAC Receive Oversize Count Register, Section 13.3.2.10
Port 1 MAC Receive OK Count Register, Section 13.3.2.11
Reserved for Future Use
Port 1 MAC Transmit Configuration Register, Section 13.3.2.23
Port 1 MAC Transmit Flow Control Settings Register,
Section 13.3.2.24
DS00002288A-page 191
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
0842h-0850h
RESERVED
Register Name
Reserved for Future Use
0851h
MAC_TX_DEFER_CNT_1
Port 1 MAC Transmit Deferred Count Register, Section 13.3.2.25
0852h
MAC_TX_PAUSE_CNT_1
Port 1 MAC Transmit Pause Count Register, Section 13.3.2.26
0853h
MAC_TX_PKTOK_CNT_1
Port 1 MAC Transmit OK Count Register, Section 13.3.2.27
0854h
MAC_RX_64_CNT_1
0855h
MAC_TX_65_TO_127_CNT_1
Port 1 MAC Transmit 65 to 127 Byte Count Register,
Section 13.3.2.29
0856h
MAC_TX_128_TO_255_CNT_1
Port 1 MAC Transmit 128 to 255 Byte Count Register,
Section 13.3.2.30
0857h
MAC_TX_256_TO_511_CNT_1
Port 1 MAC Transmit 256 to 511 Byte Count Register,
Section 13.3.2.31
0858h
MAC_TX_512_TO_1023_CNT_1
Port 1 MAC Transmit 512 to 1023 Byte Count Register,
Section 13.3.2.32
0859h
MAC_TX_1024_TO_MAX_CNT_1
Port 1 MAC Transmit 1024 to Max Byte Count Register,
Section 13.3.2.33
085Ah
MAC_TX_UNDSZE_CNT_1
Port 1 MAC Transmit Undersize Count Register,
Section 13.3.2.34
085Bh
RESERVED
085Ch
MAC_TX_PKTLEN_CNT_1
Port 1 MAC Transmit Packet Length Count Register,
Section 13.3.2.35
085Dh
MAC_TX_BRDCST_CNT_1
Port 1 MAC Transmit Broadcast Count Register,
Section 13.3.2.36
085Eh
MAC_TX_MULCST_CNT_1
Port 1 MAC Transmit Multicast Count Register, Section 13.3.2.37
085Fh
MAC_TX_LATECOL_1
0860h
MAC_TX_EXCOL_CNT_1
0861h
MAC_TX_SNGLECOL_CNT_1
Port 1 MAC Transmit Single Collision Count Register,
Section 13.3.2.40
0862h
MAC_TX_MULTICOL_CNT_1
Port 1 MAC Transmit Multiple Collision Count Register,
Section 13.3.2.41
0863h
MAC_TX_TOTALCOL_CNT_1
Port 1 MAC Transmit Total Collision Count Register,
Section 13.3.2.42
Port 1 MAC Transmit 64 Byte Count Register, Section 13.3.2.28
Reserved for Future Use
Port 1 MAC Transmit Late Collision Count Register,
Section 13.3.2.38
Port 1 MAC Transmit Excessive Collision Count Register,
Section 13.3.2.39
0864-087Fh
RESERVED
Reserved for Future Use
0880h
MAC_IMR_1
Port 1 MAC Interrupt Mask Register, Section 13.3.2.43
0881h
MAC_IPR_1
Port 1 MAC Interrupt Pending Register, Section 13.3.2.44
0882h-0BFFh
RESERVED
Reserved for Future Use
0C00h
MAC_VER_ID_2
Port 2 MAC Version ID Register, Section 13.3.2.1
Port 2 MAC Receive Configuration Register, Section 13.3.2.2
Switch Port 2 CSRs
0C01h
MAC_RX_CFG_2
0C02h-0C0Fh
RESERVED
0C10h
MAC_RX_UNDSZE_CNT_2
Reserved for Future Use
Port 2 MAC Receive Undersize Count Register, Section 13.3.2.3
0C11h
MAC_RX_64_CNT_2
0C12h
MAC_RX_65_TO_127_CNT_2
Port 2 MAC Receive 65 to 127 Byte Count Register,
Section 13.3.2.5
0C13h
MAC_RX_128_TO_255_CNT_2
Port 2 MAC Receive 128 to 255 Byte Count Register,
Section 13.3.2.6
0C14h
MAC_RX_256_TO_511_CNT_2
Port 2 MAC Receive 256 to 511 Byte Count Register,
Section 13.3.2.7
DS00002288A-page 192
Port 2 MAC Receive 64 Byte Count Register, Section 13.3.2.4
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
0C15h
MAC_RX_512_TO_1023_CNT_2
Port 2 MAC Receive 512 to 1023 Byte Count Register,
Section 13.3.2.8
0C16h
MAC_RX_1024_TO_MAX_CNT_2
Port 2 MAC Receive 1024 to Max Byte Count Register,
Section 13.3.2.9
0C17h
MAC_RX_OVRSZE_CNT_2
0C18h
MAC_RX_PKTOK_CNT_2
0C19h
MAC_RX_CRCERR_CNT_2
Port 2 MAC Receive CRC Error Count Register,
Section 13.3.2.12
0C1Ah
MAC_RX_MULCST_CNT_2
Port 2 MAC Receive Multicast Count Register, Section 13.3.2.13
0C1Bh
MAC_RX_BRDCST_CNT_2
Port 2 MAC Receive Broadcast Count Register,
Section 13.3.2.14
0C1Ch
MAC_RX_PAUSE_CNT_2
Port 2 MAC Receive Pause Frame Count Register,
Section 13.3.2.15
0C1Dh
MAC_RX_FRAG_CNT_2
Port 2 MAC Receive Fragment Error Count Register,
Section 13.3.2.16
0C1Eh
MAC_RX_JABB_CNT_2
Port 2 MAC Receive Jabber Error Count Register,
Section 13.3.2.17
0C1Fh
MAC_RX_ALIGN_CNT_2
Port 2 MAC Receive Alignment Error Count Register,
Section 13.3.2.18
0C20h
MAC_RX_PKTLEN_CNT_2
Port 2 MAC Receive Packet Length Count Register,
Section 13.3.2.19
0C21h
MAC_RX_GOODPKTLEN_CNT_2
Port 2 MAC Receive Good Packet Length Count Register,
Section 13.3.2.20
0C22h
MAC_RX_SYMBL_CNT_2
Port 2 MAC Receive Symbol Error Count Register,
Section 13.3.2.21
0C23h
MAC_RX_CTLFRM_CNT_2
Port 2 MAC Receive Control Frame Count Register,
Section 13.3.2.22
0C24h-0C3Fh
RESERVED
0C40h
MAC_TX_CFG_2
0C41h
MAC_TX_FC_SETTINGS_2
0C42h-0C50h
RESERVED
0C51h
MAC_TX_DEFER_CNT_2
Register Name
Port 2 MAC Receive Oversize Count Register, Section 13.3.2.10
Port 2 MAC Receive OK Count Register, Section 13.3.2.11
Reserved for Future Use
Port 2 MAC Transmit Configuration Register, Section 13.3.2.23
Port 2 MAC Transmit Flow Control Settings Register,
Section 13.3.2.24
Reserved for Future Use
Port 2 MAC Transmit Deferred Count Register, Section 13.3.2.25
0C52h
MAC_TX_PAUSE_CNT_2
Port 2 MAC Transmit Pause Count Register, Section 13.3.2.26
0C53h
MAC_TX_PKTOK_CNT_2
Port 2 MAC Transmit OK Count Register, Section 13.3.2.27
0C54h
MAC_RX_64_CNT_2
0C55h
MAC_TX_65_TO_127_CNT_2
Port 2 MAC Transmit 65 to 127 Byte Count Register,
Section 13.3.2.29
0C56h
MAC_TX_128_TO_255_CNT_2
Port 2 MAC Transmit 128 to 255 Byte Count Register,
Section 13.3.2.30
0C57h
MAC_TX_256_TO_511_CNT_2
Port 2 MAC Transmit 256 to 511 Byte Count Register,
Section 13.3.2.31
0C58h
MAC_TX_512_TO_1023_CNT_2
Port 2 MAC Transmit 512 to 1023 Byte Count Register,
Section 13.3.2.32
0C59h
MAC_TX_1024_TO_MAX_CNT_2
Port 2 MAC Transmit 1024 to Max Byte Count Register,
Section 13.3.2.33
0C5Ah
MAC_TX_UNDSZE_CNT_2
Port 2 MAC Transmit Undersize Count Register,
Section 13.3.2.34
0C5Bh
RESERVED
0C5Ch
MAC_TX_PKTLEN_CNT_2
2008-2016 Microchip Technology Inc.
Port 2 MAC Transmit 64 Byte Count Register, Section 13.3.2.28
Reserved for Future Use
Port 2 MAC Transmit Packet Length Count Register,
Section 13.3.2.35
DS00002288A-page 193
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
Register Name
0C5Dh
MAC_TX_BRDCST_CNT_2
Port 2 MAC Transmit Broadcast Count Register,
Section 13.3.2.36
0C5Eh
MAC_TX_MULCST_CNT_2
Port 2 MAC Transmit Multicast Count Register, Section 13.3.2.37
0C5Fh
MAC_TX_LATECOL_2
0C60h
MAC_TX_EXCOL_CNT_2
0C61h
MAC_TX_SNGLECOL_CNT_2
Port 2 MAC Transmit Single Collision Count Register,
Section 13.3.2.40
0C62h
MAC_TX_MULTICOL_CNT_2
Port 2 MAC Transmit Multiple Collision Count Register,
Section 13.3.2.41
0C63h
MAC_TX_TOTALCOL_CNT_2
Port 2 MAC Transmit Total Collision Count Register,
Section 13.3.2.42
0C64-0C7Fh
RESERVED
0C80h
MAC_IMR_2
Port 2 MAC Interrupt Mask Register, Section 13.3.2.43
0C81h
MAC_IPR_2
Port 2 MAC Interrupt Pending Register, Section 13.3.2.44
0C82h-17FFh
RESERVED
Port 2 MAC Transmit Late Collision Count Register,
Section 13.3.2.38
Port 2 MAC Transmit Excessive Collision Count Register,
Section 13.3.2.39
Reserved for Future Use
Reserved for Future Use
Switch Engine CSRs
1800h
SWE_ALR_CMD
1801h
SWE_ALR_WR_DAT_0
Switch Engine ALR Command Register, Section 13.3.3.1
Switch Engine ALR Write Data 0 Register, Section 13.3.3.2
1802h
SWE_ALR_WR_DAT_1
Switch Engine ALR Write Data 1 Register, Section 13.3.3.3
1803h-1804h
RESERVED
Reserved for Future Use
1805h
SWE_ALR_RD_DAT_0
Switch Engine ALR Read Data 0 Register, Section 13.3.3.4
1806h
SWE_ALR_RD_DAT_1
Switch Engine ALR Read Data 1 Register, Section 13.3.3.5
1807h
RESERVED
1808h
SWE_ALR_CMD_STS
1809h
SWE_ALR_CFG
180Ah
RESERVED
Reserved for Future Use
Switch Engine ALR Command Status Register, Section 13.3.3.6
Switch Engine ALR Configuration Register, Section 13.3.3.7
Reserved for Future Use
180Bh
SWE_VLAN_CMD
Switch Engine VLAN Command Register, Section 13.3.3.8
180Ch
SWE_VLAN_WR_DATA
Switch Engine VLAN Write Data Register, Section 13.3.3.9
180Dh
RESERVED
180Eh
SWE_VLAN_RD_DATA
Reserved for Future Use
Switch Engine VLAN Read Data Register, Section 13.3.3.10
180Fh
RESERVED
1810h
SWE_VLAN_CMD_STS
Reserved for Future Use
1811h
SWE_DIFFSERV_TBL_CMD
Switch Engine DIFSERV Table Command Register,
Section 13.3.3.12
1812h
SWE_DIFFSERV_TBL_WR_DATA
Switch Engine DIFFSERV Table Write Data Register,
Section 13.3.3.13
1813h
SWE_DIFFSERV_TBL_RD_DATA
Switch Engine DIFFSERV Table Read Data Register,
Section 13.3.3.14
1814h
SWE_DIFFSERV_TBL_CMD_STS
Switch Engine DIFFSERV Table Command Status Register,
Section 13.3.3.15
Switch Engine VLAN Command Status Register,
Section 13.3.3.11
1815h-183Fh
RESERVED
1840h
SWE_GLB_INGRESS_CFG
Switch Engine Global Ingress Configuration Register,
Section 13.3.3.16
1841h
SWE_PORT_INGRESS_CFG
Switch Engine Port Ingress Configuration Register,
Section 13.3.3.17
1842h
SWE_ADMT_ONLY_VLAN
Switch Engine Admit Only VLAN Register, Section 13.3.3.18
DS00002288A-page 194
Reserved for Future Use
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
Register Name
1843h
SWE_PORT_STATE
1844h
RESERVED
1845h
SWE_PRI_TO_QUE
Switch Engine Port State Register, Section 13.3.3.19
Reserved for Future Use
1846h
SWE_PORT_MIRROR
1847h
SWE_INGRESS_PORT_TYP
Switch Engine Priority to Queue Register, Section 13.3.3.20
Switch Engine Port Mirroring Register, Section 13.3.3.21
Switch Engine Ingress Port Type Register, Section 13.3.3.22
1848h
SWE_BCST_THROT
Switch Engine Broadcast Throttling Register, Section 13.3.3.23
1849h
SWE_ADMT_N_MEMBER
Switch Engine Admit Non Member Register, Section 13.3.3.24
184Ah
SWE_INGRESS_RATE_CFG
Switch Engine Ingress Rate Configuration Register,
Section 13.3.3.25
184Bh
SWE_INGRESS_RATE_CMD
Switch Engine Ingress Rate Command Register,
Section 13.3.3.26
184Ch
SWE_INGRESS_RATE_CMD_STS
Switch Engine Ingress Rate Command Status Register,
Section 13.3.3.27
184Dh
SWE_INGRESS_RATE_WR_DATA
Switch Engine Ingress Rate Write Data Register,
Section 13.3.3.28
184Eh
SWE_INGRESS_RATE_RD_DATA
Switch Engine Ingress Rate Read Data Register,
Section 13.3.3.29
184Fh
RESERVED
1850h
SWE_FILTERED_CNT_MII
Switch Engine Port 0 Ingress Filtered Count Register,
Section 13.3.3.30
Reserved for Future Use
1851h
SWE_FILTERED_CNT_1
Switch Engine Port 1 Ingress Filtered Count Register,
Section 13.3.3.31
1852h
SWE_FILTERED_CNT_2
Switch Engine Port 2 Ingress Filtered Count Register,
Section 13.3.3.32
1853h-1854h
RESERVED
1855h
SWE_INGRESS_REGEN_TBL_MII
Reserved for Future Use
Switch Engine Port 0 Ingress VLAN Priority Regeneration
Register, Section 13.3.3.33
1856h
SWE_INGRESS_REGEN_TBL_1
Switch Engine Port 1 Ingress VLAN Priority Regeneration
Register, Section 13.3.3.34
1857h
SWE_INGRESS_REGEN_TBL_2
Switch Engine Port 2 Ingress VLAN Priority Regeneration
Register, Section 13.3.3.35
1858h
SWE_LRN_DISCRD_CNT_MII
Switch Engine Port 0 Learn Discard Count Register,
Section 13.3.3.36
1859h
SWE_LRN_DISCRD_CNT_1
Switch Engine Port 1 Learn Discard Count Register,
Section 13.3.3.37
185Ah
SWE_LRN_DISCRD_CNT_2
Switch Engine Port 2 Learn Discard Count Register,
Section 13.3.3.38
185Bh-187Fh
RESERVED
1880h
SWE_IMR
Switch Engine Interrupt Mask Register, Section 13.3.3.39
1881h
SWE_IPR
Switch Engine Interrupt Pending Register, Section 13.3.3.40
1882h-1BFFh
RESERVED
Reserved for Future Use
Reserved for Future Use
Buffer Manager (BM) CSRs
1C00h
BM_CFG
1C01h
BM_DROP_LVL
1C02h
BM_FC_PAUSE_LVL
1C03h
BM_FC_RESUME_LVL
1C04h
BM_BCST_LVL
2008-2016 Microchip Technology Inc.
Buffer Manager Configuration Register, Section 13.3.4.1
Buffer Manager Drop Level Register, Section 13.3.4.2
Buffer Manager Flow Control Pause Level Register,
Section 13.3.4.3
Buffer Manager Flow Control Resume Level Register,
Section 13.3.4.4
Buffer Manager Broadcast Buffer Level Register,
Section 13.3.4.5
DS00002288A-page 195
LAN9313/LAN9313i
TABLE 13-12: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Register #
Symbol
Register Name
1C05h
BM_DRP_CNT_SRC_MII
Buffer Manager Port 0 Drop Count Register, Section 13.3.4.6
1C06h
BM_DRP_CNT_SRC_1
Buffer Manager Port 1 Drop Count Register, Section 13.3.4.7
1C07h
BM_DRP_CNT_SRC_2
Buffer Manager Port 2 Drop Count Register, Section 13.3.4.8
1C08h
BM_RST_STS
1C09h
BM_RNDM_DSCRD_TBL_CMD
Buffer Manager Reset Status Register, Section 13.3.4.9
Buffer Manager Random Discard Table Command Register,
Section 13.3.4.10
1C0Ah
BM_RNDM_DSCRD_TBL_WDATA
Buffer Manager Random Discard Table Write Data Register,
Section 13.3.4.11
1C0Bh
BM_RNDM_DSCRD_TBL_RDATA
Buffer Manager Random Discard Table Read Data Register,
Section 13.3.4.12
1C0Ch
BM_EGRSS_PORT_TYPE
Buffer Manager Egress Port Type Register, Section 13.3.4.13
1C0Dh
BM_EGRSS_RATE_00_01
Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register,
Section 13.3.4.14
1C0Eh
BM_EGRSS_RATE_02_03
Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register,
Section 13.3.4.15
1C0Fh
BM_EGRSS_RATE_10_11
Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register,
Section 13.3.4.16
1C10h
BM_EGRSS_RATE_12_13
Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register,
Section 13.3.4.17
1C11h
BM_EGRSS_RATE_20_21
Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register,
Section 13.3.4.18
1C12h
BM_EGRSS_RATE_22_23
Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register,
Section 13.3.4.19
1C13h
BM_VLAN_MII
Buffer Manager Port 0 Default VLAN ID and Priority Register,
Section 13.3.4.20
1C14h
BM_VLAN_1
Buffer Manager Port 1 Default VLAN ID and Priority Register,
Section 13.3.4.21
1C15h
BM_VLAN_2
Buffer Manager Port 2 Default VLAN ID and Priority Register,
Section 13.3.4.22
1C16h
BM_RATE_DRP_CNT_SRC_MII
Buffer Manager Port 0 Ingress Rate Drop Count Register,
Section 13.3.4.23
1C17h
BM_RATE_DRP_CNT_SRC_1
Buffer Manager Port 1 Ingress Rate Drop Count Register,
Section 13.3.4.24
1C18h
BM_RATE_DRP_CNT_SRC_2
Buffer Manager Port 2 Ingress Rate Drop Count Register,
Section 13.3.4.25
1C19h-1C1Fh
RESERVED
Reserved for Future Use
1C20h
BM_IMR
Buffer Manager Interrupt Mask Register, Section 13.3.4.26
1C21h
BM_IPR
Buffer Manager Interrupt Pending Register, Section 13.3.4.27
1C22h-FFFFh
RESERVED
DS00002288A-page 196
Reserved for Future Use
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3.1
GENERAL SWITCH CSRS
This section details the general switch fabric CSRs. These registers control the main reset and interrupt functions of the
switch fabric. A list of the general switch CSRs and their corresponding register numbers is included in Table 13-12.
13.3.1.1
Switch Device ID Register (SW_DEV_ID)
Register #:
0000h
Size:
32 bits
This read-only register contains switch device ID information, including the device type, chip version and revision codes.
Bits
Description
Type
Default
31:24
RESERVED
RO
-
23:16
Device Type Code (DEVICE_TYPE)
RO
03h
15:8
Chip Version Code (CHIP_VERSION)
RO
04h
7:0
Revision Code (REVISION)
RO
07h
13.3.1.2
Switch Reset Register (SW_RESET)
Register #:
0001h
Size:
32 bits
This register contains the switch fabric global reset. Refer to Section 4.2, "Resets," on page 30 for more information.
Bits
31:1
0
13.3.1.3
Description
Type
Default
RESERVED
RO
-
Switch Fabric Reset (SW_RESET)
This bit is the global switch fabric reset. All switch fabric blocks are affected.
This bit must be manually cleared.
WO
0b
Switch Global Interrupt Mask Register (SW_IMR)
Register #:
0004h
Size:
32 bits
This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch related interrupts in
the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will unmask the interrupt. When an unmasked switch fabric interrupt is generated in the Switch Global Interrupt Pending Register (SW_IPR), the interrupt will trigger the SWITCH_INT
bit in the Interrupt Status Register (INT_STS). Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Bits
Description
Type
Default
31:9
RESERVED
RO
-
8:7
RESERVED
R/W
11b
R/W
1b
Note:
6
These bits must be written as 11b
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of switch fabric interrupts due to the
Buffer Manager via the Buffer Manager Interrupt Pending Register (BM_IPR).
The status bits in the SW_IPR register are not affected.
2008-2016 Microchip Technology Inc.
DS00002288A-page 197
LAN9313/LAN9313i
Bits
Description
Type
Default
5
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of switch fabric interrupts due to the
Switch Engine via the Switch Engine Interrupt Pending Register (SWE_IPR).
The status bits in the SW_IPR register are not affected.
R/W
1b
RESERVED
R/W
11b
4:3
Note:
These bits must be written as 11b
2
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of switch fabric interrupts due to the Port
2 MAC via the MAC_IPR_2 register (see Section 13.3.2.44, on page 216).
The status bits in the SW_IPR register are not affected.
R/W
1b
1
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of switch fabric interrupts due to the Port
1 MAC via the MAC_IPR_1 register (see Section 13.3.2.44, on page 216).
The status bits in the SW_IPR register are not affected.
R/W
1b
0
Port 0 MAC Interrupt Mask (MAC_MII)
When set, prevents the generation of switch fabric interrupts due to the Port
0 MAC via the MAC_IPR_MII register (see Section 13.3.2.44, on page 216).
The status bits in the SW_IPR register are not affected.
R/W
1b
13.3.1.4
Switch Global Interrupt Pending Register (SW_IPR)
Register #:
0005h
Size:
32 bits
This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates an unmasked bit
in the corresponding switch fabric sub-system has been triggered. All switch related interrupts in this register may be
masked via the Switch Global Interrupt Mask Register (SW_IMR) register. When an unmasked switch fabric interrupt is
generated in this register, the interrupt will trigger the SWITCH_INT bit in the Interrupt Status Register (INT_STS). Refer
to Section 5.0, "System Interrupts," on page 41 for more information.
Bits
31:7
Description
Type
Default
RESERVED
RO
-
6
Buffer Manager Interrupt (BM)
Set when any unmasked bit in the Buffer Manager Interrupt Pending Register
(BM_IPR) is triggered. This bit is cleared upon a read.
RC
0b
5
Switch Engine Interrupt (SWE)
Set when any unmasked bit in the Switch Engine Interrupt Pending Register
(SWE_IPR) is triggered. This bit is cleared upon a read.
RC
0b
RESERVED
RO
-
2
Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see Section
13.3.2.44, on page 216) is triggered. This bit is cleared upon a read.
RC
0b
1
Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see Section
13.3.2.44, on page 216) is triggered. This bit is cleared upon a read.
RC
0b
0
Port 0 MAC Interrupt (MAC_MII)
Set when any unmasked bit in the MAC_IPR_MII register (see Section
13.3.2.44, on page 216) is triggered. This bit is cleared upon a read.
RC
0b
4:3
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LAN9313/LAN9313i
13.3.2
SWITCH PORT 0, PORT 1, AND PORT 2 CSRS
This section details the switch Port 0(External MII), Port 1, and Port 2 CSRs. Each port provides a functionally identical
set of registers which allow for the configuration of port settings, interrupts, and the monitoring of the various packet
counters.
Because the Port 0, Port 1, and Port 2 CSRs are functionally identical, their register descriptions have been consolidated. A lowercase “x” has been appended to the end of each switch port register name in this section, where “x” should
be replaced with “MII”, “1”, or “2” for the Port 0, Port 1, or Port 2 registers respectively. A list of the Switch Port 0, Port
1, and Port 2 registers and their corresponding register numbers is included in Table 13-12.
13.3.2.1
Port x MAC Version ID Register (MAC_VER_ID_x)
Register #:
Port0: 0400h
Port1: 0800h
Port2: 0C00h
Size:
32 bits
This read-only register contains switch device ID information, including the device type, chip version and revision codes.
Bits
Type
Default
RESERVED
RO
-
11:8
Device Type Code (DEVICE_TYPE)
RO
5h
7:4
Chip Version Code (CHIP_VERSION)
RO
8h
3:0
Revision Code (REVISION)
RO
3h
Type
Default
31:12
13.3.2.2
Description
Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
Register #:
Port0: 0401h
Port1: 0801h
Port2: 0C01h
Size:
32 bits
This read/write register configures the packet type passing parameters of the port.
Bits
Description
31:8
RESERVED
RO
-
7
RESERVED
R/W
0b
Note:
This bit must always be written as 0.
6
RESERVED
RO
-
5
Enable Receive Own Transmit
When set, the switch port will receive its own transmission if it is looped back
from the PHY. Normally, this function is only used in Half Duplex PHY
loopback.
R/W
0b
4
RESERVED
RO
-
3
Jumbo2K
When set, the maximum packet size accepted is 2048 bytes. Statistics
boundaries are also adjusted.
R/W
0b
2
RESERVED
RO
-
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DS00002288A-page 199
LAN9313/LAN9313i
Bits
Description
Type
Default
1
Reject MAC Types
When set, MAC control frames (packets with a type field of 8808h) are
filtered. When cleared, MAC Control frames, other than MAC Control Pause
frames, are sent to the forwarding process. MAC Control Pause frames are
always consumed by the switch.
R/W
1b
0
RX Enable
When set, the receive port is enabled. When cleared, the receive port is
disabled.
R/W
1b
13.3.2.3
Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x)
Register #:
Port0: 0410h
Port1: 0810h
Port2: 0C10h
Size:
32 bits
This register provides a counter of undersized packets received by the port. The counter is cleared upon being read.
Bits
31:0
Description
RX Undersize
Count of packets that have less than 64 byte and a valid FCS.
Note:
13.3.2.4
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 115 hours.
Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x)
Register #:
Port0: 0411h
Port1: 0811h
Port2: 0C11h
Size:
32 bits
This register provides a counter of 64 byte packets received by the port. The counter is cleared upon being read.
Bits
31:0
Description
RX 64 Bytes
Count of packets (including bad packets) that have exactly 64 bytes.
Note:
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not
an integral number of bytes is rounded down to the nearest byte.
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LAN9313/LAN9313i
13.3.2.5
Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)
Register #:
Port0: 0412h
Port1: 0812h
Port2: 0C12h
Size:
32 bits
This register provides a counter of received packets between the size of 65 to 127 bytes. The counter is cleared upon
being read.
Bits
31:0
Description
RX 65 to 127 Bytes
Count of packets (including bad packets) that have between 65 and 127
bytes.
Note:
Note:
13.3.2.6
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 487 hours.
A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not
an integral number of bytes is rounded down to the nearest byte.
Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)
Register #:
Port0: 0413h
Port1: 0813h
Port2: 0C13h
Size:
32 bits
This register provides a counter of received packets between the size of 128 to 255 bytes. The counter is cleared upon
being read.
Bits
31:0
Description
RX 128 to 255 Bytes
Count of packets (including bad packets) that have between 128 and 255
bytes.
Note:
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 848 hours.
A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not
an integral number of bytes is rounded down to the nearest byte.
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DS00002288A-page 201
LAN9313/LAN9313i
13.3.2.7
Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)
Register #:
Port0: 0414h
Port1: 0814h
Port2: 0C14h
Size:
32 bits
This register provides a counter of received packets between the size of 256 to 511 bytes. The counter is cleared upon
being read.
Bits
31:0
Description
RX 256 to 511 Bytes
Count of packets (including bad packets) that have between 256 and 511
bytes.
Note:
Note:
13.3.2.8
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 1581 hours.
A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not
an integral number of bytes is rounded down to the nearest byte.
Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)
Register #:
Port0: 0415h
Port1: 0815h
Port2: 0C15h
Size:
32 bits
This register provides a counter of received packets between the size of 512 to 1023 bytes. The counter is cleared upon
being read.
Bits
Description
Type
Default
31:0
RX 512 to 1023 Bytes
Count of packets (including bad packets) that have between 512 and 1023
bytes.
RC
00000000h
Note:
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 3047 hours.
A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not
an integral number of bytes is rounded down to the nearest byte.
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LAN9313/LAN9313i
13.3.2.9
Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x)
Register #:
Port0: 0416h
Port1: 0816h
Port2: 0C16h
Size:
32 bits
This register provides a counter of received packets between the size of 1024 to the maximum allowable number bytes.
The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
RX 1024 to Max Bytes
Count of packets (including bad packets) that have between 1024 and the
maximum allowable number of bytes. The max number of bytes is 1518 for
untagged packets and 1522 for tagged packets. If Jumbo2K (bit 3) is set in
the Port x MAC Receive Configuration Register (MAC_RX_CFG_x), the max
number of bytes is 2048.
RC
00000000h
Note:
Note:
13.3.2.10
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 5979 hours.
A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet with the
maximum number of bytes that is not an integral number of bytes (e.g. a 1518 1/2 byte packet) is counted.
Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x)
Register #:
Port0: 0417h
Port1: 0817h
Port2: 0C17h
Size:
32 bits
This register provides a counter of received packets with a size greater than the maximum byte size. The counter is
cleared upon being read.
Bits
Description
Type
Default
31:0
RX Oversize
Count of packets that have more than the maximum allowable number of
bytes and a valid FCS. The max number of bytes is 1518 for untagged
packets and 1522 for tagged packets. If Jumbo2K (bit 3) is set in the Port x
MAC Receive Configuration Register (MAC_RX_CFG_x), the max number of
bytes is 2048.
RC
00000000h
Note:
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 8813 hours.
For this counter, a packet with the maximum number of bytes that is not an integral number of bytes (e.g.
a 1518 1/2 byte packet) is not considered oversize.
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DS00002288A-page 203
LAN9313/LAN9313i
13.3.2.11
Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)
Register #:
Port0: 0418h
Port1: 0818h
Port2: 0C18h
Size:
32 bits
This register provides a counter of received packets that are or proper length and are free of errors. The counter is
cleared upon being read.
Bits
31:0
Description
RX OK
Count of packets that are of proper length and are free of errors.
Note:
Note:
13.3.2.12
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
A bad packet is one that has a FCS or Symbol error.
Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x)
Register #:
Port0: 0419h
Port1: 0819h
Port2: 0C19h
Size:
32 bits
This register provides a counter of received packets that with CRC errors. The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
RX CRC
Count of packets that have between 64 and the maximum allowable number
of bytes and have a bad FCS, but do not have an extra nibble. The max
number of bytes is 1518 for untagged packets and 1522 for tagged packets.
If Jumbo2K (bit 3) is set in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x), the max number of bytes is 2048.
RC
00000000h
Note:
13.3.2.13
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 137 hours.
Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x)
Register #:
Port0: 041Ah
Port1: 081Ah
Port2: 0C1Ah
Size:
32 bits
This register provides a counter of valid received packets with a multicast destination address. The counter is cleared
upon being read.
Bits
31:0
Description
RX Multicast
Count of good packets (proper length and free of errors), including MAC
control frames, that have a multicast destination address (not including
broadcasts).
Note:
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
A bad packet is one that has a FCS or Symbol error.
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LAN9313/LAN9313i
13.3.2.14
Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x)
Register #:
Port0: 041Bh
Port1: 081Bh
Port2: 0C1Bh
Size:
32 bits
This register provides a counter of valid received packets with a broadcast destination address. The counter is cleared
upon being read.
Bits
31:0
Description
RX Broadcast
Count of valid packets (proper length and free of errors) that have a
broadcast destination address.
Note:
Note:
13.3.2.15
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
A bad packet is one that has a FCS or Symbol error.
Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x)
Register #:
Port0: 041Ch
Port1: 081Ch
Port2: 0C1Ch
Size:
32 bits
This register provides a counter of valid received pause frame packets. The counter is cleared upon being read.
Bits
31:0
Description
RX Pause Frame
Count of valid packets (proper length and free of errors) that have a type
field of 8808h and an op-code of 0001(Pause).
Note:
Note:
13.3.2.16
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
A bad packet is one that has a FCS or Symbol error.
Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)
Register #:
Port0: 041Dh
Port1: 081Dh
Port2: 0C1Dh
Size:
32 bits
This register provides a counter of received packets of less than 64 bytes and a FCS error. The counter is cleared upon
being read.
Bits
31:0
Description
RX Fragment
Count of packets that have less than 64 bytes and a FCS error.
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 115 hours.
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DS00002288A-page 205
LAN9313/LAN9313i
13.3.2.17
Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x)
Register #:
Port0: 041Eh
Port1: 081Eh
Port2: 0C1Eh
Size:
32 bits
This register provides a counter of received packets with greater than the maximum allowable number of bytes and a
FCS error. The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
RX Jabber
Count of packets that have more than the maximum allowable number of
bytes and a FCS error. The max number of bytes is 1518 for untagged
packets and 1522 for tagged packets. If Jumbo2K (bit 3) is set in the Port x
MAC Receive Configuration Register (MAC_RX_CFG_x), the max number of
bytes is 2048.
RC
00000000h
Note:
Note:
13.3.2.18
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 8813 hours.
For this counter, a packet with the maximum number of bytes that is not an integral number of bytes (e.g.
a 1518 1/2 byte packet) and contains a FCS error is not considered jabber and is not counted here.
Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x)
Register #:
Port0: 041Fh
Port1: 081Fh
Port2: 0C1Fh
Size:
32 bits
This register provides a counter of received packets with 64 bytes to the maximum allowable, and a FCS error. The
counter is cleared upon being read.
Bits
Description
Type
Default
31:0
RX Alignment
Count of packets that have between 64 bytes and the maximum allowable
number of bytes and are not byte aligned and have a bad FCS. The max
number of bytes is 1518 for untagged packets and 1522 for tagged packets.
If Jumbo2K (bit 3) is set in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x), the max number of bytes is 2048.
RC
00000000h
Note:
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
For this counter, a packet with the maximum number of bytes that is not an integral number of bytes (e.g.
a 1518 1/2 byte packet) and a FCS error is considered an alignment error and is counted.
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LAN9313/LAN9313i
13.3.2.19
Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x)
Register #:
Port0: 0420h
Port1: 0820h
Port2: 0C20h
Size:
32 bits
This register provides a counter of total bytes received. The counter is cleared upon being read.
Bits
31:0
Description
RX Bytes
Count of total bytes received (including bad packets).
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 5.8 hours.
Note:
• If necessary, for oversized packets, the packet is either truncated at 1518 bytes (untagged, Jumbo2K=0), 1522
bytes (tagged, Jumbo2K=0), or 2048 bytes (Jumbo2K=1). If this occurs, the byte count recorded is 1518, 1522,
or 2048, respectively. The Jumbo2K bit is located in the Port x MAC Receive Configuration Register (MAC_RX_CFG_x).
• A bad packet is one that has an FCS or Symbol error. For this counter, a packet that is not an integral number of
bytes (e.g. a 1518 1/2 byte packet) is rounded down to the nearest byte.
13.3.2.20
Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x)
Register #:
Port0: 0421h
Port1: 0821h
Port2: 0C21h
Size:
32 bits
This register provides a counter of total bytes received in good packets. The counter is cleared upon being read.
Bits
31:0
Description
RX Good Bytes
Count of total bytes received in good packets (proper length and free of
errors).
Note:
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 5.8 hours.
A bad packet is one that has an FCS or Symbol error.
2008-2016 Microchip Technology Inc.
DS00002288A-page 207
LAN9313/LAN9313i
13.3.2.21
Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x)
Register #:
Port0: 0422h
Port1: 0822h
Port2: 0C22h
Size:
32 bits
This register provides a counter of received packets with a symbol error. The counter is cleared upon being read.
Bits
31:0
Description
RX Symbol
Count of packets that had a receive symbol error.
Note:
13.3.2.22
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 115 hours.
Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x)
Register #:
Port0: 0423h
Port1: 0823h
Port2: 0C23h
Size:
32 bits
This register provides a counter of good packets with a type field of 8808h. The counter is cleared upon being read.
Bits
31:0
Description
Type
Default
RC
00000000h
Type
Default
RESERVED
RO
-
MAC Counter Test
When set, TX and RX counters that normally clear to 0 when read, will be
set to 7FFF_FFFCh when read with the exception of the Port x MAC Receive
Packet Length Count Register (MAC_RX_PKTLEN_CNT_x), Port x MAC
Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x), and
Port x MAC Receive Good Packet Length Count Register
(MAC_RX_GOODPKTLEN_CNT_x) counters which will be set to
7FFF_FF80h.
R/W
0b
RX Control Frame
Count of good packets (proper length and free of errors) that have a type
field of 8808h.
Note:
Note:
13.3.2.23
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
A bad packet is one that has an FCS or Symbol error.
Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
Register #:
Port0: 0440h
Port1: 0840h
Port2: 0C40h
Size:
32 bits
This read/write register configures the transmit packet parameters of the port.
Bits
31:8
7
Description
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LAN9313/LAN9313i
Bits
6:2
Description
IFG Config
These bits control the transmit inter-frame gap.
IFG bit times = (IFG Config *4) + 12
Note:
Type
Default
R/W
10101b
IFG Config values less than 15 are unsupported.
1
TX Pad Enable
When set, packets shorter than 64 bytes are padded with zeros if needed
and a FCS is appended. Packets that are 60 bytes or less will become 64
bytes. Packets that are 61, 62, and 63 bytes will become 65, 66, and 67
bytes respectively.
R/W
1b
0
TX Enable
When set, the transmit port is enabled. When cleared, the transmit port is
disabled.
R/W
1b
13.3.2.24
Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x)
Register #:
Port0: 0441h
Port1: 0841h
Port2: 0C41h
Size:
32 bits
This read/write register configures the flow control settings of the port.
Bits
Description
Type
Default
31:18
RESERVED
RO
-
17:16
Backoff Reset RX/TX
Half duplex-only. Determines when the truncated binary exponential backoff
attempts counter is reset.
R/W
00b
R/W
FFFFh
00 = Reset on successful transmission (IEEE standard)
01 = Reset on successful reception
1X = Reset on either successful transmission or reception
15:0
13.3.2.25
Pause Time Value
The value that is inserted into the transmitted pause packet when the switch
wants to “XOFF” its link partner.
Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)
Register #:
Port0: 0451h
Port1: 0851h
Port2: 0C51h
Size:
32 bits
This register provides a counter deferred packets. The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
TX Deferred
Count of packets that were available for transmission but were deferred on
the first transmit attempt due to network traffic (either on receive or prior
transmission). This counter is not incremented on collisions. This counter is
incremented only in half-duplex operation.
RC
00000000h
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
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DS00002288A-page 209
LAN9313/LAN9313i
13.3.2.26
Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)
Register #:
Port0: 0452h
Port1: 0852h
Port2: 0C52h
Size:
32 bits
This register provides a counter of transmitted pause packets. The counter is cleared upon being read.
Bits
31:0
Description
TX Pause
Count of pause packets transmitted.
Note:
13.3.2.27
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x)
Register #:
Port0: 0453h
Port1: 0853h
Port2: 0C53h
Size:
32 bits
This register provides a counter of successful transmissions. The counter is cleared upon being read.
Bits
31:0
Description
TX OK
Count of successful transmissions. Undersize packets are not included in
this count.
Note:
13.3.2.28
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x)
Register #:
Port0: 0454h
Port1: 0854h
Port2: 0C54h
Size:
32 bits
This register provides a counter of 64 byte packets transmitted by the port. The counter is cleared upon being read.
Bits
31:0
Description
TX 64 Bytes
Count of packets that have exactly 64 bytes.
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
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LAN9313/LAN9313i
13.3.2.29
Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x)
Register #:
Port0: 0455h
Port1: 0855h
Port2: 0C55h
Size:
32 bits
This register provides a counter of transmitted packets between the size of 65 to 127 bytes. The counter is cleared upon
being read.
Bits
31:0
Description
TX 65 to 127 Bytes
Count of packets that have between 65 and 127 bytes.
Note:
13.3.2.30
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 487 hours.
Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x)
Register #:
Port0: 0456h
Port1: 0856h
Port2: 0C56h
Size:
32 bits
This register provides a counter of transmitted packets between the size of 128 to 255 bytes. The counter is cleared
upon being read.
Bits
31:0
Description
TX 128 to 255 Bytes
Count of packets that have between 128 and 255 bytes.
Note:
13.3.2.31
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 848 hours.
Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x)
Register #:
Port0: 0457h
Port1: 0857h
Port2: 0C57h
Size:
32 bits
This register provides a counter of transmitted packets between the size of 256 to 511 bytes. The counter is cleared
upon being read.
Bits
31:0
Description
TX 256 to 511 Bytes
Count of packets that have between 256 and 511 bytes.
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 1581 hours.
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LAN9313/LAN9313i
13.3.2.32
Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x)
Register #:
Port0: 0458h
Port1: 0858h
Port2: 0C58h
Size:
32 bits
This register provides a counter of transmitted packets between the size of 512 to 1023 bytes. The counter is cleared
upon being read.
Bits
31:0
Description
TX 512 to 1023 Bytes
Count of packets that have between 512 and 1023 bytes.
Note:
13.3.2.33
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 3047 hours.
Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)
Register #:
Port0: 0459h
Port1: 0859h
Port2: 0C59h
Size:
32 bits
This register provides a counter of transmitted packets between the size of 1024 to the maximum allowable number
bytes. The counter is cleared upon being read.
Bits
31:0
Description
TX 1024 to Max Bytes
Count of packets that have more than 1024 bytes.
Note:
13.3.2.34
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 5979 hours.
Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x)
Register #:
Port0: 045Ah
Port1: 085Ah
Port2: 0C5Ah
Size:
32 bits
This register provides a counter of undersized packets transmitted by the port. The counter is cleared upon being read.
Bits
31:0
Description
TX Undersize
Count of packets that have less than 64 bytes.
Note:
This condition could occur when TX padding is disabled and a tag
is removed.
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 458 hours.
DS00002288A-page 212
Type
Default
RC
00000000h
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3.2.35
Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x)
Register #:
Port0: 045Ch
Port1: 085Ch
Port2: 0C5Ch
Size:
32 bits
This register provides a counter of total bytes transmitted. The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
TX Bytes
Count of total bytes transmitted (does not include bytes from collisions, but
does include bytes from Pause packets).
RC
00000000h
Note:
13.3.2.36
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 5.8 hours.
Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x)
Register #:
Port0: 045Dh
Port1: 085Dh
Port2: 0C5Dh
Size:
32 bits
This register provides a counter of transmitted broadcast packets. The counter is cleared upon being read.
Bits
31:0
Description
TX Broadcast
Count of broadcast packets transmitted.
Note:
13.3.2.37
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x)
Register #:
Port0: 045Eh
Port1: 085Eh
Port2: 0C5Eh
Size:
32 bits
This register provides a counter of transmitted multicast packets. The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
TX Multicast
Count of multicast packets transmitted including MAC Control Pause frames.
RC
00000000h
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
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LAN9313/LAN9313i
13.3.2.38
Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x)
Register #:
Port0: 045Fh
Port1: 085Fh
Port2: 0C5Fh
Size:
32 bits
This register provides a counter of transmitted packets which experienced a late collision. The counter is cleared upon
being read.
Bits
Description
Type
Default
31:0
TX Late Collision
Count of transmitted packets that experienced a late collision. This counter
is incremented only in half-duplex operation.
RC
00000000h
Note:
13.3.2.39
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)
Register #:
Port0: 0460h
Port1: 0860h
Port2: 0C60h
Size:
32 bits
This register provides a counter of transmitted packets which experienced 16 collisions. The counter is cleared upon
being read.
Bits
Description
Type
Default
31:0
TX Excessive Collision
Count of transmitted packets that experienced 16 collisions. This counter is
incremented only in half-duplex operation.
RC
00000000h
Note:
13.3.2.40
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 1466 hours.
Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x)
Register #:
Port0: 0461h
Port1: 0861h
Port2: 0C61h
Size:
32 bits
This register provides a counter of transmitted packets which experienced exactly 1 collision. The counter is cleared
upon being read.
Bits
31:0
Description
TX Excessive Collision
Count of transmitted packets that experienced exactly 1 collision. This
counter is incremented only in half-duplex operation.
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 573 hours.
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LAN9313/LAN9313i
13.3.2.41
Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x)
Register #:
Port0: 0462h
Port1: 0862h
Port2: 0C62h
Size:
32 bits
This register provides a counter of transmitted packets which experienced between 2 and 15 collisions. The counter is
cleared upon being read.
Bits
Description
Type
Default
31:0
TX Excessive Collision
Count of transmitted packets that experienced between 2 and 15 collisions.
This counter is incremented only in half-duplex operation.
RC
00000000h
Note:
13.3.2.42
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 664 hours.
Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)
Register #:
Port0: 0463h
Port1: 0863h
Port2: 0C63h
Size:
32 bits
This register provides a counter of total collisions including late collisions. The counter is cleared upon being read.
Bits
Description
Type
Default
31:0
TX Total Collision
Total count of collisions including late collisions. This counter is incremented
only in half-duplex operation.
RC
00000000h
Note:
13.3.2.43
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 92 hours.
Port x MAC Interrupt Mask Register (MAC_IMR_x)
Register #:
Port0: 0480h
Port1: 0880h
Port2: 0C80h
Size:
32 bits
This register contains the Port x interrupt mask. Port x related interrupts in the Port x MAC Interrupt Pending Register
(MAC_IPR_x) may be masked via this register. An interrupt is masked by setting the corresponding bit of this register.
Clearing a bit will unmask the interrupt. Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Note:
There are no possible Port x interrupt conditions available. This register exists for future use, and should
be configured as indicated for future compatibility.
Bits
Description
Type
Default
31:8
RESERVED
RO
-
7:0
RESERVED
R/W
11h
Note:
These bits must be written as 11h
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LAN9313/LAN9313i
13.3.2.44
Port x MAC Interrupt Pending Register (MAC_IPR_x)
Register #:
Port0: 0481h
Port1: 0881h
Port2: 0C81h
Size:
32 bits
This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been triggered. All interrupts in this register may be masked via the Port x MAC Interrupt Pending Register (MAC_IPR_x) register. Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Note:
There are no possible Port x interrupt conditions available. This register exists for future use.
Bits
31:0
13.3.3
Description
RESERVED
Type
Default
RO
-
SWITCH ENGINE CSRS
This section details the switch engine related CSRs. These registers allow configuration and monitoring of the various
switch engine components including the ALR, VLAN, Port VID, and DIFFSERV tables. A list of the general switch CSRs
and their corresponding register numbers is included in Table 13-12.
13.3.3.1
Switch Engine ALR Command Register (SWE_ALR_CMD)
Register #:
1800h
Size:
32 bits
This register is used to manually read and write MAC addresses from/into the ALR table.
For a read access, the Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) and Switch Engine ALR
Read Data 1 Register (SWE_ALR_RD_DAT_1) should be read following the setting of bit 1(Get First Entry) or bit 0(Get
Next Entry) of this register.
For write access, the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and Switch Engine ALR Write
Data 1 Register (SWE_ALR_WR_DAT_1) registers should first be written with the MAC address, followed by the setting
of bit 2(Make Entry) of this register. The Make Pending bit in the Switch Engine ALR Command Status Register
(SWE_ALR_CMD_STS) register indicates when the command is finished.
Refer to Section 6.0, "Switch Fabric," on page 45 for more information.
Bits
Type
Default
RESERVED
RO
-
2
Make Entry
When set, the contents of ALR_WR_DAT_0 and ALR_WR_DAT_1 are
written into the ALR table. The ALR logic determines the location where the
entry is written. This command can also be used to change or delete a
previously written or automatically learned entry. This bit has no affect when
written low. This bit must be cleared once the ALR Make command is
completed, which can be determined by the ALR Status bit in the Switch
Engine ALR Command Status Register (SWE_ALR_CMD_STS) register.
R/W
0b
1
Get First Entry
When set, the ALR read pointer is reset to the beginning of the ALR table
and the ALR table is searched for the first valid entry, which is loaded into
the ALR_RD_DAT_0 and ALR_RD_DAT_1 registers. The bit has no affect
when written low. This bit must be cleared after it is set.
R/W
0b
0
Get Next Entry
When set, the next valid entry in the ALR MAC address table is loaded into
the ALR_RD_DAT_0 and ALR_RD_DAT_1 registers. This bit has no affect
when written low. This bit must be cleared after it is set.
R/W
0b
31:3
Description
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LAN9313/LAN9313i
13.3.3.2
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)
Register #:
1801h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) and
contains the first 32 bits of ALR data to be manually written via the Make Entry command in the Switch Engine ALR
Command Register (SWE_ALR_CMD).
Bits
Description
Type
Default
31:0
MAC Address
This field contains the first 32 bits of the ALR entry that will be written into
the ALR table. These bits correspond to the first 32 bits of the MAC address.
Bit 0 holds the LSB of the first byte (the multicast bit).
R/W
00000000h
13.3.3.3
Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
Register #:
1802h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and
contains the last 32 bits of ALR data to be manually written via the Make Entry command in the Switch Engine ALR
Command Register (SWE_ALR_CMD).
Bits
31:25
Description
Type
Default
RESERVED
RO
-
24
Valid
When set, this bit makes the entry valid. It can be cleared to invalidate a
previous entry that contained the specified MAC address.
R/W
0b
23
Age/Override
This bit is used by the aging and forwarding processes.
R/W
0b
R/W
0b
Filter
When set, packets with a destination address that matches this MAC
address will be filtered.
R/W
0b
Priority
These bits specify the priority that is used for packets with a destination
address that matches this MAC address. This priority is only used if the
Static bit of this register is set, and the DA Highest Priority (bit 5) in the
Switch Engine Global Ingress Configuration Register
(SWE_GLOBAL_INGRSS_CFG) is set.
R/W
00b
If the Static bit of this register is cleared, this bit should be set so that the
entry will age in the normal amount of time.
If the Static bit is set, this bit is used as a port state override bit. When set,
packets received with a destination address that matches the MAC address
in the SWE_ALR_WR_DAT_1 and SWE_ALR_WR_DAT_0 registers will be
forwarded regardless of the port state of the ingress or egress port(s). This
is typically used to allow the reception of BPDU packets in the nonforwarding state.
22
Static
When this bit is set, this entry will not be removed by the aging process
and/or be changed by the learning process. When this bit is cleared, this
entry will be automatically removed after 5 to 10 minutes of inactivity.
Inactivity is defined as no packets being received with a source address that
matches this MAC address.
Note:
21
20:19
This bit is normally set when adding manual entries. It must be
cleared when removing an entry (clearing the Valid bit).
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LAN9313/LAN9313i
Bits
Description
Type
Default
18:16
Port
These bits indicate the port(s) associated with this MAC address. When bit
18 is cleared, a single port is selected. When bit 18 is set, multiple ports are
selected.
R/W
000b
R/W
0000h
15:0
13.3.3.4
VALUE
ASSOCIATED PORT(S)
000
Port 0(External MII)
001
Port 1
010
Port 2
011
RESERVED
100
Port 0(External MII) and Port 1
101
Port 0(External MII) and Port 2
110
Port 1 and Port 2
111
Port 0(External MII), Port 1, and Port 2
MAC Address
These field contains the last 16 bits of the ALR entry that will be written into
the ALR table. They correspond to the last 16 bits of the MAC address. Bit
15 holds the MSB of the last byte (the last bit on the wire). The first 32 bits
of the MAC address are located in the Switch Engine ALR Write Data 0
Register (SWE_ALR_WR_DAT_0).
Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
Register #:
1805h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) to read
the ALR table. It contains the first 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register (SWE_ALR_CMD). This register is only valid when either of the
Valid or End of Table bits in the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) are set.
Bits
Description
Type
Default
31:0
MAC Address
This field contains the first 32 bits of the ALR entry. These bits correspond
to the first 32 bits of the MAC address. Bit 0 holds the LSB of the first byte
(the multicast bit).
RO
00000000h
DS00002288A-page 218
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LAN9313/LAN9313i
13.3.3.5
Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
Register #:
1806h
Size:
32 bits
This register is used in conjunction with the Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) to read
the ALR table. It contains the last 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register (SWE_ALR_CMD). This register is only valid when either of the
Valid or End of Table bits are set.
Bits
31:25
Description
Type
Default
RESERVED
RO
-
24
Valid
This bit is cleared when the Get First Entry or Get Next Entry bits of the
Switch Engine ALR Command Register (SWE_ALR_CMD) are written. This
bit is set when a valid entry is found in the ALR table. This bit stays cleared
when the top of the ALR table is reached without finding an entry.
RO
0b
23
End of Table
This bit indicates that the end of the ALR table has been reached and further
Get Next Entry commands are not required.
RO
0b
Note:
The Valid bit may or may not be set when the end of the table is
reached.
22
Static
Indicates that this entry will not be removed by the aging process. When this
bit is cleared, this entry will be automatically removed after 5 to 10 minutes
of inactivity. Inactivity is defined as no packets being received with a source
address that matches this MAC address.
RO
0b
21
Filter
When set, indicates that packets with a destination address that matches this
MAC address will be filtered.
RO
0b
Priority
These bits indicate the priority that is used for packets with a destination
address that matches this MAC address. This priority is only used if the
Static bit of this register is set, and the DA Highest Priority (bit 5) in the
Switch Engine Global Ingress Configuration Register
(SWE_GLOBAL_INGRSS_CFG) register is set.
RO
00b
20:19
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DS00002288A-page 219
LAN9313/LAN9313i
Bits
Description
Type
Default
18:16
Port
These bits indicate the port(s) associated with this MAC address. When bit
18 is cleared, a single port is selected. When bit 18 is set, multiple ports are
selected.
RO
000b
RO
0000h
Type
Default
15:0
13.3.3.6
VALUE
ASSOCIATED PORT(S)
000
Port 0(External MII)
001
Port 1
010
Port 2
011
RESERVED
100
Port 0(External MII) and Port 1
101
Port 0(External MII) and Port 2
110
Port 1 and Port 2
111
Port 0(External MII), Port 1, and Port 2
MAC Address
These field contains the last 16 bits of the ALR entry. They correspond to
the last 16 bits of the MAC address. Bit 15 holds the MSB of the last byte
(the last bit on the wire). The first 32 bits of the MAC address are located in
the Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0).
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
Register #:
1808h
Size:
32 bits
This register indicates the current ALR command status.
Bits
31:2
Description
RESERVED
RO
-
1
ALR Init Done
When set, indicates that the ALR table has finished being initialized by the
reset process. The initialization is performed upon any reset that resets the
switch fabric. The initialization takes approximately 20uS. During this time,
any received packet will be dropped. Software should monitor this bit before
writing any of the ALR tables or registers.
RO
SS
Note 13-64
0
Make Pending
When set, indicates that the Make Entry command is taking place. This bit
is cleared once the Make Entry command has finished.
RO
SC
0b
Note 13-64 The default value of this bit is 0 immediately following any switch fabric reset and then self-sets to 1
once the ALR table is initialized.
DS00002288A-page 220
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LAN9313/LAN9313i
13.3.3.7
Switch Engine ALR Configuration Register (SWE_ALR_CFG)
Register #:
1809h
Size:
32 bits
This register controls the ALR aging timer duration.
Bits
31:1
0
13.3.3.8
Description
Type
Default
RESERVED
RO
-
ALR Age Test
When set, this bit decreases the aging timer from 5 minutes to 50mS.
R/W
0b
Switch Engine VLAN Command Register (SWE_VLAN_CMD)
Register #:
180Bh
Size:
32 bits
This register is used to read and write the VLAN or Port VID tables. A write to this address performs the specified access.
For a read access, the Operation Pending bit in the Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) indicates when the command is finished. The Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) can then be read.
For a write access, the Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA) register should be written
first. The Operation Pending bit in the Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) indicates when the command is finished.
Bits
Type
Default
RESERVED
RO
-
5
VLAN RnW
This bit specifies a read(1) or a write(0) command.
R/W
0b
4
PVIDnVLAN
When set, this bit selects the Port VID table. When cleared, this bit selects
the VLAN table.
R/W
0b
VLAN/Port
This field specifies the VLAN(0-15) or port(0-2) to be read or written.
R/W
0h
31:6
3:0
Description
Note:
Values outside of the valid range may cause unexpected results.
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LAN9313/LAN9313i
13.3.3.9
Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA)
Register #:
180Ch
Size:
32 bits
This register is used write the VLAN or Port VID tables.
Bits
Description
Type
Default
31:18
RESERVED
RO
-
17:0
Port Default VID and Priority
When the port VID table is selected (PVIDnVLAN=1 of the Switch Engine
VLAN Command Register (SWE_VLAN_CMD)), bits 11:0 of this field specify
the default VID for the port and bits 14:12 specify the default priority. All other
bits of this field are reserved. These bits are used when a packet is received
without a VLAN tag or with a NULL VLAN ID. By default, the VID and priority
for all three ports is 0.
R/W
0b
Values of 0 and FFFh should not be used since they are special
VLAN IDs per the IEEE 802.3Q specification.
VLAN Data
When the VLAN table is selected (PVIDnVLAN=0 of the Switch Engine VLAN
Command Register (SWE_VLAN_CMD)), the bits form the VLAN table entry
as follows:
Note:
BITS
17
DESCRIPTION
Member Port 2
DEFAULT
0b
Indicates the configuration of Port 2 for this VLAN entry.
1 = Member - Packets with a VID that matches this entry
are allowed on ingress. The port is a member of the
broadcast domain on egress.
0 = Not a Member - Packets with a VID that matches this
entry are filtered on ingress unless the Admit Non Member
bit in the Switch Engine Admit Non Member Register
(SWE_ADMT_N_MEMBER) is set for this port. The port is
not a member of the broadcast domain on egress.
16
Un-Tag Port 2
0b
When this bit is set, packets received on Port 2 with a VID
that matches this entry will have their tag removed when retransmitted by egress ports that are designated as Hybrid
ports via the Buffer Manager Egress Port Type Register
(BM_EGRSS_PORT_TYPE).
15
Member Port 1
0b
See description for Member Port 2.
14
Un-Tag Port 1
0b
See description for Un-Tag Port 2.
13
Member Port 0 (External MII)
0b
See description for Member Port 2.
12
Un-Tag Port 0 (External MII)
0b
See description for Un-Tag Port 2.
11:0
VID
000h
These bits specify the VLAN ID associated with this VLAN
entry.
To disable a VLAN entry, a value of 0 should be used.
Note:
A value of 0 is considered a NULL VLAN and
should not normally be used other than to
disable a VLAN entry.
Note:
DS00002288A-page 222
A value of 3FFh is considered reserved by IEEE
802.1Q and should not be used.
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3.3.10
Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA)
Register #:
180Eh
Size:
32 bits
This register is used to read the VLAN or Port VID tables.
Bits
Description
Type
Default
31:18
RESERVED
RO
-
17:0
Port Default VID and Priority
When the port VID table is selected (PVIDnVLAN=1 of the Switch Engine
VLAN Command Register (SWE_VLAN_CMD)), bits 11:0 of this field specify
the default VID for the port and bits 14:12 specify the default priority. All other
bits of this field are reserved. These bits are used when a packet is received
without a VLAN tag or with a NULL VLAN ID. By default, the VID and priority
for all three ports is 0.
RO
00000h
VLAN Data
When the VLAN table is selected (PVIDnVLAN=0 of the Switch Engine VLAN
Command Register (SWE_VLAN_CMD)), the bits form the VLAN table entry
as follows:
BITS
17
DESCRIPTION
Member Port 2
DEFAULT
0b
Indicates the configuration of Port 2 for this VLAN entry.
1 = Member - Packets with a VID that matches this entry
are allowed on ingress. The port is a member of the
broadcast domain on egress.
0 = Not a Member - Packets with a VID that matches this
entry are filtered on ingress unless the Admit Non Member
bit in the Switch Engine Admit Non Member Register
(SWE_ADMT_N_MEMBER) is set for this port. The port is
not a member of the broadcast domain on egress.
16
Un-Tag Port 2
0b
When this bit is set, packets received on Port 2 with a VID
that matches this entry will have their tag removed when retransmitted by egress ports that are designated as Hybrid
ports via the Buffer Manager Egress Port Type Register
(BM_EGRSS_PORT_TYPE).
15
Member Port 1
0b
See description for Member Port 2.
14
Un-Tag Port 1
0b
See description for Un-Tag Port 2.
13
Member Port 0 (External MII)
0b
See description for Member Port 2.
12
Un-Tag Port 0 (External MII)
0b
See description for Un-Tag Port 2.
11:0
VID
000h
These bits specify the VLAN ID associated with this VLAN
entry
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LAN9313/LAN9313i
13.3.3.11
Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS)
Register #:
1810h
Size:
32 bits
This register indicates the current VLAN command status.
Bits
31:1
0
13.3.3.12
Description
Type
Default
RESERVED
RO
-
Operation Pending
When set, this bit indicates that the read or write command is taking place.
This bit is cleared once the command has finished.
RO
SC
0b
Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)
Register #:
1811h
Size:
32 bits
This register is used to read and write the DIFFSERV table. A write to this address performs the specified access. This
table is used to map the received IP ToS/CS to a priority.
For a read access, the Operation Pending bit in the Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) indicates when the command is finished. The Switch Engine DIFFSERV Table Read Data
Register (SWE_DIFFSERV_TBL_RD_DATA) can then be read.
For a write access, the Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) register should be written first. The Operation Pending bit in the Switch Engine DIFFSERV Table Command Status Register
(SWE_DIFFSERV_TBL_CMD_STS) indicates when the command is finished.
Bits
Type
Default
RESERVED
RO
-
7
DIFFSERV Table RnW
This bit specifies a read(1) or a write(0) command.
R/W
0b
6
RESERVED
RO
-
DIFFSERV Table Index
This field specifies the ToS/CS entry that is accessed.
R/W
0h
31:8
5:0
13.3.3.13
Description
Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
Register #:
1812h
Size:
32 bits
This register is used to write the DIFFSERV table. The DIFFSERV table is not initialized upon reset on power-up. If
DIFFSERV is enabled, the full table should be initialized by the host.
Bits
Description
Type
31:3
RESERVED
RO
-
2:0
DIFFSERV Priority
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
R/W
000b
DS00002288A-page 224
Default
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3.3.14
Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)
Register #:
1813h
Size:
32 bits
This register is used to read the DIFFSERV table.
Bits
Description
Type
Default
31:3
RESERVED
RO
-
2:0
DIFFSERV Priority
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
RO
000b
Type
Default
13.3.3.15
Switch Engine DIFFSERV Table Command Status Register
(SWE_DIFFSERV_TBL_CMD_STS)
Register #:
1814h
Size:
32 bits
This register indicates the current DIFFSERV command status.
Bits
31:1
0
13.3.3.16
Description
RESERVED
RO
-
Operation Pending
When set, this bit indicates that the read or write command is taking place.
This bit is cleared once the command has finished.
RO
SC
0b
Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)
Register #:
1840h
Size:
32 bits
This register is used to configure the global ingress rules.
Bits
Description
Type
RESERVED
RO
-
Allow Monitoring Echo
When set, monitored packets are allowed to be echoed back to the source
port. When cleared, monitored packets, like other packets, are never sent
back to the source port.
R/W
0b
IGMP Monitoring Port
This field is the port bit map where IPv4 IGMP packets are sent.
R/W
0b
9
Use IP
When set, the IPv4 TOS or IPv6 SC field is enabled as a transmit priority
queue choice.
R/W
0b
8
RESERVED
R/W
0b
7
Enable IGMP Monitoring
When set, IPv4 IGMP packets are monitored and sent to the IGMP
monitoring port.
R/W
0b
6
SWE Counter Test
When this bit is set the Switch Engine counters that normally clear to 0 when
read will be set to 7FFF_FFFCh when read.
R/W
0b
31:14
13
Default
This bit is useful when the monitoring port wishes to receive it’s own IGMP
packets.
12:10
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LAN9313/LAN9313i
Bits
Description
Type
Default
5
DA Highest Priority
When this bit is set and the Static bit in the ALR table for the destination
MAC address is set, the transmit priority queue that is selected is taken from
the ALR Priority bits (see the Switch Engine ALR Read Data 1 Register
(SWE_ALR_RD_DAT_1)).
R/W
0b
4
Filter Multicast
When this bit is set, packets with a multicast destination address are filtered
if the address is not found in the ALR table. Broadcasts are not included in
this filter.
R/W
0b
3
Drop Unknown
When this bit is set, packets with a unicast destination address are filtered if
the address is not found in the ALR table.
R/W
0b
2
Use Precedence
When the priority is taken from an IPV4 packet (enabled via the Use IP bit),
this bit selects between precedence bits in the TOS octet or the DIFFSERV
table.
R/W
1b
When set, IPv4 packets will use the precedence bits in the TOS octet to
select the transmit priority queue. When cleared, IPv4 packets will use the
DIFFSERV table to select the transmit priority queue.
1
VL Higher Priority
When this bit is set and VLANs are enabled, the priority from the VLAN tag
has higher priority than the IP TOS/SC field.
R/W
1b
0
VLAN Enable
When set, VLAN ingress rules are enabled. This also enables the VLAN to
be used as the transmit priority queue selection.
R/W
0b
13.3.3.17
Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG)
Register #:
1841h
Size:
32 bits
This register is used to configure the per port ingress rules.
Bits
Description
Type
Default
31:6
RESERVED
RO
-
5:3
Enable Learning on Ingress
When set, source addresses are learned when a packet is received on the
corresponding port and the corresponding Port State in the Switch Engine
Port State Register (SWE_PORT_STATE) is set to forwarding or learning.
R/W
111b
R/W
000b
There is one enable bit per ingress port. Bits 5,4,3 correspond to switch ports
2,1,0 respectively.
2:0
Enable Membership Checking
When set, VLAN membership is checked when a packet is received on the
corresponding port.
The packet will be filtered if the ingress port is not a member of the VLAN
(unless the Admit Non Member bit is set for the port in the Switch Engine
Admit Non Member Register (SWE_ADMT_N_MEMBER))
For destination addresses that are found in the ALR table, the packet will be
filtered if the egress port is not a member of the VLAN (for destination
addresses that are not found in the ALR table only the ingress port is
checked for membership).
The VLAN Enable bit in the Switch Engine Global Ingress Configuration
Register (SWE_GLOBAL_INGRSS_CFG) needs to be set for these bits to
have an affect.
There is one enable bit per ingress port. Bits 2,1,0 correspond to switch ports
2,1,0 respectively.
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LAN9313/LAN9313i
13.3.3.18
Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)
Register #:
1842h
Size:
32 bits
This register is used to configure the per port ingress rule for allowing only VLAN tagged packets.
Bits
Description
Type
Default
31:3
RESERVED
RO
-
2:0
Admit Only VLAN
When set, untagged and priority tagged packets are filtered.
R/W
000b
Type
Default
The VLAN Enable bit in the Switch Engine Global Ingress Configuration
Register (SWE_GLOBAL_INGRSS_CFG) needs to be set for these bits to
have an affect.
There is one enable bit per ingress port. Bits 2,1,0 correspond to switch ports
2,1,0 respectively.
13.3.3.19
Switch Engine Port State Register (SWE_PORT_STATE)
Register #:
1843h
Size:
32 bits
This register is used to configure the per port spanning tree state.
Bits
Description
31:6
RESERVED
RO
-
5:4
Port State Port 2
These bits specify the spanning tree port states for Port 2.
R/W
00b
R/W
00b
R/W
00b
00
01
10
11
3:2
Forwarding
Blocking
Learning
Listening
Port State Port 1
These bits specify the spanning tree port states for Port 1.
00
01
10
11
1:0
=
=
=
=
=
=
=
=
Forwarding
Blocking
Learning
Listening
Port State Port 0
These bits specify the spanning tree port states for Port 0(External MII).
00
01
10
11
=
=
=
=
Forwarding
Blocking
Learning
Listening
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LAN9313/LAN9313i
13.3.3.20
Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
Register #:
1845h
Size:
32 bits
This register specifies the Traffic Class table that maps the packet priority into the egress queues.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:14
Priority 7 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 7.
R/W
11b
13:12
Priority 6 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 6.
R/W
11b
11:10
Priority 5 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 5.
R/W
10b
9:8
Priority 4 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 4.
R/W
10b
7:6
Priority 3 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 3.
R/W
01b
5:4
Priority 2 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 2.
R/W
00b
3:2
Priority 1 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 1.
R/W
00b
1:0
Priority 0 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 0.
R/W
01b
Type
Default
RESERVED
RO
-
Enable RX Mirroring Filtered
When set, packets that would normally have been filtered are included in the
receive mirroring function and are sent only to the sniffer port. When cleared,
filtered packets are not mirrored.
R/W
0b
R/W
00b
13.3.3.21
Switch Engine Port Mirroring Register (SWE_PORT_MIRROR)
Register #:
1846h
Size:
32 bits
This register is used to configure port mirroring.
Bits
31:9
8
Description
Note:
7:5
The Ingress Filtered Count Registers will still count these packets
as filtered and the Switch Engine Interrupt Pending Register
(SWE_IPR) will still register a drop interrupt.
Sniffer Port
These bits specify the sniffer port that transmits packets that are monitored.
Bits 7,6,5 correspond to switch ports 2,1,0 respectively.
Note:
Only one port should be set as the sniffer.
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LAN9313/LAN9313i
Bits
Description
Type
Default
4:2
Mirrored Port
These bits specify if a port is to be mirrored. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
R/W
00b
Note:
Multiple ports can be set as mirrored.
1
Enable RX Mirroring
This bit enables packets received on the mirrored ports to be also sent to
the sniffer port.
R/W
0b
0
Enable TX Mirroring
This bit enables packets transmitted on the mirrored ports to be also sent to
the sniffer port.
R/W
0b
13.3.3.22
Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP)
Register #:
1847h
Size:
32 bits
This register is used to enable the special tagging mode used to determine the destination port based on the VLAN tag
contents.
Bits
Description
Type
Default
31:6
RESERVED
RO
-
5:4
Ingress Port Type Port 2
A setting of 11b enables the usage of the VLAN tag to specify the packet
destination. All other values disable this feature.
R/W
00b
3:2
Ingress Port Type Port 1
A setting of 11b enables the usage of the VLAN tag to specify the packet
destination. All other values disable this feature.
R/W
00b
1:0
Ingress Port Type Port 0
A setting of 11b enables the usage of the VLAN tag to specify the packet
destination. All other values disable this feature.
R/W
00b
Type
Default
13.3.3.23
Switch Engine Broadcast Throttling Register (SWE_BCST_THROT)
Register #:
1848h
Size:
32 bits
This register configures the broadcast input rate throttling.
Bits
31:27
26
25:18
17
16:9
Description
RESERVED
RO
-
Broadcast Throttle Enable Port 2
This bit enables broadcast input rate throttling on Port 2.
R/W
0b
Broadcast Throttle Level Port 2
These bits specify the number of bytes x 64 allowed to be received per every
1.72mS interval.
R/W
02h
Broadcast Throttle Enable Port 1
This bit enables broadcast input rate throttling on Port 1.
R/W
0b
Broadcast Throttle Level Port 1
These bits specify the number of bytes x 64 allowed to be received per every
1.72mS interval.
R/W
02h
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LAN9313/LAN9313i
Bits
8
7:0
13.3.3.24
Type
Default
Broadcast Throttle Enable Port 0
This bit enables broadcast input rate throttling on Port 0(External MII).
Description
R/W
0b
Broadcast Throttle Level Port 0
These bits specify the number of bytes x 64 allowed to be received per every
1.72mS interval.
R/W
02h
Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)
Register #:
1849h
Size:
32 bits
This register is used to allow access to a VLAN even if the ingress port is not a member.
Type
Default
31:3
Bits
RESERVED
Description
RO
-
2:0
Admit Non Member
When set, a received packet is accepted even if the ingress port is not a
member of the destination VLAN. The VLAN still must be active in the switch.
R/W
000b
There is one bit per ingress port. Bits 2,1,0 correspond to switch ports 2,1,0
respectively.
13.3.3.25
Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG)
Register #:
184Ah
Size:
32 bits
This register, along with the settings accessible via the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD), is used to configure the ingress rate metering/coloring.
Bits
Description
Type
Default
31:3
RESERVED
RO
-
2:1
Rate Mode
These bits configure the rate metering/coloring mode.
R/W
00b
R/W
0b
00
01
10
11
0
=
=
=
=
Source Port & Priority
Source Port Only
Priority Only
RESERVED
Ingress Rate Enable
When set, ingress rates are metered and packets are colored and dropped
if necessary.
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LAN9313/LAN9313i
13.3.3.26
Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)
Register #:
184Bh
Size:
32 bits
This register is used to indirectly read and write the ingress rate metering/color table registers. A write to this address
performs the specified access.
For a read access, the Operation Pending bit in the Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) indicates when the command is finished. The Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) can then be read.
For a write access, the Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA) should be
written first. The Operation Pending bit in the Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) indicates when the command is finished.
For details on 16-bit wide Ingress Rate Table registers indirectly accessible by this register, see Section 13.3.3.26.1
below.
Bits
31:8
7
6:5
Description
Default
RESERVED
RO
-
Ingress Rate RnW
These bits specify a read(1) or write(0) command.
R/W
0b
Type
These bits select between the ingress rate metering/color table registers as
follows:
R/W
00b
R/W
0h
00
01
10
11
4:0
Type
=
=
=
=
RESERVED
Committed Information Rate Registers
Committed Burst Register
Excess Burst Register
(uses CIS Address field)
CIR Address
These bits select one of the 24 Committed Information Rate registers.
When Rate Mode is set to Source Port & Priority in the Switch Engine
Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG), the first
set of 8 registers (CIR addresses 0-7) are for to Port 0, the second set of 8
registers (CIR addresses 8-15) are for Port 1, and the third set of registers
(CIR addresses 16-23) are for Port 2. Priority 0 is the lower register of each
set (e.g. 0, 8, and 16).
When Rate Mode is set to Source Port Only, the first register (CIR address
0) is for Port 0, the second register (CIR address 1) is for Port 1, and the
third register (CIR address 2) is for Port 2.
When Rate Mode is set to Priority Only, the first register (CIR address 0) is
for priority 0, the second register (CIR address 1) is for priority 1, and so forth
up to priority 23.
Note:
Values outside of the valid range may cause unexpected results.
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LAN9313/LAN9313i
13.3.3.26.1
Ingress Rate Table Registers
The ingress rate metering/color table consists of 24 Committed Information Rate (CIR) registers (one per port/priority),
a Committed Burst Size register, and an Excess Burst Size register. All metering/color table registers are 16-bits in size
and are accessed indirectly via the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD).
Descriptions of these registers are detailed in Table 13-13 below.
TABLE 13-13: METERING/COLOR TABLE REGISTER DESCRIPTIONS
Description
Type
Default
Excess Burst Size
This register specifies the maximum excess burst size in bytes. Bursts larger than
this value that exceed the excess data rate are dropped.
R/W
0600h
R/W
0600h
R/W
0014h
Note:
Either this value or the Committed Burst Size should be set larger than or
equal to the largest possible packet expected.
Note:
All of the Excess Burst token buckets are initialized to this default value. If
a lower value is programmed into this register, the token buckets will need
to be normally depleted below this value before this value has any affect
on limiting the token bucket maximum values.
This register is 16-bits wide.
Committed Burst Size
This register specifies the maximum committed burst size in bytes. Bursts larger than
this value that exceed the committed data rate are subjected to random dropping.
Note:
Either this value or the Excess Burst Size should be set larger than or equal
to the largest possible packet expected.
Note:
All of the Committed Burst token buckets are initialized to this default value.
If a lower value is programmed into this register, the token buckets will need
to be normally depleted below this value before this value has any affect
on limiting the token bucket maximum values.
This register is 16-bits wide.
Committed Information Rate (CIR)
These registers specify the committed data rate for the port/priority pair. The rate is
specified in time per byte. The time is this value plus 1 times 20nS.
There are 24 of these registers each 16-bits wide.
13.3.3.27
Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS)
Register #:
184Ch
Size:
32 bits
This register indicates the current ingress rate command status.
Bits
31:1
0
Type
Default
RESERVED
Description
RO
-
Operation Pending
When set, indicates that the read or write command is taking place. This bit
is cleared once the command has finished.
RO
SC
0b
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LAN9313/LAN9313i
13.3.3.28
Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)
Register #:
184Dh
Size:
32 bits
This register is used to write the ingress rate table registers.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:0
Data
This is the data to be written to the ingress rate table registers as specified
in the Switch Engine Ingress Rate Command Register
(SWE_INGRSS_RATE_CMD). Refer to Section 13.3.3.26.1, "Ingress Rate
Table Registers," on page 232 for details on these registers.
R/W
0000h
13.3.3.29
Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA)
Register #:
184Eh
Size:
32 bits
This register is used to read the ingress rate table registers.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:0
Data
This is the read data from the ingress rate table registers as specified in the
Switch Engine Ingress Rate Command Register
(SWE_INGRSS_RATE_CMD). Refer to Section 13.3.3.26.1, "Ingress Rate
Table Registers," on page 232 for details on these registers.
RO
0000h
13.3.3.30
Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)
Register #:
1850h
Size:
32 bits
This register counts the number of packets filtered at ingress on Port 0(External MII). This count includes packets filtered
due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Bits
Description
Type
Default
31:0
Filtered
This field is a count of packets filtered at ingress and is cleared when read.
RC
00000000h
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
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LAN9313/LAN9313i
13.3.3.31
Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)
Register #:
1851h
Size:
32 bits
This register counts the number of packets filtered at ingress on Port 1. This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Bits
Description
Type
Default
31:0
Filtered
This field is a count of packets filtered at ingress and is cleared when read.
RC
00000000h
Note:
13.3.3.32
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)
Register #:
1852h
Size:
32 bits
This register counts the number of packets filtered at ingress on Port 2. This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Bits
Description
Type
Default
31:0
Filtered
This field is a count of packets filtered at ingress and is cleared when read.
RC
00000000h
Note:
13.3.3.33
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register
(SWE_INGRSS_REGEN_TBL_MII)
Register #:
1855h
Size:
32 bits
This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is
used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
Bits
Description
Type
Default
31:24
RESERVED
RO
-
23:21
Regen7
These bits specify the regenerated priority for received priority 7.
R/W
7h
20:18
Regen6
These bits specify the regenerated priority for received priority 6.
R/W
6h
17:15
Regen5
These bits specify the regenerated priority for received priority 5.
R/W
5h
14:12
Regen4
These bits specify the regenerated priority for received priority 4.
R/W
4h
11:9
Regen3
These bits specify the regenerated priority for received priority 3.
R/W
3h
8:6
Regen2
These bits specify the regenerated priority for received priority 2.
R/W
2h
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LAN9313/LAN9313i
Bits
Type
Default
5:3
Regen1
These bits specify the regenerated priority for received priority 1.
R/W
1h
2:0
Regen0
These bits specify the regenerated priority for received priority 0.
R/W
0h
13.3.3.34
Description
Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register
(SWE_INGRSS_REGEN_TBL_1)
Register #:
1856h
Size:
32 bits
This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is
used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
Bits
31:24
Description
Type
Default
RESERVED
RO
-
23:21
Regen7
These bits specify the regenerated priority for received priority 7.
R/W
7h
20:18
Regen6
These bits specify the regenerated priority for received priority 6.
R/W
6h
17:15
Regen5
These bits specify the regenerated priority for received priority 5.
R/W
5h
14:12
Regen4
These bits specify the regenerated priority for received priority 4.
R/W
4h
11:9
Regen3
These bits specify the regenerated priority for received priority 3.
R/W
3h
8:6
Regen2
These bits specify the regenerated priority for received priority 2.
R/W
2h
5:3
Regen1
These bits specify the regenerated priority for received priority 1.
R/W
1h
2:0
Regen0
These bits specify the regenerated priority for received priority 0.
R/W
0h
13.3.3.35
Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register
(SWE_INGRSS_REGEN_TBL_2)
Register #:
1857h
Size:
32 bits
This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is
used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
Bits
Description
Type
Default
31:24
RESERVED
RO
-
23:21
Regen7
These bits specify the regenerated priority for received priority 7.
R/W
7h
20:18
Regen6
These bits specify the regenerated priority for received priority 6.
R/W
6h
17:15
Regen5
These bits specify the regenerated priority for received priority 5.
R/W
5h
14:12
Regen4
These bits specify the regenerated priority for received priority 4.
R/W
4h
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Type
Default
11:9
Bits
Regen3
These bits specify the regenerated priority for received priority 3.
R/W
3h
8:6
Regen2
These bits specify the regenerated priority for received priority 2.
R/W
2h
5:3
Regen1
These bits specify the regenerated priority for received priority 1.
R/W
1h
2:0
Regen0
These bits specify the regenerated priority for received priority 0.
R/W
0h
13.3.3.36
Description
Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)
Register #:
1858h
Size:
32 bits
This register counts the number of MAC addresses on Port 0(External MII) that were not learned or were overwritten by
a different address due to address table space limitations.
Bits
31:0
Description
Learn Discard
This field is a count of MAC addresses not learned or overwritten and is
cleared when read.
Note:
13.3.3.37
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)
Register #:
1859h
Size:
32 bits
This register counts the number of MAC addresses on Port 1 that were not learned or were overwritten by a different
address due to address table space limitations.
Bits
31:0
Description
Learn Discard
This field is a count of MAC addresses not learned or overwritten and is
cleared when read.
Note:
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
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LAN9313/LAN9313i
13.3.3.38
Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)
Register #:
185Ah
Size:
32 bits
This register counts the number of MAC addresses on Port 2 that were not learned or were overwritten by a different
address due to address table space limitations.
Bits
31:0
Description
Learn Discard
This field is a count of MAC addresses not learned or overwritten and is
cleared when read.
Note:
13.3.3.39
Type
Default
RC
00000000h
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Switch Engine Interrupt Mask Register (SWE_IMR)
Register #:
1880h
Size:
32 bits
This register contains the Switch Engine interrupt mask, which masks the interrupts in the Switch Engine Interrupt Pending Register (SWE_IPR). All Switch Engine interrupts are masked by setting the Interrupt Mask bit. Clearing this bit will
unmask the interrupts. Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Bits
31:1
0
Description
Type
Default
RESERVED
RO
-
Interrupt Mask
When set, this bit masks interrupts from the Switch Engine. The status bits
in the Switch Engine Interrupt Pending Register (SWE_IPR) are not affected.
R/W
1b
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13.3.3.40
Switch Engine Interrupt Pending Register (SWE_IPR)
Register #:
1881h
Size:
32 bits
This register contains the Switch Engine interrupt status. The status is double buffered. All interrupts in this register may
be masked via the Switch Engine Interrupt Mask Register (SWE_IMR) register. Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Bits
Description
Type
Default
31:15
RESERVED
RO
-
14:11
Drop Reason B
When bit 8 is set, these bits indicate the reason a packet was dropped per
the table below:
RC
0h
RC
00b
BIT
VALUES
10:9
DESCRIPTION
0000
Admit Only VLAN was set and the packet was untagged or priority tagged.
0001
The destination address was not in the ALR table (unknown or broadcast),
Enable Membership Checking on ingress was set, Admit Non Member was
cleared and the source port was not a member of the incoming VLAN.
0010
The destination address was found in the ALR table but the source port was
not in the forwarding state.
0011
The destination address was found in the ALR table but the destination port
was not in the forwarding state.
0100
The destination address was found in the ALR table but Enable Membership
Checking on ingress was set and the destination port was not a member of the
incoming VLAN.
0101
The destination address was found in the ALR table but the Enable
Membership Checking on ingress was set, Admit Non Member was cleared and
the source port was not a member of the incoming VLAN.
0110
Drop Unknown was set and the destination address was a unicast but not in
the ALR table.
0111
Filter Multicast was set and the destination address was a multicast and not in
the ALR table.
1000
The packet was a broadcast but exceeded the Broadcast Throttling limit.
1001
The destination address was not in the ALR table (unknown or broadcast) and
the source port was not in the forwarding state.
1010
The destination address was found in the ALR table but the source and
destination ports were the same.
1011
The destination address was found in the ALR table and the Filter bit was set
for that address.
1100
RESERVED
1101
RESERVED
1110
A packet was received with a VLAN ID of FFFh
1111
RESERVED
Source Port B
When bit 8 is set, these bits indicate the source port on which the packet
was dropped.
00
01
10
11
=
=
=
=
Port 0
Port 1
Port 2
RESERVED
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LAN9313/LAN9313i
Bits
Type
Default
Set B Valid
When set, bits 14:9 are valid.
RC
0b
7:4
Drop Reason A
When bit 1 is set, these bits indicate the reason a packet was dropped. See
the Drop Reason B description above for definitions of each value of this
field.
RC
0h
3:2
Source port A
When bit 1 is set, these bits indicate the source port on which the packet
was dropped.
RC
00b
8
Description
00
01
10
11
=
=
=
=
Port 0
Port 1
Port 2
RESERVED
1
Set A Valid
When set, bits 7:2 are valid.
RC
0b
0
Interrupt Pending
When set, a packet dropped event(s) is indicated.
RC
0b
13.3.4
BUFFER MANAGER CSRS
This section details the Buffer Manager (BM) registers. These registers allow configuration and monitoring of the switch
buffer levels and usage. A list of the general switch CSRs and their corresponding register numbers is included in
Table 13-12.
13.3.4.1
Buffer Manager Configuration Register (BM_CFG)
Register #:
1C00h
Size:
32 bits
This register enables egress rate pacing and ingress rate discarding.
Bits
Description
Type
RESERVED
RO
-
6
BM Counter Test
When this bit is set, Buffer Manager (BM) counters that normally clear to 0
when read, will be set to 7FFF_FFFC when read.
R/W
0b
5
Fixed Priority Queue Servicing
When set, output queues are serviced with a fixed priority ordering. When
cleared, output queues are serviced with a weighted round robin ordering.
R/W
0b
4:2
Egress Rate Enable
When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
R/W
0b
Drop on Yellow
When this bit is set, packets that exceed the Ingress Committed Burst Size
(colored Yellow) are subjected to random discard.
R/W
0b
R/W
0b
31:7
1
Note:
0
See Section 13.3.3.26, "Switch Engine Ingress Rate Command
Register (SWE_INGRSS_RATE_CMD)," on page 231 for
information on configuring the Ingress Committed Burst Size.
Drop on Red
When this bit is set, packets that exceed the Ingress Excess Burst Size
(colored Red) are discarded.
Note:
Default
See Section 13.3.3.26, "Switch Engine Ingress Rate Command
Register (SWE_INGRSS_RATE_CMD)," on page 231 for
information on configuring the Ingress Excess Burst Size.
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LAN9313/LAN9313i
13.3.4.2
Buffer Manager Drop Level Register (BM_DROP_LVL)
Register #:
1C01h
Size:
32 bits
This register configures the overall buffer usage limits.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:8
Drop Level Low
These bits specify the buffer limit that can be used per ingress port during
times when 2 or 3 ports are active.
R/W
49h
R/W
64h
Each buffer is 128 bytes.
Note:
7:0
A port is “active” when 36 buffers are in use for that port.
Drop Level High
These bits specify the buffer limit that can be used per ingress port during
times when 1 port is active.
Each buffer is 128 bytes.
Note:
13.3.4.3
A port is “active” when 36 buffers are in use for that port.
Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
Register #:
1C02h
Size:
32 bits
This register configures the buffer usage level when a Pause frame or backpressure is sent.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:8
Pause Level Low
These bits specify the buffer usage level during times when 2 or 3 ports are
active.
R/W
21h
R/W
3Ch
Each buffer is 128 bytes.
Note:
7:0
A port is “active” when 36 buffers are in use for that port.
Pause Level High
These bits specify the buffer usage level during times when 1 port is active.
Each buffer is 128 bytes.
Note:
A port is “active” when 36 buffers are in use for that port.
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LAN9313/LAN9313i
13.3.4.4
Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL)
Register #:
1C03h
Size:
32 bits
This register configures the buffer usage level when a Pause frame with a pause value of 1 is sent.
Bits
Description
Type
Default
31:16
RESERVED
RO
-
15:8
Resume Level Low
These bits specify the buffer usage level during times when 2 or 3 ports are
active.
R/W
03h
R/W
07h
Each buffer is 128 bytes.
Note:
7:0
A port is “active” when 36 buffers are in use for that port.
Resume Level High
These bits specify the buffer usage level during times when 0 or 1 ports are
active.
Each buffer is 128 bytes.
Note:
13.3.4.5
A port is “active” when 36 buffers are in use for that port.
Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)
Register #:
1C04h
Size:
32 bits
This register configures the buffer usage limits for broadcasts, multicasts, and unknown unicasts.
Bits
Description
Type
Default
31:8
RESERVED
RO
-
7:0
Broadcast Drop Level
These bits specify the maximum number of buffers that can be used by
broadcasts, multicasts, and unknown unicasts.
R/W
31h
Each buffer is 128 bytes.
13.3.4.6
Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)
Register #:
1C05h
Size:
32 bits
This register counts the number of packets dropped by the Buffer Manager that were received on Port 0(External MII).
This count includes packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow
dropping).
Bits
Description
Type
Default
31:0
Dropped Count
These bits count the number of dropped packets received on Port 0 and is
cleared when read.
RC
00000000h
Note:
The counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
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13.3.4.7
Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)
Register #:
1C06h
Size:
32 bits
This register counts the number of packets dropped by the Buffer Manager that were received on Port 1. This count
includes packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow dropping).
Bits
Description
Type
Default
31:0
Dropped Count
These bits count the number of dropped packets received on Port 1 and is
cleared when read.
RC
00000000h
Note:
13.3.4.8
The counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)
Register #:
1C07h
Size:
32 bits
This register counts the number of packets dropped by the Buffer Manager that were received on Port 2. This count
includes packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow dropping).
Bits
Description
Type
Default
31:0
Dropped Count
These bits count the number of dropped packets received on Port 2 and is
cleared when read.
RC
00000000h
Type
Default
Note:
13.3.4.9
The counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Buffer Manager Reset Status Register (BM_RST_STS)
Register #:
1C08h
Size:
32 bits
This register indicates when the Buffer Manager has been initialized by the reset process.
Bits
31:1
0
Description
RESERVED
RO
-
BM Ready
When set, indicates the Buffer Manager tables have finished being initialized
by the reset process. The initialization is performed upon any reset that
resets the switch fabric.
RO
SS
Note 13-65
Note 13-65 The default value of this bit is 0 immediately following any switch fabric reset and then self-sets to 1
once the ALR table is initialized.
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LAN9313/LAN9313i
13.3.4.10
Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)
Register #:
1C09h
Size:
32 bits
This register is used to read and write the Random Discard Weight table. A write to this address performs the specified
access. This table is used to set the packet drop probability verses the buffer usage.
For a read access, the Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)
can be read following a write to this register.
For a write access, the Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) should be written before writing this register.
Bits
31:5
4
3:0
Description
Type
Default
RESERVED
RO
-
Random Discard Weight Table RnW
Specifies a read (1) or a write (0) command.
R/W
0b
Random Discard Weight Table Index
Specifies the buffer usage range that is accessed.
R/W
0h
There are a total of 16 probability entries. Each entry corresponds to a range
of the number of buffers used by the ingress port. The ranges are structured
to give more resolution towards the lower buffer usage end.
BIT
VALUES
BUFFER USAGE LEVEL
0000
0 to 7
0001
8 to 15
0010
16 to 23
0011
24 to 31
0100
32 to 39
0101
40 to 47
0110
48 to 55
0111
56 to 63
1000
64 to 79
1001
80 to 95
1010
96 to 111
1011
112 to 127
1100
128 to 159
1101
160 to 191
1110
192 to 223
1111
224 to 255
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13.3.4.11
Buffer Manager Random Discard Table Write Data Register
(BM_RNDM_DSCRD_TBL_WDATA)
Register #:
1C0Ah
Size:
32 bits
This register is used to write the Random Discard Weight table.
Note:
The Random Discard Weight table is not initialized upon reset or power-up. If a random discard is enabled,
the full table should be initialized by the host.
Bits
31:10
9:0
Description
Type
Default
RESERVED
RO
-
Drop Probability
These bits specify the discard probability of a packet that has been colored
Yellow by the ingress metering. The probability is given in 1/1024’s. For
example, a setting of 1 is one in 1024, or approximately 0.1%. A setting of
all ones (1023) is 1023 in 1024, or approximately 99.9%.
R/W
000h
Type
Default
RESERVED
RO
-
Drop Probability
These bits specify the discard probability of a packet that has been colored
Yellow by the ingress metering. The probability is given in 1/1024’s. For
example, a setting of 1 is one in 1024, or approximately 0.1%. A setting of
all ones (1023) is 1023 in 1024, or approximately 99.9%.
RO
000h
There are a total of 16 probability entries. Each entry corresponds to a range
of the number of buffers used by the ingress port, as specified in Section
13.3.4.10, "Buffer Manager Random Discard Table Command Register
(BM_RNDM_DSCRD_TBL_CMD)".
13.3.4.12
Buffer Manager Random Discard Table Read Data Register
(BM_RNDM_DSCRD_TBL_RDATA)
Register #:
1C0Bh
Size:
32 bits
This register is used to read the Random Discard Weight table.
Bits
31:10
9:0
Description
There are a total of 16 probability entries. Each entry corresponds to a range
of the number of buffers used by the ingress port, as specified in Section
13.3.4.10, "Buffer Manager Random Discard Table Command Register
(BM_RNDM_DSCRD_TBL_CMD)".
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LAN9313/LAN9313i
13.3.4.13
Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE)
Register #:
1C0Ch
Size:
32 bits
This register is used to configure the egress VLAN tagging rules. See Section 6.5.6, "Adding, Removing, and Changing
VLAN Tags," on page 64 for additional details.
Bits
31:22
21
Description
Type
Default
RESERVED
RO
-
Insert Tag Port 2
When set, untagged packets will have a tag added that contains the Default
VLAN ID and Priority of the ingress port.
R/W
0b
R/W
0b
R/W
0b
R/W
0b
The un-tag bit in the VLAN table for the default VLAN ID also needs to be
cleared in order for the tag to be inserted.
This is only used when the Egress Port Type is set as Hybrid.
20
Change VLAN ID Port 2
When set, regular tagged packets will have their VLAN ID overwritten with
the Default VLAN ID of the egress port.
The Change Tag bit also needs to be set.
The un-tag bit in the VLAN table for the incoming VLAN ID also needs to be
cleared, otherwise the tag will be removed instead.
Priority tagged packets will have VLAN ID overwritten with the Default VLAN
ID of the ingress port independent of this bit.
This is only used when the Egress Port Type is set as Hybrid.
19
Change Priority Port 2
When set, regular tagged packets will have their Priority overwritten with the
Default Priority of the egress port. Priority tagged packets will have VLAN ID
overwritten with the Default VLAN ID of the ingress port.
For regular tagged packets, the Change Tag bit also needs to be set.
The un-tag bit in the VLAN table for the incoming VLAN ID also needs to be
cleared, otherwise the tag would be removed instead.
This is only used when the Egress Port Type is set as Hybrid.
18
Change Tag Port 2
When set, allows the Change Tag and Change Priority bits to affect regular
tagged packets.
This bit has no affect on priority tagged packets.
This is only used when the Egress Port Type is set as Hybrid.
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Bits
Description
Type
Default
17:16
Egress Port Type Port 2
These bits set the egress port type which determines the tagging/un-tagging
rules.
R/W
0b
BIT
VALUES
EGRESS PORT TYPE
00
Dumb
Packets from regular ports pass untouched. Special tagged packets from the
External MII port have their tagged stripped.
01
Access
Tagged packets (including special tagged packets from the External MII port)
have their tagged stripped.
10
Hybrid
Supports a mix of tagging, un-tagging and changing tags. See Section 6.5.6,
"Adding, Removing, and Changing VLAN Tags," on page 64 for additional
details.
11
CPU
A special tag is added to indicate the source of the packet. See Section 6.5.6,
"Adding, Removing, and Changing VLAN Tags," on page 64 for additional
details.
RESERVED
RO
-
13
Insert Tag Port 1
Identical to Insert Tag Port 2 definition above.
R/W
0b
12
Change VLAN ID Port 1
Identical to Change VLAN ID Port 2 definition above.
R/W
0b
11
Change Priority Port 1
Identical to Change Priority Port 2 definition above.
R/W
0b
10
Change Tag Port 1
Identical to Change Tag Port 2 definition above.
R/W
0b
9:8
Egress Port Type Port 1
Identical to Egress Port Type Port 2 definition above.
R/W
0b
7:6
15:14
RESERVED
RO
-
5
Insert Tag Port 0(External MII)
Identical to Insert Tag Port 2 definition above.
R/W
0b
4
Change VLAN ID Port 0(External MII)
Identical to Change VLAN ID Port 2 definition above.
R/W
0b
3
Change Priority Port 0(External MII)
Identical to Change Priority Port 2 definition above.
R/W
0b
2
Change Tag Port 0(External MII)
Identical to Change Tag Port 2 definition above.
R/W
0b
Egress Port Type Port 0(External MII)
Identical to Egress Port Type Port 2 definition above.
R/W
0b
1:0
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LAN9313/LAN9313i
13.3.4.14
Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01)
Register #:
1C0Dh
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
Bits
Description
Type
31:26
RESERVED
RO
-
25:13
Egress Rate Port 0 Priority Queue 1
These bits specify the egress data rate for the Port 0(External MII) priority
queue 1. The rate is specified in time per byte. The time is this value plus 1
times 20nS.
R/W
00000h
12:0
Egress Rate Port 0 Priority Queue 0
These bits specify the egress data rate for the Port 0(External MII) priority
queue 0. The rate is specified in time per byte. The time is this value plus 1
times 20nS.
R/W
00000h
13.3.4.15
Default
Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03)
Register #:
1C0Eh
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
Bits
Description
Type
31:26
RESERVED
RO
-
25:13
Egress Rate Port 0 Priority Queue 3
These bits specify the egress data rate for the Port 0(External MII) priority
queue 3. The rate is specified in time per byte. The time is this value plus 1
times 20nS.
R/W
00000h
12:0
Egress Rate Port 0 Priority Queue 2
These bits specify the egress data rate for the Port 0(External MII) priority
queue 2. The rate is specified in time per byte. The time is this value plus 1
times 20nS.
R/W
00000h
13.3.4.16
Default
Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11)
Register #:
1C0Fh
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
Bits
Description
Type
Default
31:26
RESERVED
RO
-
25:13
Egress Rate Port 1 Priority Queue 1
These bits specify the egress data rate for the Port 1 priority queue 1. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
12:0
Egress Rate Port 1 Priority Queue 0
These bits specify the egress data rate for the Port 1 priority queue 0. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
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13.3.4.17
Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13)
Register #:
1C10h
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
Bits
Description
Type
31:26
RESERVED
RO
-
25:13
Egress Rate Port 1 Priority Queue 3
These bits specify the egress data rate for the Port 1 priority queue 3. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
12:0
Egress Rate Port 1 Priority Queue 2
These bits specify the egress data rate for the Port 1 priority queue 2. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
13.3.4.18
Default
Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21)
Register #:
1C11h
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
Bits
Description
Type
31:26
RESERVED
RO
-
25:13
Egress Rate Port 2 Priority Queue 1
These bits specify the egress data rate for the Port 2 priority queue 1. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
12:0
Egress Rate Port 2 Priority Queue 0
These bits specify the egress data rate for the Port 2 priority queue 0. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
13.3.4.19
Default
Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23)
Register #:
1C12h
Size:
32 bits
This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
Bits
Description
Type
31:26
RESERVED
RO
-
25:13
Egress Rate Port 2 Priority Queue 3
These bits specify the egress data rate for the Port 2 priority queue 3. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
12:0
Egress Rate Port 2 Priority Queue 2
These bits specify the egress data rate for the Port 2 priority queue 2. The
rate is specified in time per byte. The time is this value plus 1 times 20nS.
R/W
00000h
DS00002288A-page 248
Default
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3.4.20
Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII)
Register #:
1C13h
Size:
32 bits
This register is used to specify the default VLAN ID and priority of Port 0(External MII).
Bits
Description
Type
Default
31:15
RESERVED
RO
-
14:12
Default Priority
These bits specify the default priority that is used when a tag is inserted or
changed on egress.
R/W
000b
11:0
Default VLAN ID
These bits specify the default that is used when a tag is inserted or changed
on egress.
R/W
000h
13.3.4.21
Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1)
Register #:
1C14h
Size:
32 bits
This register is used to specify the default VLAN ID and priority of Port 1.
Bits
Description
Type
Default
31:15
RESERVED
RO
-
14:12
Default Priority
These bits specify the default priority that is used when a tag is inserted or
changed on egress.
R/W
000b
11:0
Default VLAN ID
These bits specify the default that is used when a tag is inserted or changed
on egress.
R/W
000h
13.3.4.22
Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2)
Register #:
1C15h
Size:
32 bits
This register is used to specify the default VLAN ID and priority of Port 2.
Bits
Description
Type
31:15
RESERVED
RO
-
14:12
Default Priority
These bits specify the default priority that is used when a tag is inserted or
changed on egress.
R/W
000b
11:0
Default VLAN ID
These bits specify the default that is used when a tag is inserted or changed
on egress.
R/W
000h
2008-2016 Microchip Technology Inc.
Default
DS00002288A-page 249
LAN9313/LAN9313i
13.3.4.23
Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)
Register #:
1C16h
Size:
32 bits
This register counts the number of packets received on Port 0(External MII) that were dropped by the Buffer Manager
due to ingress rate limit discarding (Red and random Yellow dropping).
Bits
Description
Type
Default
31:0
Dropped Count
These bits count the number of dropped packets received on Port 0(External
MII) and is cleared when read.
RC
00000000h
Note:
13.3.4.24
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)
Register #:
1C17h
Size:
32 bits
This register counts the number of packets received on Port 1 that were dropped by the Buffer Manager due to ingress
rate limit discarding (Red and random Yellow dropping).
Bits
Description
Type
Default
31:0
Dropped Count
These bits count the number of dropped packets received on Port 1 and is
cleared when read.
RC
00000000h
Note:
13.3.4.25
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
Register #:
1C18h
Size:
32 bits
This register counts the number of packets received on Port 2 that were dropped by the Buffer Manager due to ingress
rate limit discarding (Red and random Yellow dropping).
Bits
Description
Type
Default
31:0
Dropped Count
These bits count the number of dropped packets received on Port 2 and is
cleared when read.
RC
00000000h
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
DS00002288A-page 250
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
13.3.4.26
Buffer Manager Interrupt Mask Register (BM_IMR)
Register #:
1C20h
Size:
32 bits
This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Buffer Manager Interrupt
Pending Register (BM_IPR). All Buffer Manager interrupts are masked by setting the Interrupt Mask bit. Clearing this
bit will unmask the interrupts. Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Bits
31:1
0
Description
Type
RESERVED
RO
-
Interrupt Mask
When set, this bit masks interrupts from the Buffer Manager. The status bits
in the Buffer Manager Interrupt Pending Register (BM_IPR) are not affected.
R/W
1b
2008-2016 Microchip Technology Inc.
Default
DS00002288A-page 251
LAN9313/LAN9313i
13.3.4.27
Buffer Manager Interrupt Pending Register (BM_IPR)
Register #:
1C21h
Size:
32 bits
This register contains the Buffer Manager interrupt status. The status is double buffered. All interrupts in this register
may be masked via the Buffer Manager Interrupt Mask Register (BM_IMR) register. Refer to Section 5.0, "System Interrupts," on page 41 for more information.
Bits
Description
Type
Default
31:14
RESERVED
RO
-
13:10
Drop Reason B
When bit 7 is set, these bits indicate the reason a packet was dropped per
the table below:
RC
0h
RC
00b
Status B Pending
When set, bits 13:8 are valid.
RC
0b
Drop Reason A
When bit 0 is set, these bits indicate the reason a packet was dropped. See
the Drop Reason B description above for definitions of each value of this
field.
RC
0h
BIT
VALUES
9:8
6:3
0000
The destination address was not in the ALR table (unknown or broadcast), and
the Broadcast Buffer Level was exceeded.
0001
Drop on Red was set and the packet was colored Red.
0010
There were no buffers available.
0011
There were no memory descriptors available.
0100
The destination address was not in the ALR table (unknown or broadcast) and
there were no valid destination ports.
0101
The packet had a receive error and was >64 bytes
0110
The Buffer Drop Level was exceeded.
0111
RESERVED
1000
RESERVED
1001
Drop on Yellow was set, the packet was colored Yellow and was randomly
selected to be dropped.
1010
RESERVED
1011
RESERVED
1100
RESERVED
1101
RESERVED
1110
RESERVED
1111
RESERVED
Source Port B
When bit 7 is set, these bits indicate the source port on which the packet
was dropped.
00
01
10
11
7
DESCRIPTION
=
=
=
=
Port 0
Port 1
Port 2
RESERVED
DS00002288A-page 252
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
Bits
2:1
Description
Source port A
When bit 0 is set, these bits indicate the source port on which the packet
was dropped.
00
01
10
11
0
=
=
=
=
Type
Default
RC
00b
RC
0b
Port 0
Port 1
Port 2
RESERVED
Set A Valid
When set, bits 6:1 are valid.
2008-2016 Microchip Technology Inc.
DS00002288A-page 253
LAN9313/LAN9313i
14.0
OPERATIONAL CHARACTERISTICS
14.1
Absolute Maximum Ratings*
Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO) (Note 14-1) . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.6V
Positive voltage on signal pins, with respect to ground (Note 14-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Negative voltage on signal pins, with respect to ground (Note 14-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V
Positive voltage on XI, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.6V
Positive voltage on XO, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.5V
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 14-4
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+/- 5kV
Note 14-1
When powering this device from laboratory or system power supplies, it is important that the absolute
maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp
circuit be used.
Note 14-2
This rating does not apply to the following pins: XI, XO, EXRES.
Note 14-3
This rating does not apply to the following pins: EXRES.
Note 14-4
0oC to +70oC for commercial version (LAN9313), -40oC to +85oC for industrial version (LAN9313I)
* Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 14.2, "Operating Conditions**", Section
14.4, "DC Specifications", or any other applicable section of this specification is not implied. Note, device signals are
NOT 5 volt tolerant.
14.2
Operating Conditions**
Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO)...........................................................+3.3V +/- 300mV
Ambient Operating Temperature in Still Air (TA) ................................................................................................ Note 14-4
** Proper operation of the LAN9313/LAN9313i is guaranteed only within the ranges specified in this section.
14.3
Power Consumption
This section details the power consumption of the LAN9313/LAN9313i. Power consumption values are provided for both
the device-only, and for the device plus the Ethernet components on ports 1 and 2.
TABLE 14-1:
SUPPLY AND CURRENT (10BASE-T FULL-DUPLEX)
Typical
(@ 3.3V)
Maximum
(@ 3.6V)
Unit
Supply current at 3.3V
(VDD33A1, VDD33A2, VDD33BIAS, VDD33IO)
135
155
mA
Power Dissipation (Device Only)
445
565
mW
Power Dissipation (Device and Ethernet components)
1140
1330
mW
25
Note 14-5
oC
Parameter
Ambient Operating Temperature in Still Air (TA)
DS00002288A-page 254
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE 14-2:
SUPPLY AND CURRENT (100BASE-TX FULL-DUPLEX)
Typical
(@ 3.3V)
Maximum
(@ 3.6V)
Unit
Supply current
(VDD33A1, VDD33A2, VDD33BIAS, VDD33IO)
230
270
mA
Power Dissipation (Device Only)
760
980
mW
Power Dissipation (Device and Ethernet components)
1045
1295
mW
25
Note 14-5
oC
Parameter
Ambient Operating Temperature in Still Air (TA)
Note 14-5
Note:
14.4
Over the conditions specified in Section 14.2, "Operating Conditions**".
Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements.
DC Specifications
TABLE 14-3:
I/O BUFFER CHARACTERISTICS
Parameter
Symbol
MIN
Low Input Level
VILI
-0.3
High Input Level
VIHI
Negative-Going Threshold
VILT
1.01
Positive-Going Threshold
VIHT
SchmittTrigger Hysteresis
(VIHT - VILT)
TYP
MAX
Units
Notes
IS Type Input Buffer
V
3.6
V
1.18
1.35
V
Schmitt trigger
1.39
1.6
1.8
V
Schmitt trigger
VHYS
345
420
485
mV
Input Leakage
IIN
-10
10
uA
Input Capacitance
CIN
3
pF
Low Output Level
VOL
0.4
V
IOL = 8mA
High Output Level
VOH
V
IOH = -8mA
Note 14-6
O8 Type Buffers
VDD33IO - 0.4
OD8 Type Buffer
VOL
0.4
V
IOL = 8mA
Low Output Level
VOL
0.4
V
IOL = 12mA
High Output Level
VOH
V
IOH = -12mA
V
IOL = 12mA
Low Output Level
O12 Type Buffer
VDD33IO - 0.4
OD12 Type Buffer
Low Output Level
0.4
VOL
Note 14-7
ICLK Type Buffer (XI Input)
Low Input Level
VILI
-0.3
0.5
V
High Input Level
VIHI
1.4
3.6
V
Note 14-6
This specification applies to all IS type inputs and tri-stated bi-directional pins. Internal pull-down and
pull-up resistors add +/- 50uA per-pin (typical).
Note 14-7
XI can optionally be driven from a 25MHz single-ended clock oscillator.
2008-2016 Microchip Technology Inc.
DS00002288A-page 255
LAN9313/LAN9313i
TABLE 14-4:
100BASE-TX TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
MIN
TYP
MAX
Units
Notes
Peak Differential Output Voltage High
VPPH
950
-
1050
mVpk
Note 14-8
Peak Differential Output Voltage Low
VPPL
-950
-
-1050
mVpk
Note 14-8
Signal Amplitude Symmetry
VSS
98
-
102
%
Note 14-8
Signal Rise and Fall Time
TRF
3.0
-
5.0
nS
Note 14-8
Rise and Fall Symmetry
TRFS
-
-
0.5
nS
Note 14-8
Duty Cycle Distortion
DCD
35
50
65
%
Note 14-9
Overshoot and Undershoot
VOS
-
-
5
%
Jitter
Note 14-8
Note 14-9
1.4
nS
Measured at line side of transformer, line replaced by 100 (+/- 1%) resistor.
Note 14-10
Offset from 16nS pulse width at 50% of pulse peak.
Note 14-10 Measured differentially.
TABLE 14-5:
10BASE-T TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
MIN
TYP
MAX
Units
Notes
Transmitter Peak Differential Output Voltage
VOUT
2.2
2.5
2.8
V
Note 14-11
Receiver Differential Squelch Threshold
VDS
300
420
585
mV
Note 14-11
14.5
Min/max voltages guaranteed as measured with 100 resistive load.
AC Specifications
This section details the various AC timing specifications of the LAN9313/LAN9313i.
Note:
The I2C timing adheres to the Philips I2C-Bus Specification. Refer to the Philips I2C-Bus Specification for
detailed I2C timing information.
Note:
The MII/SMI timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for
detailed MII timing information.
14.5.1
EQUIVALENT TEST LOAD
Output timing specifications assume the 25pF equivalent test load illustrated in Figure 14-1 below.
FIGURE 14-1:
OUTPUT EQUIVALENT TEST LOAD
OUTPUT
25 pF
DS00002288A-page 256
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
14.5.2
RESET AND CONFIGURATION STRAP TIMING
This diagram illustrates the nRST pin timing requirements and its relation to the configuration strap pins and output
drive. Assertion of nRST is not a requirement. However, if used, it must be asserted for the minimum period specified.
Please refer to Section 4.2, "Resets," on page 30 for additional information.
FIGURE 14-2:
NRST RESET PIN TIMING
trstia
nRST
tcss
tcsh
Configuration
Strap Pins
todad
Output Drive
TABLE 14-6:
NRST RESET PIN TIMING VALUES
Symbol
Description
MIN
TYP
MAX
Units
trstia
nRST input assertion time
200
S
tcss
Configuration strap pins setup to nRST deassertion
200
nS
tcsh
Configuration strap pins hold after nRST deassertion
10
nS
todad
Output drive after deassertion
30
nS
Note:
14.5.3
Device configuration straps are latched as a result of nRST assertion. Refer to Section 4.2.4, "Configuration Straps," on page 33 for details.
POWER-ON CONFIGURATION STRAP VALID TIMING
This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met.
FIGURE 14-3:
POWER-ON CONFIGURATION STRAP LATCHING TIMING
VDD33IO
2.0V
tcfg
Configuration Straps
TABLE 14-7:
POWER-ON CONFIGURATION STRAP LATCHING TIMING VALUES
Symbol
tcfg
Description
Configuration strap valid time
2008-2016 Microchip Technology Inc.
MIN
TYP
MAX
Units
15
mS
DS00002288A-page 257
LAN9313/LAN9313i
Note:
• Configuration straps must only be pulled high or low. Configuration straps must not be driven as inputs.
• Device configuration straps are also latched as a result of nRST assertion. Refer to Section 14.5.2, "Reset and
Configuration Strap Timing," on page 257 and Section 4.2.4, "Configuration Straps," on page 33 for additional
details.
14.5.4
MICROWIRE TIMING
This section specifies the Microwire EEPROM interface timing requirements. Please refer to Section 8.2.3, "Microwire
EEPROM," on page 89 for a functional description of this serial interface.
FIGURE 14-4:
MICROWIRE TIMING
tcsl
EECS
tcshckh
tckcyc
tckh
tckl
tcklcsl
EECLK
tckldis
tdvckh tckhdis
EEDO
tdsckh
tdhckh
EEDI
tdhcsl
tcshdv
EEDI (VERIFY)
TABLE 14-8:
MICROWIRE TIMING VALUES
Symbol
Description
MIN
TYP
MAX
Units
tckcyc
EECLK cycle time
1110
1130
nS
tckh
EECLK high time
550
570
nS
tckl
570
EECLK low time
550
tcshckh
EECS high before rising edge of EECLK
1070
nS
nS
tcklcsl
EECLK falling edge to EECS low
30
nS
tdvckh
EEDO valid before rising edge of EECLK
550
nS
tckhdis
EEDO disable after rising edge of EECLK
550
nS
tdsckh
EEDI setup to rising edge of EECLK
90
nS
tdhckh
EEDI hold after rising edge of EECLK
0
nS
tckldis
EECLK low to EEDO data disable
580
nS
tcshdv
EEDI valid after EECS high (VERIFY)
tdhcsl
EEDI hold after EECS low (VERIFY)
tcsl
EECS low
DS00002288A-page 258
600
nS
0
nS
1070
nS
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
14.5.5
SPI SLAVE TIMING
This section specifies the SPI slave interface timing requirements. Please refer to Section 8.4, "SPI Slave Operation,"
on page 97 for a functional description of this serial interface.
FIGURE 14-5:
SPI SLAVE TIMING
nSCS
tnscss
thigh
tnscsh
tlow
SCK
tsu thd
SI
tv
tdis
tho
SO
TABLE 14-9:
SPI SLAVE TIMING VALUES
Symbol
Description
MIN
TYP
MAX
Units
10
MHz
fsck
SCK clock frequency
thigh
SCK high time
40
nS
tlow
SCK low time
40
nS
tnscss
nSCS setup time
50
nS
tnscsh
14.6
nSCS hold time
80
nS
tsu
Data input setup time
10
nS
thd
Data input hold time
20
tv
Data output valid time
tho
Data output hold time
tdis
Data output disable time
nS
40
nS
40
nS
0
nS
Clock Circuit
The LAN9313/LAN9313i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should
be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XI/XO). See Table 14-10 for crystal specifications.
TABLE 14-10: LAN9313/LAN9313I CRYSTAL SPECIFICATIONS
Parameter
Symbol
MIN
Crystal Cut
Units
-
MHz
Notes
Fundamental Mode
Crystal Calibration Mode
2008-2016 Microchip Technology Inc.
MAX
AT, typ
Crystal Oscillation Mode
Frequency
NOM
Parallel Resonant Mode
Ffund
-
25.000
DS00002288A-page 259
LAN9313/LAN9313i
TABLE 14-10: LAN9313/LAN9313I CRYSTAL SPECIFICATIONS (CONTINUED)
Parameter
Symbol
MIN
NOM
MAX
Units
Notes
Ftol
-
-
+/-50
PPM
Note 14-12
Frequency Stability Over Temp
Ftemp
-
-
+/-50
PPM
Note 14-12
Frequency Deviation Over Time
Fage
-
+/-3 to 5
-
PPM
Note 14-13
-
-
+/-50
PPM
Note 14-14
-
7 typ
-
pF
Frequency Tolerance @
25oC
Total Allowable PPM Budget
Shunt Capacitance
CO
Load Capacitance
CL
-
20 typ
-
pF
Drive Level
PW
300
-
-
uW
Equivalent Series Resistance
R1
-
-
50
Ohm
Note 14-16
-
Note 14-17
oC
LAN9313/LAN9313i XI Pin
Capacitance
-
3 typ
-
pF
Note 14-15
LAN9313/LAN9313i XO Pin
Capacitance
-
3 typ
-
pF
Note 14-15
Operating Temperature Range
Note 14-12 The maximum allowable values for Frequency Tolerance and Frequency Stability are application
dependant. Since any particular application must meet the IEEE +/-50 PPM Total PPM Budget, the
combination of these two values must be approximately +/-45 PPM (allowing for aging).
Note 14-13 Frequency Deviation Over Time is also referred to as Aging.
Note 14-14 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3 as
+/- 50 PPM.
Note 14-15 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included
in this value. The XO/XI pin and PCB capacitance values are required to accurately calculate the
value of the two external load capacitors. These two external load capacitors determine the accuracy
of the 25.000 MHz frequency.
Note 14-16 0oC for commercial version (LAN9313), -40oC for industrial version (LAN9313I)
Note 14-17 +70oC for commercial version (LAN9313), +85oC for industrial version (LAN9313I)
DS00002288A-page 260
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
15.0
PACKAGE OUTLINES
15.1
128-VTQFP Package Outline
128-VTQFP, 14X14X1.0MM BODY, 0.4MM PITCH
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 15-1:
2008-2016 Microchip Technology Inc.
DS00002288A-page 261
LAN9313/LAN9313i
FIGURE 15-2:
128-VTQFP RECOMMENDED PCB LAND PATTERN
DS00002288A-page 262
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
128-XVTQFP Package Outline
128-XVTQFP 14X14X1.0MM BODY, 0.4MM PITCH
Note: For the most current package drawings,
see the Microchip Packaging Specification at
FIGURE 15-3:
2008-2016 Microchip Technology Inc.
http://www.microchip.com/packaging
15.2
DS00002288A-page 263
LAN9313/LAN9313i
APPENDIX A:
TABLE A-1:
DATA SHEET REVISION HISTORY
REVISION HISTORY
Revision Level & Date
DS00002288A (09-30-16)
Section/Figure/Entry
Correction
Replaces previous SMSC version Rev. 2.0 (02-14-13).
Rev. 2.0 (02-14-13)
Section 3.0, "Pin Description
and Configuration," on
page 15
Changed “Refer to the LAN9313/LAN9313i
application note for additional connection
information.” to “Refer to the LAN9313/LAN9313i
reference schematic for additional connection
information.” in the VDD18TX1, VDD18TX2,
VDD18PLL, VDD33IO, VDD18CORE, VDD33A1,
VDD33A2, and VDD33BIAS pin descriptions.
Rev. 1.9 (03-13-12)
Order Codes
Updated ordering codes to include tape and reel
options.
Rev. 1.8 (07-07-11)
Package Outlines
Updated 128-XVTQFP package dimensions and
figures.
Rev. 1.7 (06-29-10)
Table 3-6, “EEPROM Pins,”
on page 25
Added note to EE_SDA and EE_SCL pin
descriptions stating “If I2C is selected, an external
pull-up is required when using an EEPROM and is
recommended if no EEPROM is attached.”
Table 3-6, “EEPROM Pins,”
on page 25
Added note to EEDO/EEPROM_TYPE pin
descriptions stating “When not using a Microwire
or I2C EEPROM, an external pull-down resistor is
recommended on this pin.”
Section 13.1.7.4, "Virtual
PHY Identification LSB
Register (VPHY_ID_LSB),"
on page 165 and Section
13.2.2.4, "Port x PHY
Identification LSB Register
(PHY_ID_LSB_x)," on
page 180
Clarified default values using binary.
Section 13.3.2.23, "Port x
MAC Transmit Configuration
Register
(MAC_TX_CFG_x)," on
page 208
Note:
Table 6-1, “Switch Fabric
Flow Control Enable Logic,”
on page 48
Corrected rightmost column title to “TX FLOW
CONTROL ENABLE”
FIGURE 14-2: nRST Reset
Pin Timing on page 257
Updated figure shading.
Rev. 1.6 (08-19-09)
All
Standard SMSC formatting applied.
Rev. 1.5 (10-28-08)
Section 13.1.3.1, "EEPROM
Command Register
(E2P_CMD)," on page 133
Corrected CFG_LOADED bit type from “RO” to
“R/WC”
Section 14.6, "Clock
Circuit," on page 259
Changed max ESR value from 30 to 50 Ohms and
corrected typos in operating temperature range.
All
Fixed various typos
DS00002288A-page 264
Added note to IFG Config field description:
IFG Config values less than 15 are
unsupported.
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
TABLE A-1:
REVISION HISTORY (CONTINUED)
Revision Level & Date
Section/Figure/Entry
Rev. 1.3 (07-03-08)
Port x PHY Special
Control/Status Register
(PHY_SPECIAL_CONTROL
_STATUS_x) on page 188
Updated RESERVED bits 11:5 definition to
“RESERVED - Write as 0000010b, ignore on
read”, changed default to 0000010b, and made
field R/W.
Wake-Up Frame Detection
section of Host MAC
Chapter and MAC_CR
register description
Added note at end of WUFF section and to the
BCAST bit of the MAC_CR register stating:
When wake-up frame detection is enabled via the
WUEN bit of the HMAC_WUCSR register, a
broadcast wake-up frame will wake-up the device
despite the state of the Disable Broadcast Frames
(BCAST) bit in the HMAC_CR register.
HMAC_WUCSR register
Fixed error in GUE bit description: “....the MAC
Address [1:0] bits...” changed to “...the MAC
Address [0] bits....”.
Port x PHY Auto-Negotiation
Advertisement Register
(PHY_AN_ADV_x) on page
180
Bits 15 and 9 made RESERVED.
Section 14.6, "Clock
Circuit," on page 259
Changed minimum drive level from 0.5mW to
300uW
2008-2016 Microchip Technology Inc.
Correction
DS00002288A-page 265
LAN9313/LAN9313i
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
DS00002288A-page 266
2008-2016 Microchip Technology Inc.
LAN9313/LAN9313i
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
[X]
Temperature
Range
-
XXX
-
Package
Device:
LAN9313, LAN9313i
Temperature Range:
Blank
i
Package:
NU
=
NZW =
[X](1)
Tape and Reel
Option
Examples:
a)
b)
c)
d)
=
0C to
= -40C to
+70C
+85C
(Commercial)
(Industrial)
e)
f)
128-pin VTQFP
128-pin ZVTQFP
LAN9313-NU, Commercial temp
128-pin VTQFP, Tray
LAN9313-NZW, Commercial temp
128-pin XVTQFP, Tray
LAN9313i-NZW, Industrial temp
128-pin XVTQFP, Tray
LAN9313-NU-TR, Commercial temp
128-pin VTQFP, Tape & Reel
LAN9313-NZW-TR, Commercial temp
128-pin XVTQFP, Tape & Reel
LAN9313i-NZW-TR, Industrial temp
128-pin XVTQFP, Tape & Reel
Note 1:
Tape and Reel Option:
Blank
TR
= Standard packaging (tray)
= Tape and Reel(1)
2008-2016 Microchip Technology Inc.
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
DS00002288A-page 267
LAN9313/LAN9313i
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch,
Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2008-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522409847
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS00002288A-page 268
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2008-2016 Microchip Technology Inc.
Worldwide Sales and Service
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DS00002288A-page 269
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