™
Le5712
Dual Subscriber Line Interface Circuit
VE580 Series
APPLICATIONS
DESCRIPTION
Ideal for low-cost, high performance line card
applications (CO, DLC)
Meets requirements for countries such as: India,
China, Korea, Japan, Taiwan, and Australia
Meets requirements for North America DLC
applications (TR-57-CORE)
FEATURES
Dual-Channel SLIC device with small footprint
Loop start and Ground start support
+5 V and battery supply required
Optional dual battery operation
–39 to –60 V battery operation
Supplies more than 20 mA into 2000 Ω from –48 V
Programmable current limit
On-chip Thermal Management (TMG) feature in all
Active states
Low standby power (24 mW per channel)
Supports 2.0 Vrms metering applications
Control states: Active and Active Metering (Normal and
Reverse Polarity), Standby, Tip Open and Disconnect
3.3-V compatible to logic control inputs
The innovative Le5712 dual-channel SLIC device is designed
for high-density POTS applications requiring a small-footprint,
low-power SLIC device. By combining a fully featured line
interface of two channels into one SLIC device, the Le5712
device enables the design of a low-cost, high performance, and
fully programmable line interface for multiple country
applications worldwide, including Ground Start and metering
capability. The on-chip Thermal Management (TMG) feature
allows for significantly reduced power dissipation on the
device. Optional dual battery operation to reduce total power
consumption is also available. The device is offered in a
thermally efficient, space-saving 44-pin eTQFP package. The
12 x 12 mm footprint allows designers to make a dramatic
increase in the density of lines on a board. The Le5712 device
is also designed to significantly reduce the number of external
components required for line card design.
Zarlink offers a range of compatible SLAC™ devices that
perform the codec function in a line card. In particular, the
Zarlink Quad and Octal SLAC devices combined with the
Le5712 device provides a programmable line circuit that can
be configured for varying requirements.
RELATED LITERATURE
081110 Thermal Management for the Le5711 and
Le5712 SLIC Devices Application Note
080900 Le5711 and Le5712 Comparison Brief
Power up in Disconnect state
Application Note
On-hook transmission in Active states
Per-channel fault detection and indication
Per-channel thermal shutdown
Programmable Off Hook and Ground Start thresholds.
Programmable ring-trip detect threshold
080753 Le58QL02/021/031 QLSLAC™ Data Sheet
080754 Le58QL061/063 QLSLAC™ Data Sheet
080921 Le58083 Octal SLAC™ Data Sheet
080676 Le5711 Dual SLIC Data Sheet
Footprint compatible with Zarlink’s Le5711 Dual SLIC
FLT 1
C3 1
C2 1
C1 1
DET 1
RD
CAS
IREF
C1 2
DET 2
C3 2
Tray
TMG 1
CH1
2-W
Interface
CH1
CH1
CH1
HP 1
CH1
Signal
Transmission
CH2
Power Feed
Controller
CH2
Off-Hook &
Ground Start
Detector
RSN 2
CH2
Ring Trip
Detector
CH2
VTX 2
AD 1
BD 1
BD 2
Ring Trip
Detector
BGND 2
VTX 1
RSN 1
Document ID# 081047 Date:
Rev:
G
Version:
Distribution:
Public Document
AGND/
DGND
CDC 1
VCC
BGND 1
DB 1
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
CH1
Input
Decoder
and Control
Common
Bias
DAC
2.
HP 2
CH2
2-W
Interface
DB 2
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
AD 2
Off-Hook &
Ground Start
Detector
1.
CH2
Input
Decoder
and Control
TMG 2
VBREF
44-pin eTQFP (Green),
–63 dB, Reverse Polarity
CH1
Fault
Detector
Power Feed
Controller
Le57D122BTC
CH2
Fault
Detector
CDC 2
Le57D121BTC
44-pin eTQFP (Green),
–53 dB, Reverse Polarity
Packing2
Signal
Transmission
Package Type1
VBAT
Device
FLT 2
ORDERING INFORMATION
C2 2
BLOCK DIAGRAM
120402
Sep 18, 2007
2
Le5712
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Signal Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Power Feed Controller and Common Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Input Decoder and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Device State Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Off-Hook Detector (OHD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ground Start Detector (GSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ring-Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Fault Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Summary of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Supply Currents and Power Dissipation (on-hook) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Device specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
POTS Application Circuit (POTS with no metering). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Application Circuit Parts List (Pots with no metering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Pulse Metering Application Circuit (Pots with metering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Application Circuit Parts List (Pots with metering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision E1 to F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision F1 to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision G1 to G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2
Zarlink Semiconductor Inc.
Le5712
Data Sheet
PRODUCT DESCRIPTION
The Le5712 device is designed for long loop high-density POTS applications requiring a low power, small footprint SLIC device.
The Le5712 device increases line card density by integrating two SLIC devices into a single 44-pin package. This reduction in
board space permits a higher density line card, which allows for amortizing common hardware across more channels. The
Le5712 device gives line card designers a simple control interface that supports seven states: Active, Active Metering, Reverse
Polarity, Reverse Polarity Metering, Standby, Tip Open and Disconnect (Ringing). The low cost and high performance Le5712
device provides the key features for POTS markets requiring loop start, loop start and metering, or ground start. The device
includes a thermal management feature for minimizing power dissipation on the SLIC. Alternatively, the device can be operated
in a dual battery configuration to reduce overall power consumption.
BLOCK DESCRIPTIONS
Two-Wire Interface
The two-wire interface provides DC current and sends voice and signalling information to a customer premise equipment. The
two-wire interface also receives the returning signals from the customer premise equipment.
This block implements the thermal management feature, which allows power that would otherwise be dissipated within the
package to be off loaded into an external resistor when the line is Off Hook. RTMGi is connected from TMGi to the VBAT pin and
limits power within the SLIC device (Note: "i" denotes channel number).
The minimum value of RTMGi is given by:
BAT MAX – 6 – I LIMITMIN ⋅ ( 2 • R F + R LMIN + 40Ω )
R TMG ≥ ---------------------------------------------------------------------------------------------------------------------------------I LIMITMIN – 3 mA
where ILIMITMIN is the minimum programmed loop current limit and RLMIN is the minimum loop resistance. The tolerance of RTMG
should be taken into account when selecting a value that meets this requirement. For example, if BATMAX = -56 V, ILOOPMIN = 30
mA and RLMIN = 200 Ω then RTMG = 1.5 kΩ is the minimum recommended value. A value of 1.8 kΩ with 5% accuracy will keep
the power in RTMG below 1.0 W, and the total worst case SLIC power dissipation with both channels active below 1.6 W.
The power dissipated in the TMG resistor is given by:
2
( BAT – 5 – I L • ( R L + 2R F + 40 ) )
P RTMG = -----------------------------------------------------------------------------------------R TMG
where IL is the loop current, and RL is the loop resistance.
The maximum power on RTMG is given by:
2
( BAT max – 5 – I LIMITmin ( R Lmin + 2R F + 40 ) )
P RTMGmax = --------------------------------------------------------------------------------------------------------------------------R TMGmin
And the power dissipated per channel in the SLIC device while in the Active states is given by:
I
P SLICi = 0.003 BAT + ( BAT – 3 – I L ( R L + 2R F + 40 ) ) I L – --------------- ( BAT – 5 – I L ( R L + 2R F + 40 ) )
R TMG
The maximum power dissipated per channel in the SLIC device while in the Active states is given by:
I LIMITmax
P SLICmaxi = 0.003 BAT max + 1 + ------------------------- R TMGmax
2
I LIMITmax
1
------------------------ + -----------------------
2
R
TMGmax
Refer to the Thermal Management for the Le5711 and Le7512 Dual SLIC Devices Application Note for further analysis and for
dual battery condition.
The AC signal swing supported by the two-wire interface is controlled by the SLIC state. For standard voice transmission, the
Active and Reverse Polarity states are used. To support voice plus meter pulses, the Active Metering and Reverse Polarity
Metering states are provided which have increased overhead to support 2.0 Vrms metering.
3
Zarlink Semiconductor Inc.
Le5712
Data Sheet
Signal Transmission
The RSNi input current controls the receive current sent to the two-wire interface. The AC line voltage is sensed by a differential
amplifier between the ADi and HPi leads. The output of this amplifier is equal to the AC metallic components of the line voltages
and is output at VTXi.
The desired two-wire AC input impedance, Z2WIN, is defined by the fuse resistors, RF, and an impedance connected from VTXi
to RSNi, ZTi. When computing ZTi, the internal current amplifier pole and any external stray capacitance between VTX and RSN
must be taken into account.
500
Z Ti = --------- ⋅ ( Z 2WIN – 2R F )
3
To set the desired receive gain (G42L) into a load ZL from VRXi, ZRXi is connected from VRXi to RSNi, where
ZL
500 • Z T
Z RXi = ------------- • --------------------------------------------------G 42L
500
Z T + --------- ( Z L + 2R F )
3
The transmission block also contains a longitudinal feedback circuit to shunt longitudinal signals to a DC bias voltage. The
longitudinal feedback does not affect metallic signals.
Two application circuits, provided at the end of this data sheet, show how the Le5712 device can connect directly to pins of a
QLSLAC codec.
The POTS Application Circuit (POTS with no metering), on page 18 shows an application providing Loop Start and Ground
Start capability. The components selected for the transmission network allow a wide range of market transmission requirements
to be met when combined with the programmable QLSLAC device. In addition, transmit relative levels of Li = +4 to -4 dBr and
receive relative levels of Lo = 0 to -8dBr can be supported using only the digital gain within the QLSLAC device for all markets.
This configuration will meet ITU Q.552 and GR57 requirements.
The Pulse Metering Application Circuit (Pots with metering), on page 20 shows a configuration for use in a 12 or 16 kHz
pulse metering application with the QLSLAC device. The design allows 2 Vrms into 200 Ω, and supports gain ranges of at least
Li = 0 to +4dBr, and Lo = 0 to -8 dBr. This configuration will meet ITU Q.552 requirements over these gain ranges for markets
such as India and China.
The relationship between metering source VM, the feeding resistance, RM, and the output voltage at tip-ring, VTR, is given in the
following equation. The load at tip-ring is RM. RF is the protection and other, if any, front-end resistances. ZT is the impedance
between VTX and RSN at metering frequency.
ZM
500
- • ------------------------------------------------- V M
V TR = ------Z M + 2R F
RM
500
1 + --------- • -----------------------3
ZT
Metering signal at VTX needs to be filtered to prevent from overloading the codec. This has been realized in the applications
circuitry in this document.
Power Feed Controller and Common Bias
The power feed controllers have three sections: (1) the common bias circuit, (2) the battery feed circuit, and (3) the reverse
polarity circuit which operate in all Active states.
The bias circuit provides a signal which sets the current limit and creates a voltage related to VBAT, filtered by a capacitor
connected to the CAS pin, to the battery feed circuit.
470
The nominal current limit is set by the following equation: I
-------------LIMIT = R
REF
1
A recommended 3 Hz filter pole frequency (fc) can be implemented from: C
CAS = ----------------------------------------RI AS • 2 • π • f c
The battery feed circuit regulates the amount of DC current and voltage supplied to the telephone over a wide range of loop
resistance. It is designed to operate over a nominal 22 to 33 mA range of programmed current limit. It produces a filtered
reference voltage offset from the subscriber line voltage which is applied to the two-wire interface.
In addition, a low pass filter is implemented with a capacitor connected to the CDCi pin.
In the low power Standby state, an alternative feed is implemented via two current limited on chip 200-Ω resistors. The nominal
loop current below current limit in the Standby state is given by:
V BAT – 4 V
I STANDBY = ------------------------------600 Ω + R L
4
Zarlink Semiconductor Inc.
Le5712
Data Sheet
Input Decoder and Control
The input decoder and control block provides a means for a microprocessor or SLAC device IC to control such system states as
Active, Active Metering, Reverse Polarity, Reverse Polarity Metering, Standby, Tip Open and Disconnect (Ringing). The input
decoder and control block has TTL-compatible inputs, permitting interfacing to 5 or 3.3 V VCC controllers which set the operating
states of the SLIC device. It also provides the loop supervision signal sent back to the controller.
From power up, the device is in disconnect state unless over-written by external control inputs.
Device State Decoding
(For channel i = 1 or 2)
State
C3i
C2i
C1i
Two-Wire state
DETi output
0
0
0
0
Reserved
N/A
1
0
0
1
Active Metering
OHD
2
0
1
0
Tip Open
GSD
3
0
1
1
Reverse Polarity Metering
OHD
4
1
0
0
Disconnect
RTD
5
1
0
1
Active
OHD
6
1
1
0
Standby
OHD
7
1
1
1
Reverse Polarity
OHD
Off-Hook Detector (OHD)
The On-to-Off-hook and Off-to-On-hook detections are based on loop current and are defined as |IAD - IBD| / 2. The On-to-Offhook (OHD) and Off-to-On-hook (OND) thresholds are programmed with the RD resistor and the threshold applies to all Active
and Standby states.
935V
I OHD = ------------RD
I OHD = I OND + Hysteresis
Upon the loss of battery the DET pin will be HIGH.
Off-hook detection or DET state should be ignored during on-hook metering.
Ground Start Detector (GSD)
This detector is active in the Tip Open state. The threshold, IGSD, is defined by the same equation used for the OHD.
For ground start lines, the device is in the Tip Open state between calls. When a ring ground condition is detected, the device
should be switched to the Active state. During this period, the DET pin will be active if the ring to ground current is greater than
twice the IOHD threshold. The DET pin will go active once the ring ground is removed and a loop is applied. It is recommended
that a firmware time-out period is applied in case the call attempt is abandoned and DET never goes low. The time-out is reset
once an active DET is seen in the Active state.
Ring-Trip Detector
In the Disconnect state, the ring-trip detector is active. While the DBi pin is more negative than the DAC pin, the DET pin will be
High to indicate on hook. When an off hook condition occurs, the DBi pin becomes more positive than the DAC pin, and the DET
pin will go Low to indicate off hook during ringing (ring-trip) has been detected. The system implements the Ringing state using
external control of a ring relay in combination with the Disconnect SLIC device state, which enables the ring-trip detector.
The POTS Application Circuit (POTS with no metering), on page 18 shows a ring trip bridge configured and components
are selected for a typical battery-backed ringing applications such as for the US (TR-57) and China (GF002).
The Pulse Metering Application Circuit (Pots with metering), on page 20 shows a ring trip bridge configured and
components are selected for a typical earth-backed ringing applications such as in India (G/LLT and G/MLT).
Fault Detector
The DSLIC device provides a fault detection function in the Active states on each channel. Under a fault condition the detector
senses longitudinal voltage at tip and ring and flags a fault by pulling the FLTi pin Low. The FLTi pins are compatible with logic
outputs, and may be monitored to clearly identify a fault condition from a loop condition.
In case of low level longitudinal AC induction the FLTi may pulse at twice the frequency of the induction signal.
Upon the loss of battery the FLT pin will be LOW.
5
Zarlink Semiconductor Inc.
Le5712
Data Sheet
Thermal Shutdown.
Thermal shutdown is provided on a per channel basis to protect the die from excessive temperature. Persistent faults will produce
high power dissipation, and may result in the affected channel triggering its thermal shutdown detector (Minimum > 145º C). At
this point the power amplifiers are turned off and the device is in a disconnect like state, FLT and DET will be active. The thermal
shutdown detector has approximately 10º C of hysteresis. Thermal shutdown on one channel will not affect the operation of the
other channel.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout.The thermal
pad at the bottom of the package should be soldered down to printed circuit board. Refer to the Thermal Management for the
Le5711 and Le7512 Dual SLIC Devices Application Note for details.
TMG 1
HP 1
NC
FLT 1
VBREF
NC
VTX 1
NC
RSN 1
CDC 1
DET 1
CONNECTION DIAGRAM
44 43 42 41 40 39 38 37 36 35 34
C21
1
33
BGND 1
C11
2
32
BD 1
C3 1
3
31
AD 1
AGND/DGND
4
30
DB 1
VCC
5
29
DAC
RD
6
28
NC
CAS
7
27
VBAT
IREF
8
26
DB 2
C12
9
25
AD 2
C22
10
24
BD 2
DET 2
11
23
BGND 2
44-Pin eTQFP
Exposed Pad
TMG 2
HP 2
NC
FLT 2
NC
NC
VTX 2
NC
RSN 2
C3 2
CDC 2
12 13 14 15 16 17 18 19 20 21 22
120402
Note:
1.
Pin 1 is marked for orientation.
2.
NC = No Connect
3.
The exposed heat sink pad on the bottom of the eTQFP package should be connected to VBAT pin - the SLIC side of the diode from battery
supply. Do not connect it to GND.
6
Zarlink Semiconductor Inc.
Le5712
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
AD1
Output
Description
Output of AD power amplifier of channel 1.
AD2
Output
Output of AD power amplifier of channel 2.
AGND/DGND
Ground
Analog and digital ground.
Output of BD power amplifier of channel 1.
BD1
Output
BD2
Output
Output of BD power amplifier of channel 2.
BGND1
Ground
Battery (power) ground of channel 1
BGND2
Ground
Battery (power) ground of channel 2.
C11/C21/C31
Input
C12/C22/C32
Input
State decoder inputs of channel 1.
CAS
Capacitor
Pin for capacitor to filter reference voltage when operating in anti-saturation region.
CDC1
Capacitor
DC feed filter capacitor of channel 1.
CDC2
Capacitor
DC feed filter capacitor of channel 2.
FLT1
Output
Channel 1 fault detector output1.
FLT2
Output
Channel 2 fault detector output1.
DAC
Input
Ring-trip negative of both channels. Negative input to ring-trip comparator.
DB1
Input
Ring-trip positive of channel 1. Positive input to ring-trip comparator.
DB2
Input
Ring-trip positive of channel 2. Positive input to ring-trip comparator.
State decoder inputs of channel 2.
DET1
Output
DET2
Output
HP1
Capacitor
HP2
Capacitor
Connect a High-Pass filter capacitor in series with a resistor from HP2 to BD2.
Resistor
Connection for reference resistor that programs Off Hook Detector threshold and DC feed
current limit of both channels.
IREF
NC
—
RD
Resistor
Off Hook / Ring-trip detector output of channel1. Logic low indicates that a detector is tripped.
Off Hook / Ring-trip detector output of channel 2. Logic low indicates that a detector is tripped.
Connect a High-Pass filter capacitor in series with a resistor from HP1 to BD1.
No Connect. This pin is not internally connected.
Connection for resistor that programs off hook detector threshold of both channels.
Input
Receive Summing Node of channel 1. In the Active and Reverse Polarity states, the current
(both AC and DC) between AD1 and BD1 is equal to 500 times the current into this pin. The
networks that program receive gain, metering gain and two-wire impedance of Channel 1
connect to this node.
RSN2
Input
Receive Summing Node of channel 2. In the Active and Reverse Polarity states, the current
(both AC and DC) between AD2 and BD2 is equal to 500 times the current into this pin. The
networks that program receive gain, metering gain and two-wire impedance of Channel 2
connect to this node.
TMG1
Output
Thermal management of channel 1. External resistor connects from TMG1 to VBAT to off-load
power from the SLIC device.
TMG2
Output
Thermal management of channel 2. External resistor connects from TMG2 to VBAT to off-load
power from the SLIC device.
VBAT
Battery
Battery supply and connection to substrate. Connect to highest negative supply with a diode
on a per line base.
RSN1
VBREF
Input
This is a Zarlink reserved pin and must always be connected to the VBAT pin.
VCC
Power
+5 V power supply.
VTX1
Output
Transmit audio signal of channel 1. This output is a scaled version of the A and B metallic
voltage. VTX1 also sources the two-wire input impedance programming network.
VTX2
Output
Transmit audio signal of channel 2. This output is a scaled version of the A and B metallic
voltage. VTX2 also sources the two-wire input impedance programming network.
EPAD
Battery
The exposed heat sink pad on the bottom of the eTQFP package should be connected to
VBAT pin - the SLIC side of the diode from battery supply. This thermal pad should also be
soldered down to printed circuit board to achieve the desired package thermal performance.
Note:
1.
Consult Zarlink representatives for proper handling when not in use.
7
Zarlink Semiconductor Inc.
Le5712
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability
Storage temperature
VCC with respect to AGND / DGND
–55 to +150º C
–0.4 to +7.0 V
VBAT with respect to AGND / DGND
+0.4 to –63 V
BGND1, BGND2 with respect to AGND / DGND
+3 to –3 V
AD1, AD2, BD1, BD2 with respect to BGND:
VBAT to + 1 V
Continuous
10 ms (F = 0.1 Hz)
1 µs (F = 0.1 Hz)
250 ns (F = 0.1 Hz)
Current from AD1, AD2, BD1, BD2
–70 to +5 V
–80 to +8 V
–90 to +12 V
±150 mA
DB1, DB2, and DAC inputs:
VBAT to 0 V
Voltage on ring-trip inputs
Current into ring-trip inputs
C11, C21, C31, C12, C22, C32
±10 mA
Input Voltage
Maximum power dissipation in 44-pin eTQFP
TA = 70º C, continuous
–0.4 to VCC + 0.4 V
(see note 1)
Thermal Data in 44-pin eTQFP package
Junction to Ambient, θJA
(see note 2)
ESD Immunity (Human Body Model)
JESD22 Class 1C compliant
Notes:
1.
2.
Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165º C. Continuous operation above 145º C
junction temperature may degrade device reliability. Refer to the Thermal Management for the Le5711 and Le7512 Dual SLIC Devices Application
Note for details.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Refer to the Thermal
Management for the Le5711 and Le5712 Dual SLIC Devices Application Note for details.
Package Assembly
Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
The operating ranges specified below define those limits between which the device operates and is guaranteed under the noted
test conditions. (Refer to Summary of Test Conditions, on page 9.)
Environmental Ranges
Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (−40 to 85º C) temperature ranges
by conducting electrical characterization, production testing, and periodic sampling over each range. These characterization and
test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for
Telecommunications Equipment.
−40° to 85°C
15% to 85%
Ambient Temperature
Ambient Relative Humidity
Electrical ranges
VCC
4.75 to 5.25 V
–39 to –60 V
VBAT to –2 V
VBAT
DB1, DB2, and DAC
AGND
BGND1, BGND2 with respect to AGND/DGND
0V
–100 to + 100 mV
Load resistance on VTX1, VTX2 to ground
8 kΩ minimum
8
Zarlink Semiconductor Inc.
Le5712
Data Sheet
ELECTRICAL CHARACTERISTICS
Summary of Test Conditions
Unless otherwise noted, the test conditions are defined by the Le5712 device test circuit shown in Figure 7, on page 17 with:
VCC=5 V, BAT = -52 V, RL = RLAC = 600 Ω, RREF = 14.3 kΩ, RD = 82.5 kΩ.
Supply Currents and Power Dissipation (on-hook)
ICC mA (Note 1.)
Operational State
Min.
Typ
IVBAT mA (Note 1.)
Max
Min.
Typ
SLIC Device Power mW
Max
Min.
Typ
Max
Disconnect
3.2
5.5
0.5
0.8
42
62
Standby
3.2
6.5
0.6
1.0
46
70
Tip Open
3.1
6.5
0.6
1.0
46
70
Active
9.0
13
6.0
10.0
353
540
Reverse Polarity
9.0
13
6.0
10.0
353
540
Active Metering
9.3
13
6.0
10.0
355
540
Reverse Polarity
Metering
9.3
13
6.0
10.0
355
540
One channel Standby
One channel Active
6.1
10
3.3
5.5
200
305
Note
2
SPECIFICATIONS
Device specifications
Specification
Condition
Min.
Typ
Max
Active
42.75
45.7
48
Standby
46.75
42.5
Unit
Note
Line Characteristics
VAB, Open Circuit
52
V
Metering states
38
41.5
IL, Long Loops, Active state
RLDC= 2000 Ω, BAT = -48 V
20
20.5
ILIMIT, Short Loops, Active state
RLDC= 100 Ω to 1100 Ω
30
33
IL, Long Loops, Active state
RLDC= 2125 Ω
20
21.1
mA
IL, Long Loops, Active state
RLDC= 2125 Ω, BAT = -46.5 V
18
18.5
mA
0.9IL
IL
20
30
45
85
120
mA
µA
IL, Accuracy, Standby state
BAT – 4V
I L = ------------------------------ , R LDC ≥ 2000Ω
( RL + 600 )
Current Limited Region
ILLIM, AD and BD to BGND
Active, IAD + IBD
mA
36
1.1IL
mA
3
mA
IL, Loop current, Disconnect state
RL = 0 Ω
100
IAD leakage, Tip Open state
RL = 0 Ω
100
µA
IBD current, Tip Open state
BD to BGND
45
mA
VAD Active and Standby states
AD to BAT=7 kΩ, BD to GND=100Ω
20
30
-7.5
-5
VIREF, IREF pin output voltage
1.2
1.25
1.3
V
K1, Incremental RSN current gain
490
500
510
A/A
V
Power Supply Rejection Ratio at the Two-Wire Interface (Active states, On or Off Hook)
VCC
50 Hz to 3.4 kHz
VRIPPLE = 100 mVrms
VBAT
300 Hz to 3.4 kHz
VRIPPLE = 100 mVrms
RIAS, Effective internal resistance
30
40
28
50
50 Hz to 60 Hz
20
CAS pin to AGND
90
9
Zarlink Semiconductor Inc.
150
210
dB
4
kΩ
2
Le5712
Specification
Condition
Data Sheet
Min.
Typ
Max
Unit
Note
–63
-67
dB
–60
-64
dB
–60
-67
dB
2
–57
-64
dB
2
Longitudinal Capability (See Figure 4, on page 16.)
Longitudinal to metallic L-T balance
Normal polarity
200 Hz to 1.0 kHz, Le57122
0º C to +70º C
Longitudinal to metallic L-T balance
Normal polarity
3.0 kHz, Le57122
0º C to +70º C
Longitudinal to metallic L-T balance
Normal polarity
200 Hz to 1.0 kHz, Le57122
-40º C to +85º C
Longitudinal to metallic L-T balance
Normal polarity
3.0 kHz, Le57122
-40º C to +85º C
Longitudinal to metallic L-T balance
0º C to +70º C
–53
-40º C to +85º C
–50
Longitudinal signal generation 4-L
200 Hz to 3.4 kHz
40
dB
Longitudinal current per pin (ADi or
BDi)
Active state (off hook)
8.5
mArms
Longitudinal impedance at ADi or BDi
0 to 100 Hz
200 Hz to 3.0 kHz, Le57121
Longitudinal to metallic L-T balance
200 Hz to 3.0 kHz, Le57121
dB
2
5
Ω /pin
18.5
RFI Rejection (See Figure 6, on page 16.)
VTX1 or VTX2
f =.01 to 100 MHz
HF gen. output = 1.5 Vrms
CAXi = CBXi = 33 nF
1
CAXi = CBXi = 2.2 nF
3
mVrms
2
dB
2, 6
25
Ω
2
+50
mV
Transmission Performance
2-wire return loss
200 Hz to 3.4 kHz (See Figure 5, on
page 16)
26
Analog output (VTX) impedance
3
Analog (VTX) output offset voltage
–50
Overload level, 2-wire
Active or Reverse Polarity state
2.5
Overload level, 2-wire
On hook, Active or Reverse Polarity
state
1.1
Overload level, 2-wire
Metering states
5.5
Overload level, 2-wire
On hook, Metering states
5.5
THD (Total Harmonic Distortion)
7
Vpk
7
8
0 dBm
–64
–50
+7 dBm
–55
–40
+9 dBm, Metering states
-55
-40
THD, On hook
0 dBm, RLAC = 600 Ω
–36
THD with metering
RL = 300 Ω
–35
Idle Channel Noise
Idle Channel Noise with Metering
C-Message, RL = 600 Ω
Psophometric, RL = 600 Ω
8
7
12
-83
-78
Psophometric, RL = 300 Ω,
-46
Metering states
dB
4
2, 9
dBrnC
dBmp
2
2, 10
Crosstalk Between Channels
Crosstalk coupling loss
Averaged over 200 Hz to 3.4 kHz,
0dBm
10
Zarlink Semiconductor Inc.
80
dB
11
Le5712
Specification
Condition
Data Sheet
Min.
Typ
Max
Unit
Note
Insertion Loss (See Figure 2 and Figure 3, on page 15.)
Gain, 4-to-2-wire
0 dBm, 1 kHz
–0.20
0
+0.20
Gain KTX, 2-to-4-wire
0 dBm, 1 kHz
–9.74
–9.54
–9.34
Gain, 4-to-4-wire
0 dBm, 1 kHz
–9.74
–9.54
Gain, 4-to-2-wire
On hook
–0.35
+0.35
Gain over frequency
300 to 3400 Hz, relative to 1 kHz
–0.15
+0.15
Gain tracking
+3 to –55 dBm, relative to 0 dBm
–0.15
+0.15
Gain tracking, On hook
0 dBm to –37 dBm
+3 dBm to 0 dBm
–0.15
–0.35
+0.15
+0.35
Metering Gain, 4-to-2-wire
VM = 0.5 vrms, 16 kHz, RL = 300 Ω
15.1
15.6
–9.34
16.1
dB
2
dB
12
Logic Interface
Inputs (C11, C12, C21, C22, C31 and C32)
VIH, Input High voltage
2.0
VIL, Input Low voltage
0.8
IIH, Input High current
VIH=2.0V
–110
IIL, Input Low current
VIL=0.8V
–400
90
V
µA
Outputs (DET1 and DET2)
VOL, Output Low voltage
IOUT = 0.3 mA
VOH, Output High voltage
IOUT = –0.1 mA
0.40
2.4
V
Outputs (FLT1 and FLT2)
VOL, Output Low voltage
IOUT = 0.06 mA
VOH, Output High voltage
IOUT = –0.01 mA
0.40
2.4
V
Ring-Trip Detector Input (Applies to DAC, DB1 and DB2.)
Bias Current
Offset voltage
Source resistance = 2 MΩ
–50
–10
0
nA
2
–50
0
+50
mV
13
–2
V
2
mA
VBAT + 1
Common Mode Voltage Range
Fault Detector (See Figure 1, on page 15.)
IFAULT = |IAD + IBD|
8
11.5
20
Off-Hook and Ground Start Detectors (See Figure 1, on page 15.)
IOHD On-to-Off hook Detection
Threshold
Active and Standby states
9.8
11.5
13.2
Hysteresis
The difference between On-to-Off
hook detection threshold and Off-toOn hook Detection threshold
1.3
2.0
2.7
IGSD, Ground Start Detect threshold
(On-to-Off hook detection threshold)
Tip Open state
11.8
13.5
16.0
Hysteresis (Ground Start)
The difference between On-to-Off
hook detection threshold and Off-toOn hook detection threshold
2.6
4.0
5.4
11
Zarlink Semiconductor Inc.
mA
Le5712
Data Sheet
Notes:
1.
Total current measured with both channels in the same state, unless otherwise specified.
2.
Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
3.
Typical current limit range is designed to be between 22 mA and 33 mA.
4.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
5.
Minimum current level guaranteed not to cause a false loop detect. The fault detector may activate with longitudinal currents above 2.8 mA
rms, and may pulse at twice the frequency of the interfering signal.
6.
Group delay can be greatly reduced by using a ZT network such as that shown in Figure 5, on page 16 where CT = 120 pF, RTA = RTB = 50
kΩ. The network reduces the group delay to less than 2 µs and increases 2WRL. The effect of group delay on line card performance also
may be compensated by synthesizing complex impedance with the QLSLAC™ or Octal SLAC™ devices.
7.
Overload level is defined as THD = 1%,
8.
Overload level is defined as THD = 1.5%.
9.
Total Harmonic distortion with metering is specified with a metering signal of 3.0 Vrms at the two-wire output, and a transmit signal of +3
dBm or receive signal of –4 dBm. The transmit or receive signals are single frequency inputs, and the distortion is measured as the highest
in band harmonic at the two-wire or the four-wire output relative to the input signal.
10. Noise with metering is measured by applying a 3.0 Vrms metering signal (measured at the two-wire output) and measuring the psophometric
noise at the two-wire outputs over a 200 ms time interval
11. This is test at 1 kHz in production
12. In the test set up, ZT = 100 kΩ, RM = 16.5 kΩ, and RF = 0 Ω. The output voltage at tip/ring is expected to be 3 Vrms, into a load of 300 Ω,
with 0.5 Vrms source. The typical gain is 15.6 dB.
13. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
12
Zarlink Semiconductor Inc.
Le5712
Data Sheet
User-Programmable Components Summary
Equation
Description
ZTi* is connected between the VTX and
RSN pins. The fuse resistors are RF, and
Z2WIN is the desired 2-wire AC input
impedance. When computing ZTi, the
internal current amplifier pole and any
external stray capacitance between VTX
and RSN must be taken into account.
500
Z Ti = --------- ( Z 2WIN – 2R F )
3
Z RXi
ZRXi* is connected from VRX to RSN. ZTi is
defined above, and G42L is the desired
receive gain.
500 • Z T
ZL
= ------------- • ------------------------------------------------------G 42L
500
Z T + --------- ⋅ ( Z L + 2R F )
3
470 ⋅ V
R REF = -----------------I LIMIT
ILIMIT is the desired loop current limit in the
constant-current region.
1
C CAS = ----------------------------------RI AS • 2π • f c
CCAS is the regulator filter capacitor and fc is
the desired filter cut-off frequency.
935 ⋅ V
I OHD = I GSD = ----------------RD
Off Hook Detect (IOHD) and Ground Start
Detect (IGSD) thresholds are typically set at
10 to 12 mA.
V BAT – 4 V
I STANDBY = ------------------------------600 Ω + R L
Standby loop current (resistive region).
Thermal Management Equations (All Active states for one channel) (Please refer to the Thermal Management for the Le5711 and Le7512 Dual
SLIC Devices Application Note for details about dual battery operation.)
RTMG is connected from TMG to VBAT and
limits power within the SLIC device in Active,
Off-Hook states.
BAT MAX – 6 – I LIMITMIN ⋅ ( 2 • R F + R LMIN + 40Ω )
R TMG ≥ ---------------------------------------------------------------------------------------------------------------------------------I LIMITMIN – 3 mA
2
( BAT max – 5 – I LIMITmin ( R Lmin + 2R F + 40 ) )
P RTMGmax = --------------------------------------------------------------------------------------------------------------------------R TMGmin
I LIMITmax
P SLICmaxi = 0.003 BAT max + 1 + ------------------------- R TMGmax
2
I LIMITmax
1
------------------------ + -----------------------
2
R
TMGmax
* “i” denotes channel number
13
Zarlink Semiconductor Inc.
Maximum power dissipated in the TMG
resistor, RTMG, during Active, Off-Hook
states.
Maximum power dissipated per channel in
the SLIC device while in Active, Off-Hook
states.
Le5712
Data Sheet
DC Feed Characteristics
Load Line (Active) (Typical)
50
VAB3
45
VAB2
40
|VAB| (Volts)
35
30
25
VAB1
20
15
10
On-Hook
Off-Hook
5
0
0
5
10
BAT = -46.5 V
20
15
25
30
35
Loop Current (mA)
BAT = -48 V
BAT = -52 V
RL = 2125 ohm
071902
Regions:
1.
470
V AB1 = I LOOP R L = --------------R L, where, R L = R L' + 2R F
R REF
Constant current region:
In Active and Reverse Polarity states
2. Battery tracking anti-sat (Off-hook):
47 ⋅ kΩ ⋅ V
V AB2 = BAT – 7 V + --------------------------- – I L ⋅ 160 Ω
R REF
3. Battery tracking anti-sat (On-hook):
10 ⋅ kΩ ⋅ V- – I ⋅ 160 Ω
V AB3 = BAT – 7 V + -------------------------L
R REF
In Active Metering and Reverse Polarity Metering states
4. Battery tracking anti-sat (Off-hook):
⋅ kΩ ⋅ V- – I ⋅ 160 Ω
V AB2 = BAT – 10.7 V + 47
-------------------------L
R REF
5. Battery tracking anti-sat (On-hook):
⋅ kΩ ⋅ V- – I ⋅ 160 Ω
V AB3 = BAT – 10.7 V + 10
-------------------------L
R REF
14
Zarlink Semiconductor Inc.
Le5712
Data Sheet
Test Circuits
Figure 1. Feed Programming
IAD
ADi
IREF
RD
RL
DSLIC
IL
RREF
RD
IBD
BDi
DETi
RG
IG
50 pF
CDC
CDCi
Figure 2.
Two-to-Four Wire Insertion Loss
VTX 1
VTX 2
AD 1, AD 2
RL
DSLIC
2
VTX
VAB
VL
RT
AGND
RL
RRX
2
RSN 1
RSN 2
BD 1, BD 2
IL2-4 = 20 log(V TX / V AB )
Figure 3. Four-to-Two Wire Insertion Loss and Balance Return Signals
VTX 1
VTX 2
AD 1, AD 2
DSLIC
VAB
VTX
RT
RL
AGND
RRX
BD 1, BD 2
RSN 1
RSN 2
IL4-2 = 20 log(V AB / V RX )
BRS = 20 log(V TX / V RX )
15
Zarlink Semiconductor Inc.
VRX
Le5712
Figure 4.
1
ωC
Longitudinal Balance
VTX 1
VTX 2
AD 1, AD 2
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