™
Le7920
Subscriber Line Interface Circuit
VE580 Series
The Le7920 Subscriber Line Interface Circuit implements the
basic telephone line interface functions, and enables the
design of low cost, high performance, POTS line interface
cards.
DISTINCTIVE CHARACTERISTICS
Control states: Active, Ringing, Standby,
and Disconnect
Low standby power (35 mW)
–19 V to –58 V battery operation
On-hook transmission
Two-wire impedance set by single external
impedance
Programmable loop-detect threshold
Programmable ring-trip detect threshold
No –5 V supply required
Current Gain = 500
On-chip Thermal Management (TMG) feature
Four on-chip relay drivers and relay snubbers, 1
ringing and 3 general purpose (32 PLCC)
Programmable constant-current feed
BLOCK DIAGRAM
TMG
A(TIP)
HPA
HPB
B(RING)
Relay
Driver
RYOUT3
Relay
Driver
RYOUT2
Relay
Driver
RYOUT1
Ring Relay
Driver
RINGOUT
Input Decoder
and Control
Two-Wire
Interface
D1
D2
D3
C1
C2
DET
VTX
RSN
Signal
Transmission
Off-Hook
Detector
RD
RDC
CAS
Power-Feed
Controller
DA
DB
VBAT
BGND
Ring-Trip
Detector
VCC
VBREF
AGND/DGND
Document ID# 080146 Date:
Rev:
J
Version:
Distribution:
Public Document
Sep 19, 2007
2
Le7920
Data Sheet
TABLE OF CONTENTS
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical Characteristics (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical Characteristics (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Relay Driver Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Test Circuits (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Test Circuits (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision C to Revision D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision D to Revision E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision E to Revision F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision F to Revision G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision G to Revision H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision H to Revision I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision I1 to Revision J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision J1 to Revision J2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ORDERING INFORMATION
Standard Products
Zarlink standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Le7920
J
C
C = Commercial (0°C to 70°C)*
PLCC package
PACKAGING MATERIAL
Blank= Standard package
D= Green package (see note)
DEVICE NUMBER/DESCRIPTION
Le7920
Subscriber Line Interface Circuit
PERFORMANCE GRADE
Blank = Standard specification
–1 = 53 dB Longitudinal Balance
–2 = 63 dB Longitudinal Balance
Note: Green package meets RoHS Directive 2002/95/EC of the European
Council to minimize the environmental impact of electrical equipment.
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Zarlink sales office to confirm availability of specific valid combinations, to check on
newly released combinations, and to obtain additional data on Zarlink’s standard military–grade
products.
Valid Combinations
Le7920*
–1
JC
–2
DJC
*Zarlink reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix, until such time
as all inventory bearing this mark has been depleted. It should be noted that parts marked with either the "Am" or the "Le" part
number prefix are equivalent devices in terms of form, fit, and function. The only difference between the two is in the part number
prefix appearing on the topside mark.
3
Zarlink Semiconductor Inc.
Le7920
Data Sheet
CONNECTION DIAGRAM
RYOUT2
5
RYOUT3
6
RYOUT1
RINGOUT
VCC
BGND
B(RING)
A(TIP)
DB
Top View
4
3
2
1
32
31
30
32-Pin
PLCC
29
DA
28
RD
27
HPB
VBAT
8
26
HPA
D2
9
25
NC
D1
10
24
VTX
NC
11
23
VBREF
NC
12
22
RSN
DET
13
21
AGND
RDC
19 20
NC
17 18
NC
16
CAS
15
C1
14
C2
7
D3
TMG
Notes:
1. Pin 1 is marked for orientation.
2. NC = No Connect
4
Zarlink Semiconductor Inc.
Le7920
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
Description
AGND/DGND
Ground
Analog and Digital ground.
A(TIP)
Output
Output of A(TIP) power amplifier.
BGND
Ground
Battery (power) ground.
B(RING)
Output
Output of B(RING) power amplifier.
C2–C1
Inputs
Decoder. TTL compatible. C2 is MSB and C1 is LSB.
CAS
Capacitor
Anti-Saturation pin for capacitor to filter reference voltage when operating in antisaturation region.
D3–D1
Input
Relay Driver Control. D3–D1 control the relay drivers RYOUT1, RYOUT2, and RYOUT3.
Logic Low on D1 activates the RYOUT1 relay driver. Logic Low on D2 activates the
RYOUT2 relay driver. Logic Low on D3 activates the RYOUT3 relay driver. TTL
compatible.
DA
Input
Ring-trip negative. Negative input to ring-trip comparator.
DB
Input
Ring-trip positive. Positive input to ring-trip comparator.
DET
Output
Switchhook detector. Logic Low indicates that selected detector is tripped. Logic inputs
C2–C1, E1, and E0 select the detector. Open-collector with a built-in 15 kΩ pull-up
resistor.
HPA
Capacitor
High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
HPB
Capacitor
High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
NC
—
No Connect. Pin not internally connected.
RD
Resistor
Detect resistor. Detector threshold set and filter pin.
RDC
Resistor
DC feed resistor. Connection point for the DC feed current programming network. The
other end of the network connects to the receiver summing node (RSN).
RINGOUT
Output
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
RSN
Input
Receive Summing Node. The metallic current (both AC and DC) between A(TIP) and
B(RING) is equal to 500 times the current into this pin. The networks that program
receive gain, two-wire impedance, and feed resistance all connect to this node.
RYOUT1
Output
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND.
RYOUT2
Output
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND
(PLCC only).
RYOUT3
Output
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND
(PLCC only).
TMG
—
Thermal Management. External resistor connects between this pin and VBAT to offload
power from SLIC.
VBAT
Battery
Battery supply and connection to substrate.
VBREF
—
This is an Zarlink reserved pin and must always be connected to the VBAT pin.
VCC
Power
+5 V power supply.
VTX
Output
Transmit Audio. This output is a 0.50 gain version of the A(TIP) and B(RING) metallic
voltage. VTX also sources the two-wire input impedance programming network.
5
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Storage temperature ......................... –55°C to +150°C
VCC with respect to AGND/DGND ..... –0.4 V to +7.0 V
VBAT with respect to AGND/DGND:
Continuous..................................... +0.4 V to –70 V
10 ms ............................................. +0.4 V to –75 V
BGND with respect to AGND/DGND........ +3 V to –3 V
A(TIP) or B(RING) to BGND:
Continuous ........................................ VBAT to +1 V
10 ms (f = 0.1 Hz) ............................. –70 V to +5 V
1 µs (f = 0.1 Hz) ................................ –80 V to +8 V
250 ns (f = 0.1 Hz) .......................... –90 V to +12 V
Current from A(TIP) or B(RING).....................±150 mA
RINGOUT/RYOUT1,2,3 current.........................50 mA
RINGOUT/RYOUT1,2,3 voltage ........... BGND to +7 V
RINGOUT/RYOUT1,2,3 transient ....... BGND to +10 V
DA and DB inputs
Voltage on ring-trip inputs .....................VBAT to 0 V
Current into ring-trip inputs ......................... ±10 mA
C2–C1 and D3–D1
Input voltage .........................–0.4 V to VCC + 0.4 V
Maximum power dissipation, continuous,
TA = 70°C, No heat sink (See note)
In 32-pin PLCC package................................1.7 W
Thermal Data:................................................................θJA
In 32-pin PLCC package....................... 43°C/W typ
ESD immunity/pin (HBM) ..................................1500 V
Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. Continuous operation
above 145°C junction temperature may degrade device reliability.
Stresses above those listed under "Absolute Maximum Ratings" can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
6
Zarlink Semiconductor Inc.
Le7920
Data Sheet
OPERATING RANGES
The operating ranges define those limits between which the functionality of the device is guaranteed.
Commercial (C) Devices
Ambient temperature .............................0°C to +70°C*
VCC..................................................... 4.75 V to 5.25 V
VBAT ..................................................... –19 V to –58 V
AGND/DGND ..........................................................0 V
BGND with respect to
AGND/DGND ....................... –100 mV to +100 mV
Load resistance on VTX to ground .............. 20 kΩ min
* Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges
by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to
periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component
Reliability Assurance Requirements for Telecommunications Equipment.
Package Assembly
The standard (non-green) package devices are assembled with industry-standard mold compounds, and the leads possess a tin/
lead (Sn/Pb) plating. These packages are compatible with conventional SnPb eutectic solder board assembly processes. The
peak soldering temperature should not exceed 225°C during printed circuit board assembly.
The green package devices are assembled with enhanced environmental compatible lead (Pb), halogen, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile
7
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
dB
1, 4
Ω
4
Transmission Performance
2-wire return loss
200 Hz to 3.4 kHz
26
Analog output (VTX) impedance
3
Analog (VTX) output offset voltage
–50
20
+50
mV
Overload level, 2-wire and 4-wire
Active state
2.5
Vpk
2a
Overload level
On hook, RLAC = 600 Ω
0.77
Vrms
2b
THD, Total Harmonic Distortion
0 dBm
+7 dBm
dB
5
THD, On hook
–64
–55
0 dBm, RLAC = 600 Ω
–50
–40
–36
Longitudinal Capability (See Test Circuit D)
Longitudinal to
metallic L-T, L-4
balance
200 Hz to 1 kHz
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–1*
–2
–1
–2
52
63
50
58
4
4
dB
1 kHz to 3.4 kHz
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–1*
–2
–1
–2
52
58
50
53
Longitudinal signal generation 4-L
200 Hz to 3.4 kHz
40
Longitudinal current per pin (A or B)
Active state
20
Longitudinal impedance at A or B
0 to 100 Hz
4
4
27
35
mArms
8
Ω/pin
25
Idle Channel Noise
C-message weighted noise
RL = 600 Ω
RL = 600 Ω
0°C to +70°C
–40°C to +85°C
7
+10
+12
dBrnc
Psophometric weighted noise
RL = 600 Ω
RL = 600 Ω
0°C to +70°C
–40°C to +85°C
–83
–80
–78
dBmp
4
Insertion Loss and Balance Return Signal (See Test Circuits A and B)
Gain accuracy
4- to 2-wire
0 dBm, 1 kHz
–0.20
0
+0.20
Gain accuracy
2- to 4-wire, 4- to 4-wire
0 dBm, 1 kHz
–6.22
–6.02
–5.82
Gain accuracy, 4- to 2-wire
On hook
–0.35
Gain accuracy, 2- to 4-wire, 4- to 4-wire On hook
–6.37
Gain accuracy over frequency
300 to 3.4 kHz
relative to 1 kHz
–0.15
+0.15
Gain tracking
+3 dBm to –55 dBm
relative to 0 dBm
–0.15
+0.15
Gain tracking
On hook
0 dBm to –37 dBm
+3 dBm to 0 dBm
–0.15
–0.35
+0.15
+0.35
Group delay
0 dBm, 1 kHz
+0.35
–6.02
4
Note:
* Performance Grade
8
Zarlink Semiconductor Inc.
–5.67
4
dB
µs
4, 7
Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
26
Unit
Note
Line Characteristics
IL, Short Loops, Active state
RLDC = 600 Ω
20
23
IL, Long Loops, Active state
RLDC = 1930 Ω, BAT = –42.75 V,
TA = 25°C
18
19
IL, Accuracy, Standby state
BAT – 3 V
I L = ------------------------------R L + 400
0.7IL
IL
18
30
T A = 25°C
Constant-current region
IL, Loop current, Disconnect state
RL = 0
ILLIM
Active, A and B to ground
VAB, Open Circuit voltage
VBAT = –52 V
85
–42.75
–44
1.3IL
mA
100
µA
120
mA
V
Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State
VCC
50 Hz to 3.4 kHz
30
40
VBAT
50 Hz to 3.4 kHz
28
50
Effective internal resistance
CAS pin to VBAT
85
170
255
On hook, Disconnect state
25
70
On hook, Standby state
35
100
dB
5
kΩ
4
Power Dissipation
On hook, Active state
125
270
Off hook, Standby state
RL = 600 Ω
860
1200
Off hook, Active state
RL = 300 Ω, RTMG = 2350 Ω
450
800
ICC,
On-hook VCC supply current
Disconnect state
Standby state
Active state, BAT = –48 V
1.7
2.2
6.3
4.0
4.0
8.5
IBAT,
On-hook VBAT supply current
Disconnect state
Standby state
Active state, BAT = –48 V
0.25
0.55
2.8
1.0
1.5
4.8
mW
Supply Currents, Battery = –48V
mA
RFI Rejection
RFI rejection
100 kHz to 30 MHz, (See Figure F)
1.0
mVrms
4
Receive Summing Node (RSN)
RSN DC voltage
IRSN = 0 mA
0
RSN impedance
200 Hz to 3.4 kHz
10
V
20
Ω
4
Logic Inputs (C2–C1 and D3–D1)
VIH, Input High voltage
2.0
VIL, Input Low voltage
0.8
IIH, Input High current
–75
IIL, Input Low current
–400
40
V
µA
Logic Output (DET)
VOL, Output Low voltage
IOUT = 0.3 mA, 15 kΩ to VCC
VOH, Output High voltage
IOUT = –0.1 mA, 15 kΩ to VCC
0.40
2.4
V
Ring-Trip Detector Input (DA, DB)
Bias current
Offset voltage
Source resistance = 2 MΩ
9
Zarlink Semiconductor Inc.
–500
–50
–50
0
nA
+50
mV
6
Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Loop Detector
On threshold
RD = 35.4 kΩ
11.5
17.3
Off threshold
RD = 35.4 kΩ
9.4
14.1
Hysteresis
RD = 35.4 kΩ
0
4.4
mA
Relay Driver Output (RINGOUT, RYOUT1, RYOUT2, RYOUT3)
On voltage
IOL = 40 mA
Off leakage
VOH = +5 V
Zener breakover
IZ = 100 µA
Zener On voltage
IZ = 30 mA
+0.3
6
+0.7
V
100
µA
7.2
10
V
RELAY DRIVER SCHEMATICS
RINGOUT
RYOUT1, RYOUT2, RYOUT3
BGND
BGND
Notes:
1.
Unless otherwise noted, test conditions are BAT = –52 V, VCC = +5 V, RL = 600 Ω, RDC1 = RDC2 = 27.17 kΩ, RTMG = 2350 Ω,
RD = 35.4 kΩ, no fuse resistors, CHP = 0.22 µF, CDC = 0.1 µF, CCAS = 0.33 µF, D1 = 1N400x, two-wire AC input impedance is a 600 Ω
resistance synthesized by the programming network shown below.
VTX
RT1 = 75 kΩ
CT1 = 120 pF
RT2 = 75 kΩ
RSN
RRX = 150 kΩ
VRX
2.
a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3.
Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire, AC-load impedance matches
the programmed impedance.
4.
Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6.
Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
7.
Group delay can be greatly reduced by using a ZT network such as that shown in Note 1. The network reduces the group delay to less than
2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex
impedance with the QSLAC™ or DSLAC™ device.
8.
Minimum current level guaranteed not to cause a false loop detect.
10
Zarlink Semiconductor Inc.
Le7920
Table 1.
Data Sheet
SLIC Decoding
State
C2
C1
0
0
0
Disconnect
Ring trip
1
0
1
Ringing
Ring trip
2
1
0
Active
Loop detector
3
1
1
Standby
Loop detector
Table 2.
Two-Wire Status
DET Output
User-Programmable Components
Z T = 250 ( Z 2WIN – 2 R F )
ZT is connected between the VTX and RSN pins. The fuse
resistors are RF, and Z2WIN is the desired 2-wire AC input
impedance. When computing ZT, the internal current amplifier
pole and any external stray capacitance between VTX and RSN
must be taken into account.
ZL
500 Z T
Z RX = -----------• ---------------------------------------------------G 42L
Z T + 250 ( Z L + 2 R F )
ZRX is connected from VRX to RSN. ZT is defined above, and
G42L is the desired receive gain.
1250R DC1 + R DC2 = -------------I LOOP
RDC1, RDC2, and CDC form the network connected to the RDC
pin. RDC1 and RDC2 are approximately equal. ILOOP is the
desired loop current in the constant-current region.
R DC1 + R DC2
C DC = 1.5 ms • ---------------------------------R DC1 • R DC2
510
415
msRD ON = --------- , RD OFF = --------- , C D = 0.5
---------------IT
IT
RD
RD and CD form the network connected from RD to AGND/
DGND and IT is the threshold current between on hook and
off hook.
1
C CAS = ------------------------------
CCAS is the regulator filter capacitor and fc is the desired filter
cut-off frequency.
5
3.4 • 10 π f c
V BAT – 3 V
I STANDBY = --------------------------------400 Ω + R L
Standby loop current (resistive region).
Thermal Management Equations (Normal Active and Tip Open States)
V BAT – 6 V
R TMG ≥ --------------------------------- – 70 Ω
I LOOP
RTMG is connected from TMG to VBAT and saves power within
the SLIC in Active and Disconnect state constant-currents only.
2
( V BAT – 6 V – ( I L • R L ) )
- • R TMG
P RTMG = ----------------------------------------------------------------------( R TMG + 70 Ω )
Power dissipated in the TMG resistor, RTMG, during Active and
Disconnect states.
2
2
P SLIC = V BAT • I L – P RTMG – R L ( I L ) + 0.12 W
Power dissipated in the SLIC while in Active and Disconnect
states.
11
Zarlink Semiconductor Inc.
Le7920
Data Sheet
DC FEED CHARACTERISTICS
60
3
2
VAB
(volts)
1
0
IL (mA)
RDC = RDC1 + RDC2 = 54.34 kΩ
BAT = –48 V
Notes:
1250
1. V AB = I L R L' = ------------ R L' , where R L' = R L + 2 R F
R DC
R DC
2. V AB = 0.857 ( V BAT + 3.3 ) – I L ----------300
R DC
3. V AB = 0.857 ( V BAT + 1.2 ) – I L ----------300
a. Load Line (Typical)
12
Zarlink Semiconductor Inc.
30
Le7920
Data Sheet
A
a
RL
I
SLIC
L
RSN
RDC1
b
RDC2
B
RDC
Feed current programmed by RDC1 and RDC2
b. Feed Programming
Figure 1. DC Feed Characteristics
13
Zarlink Semiconductor Inc.
CDC
Le7920
Data Sheet
TEST CIRCUITS
A(TIP)
RL
2
VTX
SLIC
VAB
VL
RT
AGND
RL
RRX
2
RSN
B(RING)
IL2-4 = 20 log (VTX / VAB)
A. Two- to Four-Wire Insertion Loss
A(TIP)
VTX
SLIC
VAB
RL
AGND
RT
RRX
B(RING) RSN
VRX
IL4-2 = 20 log (VAB / VRX)
BRS = 20 log (VTX / VRX)
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
1
ωC
A(TIP)