LE7942B-1DJC

™ Le7942B A Subscriber Line Interface Circuit VE580 Series Voice Solution DISTINCTIVE CHARACTERISTICS „ „ „ „ „ „ „ „ Programmable constant-current feed Receive current gain = 500 Programmable loop-detect threshold Low standby power Performs polarity reversal Ground-key detector Pin for external ground-key noise filter capacitor Test relay driver option „ „ „ „ „ Compatible with Le7942 Device Tip Open state for ground-start lines –19 V to –58 V battery operation Ideal for PBX and KTS applications On-chip switching regulator for low-power dissipation „ Can be used with or without the on-chip switching regulator „ On-hook transmission BLOCK DIAGRAM A(TIP) Test Relay Driver TESTOUT Ring Relay Driver RINGOUT C1 C2 Ground-Key Detector HPA C3 Input Decoder and Control C4 E1 DET Two-Wire Interface HPB B(RING) GKFIL Signal Transmission RSN VTX Off-Hook Detector RD RDC CAS Power-Feed Controller DA DB VREG L VBAT Ring-Trip Detector Switching Regulator BGND CHS QBAT CHCLK VCC NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and technology of Legerity Holdings. VEE AGND/DGND 15474A-001 Document ID# 081195 Date: Rev: E Version: Distribution: Public Document Sep 19, 2007 2 Le7942B Data Sheet ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Le7942B J C C = Commercial (0°C to 70°C)* PLCC package PACKAGING MATERIAL Blank= Standard package D= Green package (see note) DEVICE NUMBER/DESCRIPTION Le7942B Subscriber Line Interface Circuit PERFORMANCE GRADE Blank = Standard specification –1 = Performance Grading –2 = Performance Grading Note: The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. Valid Combinations Valid Combinations Green Package Le7942BDJC Le7942B–1DJC Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity’s standard military–grade products. Le7942B–2DJC Non-Green Package Le7942BJC Le7942B-1JC Le7942B-2JC 2 Zarlink Semiconductor Inc. Le7942B Data Sheet RINGOUT VCC VREG BGND B(RING) A(TIP) DB CONNECTION DIAGRAMS Top View 4 3 2 1 32 31 30 TP 5 29 TP TESTOUT 6 28 DA L 7 27 RD VBAT 8 26 HPB QBAT 9 25 HPA CHS 10 24 VTX CHCLK 11 23 VBREF C4 12 22 RSN E1 13 21 AGND/DGND 16 17 18 19 20 C2 C3 C1 RDC GKFIL 15 CAS 14 DET 32-Pin PLCC Notes: 1. Pin 1 is marked for orientation. 2. TP is a thermal conduction pin tied to substrate (QBAT). 3 Zarlink Semiconductor Inc. Le7942B Data Sheet PIN DESCRIPTIONS Pin Names Type Description AGND/DGND Gnd Analog and Digital ground. A (TIP) Output Output of A(TIP) power amplifier. BGND Gnd Battery (power) ground. B (RING) Output Output of B(RING) power amplifier. C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB. C4 Input Test Relay Driver Command. TTL compatible. A logic Low enables the driver. CAS Capacitor Anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation region. CHCLK Input Chopper Clock. Input to switching regulator (TTL compatible). Freq = 256 kHz (typ). (See Note 1). CHS Input Chopper Stabilization. (See Note 1) Connection for external chopper stabilizing components. DA Input Ring-trip negative. Negative input to ring-trip comparator. DB Input Ring-trip positive. Positive input to ring-trip comparator. DET Output Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The detector is selected by the logic inputs (C3–C1, E1). The output is open-collector with a built-in 15 kΩ pull-up resistor. E1 Input Ground-Key Enable. E1 = High connects the ground-key detector to DET. E1 = Low connects the off-hook or ring-trip detector to DET. GKFIL — Connection for external ground-key, noise-filter capacitor. (See Note 2.) HPA Capacitor High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor. L Output (See Note 1) Switching Regulator Power Transistor. Connection point for filter inductor and anode of Switching Regulator Power Transistor. Connection point for filter inductor and anode of catch diode. Has up to 60 V of pulse waveform on it and must be isolated from sensitive circuits. Keep the diode connections short because of the high currents and high di/dt. QBAT Battery Quiet Battery. (See Note 1). Filtered battery supply for the signal processing circuits. RD Resistor Detector resistor. Detector threshold set and filter pin. May be connected to ground or -5V. RDC Resistor DC feed resistor. Connection point for the DC feed current programming network. The other end of the network connects to the receiver summing node (RSN). RINGOUT Output Ring Relay Driver. Open-collector driver with emitter internally connected to BGND. (See Note 3) RSN Input Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 500 x the current into this pin. The networks that program receive gain, two-wire impedance, and feed current all connect to this node. TESTOUT Output Test Relay Driver. Open collector driver with emitter internally connected to BGND. (See Note 3) TP Thermal Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation. VBAT Battery Battery supply. VCC Power +5 V power supply. VBREF Power Reference voltage. No current on the pin. May be connected to QBAT or –5 V. VREG Input Regulated Voltage. (See Note 1.) Provides negative power supply for power amplifiers. Connection point for inductor, filter capacitor, and chopper stabilization. VTX Output Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network. Notes: 1. All pins, except CHCLK, connect to VBAT when using SLIC without a switching regulator. CHCLK is connected to AGND/ DGND. 2. To prevent noise pickup by the detection circuits when using Ground-Key Detect state (E1 = logical 1), a 3300 pF minimum bypass capacitor is recommended between the GKFIL pin and ground. 3. Each relay driver has a zener clamp to BGND. 4 Zarlink Semiconductor Inc. Le7942B Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage temperature . . . . . . . . . . . . –55°C to +150°C Commercial (C) Devices VCC with respect to AGND/DGND . . . –0.4 V to +7.0 V Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C* VEE with respect to AGND/DGND . . . +0.4 V to QBAT VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V VBAT with respect to AGND/DGND. . . +0.4 V to –70 V VEE . . . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to QBAT Note: Rise time of VBAT (dv/dt) must be limited to 27 V/µs or less when QBAT bypass = 0.33 µF. VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to –58 V** BGND with respect to AGND/DGND . +1.0 V to –3.0 V BGND with respect to AGND/DGND. . . . . . . . . . . . –100 mV to +100 mV AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V A(TIP) or B(RING) to BGND: Continuous . . . . . . . . . . . . . . . . . . –70 V to +1.0 V 10 ms (f = 0.1 Hz) . . . . . . . . . . . . . –70 V to +5.0 V 1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . . –90 V to +10 V 250 ns (f = 0.1 Hz) . . . . . . . . . . . . –120 V to +15 V Load Resistance on VTX to ground . . . . . . 10 kΩ min The Operating Ranges define those limits between which the functionality of the device is guaranteed. Current from A(TIP) or B(RING). . . . . . . . . . . .±150 mA *Legerity guarantees the performance of this device over commercial (0 to 70°C) and industrial (-40 to 85 °C) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore TR-TSY-000357 Component Reliability Assurance Requireme nts for Telecommu nications Equipment. Voltage on RINGOUT, TESTOUT . . . . BGND to + 7 V Voltage on RINGOUT, TESTOUT (transient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGND to +10 V Current through relay drivers . . . . . . . . . . . . . . 60 mA Voltage on ring-trip inputs (DA and DB) . . . . . . . . . . . . . . . . . . . . . VBAT to 0 V Current into ring-trip inputs . . . . . . . . . . . . . . . . .±10 mA **Can be used without switching regulator components in this range of battery voltages, provided maximum power dissipation specifications are not exceeded. Peak current into regulator switch (L pin). . . . . . . . . . . . . . . . . . . . . . . 150 mA Package Assembly Switcher transient peak off voltage on L pin. . . . . . . . . . . . . . . . . . . . . . +1.0 V The non-green package devices are assembled with industry-standard mold compounds, and the leads possess a tin/lead (Sn/Pb) plating. These packages are compatible with conventional SnPb eutectic solder board assembly processes. The peak soldering temperature should not exceed 225°C during printed circuit board assembly. C4–C1, E1, CHCLK to AGND/DGND . . . . . . . . . . . .–0.4 V to VCC + 0.4 V Maximum power dissipation, TA (see note) . . . . .70°C In 32-pin PLCC package. . . . . . . . . . . . . . . 1.74 W Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. The device should never be exposed to this temperature. Operation above 145°C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information. The green package devices are assembled with enhanced environmental compatible lead-free, halogen-free, and antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly. Stresses above those listed under Absolute Maximum Ratings cancause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile 5 Zarlink Semiconductor Inc. Le7942B Data Sheet ELECTRICAL CHARACTERISTICS Description Test Conditions (See Note 1) Grade Min Typ all 3 — –1 –2 –35 –35 –30 — +35 +35 +30 –40°C to +85°C –1 –2 –40 –40 –35 — +40 +40 +35 300 Hz to 3.4 kHz all — 1 20 Analog (VTX) output impedance Analog (VTX) output offset Analog (RSN) input impedance 0°C to +70°C Longitudinal impedance at A or B Overload level 4-wire 2-wire Max Unit Note Ω 4 — mV 4 — Ω all — — 35 — all –2.5 — +2.5 Vpk 2 26 — — dB 4, 10 –1 –2 –2 –2 52 52 63 58 54 — — –1 –2 –2 –2 52 52 58 54 54 — — –1 –2 40 40 42 — — all — 28 18 — Transmission Performance, 2-Wire Impedance (See Test Circuit D) 2-wire return loss 300 to 3400 Hz all Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C); RL = 600 Ω 200 Hz to 1 kHz normal polarity 0°C to +70°C normal polarity –40°C to +85°C reverse polarity Longitudinal to metallic L-T, L-4 1 kHz to 3.4 kHz normal polarity 0°C to +70°C normal polarity –40°C to +85°C reverse polarity Longitudinal signal generation 4-L 300 Hz to 800 Hz Reverse polarity Longitudinal current capability per wire Active state OHT state 1, 2 1, 2, 4 1, 2 dB mArms 1, 2 1, 2, 4 1, 2 4 Insertion Loss (4- to 2-Wire, See Test Circuit B) BAT = –48 V, RLDC = RLAC = 600 Ω; BAT = –24 V, RLDC = 300 Ω, RLAC = 600 Ω Gain accuracy –1 –2 –0.15 –0.15 –0.10 — +0.15 +0.15 +0.10 –1 –2 –0.20 –0.20 –0.15 — +0.20 +0.20 +0.15 300 Hz to 3400 Hz Relative to 1 kHz 0°C to +70°C –1 –2 –0.15 –0.15 –0.10 — +0.15 +0.15 +0.10 300 Hz to 3400 Hz Relative to 1 kHz –40°C to +85°C –1 –2 –0.20 –0.20 –0.15 — +0.20 +0.20 +0.15 0 dBm, 1 kHz 0°C to +70°C 0 dBm, 1 kHz –40°C to +85°C Variation with frequency 6 Zarlink Semiconductor Inc. 4 dB 4 Le7942B Data Sheet ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) 0°C to +70°C +7 dBm to –55 dBm Reference: –0 dBm Gain tracking Grade Min Typ Max all –0.10 — +0.10 Unit Note dB –40°C to +85°C +7 dBm to –55 dBm Reference: –0 dBm all –0.15 — +0.15 4 Insertion Loss and Balance Return Signal (2- to 4-Wire and 4- to 4-Wire, See Test Circuits A and B) BAT = –48 V, RLDC = RLAC = 600 Ω; BAT = –24 V, RLDC = 300 Ω, RLAC = 600 Ω –1 –2 –6.17 –6.17 –6.12 –6.02 –5.87 –5.87 –5.92 3 3 3 –1 –2 –6.22 –6.22 –6.17 –6.02 –5.82 –5.82 –5.87 3, 4 3, 4 3, 4 300 Hz to 3400 Hz Relative to 1 kHz 0°C to +70°C all –0.10 +0.10 3 300 Hz to 3400 Hz Relative to 1 kHz –40°C to +85°C all –0.15 +0.15 3, 4 0°C to +70°C +3 dBm to –55 dBm Reference: 0 dBm all –0.10 +0.10 3 –40°C to +85°C +3 dBm to –55 dBm Reference: 0 dBm all –0.15 –0.15 3, 4 f = 1 kHz all 0 dBm, 1 kHz 0°C to +70°C Gain accuracy 0 dBm, 1 kHz –40°C to +85°C Variation with frequency Gain tracking Group delay dB µs 5.3 4, 12 Total Harmonic Distortion (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B) BAT = –48 V, RLDC = RLAC = 600 Ω Harmonic distortion 0 dBm all –64 –50 300 Hz to 3400 Hz +7 dBm all –55 –40 +7 +10 +12 dBmc 4 4 –83 –80 –78 dBmp — 4 dB 6 Idle Channel Noise BAT = –48 V, RLDC = RLAC = 600 Ω; BAT = –24 V, RLDC = 300 Ω, RLAC = 600 Ω C-message weighted noise 2-wire, 0°C to +70°C 2-wire, –40°C to +85°C all Psophometric weighted noise 2-wire, 0°C to +70°C 2-wire, –40°C to +85°C all Single Frequency Out-of-Band Noise (See Test Circuit E) Metallic Longitudinal 4 kHz to 9 kHz 9 kHz to 1 MHz 256 kHz and harmonics** 1 kHz to 15 kHz Above 15 kHz 256 kHz and harmonics** all –76 –76 –63 all –70 –85 –57 Note: **Applies only when switching regulator is used. 7 Zarlink Semiconductor Inc. dBm 4 4, 5, 8 4, 5 4 4, 5, 8 4, 5 Le7942B Data Sheet ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Grade Min Typ Max VBAT = –24 V, RLDC = 300 Ω VBAT = –43 V, RLDC = 600 Ω VBAT = –48 V, RLDC = 600 Ω all 31.8 34.4 37.0 VBAT = –24 V, RLDC = 640 Ω VBAT = –43 V, RLDC = 1300 Ω VBAT = –48 V, RLDC = 1900 Ω all 20.0 23.0 18.0 OHT state VBAT = –24 V, RLDC = 300 Ω VBAT = –48 V, RLDC = 600 Ω all Loop current Tip Open state, RL = 0 Ω Disconnect state, RL = 0 Ω all ILLIM (ITip and IRing) Tip and ring shorted to GND all 70 120 Unit Note Line Characteristics (See Figures 1a, 1b, 1c) Short loops, Active state Long loops, Active state 31.4 4, 9 4 — mA 34.4 4, 9 4 — 4, 9 — 37.4 1.0 Power Dissipation Battery, Normal Loop Polarity On-hook Open Circuit state VBAT = –24 V, w/o switching reg. VBAT = –48 V, with switching reg. all 30 35 75 100 9 — On-hook OHT state VBAT = –24 V, w/o switching reg. VBAT = –48 V, with switching reg. all 80 130 225 9 — On-hook Active state VBAT = –24 V, w/o switching reg. VBAT = –48 V, with switching reg. all 80 130 225 300 Off-hook OHT state RL = 50 Ω VBAT = –24 V, w/o switching reg. VBAT = –48 V, with switching reg. all 500 400 950 750 9 — Off-hook Active state RL = 50 Ω VBAT = –24 V, w/o switching reg. VBAT = –48 V, with switching reg. all 800 450 1100 1000 9 — 4.5 10.0 12.0 mW 9 — Supply Currents, Battery = –24 V or –48 V VCC on-hook supply current Open Circuit state OHT state Active state all 2.5 4.5 4.5 VBREF on-hook supply current Open Circuit state OHT state Active state all 0 0 0 VBAT on-hook supply current Open Circuit state OHT state Active state all 0.6 2.3 2.3 mA 9 dB 6 255 kΩ 4 +20 % 1.0 5.0 6.0 Power Supply Rejection Ratio (VRIPPLE = 50 mVrms) VCC 50 Hz to 3.4 kHz 3.4 kHz to 50 kHz VBAT Effective int. resistance all 25 22 45 35 50 Hz to 3.4 kHz 3.4 kHz to 50 kHz all 27 20 45 40 CAS to GND all 85 170 all –20 Off-Hook Detector Current threshold IDET = 365/RD If RD to gnd IDET = 1825/RD If RD to –5V 8 Zarlink Semiconductor Inc. Le7942B Data Sheet ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Grade Min Typ Max Unit Note 1.0 2.0 2.2 5.0 4.5 10.0 kΩ 9 — mA 7 kΩ 4 Ground-Key Detector Thresholds, Active State Ground-key resistance threshold VBAT = –24 V, B(RING) to GND VBAT = –48 V, B(RING) to GND all Ground-key current threshold B(RING) to GND Midpoint to GND all Effective internal resistance GKFIL to AGND/DGND all 18 36 all –5 –0.05 all –50 0 Input High voltage all 2.0 Input Low voltage all 9 9 54 Ring-Trip Detector Input Bias current Offset voltage Source resistance = 0 to 2 MΩ µA +50 mV Logic Inputs (C4–C1, E1, and CHCLK) 0.8 Input High current All inputs except E1 all –75 40 Input High current Input E1 all –75 45 all –0.4 Input Low current V µA mA Logic Output (DET) Output Low voltage IOUT = 0.3 mA all Output High voltage IOUT = –0.1 mA all 0.4 2.4 V Relay Driver Outputs (RINGOUT, TESTOUT) On voltage 25 mA sink all Off leakage VOH = 5 V all Zener break-over IL = 100 µA all Zener on voltage IL = 30 mA all 9 Zarlink Semiconductor Inc. 0.3 6 7.2 8 +1.5 V 100 µA V 11 Le7942B Data Sheet RELAY DRIVER SCHEMATICS RINGOUT TESTOUT BGND BGND SWITCHING CHARACTERISTICS Symbol tgkde Parameter Test Conditions E1 Low to DET High (E0 = 1) E1 Low to DET Low (E0 = 1) tshde E1 High to DET Low (E0 = 1) E1 High to DET High (E0 = 1) Ground-Key Detect state RL open, RG connected (See Figure H) Switchhook Detect state RL = 600 Ω, RG open (See Figure G) Temperature Range Min Typ Max 0°C to +70°C –40°C to +85°C 3.8 4.0 0°C to +70°C –40°C to +85°C 1.1 1.6 0°C to +70°C –40°C to +85°C 1.2 1.7 0°C to +70°C –40°C to +85°C 3.8 4.0 Unit Note µs 4 SWITCHING WAVEFORMS E1 to DET E1 DET tgkde tshde tgkde Note: All delays measured at 1.4 V levels. tshde 15474A-003 10 Zarlink Semiconductor Inc. Le7942B Data Sheet Notes: 1. Unless otherwise noted, test conditions are BAT = –48 V, VCC = +5 V, RL = 600 Ω, CHP = 0.33 µF, RDC1 = RDC2 = 9.09 kΩ, CDC = 0.39 µF, RD = 35.4 kΩ when RD is connected to ground and RD = 177 kΩ when Rd is connected to -5V. CCAS = 0.47 µF, no fuse resistors, RT =150 kΩ, and RRX = 150 kΩ. Switching regulator components: L = 1 mH, CFIL = 0.47 µF (see Application Circuit). 2. Overload level is defined when THD = 1%. 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes the two-wire AC load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. For frequencies below 12 kHz, these tests are performed with a longitudinal impedance of 90 Ω and metallic impedance of 300 Ω. For frequencies greater than 12 kHz, a longitudinal impedance of 90 Ω and a metallic impedance of 135 Ω is used. These tests are extremely sensitive to circuit board layout. Please refer to application notes for details. 6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 7. “Midpoint” is defined as the connection point between two 300 Ω series resistors connected between A(TIP) and B(RING). 8. Fundamental and harmonics from 256 kHz switch regulator chopper are not included. 9. For –24 V battery, switching regulator is disabled. L, CHS, and VREG pins connected to VBAT pin; CHCLK pin connected to AGND/DGND. 10. Assumes the following ZT network: VTX RSN 75 kΩ 75 kΩ 120 pF 11. Tested with 0 Ω source impedance. 2 MΩ is specified for system design purposes only. 12. Group delay can be considerably reduced by using a ZT network such as that shown in Note 10 above. The network reduces the group delay to less than 2 µs. The effect of group delay on linecard performance may be compensated for by using the QSLAC™ or DSLAC™ device. Table 1. SLIC Device Decoding DET Output State C3 C2 C1 Two-Wire Status E1 = 0 E1 = 1 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-Hook TX (OHT) Loop detector Ground key 4 1 0 0 Tip Open Loop detector — 5 1 0 1 Reserved Loop detector — 6 1 1 0 Active Polarity Reversal Loop detector Ground key 7 1 1 1 OHT Polarity Reversal Loop detector Ground key Table 2. User-Programmable Components Z T = 250 ( Z 2WIN – 2R F∗ ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. 11 Zarlink Semiconductor Inc. Le7942B Table 2. Data Sheet User-Programmable Components ZL 500Z T - • ------------------------------------------------Z RX = -----------G42 L Z T + 250 ( Z L + 2R F ) ZRX is connected from VRX to the RSN. ZT is defined above, and G42L is the desired receive gain. 625 R DC1 + R DC2 = -------------I LOOP RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP is the desired loop current in the constant-current region. R DC1 + R DC2 C DC = 1.5 ms • -------------------------------R DC1 R DC2 365 R D = --------- If RD is connected to ground. IT 1825 R D = ------------ If RD is connected to -5V. IT 0.5 ms C D = ----------------RD RD and CD form a network connected from RD to either ground or –5 V, and IT is the threshold current between on hook and off hook. 1 C CAS = ----------------------------5 3.4 • 10 πf c CCAS is the regulator filter capacitor, and fc is the desired filter cut-off frequency. Note: *RFUSE = 20 – 50 Ω, user selectable. 12 Zarlink Semiconductor Inc. Le7942B Data Sheet DC FEED CHARACTERISTICS 45 40 35 30 25 20 15 10 5 0 7942B 7942 (active) 37 34 31 28 25 22 19 16 13 10 7 4 7942 (OHT) 1 VAB VAB vesus Iloop, BAT =-48V Iloop RDC1 + RDC2 = RDC = 18.18 kΩ Active state OHT state Notes: 1. Constant-current region: Active state: OHT state: 625 I L = ----------R DC 625I L = --------R DC 2. Anti-saturation 2 region: Active state: and OHT state: R DC V AB = BAT – 7.9 – I L  -----------  210  a. VA–VB (VAB) Voltage vs. Loop Current (Typical) 13 Zarlink Semiconductor Inc. Le7942B Data Sheet DC FEED CHARACTERISTICS (continued) 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 7942B 37 33 29 25 21 17 13 9 5 7942 (active) 1 Loop Resistance Iloop vesus Loop Resistance, BAT = -48V Iloop RDC1 + RDC2 = RDC = 18.18 kΩ b. Loop Current vs. Load Resistance (Typical) A RSN a RL RDC1 SLIC IL b RDC2 B CDC RDC Feed current programmed by RDC1 and RDC2 c. Feed Programming Figure 1. DC Feed Characteristics 14 Zarlink Semiconductor Inc. 15474A-004 Le7942B Data Sheet TEST CIRCUITS A(TIP) VTX VTX A(TIP) RL RT 2 SLIC VL VAB SLIC VAB AGND RL RT AGND RL 2 RRX B(RING) RSN RRX B(RING) RSN VRX IL4-2 = –20 log (VAB / VRX) IL2-4 = –20 log (VTX / VAB) BRS = 20 log (VTX / VRX) B. Four- to Two-Wire Insertion Loss and Balance Return Signal A. Two- to Four-Wire Insertion Loss ZD 1/ωC