™
Le79555
Subscriber Line Interface Circuit
VE580 Series
APPLICATIONS
DESCRIPTION
Ideal for high-density, low-power linecard applications
The Le79555 device, part of the Zarlink VoiceEdge™ family
VE580 series of devices, was designed for high-density POTS
applications requiring a power saving, small footprint SLIC
device. The new SLIC device fulfills today's requirements for
POTS linecard markets requiring a balance of highperformance cost-effective silicon components. The Le79555
device delivers economical linecard solutions by offering power
and space savings to linecard designers. The on-chip
switching regulator allows for power dissipation to be
minimized for the entire system. Another benefit is that the
device is offered in a reduced footprint package type, a 44-pin
TQFP. This small footprint saves designers board space, thus
increasing the density or number of lines on the board.
FEATURES
Control states: Active, Reverse Polarity, Tip Open,
Ringing, Standby, and Open Circuit
Low Standby power
–40 to –58 V battery operation
On-hook transmission
Two-wire impedance set by single external impedance
Programmable constant-current feed
Low Off-Hook Active Overhead Voltage
Programmable loop-detect threshold
Ground-start detector
Programmable ring-trip detect threshold
No –5 V supply required
Three on-chip relay drivers and relay snubbers, one
ringing and two general purpose
Tip Open state for ground-start lines
On-chip switching regulator for Low power dissipation
Supports 30 mA for Active, Normal, and Reverse
Polarity operation
ORDERING INFORMATION
Le79555-4BVC
63 dB No Pol. Rev.,
44-pin TQFP (Green)
1.
2.
Tray
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
A(TIP)
Ring Relay Driver
RINGOUT
Relay Driver
RYOUT1
Relay Driver
RYOUT2
HPA
C1
C2
C3
HPB
D1
Input Decoder
and Control
D2
DET
Two Wire
Interface
Ground
Detector
VTX
RSN
Signal
Transmission
B(RING)
Off-Hook
Detector
RD
RDC
Power Feed
Controller
CAS
VDC
VREG
DA
Ring-Trip
Detector
DB
L
Switching Regulator
VBAT
BGND
AGND
63 dB Pol. Rev.,
32-pin QFN (with exposed pad)
(Green)
RSVD
Le79555-2FQC
BLOCK DIAGRAM
VCC
63 dB Pol. Rev.,
44-pin TQFP (Green)
080125 SLIC Switcher Circuit Application Note
080725 Le79555 Switching Regulator Applications
080753 Le58QL02/021/031 QLSLAC™ Data Sheet
080754 Le58QL061/063 QLSLAC™ Data Sheet
CHCLK
Le79555-2BVC
Packing2
QBAT
Performance Grade / Package1
RELATED LITERATURE
CHS
Device
Zarlink offers a range of compatible SLAC™ devices
providing a complete line circuit that can be optimized for
varying requirements. The SLIC device is designed to operate
with a range of SLAC devices from low cost, nonprogrammable to more advanced, highly programmable
options viable for a range of applications.
Document ID# 080686 Date:
Rev:
G
Version:
Distribution:
Public Document
Sept 19, 2007
3
Le79555
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Ground Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Signal Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Power Feed Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Input Decoder and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Off-Hook Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Ring-Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Ring Relay Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Transmission Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Longitudinal Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Idle Channel Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Insertion Loss and Balance Return Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Line Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
RFI Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Receive Summing Node (RSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Logic Output DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Ring-Trip Detector Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Loop Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Relay Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Test Circuit Scenarios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Application Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Line card Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
32-Pin QFN (8x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Revision A to B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Revision C1 to C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision C2 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision E1 to F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision F1 to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision G2 to G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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Zarlink Semiconductor Inc.
Le79555
Data Sheet
PRODUCT DESCRIPTION
The Le79555 device is designed for short loop and long loop high-density POTS applications requiring a power saving, small
footprint SLIC. The Le79555 device boasts increased power savings over Zarlink's other POTS solutions by using an internal
switching regulator for each channel to enhance system power management. The switching regulator eliminates the need for a
second voltage supply, commonly required for SLIC devices in POTS applications. Such elimination passes on board space and
cost savings to the designers. Thus, the smaller footprint and added features of the Le79555 device allows customers to amortize
the cost of common hardware across more channels and increase the line density per board. Additionally, the Le79555 device
gives line card designers a simple control interface that supports six control states: Active, Ringing, Standby, Disconnect, Reverse
Polarity, and Tip Open. The Le79555 device is a low cost, high performance device providing key features required for POTS
markets worldwide, including: low power dissipation and ground key detection, as well as all of the features offered currently by
Zarlink's Transformer SLIC family, Le7920/22.
BLOCK DESCRIPTIONS
Two-Wire Interface
The two-wire interface provides DC current and sends voice signals to a telephone apparatus connected to the line card with a
two-wire line. The two-wire interface also receives the returning voice signals from the telephone.
Ground Detector
The ground detector block performs ground start and ground key detection, as well as automatically detects a ring-ground fault.
Therefore, when the longitudinal current is greater than the ground key detector threshold, IGK, in either Active, Standby, or Tip
Open, the DET will go low. Note that when the device is in Active or Standby, DET may be an indication of off-hook, ground fault,
or both.
Signal Transmission
The RSN input current controls the receive current sent to the two-wire interface. The AC line voltage is sensed by differential
amplifiers between the A and HPA leads, and between HPB and B leads. The outputs of these amplifiers are equal to the AC
metallic components of the line voltages. The transmission circuit also contains a longitudinal feedback circuit to shunt
longitudinal signals to a DC bias voltage. The longitudinal feedback does not affect metallic signals.
Power Feed Controller
The power feed controller has three sections: (1) the battery feed circuit, (2) the reverse polarity circuit, and (3) the bias circuit.
The battery feed circuit regulates the amount of DC current and voltage supplied to the telephone over a wide range of loop
resistance. The reverse polarity circuit provides the capability to reverse the loop current for pay telephone key pad disable and
other applications. The bias circuit provides a reference voltage, which is offset from the subscriber line voltage. The reference
voltage controls the switched mode regulator, which minimizes SLIC power consumption by providing the minimum supply
voltage needed by the line drivers for proper operation.
Switching Regulator
A switching regulator function is implemented on the chip with a few external components. The power feed controller generates
a reference voltage which is the minimum voltage required to feed the output line amplifiers. The efficiency of the switching
regulator (>80%) minimizes both the on-chip power dissipation and the system power dissipation. This is particularly important
for short loops operating at high currents which otherwise cause high power dissipation.
Input Decoder and Control
The input decoder and control block provides a means for a microprocessor or SLAC IC to control such system functions as line
activate, on-hook transmission, ringing, and reverse polarity. The input decoder and control block has TTL-compatible inputs,
which set the operating states of the SLIC. It also provides the supervision signal sent back to the controller.
Off-Hook Detector
The most important loop monitoring function is off-hook detection. The two-wire interface produces a current equal in magnitude
to the loop current divided by a constant, and sends it out on the RD pin. An external resistor and capacitor (RD and CD) connect
the RD pin to ground. The value of the voltage across resistor RD is proportional to the current leaving the RD pin times the value
of RD. The DET pin will show a logic Low when this voltage rises above a threshold.
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Zarlink Semiconductor Inc.
Le79555
Data Sheet
Ring-Trip Detector
During the Ringing state, the DA pin is more positive than the DB pin, and the DET pin will show high to indicate the on hook.
When an off hook condition occurs, the DB pin becomes more positive than the DA pin, and the DET pin will go low to indicate
an off-hook.
Ring Relay Driver
The ring relay driver is active only in the Ringing state.
Relay Driver
A relay driver is activated by logic Low at either input pin, D1, or D2. D1 controls relay driver RYOUT1; D2 controls relay driver
RYOUT2.
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Zarlink Semiconductor Inc.
Le79555
Data Sheet
VREG
N/C
BGND
N/C
B(RING)
42
41
40
39
38
37
36
DB
N/C
43
N/C
VCC
44
A(TIP)
RINGOUT
CONNECTION DIAGRAMS
35 34
RYOUT1
1
33
DA
RYOUT2
2
32
N/C
L
3
31
RD
VBAT
4
30
N/C
CHS
5
29
HPB
44-Pin TQFP
26
N/C
D2
9
25
VTX
D1
10
24
N/C
C1
11
23
RSVD
RYOUT2
31
30
29
28
27
26
N/C
21 22
RSN
20
A (TIP)
19
DB
18
VDC
17
B (RING)
16
BGND
15
VREG
32
1
14
VCC
RYOUT1
DET
C3
13
RINGOUT
12
AGND/
DGND
8
RDC
HPA
N/C
N/C
N/C
27
CAS
28
7
N/C
6
C2
QBAT
CHCLK
25
24
DA
L
2
23
N/C
VBAT
3
22
RD
CHS
4
21
HPB
32-Pin QFN
QBAT
5
20
HPA
CHCLK
6
19
VTX
D2
7
18
RSVD
D1
8
DET
C3
C2
17
16
13
14
15
RDC
ANGD/
DGND
12
VDC
11
CAS
10
C1
Exposed Pad
9
RSN
Note:
1.
Pin 1 is marked for orientation.
2.
N/C = No Connect
3.
RSVD = Reserved
4.
QFN package only - there is VBAT potential on the exposed pad. Do not connect to GND pin.
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Zarlink Semiconductor Inc.
Le79555
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
AGND/
DGND
Ground
Description
Analog and digital ground.
A(TIP)
Output
Output of A(TIP) power amplifier.
BGND
Ground
Battery (power) ground.
B(RING)
Output
Output of B(RING) power amplifier.
C3–C1
Input
CAS
Capacitor
CHCLK
Input
(Chopper Clock) Input to switching regulator. Freq = 200 to 600 kHz.
CHS
Input
(Chopper Stabilization) Connection for external stabilization components.
D2–D1
Input
Relay Driver Control. D1 and D2 control the relay drivers RYOUT1 and RYOUT2. Logic Low on D1
activates the RYOUT1 relay driver. Logic Low on D2 activates the RYOUT2 relay driver.
DA
Input
Negative input to ring-trip comparator.
DB
Input
Positive input to ring-trip comparator.
DET
Output
SLIC control pins. C3 is MSB and C1 is LSB.
Anti-Saturation pin for capacitor to filter reference voltage when operating in anti-saturation region.
Hook-switch detector. A logic Low indicates that selected condition is detected. The detect condition is
selected by the logic inputs (C3–C1). The output is open-collector with a built-in 15 kΩ pull-up resistor.
HPA
Capacitor
A (TIP) side of high-pass filter capacitor.
HPB
Capacitor
B (RING) side of high-pass filter capacitor.
L
Output
(Switching Regulator Power Transistor) Connection point for filter inductor and anode of catch diode.
This pin will have up to 60 V of pulse waveform on it, and it must be isolated from sensitive circuits.
Care must be taken to keep the diode connections short because of the high currents and di/dt.
N/C
—
QBAT
Battery
(Quiet Battery) Filtered battery supply for the signal-processing circuits.
No Connect. This pin is not internally connected.
RD
Resistor
Detector threshold set and filter pin.
RDC
Resistor
Connection point for the DC feed current programming network. The other end of the network connects
to the receiver summing node (RSN).
RINGOUT
Output
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
Receive Summing Node. In the Active, Reverse Polarity, and Tip Open states, the metallic current
(both AC and DC) between A(TIP) and B(RING) is equal to 500 times the current into this pin. The
networks which program receive gain, two-wire impedance, and feed resistance all connect to this
node.
RSN
Input
RYOUT1
Output
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND.
RYOUT2
Output
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND.
VBAT
Battery
RSVD
—
Most negative battery.
VCC
Power
Supply
+5 V power supply.
VDC
Output
Output that is proportional to the line voltage: VDC = KDC • VAB . KDC is the VDC scale factor.
VREG
Input
(Regulated Voltage) Provides internal negative power supply and connection point for inductor, filter
capacitor, and chopper stabilization.
VTX
Output
Transmit Audio. This output is a 0.50 gain version of the A(TIP) and B(RING) metallic voltage. VTX also
sources the two-wire input impedance programming network.
Exposed
Pad (QFN
package)
Battery
This must be connected to the most negative battery on the SLIC device pin side of DVBH shown on
the test and application circuits.
This is a reserved pin and must always be left open.
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Zarlink Semiconductor Inc.
Le79555
Data Sheet
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods can effect device reliability.
Storage temperature
VCC with respect to AGND
–55 to +150ºC
–0.4 to +7.0 V
VBAT with respect to AGND:
Continuous
10 ms
BGND with respect to AGND
A (TIP) or B (RING) to BGND:
Continuous
+0.4 to –70 V
+0.4 to –75 V
+3 to –3 V
10 ms (f = 0.1 Hz)
1 µs (f = 0.1 Hz)
250 ns (f = 0.1 Hz)
Current from A (TIP) or B (RING)
RINGOUT/RYOUT1,2 current
RINGOUT/RYOUT1,2 voltage
RINGOUT/RYOUT1,2 transient
DA and DB inputs:
–70 to +5 V
–80 to +8 V
–90 to +12 V
±150 mA
50 mA
BGND to +7 V
BGND to +10 V
VBAT to +1 V
VBAT to 0 V
Voltage on ring-trip inputs
Current into ring-trip inputs
C3–C1,D2–D1, CHCLK Input voltage
±10 mA
–0.4 to VCC + 0.4 V
Maximum power dissipation, continuous,
TA = 70°C, No heat sink (See note)
1.4 W
3.0 W
In 44-pin TQFP package
In 32-pin QFN package
Thermal Data:
In 44-pin TQFP package
In 32-pin QFN package
ESD Immunity (Human Body Model)
θJA
52°C/W typ
25° C/W typ
JESD22 Class 1C compliant
Notes:
Thermal limiting circuitry on-chip will shut down the circuit at a junction temperature of about 165° C. Operation above 145° C junction temperature may degrade device reliability.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through multiple vias
to a large internal copper plane.
Package Assembly
Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
Operating Ranges
Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges
by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to
periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component
Reliability Assurance Requirements for Telecommunications Equipment.
Ambient temperature
–40 to +85°C
VCC
4.75 to 5.25 V
VBAT
–40 to –58 V
AGND
0V
BGND with respect to AGND
–100 to +100 mV
Load resistance on VTX to ground
20 kΩ min
7
Zarlink Semiconductor Inc.
Le79555
Data Sheet
SPECIFICATIONS
Refer to Figure 9, on page 16 for the Le79555 test circuit specifications.
Transmission Performance
Description
Two-wire return loss
Test Conditions (See Note 1)
200 Hz to 3.4 kHz
Min
Analog (VTX) output offset voltage
1
20
+50
mV
–50
Overload level, 2-wire
Active state
2.5
Overload level
On hook, RLAC = 600 Ω
1.1
THD, On hook
Max
26
Analog output (VTX) impedance
THD (Total Harmonic Distortion)
Typ
Unit
Note
dB
1, 4
Ω
4
Vpk
0 dBm
–64
–50
+7 dBm
–55
–40
0dBm, RLAC = 600 Ω
dB
–36
2a
2b
5
5
Longitudinal Capability
(See Figure 6.)
Description
Test Conditions
(See Note 1)
Perf.
Grade
Min
Typ
Max
Unit
Note
Normal Polarity:
Longitudinal to metallic L-T, L-4
200 Hz to 1 kHz
0ºC to +70ºC
-2,-4
63
-40ºC to +85ºC
-2,-4
58
4
0ºC to +70ºC
-1,-3
52
-40ºC to +85ºC
-1,-3
50
4
-2
54
4
Reverse Polarity:
-40ºC to +85ºC
0ºC to +70ºC
-1
52
-40ºC to +85ºC
-1
50
4
dB
Normal Polarity:
Longitudinal to metallic L-T, L-4
1 kHz to 3.4 kHz
Longitudinal signal generation 4-L
0ºC to +70ºC
-2,-4
58
-40ºC to +85ºC
-2,-4
53
0ºC to +70ºC
-1,-3
52
-40ºC to +85ºC
-1,-3
50
4
-40ºC to +85ºC
-2
53
4
0ºC to +70ºC
-1
52
-40ºC to +85ºC
-1
4
Reverse Polarity:
50
200 Hz to 3.4 kHz
40
Longitudinal current per pin (A or B)
Active state
17
Longitudinal impedance at A or B
0 to 100 Hz
4
27
mArms
4, 8
25
Ω/pin
4
Unit
Note
Idle Channel Noise
Description
C-message weighted noise
Psophometric weighted noise
Test Conditions (See Note 1)
RL = 600Ω, 0º to +70ºC
Min
Typ
Max
7
+10
RL = 600Ω, –40º to +85ºC
RL = 600Ω, 0º to +70ºC
RL = 600Ω, –40º to +85ºC
8
Zarlink Semiconductor Inc.
+12
–83
–80
–78
dBrnC
4
dBmp
Le79555
Data Sheet
Insertion Loss and Balance Return Signal
(See Figure 4 and Figure 5.)
Description
Gain accuracy, 4- to 2-wire
Test Conditions (See Note 1)
Min
0 dBm, 1 kHz
0º to +70 ºC
–0.10
0 dBm, 1 kHz
−40º to +85 ºC
–0.15
Gain accuracy
2- to 4-wire, 4- to 4-wire
0 dBm, 1 kHz
0º to +70 ºC
–6.12
0 dBm, 1 kHz
−40º to +85 ºC
–6.17
Gain accuracy, 4- to 2-wire
On hook
–0.35
Gain accuracy, 2- to 4-wire, 4- to 4-wire
On hook
–6.37
Gain accuracy over frequency
300 to 3.4 kHz
relative to 1 kHz
0º to +70 ºC
300 to 3.4 kHz
relative to 1 kHz
−40º to +85 ºC
–6.02
Unit
+0.10
3
+0.15
3, 4
–5.92
3
–5.87
3, 4
+0.35
–6.02
Note
3,4
–5.67
dB
+0.10
–0.15
+0.15
3, 4
–0.10
+0.10
3, 4
–0.15
+0.15
3, 4
0 dBm to –37 dBm
–0.15
+0.15
+3 dBm to 0 dBm
–0.35
+0.35
0º to +70 ºC
+3 dBm to –55 dBm
relative to 0 dBm
−40º to +85 ºC
Gain tracking On hook
0
Max
–0.10
+3 dBm to –55 dBm
relative to 0 dBm
Gain tracking
Typ
3
3,4
Line Characteristics
Description
Test Conditions (See Note 1)
IL, Short Loops, Active state
IL, Long Loops, Active state
IL, Standby state
RL = 2010 Ω
RL = 2010 Ω
TA = 25 ºC
RL = 600 Ω (current limit)
ILLIM
Active, A and B to ground
KDC (VDC Scaling)
V DC
K DC = ----------V AB
RL = 300 to 1500 Ω
VAB, Open Circuit voltage
Active state
IA, Leakage, Tip Open state
RL = 0
IB, Current, Tip Open state
B to GND
VA, Active state
RA to BAT = 7 kΩ,
RB to GND = 100 Ω
Min
Typ
Max
22.5
24.5
26.5
20
22.5
Note
mA
15
18
Unit
30
75
120
0.052
0.055
0.058
42.75
44
15
30
–7.5
–5
Min
Typ
V
100
µA
56
mA
V
4
Unit
Note
dB
5
kΩ
4
Power Supply Rejection Ratio
Description
Test Conditions (See Note 1)
VCC, ACTIVE STATE
50 Hz to 3.4 kHz
(VRIPPLE = 100 MV RMS)
30
40
VBAT, ACTIVE STATE
50 Hz to 3.4 kHz
Off-hook constant current region
(VRIPPLE = 500 MV PP)
28
50
Effective internal resistance
CAS pin to VBAT
85
170
9
Zarlink Semiconductor Inc.
Max
255
Le79555
Data Sheet
Power Dissipation
Description
Test Conditions (See Note 1)
On-hook, Standby state
RL = Open
On-hook Active State
RL = Open
Min
Typ
Max
45
70
130
190
Off-hook, Standby state
860
1200
Off-hook Active State
350
400
Unit
Note
mW
Supply Currents
Description
Test Conditions (See Note 1)
ICC,
On-hook VCC supply current
IBAT,
On-hook VBAT supply current + VREG
supply current
Typ
Max
Standby State
Min
2.5
3.2
Active/Polarity Reversed States
4.55
6.0
Open Circuit, RL = Open
2.5
Ringing, RL = Open
6.0
Standby State
0.65
0.9
Active/Polarity Reversed States
2.3
4.0
Open Circuit, RL = Open
0.5
Ringing, RL = Open
1.5
Unit
Note
mA
RFI Rejection
Description
VAB, RMS
Test Conditions (See Note 1)
Min
Typ
100 kHz to 30 MHz, (See Figure 8)
Max
Unit
Note
1.0
mVrms
4
Max
Unit
Note
Receive Summing Node (RSN)
Description
Test Conditions (See Note 1)
Min
Typ
RSN DC voltage
IRSN = 0 mA
0
RSN impedance
200 Hz to 3.4 kHz
10
20
Ω
Typ
Max
Unit
V
4
Logic Inputs
(C3-C1, D2-D1, and CHCLK)
Description
Test Conditions (See Note 1)
VIH, Input High voltage
Min
2.0
VIL, Input Low voltage
0.8
IIH, Input High current
–75
IIL, Input Low current
–400
40
Note
V
µA
Logic Output DET
Description
Test Conditions (See Note 1)
VOL, Output Low voltage
IOUT = 0.3 mA
VOH, Output High voltage
IOUT = –0.1 mA
Min
Typ
Max
0.40
2.4
Unit
Note
V
Ring-Trip Detector Input
(DA, DB)
Description
Test Conditions (See Note 1)
Bias Current
Offset voltage
Source resistance = 2 MΩ
10
Zarlink Semiconductor Inc.
Min
Typ
–500
–50
–50
0
Max
Unit
Note
nA
+50
mV
6
Le79555
Data Sheet
Loop Detector
Description
Min
Typ
Max
RD = 35.4 kΩ
9.4
11.7
14.0
On-hook threshold
RD = 35.4 kΩ
8.8
10.4
12.0
Hysteresis
RD = 35.4 kΩ
IGK, Ground-key detector threshold
RL from BX to GND
Active, Standby, and Tip open
Off-hook threshold
Test Conditions (See Note 1)
Unit
Note
mA
1.3
5
9
13
Min
Typ
Max
Unit
+0.3
+0.7
V
100
µA
Relay Driver Output
(RINGOUT, RYOUT1, RYOUT2)
Description
On voltage
Test Conditions (See Note 1)
IOL = 40 mA
Off leakage
VOH = +5 V
Zener breakover
IZ = 100 µA
Zener On voltage
IZ = 30 mA
6
7.2
8
Note
V
Figure 1. Relay Driver Schematic
RINGOUT,
RYOUT1, RYOUT2
BGND
Unless otherwise noted, RL = 600 Ω. Also, refer to the Le79555 device test circuit in Figure 9, on page 16.
1.
2.
a)
Overload level is defined as THD = 1%.
b)
Overload level is defined as THD = 1.5%.
3.
Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire, AC-load impedance matches
the programmed impedance.
4.
Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6.
Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
7.
Group delay can be greatly reduced by using a ZT network such as that shown in Figure 7. The network reduces the group delay to less
than 2 µs and increases 2WRL. The effect of group delay on line card performance also may be compensated for by synthesizing complex
impedance with the QLSLAC™ device.
8.
Minimum current level guaranteed not to cause a false loop detect.
11
Zarlink Semiconductor Inc.
Le79555
Data Sheet
Table 1. SLIC Device Decoding
State
C3
C2
C1
0
0
0
0
1
0
0
2
0
1
3
0
4
Two-Wire Status
DET Output
Reserved
X
1
Reserved
X
0
Active Reverse Polarity (-1, 2 devices)
Loop detector
1
1
Tip Open
Ring Ground (see note)
1
0
0
Open Circuit
Ring trip
5
1
0
1
Ringing
Ring trip
6
1
1
0
Active
Loop detector
7
1
1
1
Standby
Loop detector
Note:
Ring ground detection in Tip Open is automatic. If longitudinal current is greater than IGK in Active, Standby, or Tip Open, the DET will go low.
Therefore, if in Active or Standby, DET may be an indication of off hook, ground fault, or both.
Table 2. User-Programmable Components
Z T = 250 ( Z 2WIN – 2R F )
ZT is connected between the VTX and RSN pins. The fuse resistors are
RF, and Z2WIN is the desired 2-wire AC input impedance. When
computing ZT, the internal current amplifier pole and any external stray
capacitance between VTX and RSN must be taken into account.
ZL
500Z T
Z RX = ------------- • ---------------------------------------------------G 42L
Z T + 250 ( Z L + 2R F )
ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the
desired receive gain. ZL = Load Impedance, AD to BD.
625
R DC1 + R DC2 = --------------I LOOP
RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1
and RDC2 are approximately equal. ILOOP is the desired loop current in
R DC1 + R DC2
C DC = 1.5 ms • ----------------------------------R DC1 • R DC2
IT
OFF
414
= ---------- ,
RD
IT
ON
368
= ---------- ,
RD
the constant-current region.
0.5 ms
C D = ------------------- RD and CD form the network connected from RD to AGND/DGND and IT
RD
is the threshold current between on-hook and
(IThreshold on to off hook) (IThreshold off to on hook)
off-hook.
1
C CAS = -----------------------------------------170 kΩ • 2π • f c
CCAS is the regulator filter capacitor and fc is the desired filter cut-off
frequency.
V BAT – 3 V
I STANDBY = ------------------------------400 Ω + R L
Standby loop current (resistive region).
12
Zarlink Semiconductor Inc.
Le79555
Data Sheet
DC FEED CHARACTERISTICS
Figure 2.
Load Line (Typical)
50
48
46
2
44
42
40
38
36
34
32
(V)
30
28
1
V AB
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Loop Current (mA)
Regions:
1.
625
V AB = I L R L' = ----------- R L' , where R L' = R L + 2R F
R DC
Constant current region:
R DC = R DC1 + R DC2
2.
VAB = |BAT| − VDiode − 7.2 V − IL(RDC/210)
Battery tracking anti-sat:
Figure 3. Feed Programming
A (TIP)
RSN
RL
IL
RDC1
SLIC
B (RING)
RDC2
RDC
13
Zarlink Semiconductor Inc.
CDC
Le79555
Data Sheet
TEST CIRCUIT SCENARIOS
Figure 4. Two-to-Four-Wire Insertion Loss
A (TIP)
VTX
RL
SLIC
2
V AB
VL
RT
AGND
RL
RRX
2
RSN
B (RING)
IL2-4 = 20 log(V TX / V AB )
Figure 5.
Four-to-Two-Wire Insertion Loss and Balance Return Signal
A (TIP)
VTX
SLIC
V AB
RT
RL
AGND
RRX
B (RING)
RSN
V RX
IL4-2 = 20 log(V AB / V RX )
BRS = 20 log(V TX / V RX )
Figure 6.
1
ωC
Longitudinal Balance
RL
2
S1
VTX
A (TIP)
R > 5)
100 mA
Consult Zarlink
representatives
for further details.
100 nF
20%
16 V
10 k
1%
0.25 W
SMT
1M
1%
0.25 W
SMT
909 k
1%
0.25 W
Capacitor (X7R)
330 nF
20%
100 V
Resistor Hybrid
400
1%
19
Zarlink Semiconductor Inc.
Note
Le79555
Data Sheet
PHYSICAL DIMENSIONS
44-Pin TQFP
Min
Nom
Max
Symbol
A
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
D
12 BSC
D1
10 BSC
E
12 BSC
E1
10 BSC
L
0.45
0.60
0.75
N
44
e
0.80 BSC
b
0.30
0.37
0.45
b1
0.30
0.35
0.40
ccc
0.10
ddd
0.20
aaa
0.20
JEDEC #: MS-026 (C) ACB
Notes:
1. All dimensions and toleerances conform to ANSI Y14.5-1982.
2. Datum plane -H- is located at the mold parting line and is coincident
with the bottom of the lead where the lead exits the plastic body.
3. Dimensions “D1” and “E1” do not include mold protrusion. Allowable
protrusion is 0.254mm per side. Dimensions “D1” and “E1” include
mold mismatch and are determined at Datum plane -H- .
4. Dimension “B” does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08mm total in excess of the “b” dimension at
maximum material condition. Dambar can not be located on the lower
radius or the foot.
5. Controlling dimensions: Millimeter.
6. Dimensions “D” and “E” are measured from both innermost and
outermost points.
7. Deviation from lead-tip true position shall be within ±0.076mm for pitch
!PPDQGZLWKLQIRUSLWFKPP
8. Lead coplanarity shall be within: (Refer to 06-500)
1- 0.10mm for devices with lead pitch of 0.65-0.80mm.
2- 0.076mm for devices with lead pitch of 0.50mm.
Coplanarity is measured per specification 06-500.
9. Half span (center of package to lead tip) shall be
15.30 ± 0.165mm {.602”±.0065”}.
10. “N” is the total number of terminals.
11. The top of package is smaller than the bottom of the package by 0.15mm.
12. This outline conforms to Jedec publication 95 registration MS-026
13. The 160 lead is a compliant depopulation of the 176 lead MS-026
variation BGA.
44-Pin TQFP
Notes:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
BSC is an ANSI standard for basic centering. Dimensions are measured in millimeters.
20
Zarlink Semiconductor Inc.
Le79555
Data Sheet
32-Pin QFN (8x8)
Symbol
A
A2
b
D
D2
E
E2
e
L
N
A1
A3
aaa
bbb
ccc
Min
0.80
0.18
5.70
5.70
0.43
0.00
32 LEAD QFN
Nom
0.90
0.57 REF
0.23
8.00 BSC
5.80
8.00 BSC
5.80
0.80 BSC
0.53
32
0.02
0.20 REF
0.20
0.10
0.10
Max
1.00
0.28
5.90
5.90
0.63
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
is in degrees.
3. N is the total number of terminals.
4. The Terminal #1 identifier and terminal numbering convention
shall conform to JEP 95-1 and SSP-012. Details of the Terminal #1
identifier are optional, but must be located within the zone
indicated. The Terminal #1 identifier may be either a mold or
marked feature.
5. Coplanarity applies to the exposed pad as well as the terminals.
6. Reference Document: JEDEC MO-220.
7. Lead width deviates from the JEDEC MO-220 standard.
0.05
32-Pin QFN
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
21
Zarlink Semiconductor Inc.
Le79555
Data Sheet
REVISION HISTORY
Revision A to B
•
•
Updated document format.
In the "Features" section, the following changes were made:
– Removed "(45 mW)" from Low standby power (since it’s already in the specification).
– Changed battery voltage range from −16 V to −58 V to −40 V to −58 V.
– Removed "(6.5 V)" from Low Off-Hook Active Overhead Voltage.
•
•
In "Related Literature", added the "Introduction to the SLIC Family" application note.
Added the 32-pin PLCC information to the Ordering Information and Absolute Maximum Ratings sections and added the
connection diagram.
Updated the Connection Diagram.
Updated the Pin Description table to correct inconsistencies; added range for CHCLK.
In the Electrical Characteristics table:
– Updated the information in the Line Characteristics section on the Long Loops row and the VDC Accuracy row.
– Deleted the Disconnect state information in the Power Dissipation and Supply Currents sections.
•
•
•
•
In "Specifications", the following changes were made:
– Added a column for performance grade in the Longitudinal Capability and Insertion Loss and Balance Return Signal
tables.
– Changed test circuit reference in the Longitudinal Capability table
– Updated the Insertion Loss and Balance Return Signal table.
– In the Line Characteristics table, IL Standby state test conditions, changed the equation to RL = 2.5 k.
– In the Line Characteristics table, added spec for Overhead Voltage.
– Made changes to test conditions for IL, Long Loops, Active State; KDC (VDC Accuracy); VAB, Open Circuit voltage in
the Line Characteristics table.
– Added value for CHCLK in Note 1.
•
•
In the "DC Feed Characteristics" section, revised equations in notes and updated DC Feed Characteristics graphic.
Changed the equation for ZRX in the User-Programmable table
•
•
•
Updated Engineering Test Circuit and Application Circuit graphics; added graphic for U4/Am79Q063
Added Linecard Parts List page
The physical dimension (PQT044) was added to the Physical Dimension section.
Revision B to C
•
•
•
•
•
•
•
•
Removed current gain feature from the "Features" section
Updated "Related Literature" section to include the QLSLAC data sheets
In the "Ordering Information" table, added dashes before performance grades
Removed package graphic from "Ordering Information" section
Added OPNs for the QFN package in "Ordering Information"; added note regarding markings on QFN packages
Edited "Block Descriptions" section
In "Connection Diagrams," added pinout diagram for 32-pin QFN package; added notes regarding exposed pad and RSVD
pin
In the "Pin Descriptions" table, the following edits were made:
– Updated the Pin Description table to correct inconsistencies
– Edited the description of the RSN pin
– Added range for CHCLK
– Made minor edits to RSVD description
– Added a sentence to the description for VDC
– Added a row to describe the exposed pad
•
In "Electrical Characteristics", "Absolute Maximum Ratings" table, the following was added:
– Max power dissipation of 3.0 W for 32-pin QFN package
– Thermal data for 32-pin QFN package
•
Added a note regarding maximum power dissipation values under the Absolute Maximum Ratings table
22
Zarlink Semiconductor Inc.
Le79555
Data Sheet
•
•
In the "Operating Ranges" table, changed the ambient temperature range to −40º to 85º C
In "Specifications," the following changes were made:
–
"Transmission Performance" table, Overload level, edited test conditions; changed Min to 1.1; changed units to Vpk.
– "Transmission Performance" table, THD, On-hook, edited test conditions; changed units to dB
– "Longitudinal Capability" table, Longitudinal current per pin (A or B), added Note 4 to Note column
–
"Insertion Loss and Balance Return Signal" table, Gain Accuracy, 2-to-4 and 4-to-4 wire, changed Max from -5.82 to 5.87
–
"Insertion Loss and Balance Return Signal" table, deleted the Group delay row
– "Line Characteristics" table, changed KDC (VDC Accuracy) to KDC (VDC Scaling)
– "Line Characteristics" table, IL, Long Loops, Active state, edited the test conditions
– "Line Characteristics" table, KDC (VDC Scaling), edited the test conditions
– "Power Dissipation" table, changed the description "On-hook, Active, Polarity Reversal state" to "On-Hook Active state"
– "Power Dissipation" table, Changed Max value of Off-hook Active State from 380 mW to 400 mW
– "Supply Currents" table, added RL = Open to Open Circuit and Ringing test conditions; deleted references to Note 4
– "Power Dissipation" table, On-hook Standby and On-hook Active, added RL = Open to test conditions
– Changed "Power Supply Rejection Ratio" to "Power Supply Rejection Ratio at the Two-Wire Interface"
– "Power Dissipation" table, On-hook, Standby state, changed Max from 60 to 70
– "Logic Inputs" table, added CHCLK as an input
– "Logic Inputs" table, edited description of VIH, Input High Voltage
– "Logic Inputs" table, deleted row for VIH, C3, CHCLK
– "Logic Inputs" table, edited description of VIL
– "Logic Output DET" table, edited test conditions
– "Loop Detector" table, changed "On threshold" to "Off-hook threshold"
– "Loop Detector" table, changed "Off threshold" to "On-hook threshold"
– Extensively edited Note 1; removed Figure 2, "AC Input Impedance Programming Network"
•
•
Made minor formatting edits to SLIC Device Decoding table
In "User-Programmable Components", the following changes were made:
– Edited equations for ITON and ITOFF
– Edited equation for ZRX and CCAS.
•
•
In "DC Feed Characteristics", edited Note 2
In "Test Circuit Scenarios", the following changes were made:
– Edited title of graphic "Four-to-Four-Wire Insertion Loss and Balance Return Signal"
– Modified Longitudinal Balance graphic
– Modified Two-Wire Return Loss graphic (changed CT1 from 120 pF to 180 pF)
– Modified RFI graphic
– Modified Le79555 test circuit graphic
•
•
•
Modified Application Circuit graphic
Added Note 2 to "Application Circuit" section
Updated Linecard Parts List to reflect the updated application circuit
Revision C1 to C2
•
Formatting updates made
Revision C2 to D1
•
Added green package OPNs to Ordering Information, on page 1
•
Added Package Assembly, on page 7
Revision D1 to E1
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Added "Packing" column and Note 2 to Ordering Information, on page 1
•
Updated 32QFN drawing in Physical Dimensions, on page 20
Revision E1 to F1
•
Removed non-green OPNs, as well as all 1 and 3 dash grade options and 555-4QC and 555-4FQC
23
Zarlink Semiconductor Inc.
Le79555
Revision F1 to G1
•
Modified Application Circuits, on page 17
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Modified Line card Parts List, on page 19
Revision G2 to G3
•
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Enhanced format of package drawings in Physical Dimensions, on page 20
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
24
Zarlink Semiconductor Inc.
Data Sheet
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
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not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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