™
Le79228
Quad Intelligent Subscriber Line Audio-processing Circuit
VE790 Series
Voice Solution
A
APPLICATIONS
ORDERING INFORMATION
Voice over IP/DSL — Integrated Access Devices (IAD),
Smart Residential Gateways (SRG), Home Gateway/
Router
Cable Telephony — NIU, Set-Top Box, Home Side
Box, Cable Modem, Cable PC
Fiber — Fiber in the Loop (FITL), Fiber to the
Home (FTTH)
Wireless Local Loop, Intelligent PBX
DLC-MUX
CO
FEATURES
High performance digital signal processor provides
programmable control of all major line card functions
— A-law/µ-law and linear codec/filter
– Transmit and receive gain
– Two-wire AC impedance
– Transhybrid balance
– Equalization
— DC loop feeding
– Smooth or abrupt polarity reversal
— Loop supervision
– Off-hook debounce circuit
– Ground-key and ring-trip filters
— Internal ringing generation and integrated ring-trip
detection
— Adaptive hybrid balance
— Line and circuit testing
– Meets GR-909 and GR-844 test requirements
— Tone generation (DTMF, FSK, random noise, and
arbitrary tone)
— Metering generation at 12 kHz and 16 kHz
– Envelope shaping and level control
— Modem Tone Detection
Selectable PCM/MPI or GCI digital interfaces
— Supports most available master clock frequencies from
512 kHz to 8.192 MHz
General purpose I/O pins
+3.3 V DC operation
Package1
Device
Packing2
Le79Q2281DVC
64-pin TQFP (Green)
Tray
Le79Q2284MVC
80-pin LQFP (Green)
Tray
1.
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
DESCRIPTION
The Le79228 Quad Intelligent Subscriber Line Audioprocessing Circuit (ISLAC™) device, in combination with a
VE790 series ISLIC™ device, implements a four-channel
universal telephone line interface. This enables the design of a
s i n g l e , l o w c o s t , h i g h p e r f o r m a n c e , f u l l y s o ft w a r e
programmable line interface for multiple country applications.
All AC, DC, and signaling parameters are fully programmable
via microprocessor or GCI interfaces. Additionally, the
Le79228 Quad ISLAC device has integrated self-test and linetest capabilities to resolve faults to the line or line circuit. The
integrated test capability is crucial for remote applications
where dedicated test hardware is not cost effective.
RELATED LITERATURE
081237 Le79232 Dual ISLIC™ Device Data Sheet
081152 Le79242 Dual ISLIC™ Device Data Sheet
081185 Le79252 Dual ISLIC™ Device Data Sheet
081191 Le75282 Dual LCAS Device Data Sheet
080923 Le792x2 Le79228 Chip Set User’s Guide
081151 Le79112 VCP Device Data Sheet
BLOCK DIAGRAM
4
14
VCCA
A1
2
LD2
Dual ISLIC
A3
DGND
VREF
A2
B2
VCCD
LD1
B1
4
Protection
and LCAS or
EMR for
External Ringing
AGND
I/O1 - I/O4
2
TSCA/G
14
TSCB
B3
DRA/DD
P1-P3
Dual ISLIC
LD3
A4
LD4
B4
RREF
4
Exceeds LSSGR and ITU requirements
Supports external ringing with on-chip ring-trip circuit
— Automatic or manual ring-trip modes
Supports CallerNumber Identification (CID) tone
generation
NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and
technology of Legerity Holdings.
External
Ringing
Sense
Resistors
DRB
Quad ISLAC
DXB
DXA/DU
DCLK/S0
5
PCLK/FS
MCLK
RSHB
FS/DCL
BATH
RSLB
CS/RST
DIO/S1
BATL
RSPB
INT
BATP
Document ID# 081256 Date:
Sep 19, 2007
Rev:
G
Version: 2
Distribution:
Protected Document
Le79228
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Optional VCP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Le79228 Quad ISLAC™ Device Internal Block Diagram (80-Pin LQFP) . . . . . . . . . . . . . . . . . . . .5
Features of the Le79228 Quad ISLAC™ Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Transmission Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Transmit and Receive Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Single Frequency Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Gain Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Total Distortion Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
ISLIC Device Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Application Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Line card Parts List- INTERNAL RINGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Line card Parts List - EXTERNAL RINGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
64-Pin Thin Quad Flat Pack (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
80-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision E1 to F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision F1 to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision G1 to G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2
Zarlink Semiconductor Inc.
Le79228
Data Sheet
PRODUCT DESCRIPTION
The VE790 series voice chip sets integrate all functions of the subscriber line for four subscriber lines. One or more of two chip
types are used to implement the line card; a VE790 series ISLIC device and a Le79228 Quad ISLAC device. These provide the
following basic functions:
1.
The VE790 series ISLIC device: A high voltage, bipolar IC that drives the subscriber line, maintains longitudinal balance and
senses line conditions.
2. The Le79228 Quad ISLAC device: A low voltage CMOS IC that provides conversion and DSP functions for all four channels.
Complete schematics of line cards using the Le79228 Quad ISLAC device for internal and external ringing are shown in
Application Circuits, on page 28.
The VE790 series ISLIC device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of
subscriber lines. It can be programmed by the Quad ISLAC device to operate in eight different modes that control power
consumption and signaling. This enables it to have full control over the subscriber loop. The VE790 series ISLIC device is
designed to be used exclusively with the Le79228 Quad ISLAC device as part of a multiple-line chip set.
The VE790 series ISLIC device implements a linear loop-current feeding method with the enhancement of intelligent thermal
management in a controlled manner. This limits the amount of power dissipated on the VE790 series ISLIC chip by dissipating
excess power in external resistors.
Each Le79228 Quad ISLAC device contains high-performance analog circuits that provide A/D and D/A conversion for voice
(codec/filter), DC-feed and supervision signals for four subscriber channels. The Le79228 Quad ISLAC device contains a DSP
core that handles signaling, DC-feed, supervision and line diagnostics for all four channels.
The DSP core selectively interfaces with three types of backplanes:
•
Standard PCM/MPI
•
Standard GCI
•
Modified GCI with a single analog line per GCI channel
The Le79228 Quad ISLAC device provides a complete software configurable solution to the BORSCHT functions as well as
complete programmable control over subscriber line DC-feed characteristics, such as current limit and feed resistance. In
addition, these chip sets provide system level solutions for the loop supervisory functions and metering. In total, they provide a
programmable solution that can satisfy worldwide line card requirements by software configuration.
Software programmed filter coefficients, DC-feed data and supervision data are easily calculated with the WinSLAC software.
This PC software is provided free of charge and allows the designer to enter a description of system requirements. WinSLAC
then computes the necessary coefficients and plots the predicted system results.
The VE790 series ISLIC device interface unit inside the Le79228 Quad ISLAC device processes information regarding the line
voltages, loop currents and battery voltage levels. These inputs allow the Le79228 Quad ISLAC device to place several key
VE790 series ISLIC device performance parameters under software control.
The main functions that can be observed and/or controlled through the Le79228 Quad ISLAC device backplane interface are:
•
DC-feed characteristics
•
Ground-key detection
•
Off-hook detection
•
Metering signal
•
Longitudinal operating point
•
Subscriber line voltage and currents
•
Ring-trip detection
•
Abrupt and smooth reversal
•
Subscriber line matching
•
Ringing generation
•
Sophisticated line and circuit tests
To accomplish these functions, the VE790 series ISLIC device collects the following information and feeds it, in analog form, to
the Le79228 Quad ISLAC device:
•
•
The metallic (IMT) and longitudinal (ILG) loop currents
The AC (VTX) and DC (VSAB) loop voltages
The outputs supplied by the Le79228 Quad ISLAC device to the VE790 series ISLIC device are then:
•
A voltage (VHLi*) that provides control for the following high-level VE790 series ISLIC device outputs:
•
DC loop current
3
Zarlink Semiconductor Inc.
Le79228
•
•
•
Internal ringing signal
12- or 16-kHz metering signal
A low-level voltage proportional to the voice signal (VOUTi)
•
A voltage that controls longitudinal offset for test purposes (VLBi)
Data Sheet
The Le79228 Quad ISLAC device performs the codec and filter functions associated with the four-wire section of the subscriber
line circuitry in a digital switch. These functions involve converting an analog voice signal into digital PCM samples and converting
digital PCM samples back into an analog signal. During conversion, digital filters are used to band-limit the voice signals.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment
of the two-wire termination impedance and provide frequency attenuation adjustment (equalization) of the receive and transmit
paths. Transhybrid balancing is also included. All programmable digital filter coefficients can be calculated using WinSLAC™
software. The PCM codes can be either 16-bit linear two’s-complement or 8-bit companded A-law or µ-law.
Besides the codec/filter functions, the Le79228 Quad ISLAC device provides all the sensing, feedback, and clocking necessary
to completely control VE790 series ISLIC device functions with programmable parameters. System-level parameters under
programmable control include active loop current limits, feed resistance, and feed mode voltages.
The Le79228 Quad ISLAC device supplies complete mode control to the VE790 series ISLIC device using the control bus and
(P1-P3) tri-level load signal (LDi).
The Le79228 Quad ISLAC device provides extensive loop supervision capability including off-hook, ring-trip and ground-key
detection. Detection thresholds for these functions are programmable. A programmable debounce timer is available that
eliminates false detection due to contact bounce.
For subscriber line diagnostics, AC and DC line conditions can be monitored using built in test tools. Measured parameters can
be compared to programmed threshold levels to set a pass/fail bit. The user can choose to send the actual PCM measurement
data directly to a higher level processor by way of the voice channel. Both longitudinal and metallic resistance and capacitance
can be measured, which allows leakage resistance, line capacitance, and telephones to be identified.
*Note:
"i" denotes channel number
OPTIONAL VCP FEATURES
Optional Voice Control Processor (VCP) features provide the following solutions to the VE790 series intelligent chip sets:
•
•
•
Integrated test software routines
DTMF detection
Aggregated codec/filter control
4
Zarlink Semiconductor Inc.
Le79228
Data Sheet
Le79228 Quad ISLAC™ Device Internal Block Diagram (80-Pin LQFP)
IREF VREF
VHL1
Clock and
Reference
Circuits
VLB1
VOUT1
VIN1
VSAB1
VIMT1
Ch 1
Converter
Block
PCM
and
GCI
Interface
and
Time Slot
Assigner
VILG1
GS1
GS2
XSB1
MCLK
FS/DCL
PCLK/FS
DXA/DU
DRA/DD
TSCA/G
DXB
DRB
TSCB
DCLK/S0
DIN/S1
Ch 2
(Same as Ch 1)
Digital
Signal
Processor
GCI Control
Logic and
Microprocessor
Interface
Ch 3
(Same as Ch 1)
790 Series SLIC
Control
Logic
Ch 4
(Same as Ch 1)
Common
External
Sense
Inputs
5
Zarlink Semiconductor Inc.
DOUT
CS/RST
INT
I/O1
I/O2
I/O3
I/O4
LD1
LD2
LD3
LD4
P1
P2
P3
XSC
SHB
SLB
SPB
Le79228
Data Sheet
Features of the Le79228 Quad ISLAC™ Chip Set
•
•
•
•
•
•
•
•
•
Performs all battery feed, ringing, signaling, hybrid and
test (BORSCHT) functions
Two chip solution supports high density, multi-channel
architecture
Single hardware design meets multiple country requirements through software programming of:
– Ringing waveform and frequency (for balanced ringing)
– DC loop-feed characteristics and current-limit
– Loop-supervision detection thresholds
–Off-hook debounce circuit
–Ground-key and ring-trip filters
– Off-hook detect de-bounce interval
– Two-wire AC impedance
– Transhybrid balance impedance
– Transmit and receive gains
– Equalization
– Digital I/O pins
– A-law/µ-law and linear selection
Supports internal and external battery-backed or earthbacked ringing
– Self-contained ringing generation and control
– Supports external ringing generator and ring relay
– Ring relay operation synchronized to zero crossings
of ringing voltage and current
– Integrated ring-trip filter and software enabled manual or automatic ring-trip mode
Supports metering generation with envelope shaping
Smooth or abrupt polarity reversal
Adaptive transhybrid balance
– Continuous or adapt and freeze
Supports both loop-start and ground-start signaling
Exceeds LSSGR and CCITT central office requirements
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Selectable PCM or GCI interface
– Supports most available master clock frequencies
from 512 kHz to 8.192 MHz
On-hook transmission
Power/service denial mode
Line-feed characteristics independent of battery voltage
Only 5 V, 3.3 V and battery supplies needed
Low idle-power per line
Linear power-feed with intelligent power-management
feature
Compatible with inexpensive protection networks;
Accommodates low-tolerance fuse resistors while maintaining longitudinal balance
Monitors two-wire interface voltages and currents for
subscriber line diagnostics
Tone generation
– DTMF
– FSK
– Random noise
– Arbitrary tone
Built-in voice path test modes
Power-cross, fault, and foreign voltage detection
Meets GR-909 and GR-844 test requirements
Integrated line-test features
– Leakage
– Line and ringer capacitance
– Loop resistance
Integrated self-test features
– Echo gain, distortion, and noise
Small physical size
Up to three relay drivers per VE790 series ISLIC device
– Configurable as test load switches
6
Zarlink Semiconductor Inc.
Le79228
Data Sheet
CONNECTION DIAGRAMS
57
VOUT 3
58
VIN 3
XSB 4
59
VHL 3
VLB 4
60
VSAB 3
VIMT 4
61
VILG 3
VILG 4
62
VIMT 3
VSAB 4
63
VLB 3
VHL 4
64
56 55
54
53
52
51
50
49
XSB 3
VIN 4
64-Pin TQFP Connection Diagram
VOUT 4
Figure 1.
XSC
1
48
VCCA 3
VCCA 4
2
47
IREF
SHB
3
46
VREF
4
45
XSB1
XSB 2
5
44
AGND 2
AGND 1
6
43
VLB 1
SLB
VLB 2
7
42
VIMT 1
VIMT 2
8
41
VILG 1
VILG 2
9
40
VSAB 1
VSAB 2
10
39
VCCA 1
VCCA 2
11
38
VHL 1
VHL 2
12
37
VIN 1
VIN 2
13
36
VOUT 1
VOUT 2
14
35
DGND 2
15
34
LD 3
16
33
LD 1
P3
P2
P1
INT
MCLK
PCLK/FS
25
26
27
28
29
30
31
32
CS/RST
24
DIO/S1
23
DCLK/S0
22
VCCD
21
TSCA/G
20
DXA/DU
19
DRA/DD
18
FS/DCL
17
LD 4
DGND 1
LD 2
SPB
64-Pin TQFP
7
Zarlink Semiconductor Inc.
Le79228
Data Sheet
GS24
XSC
VOUT4
VIN4
VHL4
VSAB4
VILG4
VIMT4
VLB4
XSB4
XSB3
VLB3
VIMT3
VILG3
VSAB3
VHL3
VIN3
VOUT3
GS14
GS13
Figure 2. 80-Pin LQFP Connection Diagram
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
60
GS23
SHB
2
59
VCCA3
SLB
3
58
IREF
XSB2
VCCA4
4
57
VREF
AGND1
5
56
XSB1
VLB2
6
55
AGND2
VIMT2
7
54
VLB1
VILG2
8
53
VIMT1
VSAB2
9
52
VILG1
VCCA2
10
51
VSAB1
VHL2
11
50
VCCA1
VIN2
80-Pin TQFP
12
49
VHL1
VOUT2
13
48
VIN1
SPB
14
47
VOUT1
DGND1
15
46
DGND2
I/O4
16
45
I/O3
I/O2
17
44
I/O1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DIN/S1
DCLK/S0
CS/RST
GS21
GS11
26
DOUT
25
VCCD
24
TSCA/G
23
DXA/DU
22
TSCB
21
DRA/DD
LD1
FS/DCL
41
PCLK/FS
20
MCLK
GS22
INT
LD3
P1
42
P2
DRB
P3
43
19
LD4
18
LD2
DXB
GS12
8
Zarlink Semiconductor Inc.
Le79228
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
Description
AGND1,
AGND2
Ground
CS/RST
Input
For PCM backplane operation, a logic Low on this pin for 16 or more DCLK cycles resets the sequential logic in
the Le79228 Quad ISLAC device into a known mode. A logic low placed on this pin for less than 15 DCLK cycles
is a chip select and enables serial data transmission into or out of the DIO port. For GCI operation, a logic low on
this pin for 1 µs or longer resets the sequential logic into a known mode. This pin is 5-V tolerant.
DCLK/S0
Input
Provides data control for MPI interface control. For GCI operation, this pin is device address bit 0. This pin is 5-V
tolerant.
DGND1,
DGND2
Ground
DIN/S1
Input
For PCM backplane operation, control data is serially written into the Le79228 Quad ISLAC device via the DIN pin
with the MSB first. The data clock (DCLK) determines the data rate. For GCI operation, this pin is device address
bit 1. This pin is 5 V tolerant. DIN/S1 is available only on the 80-pin LQFP package.
DIO/S1
Input/
Output
For PCM backplane operation, control data is serially written into and read out of the Le79228 Quad ISLAC device
via the DIO pin with the MSB first. The data clock (DCLK) determines the data rate. DIO is high impedance except
when data is being transmitted from the Le79228 Quad ISLAC device under control of CS/RST. For GCI operation,
this pin is device address bit 1. This pin is 5-V tolerant. DIO/S1 is available only on the 64-pin TQFP package.
Output
For PCM backplane operation, control data is serially read out of the Le79228 Quad ISLAC device via the DOUT
pin with the MSB first. The data clock (DCLK) determines the data rate. DOUT is high impedance except when
data is being transmitted from the Le79228 Quad ISLAC device under control of CS/RST. This pin is 5-V tolerant.
DOUT is available only on the 80-pin LQFP package.
Input
For the PCM highway, the receive PCM data is input serially through the DRA or DRB pins. The data input is
received every 125 µs and is shifted in, MSB first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate. The receive
port can receive information for direct control of the VE790 series ISLIC device. This mode is selected in Device
Configuration Register 2 (RTSEN=1, RTSMD=1). When selected, this data is received in an independently
programmable timeslot from the PCM data. For the GCI mode, downstream receive and control data is accepted
on this pin. This pin is 5 V tolerant. The DRB pin is available only on the 80-pin LQFP package.
Output
For the PCM highway, the transmit PCM data is transmitted serially through the DXA or DXB pins. The
transmission data output is available every 125 µs and is shifted out, MSB first, in 8-bit PCM or 16-bit linear bursts
at the PCLK rate. DXA and DXB are high impedance between bursts and while the device is in the inactive mode.
Can also select a mode (RTSEN= 1, RTSMD=1 or 0 in Device Configuration Register 2) that transmits the
Signaling Register MSB contents first, in an independently programmable timeslot from the PCM data. This data
is transmitted in all modes except disconnect. For the GCI mode, upstream transmit and signaling data is
transferred on this pin. This pin is 5 V tolerant. The DXB pin is available only on the 80-pin LQFP package.
FS/DCL
Input
For PCM operation, pin is Frame Sync. PCM operation is selected by the presence of an 8 kHz Frame Sync signal
on this pin in conjunction with the PCLK on the PCLK/FS pin (see below). This 8 kHz pulse identifies the beginning
of a frame. The Le79228 Quad ISLAC device references individual timeslots with respect to this input, which must
be synchronized to PCLK. GCI operation is selected by the presence of the downstream clock DCL, on this pin in
conjunction with the presence of a FS on the PCLK/FS pin. In GCI mode, the data rate is 2 MHz and DCL must
be either 2 or 4 MHz. This pin is 5-V tolerant.
GS11–
GS14,
GS21–
GS24
Output
Gain select nodes for VILG and VIMT inputs. This node provides a switched tie point to VREF. The GS pins are
available only on the 80-pin LQFP package.
VILG1–
VILG4
Input
Longitudinal current input from ISLIC device. Voltage generated by RLG is sensed by this pin. Tie pin to VREF if
channel unused.
VIMT1–
VIMT4
Input
Metallic current input from ISLIC device. Voltage generated by RMT is sensed by this pin. Tie pin to VREF if
channel unused.
DOUT
DRA/DD,
DRB
DXA/DU,
DXB
INT
I/O1–I/O4
IREF
Analog circuitry ground returns
Digital ground returns
Output
For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to interrupt a higher level
processor. Several registers work together to control operation of the interrupt: Signaling and Global Interrupt
Registers with their associated Mask Registers, and the Interrupt Register. See the description at channel
configuration register 6 (Mask) for operation. Logic drive is selectable between open drain and TTL-compatible
outputs.
Input/
Output
General purpose, logic input/output connection for each of 4 channels. These control lines can be programmed
as an input or output in the Global I/O Direction Register. When programmed as outputs, they can control an
external logic device. When programmed as inputs, they can monitor external logic circuits. Data for these pins
can be written or read individually (from the channel specific I/O Register) or as a group (from the Global I/O Data
Register). The I/O pins are available only on the 80-pin LQFP package.
Input
External resistor (RREF) connected between this pin and analog ground generates an accurate, on-chip reference
current for the A/D's and D/A's on the Le79228 Quad ISLAC device.
9
Zarlink Semiconductor Inc.
Le79228
Pin Name
Data Sheet
Type
Description
Output
The LD pins output 3-level voltages. When LDi is a logic 0 (< 0.4 V), the destination of the code on P1–P3 is the
relay control latches in the VE790 series ISLIC device control register. When LDi is a logic 1 (>VCC−0.4 V), the
destination of P1–P3 is the mode control latches. LDi is driven to VREF when the contents of the VE790 series
ISLIC device control register must not change.
Input
For PCM backplane operation, the DSP master clock may connect here. A signal is required only for PCM
backplane operation when PCLK is not used as the master clock. MCLK can be a wide variety of frequencies, but
must be synchronous to FS. Upon initialization, the MCLK input is disabled, and relevant circuitry is driven by a
connection to PCLK. This pin is 5-V tolerant.
Input
For PCM operation, this is PCM Clock. PCM operation is selected by the presence of a PCLK signal on this pin
in conjunction with the FS on the FS/DCL pin (see above). For PCM backplane operation, connect a data clock,
which determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK can be any
integer multiple of the FS frequency. The minimum clock frequency for linear/ companded data plus signaling data
is 256 kHz. For GCI operation, this pin is Frame Sync. The FS signal is an 8 kHz pulse that identifies the beginning
of a frame. The Le79228 Quad ISLAC device references individual timeslots with respect to this input, which must
be synchronized to DCL. This pin is 5-V tolerant.
Output
Control the operating modes of the VE790 series ISLIC devices connected to the Le79228 Quad ISLAC device.
Input
Resistors that sense the high, low and positive battery voltages connect here. If only one negative battery is used,
connect both negative battery resistors to the same supply. If two negative batteries are used, SHB must be
connected to the battery intended to supply on-hook voltage, whether BATH or BATL. If the positive battery is not
used, leave the SPB pin unconnected. These pins are current inputs whose voltage is held at VREF.
Output
(PCM)
Input (GCI)
For PCM backplane operation, TSCA is active low when PCM data is output on the DXA or DXB pins,
respectively. The outputs are open-drain and are normally inactive (high impedance). Pull-up loads should be
connected to VCCD. When GCI mode is selected, one of two GCI modes may be selected by connecting TSCA/
G to DGND or VCCD.
TSCB
Output
For PCM backplane operation, TSCA or TSCB is active low when PCM data is output on the DXA or DXB pins,
respectively. The outputs are open-drain and are normally inactive (high impedance). Pull-up loads should be
connected to VCCD. TSCB is only available on the 80 pin LQFP package. When GCI mode is selected, one of
two GCI modes may be selected by connecting TSCA/G to DGND or VCCD. TSCB is available only on the 80pin LQFP package.
VCCA1–
VCCA4
Supply
+3.3 VDC supplies to the analog sections in each of the four channels.
VCCD
Supply
+3.3 VDC supply to all digital sections.
VHL1–
VHL4
Output
High-level loop control. Voltages on these pins are used to control DC-feed, internal ringing, metering and polarity
reversal for each VE790 series ISLIC device.
VIN1–
VIN4
Input
Analog transmit signals (VTX) from each VE790 series ISLIC device connect to these pins. The Le79228 Quad
ISLAC device converts these signals to digital words and processes them. After processing, they are multiplexed
into serial time slots and sent out of the DXA/DU or DXB pin. Tie pin to VREF if channel unused.
LD1–LD4
MCLK
PCLK/FS
P1–P3
SHB,
SLB, SPB
TSCA/G
VOUT1–
VOUT4
Output
Analog receive voltage signals are sent out of the Le79228 Quad ISLAC device from these pins. A resistor
converts these signals to currents which drive the VE790 series ISLIC device.
VLB1–
VLB4
Output
Normally connected to VCCA internally. They supply longitudinal reference voltages to the VE790 series ISLIC
devices during certain test procedures. These outputs are connected internally to VCCA during VE790 series
ISLIC Active, Standby, Ringing, and Disconnect modes. During test modes, it can be connected to the receive D/A.
VREF
Output
This pin provides a 1.4-V, single-ended reference to the VE790 series ISLIC devices to which the Le79228 Quad
ISLAC device is connected.
VSAB1–
VSAB4
Input
Connect to the VSAB pins of four VE790 series ISLIC device channels.
XSB1–
XSB4
Input
External ringing sense pin. This pin senses the current through RSRB to measure the ringing voltage on the line.
XSC
Input
External ring generator sense. This pin senses the current RSRC to measure the ringing bus voltage.
Package Type
80 pin
64 pin
I/O1–I/O4
Pin Options
√
x
DRB, DXB, TSCB
√
x
DIN/S1
√
x
DOUT
√
x
DIO/S1
x
√
GS11–GS14, GS21–GS24
√
Note: For the 80-pin LQFP package, DOUT and DIN/S1 can be connected together.
10
Zarlink Semiconductor Inc.
x
Le79228
Data Sheet
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability.
Storage Temperature
–60ºC ≤ TA ≤ +125ºC
Ambient Temperature, under Bias
–40ºC ≤ TA ≤ +85ºC
Ambient relative humidity (non condensing)
5 to 95%
VCCA with respect to (AGND or DGND)
–0.4 to + 4.0 V
VCCD with respect to (AGND or DGND)
–0.4 to + 4.0 V
VCCA with respect to VCCD
±0.4V
VIN, VIMT, VILG, VSAB with respect to (AGND or DGND)
–0.4 to (VCCA + 0.4 V)
5-V tolerant pins
–0.4 to (VCCD + 2.37) or 5.5 V,
whichever is less
AGND
DGND ± 0.4 V
Latch up immunity, 25ºC (any pin)
±100 mA
Latch up immunity, 85ºC (pin I/O4)
±50 mA
Latch up immunity, 85ºC (all other pins)
±100 mA
Any other pin with respect to DGND
–0.4 V to VCC
Package Assembly
The green package devices are assembled with enhanced environmental compatible lead (Pb), halogen, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
Operating Ranges
Legerity guarantees the performance of this device over commercial (0º to 70ºC) and industrial (−40º to 85ºC) temperature
ranges by conducting electrical characterization over each range and by conducting a production test with single insertion
coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore TR-TSY-000357
Component Reliability Assurance Requirements for Telecommunications Equipment.
Environmental Ranges
Ambient Temperature
–40 to +85ºC
Ambient Relative Humidity
15 to 85%
Electrical Ranges
Analog Supply VCCA
+3.3 V + 5%, - 10%
Digital Supply VCCD
+3.3 V ± 5%
DGND
0V
AGND
DGND ±10 mV
5-V tolerant pins with respect to DGND
DGND to 5.25V
11
Zarlink Semiconductor Inc.
Le79228
Data Sheet
DC Specifications
No.
1
Min
Typ
Max
Input Low Voltage, I/O1–I/O4
Item
Condition
–0.05
—
1.36 V
All other digital inputs
–0.50
—-
0.80 V
Input High Voltage, I/O1–I/O4
2.46
—-
VCC+0.4
All other digital inputs
2.0
—
5.25
Digital input capacitance
2
3
4
4
Input Leakage Current, I/O1–I/O4
0 to VCC
–10
—-
+10
All other digital inputs
0 to 5.25 V
–120
—-
+180
Input hysteresis (PCLK/FS, FS/DCL,
MCLK, DIO, DRA, DRB)
0.15
0.225
0.30
Input hysteresis (I/O1–I/O4)
0.16
0.25
0.34
Unit
Note
V
pF
2.
V
µA
V
2.
Ternary output voltages, LD1–LD4
5
6
7
8
High voltage
Iout = 1 mA
VCC–.4
—
—
Low voltage
Iout = 2 mA
—
—
0.4
Medium voltage
±10 µA
—
VREF
—
Output Low Voltage (DXA/DU, DIO,
I/O1–I/O4, INT, TSCA, TSCB, DXB)
Iol = 10mA
—
—-
0.4
Iol = 5 mA
—
—
0.4
VCC–0.4
—
—
–1
±0.2
1
—
VREF
±1.02
—
—
1.02
—
–50
—
+50
–40
—
+40
–80
—
Output Low Voltage
(P1-P3)
Output High Voltage (All digital outputs
except INT in open drain mode and
TSCA, TSCB)
Ioh = 400 µA
V
V
Input Leakage Current
9
(VIN1–VIN4, VSAB1–VSAB4,
VILG1–VILG4, VIMT1–VIMT4,
µA
GS11–GS14, GS21–GS24)
Full scale input voltage (VIN1–VIN4)
µ-law
3.205 dBm0
A-law
3.14 dBm0
11
Input Voltage (VSAB1–VSAB4 or
VIMT1–VIMT4 or VILG1–VILG4)
|Vov–VREF| where Vov
is input overload
voltage
12
Offset voltage allowed on VIN1–VIN4
10
DISN off
V
13
VOUT1–VOUT4 offset Voltage
14
VHL1–VHL4 D/A absolute error
% of D/A code
15
Output voltage, VREF
Load current = 0 to 10
mA, Source or Sink
16
Capacitance load on VREF and
GS11–GS14, GS21–GS24 or VOUT1–
VOUT4
17
Output drive current, VOUT1–VOUT4
or VLB1–VLB4
Source or Sink
–1
—
+1
18
Maximum output voltage, VOUT1–
VOUT4
|VOUT–VREF| with
peak digital input
—
1.02
—
19
VLB1–VLB4 operating voltage
Source current < 250µA
Sink current < 25 µA.
20
Maximum output voltage on VHL
|VHL–VREF| with peak
digital input, VFD = 0
21
VSAB1–VSAB4, VIMT1–VIMT4,
VILG1–VILG4 A/D absolute error
22
Battery read A/D absolute error
DISN on
–15 -2%
mV
4.
+80
+15 +2%
mV
1.32
1.4
1.48
V
0
—
200
pF
2.
VREF
–1.02
—
VREF
+1.02
mA
V
8.
—
1.02
—
% of input voltage
–5 –2%
—
+5 +2%
mV
9.
% of input voltage
–2 –6%
—
+2 +6%
V
9.
12
Zarlink Semiconductor Inc.
Le79228
No.
Item
Condition
Data Sheet
Min
Typ
Max
Unit
–4.8
–5
–5.2
V/V
–50
0
50
mV
23
Gain from VSAB1–VSAB4 to VHL1–
VHL4 (KRFB)
24
VSAB1–VSAB4 to VHL1–VHL4 output
offset (KRFB)
25
Gain from VSAB1–VSAB4 to VHL1–
VHL4
VFD = 0, hook bit
feedback
–
–0.128
–
V/V
26
% error of VLB1–VLB4 voltage (For
VLB equation, see the Chip Set User’s
Guide)
% of input voltage
–5
0
+5
%
27
Capacitance load on VLB1–VLB4
0
—
120
28
Capacitance load on XSB1–XSB4,
XSC
0
—
400
—
183
235
VFD = 1
One channel active
(VE790 series ISLIC
state register set to
active); three channels
inactive (VE790 series
ISLIC state register set
to Standby)
29
Power Dissipation
All channels active
(VE790 series ISLIC
state register set to
Active)
—
264
340
All channels inactive
(VE790 series ISLIC
state register set to
Standby)
—
143
188
Note
pF
2.
mW
Transmission Specifications
Table 1. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
Transmit
Receive
A-law digital mW or equivalent (0 dBm0)
Signal at Digital Interface
0.5026
0.5026
µ-law digital mW or equivalent (0 dBm0)
0.4987
0.4987
±5,800 peak linear coded sine wave
0.5026
0.5025
Unit
Vrms
Note: Expressed voltage levels on VOUT or input to VIN are equivalent to a digital milliwatt on the digital interface.
13
Zarlink Semiconductor Inc.
Le79228
No.
Item
Insertion Loss
1
A-D, D-A
A-D + D-A
Data Sheet
Min
Typ
Max
Input: 1014Hz, 0dBm0
AR = AX = GR = GX = 0 dB,
DISN, R, X, B and Z disabled
Condition
–0.25
0
+0.25
Temperature = 25°C
–0.15
0
+0.15
Variation over temperature
–0.1
0
+0.1
2
Level set error (Error between
setting and actual value)
A-D AX + GX
D-A AR + GR
–0.1
0
0.1
3
DR to DX gain in full digital
loopback mode
DR Input: 1014 Hz, –10 dBm0
AR=AX=GR=GX=0 dB, DISN,
R, X, B and Z filters default
–0.3
0
+0.3
4
Idle Channel Noise,
Psophometric Weighted (A-law)
5
A-D (PCM output)
—
—
–69
D-A (VOUT)
—
—
–78
Idle Channel Noise,
C Message weighted (µ-law)
A-D (PCM output)
—
—
+19
D-A (VOUT)
—
—
+12
6
Coder Offset decision value, Xn
A-D, Input signal = 0 V
–7
0
+7
7
PSRR Image frequency (VCC)
A-D
Input: 4.8 to 7.8 kHz,
200 mVp-p
37
—
—
8
PSRR Image frequency (VCC)
D-A
Measure at:
8000 Hz − Input frequency
37
—
—
9
DISN gain accuracy
10
End-to-end group delay
11
12
+0.2
Vin = 0 dBm0
B = Z = 0; X = R = 1
—
—
3., 7.
dBm0p
5.
dBrnC0
Bits
2.
1
525
µS
–75
dBm0
0 dBm0
300 Hz to 3400 Hz
—
—
RX to TX
0 dBm0
300 Hz to 3400 Hz
—
—
Crosstalk
TX or RX to TX
0 dBm0
1014 Hz
—
—
–76
other channel
TX or RX to RX
0 dBm0
1014 Hz
—
—
–78
TX to RX
dB
dB
same channel
Crosstalk
Note
dB
Gdisn = –0.9375 to 0.9375
1014Hz; –10dBm0
Unit
2., 6.,
8.
2.
dBm0
Notes:
1.
Not tested or partially tested in production. This parameter is guaranteed by characterization or correlation to other tests.
2.
Guaranteed by design.
3.
Overall 1.014 kHz insertion loss error of the Le79228 Quad ISLAC device is guaranteed to be 0.34 dB
4.
These voltages are referred to VREF.
5.
When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to –12
dB.
6.
Group delay spec valid only when Channels 1–4 occupy consecutive slots in the frame. Programming channels in non-consecutive timeslots
can add up to 1 frame delay in the Group delay measurements. The Group delay specification is defined as the sum of the minimum values
of the group delays for transmit and the receive paths when the B, X, R, and Z filters are disabled with null coefficients. See Figure 5, on
page 16.
7.
Requires that the calibration command (7Ch) must be performed to achieve this performance.
8.
An additional frame of delay can be added if PCLK frequencies less than 1.536 MHz are used.
9.
In the absence of any error, the analog level of VREF + 1.02 V represents a digital code of 7FFFh, and the analog level of VREF - 1.02 V
represents a digital code of 8000h.
Transmit and Receive Paths
In this section, the transmit path is defined as the analog input to the Le79228 Quad ISLAC device (VINn) to the PCM voice output
of the Le79228 Quad ISLAC device A-law/µ-law speech compressor. The receive path is defined as the PCM voice input to the
Le79228 Quad ISLAC device speech expander to the analog output of the Le79228 Quad ISLAC device (VOUTn). All limits
defined in this section are tested with B = 0, Z = 0 and X = R = GR = 1.
When AR is enabled, a nominal gain of –6.02 dB is added to the analog section of the receive path.
When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path.
When relative levels (dBm0) are used in any of the following transmission characteristics, the specification holds for any setting
of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to –12 dB.
14
Zarlink Semiconductor Inc.
Le79228
Data Sheet
These transmission characteristics are valid for 0 to 70º C.
Attenuation Distortion
The attenuation of the signal in either path is nominally independent of the frequency. The deviations from nominal attenuation
will stay within the limits shown in Figure 3 and Figure 4. The reference signal level is –10 dBm0. The minimum transmit
attenuation at 60 Hz is 24 dB.
Figure 3. Transmit Path Attenuation vs. Frequency
Attenuation (dB)
2
1
0.80
0.65
0.6
0.2
0.125
0
-0.125
3400
3200
Frequency (Hz)
3000
600
0
200
300
Acceptable Region
Figure 4. Receive Path Attenuation vs. Frequency
1
0.75
0.125
0
-0.125
Frequency (Hz)
15
Zarlink Semiconductor Inc.
0
3400
0
200
300
Acceptable Region
3000
Attenuation (dB)
2
Le79228
Data Sheet
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 5. The minimum value of the group
delay is taken as the reference. The signal level is –10 dBm0.
Figure 5. Group Delay Distortion
420
Delay (µS)
150
Acceptable
Region
2800
Frequency (Hz)
2600
1000
600
0
500
90
Single Frequency Distortion
The output signal level, at any single frequency in the range of 300 to 3400 Hz, other than that due to an applied 0 dBm0 sine
wave signal with frequency f in the same frequency range, is less than –46 dBm0. With f swept between 0 to 300 Hz and 3.4 to
12 kHz, any generated output signals other than f are less than –28 dBm0. This specification is valid for either transmission path.
16
Zarlink Semiconductor Inc.
Le79228
Data Sheet
Gain Linearity
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 6 (A-law) and Figure 7 (µ-law) for either
transmission path when the input is a sine wave signal of 1014 Hz.
Figure 6. A-law Gain Linearity with Tone Input (Both Paths)
1.5
0.55
0.25
Acceptable Region
0
Gain (dB)
-0.25
-55 -50
-40
-10
0
Input
Level
+3 (dBm0)
-0.55
-1.5
Figure 7. µ-law Gain Linearity with Tone Input (Both Paths)
1.4
0.45
0.25
Acceptable Region
Gain (dB)
0
-55 -50
-37
-10
0
Input
Level
+3 (dBm0)
-0.25
-0.45
-1.4
Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 8 for either path when the input signal is a sine wave
signal of frequency 1014 Hz.
17
Zarlink Semiconductor Inc.
Le79228
Figure 8.
Data Sheet
Total Distortion with Tone Input, Both Paths
Acceptable Region
B
A
A
B
C
D
C
D
A-Law
35.5dB
35.5dB
30dB
25dB
µ-Law
35.5dB
35.5dB
31dB
27dB
Signal-to-Total
Distortion (dB)
-45
-40
-30
0
Input Level (dBm0)
Overload Compression
Figure 9 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The
conditions for this figure are:
(1) 1 dB < GX ≤ +12 dB; (2) –12 dB ≤ GR < –1 dB; (3) Digital voice output connected to digital voice input; and (4) measurement
analog to analog.
Figure 9. A/A Overload Compression
9
8
7
Fundamental
Output Power
(dBm0)
6
Acceptable
Region
5
4
3
2.6
2
1
1
7
2
3
4
5
6
Fundamental Input Power (dBm0)
18
Zarlink Semiconductor Inc.
8
9
Le79228
Data Sheet
Discrimination Against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency
components below 4 kHz at the digital output which are caused by the out-of-band signal. These components are at least the
specified dB level below the level of a signal at the same output originating from a 1014 Hz sine wave signal with a level of A
dBm0 also applied to the analog input. The minimum specifications are shown in the following table
Table 2. Minimum Specifications for Out-of-Band Input Signals
Frequency of Out-of-Band Signal
Amplitude of Out-of-Band Signal
Level below A
16.6 Hz < f < 45 Hz
–25 dBm0 < A ≤ 0 dBm0
18 dB
45 Hz < f < 65 Hz
–25 dBm0 < A ≤ 0 dBm0
25 dB
65 Hz < f < 100 Hz
–25 dBm0 < A ≤ 0 dBm0
10 dB
3400 Hz < f < 4600 Hz
–25 dBm0 < A ≤ 0 dBm0
see Figure 10
4600 Hz < f < 100 kHz
–25 dBm0 < A ≤ 0 dBm0
32 dB
Figure 10. Discrimination Against Out-of-Band Signals
0
-10
-20
Level (dB)
-28 dBm
-30
-32 dB, -25 dBm0 < input , 0 dBm0
-40
-50
3.4
4.0
4.6
Frequency (kHz)
Note:
The attenuation of the waveform below amplitude A between 3400 Hz and 4600 Hz is given by the formula:
π ( 4000 – f )
Attenuation (db) = 14 – 14 sin -----------------------------
1200
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the
digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.
Table 3. Limits for Spurious Out-of-Band Signals
Frequency
Level
4.6 kHz to 40 kHz
–32 dBm0
40 kHz to 240 kHz
–46 dBm0
240 kHz to 1 MHz
–36 dBm0
19
Zarlink Semiconductor Inc.
Le79228
Data Sheet
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital
input, the level of the signals at the analog output are below the limits in Figure 11. The amplitude of the spurious out-of-band
signals between 3400 Hz and 4600 Hz is given by the formula:
π ( f – 4000 )
A = – 14 – 14 sin ----------------------------- dBm0
1200
Figure 11. Spurious Out-of-Band Signals
0
-10
-20
Level (dB)
-28 dBm
-30
-32 dB
-40
-50
3.4
4.0
4.6
Frequency (kHz)
SWITCHING CHARACTERISTICS
Figure 12. Switching Characteristics
2.4 V
2.0 V
2.0 V
TEST
POINTS
0.8 V
0.8 V
0.4 V
VCC = 3.3 V +5%, AGND = DGND = 0 V.
20
Zarlink Semiconductor Inc.
Le79228
Data Sheet
Microprocessor Interface
Min and max values are valid for all digital outputs with a 150 pF load. Pictorial definitions for these parameters can be found in
Figure 14, on page 23 and Figure 15, on page 24.
No.
Symbol
1
tDCY
Parameter
Min
Typ
Max
Unit
Note
Data clock period
122
—
—
2
tDCH
Data clock HIGH pulse width
48
—
—
1.
3
tDCL
Data clock LOW pulse width
48
—
—
1.
4
tDCR
Rise time of clock
—
—
25
5
tDCF
Fall time of clock
—
—
25
6
tICSS
Chip select setup time, Input mode
30
—
tDCY–10
7
tICSH
Chip select hold time, Input mode
0
—
tDCY–20
8
tICSL
Chip select pulse width, Input mode
—
8tDCY
—
9
tICSO
Chip select off time, Input mode
2000
—
—
10
tIDS
Input data setup time
25
—
tDCY–10
7.
1., 6.
ns
11
tIDH
Input data hold time
30
—
tDCY–10
13
tOCSS
Chip select setup time, Output mode
30
—
tDCY–10
14
tOCSH
Chip select hold time, Output mode
0
—
tDCH–20
15
tOCSL
Chip select pulse width, Output mode
—
8tDCY
—
16
tOCSO
Chip select off time, output Mode
2000
—
—
1., 6.
17
tODD
Output data turn on delay
—
—
35
5.
18
tODH
Output data hold time
3
—
—
19
tODOF
Output data turn off delay
3
—
35
20
tODC
Output data valid
3
—
35
PCM Interface
Min and max values are valid for TSCA and TSCB with an 150 pF load and are valid for DXA and DXB with an 80 pF load. Pictorial
definitions for these parameters can be found on Figure 16, on page 24 and Figure 17, on page 25.
No.
Symbol
Min.
Typ
Max
22
tPCY
PCM clock period
Parameter
122
—
7812.5
23
tPCH
PCM clock HIGH pulse width
48
—
—
24
tPCL
PCM clock LOW pulse width
48
—
—
25
tPCF
Fall time of clock
—
—
15
26
tPCR
Rise time of clock
—
—
15
27
tFSS
FS setup time
30
—
tPCY–30
28
tFSH
FS hold time
50
—
1250003tPCY--30
29
tTSD
Delay to TSCX valid
5
—
40
30
tTSO
Delay to TSCX off
5
—
40
31
tDXD
PCM data output delay
5
—
40
32
tDXH
PCM data output hold time
5
—
40
33
tDXZ
PCM data output delay to high-Z
10
—
40
34
tDRS
PCM data input setup time
25
—
tPCY–10
35
tDRH
PCM data input hold time
5
—
tPCY–20
36
tFST
PCM or frame sync jitter time
–97
—
97
21
Zarlink Semiconductor Inc.
Unit
Note
2., 9.
ns
3.
4.
4.
Le79228
Data Sheet
Master Clock
Master Clock can be sourced by MCLK or PCLK input by appropriate configuration of DCRI (see Figure 13). For a 2.048 mHz ±
100 PPM, 4.096 mHz ± 100 PPM, or 8.192 ± 100 PPM operation:
No.
Symbol
Parameter
37
tMCY
Period
38
tMCR
39
Min
Typ
Max
122
—
7812
Rise time of clock
—
—
15
tMCF
Fall time of clock
—
—
15
40
tMCH
Master Clock HIGH pulse width
48
—
—
41
tMCL
Master Clock LOW pulse width
48
—
—
Unit
No
2., 8.,
9.
ns
Note:
1.
DCLK may be stopped in the High or Low state indefinitely without loss of information. When CS makes a transition to the High state, the
last byte received will be interpreted by the Microprocessor Interface logic.
2.
The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK frequency.
The actual PCLK rate is dependent on the number of channels allocated within a frame. A PCLK of 1.544 mHz can be used for standard
US transmission systems. The minimum clock frequency is 128 kHz.
3.
TSCX is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock slot register.
4.
TSCX is an open drain driver. tTSO is defined as the delay time the output driver turns off after the PCLK transaction. The actual delay time
is dependent on the load circuitry. The maximum load capacitance on TSCX is 150 pF and the minimum pull-up resistance is 360 Ω.
5.
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
6.
The Le79228 Quad ISLAC device requires 2.0 µs between MPI operations. If the MPI is being accessed while the MCLK (or PCLK if
combined with MCLK) input is not active, a Chip Select Off time of 20 µs is required when accessing coefficient RAM. Immediately after
2µs ⋅ 8.192 MHz
- , where f
reset, t ICSO = ------------------------------------------PCLK is the applied PCLK frequency. Once DCR1 is programmed for the applied PCLK and
f
PCLK
MCLK, tICSO is per table specification.
7.
If chip select is held low for 16 or more DCLK cycles, the part will reset.
8.
Master Clock’s frequency can range from 512 kHz to 8.192 MHz and can be set with: Write/Read Device Configuration Register 1, and if
necessary Write/Read Master Clock Correction Register.
9.
If PCLK is greater or equal to 512 kHz, the preferred configuration is Master Clock derived from PCLK. If a separate MCLK is used, it must
be synchronous to PCLK. If PCLK is less than 512 kHz, a separate MCLK (synchronous with PCLK) with f0 greater or equal to 512 kHz
must be used.
22
Zarlink Semiconductor Inc.
Le79228
Data Sheet
WAVEFORMS
Figure 13.
Master Clock Timing
37
41
VIH
VIL
40
38
39
Figure 14.
Microprocessor Interface (Input Mode)
1
2
5
V IH
V IH
DCLK
V IL
V IL
3
7
9
4
CS
6
8
10
DIO
Data
Valid
11
Data
Valid
Data
Valid
23
Zarlink Semiconductor Inc.
Le79228
Data Sheet
Figure 15. Microprocessor Interface (Output Mode)
VIH
DCLK
VIL
13
14
16
15
CS
20
18
17
DIO
19
VOH Data
VOL Valid
Three-State
Data
Valid
Data
Valid
Three-State
Figure 16. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge)
Time Slot Zero, Clock Slot Zero
27
22
26
25
VIH
PCLK
VIL
23
24
28
FS
30
29
TSCA
See Note 4
31
32
33
VOH
DXA
First
Bit
VOL
35
34
VIH
DRA
First
Bit
Second
Bit
VIL
24
Zarlink Semiconductor Inc.
Le79228
Data Sheet
Figure 17. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero, Clock Slot Zero
27
22
26
25
VIH
PCLK
VIL
23
24
FS
28
30
29
TSCA
See Note 4
31
32
33
VOH
DXA
First
Bit
VOL
35
34
VIH
First
Bit
DRA
Second
Bit
VIL
GCI Timing Specifications
For a 2.048 mHz ± 100 PPM, 4.096 mHz ± 100 PPM, or 8.192 ± 100 PPM operation:
Symbol
Signal
tR, tF
DCL
Parameter
Min
Typ
Max
—
—
60
FDCL = 4096 kHz
478
239
—
498
249
Pulse width
90
—
—
Rise/fall time
Period, FDCL = 2048 kHz
tDCL
DCL
tWH, tWL
DCL
tR, tF
FS
Rise/fall time
—
—
60
tSF
FS
Setup time
70
—
tDCL–50
tHF
FS
Hold time
50
—
—
tWFH
FS
High pulse width
130
—
—
tDDC
DU
Delay from DCL edge
—
—
100
tDDF
DU
Delay from FS edge
—
—
150
tSD
DD
Data setup
20
—
—
tHD
DD
Data hold
50
—
—
25
Zarlink Semiconductor Inc.
Unit
ns
Le79228
Data Sheet
GCI Waveforms
DCL
FS
BIT 7
DD,
DU
BIT 6
DETAIL A
tr
tf
DCL**
tWH
tDCL
tWL
FS
tSF
tHF
tWFH
tDDF
DU
tDDC
tSD
tHD
DD
** Timing diagram valid for
F DCL = 2048 or 4096 KHz
ISLIC DEVICE TIMING SPECIFICATIONS
(See Figure 18.)
Symbol
Signal
Parameter
Min
Typ
Max
trSLD
LD
Rise time
2
tfSLD
LD
Fall time
2
tSLDPW
LD
LD minimum pulse width
tSDXSU
P1,P2,P3
P1–3 data Setup time
4.5
tSDXHD
P1,P2,P3
P1–3 data hold time
4.5
26
Zarlink Semiconductor Inc.
3
Unit
µs
Le79228
Figure 18.
Data Sheet
ISLIC Device Bus Timing Waveform
187.5 µs
LD
P1,P2,P3
S
R
S
R
S
Write State Register
VCC
LD
R
VREF
Lock Registers
0V
Write Relay Register
Previous
State Data
P1,P2,P3 Relay Data
Relay Data
New State
Data
DETAIL A
VREF
LD
Write State Register
trSLD
tfSLD
VREF
Write Relay Register
tSLDPW
tSDXHD
tSDXSU
P1,P2,P3
27
Zarlink Semiconductor Inc.
Le79228
Data Sheet
APPLICATION CIRCUITS
Figure 19. Internal Ringing Line Schematic
+3.3 V
CVCC
+3.3 V
VCC
RSAi
RRXi
SA
RSN
VOUTi
RFAi **
CVCCD
RHLai
AD
A
VCCD
See VHL Networks
for network selection
CADi
VHLi
RHLdi
RHLci
2
1
BATH
6
7
7
U3i**
4
CHLdi
2
6
1
U4i**
3
VREF
BATP
RVCCA
4
3
VCCA
RTi
CVCCA
RTESTi *
VINi
VTX
CVTXi
CSSi *
RFBi **
DGND
VSAB
VSABi
VLB
VLBi
IMT
VIMTi
GS1i
AGND
BD
B
CBDi
RSBi
SB
U1
Le79252
RMT1i
VREF
U2
Le79Q2284
RMT2i *
VBF
ILG
CVBFi
VILGi
BACK
PLANE
GS2i
RLG1i
VREF
VBP
BATP
RLG2i *
CVBP
DVBH
VBH
BATH
VREF
VREF
CVRNi
CVBH
VRN
RVBH *
BATL
VBLi
CVBL
VREF
LD
LDi
RSPB
AGND
P1
RPMGi
PMG
BATL
P1
P2
P2
P3
P3
RSLB
SHB
RREF
NOTE:
Connections are shown for one channel.
BGND
XSBi
** Consult Legerity for an optimized protection recommendation.
28
Zarlink Semiconductor Inc.
VBH
RSHB
RREFSi
* Optional components.
BATL
SLB
IREF
RREFS
TLD
BATP
SPB
XSC
Le79228
Data Sheet
Figure 20. VHL networks for POTS and IVD Applications with and without Metering
POTS with Metering
POTS no Metering
RHLa
40.2K
RHLa
40.2K
CHLb
3.3nF
RHLc
2.87K
SLIC
RHLb
4.32K
RHLd
2.87K
VREF
VREF
VREF
VREF
IVD no Metering
IVD with metering
RHLa
27.4K
RHLc
2.37K
SLIC
VREF
RHLa
100K
RHLb
3.57K
RHLd
2.37K
RHLe
1.1K
SLAC
RHLc
2.61K
SLIC
VHLi
RSN
CHLd
820nF
SLAC
VHLi
CHLd
820nF
CHLd
820nF
CHLb
4.7nF
RHLd
2.87K
RSN
VHLi
RSN
RHLc
2.87K
SLIC
SLAC
CHLe
10nF
RHLd
2.61K
SLAC
VHLi
RSN
CHLd
820nF
VREF
VREF
29
Zarlink Semiconductor Inc.
VREF
Le79228
Data Sheet
LINE CARD PARTS LIST- INTERNAL RINGING
The following list defines the parts and part values required to meet target specification limits for channel i of the line card
(i = 1,2,3,4 or i = 1,2).
Item
Type
Value
Tol.
Rating
Comments
U1i
Le79252 device
Dual ISLIC device
U2
Le79228x
ISLAC device
U3i
TISP8200M
Bourns® Negative Overvoltage
Protector
U4i
TISP8201M
Bourns® Positive Overvoltage
Protector
DVBH
Diode
100 mA
100 V
Required if VoiceEdge Control
Processor (VCP) is not used and
RFAi, RFBi are PTC components
and RSAi, RSBi sense resistors are
wired as shown in Figure 3
RVBH
Resistor
1 kΩ
5%
1/16 W
RFAi, RFBi
Resistor
50 Ω
2%
2W
Fusible resistors or PTC
protection resistors
RSAi, RSBi
Resistor
200 kΩ
1%
3/4 W
Sense resistors, pulse
withstanding component
1%
1/16 W
Impedance control resistor
Receive path gain resistor
RTi
Resistor
80.6 kΩ
RRXi
Resistor
90.9 kΩ
1%
1/16 W
CVTXi
Capacitor
100 nF
10%
50 V
RREF
Resistor
69.8 kΩ
1%
1/16 W
Current reference setting resistor
RSHB, RSLB,
RSPB
Resistor
750 kΩ
1%
1/16 W
Battery sense resistors
RHLai
Resistor
40.2 kΩ
1%
1/16 W
Feed resistor, see VHL networks
for IVD value
RHLbi
Resistor
4.32 kΩ
1%
1/16 W
Metering resistor
RHLci, RHLdi
Resistor
2.87 kΩ
1%
1/16 W
Feed resistors, see VHL networks
for IVD values
CHLbi
Capacitor
3.3 nF
10%
10 V
Metering capacitor - Not Polarized
CHLdi
Capacitor
0.82 µF
10%
10 V
Feed capacitor -Ceramic
CSSi
Capacitor
5%
100 V
Metering capacitor -Ceramic, use
33 pF for 3.2 Vrms max. or 56 pF
for 5.0 Vrms max. metering.
RMT1i
Resistor
3.01 kΩ
1%
1/16 W
Metallic loop current gain resistor
RMT2i
Resistor
75 kΩ
1%
1/16 W
Metallic loop current resistor for
high gain selection
RLG1i
Resistor
6.04 kΩ
1%
1/16 W
Longitudinal loop current gain
resistor
RLG2i
Resistor
150 kΩ
1%
1/16 W
Longitudinal loop current resistor
for high gain selection
RREFSi
Resistor
56.2 kΩ
1%
1/16 W
RPMGi
Resistor
510Ω
5%
1W
33 or
56 pF
Optional Components
Required for metering
Required for metering
Only required for metering > 2.2
Vrms, otherwise omit
Required for testing, tie RMT1i to
VREF if not used
Required for testing, tie RLG1i to
VREF if not used
Value should be adjusted to suit
application
RTESTi
Resistor
2 kΩ
1%
1W
Test load
CADi, CBDi
Capacitor
15 nF
10%
200 V
Ceramic, X7R dielectric
CVBH, CVBL,
CVBP
Capacitor
100 nF
20%
100 V
Ceramic
CVBFi
Capacitor
1 nF
20%
100 V
Ceramic
CVCC
Capacitor
100 nF
20%
10 V
30
Zarlink Semiconductor Inc.
Optional for testing
Le79228
CVCCD
Capacitor
100 nF
20%
10 V
CVCCA
Capacitor
33 µF
20%
6.3 V
RVCCA
Resistor
3.3 Ω
1%
1/16 W
CVRNi
Capacitor
100 nF
20%
10 V
Tantalum
31
Zarlink Semiconductor Inc.
Data Sheet
Le79228
Data Sheet
Figure 21. External Ringing Line Schematic
CVCC
+3.3 V
+3.3 V
VCC
SA
RSAi
RRXi
RSN
VOUTi
CVCCD
VCCD
U3i
Le75282
FAi**
A
RHLai
AD
See VHL Networks
for network selection
ARINGING
VHLi
CADi
RHLdi
RHLci
CHLdi
ATEST
U4i **
Secondary
Protector
RVCCA
VREF
VCCA
BATH
U5i **
Secondary
Protector
RTi
CVCCA
BTEST
VTX
BRINGING
VSAB
CSSi*
VINi
DGND
CVTXi
VSABi
AGND
FBi**
B
BD
P1' P2' P3' LDi
CBDi
VLB
VLBi
IMT
VIMTi
GS1i
RSBi
SB
RMT1i
U1i
Le79232
P3 P2 P1 LDi
VBF
VREF
RMT2i*
ILG
U2
Le79Q2284
VILGi
CVBFi
BACK
PLANE
GS2i
RLG1i
VREF
RLG2i*
BATH
BATL
VREF
VREF
VBH
CVRNi
CVBH
VRN
VBL
LD
CVBL
P1
RPMGi
PMG
P2
P3
VREF
LDi
P1
P2
P3
LDi
P1
SPB
SLB
BATL
RSLB
P2
P3
x
SHB
BATH
RSHB
CTESTB*
AGND
TLD
CTESTA*
R1
RGFDi
KRi
(optional)
IREF
TLDEN
RREF
RREFS
RREFSi
BGND
XSBi
+3.3 V
or 5 V
XSC
RSRBi
Ringing Bus
RTEST*
Test Bus
RSRC
* Optional components.
** Consult Legerity for an optimized protection recommendation.
32
Zarlink Semiconductor Inc.
NOTE: Connections are shown for one channel.
Le79228
Data Sheet
LINE CARD PARTS LIST - EXTERNAL RINGING
The following list defines the parts and part values required to meet target specification limits for channel i of the line card
(i = 1,2,3,4 or i = 1,2).
Item
Type
Value
Tol.
Rating
Comments
U1i
Le79232 device
Dual ISLIC device
U2
Le79228x
ISLAC device
U3i
Le75282
LCAS device
U4i
TISP4125H3
U5i
TISP4A250H3
FAi, FBi
B1250T
1.25 A
RSAi, RSBi
Resistor
200 kΩ
RTi
Resistor
RRXi
Resistor
CVTXi
Bourns® Overvoltage Protector or
equivalent
±125 V
Bourns® Asymmetrical Overvoltage
Protector or equivalent
+125 V,
-250 V
600 V
Bourns® Fuse
1%
1/2 W
Sense resistors, pulse withstanding
component
80.6 kΩ
1%
1/16 W
Impedance control resistor
90.9 kΩ
1%
1/16 W
Receive path gain resistor
Capacitor
100 nF
10%
50 V
RREF
Resistor
69.8 kΩ
1%
1/16 W
Current reference setting resistor
RSHB, RSLB
Resistor
750 kΩ
1%
1/16 W
Battery sense resistors
RHLai
Resistor
40.2 kΩ
1%
1/16 W
Feed resistor, see VHL networks for IVD
value
RHLbi
Resistor
4.32 kΩ
1%
1/16 W
Metering resistor
RHLci, RHLdi
Resistor
2.87 kΩ
1%
1/16W
Feed resistors, see VHL networks for IVD
values
CHLbi
Capacitor
3.3 nF
10%
10 V
Metering capacitor - Not Polarized
CHLdi
Capacitor
0.82 µF
10%
10 V
Feed capacitor -Ceramic
5%
100 V
Metering capacitor -Ceramic, use 33 pF
for 3.2 Vrms max. or 56 pF for 5.0 Vrms
max. metering.
33 or
Optional Components
Required for metering
Required for metering
Only required for metering >
2.2 Vrms, otherwise omit
CSSi
Capacitor
RMT1i
Resistor
3.01 kΩ
1%
1/16 W
Metallic loop current gain resistor
RMT2i
Resistor
75 kΩ
1%
1/16 W
Metallic loop current resistor for high gain
selection
RLG1i
Resistor
6.04 kΩ
1%
1/16 W
Longitudinal loop current gain resistor
RLG2i
Resistor
150 kΩ
1%
1/16 W
Longitudinal loop current resistor for high
gain selection
RREFSi
Resistor
56.2 kΩ
1%
1/16 W
RPMGi
Resistor
510Ω
5%
1W
Value should be adjusted to suit
application
RTEST(i)
Resistor
2 kΩ
1%
1W
Test load, power rating assumes
intermittent operation per test algorithms
Optional for testing
CTESTA,
CTESTB
Capacitor
1 nF
20%
100 V
Test bus capacitors
Refer to Le75282 data sheet
for applicability
CADi, CBDi
Capacitor
15 nF
10%
200 V
Ceramic, X7R dielectric
CVBH, CVBL
Capacitor
100 nF
20%
100 V
Ceramic
CVBFi
Capacitor
1 nF
20%
100 V
Ceramic
CVCC
Capacitor
100 nF
20%
10 V
CVCCD
Capacitor
100 nF
20%
10 V
CVCCA
Capacitor
33 µF
20%
6.3 V
RVCCA
Resistor
3.3 Ω
1%
1/16 W
CVRNi
Capacitor
100 nF
20%
10 V
56 pF
Tantalum
33
Zarlink Semiconductor Inc.
Required for testing, tie
RMT1i to VREF if not used
Required for testing, tie
RLG1i to VREF if not used
Le79228
RGFDi
Resistor
511 Ω
2%
2W
Ringing feed resistor, wirewound or
surge rated
RSRBi, RSRC
Resistor
750 kΩ
1%
1/4 W
Sense resistor, if EMR used for ringing,
then use a pulse withstanding
component
34
Zarlink Semiconductor Inc.
Data Sheet
Le79228
Data Sheet
PHYSICAL DIMENSIONS
64-Pin Thin Quad Flat Pack (TQFP)
Min
Nom
Max
Symbol
A
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
12 BSC
D
10 BSC
D1
E
12 BSC
E1
10 BSC
L
0.45
0.60
0.75
N
64
e
0.50 BSC
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
ccc
0.08
ddd
0.08
aaa
0.20
JEDEC #: MS-026 (C) ACD
Notes:
1. All dimensions and toleerances conform to ANSI Y14.5-1982.
2. Datum plane -H- is located at the mold parting line and is coincident
with the bottom of the lead where the lead exits the plastic body.
3. Dimensions “D1” and “E1” do not include mold protrusion. Allowable
protrusion is 0.254mm per side. Dimensions “D1” and “E1” include
mold mismatch and are determined at Datum plane -H- .
4. Dimension “B” does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08mm total in excess of the “b” dimension at
maximum material condition. Dambar can not be located on the lower
radius or the foot.
5. Controlling dimensions: Millimeter.
6. Dimensions “D” and “E” are measured from both innermost and
outermost points.
7. Deviation from lead-tip true position shall be within ±0.076mm for pitch
!PPDQGZLWKLQIRUSLWFKPP
8. Lead coplanarity shall be within: (Refer to 06-500)
1- 0.10mm for devices with lead pitch of 0.65-0.80mm.
2- 0.076mm for devices with lead pitch of 0.50mm.
Coplanarity is measured per specification 06-500.
9. Half span (center of package to lead tip) shall be
15.30 ± 0.165mm {.602”±.0065”}.
10. “N” is the total number of terminals.
11. The top of package is smaller than the bottom of the package by 0.15mm.
12. This outline conforms to Jedec publication 95 registration MS-026
13. The 160 lead is a compliant depopulation of the 176 lead MS-026
variation BGA.
64-Pin TQFP
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
35
Zarlink Semiconductor Inc.
80LD 12x12x1.4 mm LQFP
Package Outline Drawing
TOLERANCES OF FORM AND POSITION
SQUARE DOTTED LINE IS E-PAD OUTLINE.
SIZE IS DEPENDENT ON DIE ATTACH PAD.
NOTE (OPTION):
Dambar cannot be located on the lower radius or the foot.
Minimum space between protrusion and an adjacent lead is
0.07 mm for 0.4 mm and 0.5 mm pitch packages.
2. Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall not cause the lead width to
exceed the maximum b dimension by more than 0.08 mm.
1. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25 mm per side. D1 and E1 are
maximum plastic body size dimensions, including mold mismatch.
NOTES:
INCH
MIN. NOM. MAX. MIN. NOM. MAX.
MILLIMETER
CONTROL DIMENSIONS ARE IN MILLIMETERS
SYMBOL
Data Sheet
Zarlink Semiconductor Inc.
36
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used
in manufacturing.
80-Pin Low-Profile Quad Flat Pack (LQFP)
Le79228
Le79228
Data Sheet
REVISION HISTORY
Revision A1 to B1
•
•
•
•
•
•
Removed all references to 68-pin PLCC package.
Added GS1x and GS2x pins to Le792283.
Changed min/typ/max values in "Gain from VSAB to VHL" under DC Specifications from positive to negative.
Combined gain/offset errors; made other minor formatting corrections.
Updated Application Circuits and Parts Lists.
Updated Related Literature.
Revision B1 to C1
•
•
Changed Le79Q2283VC to Le79Q2284VC.
Minor text and drawing changes.
Revision C1 to D1
•
•
•
•
•
•
•
Changed OPN to reflect green package.
Added Package Assembly, on page 11.
In Pin Descriptions, on page 9, Pin Name I/O, removed TTL-compatible;Pin Name SHB, SLB, SPB, enhanced Description.
In Electrical Ranges, on page 11, changed VCCA acceptable operating tolerance from -5% to -10%.
In DC Specifications, 2, Input High Voltage Min tightened from 2.36 V to 2.46 V; 14, 21, 22, 26 Conditions added.
In Transmission Specifications, 1, Conditions modified and Min and Max specifications tightened from ±0.34 dB to ±0.25
dB; 9, Min and Max requirements removed.
GCI Timing Specifications, on page 25, tSD Min time changed from tWH+20 ns to 20 ns.
•
Updated Application drawings and BOMs.
Revision D1 to E1
•
•
•
•
•
•
•
•
Added "Packing" column and Note 2 to Ordering Information, on page 1; removed non-green package options
Document updated from Preliminary Data Sheet to Final Data Sheet.
Device Internal Block Diagram revised to 80-pin TQFP.
Modified Pin Descriptions, on page 9 to identify pins that are package dependent.
In DC Specifications, on page 12, No 1, added Digital input capacitance specification.
In Microprocessor Interface, on page 21, No. 4,5 rise/fall times, changed max from 15 to 25 ns, No. 17, 19, 20 output
parameters, changed max from 50 to 35 ns.
Updated Application Circuits, VHL Networks, and Line Card Parts List.
Minor text and table changes.
Revision E1 to F1
•
•
•
•
Changed Le792284 OPN from Le79Q2284FVC to Le79Q2284MVC to reflect package change from TQFP to LQFP.
Minor edit to schematics.
Line Card Parts List - External Ringing, changed U4i from 95 V TISP4095H3 protector to 250 V TISP4250H3 protector.
Physical Dimensions, replaced 80-pin TQFP with 80-pin LQFP.
Revision F1 to G1
•
•
•
•
•
Page 21, PCM Interface, output loading added. DXA and DXB loading changed from 150 pF to 80 pF.
Updated Figure 19, on page 28.
Updated Figure 21, on page 32.
Updated Line card Parts List- INTERNAL RINGING, on page 30.
Updated Line card Parts List - EXTERNAL RINGING, on page 33.
Revision G1 to G2
•
•
Enhanced format of package drawings in Physical Dimensions, on page 35
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
37
Zarlink Semiconductor Inc.
™
For more information about all Zarlink products
visit our Web Site at:
www.zarlink.com
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result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under
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Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
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