LE9622RQCT

Le9622 Subscriber Line Interface Circuit miSLICTMSeries Preliminary Data Sheet Features - Low Cost, 2-Layer PCB Reference Designs - Supports Multi-Channel Enterprise Applications Programmable Interface Voltage to support 1.8V, 2.5V and 3.3V SoC Processors Low Cost, Energy Efficient Dual Battery Switching Regulator Architectures Consistent with Code of Conduct on Energy Consumption of Broadband Equipment - Patented Shared Buck-Boost Automatic Battery Switch (BBABS) - 60Vrms ringing with 5 REN load Multi-Line Inverting Boost Automatic Battery Switch (ABS) - • VeriVoice Professional Test Suite Software The versatile Le9622 miSLIC is controlled via a PCM/SPI interface which makes the device ideal for both 4 or 8 channel Enterprise and 2 channel Broadband Gateway applications. Two power supply topologies are supported: Multi-Line Inverting Boost for up to 70 Vrms ringing into 5 REN and a patented Shared Buck Boost Automatic Battery Switch for up to 60 Vrms ringing into 5 REN. Manufacturing self test and subscriber line diagnostics are available features. The Le9622 features wideband clarity and complete BORSCHT functionality. All AC, DC and power parameters are programmable making the Le9622 device suitable for any short loop application requiring SLIC functionality. Comprehensive subscriber loop testing, including Telcordia GR-909-CORE / TIA-1063 Facilitates factory testing of assembled boards Worldwide Programmability • Narrowband or Wideband operation N • Applications Multi-Channel Enterprise and Small Office O • • Tape & Reel Tray The miSLICTM Series Line Circuits together with a VoIP processor or SoC, provides an economical turn-key solution for derived voice applications. The Le9622 miSLIC 2 FXS device is a cost optimized FXS solution. VeriVoice Manufacturing Test Package - VVMT - Packing 53-pin QFN 53-pin QFN Description FI D VoicePath SDK and VP-API-II Software available to implement FXS functions - 120V SLIC 120V SLIC The Green package meets RoHS 2 Directive 2011/65/EC of the European Council to minimize the environmental impact of electrical equipment. 70Vrms ringing with 5 REN load • • Device OPN Device Type Package Le9622RQCT Le9622RQC - - L 53-pin 7x7mm 0.4mm Pitch QFN Package • Ordering Information - PCM/SPI Interface September 2017 ET IA • Cost Optimized Dual Channel FXS Solution Version 3 N • Document ID# 157378 DSL Residential Gateways and Integrated Access Devices (IADs) • Cable eMTAs • PON Single Family Units (SFUs) VBL1 VBH TIPD1 RINGD1 TAC1 RAC1 RTV1 Voice Signal  Processing LFC1 RSN1 IHL1 Signaling  Control TDC1 RDC1 Supervision  Processing VS1 VS2 Voltage Sense IHL2 RSN2 RTV2 RAC2 TAC2 C • Fiber to the Premise/Home/Building (FTTx) • Fixed Wireless (LTE Gateways) FS DXA RINGD2 TIPD2 DRA PCM Interface and Time Slot  Assigner (PCM) 4 Input / Output Serial Peripheral Interface (SPI) Signal  Generation RDC2 TDC2 PCLK PLL High Voltage  Line Driver Supervision  Processing Signaling  Control Switching  Regulator Controllers  Voice Signal  Processing High Voltage  Line Driver VBL2 VBH Analog  Reference GND VREF IREF Power  Supplies I/O11,2 - I/O21,2 DCLK DIN DOUT CS INT RST SWCMPY SWVSY SWISY SWOUTY SWCMPZ SWVSZ SWISZ SWOUTZ AVDD DVDD VDDHPI VDDSW VDD1V2 Figure 1 - Le9622 Device Block Diagram Microsemi Corporation Confidential and Proprietary 1 Le9622 Preliminary Data Sheet Table of Contents C O N FI D N ET IA L 1.0 Solution Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Le9622 Automatic Battery Switch (ABS) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 Le9622 Device Overview and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 miSLICTM Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Host Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 PCM Interface and Time Slot Assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Input / Output Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Voltage Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Voice Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.1 Impedance Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 Frequency Response Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.3 Transhybrid Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.4 Gain Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.5 Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.6 Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.7 Speech Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.8 Wideband Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.1 Multi-Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.2 Frequency and Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.3 Triangular and Trapezoidal Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 Low Power DC Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Normal DC Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 Test Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.1 Balanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.2 Adaptive Ringing Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.3 Switch Hook Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.4 Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 Subscriber Line Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.1 VeriVoice Professional Test Suite Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 Manufacturing Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Metering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 Switching Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13.1 Buck Boost Automatic Battery Switch (BBABS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13.2 Multi-Line Inverting Boost Automatic Battery Switch (ABS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14 Charge Pump Regulator and MOSFET Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 Thermal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 DC Feed and Signaling - All States Except Low Power Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 DC Feed and Signaling - Low Power Idle Mode State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 Metering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet C O N FI D N ET IA L 5.7 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.8 Switching Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 Charge Pump Controller and MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.10 Voice ADC Signal Sense Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.11 Supervision ADC Signal Sense Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.12 Transmission Characteristics - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.13 Attenuation Distortion - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.14 Discrimination Against Out-of-Band Input Signals - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . 39 5.15 Discrimination Against 12kHz and 16kHz Metering Signals - Narrowband Codec Mode . . . . . . . . . . . . 40 5.16 Spurious Out-of-Band Signals at the Analog Output - Narrowband Codec Mode. . . . . . . . . . . . . . . . . . 40 5.17 Overload Compression - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.18 Gain Linearity - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.19 Total Distortion Including Quantizing Distortion - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . . . 43 5.20 Group Delay Distortion - Narrowband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.21 Transmission Characteristics - Wideband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.22 Attenuation Distortion - Wideband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.23 Group Delay Distortion - Wideband Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.0 Switching Characteristics and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 PCM and SPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 Switcher Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.0 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.0 Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.1 Line Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.1.1 Line Interface Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.1.2 Line Interface Circuit Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2 Patented BBABS Switching Regulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.2.1 Patented BBABS Switching Regulator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.2.2 BBABS Switching Regulator Circuit Bill of Materials (for VBATH 95V Maximum) . . . . . . . . . . . . . . 60 8.3 Multi-Line Inverting Boost Automatic Battery Switch (ABS) Switching Regulator Circuit . . . . . . . . . . . . . 61 8.3.1 Multi Line ABS - VBATL Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.3.2 Multi Line ABS - VBATL Bill of Materials (for VBATL 50V Maximum) . . . . . . . . . . . . . . . . . . . . . . . 62 8.3.3 Multi Line ABS - VBATH Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3.4 Multi Line ABS - VBATH Bill of Materials (for VBATH 90V Maximum)1 . . . . . . . . . . . . . . . . . . . . . 64 9.0 Programming the Le9622 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2 VoicePath SDK Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.2 Customer Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.3 VoicePath API-II. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.4 Hardware Abstraction Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.5 System Services Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.3 System Configuration Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.5 Line State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.5.1 VP_LINE_DISCONNECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.5.2 VP_LINE_STANDBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.5.3 VP_LINE_OHT, VP_LINE_OHT_POLREV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.5.4 VP_LINE_ACTIVE, VP_LINE_ACTIVE_POLREV, VP_LINE_TALK, VP_LINE_TALK_POLREV. . 68 9.5.5 VP_LINE_TIP_OPEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.5.6 VP_LINE_RING_OPEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.5.7 VP_LINE_RINGING, VP_LINE_RINGING_POLREV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.5.8 VP_LINE_HOWLER, VP_LINE_HOWLER_POLREV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet C O N FI D N ET IA L 9.6 VpShutdownDevice(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.7 Line Status Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.8 Input / Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.9 VoicePath API-II Software and QuickStarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.10 DTMF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.0 VP-API-II Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.1 Profile Wizard Project Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2 Profile Wizard Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3 Device Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4 AC FXS Profiles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.5 DC Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.6 Ringing Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.7 Tone Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.8 Tone Cadence Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.9 Ringing Cadence Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.10 Caller ID Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.11 Metering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.0 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.0 Related Collateral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.2 Development Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3 Downloads, Firmware and Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.4 Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.0 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.1 Revision 2 to Revision 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet List of Figures C O N FI D N ET IA L Figure 1 - Le9622 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Le9622 Dual-Channel VoicePort Solution Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3 - Le9622 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - PCM Highway Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5 - Transmit PCM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - Receive PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7 - PCM Data Flow Transmit and Receive Data (Transmit Data on Negative PCLK Edge) . . . . . . . . . . . . 14 Figure 8 - 4-Wire SPI Connection to Host Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 - SPI Mode 3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - MPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11 - Voice Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12 - Multi-Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13 - Frequency Tone Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14 - Trapezoidal Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15 - Normal DC Feed I / V Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16 - Balanced Ringing with Fixed Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17 - Metering Pulse Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18 - Transmit (A to D) Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 19 - Receive (D to A) Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 20 - Discrimination Against Out of Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 21 - Spurious Out of Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 22 - Analog to Analog Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 23 - A-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 24 - µ-law Gain Linearity with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 25 - Total Distortion with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 26 - Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 27 - Transmit (A to D) Path Attenuation vs. Frequency- (with High Pass Filter Enabled). . . . . . . . . . . . . . 46 Figure 28 - Receive (D to A) Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 29 - Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 30 - SPI Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 31 - SPI Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 32 - PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 33 - PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 34 - PCM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 35 - Switcher Output Waveform SWOUTY, SWOUTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 36 - Le9622 Device Pinout (QFN-53) - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 37 - Le9622 Line Interface Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 38 - VP-API-II Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 39 - Profile Wizard - Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 40 - Profile Wizard - Device Profile Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 41 - Profile Wizard - DC Profile Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 42 - Profile Wizard - Ringing Profile Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 43 - Profile Wizard - Tone Profile Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 44 - Profile Wizard - Tone Cadence Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 45 - Profile Wizard - Ringing Cadence Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 46 - Profile Wizard - Type 1 Caller ID Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 47 - Profile Wizard - Metering Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 48 - Le9622 Package Pin Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet C O N FI D N ET IA L Figure 49 - Le9622 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 50 - Recommended Land Pattern (QFN-53) - Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet List of Tables C O N FI D N ET IA L Table 1 - Maximum Number of Transmit or Receive Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 1 - SPI Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2 - VP-API-II Functions for Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3 - VP-API-II Functions for Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4 - VP-API-II Functions Using Signal Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5 - VP-API-II Functions for Howler Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6 - DC Feed and Battery Switch Programmable Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7 - Ring Trip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8 - Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 9 - Out of Band Discrimination, Narrowband Codec Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 10 - VP-API-II Functions for System Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 11 - VP-API-II Functions for System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 12 - VP-API-II Functions for Line State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 13 - VP-API-II Functions for Line Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 14 - VP-API-II Functions for Configuring and Accessing I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 15 - VP-API-II Profile Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 16 - VP-API-II Functions for Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 17 - Supported AC Source Impedances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 18 - VP-API-II Functions Using AC FXS Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 19 - VP-API-II Functions for DC Feed and Hook Detection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 20 - VP-API-II Functions for Ringing and Ring Trip Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 21 - VP-API-II Function Using Tone Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 22 - VP-API-II Function For Tone Cadencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 23 - VP-API-II Functions For Ringing Cadencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 24 - VP-API-II Functions for Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 25 - VP-API-II Functions for Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7 Microsemi Corporation Confidential and Proprietary Le9622 1.0 Preliminary Data Sheet Solution Overview The sixth-generation miSLIC line interface solution consists of a miSLIC device, VoicePath API-II (VP-API-II) Software, and Profiles Data Structures. To support the miSLIC device, Microsemi offers comprehensive software and hardware collateral packages, including 2-layer printed circuit board reference designs. ET IA L The VoicePath API-II (VP-API-II) software initializes the FXS port coefficient data containing application or countryspecific AC and DC parameters, ringing and other signaling characteristics, and configures the switching power supply. VP-API-II resides on the customer’s VoIP processor or SoC and provides high level control over the telephony functions. VP-API-II offers a seamless migration between products utilizing its common software architecture and interfaces with the Microsemi VeriVoice Professional Test Suite Software. A Microsoft® Windows® GUI (Graphical User Interface) application, VoicePath Profile Wizard (VP Profile Wizard), allows the user to select the operating parameters of the FXS channels and to automatically generate the sets of data structures, called Profiles, that are required by the VP-API-II for integration with the VoIP host software. 1.1 Le9622 Automatic Battery Switch (ABS) Devices The Le9622 device implements a dual-channel universal telephone line interface with a PCM and SPI interface, making it the ideal solution for 4 or 8 channel Enterprise and Small Office applications and dual port cable eMTAs, fiber PON SFUs, Integrated Access Devices, DSL Gateways, and other telephony products for worldwide markets. N Two Automatic Battery Switch (ABS) power supply topologies are supported: The lower cost Buck Boost ABS for lower cost and Microsemi's Multi-line Inverting Boost topology. The Le9622 features integrated switching controllers which generate the high voltages needed for efficiently powering and ringing analog telephones. The Le9622 performs all necessary voice telephony functions from driving a high voltage subscriber telephone line to DSP Codec functions. All AC, DC, and signaling parameters are fully programmable via the PCM and SPI interface. The Le9622 supports both Wideband and Narrowband voice. FI D The VoicePath API-II (VP-API-II) software initializes each FXS port coefficient data containing application or country specific AC and DC parameters, ringing and other signaling characteristics, and configures the switcher. VP-API-II resides on the customer’s VoIP processor or SoC and provides high level control over the telephony functions. VP-API-II offers a seamless migration between products utilizing its common software architecture and interfaces with the Microsemi VeriVoice Professional Test Suite Software. Figure 2 shows a high level solution diagram with a Le9622 device, VP-API-II and Profiles. VoIP Processor / SoC Le9622 Device C O N Analog Ref. & PLL FXS FXS Tip & Ring Line Drivers Switching Regulator Controllers Audio Processing Supervision, Control, & Test Control Level Shifting Buffer Serial Peripheral Interface (SPI) PCM Interface & Time Slot Assigner (TSA) SPI + Profiles VoicePath API-II Software (Device, AC, DC, Ringing, Tone, Cadence, CID, Metering) PCM Figure 2 - Le9622 Dual-Channel VoicePort Solution Diagram 8 Microsemi Corporation Confidential and Proprietary Le9622 2.0 Le9622 Device Overview and Block Diagram 2.1 miSLICTM Series Features Preliminary Data Sheet Performs all Battery feed, Ringing, Signaling, Coding, Hybrid and Test (BORSCHT) functions Single chip solution provides high voltage line driving, digital signal processing, and high voltage power generation for two lines - Le9622 is ideal for 4 and 8 line applications • Wideband 150 Hz  6.8 kHz and Narrowband 200 Hz  3.4 kHz Codec modes - Compliant with Cable Labs PacketCable High Definition Voice Specification PKT-SP-HDV-104-120823 • • Exceeds Telcordia® GR-909-CORE transmission requirements Single hardware design meets worldwide requirements through software programming of: - Ringing waveform, frequency and amplitude - DC loop feed characteristics and current limit - Loop supervision detection thresholds - Off-hook debounce circuit - Ground-key and ring trip filters - Two wire AC impedance - Transhybrid balance impedance - Transmit and receive gains and equalization - Digital I/O - A-law/µ-law and linear coding selection - Switching power supply N ET IA L • • Per Channel Wideband or Narrowband Select Supports loop-start and ground-start signaling On-hook transmission Power/service denial mode Smooth polarity reversal Supports wink function Metering generation with envelope shaping – Programmable frequency and duration • • • Internal Test Termination Compatible with inexpensive protection networks Self contained ringing generation and control – Programmable ringing cadencing – Internal battery-backed balanced sinusoidal or trapezoidal – Integrated ring trip filter and software, manual or automatic ring trip mode O N FI D • • • • • • • Flexible tone generation – Call progress tone generation – DTMF tone generation – Universal Caller ID generation (FSK and DTMF signaling) – Howler tone generation with VP-API-II with frequency modulation capability for compliance with BT, NTT, and Austel special Howler tone requirements C • • DTMF detection with VP-API-II 9 Microsemi Corporation Confidential and Proprietary Le9622 Integrated switching regulator controller – Generates battery voltage for each line – Energy efficient in all states – Low idle power per line – Line feed characteristics independent of battery voltage L • Preliminary Data Sheet – Direct FET Driver VeriVoice Professional Test Suite Software - Monitors two-wire interface voltages and currents for subscriber line diagnostics - Integrated self-test features • • • • • VeriVoice Manufacturing Test Package Supported by VoicePath SDK and VP-API-II Small physical size in 7x7 mm, 0.4mm pitch 53-pin QFN -40°C to +85°C operation Programmable PCM and SPI interface voltage - Supports communication with host processors at 1.8 V, 2.5 V or 3.3 V - Allows for optimized interface to 4 or 8 channel application - Supports SPI Modes 0 and 3 Low BOM cost: Compatible with 2-layer PCB designs Small value/size/cost switcher output and SLIC capacitors No external diodes for protecting SLIC against negative surges - Low-Power Idle Mode (LPIM) Voltage based off-hook detection • N - FI D • Monitors and drives Tip & Ring independently Built-in voice path test modes Simultaneous ground key / DC fault detection Over current monitoring and blanking Hook and ground key detection with hysteresis and calibrated thresholds On-chip timer functions Comprehensive device calibration capabilities - Short calibration time - No need to generate voltages to the Tip/Ring interface - Programmable loop current dependent overhead C O N • • • • • • • ET IA • 10 Microsemi Corporation Confidential and Proprietary Le9622 2.2 Preliminary Data Sheet Device Block Diagram Figure 3 shows the major functional blocks of the Le9622 device. RINGD 1 TAC 1 RAC 1 RTV1 Voice Signal  Processing LFC1 RSN 1 IHL 1 Signaling  Control TDC 1 RDC 1 Supervision  Processing VS 1 VS2 FS DXA RTV2 RAC 2 TAC 2 RINGD 2 TIPD 2 4 Input / Output Voltage Sense Serial Peripheral Interface (SPI) Signaling  Control N Supervision  Processing FI D IHL2 RSN 2 DRA PCM Interface and Time Slot  Assigner (PCM) Signal  Generation RDC 2 TDC2 PCLK PLL High Voltage  Line Driver ET IA TIPD 1 VBH L VBL 1 Switching  Regulator Controllers  Voice Signal  Processing High Voltage  Line Driver VBH GND VREF IREF Power  Supplies VDDSW VDD1V2 Figure 3 - Le9622 Device Block Diagram C O N VBL 2 Analog  Reference 11 Microsemi Corporation Confidential and Proprietary I/O1 1,2 - I/O21,2 DCLK DIN DOUT CS INT RST SWCMPY SWVSY SWISY SWOUTY SWCMPZ SWVSZ SWISZ SWOUTZ AVDD DVDD VDDHPI Le9622 3.0 3.1 Preliminary Data Sheet Functional Description Host Port Interface L The Le9622 device features a flexible host port interface which is hardware selectable for communicating with VoIP processors and SoCs using standard PCM and SPI interfaces. ET IA The host port interface voltage level (VDDHPI) can be set for 1.8 V, 2.5 V, or 3.3 V for maximum system level compatibility. The host port interface supports the standard telecommunications clock rates of 1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz and 8.192 MHz with a Frame Sync (FS) of 8 kHz. 3.1.1 PCM Interface and Time Slot Assigner The PCM Interface and Time Slot Assigner (PCM block) is a synchronized serial mode of communication between the system and the Le9622 device. Voice data is transmitted/received on a serial PCM highway. This highway uses Frame Sync (FS) and PCLK as reference. N Data is transmitted out of the DXA pin and received on the DRA pin. The Le9622 device transmits/receives single 8-bit time slot (A-law/µ-law) compressed voice data or two contiguous time slot 16-bit two’s complement linear voice data. The PCLK is a data clock supplied to the device that determines the rate at which the data is shifted in/out of the PCM ports. The FS pulse identifies the beginning of a transmit/receive frame and all time slots are referenced to it. For the Le9622 device, the frequency of the FS signal is 8 kHz. In Wideband mode, two evenly spaced sets of time slots are exchanged in each frame. The PCLK frequency can be a number of fixed frequencies as defined by the VP-API-II. Please refer to Figure 40, “Profile Wizard - Device Profile Configuration” on page 73 for an example setting of the Transmit and Receive Clock Slots, PCM Transmit Edge, and PCLK Frequency. FI D The VP-API-II allows the time slots to be offset to eliminate any clock skew in the system. The Transmit Clock Slot and Receive Clock Slot fields are each three bits wide to offset the time slot assignment by 0 to 7 PCLK periods. The Transmit and Receive Clock Slot is a global command that is applied at the device level. Thus, for each channel, two time slots must be assigned: one for transmitting voice data and the other for receiving voice data. Figure 4 shows the PCM highway time slot structure. 125 us FS N PCLK RTS0 RTS1 RTS2 RTS3 RTS4 RTS5 RTS6 RTS7 DXA TTS0 TTS1 TTS2 TTS3 TTS4 TTS5 TTS6 TTS7 4 6 C O DRA 0 B its 1 2 3 5 7 Figure 4 - PCM Highway Structure 12 Microsemi Corporation Confidential and Proprietary 3 1 ,6 3 ,e tc 3 1 ,63 ,e tc RTS0 TTS0 Le9622 3.1.1.1 Preliminary Data Sheet Transmit PCM Interface From Receive  Voice Signal  Processor  L The Transmit PCM interface receives an 8-bit compressed code (A-law/µ-law) or a 16-bit two’s complement linear code from the voice signal processor (compressor). The transmit PCM interface logic (shown in Figure 5) controls the transmission of the data onto the PCM highway through the output port selection circuitry and the time and clock slot control block. The data can be transmitted on either edge of the PCLK, as selected in the Device Profile. DXA ET IA Output Register FS Time and Clock Slot  Control Time and Clock Slot  Register From MPI PCLK Figure 5 - Transmit PCM Interface N The VP-API-II allows the time slot of the selected channel to be programmed. The Transmit Time Slot Register is 7 bits wide and allows up to 128 8-bit time slots in each frame, depending on the value of the PCLK frequency, the encoding scheme, and whether Narrowband or Wideband modes are selected. Refer to Table 1 below for the maximum number of available channels. Please note that linear mode requires two back to back time slots to transmit one voice channel. The data is transmitted in bytes with the most significant bit first. Wideband mode requires twice the number of transmit time slots as Narrowband linear mode. Encoding 1.024 MHz FI D Audio Mode Narrowband (8 kHz sampling) 2.048 MHz 4.096 MHz 8.192 MHz 8-bit compressed A-law/µ-law 16 32 64 128 16-bit linear 8 16 32 64 16-bit linear 4 8 16 32 Wideband (16 kHz sampling) Table 1 - Maximum Number of Transmit or Receive Channels 3.1.1.2 Receive PCM Interface C O N The receive PCM interface logic (see Figure 6) controls the reception of data bytes from the PCM highway. 8-bit compressed (A-law/µ-law) or 16-bit two's complement linear data is formatted and passed to the voice signal processor (expander). To Receive  Voice Signal  Processor  From MPI Input Register Time and Clock Slot  Control Time and Clock Slot  Register Figure 6 - Receive PCM Interface 13 Microsemi Corporation Confidential and Proprietary DRA FS PCLK Le9622 Preliminary Data Sheet L The VP-API-II allows the time slot of the selected channel to be programmed. The Receive Time Slot Register is 7 bits wide and allows up to 128 8-bit time slots in each frame. Refer to Table 1 on page 13 for the maximum number of available channels. Please note that linear mode requires two back to back time slots to receive one voice channel. The data is transmitted in bytes with the most significant bit first. Wideband mode requires twice the numbers of receive time slots as Narrowband linear mode. Please refer to “VP-API-II Functions for Speech Coding” on page 20 for more details about setting the Codec mode and transmit and receive time slots. Figure 7 illustrates data flow on the PCM highway with data transmitted on the negative PCLK edge. FS 2 3 4 5 6 PCLK 7 8 9 10 11 12 13 14 15 16 ET IA 1 Tri - State DXA PCM MODE DXA PCM SIGNALING DXA LINEAR MODE P7 P6 P5 P4 P3 P2 P1 P0 P7 P6 P5 P4 P3 P2 P1 P0 S7 S6 S5 S4 S3 S2 S1 S0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Don't care P7 P6 P5 P4 L15 L14 L13 L12 PCM MODE DRA P2 P1 P0 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 FI D LINEAR MODE P3 N DRA Figure 7 - PCM Data Flow Transmit and Receive Data (Transmit Data on Negative PCLK Edge) 3.1.2 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) block communicates with external VoIP processors over a flexible half-duplex synchronous serial interface. This port is always a slave to the host processor’s SPI port which provides clocking, chip select and initiates transactions. 3.1.2.1 SPI Signals N The SPI port physically consists of a serial data input (DIN) serial data output (DOUT), a data clock (DCLK), and a chip select (CS). Type Description DCLK Input Serial Clock CS Input Chip or Slave Select, active low DOUT Output Master Input Slave Output DIN Input Master Output Slave Input C O Signal Name 3.1.2.2 Table 1 - SPI Interface Signals Interrupt Signal An optional interrupt signal (INT) is available to alert the host processor that the device has status information. It is recommended that the INT signal be tied to an interrupt-generating pin on the host processor. If the interrupt signal is not used, the host processor will need to regularly poll the device. 14 Microsemi Corporation Confidential and Proprietary Le9622 3.1.2.3 Preliminary Data Sheet SPI Connection Diagram DCLK SCK SS MISO MOSI INT or GPIO CS Le9622 (SPI Slave) DOUT ET IA Host Processor (SPI Master) L Figure 8 below shows a the standard 4-Wire SPI connection to the host processor. The optional INT signal is also shown here. DIN INT Figure 8 - 4-Wire SPI Connection to Host Processor 3.1.2.4 Chip Select Settings N The Le9622 device also supports 2- and 3-wire variants of the SPI interface in case of limitations on the host’s serial port. Contact Microsemi CMPG Customer Applications for more information. Three chip select settings are supported: FI D 1. Low for each Byte or Word: CS goes inactive between bytes or words. This mode is compatible with the legacy MPI mode. 2. Command Framing: CS goes inactive on some command boundaries. Commands cannot be aborted in this mode. All required bytes are expected even if CS is de-asserted in the middle. 3. CS Hard-Wired Low: This can be used when the Le9622 device is the only slave on the SPI bus, but additional measures are required to acquire synchronization if it is ever lost. Whenever CS goes inactive the bit state machine is reset. Also, if CS has not been active for exactly a multiple of 8 bit times, any byte which was partially received when CS goes inactive is ignored. DCLK Polarity and Phase Settings N 3.1.2.5 O The SPI standards include four modes, defined by the polarity of DCLK and the phase relationship between data and DCLK. The clock polarity (CPOL) is determined by the idle state of DCLK. If the idle state is low, CPOL is 0. If the idle state is high, CPOL is 1. The clock phase (CPHA) is determined by which edge that data is valid. If the data is valid on the first edge of DCLK, CPHA is 0. If the data is valid on the second edge of DCLK, CPHA is 1. The Le9622 device supports SPI Modes 0 (CPOL =0 and CPHA = 0) and 3 (CPOL =1 and CPHA = 1) and contains a logic block to automatically conform to the selected Mode. SPI Modes 1 (CPOL =0 and CPHA = 1) and 2 (CPOL =1 and CPHA = 0) are not supported. C Since the host processor is the master, it must place DCLK in the proper idle state before CS is asserted. 3.1.2.6 Length of Data Transactions The SPI port on the Le9622 device supports 8-bit (byte-wide) transactions. 16-bit transactions are not supported. 15 Microsemi Corporation Confidential and Proprietary Le9622 3.1.2.7 Preliminary Data Sheet SPI Interface Timing Figure 9 below shows a typical timing interface diagram for SPI Mode 3. L DCLK DIN X D7 D6 D.. D0 X DOUT D7 ET IA CS X X X X X X X D6 D5 D4 D3 D2 D1 D0 X Figure 9 - SPI Mode 3 Interface Timing 3.1.2.8 MPI Interface N The Microprocessor Interface (MPI) is essentially a 4-Wire SPI Mode 3, with CS low for each byte and 8-bit data transactions. This interface has been historically used on numerous Microsemi devices.With the MPI interface, 8-bit commands can be followed with additional bytes of input data, or can be followed by the Le9622 device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data bytes are read or written one at a time, with CS going high for at least a minimum off period before the next byte is read or written. Only a single channel should be enabled during read commands. FI D All commands that require additional input data to the device must have the input data as the next N words written into the device (for example, framed by the next N transitions of CS). All unused bits must be programmed to 0 to ensure compatibility with future parts. All commands that are followed by output data will cause the device to output data for the next N transitions of CS going low. The Le9622 device will not accept any commands until all the data has been shifted in or out. The output values of unused bits are not specified. Figure 10 shows an example MPI mode interface timing, with DOUT changing on the negative edge of DCLK. DIN is sampled on the rising edge of DCLK. CS Off-Period N CS 1 2 3 4 5 6 7 8 1 2 3 O DCLK DOUT Three-State C DIN Figure 10 - MPI Interface Timing An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the high state between accesses, the DCLK may run continuously with no change to the internal control data. Using this method, the same DCLK can be run to a number of Le9622 devices and the individual CS lines will select the appropriate device to access. 16 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet Between command sequences, DCLK can stay in a static state indefinitely with no loss of internal control information regardless of any transitions on the CS lines. Between bytes of a multi byte read or write command sequence, DCLK can also stay in a static high state indefinitely. If the host controller has a single bidirectional serial data pin, the DOUT pin of the Le9622 device can be connected to its DIN pin. Input / Output Block ET IA 3.2 L If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 or more positive transitions, the first 8 transitions will be interpreted as the first byte and the next 8 transitions will be treated as the second byte, etc. This allows the chip select input to be tied low permanently if desired. The Le9622 device features two dedicated and two optional general purpose input / output (I/O) pins. I/O11 and I/O12 can be configured by the user as inputs, outputs, or as high current LED or relay drivers. I/O21 and I/O22 may be configured as general purpose digital inputs or outputs or as voltage sense pins (VS1 and VS2). When configured as inputs, I/O21 and I/O22 are capable of generating interrupts. 3.3 Voltage Sense C O N FI D N The voltage sense block allows the measurement of analog voltages at the pins VS1 and VS2, when they are configured as analog inputs. This makes it possible to monitor VSW and VBH or VBL in real time and make switcher optimizations based on their levels and to measure power consumption. An external 1.0M1 resistor needs to be connected between each of these pins and the voltages to be measured. 17 Microsemi Corporation Confidential and Proprietary Le9622 3.4 Preliminary Data Sheet Voice Signal Processor L This block, shown in Figure 11, performs digital signal processing for the transmission and reception of voice. It includes G.711 compression/decompression, impedance matching, filtering, gain scaling, DTMF generation and general purpose tone generators for each channel. Additionally Caller ID (FSK and DTMF) and metering generation are provided. ET IA This block performs the Codec and filter functions associated with the four wire section of the subscriber line circuitry in a digital switch. These functions involve converting an analog voice signal into digital PCM samples and converting digital PCM samples back into an analog signal. During conversion, digital filters are used to band limit the voice signals. The user-programmable filters perform the following functions: • Sets the receive and transmit gain • Performs the transhybrid balancing function • Permits adjustment of the two wire termination impedance • Provides frequency attenuation adjustment (equalization) of the receive and transmit paths Country and standards specific Profiles are available from Microsemi with pre-computed digital filter coefficients. The PCM codes can be either 16-bit linear two's-complement or 8-bit companded A-law or µ-law. PTCA High Voltage Line Driver FI D TIP RING N The Le9622 device is architected in such a way as to reduce the real time demands on the host processor. An integrated cadencer/sequencer controls ringing and call progress tone generation. This feature can also generate timed interrupts and substantially reduces the user’s need to implement time critical functions.  AR* DAC  DRL*  Interpolator  Interpolator V to I Converter LPF  RI* (C/L) Expander (CRP) (LRG) Lower Receive Gain Z* DISN* 1kHz Tone (TON) 0 R* GR* IRSN RTV Signal Generators A, B, C and D (Ringing, FSK, Call Progress) (TON) From PCM Block Linear Mode * Programmable Blocks B* RTV TAC ADC & AX RTAC CTAC N Transmit RAC Buffer Decimator High Pass Filter Decimator  GX* X* NF & HPF (HPF) High Pass Filter RRAC CRAC C O Figure 11 - Voice Signal Processing Block Diagram 18 Microsemi Corporation Confidential and Proprietary LPF Com- (C/L) pressor Linear Mode (ILB) To PCM Block Le9622 3.4.1 Preliminary Data Sheet Impedance Synthesis L The analog impedance synthesis loop is comprised of the SLIC block, the AC sense path components, the transmit amplifier, and a voltage to current converter. An external resistor, RTV, synthesizes the nominal impedance in the analog domain. Additional refinement of the impedance is done in the DSP via the Digital Impedance Scaling Network (DISN) and Z-blocks. ET IA The DISN path is comprised of the voice A/D and its first stage of decimation, a DISN, and the voice DAC. The 8-bit DISN synthesizes a portion of the AC impedance which appears in parallel with RTV and is used to modify the impedance set by the external analog network. The Z Filter is a programmable digital filter providing an additional path and programming flexibility over the DISN in modifying the transfer function of the synthesis loop. Together RTV, DISN, and the Z Filter enable the user to synthesize virtually all required telephony device input impedances. 3.4.2 Frequency Response Correction and Equalization The voice signal processor contains programmable filters in the receive (R) and transmit (X) directions that may be programmed for line equalization and to correct any attenuation distortion caused by the Z Filter. 3.4.3 Transhybrid Balancing 3.4.4 N The voice signal processor’s programmable B Filter is used to adjust transhybrid balance. The filter has a single pole Infinite Impulse Response (IIR) section and an eight-tap Finite Impulse Response (FIR) section, both operating at 16 kHz. Gain Adjustment FI D The transmit path of the FXS has two programmable gain blocks. Gain block AX is an analog gain of 0 dB or 6.02 dB (unity gain or gain of 2.0), located immediately before the A/D converter. GX is a digital gain block that is programmable from 0 dB to +12 dB, with a worst case step size of 0.1 dB for gain settings below +10 dB, and a worst case step size of 0.3 dB for gain settings above +10 dB. The filters provide a net gain in the range of 0 dB to 18 dB. The receive voice path has three programmable gain blocks. GR is a digital loss block that is programmable from 0 dB to 12 dB, with a worst case step size of 0.1 dB. DRL is a digital loss block of 0 dB or 6.02 dB. AR is an analog gain of 0 dB or 6.02 dB (unity gain or gain of 2) or a loss of 6.02 dB (gain of 0.5), located immediately after the D/A converter. This provides an attenuation in the range of 0 dB to 18 dB. The gain adjustment block can also be accessed by a VP-API-II function directly, without using an AC FXS Profile. N Function Name Description Adjusts transmit and/or receive gain up to +/-6 dB. Relative gain of 1 (0 dB) defined as initial value programmed by AC FXS Profile. Note that the supplied AC FXS Profiles have initial gains of -6 dBr receive and 0 dBr transmit VpSetOption() VP_OPTION_ID_ABS_GAIN -- Programs absolute gain O VpSetRelGain() 3.4.5 Table 2 - VP-API-II Functions for Gain Adjustment Transmit Signal Processing C In the transmit path (A/D) of the FXS, the AC Tip - Ring analog input signal is sensed by the TAC and RAC pins, buffered, amplified by the analog AX gain and sampled by the A/D converter, filtered, companded (for A-law or µ-law), and made available to the PCM blocks. If linear format is selected, the 16-bit data will be transmitted in two consecutive time slots starting at the programmed time slot. The B, X, and GX digital filter blocks are userprogrammable digital filter sections. The first high-pass filter is for DC rejection, and the second high pass and notch filters reject low frequencies such as 50 Hz or 60 Hz. 19 Microsemi Corporation Confidential and Proprietary Le9622 3.4.6 Preliminary Data Sheet Receive Signal Processing In the receive path (D/A) of the FXS port, the digital signal is expanded (for A-law or µ-law), filtered, interpolated, converted to analog, and driven onto TIP and RING by the SLIC block. The AR, DRL, DISN, Z, R, and GR blocks are user programmable filter sections. Speech Coding L 3.4.7 3.4.8 Wideband Operation ET IA The A/D and D/A conversion follows either the A-law or the µ-law standard as defined in ITU-T Recommendation G.711. Alternate bit inversion is performed as part of the A-law coding. Linear code is an option on both the transmit and receive sides of the device. Two successive time slots are required for linear code operation. The linear code is a 16-bit two’s-complement number which appears sign bit first on the PCM highway. Each channel on the Le9622 device can be set to operate in either Narrowband or Wideband mode under VP-APIII software control. In the Wideband mode, the nominal voice bandwidth is expanded and starts at 50 Hz or 200 Hz (depending on whether or not a high-pass and 50/60 Hz notch filter is enabled) to 7000 Hz to provide better voice quality. The AC FXS Profiles must be programmed with wideband coefficients. In the Wideband mode, the increased data rate is processed by accessing a second set of timeslots equally spaced in the frame. Function Name Description VP_OPTION_ID_TIMESLOT -- Programs transmit and receive timeslot. VP_OPTION_ID_CODEC -- Programs speech coding mode. VpGetOption() VP_OPTION_ID_TIMESLOT -- Retrieves current values of transmit and receive timeslot. VP_OPTION_ID_CODEC -- Retrieves current speech coding mode. N VpSetOption() 3.5 FI D Table 3 - VP-API-II Functions for Speech Coding Signal Generation Up to four programmable digital signal generators are available for the FXS channel. These signal generators can be programmed for multi-tone generation, amplitude and frequency modulation, and or the generation of complex sine, triangular or trapezoidal signals. 3.5.1 Multi-Tone Generation N In this configuration, up to four tone generators are summed into the output path, as shown in Figure 12 on page 21. The Bias generator produces a DC bias that can be used to provide DC offset during ringing or DC test signals during diagnostics. This generator is automatically enabled when entering the VP_LINE_RINGING state. O Function Name Description Provides simultaneous generation of up to four tones. Note that with Tone Cadencing, tones can be enabled/disabled individually to provide Special Indication Tone (SIT). VpSetLineState() VP_LINE_RINGING and VP_LINE_RINGING_POLREV -- Uses Signal Generator A (and B for trapezoidal type ringing) with user selected frequency, offset, amplitude, and type. VpSendSignal() VP_SENDSIG_DTMF_DIGIT -- Generates a DTMF digit on the line. C VpSetLineTone() VpInitCid() VpSendCid() Sending Caller ID (FSK and DTMF message data supported) on an FXS line. Providing Type 2 CID Alerting tone. VpContinueCid() Table 4 - VP-API-II Functions Using Signal Generators 20 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet AMPA Signal Generator A FRQA EGA EGB Signal Generator B FRQB  EGC AMPC Signal Generator C L AMPB Signal Generator Out ET IA EGD FRQC EGBIAS AMPD Signal Generator D FRQD Bias BIAS Figure 12 - Multi-Tone Generation Signal Generator A is also used by the VeriVoice test suites to produce slow ramps. This allows a complex sequence of diagnostic test voltages to be generated in a controlled manner without generating unwanted transients on the line. N Each generator has independent frequency and amplitude parameters. The frequency accuracy is basically the same as the crystal accuracy of the system. The EGA/B/C/D bits are controlled by the VP-API-II Cadencing engine. Frequency and Amplitude Modulation FI D 3.5.2 The signal generators can also be used to generate frequency and/or amplitude modulated tones in conformance with worldwide Howler (receiver off-hook) and call progress tone requirements. Frequency modulation is performed in a dedicated hardware block, while amplitude modulation is performed in software by VP-API-II. N To generate frequency modulated tones, Signal Generator A is configured as a modulator, while Signal Generator D is configured as a carrier. The output of Signal Generator A is the frequency input to Signal Generator D as shown in Figure 13. Note that Signal Generator A needs a positive DC bias so that its output is always positive. Caller ID generation is not available while frequency modulation is taking place. Note that Signal Generators B and C are available to be summed to the frequency modulated signal, if necessary. AMPA  C O FRQA EGA Signal Generator A  (Modulator) AMPD FRQD Signal Generator D  (Carrier) Frequency  Modulated Signal Out EGBIAS BIAS Bias Figure 13 - Frequency Tone Modulation 21 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet Frequency and amplitude modulation allow the Le9622 device to meet exacting Howler tone requirements such as those specified in BTNR 1080 Version 15 and Draft 960-G, NTT Edition 5 and Austel AUS002:2001. Table 5 lists the VP-API-II functions that are used for Howler tone generation. Description L Function Name VP_LINE_HOWLER -- Places the device in a high gain state for Howler tone generation. VpSetLineTone() Provides simultaneous generation of up to four tones. Note that with Tone Cadencing, tones can be enabled/disabled individually or modulated in order to generate Howler tones. ET IA VpSetLineState() Table 5 - VP-API-II Functions for Howler Tone Generation 3.5.3 Triangular and Trapezoidal Signal Generation The signal generators can also be used to generate trapezoidal waveforms for ringing. Figure 14 shows a configuration that is typically used to generate trapezoidal waveforms. Triangular waveforms can also be generated. AMPA Signal Generator A (Modulator) EGA  AMPD FRQD AMPC FRQC  Signal Generator D  (Carrier) N FRQA AMPB FRQB Triangular or  Trapezoidal  Signal Signal  Generator  Out EGC Signal Generator C FI D EGBIAS BIAS Bias Figure 14 - Trapezoidal Signal Generation Low Power DC Feed N 3.6 O The Le9622 device supports Low Power Idle Mode (LPIM), which reduces the system power consumption during idle (On-Hook) state. LPIM provides a weak DC feed capable of at least 5 mA to the line and reacts to a change in the line voltage to create an off-hook indication when a telephone goes off-hook. 3.7 Normal DC Feed C DC feed is active in normal idle, talk and ringing states and the programmed characteristics appear between Tip and Ring. VAS is chosen to ensure that sufficient headroom is available for the amplifiers when on-hook to support On-Hook Transmission with the programmed open circuit (VOC) voltage. The parameters that control DC feed are summarized in Table 6 on page 23. Their values are determined by the VP-API-II using the VpCalLine() function to ensure circuit performance. In addition, the VP-API-II handles some internal programming depending on the selected VOC voltage. 22 Microsemi Corporation Confidential and Proprietary Le9622 Description 20 – 30 mA Sets open circuit DC feed voltage. Two ranges, 12 - 33 V and 36 - 57 V are supported VOC 12 – 57 V VAS 1.5 – 7.25 V ABSCAL -5.25 – +5.25 V bshv Sets the current limit for DC feed 1.0 – 7.0 V L ILA Range Allows for some programmability for the automatic battery switching point ET IA Parameter Preliminary Data Sheet Allows calibration of the battery switching point per channel Battery switch hysteresis voltage Table 6 - DC Feed and Battery Switch Programmable Parameters The DC Profile produces a DC feed curve at Tip and Ring when the fuse resistors are inside the feedback loop formed by the RTDC, RRDC feedback network. Note that the value of the combined Tip and Ring feed resistors Rfeed is programmable to 0, 50, 100, or 200  to correspond to the choice of PTCs or fuse resistors that are used. Please refer to Figure 15 below for the active state I/V feed curve for Rfeed = 200 . N VTIP - VRING VBH VOC FI D Rfeed = 200 Loop Feed from VBH VBL O N (VAS + ABSCAL + 200*ILA + bshv )V VBH to VBL switching point Loop Feed from VBL ILOOP ILA Figure 15 - Normal DC Feed I / V Characteristic C Figure 41, “Profile Wizard - DC Profile Configuration Example” on page 75 shows typical DC feed parameters. 3.8 Test Feed The Tip Open test state presents the DC feed characteristic shown in Figure 15 between the Ring lead and ground. 23 Microsemi Corporation Confidential and Proprietary Le9622 3.9 Preliminary Data Sheet Ringing The Le9622 device supports balanced ringing. 3.9.1 Balanced Ringing ET IA L Internal balanced ringing drives the subscriber line with balanced ringing voltage waveforms (see Figure 16). In the balanced ringing mode, the ringing signal is driven differentially, thus maximizing the ringing signal swing. In this mode, the SLIC appears to the subscriber line as a voltage source with an output impedance of 200 . The maximum ringing signal possible in the balanced mode for the Le9622 is 100VPK corresponding to the maximum AC + DC voltages. V Tip - Ring Voltage 0V Ring Voltage N Tip Voltage Battery Voltage = SWRV 3.9.2 FI D Figure 16 - Balanced Ringing with Fixed Supply Adaptive Ringing Amplitude The Le9622 device supports adaptive ringing amplitude, which limits the maximum power that is generated by the device during ringing at or below a specified level. This will contribute to greater power efficiency and will avoid the thermal shutdown of the device or ringing stoppage when driving heavy loads. 3.9.3 Switch Hook Detection N The FXS supervision circuits of the Le9622 device provide debounced off-hook indications to an external processor via the host port interface. The supervision circuit compares a scaled version of the Tip-Ring current to a programmed off-hook threshold, TSH. The output of the comparator is debounced by a programmable debounce timer, DSH. A debounced Off-Hook indication generates an interrupt to the host processor. 3.9.4 Ring Trip Detection O Ring trip is the process of sensing a subscriber’s off-hook event during ringing. This is accomplished by sensing the rise in loop current which occurs when a phone goes Off-Hook. The Le9622 device can detect ring trip when the ringing signal is purely AC and/or when the ringing signal has a DC bias on it. To do so, the ring trip algorithm is automatically altered internally by the Le9622 device based on the user-programmed parameters. C The ring trip detector uses the Tip-Ring current as an input. This current is rectified so that AC + DC ring trip can be detected. The output of the rectified signal is compared to a programmable ring trip threshold and the output is digitally debounced. The output is blanked upon ring entry to avoid false ring trips. The ring trip detection circuit provides debounced ring trip indications to an external processor via the host port interface. The ring trip circuit compares a scaled version of the Tip-Ring current to a programmed Ring Trip Threshold (RTTH). The output of the comparator is processed by the ring trip algorithm on a cycle by cycle basis to 24 Microsemi Corporation Confidential and Proprietary Le9622 Preliminary Data Sheet provide immunity to false ring trips. In addition, spending more than 50% of the time in ringing current limit will generate a trip indication. A positive ring trip occurs if a trip indication is present for one (optional) or two (default) complete ring cycles, and an interrupt can be raised to the host processor. For AC-only ringing, the signal is halfwave rectified. L The Ring Trip Threshold (RTTH), integration method (positive half-wave for AC only or full-wave for AC+DC), the number of cycles (1 or 2), and Ringing Current Limit (ILR) are programmed in the Ringing Profile. Microsemi provides a number of example Ringing Profiles for most common ringing requirements incorporating the ringing signal parameters and corresponding ring trip settings. Name ET IA The following equations can be used to select new ring trip settings when using different ringing waveforms and different loads. They allow the ratio of the open circuit ringing voltage to the ringing threshold current to vary by +/-20%, which is conservative. Description AMPA Amplitude of signal generator A which is used for ringing FREQA Frequency of signal generator A which is used for ringing BIAS DC bias for ringing RTDCAC Ringing trip based on AC only or Battery Backed (DC) Ringing RTTH Ringing trip threshold in 0.5 mA steps from 0 to 63.5 mA ILR Ringing current limit programmed in 2 mA steps. ILR=0 represents 50 mA. ILR = 31 represents 112 mA HOOK Interrupt in signalling register indicating a ring trip occurred N Table 7 - Ring Trip Parameters FI D For AC only ringing, RTDCAC is 1 and the ringing current is half-wave rectified and averaged over a ringing cycle. If this result exceeds the RTTH threshold for two successive cycles, the HOOK bit will be set. This method limits the supported loop length x depending on the minimum must not trip ringing impedance (Rmnt in Ohms) and allowing for errors in the applied ringing voltage and trip level. The maximum loop resistance is given by: RLOOP  max  = 0.67 xR mnt – Rphone – 66 RLOOP (max) excludes the DC resistance of the phone (Rphone, typically 430  in the U.S.), and the fuse resistance if DC line sensing is behind the fuse resistors. 0.54 x VRING RTTH = -----------------------------------Rmnt + 200 1.4 x VRING ILR = -----------------------------------Rmnt + 200 O N For a sinusoidal ringing waveform of VRING (RMS) volts, and Rmnt impedance, the following ring trip settings should be used: C In general for short loop applications, it is recommended to use AC ring trip even in the presence of a DC bias that could allow a DC based ring trip, and the above equations still apply. Note that the ringing source impedance is nominally 200 . 25 Microsemi Corporation Confidential and Proprietary Le9622 3.10 Preliminary Data Sheet Subscriber Line Testing 3.10.1 VeriVoice Professional Test Suite Software L The Le9622 device provides the ability for the user to perform the Telcordia GR-909-CORE / TIA-1063 diagnostic testing for the voice ports. In Test mode, a variety of input signals can be read from the voice ADC converter. These signals include the switching regulator voltage and the line DC and AC voltages. VeriVoice Professional Test Suite Software is an advanced test suite featuring the following tests: Line Voltage: Receiver Off-Hook: Regular REN: • • • Electronic REN: Resistive Fault: GR-909-CORE / TIA-1063: • • • • • • Capacitance: Master Socket: Cross Connect: Loop back: Read Loop Conditions: • • • N • N • Measures three element capacitance Detects master socket terminations Detects cross connected FXS Enables receive-to-transmit signal loop-back using two different methods Measures DC voltages between Tip and Ring, Tip to ground, Ring to ground, and VBAT to ground. Also measures metallic and longitudinal DC line currents in supported States. Read Battery Conditions: Reads the battery voltages connected to the line circuit. DC Voltage Self-Test: Verifies that the line circuit has the ability to drive the voltage ranges required for the normal operation of the line circuit. DC Feed Self-Test Measures the voltage and current across a known internal test termination using the DC Profile that has been programmed. Ringing Self-Test Verifies ring signal generation, drive capability, and ring trip. On/Off-Hook Self-Test Creates on-hook and off-hook conditions on the line using the internal test termination and verifies that they are properly reported. Draw and Break Dial Tone Verifies the capability of the line circuit to detect off-hook and on-hook as well as the voice path to/from the host Read Loop Conditions - Extended Reads the loop conditions of the current state of the line without disturbing the T/R feed conditions. Measures AC and DC voltages Tip and Ring, Tip to ground and Ring to ground. Measures VBAT to ground. Also measures metallic and longitudinal AC and DC line currents in supported States. FI D • • Checks for hazardous and foreign AC and DC voltages. Checks for longitudinal fault, off-hook resistive fault and receiver off-hook. Tests the impedance of the line and returns a fail if the Ringer Equivalence Number (REN) is too low or high. Provides REN Tip to Ring, Tip to ground and Ring to ground based on capacitance Measures three-element resistance. Performs all of the GR-909-CORE outward tests in the correct sequence. ET IA • • • 3.11 Manufacturing Testing C O The Le9622 is supported by the VeriVoice Manufacturing Test Package (VVMT), a platform-independent ’C’ source code module which facilitates factory testing and calibration of assembled boards with this and other Microsemi voice products. 26 Microsemi Corporation Confidential and Proprietary Le9622 3.12 Preliminary Data Sheet Metering The Le9622 device is capable of 0.5 VRMS metering into a 200  metering load at either 12 kHz or 16 kHz. Smooth metering application and abrupt metering application are supported. A typical metering sequence is shown below in Figure 17. ET IA L Metering Signal (Peak Current / Voltage Limit)