LX7178-01CSP-TR

LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Description Features The LX7178 is a digitally controlled step-down regulator IC with an integrated 40mΩ high-side P-channel MOSFET and a 14mΩ low-side N-channel MOSFET. It features Microsemi’s proprietary constant-frequency hysteretic control engine for near-instantaneous correction to line/load transients. It does not require high-ESR output capacitors and incorporates energysaving “PSM” (Power Save or Pulse Skip Mode) at light loads, to extend battery life in mobile applications.  Constant Frequency Hysteretic Control 2 The LX7178 has an I C serial interface port for output voltage margining and monitoring if required (it can also operate in default mode). In addition it includes robust fault monitoring functions. The LX7178 will operate from 3V to 5.5V, and is available in 0.8V fixed output voltage option (no voltage divider is necessary). The output voltage can also be adjusted with an external voltage divider up to 3.3V.  Extremely Fast Line/Load Transient Response  I2C for Output Adjustment (3.4Mbps)  1.875 MHz Switching Frequency  Extremely Low-RDSON MOSFETS  Input Voltage Rail 3.3V to 5V  Greater than 5A Output Current  I2C Selectable Power Save Mode for Light-Load Efficiency  UVLO, OVP, OCP  0°C to +85°C Ambient Temperature  Available in WLCSP-20 (0.4mm pitch)  RoHS Compliant Applications  High Performance HDD  Notebooks/Netbooks/Tablets/Slates Figure 1: Typical 5V to 0.8V application with I2C implemented Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 1 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Other Application Diagrams Figure 2: Typical 5V to 0.96V application without I2C implemented Figure 3: Typical 5V to 0.96V application with I2C implemented Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 2 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Pin/Ball Configuration Part Marking: MSC XXXX YWWA XXXX=Device Number YWWA E.g.: 7801=LX7178-01CSP Year/Work Week/Lot Code Figure 4: Pinout Ordering Information Ambient Temperature Type Package Set Output Voltage 0.8V 0°C to 85°C RoHS compliant, Pb-free WLCSP-20 (0.4mm pitch) 0.8V Part Number LX7178-01CSP LX7178-xyCSP* LX7178-01CSP-TR LX7178-xyCSP-TR* Packaging Type Bulk Tape and Reel 2 * Consult factory for other I C slave address and set output voltage options. 2 “x” is the 2 LSB bits of the binary I C slave address (0 to 3); “y” is the set output voltage (0 is 0.6V, 1 is 0.8V, 2 is 0.9V, 3 is 0.975V) Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 3 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Pin/Ball Description Pin/Ball Number Pin/Ball Designator Description Open Drain status output, requires external pull up resistor. This pin will go low when VOUT is outside the defined power good range, when the die is hotter than the thermal shutdown threshold, when PVIN is above the over voltage threshold, or when PVIN is below the under voltage threshold. A1 PGOOD A2 EN Enable for switching regulator. Force high to enable, force low to disable the IC. A3 FB Feedback Voltage sense – Analog Input – This voltage is compared with the internal VREF voltage to control the hysteretic converter. Normally this is connected to VOUT via a resistor divider network. SCL Serial Data Clock – Logic Input – Clock for the serial interface. Glitches shorter than 50nS will be ignored. If the serial interface is not used, connect to GND or VIN. This pin can also be connect to VOUT if required by the layout. B1 SDA Serial Data – Bi-Directional Logic – This I2C pin is used to receive clocked serial data from the host and to send clocked serial data to the host. Glitches shorter than 50nS will be ignored. If the serial interface is not used in the application, this pin should be connected to VIN or GND. B2, B3, C1 – C4 GND Ground. Connect to ground plane. B4 AGND Analog Ground. Connect to ground plane. A4 D1, D2 E1, E2 VIN Input of IC and buck stage. Connect to input rail VIN (between 3V and 5.5V). A minimum input capacitance of one 1µF and one 22µF of X5R or better multilayer ceramic, should be placed very close to IC between this node and GND. D3, D4 E3, E4 SW Switching Node. Drives the external L-C low pass filter. Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 4 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Functional Block Diagram Figure 5: Block Diagram Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 5 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Absolute Maximum Ratings Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability. Min -0.3 -0.3 -2 VIN, SW to GND EN, FB, SDA, SCL, PGOOD to GND SW to GND (Shorter than 50ns) Maximum Junction Temperature Lead Soldering Temperature (40s, reflow) Storage Temperature -65 Max 7 7 7 150 260 (+0, -5) 150 Units V V V °C °C °C Operating Ratings Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. Min 3 0 VIN Ambient Temperature Output Current Max 5.5 85 5 Units V °C A Note: Corresponding Absolute Max Junction Temperature is 150°C. Thermal Properties Thermal Resistance θJA Typical 38 Units °C/W Note: The JA number assume no forced airflow. Junction Temperature is calculated using TJ = TA + (PD x JA). In particular, θJA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 6 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Electrical Characteristics Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device. Typ values stated, are either by design or by production testing at 25°C ambient. Symbol Parameter Input Voltage IQ Input current Input current at IIN shut down Input current I2C IIN_I2C shut down Under voltage UVLO rising threshold UVLOHYST UVLO hysteresis Over voltage rising OVPR threshold Over voltage falling OVPF threshold Reference Voltage Minimum VREFMIN reference voltage Mean VREFMEAN reference voltage Maximum VREFMAX reference voltage TSS VREF slew rate THICCUP Hiccup time Output Voltage VOUT Default VOUT Line regulation VOUV Copyright © 2014 Rev. 1.1, 8/7/2014 Load regulation VOUT input current VOUT under voltage threshold Conditions Min Typ Max Units ILOAD = 0, PSM enabled 200 440 600 µA EN = GND, TA = 25°C 0.1 3 µA VSEL(7) = low, EN = high 100 120 µA VIN rising 2.6 2.8 V 0.26 V VIN_OVP: Ctrl1(1) = 1 6.25 6.75 V VIN_OVP: Ctrl1(1) = 1 5.75 6.2 V VSEL(6:0) = 00h 0.588 0.6 0.612 V VSEL(6:0) = 40h 0.888 0.9 0.912 V VSEL(6:0) = 7Fh 1.184 1.195 1.206 V 3 4 1.5 5.5 mV/μs ms -1.5 0 1.5 % SLEW: Ctrl2(2:0) = 011 VOUT = 0.2V Target based on option: 01 = 0.8. Measured with respect to target voltage. VIN from 3V to 5.5V, ILOAD = 1A. Note 1 ILOAD = 0A to 5A. Note 1 VOUT below this threshold will initiate a hiccup sequence 0.1 77 % -0.17 0 1 %/A μA 82 85 %VREF Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 7 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Symbol SW Parameter High side on resistance Low side on RDSON_L resistance OCP Current limit Thermal shut down TSH threshold TH Hysteresis PWM switching FSW frequency SW discharge RSWDISC resistance EN, SDA (as input), SCL VIH Input high VIL Input low VH Hysteresis III Input current PGOOD PGOOD VOUT VPG90 lower threshold PGOOD VOUT VPG110 upper threshold VPGHY Hysteresis PGOOD pull down PGRDSON resistance PGOOD leakage current Conditions Min RDSON_H PGOOD delay Note 1 6.5 Typ Max Units 40 mΩ 14 mΩ 7.5 9 A Note 1 150 °C Note 1 20 °C EN = low; Discharge: Ctrl2(4) = 1; 1.5 1.875 2.25 MHz 80 200 1400 Ω 1.1 0.1 0.01 1 V V V μA 0.4 VOUT rising, percentage of VREF 85 90 95 %VREF VOUT falling, percentage of VREF 105 110 115 %VREF Percentage of VREF PGOOD rising edge delay (only when enabled by setting CTRL 1:5 to 0). By default, this delay is not enabled. 5 30 %VREF 100 300 Ω 0 1 μA 45 65 ms 0.8 LSB 7 Bit DAC Differential linearity Note 1: Guaranteed by design. Copyright © 2014 Rev. 1.1, 8/7/2014 Monotonicity assured by design Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 8 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Application Specifics Efficiency IOUT = 1.5A, VCC = 5V, VOUT = 3.3V 95% IOUT = 5.0A, VCC = 5V, VOUT = 3.3V 90% VOUT Min Transient 0.5 A to 2.5 A load step slews in 900ns, CLOAD = 3 x 22μF ceramic caps, 0.47μH inductor 31.6mV VOUT Max transient 2.5 A to 0.5 A load step slews in 1.46μs, CLOAD = 3 x 22μF ceramic caps, L = 0.47μH inductor 34.8mV Typical Load Inductance DCR = 6.7mΩ, IDC = 12.2A, ISAT = 16A. 0.47μH Typical Load Capacitance 6.3V, X5R 3x22μF Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 9 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Layout Recommendations The LX7178 EVAL Board is a 4-layer board, the thickness of the board is 63mil in total. The second layer to top layer is 7mil, the third layer to the bottom layer is 7mil. The recommended BGA PCB layout shown below requires no microvias or blind vias. Each signal trace can exit the LX7178 directly without any vias under the device. Also, with the bypass capacitors C2, C3 and C8 implemented as shown it can lower the ESL. Please see LX7178 User Guide for additional details. Figure 6: Layout recommendation (TOP layer) Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 10 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Figure 7: Layout recommendation (BOTTOM layer) Figure 8: Closeup of Layout in Region of BGA (note Ground gull-wings and via Stitching to BOTTOM) Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 11 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Typical Performance Curves Dynamic Response Copyright © 2014 Rev. 1.1, 8/7/2014 Figure 9: No load to 0.5A PWM CH2: VOUT, CH4: ILOAD Figure 10: No load to 0.5A PSM CH2: VOUT, CH4: ILOAD Figure 11: 0.5A to 2.5A PWM CH2: VOUT, CH4: ILOAD Figure 12: 0.8A to 2.5A PWM CH2: VOUT, CH4: ILOAD Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 12 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Typical Performance Curves (Continued) Dynamic Response (Continued) Figure 13: 0.5A to 2.5A PWM Rising Edge CH2: VOUT, CH3: SW, CH4: ILOAD Figure 14: No load to 0.5A PSM Rising Edge CH2: VOUT, CH3: SW, CH4: ILOAD Figure 15: 0.5A to 2.5A PWM Falling Edge CH2: VOUT, CH3: SW, CH4: ILOAD Figure 16: No load to 0.5A PSM Falling Edge CH2: VOUT, CH3: SW, CH4: ILOAD Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 13 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Typical Performance Curves (Continued) Efficiency LX7178 5V VIN Efficiency 100% 90% 80% 70% Efficiency 60% 50% 40% 30% 20% 10% 0.96V PSM 1.8V PSM 3.3V PSM 0.96V PWM 1.8V PWM 3.3V PWM 0% 10 100 1000 Load Current (mA) Figure 17: Efficiency Curves for 5V input Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 14 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet I2C Timing Specifications Symbol fSCHL tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT trCL trCL1 tfCL trDA tfDA tSU;STO tBUF tVD;DAT tVD;ACK Cb Parameter SCL clock frequency Set-up time for a repeated START condition Hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock Data set-up time Data hold time Rise time of SCL signal Rise time of SCL signal after a repeated START condition and after an acknowledge bit Fall time of SCL signal Rise time of SDA signal Fall time of SDA signal Set-up time for STOP condition Bus free time between a STOP and START condition Data valid time Data valid acknowledge time Capacitive load for each bus line Conditions SDA and SCL lines Cb = 100 pF (max) (*Note2) Min Max 0 3.4 Cb = 400 pF Unit Min 0 Max 0.4 MHz 160 - 600 - ns 160 - 600 - ns 160 - 1300 - ns 60 - 600 - ns 10 0 10 70 40 100 0 20*0.1Cb 300 ns ns ns 10 80 20*0.1Cb 300 ns 10 10 10 40 80 80 20*0.1Cb 20*0.1Cb 20*.01Cb 300 300 300 ns ns ns 160 - 600 - ns 160 - 1300 - ns - 160 - 900 ns - 160 - 900 ns - 100 400 pF Note 1: All values referred to VIH(min) and VIL(max) levels of I/O stages table. Note 2: Loads in excess of 100pf will restrict bus operation speed below 3.4MHz Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 15 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Operation Theory Basic Operation Setting the Output Voltage The LX7178 compares VOUT voltage to an internal reference, VREF. When VOUT is lower than VREF, the upper switch turns on and the lower switch turns off. When VOUT is higher than VREF, the upper switch turns off and the lower switch turns on. An internal ramp helps to keep the switching frequency constant over a wide range of output capacitor values and parasitic components (i.e. ESR, ESL). In addition, a frequency control loop keeps the switching frequency constant during continuous conduction mode. The reference voltage is programmed with the I2C bus VSEL register value. At light loads, if enabled, the converter automatically reduces the switching frequency and enters discontinuous conduction to optimize efficiency while ensuring low VOUT ripple voltage. An integrated I2C bus interface, operating up to 3.4Mbps, adds the following use programmability to the converter: (2) Where NSEL is the decimal value of the 7 VSEL bits. Startup If the LX7178 is enabled, when VIN rises above the UVLO threshold, the regulator will initiate a startup sequence. The serial port registers are initialized to their default values and all internal bias voltages and currents are allowed to stabilize. VREF then ramps up from 0V to the default voltage at the default slew rate. At the end of the ramp time, PGOOD is allowed to go high 45ms after VOUT has reached the PGOOD rising threshold. During the ramp time, the LX7178 switches to PSM to allow discontinuous operation. This switchover is independent of the MODE bit setting. 1. On the fly programming of the output voltage in 4.7mV increments. 2. Enable / Disable the regulator. 3. Allow PSM or limit operation to only PWM mode. 4. Set the VREF slew rate. 5. Switch node slew rate control. Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 16 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Operation Theory (Continued) Over Current Protection Negative Voltage Transitions The LX7178 protects against all types of short circuit conditions. Cycle by cycle over current protection turns off the upper switch when the current exceeds the OCP threshold. When this occurs, the upper switch is held off for at least 200ns before being allowed to turn on again. After startup, if VOUT drops below the VOUT under voltage threshold, a hiccup sequence will be initiated where both output switches are shut off for 1.5ms before initiating another soft start cycle. This protects against a crowbar short circuit. The VOUT under voltage detection is not active during start up. A negative voltage transition occurs when a lower output voltage is programmed into the VSEL register, and initiated by asserting the GO bit. In PSM, the LX7178 will not discharge the output filter capacitor. Positive Voltage Transitions After the initial start up sequence, the output voltage can be programmed to a new value by programming the VSEL register bits and then asserting the GO bit. VREF will transition to the new value at the programmed slew rate. The PGOK monitor bit is deasserted during the VREF ramp time, or when VOUT is outside the error envelope. Figure 19: Negative Voltage Transition Enabling Regulator from I2C Bus In addition to the EN pin, the regulator can be enabled and disabled via the I2C bus by programming the control register. During disable, the regulator and most of the support circuitry is turned off. However, the I2C bus circuitry is still active and may be programmed. Switch Node Rise Rate Adjustment The LX7178 can be programmed to operate in a lower emissions mode by slowing down the switch node rise rate. In this mode, the switch node rise rate will slow down 25%, reducing the switching frequency harmonic content. Figure 18: Positive Voltage Transition Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 17 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet I2C Interface I2C Port Functional Description Slave Address  In the table below, the A1 and A0 are the binary value of the address given in the ordering information shown on page 3.    Simple two wire, bidirectional, serial communication port. Multiple devices on same bus speeds from 400Kbps (FS-Mode) to 3.4Mbps (HS-Mode). SOC Master controls bus. Device listens for the unique address that precedes data. 7 0 6 0 5 0 4 1 3 1 2 A1 1 A0 0 R/W Table 1: I2C Slave Address General I2C Port Description START and STOP Commands The LX7178 includes an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock and data respectively. Each line is externally pulled up to a logic voltage when they are not being controlled by a device on the bus. The LX7178 interface acts as a I2C slave that is clocked by the incoming SCL clock. The LX7178 I2C port will support both the Fast mode (400kHz max) and typically the High Speed mode(3.4MHz max). The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). The state of the SDA line can only be changed when SCL is LOW (except for start, stop, and restart). When the bus is idle, both SCL and SDA must be high except in the power up case where they may be held high or low during the system power up sequence. Register Map The LX7178 has five 8-bit user-accessible registers. See Control Register Bit Definition. Copyright © 2014 Rev. 1.1, 8/7/2014 The STX SOC (bus master) signals START and STOP bits signify the beginning and the end of the I2C transfer. The START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. The STOP condition is defined as the SDA transitioning from LOW to HIGH while the SCL is HIGH. The STX SOC acts as the I2C masters and always generates the START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transfer, STX SOC master can generate repeated START conditions. The START and the repeated START conditions are functionally equivalent. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 18 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet I2C Interface (Continued) Data Transfers Data is transferred in 8 bit bytes by SDA with the MSB transferred first. Each byte of data has to be followed by an acknowledge (ACK) bit. The acknowledged related clock pulse is generated by the master. The acknowledge occurs when the transmitter master releases the SDA line to a high state during the acknowledge clock. The SDA line must be pulled down by the receiver slave during the 9th clock pulse to signify acknowledgment. A receiver slave which has been addressed must generate an acknowledgement (“ACK”) after each byte has been received. After the START condition, the STX SOC (I2C) master sends a chip address. The standard I2C address is seven bits long. Making the eighth bit a data direction bit (R/W). For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. (For clarification, communications are broken up into 9-bit segments, one byte followed by one bit for acknowledging.) The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. When a receiver slave doesn’t acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP command to abort the transfer. If a slave receiver does acknowledge the slave address but, sometime later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. Copyright © 2014 Rev. 1.1, 8/7/2014 The slave leaves the data line HIGH and the master generates the STOP command. The data line is also left high by the slave and master after a slave has transmitted a byte of data to the master in a read operation, but this is a not acknowledge that indicates that the data transfer is successful. Data Transfer Timing for Write Commands In order to help assure that bad data is not written into the part, data from a write command is only stored after a valid STOP command has been performed. I2C Electrical Characteristics The minimum HIGH and LOW periods of the SCL clock specified the I2C Timing Specification table determine the maximum bit transfer rates of, 400 kbit/s for Fast-mode devices, and 3.4 Mbits/s for HS-mode Plus. Devices must be able to follow transfers at their own maximum bit rates, either by being able to transmit or receive at that speed or by applying the I2C clock synchronization procedure, which will force the master into a wait state and stretch the LOW period of the SCL signal. Of course, in the latter case the bit transfer rate is reduced. Figures 22 and Figure 23 show all timing parameters for the HS & FS-mode timing. The ‘normal’ START condition S does not exist in HSmode. Timing parameters for Address bits, R/W bit, Acknowledge bit and DATA bits are all the same. Only the rising edge of the first SCL clock signal after an acknowledge bit has a larger value because the external Rp has to pull-up SCL without the help of the internal current-source. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 19 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet I2C Interface (Continued) The HS & FS-mode timing parameters for the bus lines are specified in the I2C Timing Specification Table. The minimum HIGH and LOW periods and the maximum rise and fall times of the SCL clock signal determine the highest bit rate. With an internally generated SCL signal with LOW and HIGH level periods of 200ns and 100ns respectively, an HS-mode master fulfills the timing requirements for the external SCL clock pulses (taking the rise and fall times into account) for the maximum bit rate of 3.4Mbit/s. So a basic frequency of 10MHz, or a multiple of 10MHz, can be used by an HS-mode master to generate the SCL signal. There are no limits for maximum HIGH and LOW periods of the SCL clock, and there is no limit for a lowest bit rate. Timing parameters are independent for capacitive load up to 100pF for each bus line allowing the maximum possible bit rate of 3.4Mbit/s. At a higher capacitive load on the bus lines, the bit rate decreases gradually. The timing parameters for a capacitive bus load of 400pF are specified in I2C Timing Specification Table, allowing a maximum bit rate of 1.7Mbit/s. For capacitive bus loads between 100pF and 400pF, the timing parameters must be interpolated linearly. Rise and fall times are in accordance with the maximum propagation time of the transmission lines SDA and SCL to prevent reflections of the open ends. Figure 20: Write Protocol Figure 21: Read Protocol Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 20 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet I2C Interface (Continued) Figure 22: Definition for FS-Mode devices on the I2C Port Figure 23: Timing definition for HS-mode devices on the I2C Port Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 21 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet I2C Interface (Continued) Figure 24: Write Cycle Diagram Figure 25: Read Cycle Diagram Control Register Bit Definition Bit Name Status, Address 00h 7:3 Reserved 2 OCP 1 OTP 0 FB_UVLO Value Description Latched to 1 if the over current limit is reached. Write a “1” to reset the status flag. Latched to 1 if an over temperature event occurs. Write a “1” to reset the status flag. Latched to 1 if a FB_UVLO event occurs. Write a “1” to reset the status flag. Vsel, Address 01h, (aka dac) 1-d 0 7 EN 6:0 VSEL[6:0] Copyright © 2014 Rev. 1.1, 8/7/2014 Device enabled. Device disabled. 7-bit DAC value to set VREF. The default value is determined by the part ordering code. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 22 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Bit Name Value Ctrl1, Address 02h, (aka reg2) 7:6 Reserved 00-d 1-d 5 DLY_DIS 0 4 ctrl1 0-d 1-d 3 SW_RATE 0 1-d 2 Reserved 0 1-d 1 Reserved 0 1 0 MODE 0-d Vendor ID, Address 03h (Read Only) 7:4 VID[7:0] 0010 3:2 A1A0 00 1:0 VOUT 00 Description Disable 45ms delay on PGOOD. 45ms delay on PGOOD is enabled. TBD Normal high efficiency rise rate. Reduced switch node rise rate. PWM mode only – NO PSM. Power Save Mode – allows discontinuous conduction. Microsemi Vendor ID . Designates the slave address version. These bits will correspond to the two LSB bits. Designates the default output voltage version, 00=0.6V, 01=0.8V, 10=0.9V, 11=0.975V. Ctrl2, Address 04h, (aka reg4) 7:6 Reserved 5 1 GO 0-d 4 3 2:0 1 Discharge PGOK (read only) SLEW 0-d 1 0 000 001 010 011-d 100 101 110 111 Writing to this bit starts a VOUT transition regardless of its initial value. The VOUT is ramped to the default VSEL Value. When the regulator is disabled, the output voltage is discharged through the SW pin. When the regulator is disabled, the output voltage Is not discharged. Is high when output is in regulation and VREF has stabilized. Is low during a output voltage transition or when the output is not in regulation. Reserved. Reserved. VOUT slews at 2mv/µs. VOUT Slews at 4mV/µs; this is the default setting. VOUT slews at 8mV/µs. VOUT slews at 16mv/µs. VOUT slews at 32mv/µs. VOUT slews at 64mV/µs. Note: -d is the default value at startup. Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 23 LX7178 3V to 5.5V, 5A Constant Frequency Hysteretic Synchronous Buck Regulator with I2C Production Datasheet Package Dimensions WLCSP 20 Ball 0.4mm Pitch D A2 4 3 2 1 b 20X A B C E1 Ball 1 E D E D1 e A1 MILLIMETERS INCHES Dim MIN MAX MIN MAX A1 0.186 0.226 0.0073 0.0089 A2 0.360 0.400 0.0142 0.0157 b 0.240 0.280 0.0094 0.0110 D1 1.20 BSC 0.0472 BSC D 1.630 0.0642 e 0.40 BSC 0.0157 BSC E1 1.60 BSC 0.0630 BSC E 2.045 0.0805 Note: 1. Solder ball composition SnAgCu PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2014 Rev. 1.1, 8/7/2014 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 24