LX8237
PMIC with E-Fuse and Current Monitoring for
HDD and SSD
Features
Description
The LX8237 integrated power management IC is the
ideal choice for next generation enterprise HDD and
SSD power systems. It consists of 5V and 12V
eFuse over-voltage protection switches and 3.3V
and 0.94V switching regulators.
The 5V and 12V eFuse switches are designed for
hot swap and limit inrush current limiting. In addition,
they provide fast acting protection of voltage surges,
output over current, and crow bar events. Under an
input voltage surge condition, the E-Fuse devices
clamp the output voltage to protect downstream
circuitry and maximize run time. In addition to surge
protection, The 5V eFuse switch provides
bidirectional voltage blocking to block current in the
reverse direction under input voltage crowbar
conditions. Both E-Fuses have thermal protection to
protect all circuitry in the event of sustained surge or
short conditions.
The LX8237 has dual current monitoring outputs to
allow monitoring of the input power under all
conditions.
Both the 5V and 12V inputs are
monitored.
Flexible SATA and SAS disable modes are
supported and can be tailored to a particular system.
Two high performance constant frequency hysteretic
regulators provide ultra-fast regulation, on the fly
output voltage setting, and optimal footprint sizes.
The 3.5A regulator defaults at 0.94V and switches at
2MHz providing minimal output filter size.
The
300mA regulator defaults at 3.3V and switches at
6MHz for ultra-small foot print size. Both outputs
can be adjusted with a high speed I2C serial bus.
They are fully protected against over current and
short circuit conditions.
12V eFuse
- Current Limiting (hot swap inrush, over-load,
short-circuit)
- Output Voltage Clamping and Soft start
- Output Current Monitoring
- Thermal Latch Off
5V eFuse
- Current Limiting (hot swap inrush, over-load,
short-circuit)
- Output Voltage Clamping and Soft-start
- Current Monitoring
- Reverse Current Protection
- Thermal Latch Off
2MHz, 0.94V (default), 3.5A Switching
Regulator
- Soft-start
- Hysteretic control
- Power Save Mode for Light Load Efficiency
- Constant Frequency Operation at Higher
Loads
- Current Limiting (over-load, short-circuit)
6MHz, 3.3V (default), 0.3A Switching
Regulator
- Soft-start
- Hysteretic Control
- Power Save Mode for Light Load Efficiency
- Constant Frequency Operation at Higher
Loads
- Current Limiting (over-load, short-circuit)
- 100% Duty Cycle Capable
Voltage Positioning on 3.3V,0.94V
High-speed (3.4MHz) I²C Serial Bus
Power Disable Support
Applications
Enterprise HDD and SSD
June 2015 Rev. 1.0b
www.microsemi.com
© 2015 Microsemi Corporation
1
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Figure 1 · Typical Application of LX8237
2
Pin Configuration and Pinout
Pin Configuration and Pinout
Figure 2 · Pin out QFN 24L 3.5mm x 4.5mm. (Top View)
Ordering Information
Ambient
Temperature
Type
Package
-40°C to 85°C
RoHS Compliant,
Pb-free
QFN 24L
3.5mm x 4.5mm
Part Number
Packaging Type
LX8237ILQ-TR-V2R3
Tape and Reel
3
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Pin Description
Pin Number
Pin Name
Pin Type
Description
V12OUT
Power Output
12V eFuse output. Clamped at 15V when V12IN goes beyond 15V. The
initial slew rate at this pin is controlled to limit turn-on surge currents.
2
V12IN
Power Input
12V Input.
3
AGND
Power Input
Analog ground. Connect to the board PGND plane at a single point.
4
VR09FB
Analog Input
0.94V output sense input.
5
GND(FSOURCE)
Power Input
Ground. (Internally Reserved for programming eFUSE. 6V power source
pin for programming OTP. After programmed, this pin needs to be
grounded. )
6
VR09EN
Digital Input
Input used to enable VR09 to start/stop.
7
V5IN
Power Input
5V input.
8
P3
Digital Input
SAS P3 PowerDisable. 3.3V CMOS input. Force high to initiate
PowerDisable sequence. Force low to enter active mode.
9
V5OUT
Power Output
10
V5OUTB
Power Input
11
VR09SW
Power Output
12
PGND
Power Input
13
VR33SW
Power Output
Drives the 3.3V output L-C filter.
1
5V input after eFuse 5V output for VR33, VR09, and control.
Drives the 0.94V output L-C filter.
Power Ground.
14
AVDD
Power Output
Output of the internal pre-regulator. This housekeeping voltage will be used
to generate internal bias currents and voltages. It also represents the
voltage that is used for internal IC communication. It will be current limited
with an on-chip resistor to limit turn-on surge current. This pin is not to be
used by external circuitry. A 1µF bypass cap should be placed between
AVDD and AGND.
15
P3FW
Digital Input
Allow firmware to control P3 function when P3FW is connected to AVDD
16
VR33FB
Analog Input
3.3V output sense input. Drives an internal resistive feedback divider.
Digital Output
Power Good pin for 0.9V switching regulator. Open drain output which
requires an external pull-up resistor. PG09 will go high a certion delay (1µs:
deGlitch=1, 200ns: deGlitch=0) after 0.9V outputs is good, it will be low
otherwise. Also used as an internal digital test visibility bus output.
17
PG09
18
PG33
Digital Output
Power Good pin for 3.3V switching regulator. Open drain output which
requires an external pull-up resistor. PG33 will go high a certain delay (1µs:
deGlitch=1, 200ns: deGlitch=0) after 3.3V outputs is good, it will be low
otherwise. Also used as an internal analog test visibility bus output.
19
EF5ON
Digital Output
Open drain ouput. External pull up resistor is required. Logic 1 indicates 5V
eFuse FET is closed.
Digital In/Out
I²C data port. External pull up resistor is required. 1.8V CMOS logic levels.
The power supply for the external pull up resistors is assumed to be at 1.8V,
but the sequencing of this supply can occur at any time before, during or
after powering of the LX8237 5V or 12V input. If this power supply drops
below 1.8V logic level thresholds tolerance value (+/-10%), then I²C
communication may be interrupted. The default register value loading of all
I²C registers (customer and test) should be independent on the SDA state.
20
4
Bi-directionally protected 5V output. Clamped at 6V. The initial slew rate at
this pin is controlled to limit turn-on surge currents.
SDA
Pin Description
Pin Number
Pin Name
Pin Type
Description
21
SCL
Digital Input
I²C clock port. External pull up resistor is required. 1.8V CMOS logic levels.
The power supply for the external pull up resistors is assumed to be at 1.8V,
but the sequencing of this supply can occur at any time before, during or
after powering of the LX8237 5V or 12V input. If this power supply drops
below 1.8V logic level thresholds tolerance value (+/-10%), then I²C
communication may be interrupted. The default register value loading of all
I²C registers (customer and test) should be independent on the SCL state.
22
SINTN
Digital Output
General purpose interrupt output. External pull up resistor is required. Logic
0 to indicate interrupt.
23
I5SNS
Analog Output
5V eFuse output current monitor. Connect to an external parallel R-C filter
network. These component values will be adjusted when the final gain of
the current monitor is determined.
24
I12SNS
Analog Output
12V eFuse output current monitor. Connect to an external parallel R-C filter
network. These component values will be adjusted when the final gain of
the current monitor is determined.
25*
PGND
Power Ground
Power Ground. Connected to back side thermal pad.
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PMIC with E-Fuse and Current Monitoring for HDD and SSD
V12OUT
Block Diagram
E-Fuse
12V and 5V
Current monitor
V12IN
(Convert I to V)
I12SNS
I5SNS
VREF
VOUT Clamp
UVLO
Over Current
Thermal
Memory
V5OUTB
P3
Power Lines control
Hys. Control
VR33SW
DAC
VR33FB
Current Limit
P3FW
VOUT Clamp
UVLO
Over Current
Thermal
PG33
VR09SW
VR09FB
VR09EN
PG09
V5IN
I/O Logic
SCL
SDA
SINTN
EF5ON
V5OUT
E-Fuse
Figure 3 · Simplified Block Diagram of LX8237
6
Absolute Maximum Ratings
Absolute Maximum Ratings
Min
Max
Units
V12IN
-0.3
25
V
V5IN, V12OUT
-0.3
15
V
V12OUT Current
3.5
A
V5OUT Current
P3, P3FW, V5OUT, SINTN, SDA, SCL, PG09, VR09EN, VR09FB,
VR09SW, PG33, VR33FB VR33SW, V5OUTB, I5SNS, I12SNS, AVDD,
EF5ON
Junction Temperature
3.5
A
-0.3
6.5
V
-10
150
°C
Parameter
Storage Temperature
-65
150
°C
260+0,-5
°C
ESD (Human Body Model)
2000
V
ESD (Charged Device Model)
500
V
Peak Solder Reflow Temperature (40 seconds)
Note: Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only.
Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating
reliability
Operating Ratings
Min
V12IN Voltage
Typ
10.8
V12OUT Continous Current
Max
Units
13.2
V
2.5
A
V5IN Voltage
4.3
5.5
V
V5OUT Voltage
2.5
5.5
V
2.5
A
V5OUT Continous Current
Serial I/F Voltage
1.7
1.8
1.95
V
P3 Input Voltage
-0.3
3.3
3.6
V
P3FW Input Voltage
-0.3
1.1*AVDD
V
Junction Temperature
-10
125
°C
Ambient Temperature
-10
85
°C
Note: Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics.
Thermal Properties
Thermal Resistance
θJA
Typ
Units
40
°C/W
Note: The JA numbers assume no forced airflow. Junction Temperature is calculated using TJ = TA + (PD x JA). In
particular, θJA is a function of the PCB construction. The stated number above is for a four-layer board in accordance
with JESD-51 (JEDEC).
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PMIC with E-Fuse and Current Monitoring for HDD and SSD
Electrical Characteristics
Note: Unless otherwise specified, the following specifications apply over the operating ambient temperature of -40C TA 85C.
Except where otherwise noted, the following test conditions apply: V12IN=12V, V5IN=5V, LX1=1 µH, COUT1=22µF,
LX2=0.47µH, COUT2=44µF, COUT12=3*22µF, COUT5 = 3*22µF. Typical parameters refers to TA=25°C
Symbol
Parameters
Test Conditions/Comments
Ibias1
Biasing current 1
Ibias2
Min
Typ
Max
Units
V5IN CURRENT, P3 LOW, VR09EN HIGH,
VR33FB=5V @ V12IN=12V, V5IN=5V
0.4
1
mA
Biasing current 2
V5IN CURRENT, P3 LOW, VR09EN LOW,
VR33FB=5V @ V12IN=12V, V5IN=5V
0.4
1
mA
Ibias3
Biasing current 3
V5IN CURRENT, P3 HIGH, VR09EN LOW,
VR33FB=5V @ V12IN=12V, V5IN=5V
0.4
1
mA
Ibias4
Biasing current 4
V12IN CURRENT, P3 LOW, VR09EN HIGH,
VR33FB=5V @ V12IN=12V, V5IN=5V
0.4
1
mA
Ibias5
Biasing current 5
V12IN CURRENT P3 HIGH @ V12IN=12V,
V5IN=5V
0.4
1
mA
Device
12V eFuse FET
I_inrush_12 Inrush Current
Rdson_12
On Resistance
Inrush current during the hot-swap condition.
Measure the input current into V12IN in the
transient of VCC from 0V to 12V at the slewrate
of 12V/20ns.
1.5
TJ=25°C, 200mA through V12IN to
V12OUT(Note 2)
A
50
m
TJ=125°C, 200mA through V12IN to
V12OUT(Note 1)
95
Off state leakage
current
4
µA
Idc_12
Continuous Current
TA=25°C(Note 1)
2.5
A
Trise_12
Vout ramp time
Measure 10% to 90% rise time at V12OUT
Initiate the ramp by setting P3 low.
10
ms
Tdly_12
Turn on delay
Measure delay from the falling edge of P3 to
the 10% point at V12OUT.
1.3
ms
Vclamp_12
Output Clamping
Voltage
V12IN=18V, dc test, no load. Measure
V12OUT.
13.8
Increase V12IN from 12V to 24V in 12V/100ns.
Maximum overshoot
Monitor the maximum excursion at V12OUT
in the transient
with no load.
Isc_lim_12
8
14.98
V
15
V
UVLO falling
threshold
Decrease V12IN. Observe when V12OUT with
some load falls below V12IN by 100mV.
8.8
9
9.24
V
UVLO rising
hysteresis
Increase V12IN. Observe when V12OUT turns
on.
0.6
0.7
0.8
V
Short circuit current
limit
V12OUT < 1.5V. Force V12OUT to 0V,
measure I(V12OUT).
1
1.5
A
Electrical Characteristics
Symbol
Iavg_lim_12
Parameters
Test Conditions/Comments
Overloading current
limit
Force V12OUT to 0.5V less than
V12IN,measure I(V12OUT).
Current monitor
output current gain
Current monitor
error
Min
Typ
Max
Units
3
4
5
A
Imon/IeFuse, ImonG=0. Test at 200mA and
300mA.
232.8
240
247.2
Imon/IeFuse, ImonG=1. Test at 200mA and
300mA.
465.6
480
494.4
2
3
%
1.5
A
uA/A
I(eFuse12) = 200mA, Imon/IeFuse. ImonG=1.
Calculate error vs. ideal value.
5V eFuse FET
I_inrush_5
Rdson_5
Inrush Current
On Resistance
Inrush current during the hot-swap condition.
Measure the input current into V5IN in the
transient of VCC from 0V to 5V at the slewrate
of 5V/10ns.
TJ=25°C, 200mA through V5IN to V5OUT(Note
2)
50
m
TJ=125°C, 200mA through V5IN to
V5OUT(Note 1)
95
Off state leakage
current
9
µA
Idc_5
Continuous Current
TA=25°C(Note 1)
2.5
A
Trise_5
Vout ramp time
Measure 10% to 90% rise time at V5OUT
Initiate the ramp by setting P3 low.
10
ms
Tdly_5
Turn on delay
Measure delay from the falling edge of P3 to
the 10% point at V5OUT.
2.2
ms
Vclamp_5
Output Clamping
Voltage
V5IN=10V, dc test, no load. Measure V5OUT.
5.7
6
Increase V5IN from 5V to 12V in 70nS (5V/µS).
Maximum overshoot
Monitor the maximum excursion at V5OUT with
in the transient
no load.
6.3
V
6.5
V
UVLO falling
threshold
Decrease V5IN. Observe when V5OUT with
some load begins to fall.
4.0
4.1
4.2
V
UVLO rising
threshold
Increase V5IN. Observe when V5OUT turns
on.
4.25
4.35
4.45
V
Isc_lim_5
Short circuit current
limit
V5OUT < 1.5V. Force 0V at V5OUT measure
I(V5OUT).
1
1.5
A
Iavg_lim_5
Overloading current
limit
Force V5OUT to 0.5V less than V5IN, measure
I(V5OUT)
4
5
A
AVDD UVLO rising
This is the point that the 12v E-fuse turns on
when 5voutb is rising
2.79
3.2
V
AVDD UVLO falling
This is the point that the 12V E-fuse turns off
when 5OUT5B is lowered
2.17
2.35
V
V5OUTB UVLO
rising
This is where the 3.3V and 0.94 regulators turn
off. The SINT pins also in disabled (see the
fault condition table)
3.85
4.13
V
V5OUTB UVLO
faling
This is where the 3.3V and 0.94V regulators
turn off. The SINT pins also in disabled (see
1.92
3.38
V
3
9
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Symbol
Parameters
Test Conditions/Comments
Min
Typ
Max
Imon/IeFuse, ImonG=0. Test at 200mA and
300mA.
242.5
250
257.5
Imon/IeFuse, ImonG=1. Test at 200mA and
300mA.
485
500
515
2
3
Units
the fault condition table)
Current monitor
output current gain
µA/A
Current monitor
error
I(eFuse5) = 200mA, Imon/IeFuse
Reverse current
voltage threshold
Force V5OUT above V5IN. Monitor the
comparator output. Determine the rising and
falling thresholds.
-35
mV
Reverse current
voltage hysteresis
See test above.
15
mV
%
0.94V Switching Regulator
0.94V regulator
Input Range
HSrdson_9
PFET resistance
LSrdson_9 NFET resistance
Idc_9
Continuous DC out
current
The core blocks of 0.94V Switching Regulator
needs to be operational in this condition. The
0.94V regulator will not be enabled until VDD5
has cleared its UVLO threshold and V5OUT has
finished rising. (Note 1)
2.5
5.5
TJ=25°C, sink -0.5A at VR09SW at
V5OUTB=5V(Note 2)
65
TJ=125°C, sink -0.5A at VR09SW at
V5OUTB=5V(Note 1)
90
TJ=125°C, sink -0.5A at VR09SW at
V5OUTB=3V(Note 1)
135
TJ=25°C, source 0.5A at VR09SW at
V5OUTB=5V(Note 2)
18
TJ=125°C, source 0.5A at VR09SW at
V5OUTB=5V(Note 1)
30
TJ=125°C, source 0.5A at VR09SW at
V5OUTB=3V(Note 1)
40
TA=25°C
3.5
Peak Current Limit
6.4
7.1
Overcurrent –Limit
Toff Time
m
m
A
7.8
A
605
ns
PWM only, no load. Code 000000
770
PWM only, no load. Code 111111
1085
Output voltage
accuracy
PWM only, no load. Measure at 0.94V output.
+/-1
DC output voltage
step size
(Note 1)
5
mV
Measure 10% to 90% rise time at 0.94V output
Initiate the ramp by enabling the regulator via
VR09EN.
1
ms
DC output voltage
Tsoftstart_
Soft start time
9
10
V
mV
+/-1.5
%
Electrical Characteristics
Symbol
Parameters
Test Conditions/Comments
Min
VR09EN rising
threshold
Increase voltage at VR09EN.
0.6
VR09EN falling
threshold Hysterisis
Force 1.8V at VR09EN.
PG09 active voltage
Force the FB pin in open loop. Measure when
the PG09 pin pulls low.
PG09 logic 0 active
output voltage
-17
1
V
-10
mV
1
uA
-8
%
300
ns
Register DEGLITCH=1
1.2
µs
ISINK=1mA
Hiccup time
FBUVLO hiccup time. Force FB to 60%,
monitor the SW pin for high and Hi-Z conditions
Voltage output
transient due to
step transient
current
ILOAD Slew-rate: 1.6A/1µs from 0.8A to 2.4A
Switching
Frequency
PWM only, no load.
Efficiency
3V < V5OUTB < 5.5V,
Iload = 0.5A to 2A
DCM to CCM
Change Point
Units
Register DEGLITCH=0
400
PG09 logic 1 inTpgdelay_
active output
9
voltage delay
CCM to DCM
Change Point
Max
100
VR09EN input bias
current
PG09 deglitch filter
Typ
1.6
mV
1
ms
8.5
ms
2
47
mV
2.4
MHz
90
%
600
Sweep the load current.
0A -> 1500mA -> 0A.
mA
1000
3.3V Switching Regulator
3.3V regulator
Input Range
HSrdson_3
PFET resistance
LSrdson_3 NFET resistance
(Note 1)
2.5
5.5
TJ=25°C, V5OUTB=5V, sink -0.2A at
VR33SW(Note 2)
290
TJ=125°C, V5OUTB=5V, sink -0.2A at
VR33SW(Note 1)
350
TJ=125°C, V5OUTB=3V, sink -0.2A at
VR33SW(Note 1)
500
TJ=25°C, V5OUTB=5V, source 0.2A at
VR33SW(Note 2)
440
TJ=125°C, V5OUTB=5V, source 0.2A at
VR33SW(Note 1)
640
TJ=125°C, V5OUTB=3V, source 0.2A at
VR33SW(Note 1)
900
V
m
m
11
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Symbol
Parameters
Test Conditions/Comments
Idc_3
Continuous DC
current
TA=25°C(Note 1)
Peak Current Limit
Min
Typ
Max
300
0.75
1.25
Units
mA
1.75
A
PWM only, no load. Code 000000
2540
PWM only, no load. Code 111111
3780
Output voltage
accuracy
PWM only, no load. Measure at 3.3V output.
+/-1
DC output voltage
step size
(Note 1)
VR33FB voltage
range
(Note 1)
V5OUTB to enable
VR33 to start-up
Increase V5OUTB, measure when VR33 starts
up.
4
V
Measure 10% to 90% rise time at 3.3V output
Initiate the ramp by forcing V5OUTB to 5V.
1
ms
DC output voltage
Tsoftstart_
Soft start time
3
PG33 active voltage
PG33 deglitch filter
PG33 logic 0 active
output voltage
Force the FB pin in open loop. Measure when
the PG09 pin pulls low.
mV
+/-1.5
40
mV
V5OUTB
-14
-10
%
-8
V
%
Register DEGLITCH=0
230
ns
Register DEGLITCH=1
1.4
µs
Isink=1mA
400
PG33 logic 1 inTpgdelay_
active output
3
voltage delay
1
mV
ms
Voltage output
transient due to
step transient
current
ILOAD Slew-rate: 1.6A/1µs from 0.15A to 0.35A
Switching
Frequency
PWM only.
6
MHz
Efficiency
3V < V5OUTB < 5.5V,
Iload = 0.1A to 0.3A
90
%
DCM to CCM
Change Point
CCM to DCM
Change Point
Cooling Time
165
mV
100
Sweep the load current.
0A -> 300mA -> 0A.
mA
95
FBUVLO hiccup time. Force FB to 60%,
monitor the SW pin for high and Hi-Z
conditions. Will probably need a pull down
resistor at SW.
10
ms
Temperature Monitor
EOTW
12
Early over
temperature
warning
140
155
170
°C
Electrical Characteristics
Symbol
Parameters
Test Conditions/Comments
Min
Typ
Max
Units
OTth
Over Temperature
Threshold
Sweep temperature. 5V and 12V eFuse have
their own thermal shutdown circuit. They should
be separately characterized.
160
175
190
°C
OThy
Over temperature
hysteresis
EN/FAULT pin is driven by the other eFuse.
Thermal Fault, Output Disabled,
Tdelta
Temperature
difference from
EOTW to OTth
Output Enabled
15
20
25
°C
V(P3) < VP3th: Power Enable
V(P3) > VP3th: Power Disable
Use the digital XOR test mode output
1.2
1.6
2.0
V
P3 logic falling
threshold hystresys
200
300
400
mV
P3 pull-down
resistor
60
100
140
k
1.2
1.6
2.0
V
200
300
400
mV
0.4
V
2
µA
0.4
V
2
uA
VR33FB
V
400
mV
VR33FB
V
50
°C
P3 and P3FW
VP3th
VP3FWth
P3 logic rising
threshold
P3FW logic rising
threshold
V(P3FW) < VP3FWth: P3EN Register Bit
Control throughI2C is disabled.
V(P3FW) > VP3FWth: P3EN Register Bit
Control throughI2C is enabled.
Use the digital XOR test mode output.
P3FW logic
threshold hystresys
SINTN
Output Low Voltage
ISINK(SINTN)=1mA
Output High
Leakage Current
Set SINTN off, force 1.8V at SINTN, measure
the leakage current.
Output Low Voltage
ISINK(EF5ON)=1mA
Output High
Leakage Current
Set EF5ON off, force 1.8V at EF5ON, measure
the leakage current.
EF5ON max output
voltage
EF5ON is pulled up to VR33FB through a
external resistor. (Note 1)
EF5ON logic 0
output voltage
Isink = 1mA
EF5ON
-300
EF5ON max output
voltage
3
EF5ON comparator
deglitch filter
500
ns
I²C
IQ_OP
Vol-SDA
I=4mA(Note 1)
VMIN
VDD for I²C
interface
Input condition(Note 1)
1.7
Vil
Logic0 input voltage(Note 1)
-0.5
1.8
0.4
V
1.95
V
0.3*VDD
V
13
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Symbol
Parameters
Test Conditions/Comments
Min
Vih
Logic1 input voltage(Note 1)
0.7*VDD
Vihyst
Input hysteresis(Note 1)
0.1*VDD
Iin
Input current, Vi=0.1*VDD to 0.9*VDD (Note 1)
Vol
Typ
Max
Units
VDD+0.5
V
V
-10
10
µA
Logic0 output voltage, Isink=2mA(Note 1)
0
0.2*VDD
V
Iol
Vol=0.4V(Note 1)
3
Input voltage
deglitch
(Note 1)
0
10
ns
SCL clock
frequency
(Note 1)
0
3.4
MHz
tsu, start/stop
Setup time(Note 1)
160
ns
thold, start/stop
Hold time(Note 1)
160
ns
tlow, SCL
low pulse time(Note 1)
160
ns
thi, SCL
high pulse time(Note 1)
60
ns
tsu, SDA
data setup time(Note 1)
10
ns
thold, SDA
data hold time(Note 1)
0
70
ns
trise, tfall, SCL
clock rise/fall time(Note 1,3,4)
10
1000
ns
trise, tfall, SDA
data rise/fall time(Note 1,3,4)
10
1000
ns
mA
Note: 1. Guaranteed by Design
Note: 2. Pulse test: Pulse width = 300µs, Duty cycle = 2%.
Note: 3. The signal must be compliant to the characteristic of standard I2C bus. LX8237 is compatible with “Normal/Fast/Fast
Plus/High Speed” mode
Note: 4. To achieve the faster rising time, users may need to adjust the pull up resistor value.
14
Theory of Operation / Application Information
Theory of Operation / Application Information
12V eFuse
The 12V eFuse block functions as follows: The 12V eFuse is initially on its off state. The ON/OFF control of
the eFuse is base on the input pins V12IN, P3, P3FW, P3En bit and fault conditions. See application details
section for the complete control functions. After the eFuse is allowed to turn on, it then ramps the output
voltage to its final value while at the same time limit the max current to the current limit value. If the input
continues to rise above the OV12 threshold, the eFuse will limit the output to the OV12limit and set the OV12
bit in the serial port. The 12V eFuse will operate in this state until it hits its OT limit and shuts down. The
eFuse will restart after temperature is below the OT hystereis value.The 12V eFuse block also has an output
current monitor. The current monitor output current is proportional to the current of the 12V eFuse from input
to output.
The 12v E-Fuse will limit current to the current limit level. If the output voltage drops low enough, a short is
detected and the current limit is reduced even further. If the short circuit is removed before an over
temperature event occurs, the current limit level will remain at the short circuit current limit level until all the
faults in the I2C registers are cleared by writing to the status register. This will ensure that the output voltage
rise rate is limited to the short circuit current level.
5V eFuse
The 5V eFuse block functions as follows: The 5V eFuse is initially on its off state. The ON/OFF control of the
eFuse is base on the input pins V5IN, P3, P3FW, P3En bit and fault conditions. See application details section
for the complete control functions. After the eFuse is allowed to turn on, it then ramps the output voltage to its
final value while at the same time limit the max current to the current limit value. If the input continues to rise
above the OV5 threshold, the chip will limit the output to the OV5limit and set the OV5 bit in the serial port.
The 5V eFuse will operate in this state until it hits its OT limit and shuts down. The eFuse will restart after
temperature is below the OT hystereis value. When the current goes in the reverse direction above the
threshold, the eFuse will open and isolate the output from the input. The eFuse will restart with current limit
once the reverse current goes to zero AND the input has satisfied the normal startup criteria. The 5V eFuse
block has an output current monitor. The current monitor output current is proportional to the current of the 5V
eFuse from input to output. The 5V Efuse block has a logic output at EF5on open drain pin to indicate when
the eFuse is in its open protective state.
The 5v E-Fuse will limit current to the current limit level. If the output voltage drops low enough, a short is
detected and the current limit is reduced even further. If the short circuit is removed before an over
temperature event occurs, the current limit level will remain at the short circuit current limit level until the 3.3v
Power Good is OK. This will ensure that the output voltage rise rate is limited to the short circuit current level.
eFuse Current Monitor Function
The average current being supplied by each eFuse output can be monitored at I5SNS and I12SNS. A current
proportional to the average eFuse output current will be sourced out of the sense pins. This current will be
converted to a voltage and filtered by a parallel R-C network connect at I5SNS and I12SNS pins.
By default, the current monitors are disabled. They are enabled via the serial port. Any fault that turns off
either the eFuses or the regulators will turn off the current monitor by reseting IMON bits as well. The current
monitors have two different gain selections to allow for better resolution at different current ranges.
15
PMIC with E-Fuse and Current Monitoring for HDD and SSD
094V Switching Regulator
The VR09 regulator is a fully integrated switching regulator. This regulator features adjustable output
voltage with power monitor and over current protection. Whenever the output is 10% below the
programmed target output voltage, the PG09 pin is pulled low to indicate a fault. The regulator starts when
VR09En goes high and turns off when VR09En goes low. When VR09En is low, the VR09Dis and
VR09MonDis bits are automatically reset.
Firmware can disable VR09 when VR09En is high as follows:
1. Set the VR09Key bit to allow the VR09Dis/VR09MonDis bits to be programmed.
2. Set VR09MonDis and VR09Dis as desired. When VR09MonDis is set, the state of the PG09 pin is held
steady at the previous value, independent of the actual VR09 output voltage. When VR09Dis is set,
VR09 is shut off.
3. VR09Key will automatically reset when any register other than 03H is written. This two step
programming approach prevents accidentally disabling VR09 through firmware since the VR09MonDis
and VR09Dis bits cannot be changed when VR09Key is reset.
4. Setting VR09Key and then resetting VR09Dis will restart VR09. At the end of the soft start period
(rising edge-sensitive), VR09MonDis will automatically reset to re-enable PG09. This allows VR09 to
be shut off without disturbing the PG09 pin.
These tables specify the functionality of the VR09Key, VR09Dis, and VR09MonDis bits:
0V9KEY
0
16
1
Function
0V9Dis and 0V9MonDis bits cannot be changed via the serial interface. This bit is
automatically reset when any register other than 03H is written.
0V9Dis and 0V9MonDis bits can be changed via the serial interface.
0V9Dis
0
1
Function
VR09 is controlled by the VR09En pin.
Shut off VR09. This bit is automatically reset whenever VR09En (pin) is set low.
0V9MonDis
0
1
Function
Allows the PG09 pin to monitor the status of the VR09 output.
Hold the PG09 state at whatever value it was at when this bit was set. This bit is
automatically reset whenever VR09En (pin) is set low. It is also reset at the end of
the soft start ramp up period.
Theory of Operation / Application Information
This table shows how the VR09 output is controlled by the 0V9SEL bits. The default setting of 100010
gives an output of 0.94V.
0V9SEL
000 000
000 001
000 010
000 011
000 100
000 101
000 110
000 111
001 000
001 001
001 010
001 011
001 100
001 101
001 110
001 111
VR09 (V)
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
0.825
0.830
0.835
0.840
0.845
0V9SEL
010 000
010 001
010 010
010 011
010 100
010 101
010 110
010 111
011 000
011 001
011 010
011 011
011 100
011 101
011 110
011 111
VR09 (V)
0.850
0.855
0.860
0.865
0.870
0.875
0.880
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0V9SEL
100 000
100 001
100 010
100 011
100 100
100 101
100 110
100 111
101 000
101 001
101 010
101 011
101 100
101 101
101 110
101 111
VR09 (V)
0.930
0.935
0.940
0.945
0.950
0.955
0.960
0.965
0.970
0.975
0.980
0.985
0.990
0.995
1.000
1.005
0V9SEL
110 000
110 001
110 010
110 011
110 100
110 101
110 110
110 111
111 000
111 001
111 010
111 011
111 100
111 101
111 110
111 111
VR09 (V)
1.010
1.015
1.020
1.025
1.030
1.035
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
3.3V Switching Regulator
The VR33 regulator is a fully integrated switching regulator. This regulator features adjustable output
voltage with power monitor and over current protection. Whenever the output is 10% below the
programmed target output voltage, the PG is triggered and the VR33FLT bit is set along with the PG33 pin
pulled low to indicate a
failure.This regulator starts when 5VoutB is crosses the start regulator threshold. It will stop when 5VoutB
is below its min supply for proper operation. The start/stop thresholds are different.
This table shows how the VR33 output is controlled by the 3V3SEL bits. The default setting of 10011 gives
an output of 3.3V.
3V3SEL
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
VR33 (V)
2.54
2.58
2.62
2.66
2.70
2.74
2.78
2.82
3V3SEL
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
VR33 (V)
2.86
2.90
2.94
2.98
3.02
3.06
3.10
3.14
3V3SEL
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
VR33 (V)
3.18
3.22
3.26
3.30
3.34
3.38
3.42
3.46
3V3SEL
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
VR33 (V)
3.50
3.54
3.58
3.62
3.66
3.70
3.74
3.78
17
PMIC with E-Fuse and Current Monitoring for HDD and SSD
I2C Serial Interface
The chips sports a high speed (3.4MHz) serial interface with the I²C serial protocol. This interface is bidirectional allowing the microprocessor to set functions and read status. Status0/1 register bits are latched
once the first fault happens. In this case, the following fault cannot write the register anymore. Cleared by
write action to the status register.
I2C Slave Address:
The Slave Address for the LX8237 is 01101110 or 6EH.
Serial Bus Register Map
Address
Dec Hex
0
00H
1
01H
2
02H
3
03H
4
04H
5
05H
6
06H
ID1
Read-Only
ID2
Read-Only
0V9VSEL
Read/Write
3V3VSEL
Read/Write
CONTROL0
Read/Write
STATUS0
Read/Write
STATUS1
Read/Write
Bit 7
DEV[1]
0
VID[3]
0
N/A
0
N/A
0
P3EN
0
UV12
0
OC12
0
Bit 6
DEV[0]
1
VID[2]
0
N/A
0
N/A
0
IMONG
0
UV5
0
OC5
0
Bit 5
MID[2]
0
VID[1]
0
0V9SEL[5]
1
0V9KEY
0
VR33PWM
0
UV33
0
OC33
0
Bit 4
MID[1]
1
VID[0]
0
0V9SEL[4]
0
3V3SEL[4]
1
VR09PWM
0
UV09
0
OC09
0
Bit 3
MID[0]
0
FAB[1]
0
0V9SEL[3]
0
3V3SEL[3]
0
DEGLITCH
0
OT12
0
P3STATE
0
Bit 2
NID[2]
0
FAB[0]
0
0V9SEL[2]
0
3V3SEL[2]
0
IMONEN
0
OT5
0
N/A
0
ID1 and ID2:
DEV = Device [01]
MID= major ID [010]: Mask revisions (includes pizza versions)
NID= minor ID [000]
VID= Device [0000]: device pizza version. (ver 1 = 0000, ver 2 = 0001, ver 3 = 0010, etc)
FAB= Fab [00] :
SID= VendorID [00]
Device
ID1
ID2
LX8237ILQ-TR-V2R3
x53 [0101 0011]
X00 [ 0000 0000]
0V9Sel= VR09 output voltage select
3V3Sel= VR33 output voltage select
VR33PWM= Force VR33 to operate in PWM mode only
VR09PWM= ForceVR09 to operate in PWM mode only
DEGLITCH= deglitch time selection for Fault/POR detection.
IMONEN= eFuse current monitor Enable.
IMONG= Current Monitor Gain
0V9MONDIS= VR09 regulator monitoring Disable (OFF).
0V9DIS= VR09 regulator Disable (OFF).
P3EN= P3 PowerDisable feature enable.
UV12 = 12V input voltage under voltage
UV5= 5V input voltage under voltage
UV33= VR33 output voltage under voltage.
UV09= VR09 output voltage under voltage.
OT12= eFuse12 over temperature
18
Bit 1
NID[1]
1
SID[1]
0
0V9SEL[1]
1
3V3SEL[1]
1
0V9MONDIS
0
EOTW12
0
OV12
0
Bit 0
NID[0]
1
SID[0]
0
0V9SEL[0]
0
3V3SEL[0]
1
0V9DIS
0
EOTW5
0
OV5
0
Theory of Operation / Application Information
OT5= eFuse5 over temperature
EOTW12= eFuse12 early temperature warning
EOTW5= eFuse5 early temperature warning
OC12 = eFuse12 over current
OC5 = 3Fuse5 over current
OC33 = VR33 output over current
OC09 = VR09 output over current
P3State = P3 pin state
OV12 = eFuse12 input over voltage
OV5= eFuse5 input over voltage
0V9KEY= key to enable 0.94V moniotor & regulator disable.
19
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Power On and Off Sequence
The Yosemite chip is powered from either the VCC5 input or Vout5 depending on its mode of operation. On
startup, eFuse12 will wait for VCC5 to come up before it can close. As long as VCC5 input is present,
eFuse12 will close and open with VCC12 input above or below its EF12 close/open threshold. If VCC5in
input fails, eFuse12 will open in addition to eFuse5 being open from loss of 5V input.
However, eFuse5 can start up only with VCC5 input present.
The Power on sequence for the system is as follows:
1. VCC5 power up and goes above the required operating voltage for the system.
2. The eFuse5 starts ramping its output.
3. Upon 5Vout crossing the regulator minimum operating voltage for turn ON, the VR33 starts up.
4. After VR33 output crosses PG detection threshold, VR33PG signal goes to logic1 1ms after the last time
that VR33 is above its target have stabilized.
5. VR09 starts up after VR09EN pin is at logic1 state
6. VR09 output crosses VR09PGth and outputs V09PG signal to logic1 1ms after the last time VR09 output
is above its target.
7. Efuse12 starts to ramp AFTER both VCC5 AND VCC12 are good. If either input fails, its respective
EF5/EF12 is open.
Reverse Current Control of 5V eFuse
The simplest protection against to the reverse current is a diode in series connection to the load. However,
the power loss is significant at the forward current mode. At the worst, the supply rail of the load is not
regulated. In order to solve this problem, the body gating technique is implemented for LX8233. The basic
concept on this method is to detect the polarity of voltage drop through the pass N-type FET. Once the
negative voltage drop is detected, an active switch connects the body of the pass FET from the source to
drain. It generates the opposite polarity of body diode to block the reverse current.
20
Theory of Operation / Application Information
Microsemi’s approach to protect the discharging from the output capacitor is to utilize the combination of
two methods. One method is to detect the voltage drop over the Rdson of an eFuse FET. The othere is to
use the accurate input UVLO circuit.
The Rdson sensing is responsible for the high dv/dt input drop like crawbar response (max -5V/µs). 33mV
threshold is assigned to detect the reverse voltage from VCC to VOUT through 50mIt represents 660mA
reverse current to discharge the output capacitor through eFuse. Any reverse current higher than 660mA
by the high dv/dt will be shut off by Rdson sensing circuit.
The slow dv/dt input won’t be detected by Rdson sensing circuit since the reverse current is lower than
660mA. The input with slow dv/dt will rely on UVLO detection. Once V5IN goes lower than the UVLO
threshold, UVLO circuit will open an eFuse. It requires the accurate threshold( L
Open
Closed
Enable
Enable
UV5
H
H
H => L
Closed
Closed
(V12OUT
Clamp)
Enable
Enable
OV12
H
H
H => L
Closed
(V5OUT
Clamp)
Closed
Enable
Enable
OV5
H
H
H => L
Closed
Enable
(I12OUT
Limit)
Enable
Enable
OC12
H
H
H => L
Enable
(I5OUT
Limit)
Closed
Enable
Enable
OC5
This fault asserts when V12OUT clamping occurs.
V12IN over
voltage
This fault asserts when V5OUT clamping occurs.
V5IN over
voltage
V12OUT
Over
Current
(delay filter
~1.024ms)
This fault asserts when current limit occurs at 12V
eFuse FET.
V5OUT
Over
Current
(delay filter
~1.024ms)
This fault asserts when current limit occurs at 5V
eFuse FET.
0.9V Reg
under
voltage
This fault asserts when V09OUT is lower than 90% of
the target voltage.
H => L
H
H => L
Closed
Closed
Enable
(Recovery)
Enable
UV09
3.3V Reg
under
voltage
This fault asserts when V33OUT is lower than 90% of
the target voltage.
H
H =>L
H => L
Closed
Closed
Enable
Enable
(Recovery)
UV33
0.9V Reg
Output
Short
This fault VR09OUT is lower than 70% and current
limit occurs.
H => L
H
H => L
Closed
Closed
Enable
(Hiccup)
Enable
UV09
3.3V Reg
Output
Short
This fault VR33OUT is lower than 70% and current
limit occurs.
H
H => L
H => L
Closed
Closed
Enable
Enable
(Hiccup)
UV33
0.9V Reg
Over
current
(delay
~32us)
This fault asserts when the measure current peak hits
the current limit. This fault pulls SINTn low but allow
the other fault condition to write the fault register
instead of locking up the register not to allow since this
fault often occurs at the transient.
H
H
H => L
Closed
Closed
Enable
(Iout Limit)
Enable
0V90C
3.3V Reg
Over
current
(delay
~32µs)
This fault asserts when the measure current peak hits
the current limit. This fault pulls SINTn low but allow
the other fault condition to write the fault register
instead of locking up the register not to allow since this
fault often occurs at the transient
H
H
H => L
Closed
Closed
Enable
5V Early
Over
Temperatu
re Warning
(delay
~32µs)
This fault asserts when 5V eFuse temperature cross
the EOTW threshold.
H
H
H => L
Closed
Closed
Enable
Enable
EOTW
5
12V Early
Over
Temperatu
re Warning
(delay
~32µs)
This fault asserts when 12V eFuse temperature cross
the EOTW threshold.
H
H
H => L
Closed
Closed
Enable
Enable
EOTW
12
5V Over
Temperature
This fault asserts when temperature cross the OT
threshold.
H
H
H => L
Open
Closed
Enable
24
Enable
3V3OC
(Iout Limit)
Enable
OT5
I²C SCL and SDA pin requirements
12V Over
Temperatu
re
This fault asserts when temperature cross the OT
threshold
H
H
H => L
Closed
Open
Enable
Enable
OT12
V5OUTB
Under
Voltage
-
-
H => L
Open
Open
Disable
Disable
-
VR09EN
input
voltage low
-
-
H
Closed
Closed
Disable
Enable
-
P3 Pin
Logic 1
(feature
enabled)
-
-
H => L
Open
Open
-
-
P3STA
TE
I²C SCL and SDA pin requirements
Ideal Specification:
The power supply for the external pull up resistors attached to the SCL and SDA pins is assumed to be at
1.8 us, but the sequencing relative to the internal digital block power supply can occur at any time before
or during startup or power down or any time in between. If the power supply drops below 1.8v logic level
thresholds tolerance value (-10%), then I²C communication can be interrupted. The default register value
loading of all I²C registers (customer and test) should be independent on the SCL/SDA state since this is
not known.
25
PMIC with E-Fuse and Current Monitoring for HDD and SSD
Package Marking Description
•
MSC X
8237
FA
YYWWL
26
Device Marking
Description
•
Pin 1 Indicator
MSC
Microsemi Corporation
X
For production parts, X=”N” . All other values of X represent pre-production parts.
8237
Supplier Part Number
F
Wafer Fab Location
A
Assembly Location
YY
Year
WW
Work Week
L
Lot Trace Code
Package Outline Dimensions
Package Outline Dimensions
Figure 4 · 24-Pin QFN Package Dimensions
Land Pattern Recommendation
3.50mm
0.35mm
0.25mm
1.40
mm
4.50mm
0.90mm
0.50mm
1.30
mm
0.90mm
0.125mm
0.80mm
Figure 5 · 24-Pin QFN Package Land Pattern
Disclaimer:
This PCB land pattern recommendation is based on information available to Microsemi by its suppliers. The actual land pattern to be used could be different depending on the
materials and processes used in the PCB assembly, end user must account for this in their final layout. Microsemi makes no warranty or representation of performance based
on this recommended land patter
27
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world’s standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: sales.support@microsemi.com
© 2015 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
LX8237-1.0b/06.15
工商网监
湘ICP备2023018690号
