Revision 27
DS0095
IGLOO Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
High Capacity
• 15K to 1 Million System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM®-enabled IGLOO® devices) via
JTAG (IEEE 1532–compliant)†
• FlashLock® Designed to Secure FPGA Contents
High-Performance Routing Hierarchy
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
UC/CS
QFN
VQFP
QN68
AGL030
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)†
ARM Processor Support in IGLOO FPGAs
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
IGLOO Devices
AGL0151
2
ARM-Enabled IGLOO Devices
System Gates
15,000
Typical Equivalent Macrocells
128
VersaTiles (D-flip-flops)
384
Flash*Freeze Mode (typical, µW)
5
RAM kbits (1,024 bits)
–
4,608-Bit Blocks
–
FlashROM Kbits (1,024 bits)
1
AES-Protected ISP 2
–
Integrated PLL in CCCs 3
–
6
VersaNet Globals 4
I/O Banks
2
Maximum User I/Os
49
Package Pins
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†,
and LVCMOS 2.5 V / 5.0 V Input†
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above)
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
†
• M1 IGLOO Devices—Cortex®-M1 Soft Processor Available with
or without Debug
AGL400
125,000
1,024
3,072
16
36
8
1
Yes
1
18
2
133
AGL250
M1AGL250
250,000
2,048
6,144
24
36
8
1
Yes
1
18
4
143
UC81, CS81 CS121 3
CS196
CS196 5
QN48, QN68,
QN1326
QN1326
VQ100
VQ100
QN1326
QN1326
VQ100
VQ100
FG144
FG144
30,000
256
768
5
–
–
1
–
–
6
2
81
AGL060 AGL125
60,000
512
1,536
10
18
4
1
Yes
1
18
2
96
FBGA
400,000
–
9,216
32
54
12
1
Yes
1
18
4
194
AGL600
M1AGL600
600,000
–
13,824
36
108
24
1
Yes
1
18
4
235
AGL1000
M1AGL1000
1,000,000
–
24,576
53
144
32
1
Yes
1
18
4
300
CS196
CS281
CS281
FG144, FG256, FG144, FG256, FG144, FG256,
FG484
FG484
FG484
Notes:
1.
2.
3.
4.
5.
6.
7.
AGL015 is not recommended for new designs
AES is not available for ARM-enabled IGLOO devices.
AGL060 in CS121 does not support the PLL.
Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
The M1AGL250 device does not support this package.
Package not available.
The IGLOOe datasheet and IGLOOe FPGA Fabric User Guide provide information on higher densities and additional features.
† AGL015 and AGL030 devices do not support this feature.
May 2016
© 2016 Microsemi Corporation
‡ Supported only by AGL015 and AGL030 devices.
I
IGLOO Low Power Flash FPGAs
I/Os Per Package1
IGLOO Devices
AGL0152 AGL030 AGL060
AGL125
ARM-Enabled
IGLOO Devices
AGL250
AGL400
M1AGL250
AGL600
AGL1000
M1AGL600
M1AGL1000
Package
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O 4
Differential I/O Pairs
Single-Ended I/O 4
Differential I/O Pairs
Single-Ended I/O 4
Differential I/O Pairs
Single-Ended I/O 4
Differential I/O Pairs
I/O Type3
QN48
–
34
–
–
–
–
–
–
–
–
–
–
QN68
49
49
–
–
–
–
–
–
–
–
–
–
UC81
–
66
–
–
–
–
–
–
–
–
–
–
CS81
–
66
–
–
–
–
–
–
–
–
–
–
CS121
–
–
96
96
–
–
–
–
–
–
–
–
–
77
71
71
68
13
–
–
–
–
–
–
VQ100
6
QN132
–
81
80
84
–
–
–
–
–
–
–
–
CS196
–
–
–
133
143 5
35 5
143
35
–
–
–
–
FG144
–
–
–
97
97
24
97
25
97
25
97
25
FG256
–
–
–
–
–
–
178
38
177
43
177
44
CS281
–
–
–
–
–
–
–
–
215
53
215
53
FG4847
–
–
–
–
–
–
194
38
235
60
300
74
7
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO FPGA Fabric User Guide to
ensure compliance with design and board migration requirements.
2. AGL015 is not recommended for new designs.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of singleended user I/Os available is reduced by one.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1AGL250 device does not support QN132 or CS196 packages.
6. Package not available.
7. FG256 and FG484 are footprint-compatible packages.
Table 1 • IGLOO FPGAs Package Sizes Dimensions
QN132* CS196
Package
UC81
CS81
CS121
QN48
QN68
Length × Width
(mm\mm)
4×4
5×5
6×6
6×6
8×8
8×8
8×8
Nominal Area
(mm2)
16
25
36
36
64
64
64
100
169
196
289
529
Pitch (mm)
0.4
0.5
0.5
0.4
0.4
0.5
0.5
0.5
1.0
0.5
1.0
1.0
Height (mm)
0.80
0.80
0.99
0.90
0.90
0.75
1.20
1.05
1.45
1.00
1.60
2.23
Note:
II
* Package not available.
R evis i o n 27
CS281
FG144
VQ100
10 × 10 13 × 13 14 × 14
FG256
FG484
17 × 17 23 × 23
IGLOO Low Power Flash FPGAs
IGLOO Ordering Information
AGL1000
V2
_
G
FG
144
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +85°C Junction Temperature)
I = Industrial (–40°C to +100°C Junction Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging (some packages also halogen-free)
Package Type
UC = Micro Chip Scale Package (0.4 mm pitch)
CS = Chip Scale Package (0.4 mm and 0.5 mm pitches)
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO Devices
AGL015 = 15,000 System Gates
AGL030 = 30,000 System Gates
AGL060 = 60,000 System Gates
AGL125 = 125,000 System Gates
AGL250 = 250,000 System Gates
AGL400 = 400,000 System Gates
AGL600 = 600,000 System Gates
AGL1000 = 1,000,000 System Gates
IGLOO Devices with Cortex-M1
M1AGL250 = 250,000 System Gates
M1AGL600 = 600,000 System Gates
M1AGL1000 = 1,000,000 System Gates
Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
R ev i si o n 2 7
III
IGLOO Low Power Flash FPGAs
Temperature Grade Offerings
AGL015 1
AGL030
AGL060
AGL125
Package
AGL250
AGL400
M1AGL250
AGL600
AGL1000
M1AGL600 M1AGL1000
QN48
–
C, I
–
–
–
–
–
–
QN68
C, I
–
–
–
–
–
–
–
UC81
–
C, I
–
–
–
–
–
–
CS81
–
C, I
–
–
–
–
–
–
CS121
–
–
C, I
C, I
–
–
–
–
VQ100
–
C, I
C, I
C, I
C, I
–
–
–
C, I
–
–
–
–
QN1322
–
C, I
CS196
–
–
–
C, I
C, I
C, I
–
–
FG144
–
–
–
C, I
C, I
C, I
C, I
C, I
FG256
–
–
–
–
–
C, I
C, I
C, I
CS281
–
–
–
–
–
–
C, I
C, I
FG484
–
–
–
–
–
C, I
C, I
C, I
C, I
2
Notes:
1. AGL015 is not recommended for new designs.
2. Package not available.
C = Commercial temperature range: 0°C to 85°C junction temperature.
I = Industrial temperature range: –40°C to 100°C junction temperature.
IGLOO Device Status
IGLOO Devices
Status
M1 IGLOO Devices
Status
M1AGL250
Production
AGL015
Not recommended for new
designs.
AGL030
Production
AGL060
Production
AGL125
Production
AGL250
Production
AGL400
Production
AGL600
Production
M1AGL600
Production
AGL1000
Production
M1AGL1000
Production
References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1
(Cortex-M1).
Contact your local Microsemi SoC Products Group representative for device availability:
www.microsemi.com/soc/contact/default.aspx.
AGL015 and AGL030
The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
AGL015 is not recommended for new designs.
IV
R evis i o n 27
IGLOO Low Power Flash FPGAs
IGLOO Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-4
3-5
3-5
3-5
Package Pin Assignments
UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
R ev i si o n 2 7
V
1 – IGLOO Device Family Overview
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a
single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced
features.
The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low power
mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze technology
simplifies power management through I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low power consumption (from 12 µW) while
the IGLOO device is completely functional in the system. This allows the IGLOO device to control system
power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming
minimal power.
Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, singlechip solution that is Instant On. IGLOO is reprogrammable and offers time-to-market benefits at an ASIClevel unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock
conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030
devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with
up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for
implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It
has a three-stage pipeline that offers a good balance between low power consumption and speed when
implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a
configurable nested interrupt controller, and can be implemented with or without the debug block. CortexM1 is available for free from Microsemi for use in M1 IGLOO FPGAs.
The ARM-enabled devices have ordering numbers that begin with M1AGL and do not support AES
decryption.
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low
power Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks
while retaining the design information, SRAM content, and registers. Flash*Freeze technology is
combined with in-system programmability, which enables users to quickly and easily upgrade and update
their designs in the final stages of manufacturing or in the field. The ability of IGLOO V2 devices to
support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus
achieving the lowest total system power.
When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and
inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is
retained.
The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage
solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for
portable electronics.
R ev i si o n 2 7
1-1
IGLOO Low Power Flash FPGAs
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for
power-sensitive applications. IGLOO devices have only a very limited power-on current surge and no high-current
transition period, both of which occur on many FPGAs.
IGLOO devices also have low dynamic power consumption to further maximize power savings; power is even further
reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives
the IGLOO device the lowest total system power offered by any FPGA.
Security
Nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external bitstream that
can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique combination of
reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash
programming can offer.
IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in
the FPGA industry for intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices
can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard.
AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES
standard. IGLOO devices have a built-in AES decryption engine and a flash-based AES key that make them the most
comprehensive programmable logic device security solution available today. IGLOO devices with AES-based security
provide a high level of protection for remote field updates over public networks such as the Internet, and are designed
to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves.
Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are located beneath
seven metal layers, and many device design and layout techniques have been used to make invasive attacks
extremely difficult. The IGLOO family, with FlashLock and AES security, is unique in being highly resistant to both
invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP
possible. An IGLOO device provides the best available security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration
data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system powerup (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do not require system configuration
components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials
costs and PCB area, and increases security and system reliability.
Instant On
Flash-based IGLOO devices support Level 0 of the Instant On classification standard. This feature helps in system
component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory
blocks, clock generation, and bus activity management. The Instant On feature of flash-based IGLOO devices greatly
simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock
generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash
configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored.
This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout
detection, and clock generator devices from the PCB design. Flash-based IGLOO devices simplify total system design
and reduce cost and design risk while increasing system reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1
µs) and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs the device does
not need to reload configuration and design state from external memory components; instead it retains all necessary
information to resume operation immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs,
Flash-based IGLOO devices allow all functionality to be Instant On; no external boot PROM is required. On-board
security mechanisms prevent access to all the programming information and enable secure remote updates of the
FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and
R ev i si o n 2 7
1-2
IGLOO Device Family Overview
field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can
be performed using the industry-standard AES algorithm. The IGLOO family device architecture mitigates the need for
ASIC migration at higher user volumes. This makes the IGLOO family a cost-effective ASIC replacement solution,
especially for applications in the consumer, networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and
thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in
SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the
configuration memory of IGLOO flash-based FPGAs. Once it is programmed, the flash cell configuration element of
IGLOO FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)
errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an advanced flashbased, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to
implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and
abundant flash switches allows for very high logic utilization without compromising device routability or performance.
Logic functions within the device are interconnected through a four-level routing hierarchy.
IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation.
Advanced Architecture
The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The IGLOO device
consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4):
•
Flash*Freeze technology
•
FPGA VersaTiles
•
Dedicated FlashROM
•
Dedicated SRAM/FIFO memory†
•
Extensive CCCs and PLLs†
•
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a Dflip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The
versatility of the IGLOO core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable
allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC® family of thirdgeneration-architecture flash FPGAs.
† The AGL015 and AGL030 do not support PLL or SRAM.
1 -3
R evis i o n 27
IGLOO Low Power Flash FPGAs
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for
virtually any design.
Bank 0
Bank 0
Bank 1
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 0
Bank 1
VersaTile
Bank 1
Note: *Not supported by AGL015 and AGL030 devices
Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and AGL125)
Bank 0
Bank 1
Bank 3
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
Bank 1
Bank 3
VersaTile
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(AGL600 and AGL1000)
Bank 2
Figure 1-2 •
IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and AGL1000)
R ev i si o n 2 7
1-4
IGLOO Device Family Overview
Flash*Freeze Technology
The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and
register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to
quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are
kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on
power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device
retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be
set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O
banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management
of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe
to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is
not planned, which is advantageous because of the inherent low power static (as low as 12 µW) and dynamic
capabilities of the IGLOO device. Refer to Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode.
IGLOO FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-3 •
IGLOO Flash*Freeze Mode
VersaTiles
The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The IGLOO
VersaTile supports the following:
•
All 3-input logic functions—LUT-3 equivalent
•
Latch with clear or set
•
D-flip-flop with clear or set
•
Enable D-flip-flop with clear or set
Refer to Figure 1-4 for VersaTile configurations.
LUT-3 Equivalent
X1
X2
X3
LUT-3
Y
D-Flip-Flop with Clear or Set
Data
CLK
CLR
Y
D-FF
Enable D-Flip-Flop with Clear or Set
Data
CLK
Enable
CLR
Figure 1-4 •
1 -5
VersaTile Configurations
R evis i o n 27
Y
D-FF
IGLOO Low Power Flash FPGAs
User Nonvolatile FlashROM
IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse
system applications:
•
Internet protocol addressing (wireless or fixed)
•
System calibration settings
•
Device serialization and/or inventory control
•
Subscription-based business models (for example, set-top boxes)
•
Secure key storage for secure communications algorithms
•
Asset management/tracking
•
Date stamping
•
Version management
The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The core can be
individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load
data over public networks (except in the AGL015 and AGL030 devices), as in security keys stored in the FlashROM for
a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either
through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be
programmed from the JTAG interface and cannot be programmed from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a
synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes
within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank,
and the four least significant bits (LSBs) of the FlashROM address define the byte.
The Microsemi development software solutions, Libero® System-on-Chip (SoC) and Designer, have extensive support
for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a
unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data
for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehensive
programming file support is also included to allow for easy programming of large numbers of parts with differing
FlashROM contents.
SRAM and FIFO
IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their north and south
sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,
512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured
with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream.
The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG
macro (except in the AGL015 and AGL030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be
configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in
addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for
generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create
larger configurations.
PLL and CCC
IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the
IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The AGL015 and AGL030 do not have a
PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west
side) has a PLL.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as
clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the
CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
R ev i si o n 2 7
1-6
IGLOO Device Family Overview
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
•
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
•
2 programmable delay types for clock skew minimization
•
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration
(for PLL only).
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)
•
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used
(for PLL only)
•
Maximum acquisition time is 300 µs (for PLL only)
•
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
•
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / fOUT_CCC (for
PLL only)
Global Clocking
IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support
described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global
networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The
VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V,
3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the
I/O standards supported (Table 1-1).
Table 1-1 • I/O Standards Supported
I/O Standards Supported
I/O Bank Type
Device and Bank Location
LVTTL/
LVCMOS
PCI/PCI-X
LVPECL, LVDS,
B-LVDS, M-LVDS
Advanced
East and west banks of AGL250 and larger devices
Standard Plus
North and south banks of AGL250 and larger devices
Not supported
Not supported
Not supported
All banks of AGL060 and AGL125K
Standard
All banks of AGL015 and AGL030
Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the
following:
•
Single-Data-Rate applications
•
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications
IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS
can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a poweredup system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system
is powered up, while the component itself is powered down, or when power supplies are floating.
1 -7
R evis i o n 27
IGLOO Low Power Flash FPGAs
Wide Range I/O Support
IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both the JESD8-B
specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its
1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or
move to less costly components with greater tolerances. Wide range eases I/O bank management and provides
enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage
applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files
generated from Designer v8.5 or greater. See the FlashPro User Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of
Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming
dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os
you wish to modify (Figure 1-5 on page 1-9).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins,
or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and
then held at that value during programming
Z -Tri-State: I/O is tristated
R ev i si o n 2 7
1-8
IGLOO Device Family Overview
Figure 1-5 •
I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after completing
programming file generation.
1 -9
R evis i o n 27
2 – IGLOO DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in Table 22 on page 2-2 is not implied.
Table 2-1 •
Symbol
Absolute Maximum Ratings
Parameter
Limits1
Units
VCC
DC core supply voltage
–0.3 to 1.65
V
VJTAG
JTAG DC voltage
–0.3 to 3.75
V
VPUMP
Programming voltage
–0.3 to 3.75
V
VCCPLL
Analog power supply (PLL)
–0.3 to 1.65
V
–0.3 to 3.75
V
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
V
VCCI and VMV 2 DC I/O buffer supply voltage
VI
I/O input voltage
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
TSTG 3
Storage Temperature
–65 to +150
°C
TJ 3
Junction Temperature
+125
°C
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA
Fabric User Guide for further information.
3. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-3, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
R ev i si o n 2 7
2-1
IGLOO DC and Switching Characteristics
Table 2-2 •
Recommended Operating Conditions 1
Symbol
Parameter
Commercial
Industrial
Units
0 to +85
–40 to +100
°C
1.5 V DC core supply voltage
1.425 to 1.575
1.425 to 1.575
V
1.2 V–1.5 V wide range DC core
supply voltage 4,6
1.14 to 1.575
1.14 to 1.575
V
1.4 to 3.6
1.4 to 3.6
V
3.15 to 3.45
3.15 to 3.45
V
0 to 3.6
0 to 3.6
V
1.425 to 1.575
1.425 to 1.575
V
1.14 to 1.575
1.14 to 1.575
V
Junction Temperature 2
TJ
3
5
VCC
VJTAG
JTAG DC voltage
VPUMP
Programming voltage
Programming Mode
Operation 7
8
VCCPLL
Analog power supply (PLL)
1.5 V DC core supply voltage
5
1.2 V – 1.5 V DC core supply
voltage4,6
VCCI
VMV 9
and 1.2 V DC core supply voltage6
1.14 to 1.26
1.14 to 1.26
V
1.2 V DC wide range DC supply
voltage6
1.14 to 1.575
1.14 to 1.575
V
1.5 V DC supply voltage
1.425 to 1.575
1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
2.3 to 2.7
V
3.0 V DC supply voltage 10
2.7 to 3.6
2.7 to 3.6
V
3.3 V DC supply voltage
3.0 to 3.6
3.0 to 3.6
V
2.375 to 2.625
2.375 to 2.625
V
3.0 to 3.6
3.0 to 3.6
V
LVDS differential I/O
LVPECL differential I/O
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. Software Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and -40°C to +85°C
for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures, Microsemi recommends
using custom settings for temperature range before running timing and power analysis tools. For more information on custom settings,
refer to the New Project Dialog Box in the Libero SoC Online Help.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in
Table 2-25 on page 2-24. VCCI should be at the same voltage within a given I/O bank.
4. All IGLOO devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2 devices powered
by 1.2 V supply must switch the core supply to 1.5 V for in-system programming.
5. For IGLOO® V5 devices
6. For IGLOO V2 devices only, operating at VCCI VCC.
7. VPUMP can be left floating during operation (not programming mode).
8. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User Guide for further
information.
9. VMV and VCCI must be at the same voltage within a given I/O bank. VMV pins must be connected to the corresponding VCCI pins.
See the "VMVx I/O Supply Voltage (quiet)" on page 3-1 for further information.
10. 3.3 V wide range is compliant to the JESD-8B specification and supports 3.0 V VCCI operation.
2 -2
R evis i o n 27
IGLOO Low Power Flash FPGAs
Table 2-3 •
Flash Programming Limits – Retention, Storage, and Operating Temperature1
Programming Cycles
Program Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG (°C) 2
Maximum Operating Junction
Temperature TJ (°C) 2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
Product Grade
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 on page 2-2 for device operating
conditions and absolute limits.
Table 2-4 •
VCCI
Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or Undershoot Duration
as a Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot2
10%
1.4 V
5%
1.49 V
2.7 V or less
3V
10%
1.1 V
5%
1.19 V
3.3 V
10%
0.79 V
5%
0.88 V
3.6 V
10%
0.45 V
5%
0.54 V
Notes:
1. Based on reliability requirements at junction temperature at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum
overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits ensure easy
transition from the powered-off state to the powered-up state of the device. The many different supplies can power up
in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the
power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5.
There are five regions to consider during power-up.
IGLOO I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and Figure 2-2 on
page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V
Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V
Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V
VCC Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V
R ev i si o n 2 7
2-3
IGLOO DC and Switching Characteristics
Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in
hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
•
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior.
Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 21 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5
devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the output clock is lost. Refer
to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the
ProASIC®3 and ProASIC3E FPGA fabric user guides for information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns
from input buffer to output buffer in your design.
VCC
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC = 1.575 V
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
Region 1: I/O Buffers are OFF
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
VCC = 1.425 V
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Region 1: I/O buffers are OFF
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
Figure 2-1 •
2 -4
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
R evis i o n 27
VCCI
IGLOO Low Power Flash FPGAs
VCC
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC = 1.575 V
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
Region 1: I/O Buffers are OFF
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
VCC = 1.14 V
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
Va = 0.85 V ± 0.2 V
Deactivation trip point:
Vd = 0.75 V ± 0.2 V
Region 1: I/O buffers are OFF
Activation trip point:
Va = 0.9 V ± 0.15 V
Deactivation trip point:
Vd = 0.8 V ± 0.15 V
Figure 2-2 •
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
VCCI
V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature.
This is an important distinction because dynamic and static power consumption cause the chip junction to be higher
than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5 on page 2-6.
P = Power dissipation
R ev i si o n 2 7
2-5
IGLOO DC and Switching Characteristics
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The
thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100°C.
EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for the AGL1000-FG484
package at commercial temperature and in still air.
– 70Cjunction temp. (C) – Max. ambient temp. (C)- = 100C
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------= 1.28 W
Maximum Power Allowed = Max.
23.3°C/W
ja (C/W)
EQ 2
Table 2-5 •
Package Thermal Resistivities
ja
Package Type
Device
Pin Count
jc
Still Air
1 m/s
2.5 m/s
Unit
Quad Flat No Lead (QN)
AGL030
132
13.1
21.4
16.8
15.3
C/W
AGL060
132
11.0
21.2
16.6
15.0
C/W
AGL125
132
9.2
21.1
16.5
14.9
C/W
AGL250
132
8.9
21.0
16.4
14.8
C/W
AGL030
68
13.4
68.4
45.8
43.1
C/W
100
10.0
35.3
29.4
27.1
C/W
AGL1000
281
6.0
28.0
22.8
21.5
C/W
AGL400
196
7.2
37.1
31.1
28.9
C/W
AGL250
196
7.6
38.3
32.2
30.0
C/W
AGL125
196
8.0
39.5
33.4
31.1
C/W
AGL030
81
12.4
32.8
28.5
27.2
C/W
AGL060
81
11.1
28.8
24.8
23.5
C/W
AGL250
81
10.4
26.9
22.3
20.9
C/W
Micro Chip Scale Package (UC)
AGL030
81
16.9
40.6
35.2
33.7
C/W
Fine Pitch Ball Grid Array (FG)
AGL060
144
18.6
55.2
49.4
47.2
C/W
AGL1000
144
6.3
31.6
26.2
24.2
C/W
AGL400
144
6.8
37.6
31.2
29.0
C/W
AGL250
256
12.0
38.6
34.7
33.0
C/W
AGL1000
256
6.6
28.1
24.4
22.7
C/W
AGL1000
484
8.0
23.3
19.0
16.7
C/W
Very Thin Quad Flat Pack (VQ)*
Chip Scale Package (CS)
Note: *Thermal resistances for other device-package combinations will be posted in a later revision.
Disclaimer:
The simulation for determining the junction-to-air thermal resistance is based on JEDEC standards (JESD51) and
assumptions made in building the model. Junction-to-case is based on SEMI G38-88. JESD51 is only used for
comparing one package to another package, provided the two tests uses the same condition. They have little
relevance in actual application and therefore should be used with a degree of caution.
2 -6
R evis i o n 27
IGLOO Low Power Flash FPGAs
Temperature and Voltage Derating Factors
Table 2-6 •
Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V)
For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage VCC
(V)
–40°C
0°C
25°C
70°C
85°C
100°C
1.425
0.934
0.953
0.971
1.000
1.007
1.013
1.500
0.855
0.874
0.891
0.917
0.924
0.929
1.575
0.799
0.816
0.832
0.857
0.864
0.868
Table 2-7 •
Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V)
For IGLOO V2, 1.2 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage VCC
(V)
–40°C
0°C
25°C
70°C
85°C
100°C
1.14
0.967
0.978
0.991
1.000
1.006
1.010
1.20
0.864
0.874
0.885
0.894
0.899
0.902
1.26
0.794
0.803
0.814
0.821
0.827
0.830
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and
VJTAG), operating temperature, system clock frequency, and power modes usage. Microsemi recommends using the
PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on
the user design, power mode usage, operating voltage, and temperature.
Table 2-8 •
Power Supply State per Mode
Power Supply Configurations
Modes/power supplies
VCC
VCCPLL
VCCI
VJTAG
VPUMP
Flash*Freeze
On
On
On
On
On/off/floating
Sleep
Off
Off
On
Off
Off
Shutdown
Off
Off
Off
Off
Off
No Flash*Freeze
On
On
On
On
On/off/floating
Note: Off: Power supply level = 0 V
Table 2-9 •
Typical
(25°C)
Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode*
Core
Voltage
AGL015
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
AGL1000
Units
1.2 V
4
4
8
13
20
27
30
44
µA
1.5 V
6
6
10
18
34
51
72
127
µA
Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution, which is shown
in Table 2-13 on page 2-10 through Table 2-15 on page 2-11 and Table 2-16 on page 2-11 through Table 2-18 on page 2-12
(PDC6 and PDC7).
R ev i si o n 2 7
2-7
IGLOO DC and Switching Characteristics
Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode*
Core
Voltage
VCCI/ VJTAG = 1.2 V
(per bank) Typical (25°C)
1.2 V
AGL015 AGL030 AGL060 AGL125
AGL250 AGL400 AGL600 AGL1000 Units
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
µA
VCCI/VJTAG = 1.5 V
1.2 V / 1.5
(per bank) Typical (25°C)
V
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
µA
VCCI/VJTAG = 1.8 V
1.2 V / 1.5
(per bank) Typical (25°C)
V
1.9
1.9
1.9
1.9
1.9
1.9
1.9
1.9
µA
VCCI/VJTAG = 2.5 V
1.2 V / 1.5
(per bank) Typical (25°C)
V
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
µA
VCCI/VJTAG = 3.3 V
1.2 V / 1.5
(per bank) Typical (25°C)
V
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
µA
Note: IDD = NBANKS × ICCI. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-10 through
Table 2-15 on page 2-11 and Table 2-16 on page 2-11 through Table 2-18 on page 2-12 (PDC6 and PDC7).
Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode
Typical (25°C)
Core Voltage
AGL015
AGL030
Units
1.2 V / 1.5 V
0
0
µA
Table 2-12 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1
Core
Voltage
ICCA Current
AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600
AGL1000 Units
2
Typical (25°C)
1.2 V
5
6
10
13
18
25
28
42
µA
1.5 V
14
16
20
28
44
66
82
137
µA
VCCI/VJTAG = 1.2 V
(per bank) Typical (25°C)
1.2 V
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
µA
VCCI/VJTAG = 1.5 V (per
bank) Typical (25°C)
1.2 V /
1.5 V
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
µA
VCCI/VJTAG = 1.8 V (per
bank) Typical (25°C)
1.2 V /
1.5 V
1.9
1.9
1.9
1.9
1.9
1.9
1.9
1.9
µA
VCCI/VJTAG = 2.5 V (per
bank) Typical (25°C)
1.2 V /
1.5 V
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
µA
VCCI/VJTAG = 3.3 V (per
bank) Typical (25°C)
1.2 V /
1.5 V
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
µA
ICCI or IJTAG
Current3
Notes:
1. IDD = NBANKS × ICCI + ICCA. JTAG counts as one bank when powered.
2. Includes VCC, VPUMP, and VCCPLL currents.
3. Values do not include I/O static contribution (PDC6 and PDC7).
2 -8
R evis i o n 27
IGLOO Low Power Flash FPGAs
Power per I/O Pin
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
VCCI (V)
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
16.27
3
3.3 V LVCMOS Wide Range
3.3
–
16.27
2.5 V LVCMOS
2.5
–
4.65
1.8 V LVCMOS
1.8
–
1.61
1.5 V LVCMOS (JESD8-11)
1.5
–
0.96
1.2
–
0.58
1.2 V LVCMOS Wide Range
1.2
–
0.58
3.3 V PCI
3.3
–
17.67
3.3 V PCI-X
3.3
–
17.67
LVDS
2.5
2.26
23.39
LVPECL
3.3
5.72
59.05
Single-Ended
1.2 V LVCMOS4
4
Differential
Notes:
1.
2.
3.
4.
PDC6 is the static power (where applicable) measured on VCCI.
PAC9 is the total dynamic power measured on VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Applicable for IGLOO V2 devices only
Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
VCCI (V)
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
16.41
3.3 V LVCMOS Wide Range3
3.3
–
16.41
2.5 V LVCMOS
2.5
–
4.75
1.8 V LVCMOS
1.8
–
1.66
1.5 V LVCMOS (JESD8-11)
1.5
–
1.00
1.2 V LVCMOS4
1.2
–
0.61
1.2 V LVCMOS Wide Range4
1.2
–
0.61
3.3 V PCI
3.3
–
17.78
3.3 V PCI-X
3.3
–
17.78
Notes:
1.
2.
3.
4.
PDC6 is the static power (where applicable) measured on VCCI.
PAC9 is the total dynamic power measured on VCCI.
Applicable for IGLOO V2 devices only.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
R ev i si o n 2 7
2-9
IGLOO DC and Switching Characteristics
Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
VCCI (V)
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
17.24
3
3.3 V LVCMOS Wide Range
3.3
–
17.24
2.5 V LVCMOS
2.5
–
5.64
1.8 V LVCMOS
1.8
–
2.63
1.5 V LVCMOS (JESD8-11)
1.5
–
1.97
1.2 V LVCMOS
1.2
–
0.57
1.2 V LVCMOS Wide Range4
1.2
–
0.57
Single-Ended
4
Notes:
1.
2.
3.
4.
PDC6 is the static power (where applicable) measured on VCCI.
PAC9 is the total dynamic power measured on VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Applicable for IGLOO V2 devices only.
Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
5
3.3
–
136.95
3.3 V LVCMOS Wide Range4
5
3.3
–
136.95
2.5 V LVCMOS
5
2.5
–
76.84
1.8 V LVCMOS
5
1.8
–
49.31
1.5 V LVCMOS (JESD8-11)
5
1.5
–
33.36
1.2 V LVCMOS5
5
1.2
–
16.24
1.2 V LVCMOS Wide Range5
5
1.2
–
16.24
3.3 V PCI
10
3.3
–
194.05
3.3 V PCI-X
10
3.3
–
194.05
LVDS
–
2.5
7.74
156.22
LVPECL
–
3.3
19.54
339.35
Differential
Notes:
1.
2.
3.
4.
5.
Dynamic power consumption is given for standard load and software default drive strength and output slew.
PDC7 is the static power (where applicable) measured on VCCI.
PAC10 is the total dynamic power measured on VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Applicable for IGLOO V2 devices only.
2 -1 0
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
3.3 V LVTTL / 3.3 V LVCMOS
5
3.3
–
122.16
4
3.3 V LVCMOS Wide Range
5
3.3
–
122.16
2.5 V LVCMOS
5
2.5
–
68.37
1.8 V LVCMOS
5
1.8
–
34.53
1.5 V LVCMOS (JESD8-11)
5
1.5
–
23.66
1.2 V LVCMOS
5
1.2
–
14.90
1.2 V LVCMOS Wide Range5
5
1.2
–
14.90
3.3 V PCI
10
3.3
–
181.06
3.3 V PCI-X
10
3.3
–
181.06
Single-Ended
5
Notes:
1.
2.
3.
4.
5.
Dynamic power consumption is given for standard load and software default drive strength and output slew.
PDC7 is the static power (where applicable) measured on VCCI.
PAC10 is the total dynamic power measured on VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Applicable for IGLOO V2 devices only.
Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
3.3 V LVTTL / 3.3 V LVCMOS
5
3.3
–
104.38
4
3.3 V LVCMOS Wide Range
5
3.3
–
104.38
2.5 V LVCMOS
5
2.5
–
59.86
1.8 V LVCMOS
5
1.8
–
31.26
1.5 V LVCMOS (JESD8-11)
5
1.5
–
21.96
5
1.2
–
13.49
5
1.2
–
13.49
Single-Ended
5
1.2 V LVCMOS
5
1.2 V LVCMOS Wide Range
Notes:
1.
2.
3.
4.
5.
Dynamic power consumption is given for standard load and software default drive strength and output slew.
PDC7 is the static power (where applicable) measured on VCCI.
PAC10 is the total dynamic power measured on VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Applicable for IGLOO V2 devices only.
R ev i si o n 2 7
2-11
IGLOO DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-19 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Device Specific Dynamic Power
(µW/MHz)
Parameter
Definition
AGL1000
AGL600
AGL400
AGL250
AGL125
AGL060
AGL030
AGL015
PAC1
Clock contribution of a
Global Rib
7.778
6.221
6.082
4.460
4.446
2.736
0.000
0.000
PAC2
Clock contribution of a
Global Spine
4.334
3.512
2.759
2.718
1.753
1.971
3.483
3.483
PAC3
Clock contribution of a
VersaTile row
1.379
1.445
1.377
1.483
1.467
1.503
1.472
1.472
PAC4
Clock contribution of a
VersaTile used as a
sequential module
0.151
0.149
0.151
0.149
0.149
0.151
0.146
0.146
PAC5
First contribution of a
VersaTile used as a
sequential module
0.057
PAC6
Second contribution of a
VersaTile used as a
sequential module
0.207
PAC7
Contribution of a VersaTile
used as a combinatorial
module
0.276
0.262
0.279
0.277
0.280
0.300
0.281
0.273
PAC8
Average contribution of a
routing net
1.161
1.147
1.193
1.273
1.076
1.088
1.134
1.153
PAC9
Contribution of an I/O input
pin (standard-dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
PAC10
Contribution of an I/O output
pin (standard-dependent)
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
PAC11
Average contribution of a
RAM block during a read
operation
25.00
PAC12
Average contribution of a
RAM block during a write
operation
30.00
PAC13
Dynamic PLL contribution
2.70
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or SmartPower tool in Libero SoC.
2 -1 2
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-20 • Different Components Contributing to the Static Power Consumption in IGLOO Devices
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Device-Specific Static Power (mW)
Parameter
Definition
AGL1000
AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
PDC1
Array static power in Active
mode
See Table 2-12 on page 2-9.
PDC2
Array static power in Static
(Idle) mode
See Table 2-11 on page 2-8.
PDC3
Array static power in
Flash*Freeze mode
See Table 2-9 on page 2-7.
PDC4
Static PLL contribution
1.84
PDC5
Bank quiescent power
(VCCI-dependent)
See Table 2-12 on page 2-9.
PDC6
I/O input pin static power
(standard-dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
PDC7
I/O output pin static power
(standard-dependent)
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or SmartPower tool in Libero SoC.
R ev i si o n 2 7
2-13
IGLOO DC and Switching Characteristics
Table 2-21 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Device Specific Dynamic Power
(µW/MHz)
Parameter
Definition
AGL1000
AGL600
AGL400
AGL250 AGL125 AGL060 AGL030 AGL015
PAC1
Clock contribution of a
Global Rib
4.978
3.982
3.892
2.854
2.845
1.751
0.000
0.000
PAC2
Clock contribution of a
Global Spine
2.773
2.248
1.765
1.740
1.122
1.261
2.229
2.229
PAC3
Clock contribution of a
VersaTile row
0.883
0.924
0.881
0.949
0.939
0.962
0.942
0.942
PAC4
Clock contribution of a
VersaTile used as a
sequential module
0.096
0.095
0.096
0.095
0.095
0.096
0.094
0.094
PAC5
First contribution of a
VersaTile used as a
sequential module
0.045
PAC6
Second contribution of a
VersaTile used as a
sequential module
0.186
PAC7
Contribution of a VersaTile
used as a combinatorial
module
0.158
0.149
0.158
0.157
0.160
0.170
0.160
0.155
PAC8
Average contribution of a
routing net
0.756
0.729
0.753
0.817
0.678
0.692
0.738
0.721
PAC9
Contribution of an I/O input
pin (standard-dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
PAC10
Contribution of an I/O output
pin (standard-dependent)
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
PAC11
Average contribution of a
RAM block during a read
operation
25.00
PAC12
Average contribution of a
RAM block during a write
operation
30.00
PAC13
Dynamic PLL contribution
2.10
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or SmartPower tool in Libero SoC.
2 -1 4
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-22 • Different Components Contributing to the Static Power Consumption in IGLOO Device
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Device Specific Static Power (mW)
Parameter
Definition
AGL1000
AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
PDC1
Array static power in Active
mode
See Table 2-12 on page 2-9.
PDC2
Array static power in Static
(Idle) mode
See Table 2-11 on page 2-8.
PDC3
Array static power in
Flash*Freeze mode
See Table 2-9 on page 2-7.
PDC4
Static PLL contribution
0.90
PDC5
Bank quiescent power
(VCCI-Dependent)
See Table 2-12 on page 2-9.
PDC6
I/O input pin static power
(standard-dependent)
See Table 2-13 on page 2-10 through Table 2-15 on page 2-11.
PDC7
I/O output pin static power
(standard-dependent)
See Table 2-16 on page 2-11 through Table 2-18 on page 2-12.
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or SmartPower tool in Libero SoC.
R ev i si o n 2 7
2-15
IGLOO DC and Switching Characteristics
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more accurate and
detailed power estimations, use the SmartPower tool in Microsemi Libero SoC software.
The power calculation methodology described below uses the following variables:
•
The number of PLLs as well as the number and the frequency of each output clock generated
•
The number of combinatorial and sequential cells used in the design
•
The internal clock frequencies
•
The number and the standard of I/O pins used in the design
•
The number of RAM blocks used in the design
•
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-23 on page 2-19.
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-24 on page 2-19.
•
Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-24 on
page 2-19. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS * PDC6 + NOUTPUTS * PDC7
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE* PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine
Architecture" section of the IGLOO FPGA Fabric User Guide.
NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine
Architecture" section of the IGLOO FPGA Fabric User Guide.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on page 2-19.
FCLK is the global clock signal frequency.
2 -1 6
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on page 2-19.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on page 2-19.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-24 on page 2-19.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-24 on page 2-19.
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.†
† If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution
(PAC13* FCLKOUT product) to the total PLL contribution.
R ev i si o n 2 7
2-17
IGLOO DC and Switching Characteristics
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a
net is 100%, this means that this net switches at half the clock frequency. Below are some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock
frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
Bit 0 (LSB) = 100%
–
Bit 1
= 50%
–
Bit 2
= 25%
–
…
–
Bit 7 (MSB) = 0.78125%
–
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate
output buffers are used, the enable rate should be 100%.
Table 2-23 • Toggle Rate Guidelines Recommended for Power Calculation
Component
1
2
Definition
Guideline
Toggle rate of VersaTile outputs
10%
I/O buffer toggle rate
10%
Table 2-24 • Enable Rate Guidelines Recommended for Power Calculation
Component
1
2
3
2 -1 8
Definition
Guideline
I/O output buffer enable rate
100%
RAM enable rate for read operations
12.5%
RAM enable rate for write operations
12.5%
R evi s i o n 27
IGLOO Low Power Flash FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Combinational Cell
Y
LVPECL (Applicable to
Advanced I/O Banks Only)L
Y
tPD = 1.22 ns
tPD = 1.20 ns
tDP = 1.72 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
LVTTL Output drive strength = 12 mA
High slew rate
tDP = 3.05 ns (Advanced I/O Banks)
tPD = 1.80 ns
I/O Module
(Non-Registered)
Combinational Cell
I/O Module
(Registered)
Y
LVTTL Output drive strength = 8 mA
High slew rate
tDP = 4.12 ns (Advanced I/O Banks)
tPY = 1.20 ns
LVPECL
(Applicable
to Advanced
I/O Banks only)
D
tPD = 1.49 ns
Q
I/O Module
(Non-Registered)
Combinational Cell
Y
tICLKQ = 0.43 ns
tISUD = 0.47 ns
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
tDP = 4.42 ns (Advanced I/O Banks)
tPD = 0.86 ns
Input LVTTL
Clock
Register Cell
tPY = 0.87 ns (Advanced I/O Banks)
D
Combinational Cell
Y
Q
I/O Module
(Non-Registered)
LVDS,
BLVDS,
M-LVDS
(Applicable for
Advanced I/O
Banks only)
Figure 2-3 •
D
Q
D
tPD = 0.92 ns
tCLKQ = 0.90 ns
tSUD = 0.82 ns
tPY = 1.35 ns
I/O Module
(Registered)
Register Cell
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
tDP = 3.05 ns
(Advanced I/O Banks)
tCLKQ = 0.90 ns
tSUD = 0.82 ns
tOCLKQ = 1.02 ns
tOSUD = 0.52 ns
Input LVTTL
Clock
Input LVTTL
Clock
tPY = 0.87 ns
(Advanced I/O Banks)
tPY = 0.87 ns
(Advanced I/O Banks)
Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V,
for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
R ev i si o n 2 7
2-19
IGLOO DC and Switching Characteristics
tPY
tDIN
D
PAD
Q
DIN
Y
CLK
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
To Array
I/O Interface
VIH
PAD
Vtrip
Vtrip
VIL
VCC
50%
50%
Y
GND
tPY
(F)
tPY
(R)
VCC
50%
DIN
GND
50%
tDIN
tDIN
(R)
Figure 2-4 •
2 -2 0
(F)
Input Buffer Timing Model and Delays (example)
R evi s i o n 27
IGLOO Low Power Flash FPGAs
tDOUT
tDP
D Q
PAD
DOUT
D
Std
Load
CLK
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
tDOUT
VCC
(R)
D
50%
(F)
50%
0V
VCC
DOUT
50%
50%
0V
VOH
Vtrip
Vtrip
VOL
PAD
tDP
(R)
Figure 2-5 •
tDP
(F)
Output Buffer Model and Delays (example)
R ev i si o n 2 7
2-21
IGLOO DC and Switching Characteristics
tEOUT
D
Q
CLK
E
tZL, tZH, tHZ, tLZ, tZLS, tZHS
EOUT
D
Q
PAD
DOUT
CLK
D
tEOUT = MAX(tEOUT(r), tEOUT(f))
I/O Interface
VCC
D
VCC
50%
tEOUT (F)
50%
E
tEOUT (R)
VCC
50%
50%
50%
EOUT
tZL
tZH
tHZ
VCCI
90% VCCI
PAD
Vtrip
Vtrip
VOL
10% VCCI
VCC
D
VCC
E
50%
tEOUT (R)
50%
tEOUT (F)
VCC
EOUT
50%
50%
tZLS
VOH
50%
tZHS
PAD
Vtrip
Figure 2-6 •
2 -2 2
50%
tLZ
Vtrip
VOL
Tristate Output Buffer Timing Model and Delays (example)
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions—Software Default Settings
Applicable to Advanced I/O Banks
I/O
Standard
VIL
Equivalent
Software
Default
Drive
Max.
Drive
Strength Slew
V
Rate Min.V
Strength
Option2
VIH
VOL
VOH
IOL1 IOH1
Min.
V
Max.V
Max.
V
Min.
V
mA
mA
3.3 V
LVTTL /
3.3 V
LVCMOS
12 mA
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V
LVCMOS
Wide
Range3
100 µA
12 mA
High
–0.3
0.8
2
3.6
0.2
VCCI – 0.2
0.1
0.1
2.5 V
LVCMOS
12 mA
12 mA
High
–0.3
0.7
1.7
2.7
0.7
1.7
12
12
1.8 V
LVCMOS
12 mA
12 mA
High
–0.3 0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
12
12
1.5 V
LVCMOS
12 mA
12 mA
High
–0.3 0.35 * VCCI
0.65 * VCCI
1.575 0.25 * VCCI
0.75 * VCCI
12
12
1.2 V
LVCMOS4
2 mA
2 mA
High
–0.3 0.35 * VCCI
0.65 * VCCI
1.26
0.25 * VCCI
0.75 * VCCI
2
2
1.2 V
LVCMOS
Wide
Range4,5
100 µA
2 mA
High
–0.3
0.7 * VCCI
1.575
0.1
VCCI – 0.1
0.1
0.1
3.3 V PCI
3.3 V
PCI-X
0.3 * VCCI
Per PCI specifications
Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to V2 Devices operating at VCCI VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
R ev i si o n 2 7
2-23
IGLOO DC and Switching Characteristics
Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
I/O
Standard
Equivalent
Software
Default
Drive
Drive
Strength Slew
Strength
Rate
Option2
VIL
VIH
VOL
VOH
IOL
IOH
Min.
V
Max.
V
Min.
V
Max. V
Max.
V
Min.
V
mA
mA
3.3 V
LVTTL /
3.3 V
LVCMOS
12 mA
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V
LVCMOS
Wide
Range3
100 µA
12 mA
High
–0.3
0.8
2
3.6
0.2
VDD-0.2
0.1
0.1
2.5 V
LVCMOS
12 mA
12 mA
High
–0.3
0.7
1.7
2.7
0.7
1.7
12
12
1.8 V
LVCMOS
8 mA
8 mA
High
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
8
8
1.5 V
LVCMOS
4 mA
4 mA
High
–0.3
0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI
0.75 * VCCI
4
4
1.2 V
LVCMOS4
2 mA
2 mA
High
–0.3
0.35 * VCCI
0.65 * VCCI
1.26
0.25 * VCCI
0.75 * VCCI
2
2
1.2 V
LVCMOS
Wide
Range4
100 µA
2 mA
High
–0.3
0.3 * VCCI
0.7 * VCCI
1.575
0.1
VCCI – 0.1
0.1
0.1
3.3 V PCI
3.3 V
PCI-X
Per PCI specifications
Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to V2 Devices operating at VCCI VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
2 -2 4
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-27 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions—Software Default Settings
Applicable to Standard I/O Banks
I/O
Standard
Equivalent
Software
Default
Drive
Drive
Strength Slew
Strength
Rate
Option2
VIL
VIH
VOL
VOH
IOL1 IOH1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA
mA
3.3 V
LVTTL /
3.3 V
LVCMOS
8 mA
8 mA
High
–0.3
0.8
2
3.6
0.4
2.4
8
8
3.3 V
LVCMOS
Wide
Range3
100 µA
8 mA
High
–0.3
0.8
2
3.6
0.2
VDD-0.2
0.1
0.1
2.5 V
LVCMOS
8 mA
8 mA
High
–0.3
0.7
1.7
3.6
0.7
1.7
8
8
1.8 V
LVCMOS
4 mA
4 mA
High
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
4
1.5 V
LVCMOS
2 mA
2 mA
High
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
2
1.2 V
LVCMOS4
1 mA
1 mA
High
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
1
1
1.2 V
LVCMOS
Wide
Range4,5
100 µA
1 mA
High
–0.3
0.3 * VCCI
0.7 * VCCI
3.6
0.1
0.1
0.1
VCCI – 0.1
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to V2 Devices operating at VCCI VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
R ev i si o n 2 7
2-25
IGLOO DC and Switching Characteristics
Table 2-28 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL4
IIH5
IIL4
IIH5
DC I/O Standards
µA
µA
µA
µA
3.3 V LVTTL / 3.3 V LVCMOS
10
10
15
15
3.3 V LVCMOS Wide Range
10
10
15
15
2.5 V LVCMOS
10
10
15
15
1.8 V LVCMOS
10
10
15
15
1.5 V LVCMOS
10
10
15
15
10
10
15
15
10
10
15
15
3.3 V PCI
10
10
15
15
3.3 V PCI-X
10
10
15
15
1.2 V
LVCMOS3
1.2 V LVCMOS Wide Range
3
Notes:
1.
2.
3.
4.
5.
Commercial range (0°C < TA < 70°C)
Industrial range (–40°C < TA < 85°C)
Applicable to V2 Devices operating at VCCI VCC.
IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
2 -2 6
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-29 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS
1.4 V
3.3 V VCMOS Wide Range
1.4 V
2.5 V LVCMOS
1.2 V
1.8 V LVCMOS
0.90 V
1.5 V LVCMOS
0.75 V
1.2 V LVCMOS
0.60 V
1.2 V LVCMOS Wide Range
0.60 V
3.3 V PCI
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V PCI-X
0.285 * VCCI (RR)
0.615 * VCCI (FF)
Table 2-30 • I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer
tDOUT
Data to Output Buffer delay through the I/O interface
tEOUT
Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN
Input Buffer to Data delay through the I/O interface
tHZ
Enable to Pad delay through the Output Buffer—High to Z
tZH
Enable to Pad delay through the Output Buffer—Z to High
tLZ
Enable to Pad delay through the Output Buffer—Low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to Low
tZHS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
R ev i si o n 2 7
2-27
IGLOO DC and Switching Characteristics
–
0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87 ns
2.5 V
LVCMOS
12 mA
12
High
5
–
0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43 ns
1.8 V
LVCMOS
12 mA
12
High
5
–
0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns
1.5 V
LVCMOS
12 mA
12
High
5
–
0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns
3.3 V PCI
Per PCI
spec
–
High
10
25 2 0.97 2.32 0.18 0.74 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns
3.3 V
PCI-X
Per PCIX spec
–
High
10
25 2 0.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns
LVDS
24 mA
–
High
–
–
0.97 1.74 0.19 1.35
–
–
–
–
–
–
–
ns
LVPECL
24 mA
–
High
–
–
0.97 1.68 0.19 1.16
–
–
–
–
–
–
–
ns
Units
5
tZHS (ns)
High
tZLS (ns)
12
tHZ (ns)
100 µA
tLZ (ns)
3.3 V
LVCMOS
Wide
Range2
tZH (ns)
0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27 ns
tZL (ns)
–
tE O U T (ns)
5
tPY (ns)
External Resistor ()
High
tDIN (ns)
Capacitive Load (pF)
12
tDP (ns)
Slew Rate
12 mA
tDOUT (ns)
Equivalent Software Default
Drive Strength Option1 (mA)
3.3 V
LVTTL /
3.3 V
LVCMOS
I/O Standard
Drive Strength
Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case
Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard)
Applicable to Advanced I/O Banks
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed
in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity.
This resistor is not required during normal operation.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2 -2 8
R evi s i o n 27
IGLOO Low Power Flash FPGAs
High
5
–
0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51
ns
2.5 V
LVCMOS
12 mA
12
High
5
–
0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39
5.11
ns
1.8 V
LVCMOS
8 mA
8
High
5
–
0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36
ns
1.5 V
LVCMOS
4 mA
4
High
5
–
0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59
ns
3.3 V PCI
Per PCI
spec
–
High
10
25 2
0.97 1.97 0.18 0.73 0.66 2.01 1.50 2.36 2.79 5.61 5.10
ns
3.3 V
PCI-X
Per PCIX spec
–
High
10
25 2
0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10
ns
Units
tZHS (ns)
12
tZLS (ns)
100 µA
tHZ (ns)
3.3 V
LVCMOS
Wide
Range2
tLZ (ns)
ns
tZH (ns)
0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99
tZL (ns)
–
tE O U T (ns)
5
tPY (ns)
External Resistor ()
High
tDIN (ns)
Capacitive Load (pF)
12
tDP (ns)
Slew Rate
12 mA
tDOUT (ns)
Equivalent Software Default
Drive Strength Option1 (mA)
3.3 V
LVTTL /
3.3 V
LVCMOS
I/O Standard
Drive Strength
Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case
Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard)
Applicable to Standard Plus I/O Banks
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed
in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity.
This resistor is not required during normal operation.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
R ev i si o n 2 7
2-29
IGLOO DC and Switching Characteristics
Equivalent Software Default
Drive Strength Option1 (mA)
Slew Rate
Capacitive Load (pF)
External Resistor ()
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tE O U T (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
Units
3.3 V
LVTTL /
3.3 V
LVCMOS
8 mA
8
High
5
–
0.97
1.85
0.18
0.83
0.66
1.89
1.46
1.96
2.26
ns
3.3 V
LVCMOS
Wide
Range2
100 µA
8
High
5
–
0.97
2.62
0.18
1.17
0.66
2.63
2.02
2.79
3.17
ns
2.5 V
LVCMOS
8 mA
8
High
5
–
0.97
1.88
0.18
1.04
0.66
1.92
1.63
1.95
2.15
ns
1.8 V
LVCMOS
4 mA
4
High
5
–
0.97
2.18
0.18
0.98
0.66
2.22
1.93
1.97
2.06
ns
1.5 V
LVCMOS
2 mA
2
High
5
–
0.97
2.51
0.18
1.14
0.66
2.56
2.21
1.99
2.03
ns
I/O Standard
Drive Strength)
Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case
Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard)
Applicable to Standard I/O Banks
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed
in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2 -3 0
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Equivalent Software Default
Drive Strength Option1
Slew Rate
Capacitive Load (pF)
External Resistor ()
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tE O U T (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
tZLS (ns)
tZHS (ns)
Units
3.3 V
LVTTL /
3.3 V
LVCMOS
12 mA
12 mA
High
5
–
1.55
2.67
0.26
0.98
1.10
2.71
2.18
3.25
3.93
8.50
7.97
ns
3.3 V
LVCMOS
Wide
Range2
100 µA
12 mA
High
5
–
1.55
3.73
0.26
1.32
1.10
3.73
2.91
4.51
5.43
9.52
8.69
ns
2.5 V
LVCMOS
12 mA
12 mA
High
5
–
1.55
2.64
0.26
1.20
1.10
2.67
2.29
3.30
3.79
8.46
8.08
ns
1.8 V
LVCMOS
12 mA
12 mA
High
5
–
1.55
2.72
0.26
1.11
1.10
2.76
2.43
3.58
4.19
8.55
8.22
ns
1.5 V
LVCMOS
12 mA
12 mA
High
5
–
1.55
2.96
0.26
1.27
1.10
3.00
2.70
3.75
4.23
8.78
8.48
ns
1.2 V
LVCMOS
2 mA
2 mA
High
5
–
1.55
3.60
0.26
1.60
1.10
3.47
3.36
3.93
3.65
9.26
9.14
ns
1.2 V
LVCMOS
Wide
Range3
100 µA
2 mA
High
5
–
1.55
3.60
0.26
1.60
1.10
3.47
3.36
3.93
3.65
9.26
9.14
ns
3.3 V PCI
Per PCI
spec
–
High
10
252
1.55
2.91
0.26
0.86
1.10
2.95
2.29
3.25
3.93
8.74
8.08
ns
3.3 V
PCI-X
Per PCIX spec
–
High
10
252
1.55
2.91
0.25
0.86
1.10
2.95
2.29
3.25
3.93
8.74
8.08
ns
LVDS
24 mA
–
High
–
–
1.55
2.27
0.25
1.57
–
–
–
–
–
–
–
ns
LVPECL
24 mA
–
High
–
–
1.55
2.24
0.25
1.38
–
–
–
–
–
–
–
ns
I/O Standard
Drive Strength
Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case
Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard)
Applicable to Advanced I/O Banks
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity.
This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
R ev i si o n 2 7
2-31
IGLOO DC and Switching Characteristics
Equivalent Software Default
Drive Strength Option1 (mA)
Slew Rate
Capacitive Load (pF)
External Resistor ()
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tE O U T (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
tZLS (ns)
tZHS (ns)
Units
3.3 V
LVTTL /
3.3 V
LVCMOS
12 mA
12
High
5
–
1.55
2.31
0.26
0.97
1.10
2.34
1.86
2.93
3.64
8.12
7.65
ns
3.3 V
LVCMOS
Wide
Range2
100 µA
12
High
5
–
1.55
3.20
0.26
1.32
1.10
3.20
2.52
4.01
4.97
8.99
8.31
ns
2.5 V
LVCMOS
12 mA
12
High
5
–
1.55
2.29
0.26
1.19
1.10
2.32
1.94
2.94
3.52
8.10
7.73
ns
1.8 V
LVCMOS
8 mA
8
High
5
–
1.55
2.43
0.26
1.11
1.10
2.47
2.16
2.99
3.39
8.25
7.94
ns
1.5 V
LVCMOS
4 mA
4
High
5
–
1.55
2.68
0.26
1.27
1.10
2.72
2.39
3.07
3.37
8.50
8.18
ns
1.2 V
LVCMOS
2 mA
2
High
5
–
1.55
3.22
0.26
1.59
1.10
3.11
2.78
3.29
3.48
8.90
8.57
ns
1.2 V
LVCMOS
Wide
Range3
100 µA
2
High
5
–
1.55
3.22
0.26
1.59
1.10
3.11
2.78
3.29
3.48
8.90
8.57
ns
3.3 V PCI
Per PCI
spec
–
High
10
252
1.55
2.53
0.26
0.84
1.10
2.57
1.98
2.93
3.64
8.35
7.76
ns
Per
PCI-X
spec
–
High
10
252
1.55
2.53
0.25
0.85
1.10
2.57
1.98
2.93
3.64
8.35
7.76
ns
I/O Standard
Drive Strength
Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case
Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard)
Applicable to Standard Plus I/O Banks
3.3 V
PCI-X
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA.
Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity.
This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2 -3 2
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Equivalent Software Default
Drive Strength Option1 (mA)
Slew Rate
Capacitive Load (pF)
External Resistor ()
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tE O U T (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
Units
3.3 V
LVTTL /
3.3 V
LVCMOS
8 mA
8
High
5
–
1.55
2.38
0.26
0.94
1.10
2.41
1.92
2.40
2.96
ns
3.3 V
LVCMOS
Wide
Range3
100 µA
8
High
5
–
1.55
3.33
0.26
1.29
1.10
3.33
2.62
3.34
4.07
ns
2.5 V
LVCMOS
8 mA
8
High
5
–
1.55
2.39
0.26
1.15
1.10
2.42
2.05
2.38
2.80
ns
1.8 V
LVCMOS
4 mA
4
High
5
–
1.55
2.60
0.26
1.08
1.10
2.64
2.33
2.38
2.62
ns
1.5 V
LVCMOS
2 mA
2
High
5
–
1.55
2.92
0.26
1.22
1.10
2.96
2.60
2.40
2.56
ns
1.2 V
LVCMOS
1 mA
1
High
5
–
1.55
3.59
0.26
1.53
1.10
3.47
3.06
2.51
2.49
ns
1.2 V
LVCMOS
Wide
Range3
100 µA
1
High
5
–
1.55
3.59
0.26
1.53
1.10
3.47
3.06
2.51
2.49
ns
I/O Standard
Drive Strength
Table 2-36 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case
Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard)
Applicable to Standard I/O Banks
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA.
Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
R ev i si o n 2 7
2-33
IGLOO DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-37 • Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
CIN
Input capacitance
VIN = 0, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
8
pF
Table 2-38 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS4
1.2 V LVCMOS Wide Range4
3.3 V PCI/PCI-X
Drive Strength
RPULL-DOWN
()2
RPULL-UP
()3
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
100 A
Same as regular 3.3 V LVCMOS
Same as regular 3.3 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
2 mA
158
164
100 A
Same as regular 1.2 V LVCMOS
Same as regular 1.2 V LVCMOS
Per PCI/PCI-X
specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H spec
4. Applicable to IGLOO V2 Devices operating at VCCI VCC
2 -3 4
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-39 • I/O Output Buffer Maximum Resistances1
Applicable to Standard Plus I/O Banks
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
4
1.2 V LVCMOS
1.2 V LVCMOS Wide Range4
3.3 V PCI/PCI-X
Drive Strength
RPULL-DOWN
()2
RPULL-UP
()3
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
25
75
100 A
Same as regular 3.3 V LVCMOS
Same as regular 3.3 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
2 mA
200
224
4 mA
100
112
2 mA
158
164
100 A
Same as regular 1.2 V LVCMOS
Same as regular 1.2 V LVCMOS
Per PCI/PCI-X
specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H spec
4. Applicable to IGLOO V2 Devices operating at VCCI VCC
R ev i si o n 2 7
2-35
IGLOO DC and Switching Characteristics
Table 2-40 • I/O Output Buffer Maximum Resistances1
Applicable to Standard I/O Banks
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
4
Drive Strength
RPULL-DOWN
()2
RPULL-UP
()3
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
100 A
Same as regular 3.3 V LVCMOS
Same as regular 3.3 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
2 mA
200
225
4 mA
100
112
2 mA
200
224
1 mA
158
164
100 A
Same as regular 1.2 V LVCMOS
Same as regular 1.2 V LVCMOS
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H spec
Table 2-41 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
R(WEAK PULL-UP)1
()
R(WEAK PULL-DOWN)2
()
VCCI
Min.
Max.
Min.
Max.
3.3 V
10 K
45 K
10 K
45 K
3.3 V Wide Range I/Os
10 K
45 K
10 K
45 K
2.5 V
11 K
55 K
12 K
74 K
1.8 V
18 K
70 K
17 K
110 K
1.5 V
19 K
90 K
19 K
140 K
1.2 V
25 K
110 K
25 K
150 K
1.2 V Wide Range I/Os
19 K
110 K
19 K
150 K
Notes:
1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN)
2 -3 6
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-42 • I/O Short Currents IOSH/IOSL
Applicable to Advanced I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI/PCI-X
Drive Strength
IOSL (mA)*
IOSH (mA)*
2 mA
25
27
4 mA
25
27
6 mA
51
54
8 mA
51
54
12 mA
103
109
16 mA
132
127
24 mA
268
181
100 A
Same as regular 3.3 V LVCMOS
Same as regular 3.3 V LVCMOS
2 mA
16
18
4 mA
16
18
6 mA
32
37
8 mA
32
37
12 mA
65
74
16 mA
83
87
24 mA
169
124
2 mA
9
11
4 mA
17
22
6 mA
35
44
8 mA
45
51
12 mA
91
74
16 mA
91
74
2 mA
13
16
4 mA
25
33
6 mA
32
39
8 mA
66
55
12 mA
66
55
2 mA
20
26
100 A
20
26
Per PCI/PCI-X
specification
103
109
Note: *TJ = 100°C
R ev i si o n 2 7
2-37
IGLOO DC and Switching Characteristics
Table 2-43 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI/PCI-X
Drive Strength
IOSL (mA)*
IOSH (mA)*
2 mA
25
27
4 mA
25
27
6 mA
51
54
8 mA
51
54
12 mA
103
109
16 mA
103
109
100 A
Same as regular 3.3 V LVCMOS
Same as regular 3.3 V LVCMOS
2 mA
16
18
4 mA
16
18
6 mA
32
37
8 mA
32
37
12 mA
65
74
2 mA
9
11
4 mA
17
22
6 mA
35
44
8 mA
35
44
2 mA
13
16
4 mA
25
33
2 mA
20
26
100 A
20
26
Per PCI/PCI-X
specification
103
109
Note: *TJ = 100°C
2 -3 8
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-44 • I/O Short Currents IOSH/IOSL
Applicable to Standard I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
Drive Strength
IOSL (mA)*
IOSH (mA)*
2 mA
25
27
4 mA
25
27
6 mA
51
54
8 mA
51
54
100 A
Same as regular 3.3 V LVCMOS
Same as regular 3.3 V LVCMOS
2 mA
16
18
4 mA
16
18
6 mA
32
37
8 mA
32
37
2 mA
9
11
4 mA
17
22
1.5 V LVCMOS
2 mA
13
16
1.2 V LVCMOS
1 mA
20
26
100 A
20
26
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.2 V LVCMOS Wide Range
Note: *TJ = 100°C
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data
below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a
reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be
needed in extremely prolonged stress conditions.
Table 2-45 • Duration of Short Circuit Event before Failure
Temperature
Time before Failure
–40°C
> 20 years
–20°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
6 months
Table 2-46 • I/O Input Rise Time, Fall Time, and Related I/O Reliability1
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS
No requirement
10 ns *
20 years (100°C)
LVDS/B-LVDS/M-LVDS/
LVPECL
No requirement
10 ns *
10 years (100°C)
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time
and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible
the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
R ev i si o n 2 7
2-39
IGLOO DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It
uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V software macros comply with
LVCMOS 3.3 V wide range as specified in the JESD8a specification.
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
25
27
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.8
2
3.6
0.4
2.4
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
4
25
27
10
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
6
51
54
10
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
8
51
54
10
10
12 mA
–0.3
0.8
2
3.6
0.4
2.4
12
12
103
109
10
10
16 mA
–0.3
0.8
2
3.6
0.4
2.4
16
16
132
127
10
10
24 mA
–0.3
0.8
2
3.6
0.4
2.4
24
24
268
181
10
10
2
2
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges.
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-48 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1
IIH2
µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA
mA
Max.
mA3
Max.
mA3
2 mA
–0.3
0.8
2
3.6
0.4
2.4
2
2
25
27
10
10
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
4
25
27
10
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
6
51
54
10
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
8
51
54
10
10
12 mA
–0.3
0.8
2
3.6
0.4
2.4
12
12
103
109
10
10
16 mA
–0.3
0.8
2
3.6
0.4
2.4
16
16
103
109
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2 -4 0
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-49 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1
IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.8
2
3.6
0.4
2.4
2
2
25
27
10
10
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
4
25
27
10
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
6
51
54
10
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
8
51
54
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Test Point
Datapath
Figure 2-7 •
5 pF
R=1k
Test Point
Enable Path
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
AC Loading
Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
R ev i si o n 2 7
2-41
IGLOO DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
4.47
0.18
0.85
0.66
4.56
3.89
2.24
2.19
8.15
7.48
ns
4 mA
Std.
0.97
4.47
0.18
0.85
0.66
4.56
3.89
2.24
2.19
8.15
7.48
ns
6 mA
Std.
0.97
3.74
0.18
0.85
0.66
3.82
3.37
2.49
2.63
7.42
6.96
ns
8 mA
Std.
0.97
3.74
0.18
0.85
0.66
3.82
3.37
2.49
2.63
7.42
6.96
ns
12 mA
Std.
0.97
3.23
0.18
0.85
0.66
3.30
2.98
2.66
2.91
6.89
6.57
ns
16 mA
Std.
0.97
3.08
0.18
0.85
0.66
3.14
2.89
2.70
2.99
6.74
6.48
ns
24 mA
Std.
0.97
3.00
0.18
0.85
0.66
3.06
2.91
2.74
3.27
6.66
6.50
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
2.73
0.18
0.85
0.66
2.79
2.22
2.25
2.32
6.38
5.82
ns
4 mA
Std.
0.97
2.73
0.18
0.85
0.66
2.79
2.22
2.25
2.32
6.38
5.82
ns
6 mA
Std.
0.97
2.32
0.18
0.85
0.66
2.37
1.85
2.50
2.76
5.96
5.45
ns
8 mA
Std.
0.97
2.32
0.18
0.85
0.66
2.37
1.85
2.50
2.76
5.96
5.45
ns
12 mA
Std.
0.97
2.09
0.18
0.85
0.66
2.14
1.68
2.67
3.05
5.73
5.27
ns
16 mA
Std.
0.97
2.05
0.18
0.85
0.66
2.10
1.64
2.70
3.12
5.69
5.24
ns
24 mA
Std.
0.97
2.07
0.18
0.85
0.66
2.12
1.60
2.75
3.41
5.71
5.20
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
3.94
0.18
0.85
0.66
4.02
3.46
1.98
2.03
7.62
7.05
ns
4 mA
Std.
0.97
3.94
0.18
0.85
0.66
4.02
3.46
1.98
2.03
7.62
7.05
ns
6 mA
Std.
0.97
3.24
0.18
0.85
0.66
3.31
2.99
2.21
2.42
6.90
6.59
ns
8 mA
Std.
0.97
3.24
0.18
0.85
0.66
3.31
2.99
2.21
2.42
6.90
6.59
ns
12 mA
Std.
0.97
2.76
0.18
0.85
0.66
2.82
2.63
2.36
2.68
6.42
6.22
ns
16 mA
Std.
0.97
2.76
0.18
0.85
0.66
2.82
2.63
2.36
2.68
6.42
6.22
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2 -4 2
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
2.32
0.18
0.85
0.66
2.37
1.90
1.98
2.13
5.96
5.49
ns
4 mA
Std.
0.97
2.32
0.18
0.85
0.66
2.37
1.90
1.98
2.13
5.96
5.49
ns
6 mA
Std.
0.97
1.94
0.18
0.85
0.66
1.99
1.57
2.20
2.53
5.58
5.16
ns
8 mA
Std.
0.97
1.94
0.18
0.85
0.66
1.99
1.57
2.20
2.53
5.58
5.16
ns
12 mA
Std.
0.97
1.75
0.18
0.85
0.66
1.79
1.40
2.36
2.79
5.38
4.99
ns
16 mA
Std.
0.97
1.75
0.18
0.85
0.66
1.79
1.40
2.36
2.79
5.38
4.99
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.97
3.80
0.18
0.83
0.66
3.88
3.41
1.74
1.78
ns
4 mA
Std.
0.97
3.80
0.18
0.83
0.66
3.88
3.41
1.74
1.78
ns
6 mA
Std.
0.97
3.15
0.18
0.83
0.66
3.21
2.94
1.96
2.17
ns
8 mA
Std.
0.97
3.15
0.18
0.83
0.66
3.21
2.94
1.96
2.17
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.97
2.19
0.18
0.83
0.66
2.24
1.79
1.74
1.87
ns
4 mA
Std.
0.97
2.19
0.18
0.83
0.66
2.24
1.79
1.74
1.87
ns
6 mA
Std.
0.97
1.85
0.18
0.83
0.66
1.89
1.46
1.96
2.26
ns
8 mA
Std.
0.97
1.85
0.18
0.83
0.66
1.89
1.46
1.96
2.26
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
R ev i si o n 2 7
2-43
IGLOO DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
5.12
0.26
0.98
1.10
5.20
4.46
2.81
3.02
10.99
10.25
ns
4 mA
Std.
1.55
5.12
0.26
0.98
1.10
5.20
4.46
2.81
3.02
10.99
10.25
ns
6 mA
Std.
1.55
4.38
0.26
0.98
1.10
4.45
3.93
3.07
3.48
10.23
9.72
ns
8 mA
Std.
1.55
4.38
0.26
0.98
1.10
4.45
3.93
3.07
3.48
10.23
9.72
ns
12 mA
Std.
1.55
3.85
0.26
0.98
1.10
3.91
3.53
3.24
3.77
9.69
9.32
ns
16 mA
Std.
1.55
3.69
0.26
0.98
1.10
3.75
3.44
3.28
3.84
9.54
9.23
ns
24 mA
Std.
1.55
3.61
0.26
0.98
1.10
3.67
3.46
3.33
4.13
9.45
9.24
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
3.33
0.26
0.98
1.10
3.38
2.75
2.82
3.18
9.17
8.54
ns
4 mA
Std.
1.55
3.33
0.26
0.98
1.10
3.38
2.75
2.82
3.18
9.17
8.54
ns
6 mA
Std.
1.55
2.91
0.26
0.98
1.10
2.95
2.37
3.07
3.64
8.73
8.15
ns
8 mA
Std.
1.55
2.91
0.26
0.98
1.10
2.95
2.37
3.07
3.64
8.73
8.15
ns
12 mA
Std.
1.55
2.67
0.26
0.98
1.10
2.71
2.18
3.25
3.93
8.50
7.97
ns
16 mA
Std.
1.55
2.63
0.26
0.98
1.10
2.67
2.14
3.28
4.01
8.45
7.93
ns
24 mA
Std.
1.55
2.65
0.26
0.98
1.10
2.69
2.10
3.33
4.31
8.47
7.89
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
4.56
0.26
0.97
1.10
4.63
3.98
2.54
2.83
10.42
9.76
ns
4 mA
Std.
1.55
4.56
0.26
0.97
1.10
4.63
3.98
2.54
2.83
10.42
9.76
ns
6 mA
Std.
1.55
3.84
0.26
0.97
1.10
3.90
3.50
2.77
3.24
9.69
9.29
ns
8 mA
Std.
1.55
3.84
0.26
0.97
1.10
3.90
3.50
2.77
3.24
9.69
9.29
ns
12 mA
Std.
1.55
3.35
0.26
0.97
1.10
3.40
3.13
2.93
3.51
9.19
8.91
ns
16 mA
Std.
1.55
3.35
0.26
0.97
1.10
3.40
3.13
2.93
3.51
9.19
8.91
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -4 4
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
2.89
0.26
0.97
1.10
2.93
2.38
2.53
2.96
8.72
8.17
ns
4 mA
Std.
1.55
2.89
0.26
0.97
1.10
2.93
2.38
2.53
2.96
8.72
8.17
ns
6 mA
Std.
1.55
2.50
0.26
0.97
1.10
2.54
2.04
2.77
3.37
8.33
7.82
ns
8 mA
Std.
1.55
2.50
0.26
0.97
1.10
2.54
2.04
2.77
3.37
8.33
7.82
ns
12 mA
Std.
1.55
2.31
0.26
0.97
1.10
2.34
1.86
2.93
3.64
8.12
7.65
ns
16 mA
Std.
1.55
2.31
0.26
0.97
1.10
2.34
1.86
2.93
3.64
8.12
7.65
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
1.55
4.39
0.26
0.94
1.10
4.46
3.91
2.17
2.44
ns
4 mA
Std.
1.55
4.39
0.26
0.94
1.10
4.46
3.91
2.17
2.44
ns
6 mA
Std.
1.55
3.72
0.26
0.94
1.10
3.78
3.43
2.40
2.85
ns
8 mA
Std.
1.55
3.72
0.26
0.94
1.10
3.78
3.43
2.40
2.85
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-62 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
1.55
2.74
0.26
0.94
1.10
2.78
2.26
2.17
2.55
ns
4 mA
Std.
1.55
2.74
0.26
0.94
1.10
2.78
2.26
2.17
2.55
ns
6 mA
Std.
1.55
2.38
0.26
0.94
1.10
2.41
1.92
2.40
2.96
ns
8 mA
Std.
1.55
2.38
0.26
0.94
1.10
2.41
1.92
2.40
2.96
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
R ev i si o n 2 7
2-45
IGLOO DC and Switching Characteristics
3.3 V LVCMOS Wide Range
Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Advanced I/O Banks
3.3 V LVCMOS Wide Range
Drive
Strength
Equivalent
Software
Default Drive
Strength
Option1
VIL
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL2 IIH3
Max.
V
Max.
V
Min.
V
µA
µA
Max.
mA4
Max.
mA4
µA5 µA5
VIH
Min.
Min.
V Max. V V
100 µA
2 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
25
27
10
10
100 µA
4 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
25
27
10
10
100 µA
6 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
51
54
10
10
100 µA
8 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
51
54
10
10
100 µA
12 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
103
109
10
10
100 µA
16 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
132
127
10
10
100 µA
24 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100
100
268
181
10
10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
2 -4 6
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Standard Plus I/O Banks
3.3 V LVCMOS Wide Range
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL2 IIH3
Min.
V
µA
Max.
mA4
Max.
mA4
µA5 µA5
Equivalent
Software
Default Drive
Strength
Option1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
100 µA
2 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
25
27
10
10
100 µA
4 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
25
27
10
10
100 µA
6 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
51
54
10
10
100 µA
8 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
51
54
10
10
100 µA
12 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
103
109
10
10
100 µA
16 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
103
109
10
10
Drive
Strength
µA
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
R ev i si o n 2 7
2-47
IGLOO DC and Switching Characteristics
Table 2-65 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Standard I/O Banks
3.3 V LVCMOS Wide Range
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL2 IIH3
Min.
V
µA
µA
Max.
mA4
Max.
mA4
µA5 µA5
Equivalent
Software
Default Drive
Strength
Option1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
100 µA
2 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100
100
25
27
10
10
100 µA
4 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100
100
25
27
10
10
100 µA
6 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100
100
51
54
10
10
100 µA
8 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100
100
51
54
10
10
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
4. Currents are measured at 100°C junction temperature and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Table 2-66 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
3.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
2 -4 8
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-67 •
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
0.97
6.61
0.18
1.19
0.66
6.63
5.63
3.15
2.98
10.22
9.23
ns
100 µA
4 mA
Std.
0.97
6.61
0.18
1.19
0.66
6.63
5.63
3.15
2.98
10.22
9.23
ns
100 µA
6 mA
Std.
0.97
5.49
0.18
1.19
0.66
5.51
4.84
3.54
3.66
9.10
8.44
ns
100 µA
8 mA
Std.
0.97
5.49
0.18
1.19
0.66
5.51
4.84
3.54
3.66
9.10
8.44
ns
100 µA
12 mA
Std.
0.97
4.69
0.18
1.19
0.66
4.71
4.25
3.80
4.10
8.31
7.85
ns
100 µA
16 mA
Std.
0.97
4.46
0.18
1.19
0.66
4.48
4.11
3.86
4.21
8.07
7.71
ns
100 µA
24 mA
Std.
0.97
4.34
0.18
1.19
0.66
4.36
4.14
3.93
4.64
7.95
7.74
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-68 •
3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
0.97
3.92
0.18
1.19
0.66
3.94
3.10
3.16
3.17
7.54
6.70
ns
100 µA
4 mA
Std.
0.97
3.92
0.18
1.19
0.66
3.94
3.10
3.16
3.17
7.54
6.70
ns
100 µA
6 mA
Std.
0.97
3.28
0.18
1.19
0.66
3.30
2.54
3.54
3.86
6.90
6.14
ns
100 µA
8 mA
Std.
0.97
3.28
0.18
1.19
0.66
3.30
2.54
3.54
3.86
6.90
6.14
ns
100 µA
12 mA
Std.
0.97
2.93
0.18
1.19
0.66
2.95
2.27
3.81
4.30
6.54
5.87
ns
100 µA
16 mA
Std.
0.97
2.87
0.18
1.19
0.66
2.89
2.22
3.86
4.41
6.49
5.82
ns
100 µA
24 mA
Std.
0.97
2.90
0.18
1.19
0.66
2.92
2.16
3.94
4.86
6.51
5.75
ns
Drive
Strength
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Software default selection highlighted in gray.
3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
R ev i si o n 2 7
2-49
IGLOO DC and Switching Characteristics
Table 2-69 •
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Plus Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
0.97
5.84
0.18
1.20
0.66
5.86
5.04
2.74
2.71
9.46
8.64
ns
100 µA
4 mA
Std.
0.97
5.84
0.18
1.20
0.66
5.86
5.04
2.74
2.71
9.46
8.64
ns
100 µA
6 mA
Std.
0.97
4.76
0.18
1.20
0.66
4.78
4.33
3.09
3.33
8.37
7.93
ns
100 µA
8 mA
Std.
0.97
4.76
0.18
1.20
0.66
4.78
4.33
3.09
3.33
8.37
7.93
ns
100 µA
12 mA
Std.
0.97
4.02
0.18
1.20
0.66
4.04
3.78
3.33
3.73
7.64
7.37
ns
100 µA
16 mA
Std.
0.97
4.02
0.18
1.20
0.66
4.04
3.78
3.33
3.73
7.64
7.37
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-70 •
3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Plus Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
0.97
3.33
0.18
1.20
0.66
3.35
2.68
2.73
2.88
6.94
6.27
ns
100 µA
4 mA
Std.
0.97
3.33
0.18
1.20
0.66
3.35
2.68
2.73
2.88
6.94
6.27
ns
100 µA
6 mA
Std.
0.97
2.75
0.18
1.20
0.66
2.77
2.17
3.08
3.50
6.36
5.77
ns
100 µA
8 mA
Std.
0.97
2.75
0.18
1.20
0.66
2.77
2.17
3.08
3.50
6.36
5.77
ns
100 µA
12 mA
Std.
0.97
2.45
0.18
1.20
0.66
2.47
1.92
3.33
3.90
6.06
5.51
ns
100 µA
16 mA
Std.
0.97
2.45
0.18
1.20
0.66
2.47
1.92
3.33
3.90
6.06
5.51
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
2 -5 0
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-71 •
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
100 µA
2 mA
Std.
0.97
5.64
0.18
1.17
0.66
5.65
4.98
2.45
2.42
ns
100 µA
4 mA
Std.
0.97
5.64
0.18
1.17
0.66
5.65
4.98
2.45
2.42
ns
100 µA
6 mA
Std.
0.97
4.63
0.18
1.17
0.66
4.64
4.26
2.80
3.02
ns
100 µA
8 mA
Std.
0.97
4.63
0.18
1.17
0.66
4.64
4.26
2.80
3.02
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-72 •
3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
100 µA
2 mA
0.97
3.16
0.18
1.17
0.66
3.17
2.53
2.45
2.56
0.97
ns
100 µA
4 mA
0.97
3.16
0.18
1.17
0.66
3.17
2.53
2.45
2.56
0.97
ns
100 µA
6 mA
0.97
2.62
0.18
1.17
0.66
2.63
2.02
2.79
3.17
0.97
ns
100 µA
8 mA
0.97
2.62
0.18
1.17
0.66
2.63
2.02
2.79
3.17
0.97
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
R ev i si o n 2 7
2-51
IGLOO DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-73 •
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
1.55
7.52
0.26
1.32
1.10
7.52
6.38
3.84
4.02
13.31
12.16
ns
100 µA
4 mA
Std.
1.55
7.52
0.26
1.32
1.10
7.52
6.38
3.84
4.02
13.31
12.16
ns
100 µA
6 mA
Std.
1.55
6.37
0.26
1.32
1.10
6.37
5.57
4.23
4.73
12.16
11.35
ns
100 µA
8 mA
Std.
1.55
6.37
0.26
1.32
1.10
6.37
5.57
4.23
4.73
12.16
11.35
ns
100 µA
12 mA
Std.
1.55
5.55
0.26
1.32
1.10
5.55
4.96
4.50
5.18
11.34
10.75
ns
100 µA
16 mA
Std.
1.55
5.32
0.26
1.32
1.10
5.32
4.82
4.56
5.29
11.10
10.61
ns
100 µA
24 mA
Std.
1.55
5.19
0.26
1.32
1.10
5.19
4.85
4.63
5.74
10.98
10.63
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-74 •
3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Advanced Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
1.55
4.75
0.26
1.32
1.10
4.75
3.77
3.84
4.27
10.54
9.56
ns
100 µA
4 mA
Std.
1.55
4.75
0.26
1.32
1.10
4.75
3.77
3.84
4.27
10.54
9.56
ns
100 µA
6 mA
Std.
1.55
4.10
0.26
1.32
1.10
4.10
3.19
4.24
4.98
9.88
8.98
ns
100 µA
8 mA
Std.
1.55
4.10
0.26
1.32
1.10
4.10
3.19
4.24
4.98
9.88
8.98
ns
100 µA
12 mA
Std.
1.55
3.73
0.26
1.32
1.10
3.73
2.91
4.51
5.43
9.52
8.69
ns
100 µA
16 mA
Std.
1.55
3.67
0.26
1.32
1.10
3.67
2.85
4.57
5.55
9.46
8.64
ns
100 µA
24 mA
Std.
1.55
3.70
0.26
1.32
1.10
3.70
2.79
4.65
6.01
9.49
8.58
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
2 -5 2
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-75 •
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Plus Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
1.55
6.69
0.26
1.32
1.10
6.69
5.73
3.41
3.72
12.48
11.52
ns
100 µA
4 mA
Std.
1.55
6.69
0.26
1.32
1.10
6.69
5.73
3.41
3.72
12.48
11.52
ns
100 µA
6 mA
Std.
1.55
5.58
0.26
1.32
1.10
5.58
5.01
3.77
4.35
11.36
10.79
ns
100 µA
8 mA
Std.
1.55
5.58
0.26
1.32
1.10
5.58
5.01
3.77
4.35
11.36
10.79
ns
100 µA
12 mA
Std.
1.55
4.82
0.26
1.32
1.10
4.82
4.44
4.02
4.76
10.61
10.23
ns
100 µA
16 mA
Std.
1.55
4.82
0.26
1.32
1.10
4.82
4.44
4.02
4.76
10.61
10.23
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-76 •
3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Plus Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
100 µA
2 mA
Std.
1.55
4.10
0.26
1.32
1.10
4.10
3.30
3.40
3.92
9.89
9.09
ns
100 µA
4 mA
Std.
1.55
4.10
0.26
1.32
1.10
4.10
3.30
3.40
3.92
9.89
9.09
ns
100 µA
6 mA
Std.
1.55
3.51
0.26
1.32
1.10
3.51
2.79
3.76
4.56
9.30
8.57
ns
100 µA
8 mA
Std.
1.55
3.51
0.26
1.32
1.10
3.51
2.79
3.76
4.56
9.30
8.57
ns
100 µA
12 mA
Std.
1.55
3.20
0.26
1.32
1.10
3.20
2.52
4.01
4.97
8.99
8.31
ns
100 µA
16 mA
Std.
1.55
3.20
0.26
1.32
1.10
3.20
2.52
4.01
4.97
8.99
8.31
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
R ev i si o n 2 7
2-53
IGLOO DC and Switching Characteristics
Table 2-77 •
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
100 µA
2 mA
Std.
1.55
6.44
0.26
1.29
1.10
6.44
5.64
2.99
3.28
ns
100 µA
4 mA
Std.
1.55
6.44
0.26
1.29
1.10
6.44
5.64
2.99
3.28
ns
100 µA
6 mA
Std.
1.55
5.41
0.26
1.29
1.10
5.41
4.91
3.35
3.89
ns
100 µA
8 mA
Std.
1.55
5.41
0.26
1.29
1.10
5.41
4.91
3.35
3.89
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-78 •
3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
Applicable to Standard Banks
Equivalent
Software
Default Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
100 µA
2 mA
Std.
1.55
3.89
0.26
1.29
1.10
3.89
3.13
2.99
3.45
ns
100 µA
4 mA
Std.
1.55
3.89
0.26
1.29
1.10
3.89
3.13
2.99
3.45
ns
100 µA
6 mA
Std.
1.55
3.33
0.26
1.29
1.10
3.33
2.62
3.34
4.07
ns
100 µA
8 mA
Std.
1.55
3.33
0.26
1.29
1.10
3.33
2.62
3.34
4.07
ns
Drive
Strength
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths
displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
2 -5 4
R evi s i o n 27
IGLOO Low Power Flash FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V
applications.
Table 2-79 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1
IIH2
mA mA
Max.
mA3
Max.
mA3
µA4
µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.7
1.7
2.7
0.7
1.7
2
2
16
18
10
10
4 mA
–0.3
0.7
1.7
2.7
0.7
1.7
4
4
16
18
10
10
6 mA
–0.3
0.7
1.7
2.7
0.7
1.7
6
6
32
37
10
10
8 mA
–0.3
0.7
1.7
2.7
0.7
1.7
8
8
32
37
10
10
12 mA
–0.3
0.7
1.7
2.7
0.7
1.7
12
12
65
74
10
10
16 mA
–0.3
0.7
1.7
2.7
0.7
1.7
16
16
83
87
10
10
24 mA
–0.3
0.7
1.7
2.7
0.7
1.7
24
24
169
124
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-80 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSH
IOSL
IIL1
IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA
mA
Max.
mA3
Max.
mA3
µA4
µA4
2 mA
–0.3
0.7
1.7
2.7
0.7
1.7
2
2
16
18
10
10
4 mA
–0.3
0.7
1.7
2.7
0.7
1.7
4
4
16
18
10
10
6 mA
–0.3
0.7
1.7
2.7
0.7
1.7
6
6
32
37
10
10
8 mA
–0.3
0.7
1.7
2.7
0.7
1.7
8
8
32
37
10
10
12 mA
–0.3
0.7
1.7
2.7
0.7
1.7
12
12
65
74
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R ev i si o n 2 7
2-55
IGLOO DC and Switching Characteristics
Table 2-81 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1
IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA
mA
Max.
mA3
Max.
mA3
µA4
µA4
2 mA
–0.3
0.7
1.7
3.6
0.7
1.7
2
2
16
18
10
10
4 mA
–0.3
0.7
1.7
3.6
0.7
1.7
4
4
16
18
10
10
6 mA
–0.3
0.7
1.7
3.6
0.7
1.7
6
6
32
37
10
10
8 mA
–0.3
0.7
1.7
3.6
0.7
1.7
8
8
32
37
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Test Point
Datapath
Figure 2-8 •
5 pF
R=1k
Test Point
Enable Path
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
AC Loading
Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
2.5
1.2
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
2 -5 6
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-83 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
4.96
0.18
1.08
0.66
5.06
4.59
2.26
2.00
8.66
8.19
ns
4 mA
Std.
0.97
4.96
0.18
1.08
0.66
5.06
4.59
2.26
2.00
8.66
8.19
ns
6 mA
Std.
0.97
4.15
0.18
1.08
0.66
4.24
3.94
2.54
2.51
7.83
7.53
ns
8 mA
Std.
0.97
4.15
0.18
1.08
0.66
4.24
3.94
2.54
2.51
7.83
7.53
ns
12 mA
Std.
0.97
3.57
0.18
1.08
0.66
3.65
3.47
2.73
2.84
7.24
7.06
ns
16 mA
Std.
0.97
3.39
0.18
1.08
0.66
3.46
3.36
2.78
2.92
7.06
6.95
ns
24 mA
Std.
0.97
3.38
0.18
1.08
0.66
3.38
3.38
2.83
3.25
6.98
6.98
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-84 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
2.77
0.18
1.08
0.66
2.83
2.60
2.26
2.08
6.42
6.19
ns
4 mA
Std.
0.97
2.77
0.18
1.08
0.66
2.83
2.60
2.26
2.08
6.42
6.19
ns
6 mA
Std.
0.97
2.34
0.18
1.08
0.66
2.39
2.08
2.54
2.60
5.99
5.68
ns
8 mA
Std.
0.97
2.34
0.18
1.08
0.66
2.39
2.08
2.54
2.60
5.99
5.68
ns
12 mA
Std.
0.97
2.09
0.18
1.08
0.66
2.14
1.83
2.73
2.93
5.73
5.43
ns
16 mA
Std.
0.97
2.05
0.18
1.08
0.66
2.09
1.78
2.78
3.02
5.69
5.38
ns
24 mA
Std.
0.97
2.06
0.18
1.08
0.66
2.10
1.72
2.83
3.35
5.70
5.32
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-85 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
4.42
0.18
1.08
0.66
4.51
4.10
1.96
1.85
8.10
7.69
ns
4 mA
Std.
0.97
4.42
0.18
1.08
0.66
4.51
4.10
1.96
1.85
8.10
7.69
ns
6 mA
Std.
0.97
3.62
0.18
1.08
0.66
3.70
3.52
2.21
2.32
7.29
7.11
ns
8 mA
Std.
0.97
3.62
0.18
1.08
0.66
3.70
3.52
2.21
2.32
7.29
7.11
ns
12 mA
Std.
0.97
3.09
0.18
1.08
0.66
3.15
3.09
2.39
2.61
6.74
6.68
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
R ev i si o n 2 7
2-57
IGLOO DC and Switching Characteristics
Table 2-86 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
2.36
0.18
1.08
0.66
2.41
2.21
1.96
1.92
6.01
5.81
ns
4 mA
Std.
0.97
2.36
0.18
1.08
0.66
2.41
2.21
1.96
1.92
6.01
5.81
ns
6 mA
Std.
0.97
1.97
0.18
1.08
0.66
2.01
1.75
2.21
2.40
5.61
5.34
ns
8 mA
Std.
0.97
1.97
0.18
1.08
0.66
2.01
1.75
2.21
2.40
5.61
5.34
ns
12 mA
Std.
0.97
1.75
0.18
1.08
0.66
1.79
1.52
2.38
2.70
5.39
5.11
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-87 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.97
4.27
0.18
1.04
0.66
4.36
4.06
1.71
1.62
ns
4 mA
Std.
0.97
4.27
0.18
1.04
0.66
4.36
4.06
1.71
1.62
ns
6 mA
Std.
0.97
3.54
0.18
1.04
0.66
3.61
3.48
1.95
2.08
ns
8 mA
Std.
0.97
3.54
0.18
1.04
0.66
3.61
3.48
1.95
2.08
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-88 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.97
2.24
0.18
1.04
0.66
2.29
2.09
1.71
1.68
ns
4 mA
Std.
0.97
2.24
0.18
1.04
0.66
2.29
2.09
1.71
1.68
ns
6 mA
Std.
0.97
1.88
0.18
1.04
0.66
1.92
1.63
1.95
2.15
ns
8 mA
Std.
0.97
1.88
0.18
1.04
0.66
1.92
1.63
1.95
2.15
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2 -5 8
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Applies to 1.2 V Core Voltage
Table 2-89 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
5.59
0.26
1.20
1.10
5.68
5.14
2.82
2.80
11.47
10.93
ns
4 mA
Std.
1.55
5.59
0.26
1.20
1.10
5.68
5.14
2.82
2.80
11.47
10.93
ns
6 mA
Std.
1.55
4.76
0.26
1.20
1.10
4.84
4.47
3.10
3.33
10.62
10.26
ns
8 mA
Std.
1.55
4.76
0.26
1.20
1.10
4.84
4.47
3.10
3.33
10.62
10.26
ns
12 mA
Std.
1.55
4.17
0.26
1.20
1.10
4.23
3.99
3.30
3.67
10.02
9.77
ns
16 mA
Std.
1.55
3.98
0.26
1.20
1.10
4.04
3.88
3.34
3.76
9.83
9.66
ns
24 mA
Std.
1.55
3.90
0.26
1.20
1.10
3.96
3.90
3.40
4.09
9.75
9.68
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-90 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
3.33
0.26
1.20
1.10
3.38
3.09
2.82
2.91
9.17
8.88
ns
4 mA
Std.
1.55
3.33
0.26
1.20
1.10
3.38
3.09
2.82
2.91
9.17
8.88
ns
6 mA
Std.
1.55
2.89
0.26
1.20
1.10
2.93
2.56
3.10
3.45
8.72
8.34
ns
8 mA
Std.
1.55
2.89
0.26
1.20
1.10
2.93
2.56
3.10
3.45
8.72
8.34
ns
12 mA
Std.
1.55
2.64
0.26
1.20
1.10
2.67
2.29
3.30
3.79
8.46
8.08
ns
16 mA
Std.
1.55
2.59
0.26
1.20
1.10
2.63
2.24
3.34
3.88
8.41
8.03
ns
24 mA
Std.
1.55
2.60
0.26
1.20
1.10
2.64
2.18
3.40
4.22
8.42
7.97
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-91 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
5.02
0.26
1.19
1.10
5.11
4.60
2.50
2.62
10.89
10.38
ns
4 mA
Std.
1.55
5.02
0.26
1.19
1.10
5.11
4.60
2.50
2.62
10.89
10.38
ns
6 mA
Std.
1.55
4.21
0.26
1.19
1.10
4.27
4.00
2.76
3.10
10.06
9.79
ns
8 mA
Std.
1.55
4.21
0.26
1.19
1.10
4.27
4.00
2.76
3.10
10.06
9.79
ns
12 mA
Std.
1.55
3.66
0.26
1.19
1.10
3.71
3.55
2.94
3.41
9.50
9.34
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
R ev i si o n 2 7
2-59
IGLOO DC and Switching Characteristics
Table 2-92 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
2.91
0.26
1.19
1.10
2.95
2.66
2.50
2.72
8.74
8.45
ns
4 mA
Std.
1.55
2.91
0.26
1.19
1.10
2.95
2.66
2.50
2.72
8.74
8.45
ns
6 mA
Std.
1.55
2.51
0.26
1.19
1.10
2.54
2.18
2.75
3.21
8.33
7.97
ns
8 mA
Std.
1.55
2.51
0.26
1.19
1.10
2.54
2.18
2.75
3.21
8.33
7.97
ns
12 mA
Std.
1.55
2.29
0.26
1.19
1.10
2.32
1.94
2.94
3.52
8.10
7.73
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-93 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
1.55
4.85
0.26
1.15
1.10
4.93
4.55
2.13
2.24
ns
4 mA
Std.
1.55
4.85
0.26
1.15
1.10
4.93
4.55
2.13
2.24
ns
6 mA
Std.
1.55
4.09
0.26
1.15
1.10
4.16
3.95
2.38
2.71
ns
8 mA
Std.
1.55
4.09
0.26
1.15
1.10
4.16
3.95
2.38
2.71
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-94 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
1.55
2.76
0.26
1.15
1.10
2.80
2.52
2.13
2.32
ns
4 mA
Std.
1.55
2.76
0.26
1.15
1.10
2.80
2.52
2.13
2.32
ns
6 mA
Std.
1.55
2.39
0.26
1.15
1.10
2.42
2.05
2.38
2.80
ns
8 mA
Std.
1.55
2.39
0.26
1.15
1.10
2.42
2.05
2.38
2.80
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -6 0
R evi s i o n 27
IGLOO Low Power Flash FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V
applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-95 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
2
2
9
11
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
4
4
17
22
10
10
6 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
6
6
35
44
10
10
8 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
8
8
45
51
10
10
12 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
12
12
91
74
10
10
16 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
16
16
91
74
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-96 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1 IIH2
µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA
mA
Max.
mA3
Max.
mA3
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
2
2
9
11
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
4
4
17
22
10
10
6 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
6
6
35
44
10
10
8 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
8
8
35
44
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R ev i si o n 2 7
2-61
IGLOO DC and Switching Characteristics
Table 2-97 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
2
9
11
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
4
17
22
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R=1k
Test Point
Enable Path
Test Point
Datapath
Figure 2-9 •
5 pF
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
AC Loading
Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
1.8
0.9
5
0
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-99 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
6.38
0.18
1.01
0.66
6.51
5.93
2.33
1.56
10.10
9.53
ns
4 mA
Std.
0.97
5.35
0.18
1.01
0.66
5.46
5.04
2.67
2.38
9.05
8.64
ns
6 mA
Std.
0.97
4.62
0.18
1.01
0.66
4.71
4.44
2.90
2.79
8.31
8.04
ns
8 mA
Std.
0.97
4.37
0.18
1.01
0.66
4.46
4.31
2.95
2.89
8.05
7.90
ns
12 mA
Std.
0.97
4.32
0.18
1.01
0.66
4.37
4.32
3.03
3.30
7.97
7.92
ns
16 mA
Std.
0.97
4.32
0.18
1.01
0.66
4.37
4.32
3.03
3.30
7.97
7.92
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2 -6 2
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-100 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
3.25
0.18
1.01
0.66
3.21
3.25
2.33
1.61
6.80
6.85
ns
4 mA
Std.
0.97
2.62
0.18
1.01
0.66
2.68
2.51
2.66
2.46
6.27
6.11
ns
6 mA
Std.
0.97
2.31
0.18
1.01
0.66
2.36
2.15
2.90
2.87
5.95
5.75
ns
8 mA
Std.
0.97
2.25
0.18
1.01
0.66
2.30
2.08
2.95
2.98
5.89
5.68
ns
12 mA
Std.
0.97
2.24
0.18
1.01
0.66
2.29
2.00
3.02
3.40
5.88
5.60
ns
16 mA
Std.
0.97
2.24
0.18
1.01
0.66
2.29
2.00
3.02
3.40
5.88
5.60
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-101 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
5.78
0.18
1.01
0.66
5.90
5.32
1.95
1.47
9.49
8.91
ns
4 mA
Std.
0.97
4.75
0.18
1.01
0.66
4.85
4.54
2.25
2.21
8.44
8.13
ns
6 mA
Std.
0.97
4.07
0.18
1.01
0.66
4.15
3.98
2.46
2.58
7.75
7.57
ns
8 mA
Std.
0.97
4.07
0.18
1.01
0.66
4.15
3.98
2.46
2.58
7.75
7.57
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-102 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.97
2.76
0.18
1.01
0.66
2.79
2.76
1.94
1.51
6.39
6.35
ns
4 mA
Std.
0.97
2.25
0.18
1.01
0.66
2.30
2.09
2.24
2.29
5.89
5.69
ns
6 mA
Std.
0.97
1.97
0.18
1.01
0.66
2.02
1.76
2.46
2.66
5.61
5.36
ns
8 mA
Std.
0.97
1.97
0.18
1.01
0.66
2.02
1.76
2.46
2.66
5.61
5.36
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-103 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.97
5.63
0.18
0.98
0.66
5.74
5.30
1.68
1.24
ns
4 mA
Std.
0.97
4.69
0.18
0.98
0.66
4.79
4.52
1.97
1.98
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
R ev i si o n 2 7
2-63
IGLOO DC and Switching Characteristics
Table 2-104 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
2.62
0.18
0.98
0.66
2.67
2.59
1.67
1.29
2.62
ns
4 mA
Std.
2.18
0.18
0.98
0.66
2.22
1.93
1.97
2.06
2.18
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-105 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
6.97
0.26
1.11
1.10
7.08
6.48
2.87
2.29
12.87
12.27
ns
4 mA
Std.
1.55
5.91
0.26
1.11
1.10
6.01
5.57
3.21
3.14
11.79
11.36
ns
6 mA
Std.
1.55
5.16
0.26
1.11
1.10
5.24
4.95
3.45
3.55
11.03
10.74
ns
8 mA
Std.
1.55
4.90
0.26
1.11
1.10
4.98
4.81
3.50
3.66
10.77
10.60
ns
12 mA
Std.
1.55
4.83
0.26
1.11
1.10
4.90
4.83
3.58
4.08
10.68
10.61
ns
16 mA
Std.
1.55
4.83
0.26
1.11
1.10
4.90
4.83
3.58
4.08
10.68
10.61
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-106 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
3.73
0.26
1.11
1.10
3.71
3.73
2.86
2.34
9.49
9.51
ns
4 mA
Std.
1.55
3.12
0.26
1.11
1.10
3.16
2.97
3.21
3.22
8.95
8.75
ns
6 mA
Std.
1.55
2.79
0.26
1.11
1.10
2.83
2.59
3.45
3.65
8.62
8.38
ns
8 mA
Std.
1.55
2.73
0.26
1.11
1.10
2.77
2.52
3.50
3.75
8.56
8.30
ns
12 mA
Std.
1.55
2.72
0.26
1.11
1.10
2.76
2.43
3.58
4.19
8.55
8.22
ns
16 mA
Std.
1.55
2.72
0.26
1.11
1.10
2.76
2.43
3.58
4.19
8.55
8.22
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -6 4
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-107 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
6.32
0.26
1.11
1.10
6.43
5.81
2.47
2.16
12.22
11.60
ns
4 mA
Std.
1.55
5.27
0.26
1.11
1.10
5.35
5.01
2.78
2.92
11.14
10.79
ns
6 mA
Std.
1.55
4.56
0.26
1.11
1.10
4.64
4.44
3.00
3.30
10.42
10.22
ns
8 mA
Std.
1.55
4.56
0.26
1.11
1.10
4.64
4.44
3.00
3.30
10.42
10.22
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-108 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
1.55
3.22
0.26
1.11
1.10
3.26
3.18
2.47
2.20
9.05
8.97
ns
4 mA
Std.
1.55
2.72
0.26
1.11
1.10
2.75
2.50
2.78
3.01
8.54
8.29
ns
6 mA
Std.
1.55
2.43
0.26
1.11
1.10
2.47
2.16
2.99
3.39
8.25
7.94
ns
8 mA
Std.
1.55
2.43
0.26
1.11
1.10
2.47
2.16
2.99
3.39
8.25
7.94
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-109 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
1.55
6.13
0.26
1.08
1.10
6.24
5.79
2.08
1.78
ns
4 mA
Std.
1.55
5.17
0.26
1.08
1.10
5.26
4.98
2.38
2.54
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-110 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Banks
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
3.06
0.26
1.08
1.10
3.10
3.01
2.08
1.83
3.06
ns
4 mA
Std.
2.60
0.26
1.08
1.10
2.64
2.33
2.38
2.62
2.60
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
R ev i si o n 2 7
2-65
IGLOO DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V
applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-111 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3 µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
2
2
13
16
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
4
4
25
33
10
10
6 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
6
6
32
39
10
10
8 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
8
8
66
55
10
10
12 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
12
12
66
55
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-112 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
2
2
13
16
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI
0.75 * VCCI
4
4
25
33
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when
operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2 -6 6
R evi s i o n 27
IGLOO Low Power Flash FPGAs
Table 2-113 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
13
16
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.25 * VCCI
0.75 * VCCI
2
2
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN
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