dsPIC33F Family
Data Sheet
High-Performance, 16-Bit
Digital Signal Controllers
© 2007 Microchip Technology Inc.
DS70165E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS70165E-page ii
© 2007 Microchip Technology Inc.
dsPIC33F
High-Performance, 16-bit Digital Signal Controllers
Operating Range:
Digital I/O:
• DC – 40 MIPS (40 MIPS @ 3.0-3.6V,
-40°C to +85°C)
• Industrial temperature range (-40°C to +85°C)
•
•
•
•
•
High-Performance DSC CPU:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Modified Harvard architecture
C compiler optimized instruction set
16-bit wide data path
24-bit wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
83 base instructions: mostly 1 word/1 cycle
Sixteen 16-bit General Purpose Registers
Two 40-bit accumulators:
- With rounding and saturation options
Flexible and powerful addressing modes:
- Indirect, Modulo and Bit-Reversed
Software stack
16 x 16 fractional/integer multiply operations
32/16 and 16/16 divide operations
Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
• 8-channel hardware DMA:
• 2 Kbytes dual ported DMA buffer area
(DMA RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a
peripheral while CPU is executing code
(no cycle stealing)
• Most peripherals support DMA
Interrupt Controller:
•
•
•
•
•
•
5-cycle latency
118 interrupt vectors
Up to 67 available interrupt sources
Up to 5 external interrupts
7 programmable priority levels
5 processor exceptions
© 2007 Microchip Technology Inc.
Up to 85 programmable digital I/O pins
Wake-up/Interrupt-on-Change on up to 24 pins
Output pins can drive from 3.0V to 3.6V
All digital input pins are 5V tolerant
4 mA sink on all I/O pins
On-Chip Flash and SRAM:
• Flash program memory, up to 256 Kbytes
• Data SRAM, up to 30 Kbytes (includes 2 Kbytes
of DMA RAM):
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated PLL
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare/PWM:
• Timer/Counters, up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
- 1 timer runs as Real-Time Clock with external
32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to 8 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to 8 channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM mode
Preliminary
DS70165E-page 1
dsPIC33F
Communication Modules:
Motor Control Peripherals:
• 3-wire SPI (up to 2 modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™ (up to 2 modules):
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to 2 modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Data Converter Interface (DCI) module:
- Codec interface
- Supports I2S and AC’97 protocols
- Up to 16-bit data words, up to 16 words per
frame
- 4-word deep TX and RX buffers
• Enhanced CAN (ECAN™ module) 2.0B active
(up to 2 modules):
- Up to 8 transmit and up to 32 receive buffers
- 16 receive filters and 3 masks
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
- Automatic processing of Remote
Transmission Requests
- FIFO mode using DMA
- DeviceNet™ addressing support
• Motor Control PWM (up to 8 channels):
- 4 duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center-aligned
- Manual output override control
- Up to 2 Fault inputs
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
• Quadrature Encoder Interface module:
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
Analog-to-Digital Converters (ADCs):
• Up to two ADC modules in a device
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- 2, 4 or 8 simultaneous samples
- Up to 32 input channels with auto-scanning
- Conversion start can be manual or
synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
CMOS Flash Technology:
•
•
•
•
•
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial temperature
Low-power consumption
Packaging:
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 80-pin TQFP (12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
Note:
DS70165E-page 2
Preliminary
See the device variant tables for exact
peripheral features per device.
© 2007 Microchip Technology Inc.
dsPIC33F
dsPIC33F PRODUCT FAMILIES
for Uninterrupted Power Supply (UPS), inverters,
Switched mode power supplies, power factor correction and also for controlling the power management
module in servers, telecommunication equipment and
other industrial equipment.
There are two device subfamilies within the dsPIC33F
family of devices. They are the General Purpose
Family and the Motor Control Family.
The General Purpose Family is ideal for a wide variety
of 16-bit MCU embedded applications. The variants
with codec interfaces are well-suited for speech and
audio processing applications.
The device names, pin counts, memory sizes and
peripheral availability of each family are listed below,
followed by their pinout diagrams.
The Motor Control Family supports a variety of motor
control applications, such as brushless DC motors,
single and 3-phase induction motors and switched
reluctance motors. These products are also well-suited
Device
Pins
Program
Flash
Memory
(Kbyte)
RAM
(Kbyte)(1)
16-bit Timer
Input Capture
Output Compare
Std. PWM
Codec
Interface
ADC
UART
SPI
I2C™
Enhanced
CAN
I/O Pins (Max)(2)
dsPIC33F General Purpose Family Variants
Packages
dsPIC33FJ64GP206
64
64
8
9
8
8
1
1 ADC, 18
ch
2
2
1
0
53
PT
dsPIC33FJ64GP306
64
64
16
9
8
8
1
1 ADC, 18
ch
2
2
2
0
53
PT
dsPIC33FJ64GP310
100
64
16
9
8
8
1
1 ADC, 32
ch
2
2
2
0
85
PF, PT
dsPIC33FJ64GP706
64
64
16
9
8
8
1
2 ADC, 18
ch
2
2
2
2
53
PT
dsPIC33FJ64GP708
80
64
16
9
8
8
1
2 ADC, 24
ch
2
2
2
2
69
PT
dsPIC33FJ64GP710
100
64
16
9
8
8
1
2 ADC, 32
ch
2
2
2
2
85
PF, PT
dsPIC33FJ128GP206
64
128
8
9
8
8
1
1 ADC, 18
ch
2
2
1
0
53
PT
dsPIC33FJ128GP306
64
128
16
9
8
8
1
1 ADC, 18
ch
2
2
2
0
53
PT
dsPIC33FJ128GP310
100
128
16
9
8
8
1
1 ADC, 32
ch
2
2
2
0
85
PF, PT
dsPIC33FJ128GP706
64
128
16
9
8
8
1
2 ADC, 18
ch
2
2
2
2
53
PT
dsPIC33FJ128GP708
80
128
16
9
8
8
1
2 ADC, 24
ch
2
2
2
2
69
PT
dsPIC33FJ128GP710
100
128
16
9
8
8
1
2 ADC, 32
ch
2
2
2
2
85
PF, PT
dsPIC33FJ256GP506
64
256
16
9
8
8
1
1 ADC, 18
ch
2
2
2
1
53
PT
dsPIC33FJ256GP510
100
256
16
9
8
8
1
1 ADC, 32
ch
2
2
2
1
85
PF, PT
dsPIC33FJ256GP710
100
256
30
9
8
8
1
2 ADC, 32
ch
2
2
2
2
85
PF, PT
Note 1:
2:
RAM size is inclusive of 2 Kbytes DMA RAM.
Maximum I/O pin count includes pins shared by the peripheral functions.
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 3
dsPIC33F
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CSDO/RG13
CSDI/RG12
CSCK/RG14
RG0
RG1
RF1
RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GP206
dsPIC33FJ128GP206
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/CN17/RF4
U2TX/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
DS70165E-page 4
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CSDO/RG13
CSDI/RG12
CSCK/RG14
RG0
RG1
RF1
RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GP306
dsPIC33FJ128GP306
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 5
dsPIC33F
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CSDO/RG13
CSDI/RG12
CSCK/RG14
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ256GP506
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
DS70165E-page 6
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CSDO/RG13
CSDI/RG12
CSCK/RG14
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GP706
dsPIC33FJ128GP706
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 7
dsPIC33F
Pin Diagrams (Continued)
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
63
62
61
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
CSCK/RG14
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
OC7/CN15/RD6
CSDO/RG13
CSDI/RG12
80
79
AN23/CN23/RA7
AN22/CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/CN16/RD7
80-Pin TQFP
1
60
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
2
59
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
AN18/T4CK/T9CK/RC3
3
4
58
57
IC4/RD11
AN19/T5CK/T8CK/RC4
5
56
IC3/RD10
SCK2/CN8/RG6
6
55
IC2/RD9
SDI2/CN9/RG7
7
54
IC1/RD8
53
SDA2/INT4/RA3
52
SCL2/INT3/RA2
SS2/CN11/RG9
8
9
10
51
VSS
VSS
11
50
VDD
12
49
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
TMS/AN20/INT1/RA12
13
48
TDO/AN21/INT2/RA13
14
47
VDD
SCL1/RG2
AN5/CN7/RB5
15
16
46
SDA1/RG3
AN4/CN6/RB4
45
SCK1/INT0/RF6
AN3/CN5/RB3
17
44
SDI1/RF7
AN2/SS1/CN4/RB2
18
43
SDO1/RF8
PGC3/EMUC3/AN1/CN3/RB1
19
42
U1RX/RF2
PGD3/EMUD3/AN0/CN2/RB0
20
41
U1TX/RF3
DS70165E-page 8
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
25
AVDD
26
24
VREF+/RA10
AVSS
23
U2CTS/AN8/RB8
22
dsPIC33FJ64GP708
dsPIC33FJ128GP708
VREF-/RA9
MCLR
21
SDO2/CN10/RG8
PGD1/EMUD1/AN7/RB7
AN17/T3CK/T6CK/RC2
PGC1/EMUC1/AN6/OCFA/RB6
COFS/RG15
AN16/T2CK/T7CK/RC1
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
CSDO/RG13
CSDI/RG12
CSCK/RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
RF1
RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
COFS/RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
1
75
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
74
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
73
PGD2/EMUD2/SOSCI/CN1/RC13
72
OC1/RD0
IC4/RD11
PGD3/EMUD3/AN0/CN2/RB0
25
dsPIC33FJ64GP310
dsPIC33FJ128GP310
IC3/RD10
IC2/RD9
IC1/RD8
67
66
INT4/RA15
INT3/RA14
65
64
VSS
63
62
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
61
60
TDO/RA5
TDI/RA4
59
58
57
56
SDA2/RA3
SCL2/RA2
55
SCK1/INT0/RF6
54
53
SDI1/RF7
SDO1/RF8
U1RX/RF2
52
51
SCL1/RG2
SDA1/RG3
U1TX/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGC3/EMUC3/AN1/CN3/RB1
23
24
71
70
69
68
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 9
dsPIC33F
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
CSDO/RG13
CSDI/RG12
CSCK/RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
COFS/RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
74
73
72
71
70
69
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
68
67
66
65
64
dsPIC33FJ256GP510
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGD3/EMUD3/AN0/CN2/RB0
75
1
2
3
4
5
6
7
8
9
DS70165E-page 10
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
CSDO/RG13
CSDI/RG12
CSCK/RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
COFS/RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
75
VSS
2
3
4
5
6
7
8
9
10
11
12
74
73
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/CN1/RC13
72
OC1/RD0
71
IC4/RD11
IC3/RD10
IC2/RD9
13
14
15
16
17
18
19
20
21
22
23
24
25
70
69
68
67
66
dsPIC33FJ64GP710
dsPIC33FJ128GP710
dsPIC33FJ256GP710
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
1
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 11
dsPIC33F
Timer 16-bit
Input Capture
Output Compare
Std. PWM
Motor Control PWM
Quadrature Encoder
Interface
Codec Interface
ADC
UART
SPI
I2C™
Enhanced CAN
I/O Pins (Max)(2)
dsPIC33F Motor Control Family Variants
Packages
dsPIC33FJ64MC506
64
64
8
9
8
8
8 ch
1
0
1 ADC,
16 ch
2
2
2
1
53
PT
dsPIC33FJ64MC508
80
64
8
9
8
8
8 ch
1
0
1 ADC,
18 ch
2
2
2
1
69
PT
dsPIC33FJ64MC510
100
64
8
9
8
8
8 ch
1
0
1 ADC,
24 ch
2
2
2
1
85
PF, PT
dsPIC33FJ64MC706
64
64
16
9
8
8
8 ch
1
0
2 ADC,
16 ch
2
2
2
1
53
PT
dsPIC33FJ64MC710
100
64
16
9
8
8
8 ch
1
0
2 ADC,
24 ch
2
2
2
2
85
PF, PT
dsPIC33FJ128MC506
64
128
8
9
8
8
8 ch
1
0
1 ADC,
16 ch
2
2
2
1
53
PT
dsPIC33FJ128MC510
100
128
8
9
8
8
8 ch
1
0
1 ADC,
24 ch
2
2
2
1
85
PF, PT
dsPIC33FJ128MC706
64
128
16
9
8
8
8 ch
1
0
2 ADC,
16 ch
2
2
2
1
53
PT
dsPIC33FJ128MC708
80
128
16
9
8
8
8 ch
1
0
2 ADC,
18 ch
2
2
2
2
69
PT
dsPIC33FJ128MC710
100
128
16
9
8
8
8 ch
1
0
2 ADC,
24 ch
2
2
2
2
85
PF, PT
dsPIC33FJ256MC510
100
256
16
9
8
8
8 ch
1
0
1 ADC,
24 ch
2
2
2
1
85
PF, PT
dsPIC33FJ256MC710
100
256
30
9
8
8
8 ch
1
0
2 ADC,
24 ch
2
2
2
2
85
PF, PT
Device
Note 1:
2:
Progra
m Flash
RAM
Pins
Memory (Kbyte)(1)
(Kbyte)
RAM size is inclusive of 2 Kbytes DMA RAM.
Maximum I/O pin count includes pins shared by the peripheral functions.
DS70165E-page 12
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/UPDN/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64MC506
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/CN17/RF4
U2TX/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
VDD
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 13
dsPIC33F
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/UPDN/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ128MC506
dsPIC33FJ64MC506
dsPIC33FJ128MC706
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
VDD
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
DS70165E-page 14
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
63
62
61
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
OC7/CN15/RD6
RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/CN16/UPDN/RD7
75
74
73
72
71
70
69
68
67
66
65
64
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
RG0
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
80-Pin TQFP
PWM3H/RE5
1
60
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PWM4L/RE6
2
59
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
PWM4H/RE7
3
58
AN16/T2CK/T7CK/RC1
4
57
IC4/RD11
AN17/T3CK/T6CK/RC2
5
56
IC3/RD10
SCK2/CN8/RG6
6
55
IC2/RD9
SDI2/CN9/RG7
7
54
IC1/RD8
SDO2/CN10/RG8
8
53
SDA2/INT4/RA3
MCLR
9
52
SS2/CN11/RG9
VSS
10
51
SCL2/INT3/RA2
VSS
50
OSC2/CLKO/RC15
VDD
12
49
OSC1/CLKIN/RC12
TMS/FLTA/INT1/RE8
13
14
48
VDD
47
SCL1/RG2
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
15
46
SDA1/RG3
16
45
SCK1/INT0/RF6
AN3/INDX/CN5/RB3
17
44
SDI1/RF7
AN2/SS1/CN4/RB2
18
43
SDO1/RF8
PGC3/EMUC3/AN1/CN3/RB1
19
42
U1RX/RF2
PGD3/EMUD3/AN0/CN2/RB0
20
41
U1TX/RF3
31
32
33
34
35
36
37
38
39
40
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
28
AN9/RB9
30
27
U2CTS/AN8/RB8
VSS
26
AVSS
29
25
AVDD
AN11/RB11
24
AN10/RB10
23
VREF-/RA9
22
PGD1/EMUD1/AN7/RB7
© 2007 Microchip Technology Inc.
VREF+/RA10
21
PGC1/EMUC1/AN6/OCFA/RB6
TDO/FLTB/INT2/RE9
dsPIC33FJ64MC508
11
Preliminary
DS70165E-page 15
dsPIC33F
Pin Diagrams (Continued)
OC2/RD1
IC5/RD12
OC4/RD3
OC3/RD2
OC8/CN16/UPDN/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
CRX2/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
80-Pin TQFP
PWM3H/RE5
1
60
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PWM4L/RE6
2
59
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
PWM4H/RE7
3
58
AN16/T2CK/T7CK/RC1
4
57
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
5
56
IC4/RD11
IC3/RD10
6
55
IC2/RD9
SDI2/CN9/RG7
SDO2/CN10/RG8
7
54
IC1/RD8
8
53
SDA2/INT4/RA3
MCLR
9
52
SCL2/INT3/RA2
SS2/CN11/RG9
10
51
VSS
VSS
11
50
OSC2/CLKO/RC15
VDD
12
49
OSC1/CLKIN/RC12
TMS/FLTA/INT1/RE8
48
VDD
TDO/FLTB/INT2/RE9
13
14
47
SCL1/RG2
AN5/QEB/CN7/RB5
15
46
SDA1/RG3
AN4/QEA/CN6/RB4
16
45
SCK1/INT0/RF6
AN3/INDX/CN5/RB3
17
44
SDI1/RF7
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
18
43
SDO1/RF8
19
42
U1RX/RF2
PGD3/EMUD3/AN0/CN2/RB0
20
41
U1TX/RF3
DS70165E-page 16
35
36
37
38
39
40
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
33
AN15/OCFB/CN12/RB15
32
TCK/AN12/RB12
34
31
VDD
TDI/AN13/RB13
30
VSS
U2RTS/AN14/RB14
29
27
U2CTS/AN8/RB8
AN11/RB11
26
AVSS
28
25
AVDD
AN9/RB9
24
AN10/RB10
23
VREF-/RA9
22
PGD1/EMUD1/AN7/RB7
VREF+/RA10
21
PGC1/EMUC1/AN6/OCFA/RB6
dsPIC33FJ128MC708
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
CSDO/RG13
CSDI/RG12
CSCK/RG14
PWM1H/RE1
PWM1L/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/UPDN//CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
COFS/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
1
75
VSS
2
3
4
5
6
7
8
9
10
11
12
74
73
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
72
OC1/RD0
IC4/RD11
PGC3/EMUC3/AN1/CN3/RB1
13
14
15
16
17
18
19
20
21
22
23
24
PGD3/EMUD3/AN0/CN2/RB0
25
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
70
69
68
67
66
dsPIC33FJ64MC510
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
65
64
INT3/RA14
VSS
OSC2/CLKO/RC15
63
62
61
OSC1/CLKIN/RC12
VDD
TDO/RA5
60
59
58
57
56
TDI/RA4
RA3
RA2
55
54
53
52
51
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
71
PGD2/EMUD2/SOSCI/CN1/RC13
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 17
dsPIC33F
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
CSDO/RG13
CSDI/RG12
CSCK/RG14
PWM1H/RE1
PWM1L/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/UPDN//CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
COFS/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
VSS
73
72
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
71
70
69
68
67
66
65
64
dsPIC33FJ128MC510
dsPIC33FJ256MC510
63
62
61
60
59
58
57
56
55
54
53
52
51
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGD3/EMUD3/AN0/CN2/RB0
1
DS70165E-page 18
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
CSDO/RG13
CSDI/RG12
CSCK/RG14
PWM1H/RE1
PWM1L/RE0
AN23/CN23/RA7
AN22/CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VDDCORE
OC8/UPDN//CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
COFS/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
75
2
3
4
5
6
7
8
9
10
11
12
74
73
72
71
70
69
68
67
66
dsPIC33FJ64MC710
dsPIC33FJ128MC710
dsPIC33FJ256MC710
13
14
15
16
17
18
19
20
21
22
23
24
25
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC1/EMUC1/AN6/OCFA/RB6
PGD1/EMUD1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGD3/EMUD3/AN0/CN2/RB0
1
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 19
dsPIC33F
Table of Contents
dsPIC33F Product Families ................................................................................................................................................................... 3
1.0 Device Overview ........................................................................................................................................................................ 23
2.0 CPU............................................................................................................................................................................................ 27
3.0 Memory Organization ................................................................................................................................................................. 39
4.0 Flash Program Memory.............................................................................................................................................................. 77
5.0 Resets ....................................................................................................................................................................................... 83
6.0 Interrupt Controller ..................................................................................................................................................................... 87
7.0 Direct Memory Access (DMA) .................................................................................................................................................. 135
8.0 Oscillator Configuration ............................................................................................................................................................ 149
9.0 Power-Saving Features............................................................................................................................................................ 157
10.0 I/O Ports ................................................................................................................................................................................... 159
11.0 Timer1 ...................................................................................................................................................................................... 161
12.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 163
13.0 Input Capture............................................................................................................................................................................ 169
14.0 Output Compare....................................................................................................................................................................... 171
15.0 Motor Control PWM Module ..................................................................................................................................................... 175
16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 197
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205
18.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 213
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 223
20.0 Enhanced CAN Module............................................................................................................................................................ 231
21.0 Data Converter Interface (DCI) Module.................................................................................................................................... 261
22.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 275
23.0 Special Features ...................................................................................................................................................................... 289
24.0 Instruction Set Summary .......................................................................................................................................................... 297
25.0 Development Support............................................................................................................................................................... 305
26.0 Electrical Characteristics .......................................................................................................................................................... 309
27.0 Packaging Information.............................................................................................................................................................. 351
Appendix A: Revision History............................................................................................................................................................. 357
Index ................................................................................................................................................................................................. 359
The Microchip Web Site ..................................................................................................................................................................... 365
Customer Change Notification Service .............................................................................................................................................. 365
Customer Support .............................................................................................................................................................................. 365
Reader Response .............................................................................................................................................................................. 366
Product Identification System ............................................................................................................................................................ 367
DS70165E-page 20
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 21
dsPIC33F
NOTES:
DS70165E-page 22
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
This document contains device specific information for
the following devices:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
dsPIC33FJ64GP206
dsPIC33FJ64GP306
dsPIC33FJ64GP310
dsPIC33FJ64GP706
dsPIC33FJ64GP708
dsPIC33FJ64GP710
dsPIC33FJ128GP206
dsPIC33FJ128GP306
dsPIC33FJ128GP310
dsPIC33FJ128GP706
dsPIC33FJ128GP708
dsPIC33FJ128GP710
dsPIC33FJ256GP506
dsPIC33FJ256GP510
dsPIC33FJ256GP710
dsPIC33FJ64MC506
dsPIC33FJ64MC508
dsPIC33FJ64MC510
dsPIC33FJ64MC706
dsPIC33FJ64MC710
dsPIC33FJ128MC506
dsPIC33FJ128MC510
dsPIC33FJ128MC706
dsPIC33FJ128MC708
dsPIC33FJ128MC710
dsPIC33FJ256MC510
dsPIC33FJ256MC710
This makes these families suitable for a wide variety of
high-performance digital signal control application. The
devices are pin compatible with the PIC24H family of
devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy
migration between device families as may be necessitated by the specific functionality, computational
resource and system cost requirements of the application.
The dsPIC33F device family employs a powerful 16-bit
architecture that seamlessly integrates the control
features of a Microcontroller (MCU) with the
computational capabilities of a Digital Signal Processor
(DSP). The resulting functionality is ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 x 17
multiplier, a large array of 16-bit working registers and
a wide variety of data addressing modes, together
provide the dsPIC33F Central Processing Unit (CPU)
with extensive mathematical processing capability.
Flexible and deterministic interrupt handling, coupled
with a powerful array of peripherals, renders the
dsPIC33F devices suitable for control applications.
Further, Direct Memory Access (DMA) enables
overhead-free transfer of data between several
peripherals and a dedicated DMA RAM. Reliable, field
programmable Flash program memory ensures
scalability of applications that use dsPIC33F devices.
Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the dsPIC33F
family of devices, while Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
The dsPIC33F General Purpose and Motor Control
Families of devices include devices with a wide range
of pin counts (64, 80 and 100), different program
memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes)
and different RAM sizes (8 Kbytes, 16 Kbytes and
30 Kbytes)
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 23
dsPIC33F
FIGURE 1-1:
dsPIC33F GENERAL BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
16
8
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
DMA
RAM
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
23
PORTB
DMA
16
16
Controller
16
PORTC
Address Generator Units
Address Latch
Program Memory
EA MUX
Address Bus
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VDDCORE/VCAP
Timers
1-9
IC1-8
Note:
Literal Data
16
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
PORTD
ROM Latch
16
PORTE
16
DSP Engine
Power-up
Timer
Divide Support
16 x 16
W Register Array
16
PORTF
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
VDD, VSS
PWM
OC/
PWM1-8
PORTG
MCLR
QEI
DCI
ADC1,2
ECAN1,2
CN1-23
SPI1,2
I2C1,2
UART1,2
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
DS70165E-page 24
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN31
I
Analog
AVDD
P
P
Positive supply for analog modules.
AVSS
P
P
Ground reference for analog modules.
CLKI
CLKO
I
O
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
Pin Name
Description
Analog input channels.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
Optionally functions as CLKO in RC and EC modes. Always associated with OSC2
pin function.
IC1-IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
I
I
ST
ST
QEB
I
ST
UPDN
O
CMOS
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
FLTA
FLTB
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM 1 low output.
PWM 1 high output.
PWM 2 low output.
PWM 2 high output.
PWM 3 low output.
PWM 3 high output.
PWM 4 low output.
PWM 4 high output.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
OSC2
I
I/O
Legend:
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
Optionally functions as CLKO in RC and EC modes.
CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 25
dsPIC33F
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
I/O
I/O
I/O
ST
ST
ST
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE9
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF8
RF12-RF13
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
O
I/O
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
SOSCO
I
O
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
Positive supply for peripheral logic and I/O pins.
Pin Name
RA0-RA7
RA9-RA10
RA12-RA15
Description
PORTA is a bidirectional I/O port.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
VDD
P
—
VDDCORE
P
—
CPU logic filter capacitor connection.
VSS
P
—
Ground reference for logic and I/O pins.
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Legend:
CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
DS70165E-page 26
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
2.0
Note:
CPU
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
The dsPIC33F CPU module has a 16-bit (data) modified
Harvard architecture with an enhanced instruction set,
including significant support for DSP. The CPU has a
24-bit instruction word with a variable length opcode field.
The Program Counter (PC) is 23 bits wide and
addresses up to 4M x 24 bits of user program memory
space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which are
interruptible at any point.
The dsPIC33F devices have sixteen, 16-bit working
registers in the programmer’s model. Each of the working
registers can serve as a data, address or address offset
register. The 16th working register (W15) operates as a
software Stack Pointer (SP) for interrupts and calls.
The dsPIC33F instruction set has two classes of
instructions: MCU and DSP. These two instruction
classes are seamlessly integrated into a single CPU.
The instruction set includes many addressing modes
and is designed for optimum C compiler efficiency. For
most instructions, the dsPIC33F is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 2-1,
and the programmer’s model for the dsPIC33F is
shown in Figure 2-2.
2.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The MCU
class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one
linear data space. Certain DSP instructions operate
through the X and Y AGUs to support dual operand
reads, which splits the data address space into two parts.
The X and Y data space boundary is device-specific.
© 2007 Microchip Technology Inc.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU circular addressing can be used with any of
the MCU class of instructions. The X AGU also supports
Bit-Reversed Addressing to greatly simplify input or
output data reordering for radix-2 FFT algorithms.
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary defined by the 8-bit Program
Space Visibility Page (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
2.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value,
up to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal
real-time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM memory data space
be split for these instructions and linear for all others.
Data space partitioning is achieved in a transparent
and flexible manner through dedicating certain working
registers to each address space.
2.3
Special MCU Features
The dsPIC33F features a 17-bit by 17-bit, single-cycle
multiplier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed-sign multiplication, it also
achieves accurate results for special operations, such
as (-1.0) x (-1.0).
The dsPIC33F supports 16/16 and 32/16 divide
operations, both fractional and integer. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit,
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
Preliminary
DS70165E-page 27
dsPIC33F
FIGURE 2-1:
dsPIC33F CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
DMA
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
RAM
16
23
16
16
DMA
Controller
Address Generator Units
Address Latch
Program Memory
EA MUX
Address Bus
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Instruction Reg
Literal Data
Instruction
Decode &
Control
16
16
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
To Peripheral Modules
DS70165E-page 28
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
FIGURE 2-2:
dsPIC33F PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
DSP
Accumulators
AD15
AD31
AD0
AccA
AccB
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
© 2007 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
Preliminary
DS70165E-page 29
dsPIC33F
2.4
CPU Control Registers
REGISTER 2-1:
R-0
OA
SR: CPU STATUS REGISTER
R-0
R/C-0
R/C-0
OB
SA(1)
(1)
SB
R-0
R/C-0
R -0
R/W-0
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(2)
R/W-0(3)
R/W-0(3)
(2)
IPL
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
Note:
Note 1:
2:
3:
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
This bit may be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
DS70165E-page 30
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
REGISTER 2-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
This bit may be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 31
dsPIC33F
REGISTER 2-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
R/W-0
SATA
bit 7
R/W-0
SATB
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
DL
R-0
bit 8
Legend:
R = Readable bit
0’ = Bit is cleared
bit 15-13
bit 12
U-0
—
R/W-1
SATDW
R/W-0
ACCSAT
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
001 = 1 DO loop active
000 = 0 DO loops active
SATA: AccA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: AccB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.
DS70165E-page 32
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
2.5
Arithmetic Logic Unit (ALU)
The dsPIC33F ALU is 16 bits wide and is capable of
addition, subtraction, bit shifts and logic operations.
Unless otherwise mentioned, arithmetic operations are
2’s complement in nature. Depending on the operation,
the ALU may affect the values of the Carry (C), Zero
(Z), Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The dsPIC33F CPU incorporates hardware support for
both multiplication and division. This includes a dedicated hardware multiplier and support hardware for
16-bit-divisor division.
2.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
1.
2.
3.
4.
5.
6.
7.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
2.5.2
2.6
DSP Engine
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33F is a single-cycle, instruction flow architecture; therefore, concurrent operation of the DSP engine
with MCU instruction flow is not possible. However, some
MCU ALU and DSP engine resources may be used
concurrently by the same instruction (e.g., ED, EDAC).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
7.
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
1.
2.
3.
4.
5.
6.
DIVIDER
TABLE 2-1:
1.
2.
3.
4.
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection (ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-3.
DSP INSTRUCTIONS SUMMARY
Instruction
Algebraic Operation
ACC Write Back
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
A=0
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
No change in A
A=x*y
A=x2
A=–x*y
A=A–x*y
Yes
No
No
Yes
No
Yes
No
No
No
Yes
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 33
dsPIC33F
FIGURE 2-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Saturate
Carry/Borrow In
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70165E-page 34
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
2.6.1
MULTIPLIER
2.6.2.1
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value which is
sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where
the MSb is defined as a sign bit. Generally speaking,
the range of an N-bit two’s complement integer is -2N-1
to 2N-1 – 1. For a 16-bit integer, the data range is
-32768 (0x8000) to 32767 (0x7FFF) including ‘0’. For a
32-bit integer, the data range is -2,147,483,648
(0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSb is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX
format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1 – 21-N).
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF) including ‘0’ and
has a precision of 3.01518x10-5. In Fractional mode,
the 16 x 16 multiply operation generates a 1.31 product
which has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true, or complement
data into the other input. In the case of addition, the
carry/borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active-low and the
other input is complemented. The adder/subtracter
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS
register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above and the SAT (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.
2.6.2
4.
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter prior to accumulation.
Adder/Subtracter, Overflow and
Saturation
5.
6.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in
the INTCON1 register (refer to Section 6.0 “Interrupt
Controller”) are set. This allows the user to take
immediate action, for example, to correct system gain.
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 35
dsPIC33F
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When
saturation is not enabled, SA and SB default to bit 39
overflow and, thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1
register is set, SA and SB bits will generate an
arithmetic warning trap when saturation is disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three Saturation and Overflow
modes:
1.
2.
3.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000), into the target accumulator. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erroneous data or unexpected algorithm problems
(e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally
negative 1.31 value (0x0080000000), into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used (so the OA, OB or OAB bits are never
set).
Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
DS70165E-page 36
2.6.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
2.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
[W13]+ = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.6.2.3
Round Logic
The round logic is a combinational block which
performs a conventional (biased) or convergent
(unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a
16-bit, 1.15 data value which is passed to the data
space write saturation logic. If rounding is not indicated
by the instruction, a truncated 1.15 data value is stored
and the least significant word is simply discarded.
Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator). If the ACCxL word (bits 0
through 15 of the accumulator) is between 0x8000 and
0xFFFF (0x8000 included), ACCxH is incremented. If
ACCxL is between 0x0000 and 0x7FFF, ACCxH is left
unchanged. A consequence of this algorithm is that
over a succession of random rounding operations, the
value tends to be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is
examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,
ACCxH is not modified. Assuming that bit 16 is
effectively random in nature, this scheme removes any
rounding bias that may accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 2.6.2.4 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator
write-back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
2.6.2.4
Data Space Write Saturation
2.6.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly, For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The Most
Significant bit of the source (bit 39) is used to determine
the sign of the operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to
31 for right shifts, and between bit positions 0 to 16 for
left shifts.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 37
dsPIC33F
NOTES:
DS70165E-page 38
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
3.0
MEMORY ORGANIZATION
Note:
3.1
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
The dsPIC33F architecture features separate program
and data memory spaces and buses. This architecture
also allows the direct access of program memory from
the data space during code execution.
Program Address Space
The program address memory space of the dsPIC33F
devices is 4M instructions. The space is addressable by a
24-bit value derived from either the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 3.6
“Interfacing Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the dsPIC33F family of devices are
shown in Figure 3-1.
FIGURE 3-1:
PROGRAM MEMORY MAP FOR dsPIC33F FAMILY DEVICES
User Memory Space
dsPIC33FJ64XXXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(22K instructions)
dsPIC33FJ128XXXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
dsPIC33FJ256XXXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(44K instructions)
User Program
Flash Memory
(88K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
Unimplemented
0x02ABFE
0x02AC00
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
Configuration Memory Space
0x7FFFFE
0x800000
Reserved
Reserved
Reserved
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
© 2007 Microchip Technology Inc.
Preliminary
0xF7FFFE
0xF80000
0xF80017
0xF80010
0xFEFFFE
0xFF0000
0xFFFFFE
DS70165E-page 39
dsPIC33F
3.1.1
PROGRAM MEMORY
ORGANIZATION
3.1.2
All dsPIC33F devices reserve the addresses between
0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 0x000000,
with the actual address for the start of code at
0x000002.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 3-2).
dsPIC33F devices also have two interrupt vector
tables, located from 0x000004 to 0x0000FF and
0x000100 to 0x0001FF. These vector tables allow each
of the many device interrupt sources to be handled by
separate Interrupt Service Routines (ISRs). A more
detailed discussion of the interrupt vector tables is
provided in Section 6.1 “Interrupt Vector Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
FIGURE 3-2:
msw
Address
PROGRAM MEMORY ORGANIZATION
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS70165E-page 40
least significant word
most significant word
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
3.2
Data Address Space
The dsPIC33F CPU has a separate 16-bit wide data
memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and
write operations. Data memory maps of devices with
different RAM sizes are shown in Figure 3-3 through
Figure 3-5.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space
Visibility area (see Section 3.6.3 “Reading Data From
Program Memory Using Program Space Visibility”).
dsPIC33F devices implement a total of up to 30 Kbytes
of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be
returned.
3.2.1
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® devices
and improve data space memory usage efficiency, the
dsPIC33F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
effective address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws +
1 for byte operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSb of the data path. That is, data memory and registers are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
© 2007 Microchip Technology Inc.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSb of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
3.2.3
DATA SPACE WIDTH
The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
3.2.2
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the dsPIC33F
core and peripheral modules for controlling the
operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 3-1
through Table 3-34.
Note:
3.2.4
The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
Preliminary
DS70165E-page 41
dsPIC33F
FIGURE 3-3:
DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 8 KBs RAM
MSb
Address
MSb
2-Kbyte
SFR Space
LSb
Address
16 bits
LSb
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8-Kbyte
Near
Data
Space
X Data RAM (X)
8-Kbyte
SRAM Space
0x17FF
0x1801
0x17FE
0x1800
Y Data RAM (Y)
0x1FFF
0x2001
0x27FF
0x2801
0x1FFE
0x2000
DMA RAM
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70165E-page 42
0x27FE
0x2800
0xFFFE
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
FIGURE 3-4:
DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 16 KBs RAM
MSb
Address
LSb
Address
16 bits
MSb
LSb
0x0000
0x0001
2-Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
0x1FFF
X Data RAM (X)
0x1FFE
0x27FF
0x2801
16-Kbyte
SRAM Space
8-Kbyte
Near
Data
Space
0x27FE
0x2800
Y Data RAM (Y)
0x3FFF
0x4001
0x47FF
0x4801
0x3FFE
0x4000
DMA RAM
0x8001
0x47FE
0x4800
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFE
0xFFFF
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 43
dsPIC33F
FIGURE 3-5:
DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 30 KBs RAM
MSb
Address
MSb
2-Kbyte
SFR Space
LSb
Address
16 bits
LSb
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8-Kbyte
Near
Data
Space
X Data RAM (X)
30-Kbyte
SRAM Space
0x47FF
0x4801
0x47FE
0x4800
Y Data RAM (Y)
0x77FF
0x7800
0x7FFF
0x8001
Optionally
Mapped
into Program
Memory
DMA RAM
X Data
Unimplemented (X)
0xFFFF
DS70165E-page 44
0x77FE
0x7800
0x7FFE
0x8000
0xFFFE
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F
3.2.5
X AND Y DATA SPACES
3.2.6
DMA RAM
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
Every dsPIC33F device contains 2 Kbytes of dual ported
DMA RAM located at the end of Y data space. Memory
locations is part of Y data RAM and is in the DMA RAM
space are accessible simultaneously by the CPU and
the DMA controller module. DMA RAM is utilized by the
DMA controller to store data to be transferred to various
peripherals using DMA, as well as data transferred from
various peripherals using DMA. The DMA RAM can be
accessed by the DMA controller without having to steal
cycles from the CPU.
The X data space is used by all instructions and
supports all addressing modes. There are separate
read and write data buses for X data space. The X read
data bus is the read data path for all instructions that
view data space as combined X and Y address space.
It is also the X data prefetch path for the dual operand
DSP instructions (MAC class).
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
Note:
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
© 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 45
CPU CORE REGISTERS MAP
Preliminary
SFR Name
SFR
Addr
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
Program Counter High Byte Register
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Page Address Pointer Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Memory Visibility Page Address Pointer Register
0000
RCOUNT
0036
Repeat Loop Counter Register
xxxx
DCOUNT
0038
DCOUNT
xxxx
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
© 2007 Microchip Technology Inc.
—
—
—
—
—
—
0040
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
CORCON
0044
—
—
—
US
EDT
MODCON
0046
XMODEN
YMODEN
—
—
0
—
—
—
DOSTARTH
—
—
DOENDH
0
IPL2
IPL1
IPL0
RA
N
OV
Z
C
SATB
SATDW
ACCSAT
IPL3
PSV
RND
IF
YWM
xxxx
00xx
SATA
BWM
xxxx
00xx
DOENDL
DL
All
Resets
0000
DOSTARTL
—
Bit 0
XWM
0000
0000
0000
XMODSRT
0048
XS
0
xxxx
XMODEND
004A
XE
1
xxxx
YMODSRT
004C
YS
0
xxxx
YMODEND
004E
YE
1
XBREV
0050
DISICNT
0052
—
—
BSRAM
0750
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR
IR_BSR
RL_BSR
0000
SSRAM
0752
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_SSR
IR_SSR
RL_SSR
0000
Legend:
BREN
XB
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
xxxx
xxxx
dsPIC33F
DS70165E-page 46
TABLE 3-1:
© 2007 Microchip Technology Inc.
TABLE 3-2:
CHANGE NOTIFICATION REGISTER MAP
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Preliminary
dsPIC33F
DS70165E-page 47
SFR
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
INTCON1
0080
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE
INTCON2
0082
ALTIVT
DISI
—
—
—
IFS0
0084
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
—
Bit 6
Bit 5
Bit 4
Bit 3
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
OC1IF
IC1IF
INT0IF
0000
—
MI2C1IF
SI2C1IF
0000
0000
Bit 8
OVBTE
COVTE
—
—
—
—
—
INT4EP
INT3EP
INT2EP
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC3IF
DMA2IF
IC8IF
IC7IF
AD2IF
INT1IF
CNIF
SPI1IF SPI1EIF
Bit 7
Bit 0
Bit 9
Bit 2
Bit 1
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR
IFS2
0088
T6IF
DMA4IF
—
OC8IF
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
IFS3
008A
FLTAIF
—
DMA5IF
DCIIF
DCIEIF
QEIIF
PWMIF
C2IF
C2RXIF
INT4IF
INT3IF
T9IF
T8IF
MI2C2IF
SI2C2IF
T7IF
0000
IFS4
008C
—
—
—
—
—
—
—
—
C2TXIF
C1TXIF
DMA7IF
DMA6IF
—
U2EIF
U1EIF
FLTBIF
0000
IEC0
0094
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
IC1IE
INT0IE
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
SPI1IE SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
OC3IE
DMA2IE
IC8IE
IC7IE
AD2IE
INT1IE
CNIE
—
MI2C1IE SI2C1IE
0000
0000
Preliminary
© 2007 Microchip Technology Inc.
IEC2
0098
T6IE
DMA4IE
—
OC8IE
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
IEC3
009A
FLTAIE
—
DMA5IE
DCIIE
DCIEIE
QEIIE
PWMIE
C2IE
C2RXIE
INT4IE
INT3IE
T9IE
T8IE
MI2C2IE
SI2C2IE
T7IE
0000
IEC4
009C
—
—
—
—
—
—
—
—
C2TXIE
C1TXIE
DMA7IE
DMA6IE
—
U2EIE
U1EIE
FLTBIE
0000
IPC0
00A4
—
T1IP
—
OC1IP
—
IC1IP
—
INT0IP
4444
IPC1
00A6
—
T2IP
—
OC2IP
—
IC2IP
—
DMA0IP
4444
IPC2
00A8
—
U1RXIP
—
SPI1IP
—
SPI1EIP
—
T3IP
4444
IPC3
00AA
—
—
DMA1IP
—
AD1IP
—
U1TXIP
4444
IPC4
00AC
—
CNIP
—
—
MI2C1IP
—
SI2C1IP
4444
IPC5
00AE
—
IC8IP
—
IC7IP
—
AD2IP
—
INT1IP
4444
IPC6
00B0
—
T4IP
—
OC4IP
—
OC3IP
—
DMA2IP
4444
IPC7
00B2
—
U2TXIP
—
U2RXIP
—
INT2IP
—
T5IP
4444
IPC8
00B4
—
C1IP
—
C1RXIP
—
SPI2IP
—
SPI2EIP
4444
IPC9
00B6
—
IC5IP
—
IC4IP
—
IC3IP
—
DMA3IP
4444
IPC10
00B8
—
OC7IP
—
OC6IP
—
OC5IP
—
IC6IP
4444
IPC11
00BA
—
T6IP
—
DMA4IP
—
—
OC8IP
4444
IPC12
00BC
—
T8IP
—
MI2C2IP
—
SI2C2IP
—
T7IP
4444
IPC13
00BE
—
C2RXIP
—
INT4IP
—
INT3IP
—
T9IP
4444
IPC14
00C0
—
DCIEIP
—
QEIIP
—
PWMIP
—
C2IP
4444
IPC15
00C2
—
FLTAIP
—
—
DMA5IP
—
DCIIP
4444
IPC16
00C4
—
IPC17
00C6
—
Legend:
—
—
—
—
C2TXIP
—
—
—
—
—
—
—
—
—
—
—
0000
—
U2EIP
—
U1EIP
—
FLTBIP
4444
—
C1TXIP
—
DMA7IP
—
DMA6IP
4444
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33F
DS70165E-page 48
TABLE 3-3:
© 2007 Microchip Technology Inc.
TABLE 3-4:
SFR
Name
SFR
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
—
TMR3HLD 0108
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
FFFF
TGATE
TCKPS
—
TSYNC
TCS
—
0000
Timer2 Register
xxxx
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
Preliminary
TMR3
010A
Timer3 Register
xxxx
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR4
0114
Timer4 Register
xxxx
TMR5HLD
0116
Timer5 Holding Register (for 32-bit operations only)
xxxx
TMR5
0118
Timer5 Register
xxxx
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR6
0122
TMR7HLD 0124
FFFF
FFFF
Timer6 Register
xxxx
Timer7 Holding Register (for 32-bit operations only)
xxxx
TMR7
0126
Timer7 Register
xxxx
PR6
0128
Period Register 6
FFFF
PR7
012A
Period Register 7
T6CON
012C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T7CON
012E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR8
0130
TMR9HLD 0132
FFFF
Timer8 Register
xxxx
Timer9 Holding Register (for 32-bit operations only)
xxxx
0134
Timer9 Register
xxxx
PR8
0136
Period Register 8
FFFF
PR9
0138
Period Register 9
T8CON
013A
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T9CON
013C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
FFFF
dsPIC33F
DS70165E-page 49
TMR9
Preliminary
SFR Name
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
IC6BUF
0154
IC6CON
0156
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
Legend:
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
Input 1 Capture Register
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
xxxx
Input 8 Capture Register
—
0000
xxxx
Input 7 Capture Register
—
0000
xxxx
Input 6 Capture Register
—
0000
xxxx
Input 5 Capture Register
—
0000
xxxx
Input 4 Capture Register
—
0000
xxxx
Input 3 Capture Register
—
All
Resets
xxxx
Input 2 Capture Register
—
Bit 0
0000
xxxx
0000
dsPIC33F
DS70165E-page 50
TABLE 3-5:
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
TABLE 3-6:
SFR Name
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Preliminary
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
OC4RS
0192
Output Compare 4 Secondary Register
OC4R
0194
Output Compare 4 Register
OC4CON
0196
OC5RS
0198
Output Compare 5 Secondary Register
OC5R
019A
Output Compare 5 Register
OC5CON
019C
OC6RS
019E
Output Compare 6 Secondary Register
OC6R
01A0
Output Compare 6 Register
OC6CON
01A2
OC7RS
01A4
Output Compare 7 Secondary Register
OC7R
01A6
Output Compare 7 Register
OC7CON
01A8
OC8RS
01AA
Output Compare 8 Secondary Register
OC8R
01AC
Output Compare 8 Register
OC8CON
01AE
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33F
DS70165E-page 51
SFR Name Addr.
8-OUTPUT PWM REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
PTSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
—
Bit 5
Bit 4
PTOPS
Bit 3
Bit 2
PTCKPS
Bit 1
Bit 0
PTMOD
Reset State
PTCON
01C0
PTEN
PTMR
01C2
PTDIR
PWM Timer Count Value Register
0000 0000 0000 0000
PTPER
01C4
—
PWM Time Base Period Register
0000 0000 0000 0000
SEVTCMP
01C6
SEVTDI
R
PWM Special Event Compare Register
0000 0000 0000 0000
Preliminary
PWMCON1 01C8
—
—
—
—
PWMCON2 01CA
—
—
—
—
DTCON1
01CC
DTBPS
DTCON2
01CE
—
FLTACON
01D0
FLTBCON
01D2
OVDCON
01D4 POVD4H
PDC1
01D6
PWM Duty Cycle #1 Register
0000 0000 0000 0000
PDC2
01D8
PWM Duty Cycle #2 Register
0000 0000 0000 0000
PDC3
01DA
PWM Duty Cycle #3 Register
0000 0000 0000 0000
PDC4
01DC
PWM Duty Cycle #4 Register
0000 0000 0000 0000
Legend:
—
PMOD4
PMOD3
PMOD2
PMOD1
0000 0000 0000 0000
SEVOPS
DTB
PEN4H
PEN3H
PEN2H
PEN1H
PEN4L
PEN3L
PEN2L
PEN1L
0000 0000 1111 1111
—
—
—
—
—
IUE
OSYNC
UDIS
0000 0000 0000 0000
DTAPS
DTA
0000 0000 0000 0000
—
—
—
—
—
—
DTS4A
DTS4I
DTS3A
DTS3I
DTS2A
DTS2I
DTS1A
DTS1I
0000 0000 0000 0000
FAOV4H FAOV4L
FAOV3
H
FAOV3L
FAOV2
H
FAOV2L
FAOV1
H
FAOV1L
FLTAM
—
—
—
FAEN4
FAEN3
FAEN2
FAEN1
0000 0000 0000 0000
FBOV4H FBOV4L
FBOV3
H
FBOV3L
FBOV2
H
FBOV2L
FBOV1
H
FBOV1L
FLTBM
—
—
—
FBEN4
FBEN3
FBEN2
FBEN1
0000 0000 0000 0000
POVD3
H
POVD3
L
POVD2
H
POVD2L
POVD1
H
POVD1L
POUT4
H
POUT4
L
POUT3
H
POUT3
L
POUT2
H
POUT2
L
POUT1
H
POUT1
L
1111 1111 0000 0000
POVD4
L
u = uninitialized bit, — = unimplemented, read as ‘0’
dsPIC33F
DS70165E-page 52
TABLE 3-7:
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
TABLE 3-8:
SFR
Name
Addr
.
QEI REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
SWPAB
PCDOUT
CEID
QEOUT
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
QEICON
01E0 CNTERR
—
QEISIDL
INDX
UPDN
DFLTCON
01E2
—
—
—
—
POSCNT
01E4
Position Counter
0000 0000 0000 0000
MAXCNT
01E6
Maximum Count
1111 1111 1111 1111
Legend:
—
QEIM
IMV
TQGATE
TQCKPS
QECK
POSRES TQCS UPDN_SRC
—
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
u = uninitialized bit, — = unimplemented, read as ‘0’
TABLE 3-9:
I2C1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Preliminary
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-10:
I2C2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C2RCV
0210
—
—
—
—
—
—
—
—
Receive Register
0000
I2C2TRN
0212
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C2STAT
0218
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C2ADD
021A
—
—
—
—
—
—
Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All
Resets
0000
DS70165E-page 53
dsPIC33F
Legend:
Bit 7
UART1 REGISTER MAP
SFR Name
SFR
Addr
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
U1TXREG
0224
—
—
U1RXREG
0226
—
—
U1BRG
0228
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-12:
Bit 15
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
UEN1
UEN0
WAKE
LPBACK
UTXBF
TRMT
URXINV
BRGH
RIDLE
PERR
Bit 1
0110
IREN
RTSMD
—
—
UTXBRK
UTXEN
—
—
—
—
—
UART Transmit Register
xxxx
—
—
—
—
—
UART Receive Register
0000
PDSEL
FERR
OERR
Baud Rate Generator Prescaler
0000
UART2 REGISTER MAP
Preliminary
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1
U2TXREG
0234
—
U2RXREG
0236
—
U2BRG
0238
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 15
Bit 14
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
UEN1
UEN0
WAKE
LPBACK
UTXBF
TRMT
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
Bit 12
—
USIDL
IREN
RTSMD
—
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
—
—
—
—
—
—
UART Transmit Register
xxxx
—
—
—
—
—
—
UART Receive Register
0000
URXISEL
Bit 5
Bit 0
Bit 13
PDSEL
FERR
OERR
Baud Rate Generator Prescaler
0000
SPI1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2007 Microchip Technology Inc.
TABLE 3-14:
ABAUD
ADDEN
Bit 2
0000
USIDL
SFR
Addr
SFR
Name
Bit 3
STSEL
—
SFR
Name
TABLE 3-13:
Bit 4
URXDA
Bit 12
URXISEL
Bit 5
All
Resets
Bit 13
UTXINV UTXISEL0
Bit 11
Bit 0
Bit 14
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
0000
0000
0000
SPI2 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
—
—
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI2BUF
0268
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
SPI2 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
0000
0000
0000
dsPIC33F
DS70165E-page 54
TABLE 3-11:
© 2007 Microchip Technology Inc.
TABLE 3-15:
File Name
Addr
ADC1BUF0
0300
AD1CON1
0320
AD1CON2
ADC1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
—
—
CSCNA
CHPS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
ADC Data Buffer 0
0322
VCFG
AD1CON3
0324
ADRC
—
—
AD1CHS123
0326
—
—
—
—
BUFS
—
—
—
CH123SB
—
—
SAMC
—
—
CH123NB
xxxx
SSRC
SMPI
ADCS
—
—
—
0000
CH123NA
AD1CHS0
0328
CH0NB
CH0NA
—
—
AD1PCFGH
032A
PCFG31 PCFG30
PCFG29
PCFG28
PCFG27 PCFG26 PCFG25
PCFG24
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19 PCFG18 PCFG17
PCFG16
0000
AD1PCFGL
032C
PCFG15 PCFG14
PCFG13
PCFG12
PCFG11 PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
AD1CSSH
032E
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
0000
AD1CSSL
0330
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
AD1CON4
0332
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
Legend:
—
CH0SA
0000
DMABL
0000
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-16:
ADC2 REGISTER MAP
Preliminary
File Name
Addr
ADC2BUF0
0340
AD2CON1
0360
AD2CON2
0362
AD2CON3
0364
ADRC
—
—
AD2CHS123
0366
—
—
AD2CHS0
0368
CH0NB
Reserved
036A
—
AD2PCFGL
036C
Reserved
036E
—
AD2CSSL
0370
AD2CON4
0372
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
—
—
CSCNA
CHPS
—
—
—
—
—
—
—
—
—
PCFG13
PCFG12
—
—
—
—
CSS15
CSS14
CSS13
CSS12
—
—
—
—
Bit 7
ADC Data Buffer 0
VCFG
PCFG15 PCFG14
CH123NB
BUFS
—
—
—
—
—
—
—
CH123SB
CH0SB
xxxx
SSRC
SAMC
All
Resets
SMPI
ADCS
—
0000
CH123NA
CH0NA
—
—
—
—
—
—
—
—
—
—
—
—
—
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
—
—
—
—
—
—
—
—
—
—
—
0000
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
—
—
—
—
—
—
—
—
—
—
—
PCFG11 PCFG10
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CH0SA
DMABL
0000
0000
0000
0000
DS70165E-page 55
dsPIC33F
Legend:
CH0SB
File Name Addr
DMA REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DMA0CON 0380
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
DMA0REQ 0382
FORCE
—
—
—
—
—
—
—
—
Bit 5
Bit 4
AMODE
Bit 3
Bit 2
—
—
Bit 1
Bit 0
MODE
IRQSEL
All
Resets
0000
0000
DMA0STA
0384
STA
0000
DMA0STB
0386
STB
0000
DMA0PAD
0388
PAD
DMA0CNT
038A
—
—
—
—
—
—
DMA1CON 038C
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA1REQ 038E
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA1STA
0390
STA
0000
DMA1STB
0392
STB
0000
DMA1PAD
0394
PAD
DMA1CNT
0396
—
—
—
—
—
—
DMA2CON 0398
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA2REQ 039A
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
Preliminary
DMA2STA
039C
STA
0000
DMA2STB
039E
STB
0000
DMA2PAD
03A0
PAD
DMA2CNT
03A2
—
—
—
—
—
—
DMA3CON 03A4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA3REQ 03A6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA3STA
03A8
STA
0000
DMA3STB
03AA
STB
0000
DMA3PAD 03AC
PAD
DMA3CNT 03AE
—
—
—
—
—
—
DMA4CON 03B0
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA4REQ 03B2
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
© 2007 Microchip Technology Inc.
DMA4STA
03B4
STA
0000
DMA4STB
03B6
STB
0000
DMA4PAD
03B8
PAD
DMA4CNT 03BA
—
—
—
—
—
—
DMA5CON 03BC
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA5REQ 03BE
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
IRQSEL
—
MODE
0000
0000
DMA5STA
03C0
STA
0000
DMA5STB
03C2
STB
0000
DMA5PAD
03C4
PAD
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33F
DS70165E-page 56
TABLE 3-17:
© 2007 Microchip Technology Inc.
TABLE 3-17:
File Name Addr
DMA REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
—
DMA5CNT 03C6
—
—
—
—
—
—
DMA6CON 03C8
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
—
—
—
—
—
—
—
DMA6REQ 03CA FORCE
Bit 5
Bit 4
Bit 3
Bit 2
—
—
Bit 1
Bit 0
CNT
AMODE
All
Resets
0000
MODE
IRQSEL
0000
0000
DMA6STA
03CC
STA
0000
DMA6STB
03CE
STB
0000
DMA6PAD
03D0
PAD
DMA6CNT 03D2
—
—
—
—
—
—
DMA7CON 03D4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA7REQ 03D6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA7STA
03D8
STA
0000
DMA7STB
03DA
STB
0000
DMA7PAD 03DC
PAD
DMA7CNT 03DE
—
—
—
—
—
CNT
Preliminary
DMACS0
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0
DMACS1
03E2
DSADR
03E4
Legend:
—
—
—
—
0000
—
LSTCH
XWCOL7
PPST7
DSADR
XWCOL6 XWCOL5
PPST6
PPST5
0000
XWCOL4
XWCOL3
XWCOL2
PPST4
PPST3
PPST2
XWCOL1 XWCOL0
PPST1
PPST0
0000
0000
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33F
DS70165E-page 57
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
C1CTRL1
0400
—
—
CSIDL
ABAT
CANCK
S
C1CTRL2
0402
—
—
—
—
—
C1VEC
0404
—
—
—
C1FCTRL
0406
Bit 9
Bit 8
Bit 7
REQOP
—
—
—
Bit 5
OPMODE
—
—
—
FILHIT
DMABS
Bit 6
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Reset
s
—
CANCAP
—
—
WIN
0480
—
DNCNT
—
—
—
—
—
0000
ICODE
—
—
0000
0000
FSA
Preliminary
C1FIFO
0408
—
—
—
—
C1INTF
040A
—
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
C1INTE
040C
—
—
—
—
—
—
—
—
IVRIE
WAKIE
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
C1EC
040E
C1CFG1
0410
—
—
—
—
—
C1CFG2
0412
—
WAKFIL
—
—
—
C1FEN1
0414
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
C1FMSKSEL1
0418
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C1FMSKSEL2
041A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
FNRB
TERRCNT
0000
RERRCNT
—
—
—
SEG2PH
FLTEN10
FLTEN9
SJW
SAM
FLTEN7
FLTEN6
FLTEN8
SEG1PH
FLTEN5
FLTEN4
0000
PRSEG
FLTEN3
0000
0000
BRP
SEG2PHT
S
0000
FLTEN2
FLTEN1
0000
FLTEN0
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-19:
File Name
FBP
Addr
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0400041E
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
See definition when WIN = x
© 2007 Microchip Technology Inc.
C1RXFUL1
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9
RXFUL0
0000
C1RXFUL2
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
RXFUL8
0000
C1RXOVF1
0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9
RXOVF0
0000
C1RXOVF2
042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
0000
RXOVF8
RXFUL7
RXOVF7
RXFUL6
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
C1TR01CON 0430
TXEN1
TXABT1
TXLARB1
TXERR1
TXREQ1
RTREN1
TX1PRI
TXEN0
TXABAT0 TXLARB0
TXERR0
TXREQ0
RTREN0
TX0PRI
0000
C1TR23CON 0432
TXEN3
TXABT3
TXLARB3
TXERR3
TXREQ3
RTREN3
TX3PRI
TXEN2
TXABAT2 TXLARB2
TXERR2
TXREQ2
RTREN2
TX2PRI
0000
C1TR45CON 0434
TXEN5
TXABT5
TXLARB5
TXERR5
TXREQ5
RTREN5
TX5PRI
TXEN4
TXABAT4 TXLARB4
TXERR4
TXREQ4
RTREN4
TX4PRI
0000
C1TR67CON 0436
TXEN7
TXABT7
TXLARB7
TXERR7
TXREQ7
RTREN7
TX7PRI
TXEN6
TXABAT6 TXLARB6
TXERR6
TXREQ6
RTREN6
TX6PRI
xxxx
C1RXD
0440
Received Data Word
xxxx
C1TXD
0442
Transmit Data Word
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33F
DS70165E-page 58
TABLE 3-18:
© 2007 Microchip Technology Inc.
TABLE 3-20:
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0400041E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
Preliminary
0420
F3BP
F2BP
F1BP
F0BP
0000
C1BUFPNT2
0422
F7BP
F6BP
F5BP
F4BP
0000
C1BUFPNT3
0424
F11BP
F10BP
F9BP
F8BP
0000
C1BUFPNT4
0426
F15BP
F14BP
F13BP
F12BP
0000
C1RXM0SID
0430
—
EID
xxxx
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
SID
C1RXM0EID
0432
EID
C1RXM1SID
0434
SID
C1RXM1EID
0436
EID
C1RXM2SID
0438
SID
C1RXM2EID
043A
EID
C1RXF0SID
0440
SID
C1RXF0EID
0442
EID
C1RXF1SID
0444
SID
C1RXF1EID
0446
EID
C1RXF2SID
0448
SID
C1RXF2EID
044A
EID
C1RXF3SID
044C
SID
C1RXF3EID
044E
EID
C1RXF4SID
0450
SID
C1RXF4EID
0452
EID
C1RXF5SID
0454
SID
C1RXF5EID
0456
EID
C1RXF6SID
0458
SID
C1RXF6EID
045A
EID
C1RXF7SID
045C
SID
C1RXF7EID
045E
EID
C1RXF8SID
0460
SID
C1RXF8EID
0462
EID
C1RXF9SID
0464
SID
C1RXF9EID
0466
EID
C1RXF10SID
0468
SID
C1RXF10EID
046A
EID
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SID
—
SID
—
MIDE
EID
MIDE
xxxx
EID
SID
—
MIDE
xxxx
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
xxxx
xxxx
xxxx
dsPIC33F
DS70165E-page 59
C1BUFPNT1
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C1RXF11SID
046C
SID
C1RXF11EID
046E
EID
C1RXF12SID
0470
SID
C1RXF12EID
0472
EID
C1RXF13SID
0474
SID
C1RXF13EID
0476
EID
C1RXF14SID
0478
SID
C1RXF14EID
047A
EID
C1RXF15SID
047C
SID
C1RXF15EID
047E
EID
Legend:
Bit 10
Bit 9
Bit 8
Bit 7
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
SID
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
EXIDE
—
EID
—
EID
—
EID
—
EID
—
EID
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
All
Resets
xxxx
xxxx
xxxx
xxxx
dsPIC33F
DS70165E-page 60
TABLE 3-20:
Preliminary
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
TABLE 3-21:
File Name
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
C2CTRL1
0500
—
—
CSIDL
ABAT
CANCKS
C2CTRL2
0502
—
—
—
—
—
C2VEC
0504
—
—
—
C2FCTRL
0506
—
—
TXBP
RXBP
TXWAR
—
—
—
Bit 8
Bit 7
—
—
—
—
—
REQOP
—
Bit 5
OPMODE
FILHIT
DMABS
Bit 6
—
—
—
—
Bit 4
Bit 3
—
CANCAP
Bit 1
Bit 0
—
—
WIN
DNCNT
—
—
Bit 2
0480
0000
ICODE
—
All
Resets
0000
0000
FSA
C2FIFO
0508
—
—
C2INTF
050A
—
—
TXBO
C2INTE
050C
—
—
—
C2EC
050E
C2CFG1
0510
—
—
—
—
—
C2CFG2
0512
—
WAKFIL
—
—
—
SEG2PH
SEG2PHTS
C2FEN1
0514
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10 FLTEN9 FLTEN8
FLTEN7
C2FMSKSEL1
0518
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C2FMSKSEL2
051A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Preliminary
Legend:
RXWAR EWARN
—
—
—
—
IVRIF
WAKIF
ERRIF
FNRB
IVRIE
WAKIE
ERRIE
TERRCNT
0000
—
FIFOIF
RBOVIF
RBIF
TBIF
—
FIFOIE
RBOVIE
RBIE
TBIE
RERRCNT
—
—
—
SJW
SEG1PH
0000
PRSEG
FLTEN6 FLTEN5 FLTEN4 FLTEN3
0000
0000
BRP
SAM
0000
FLTEN2 FLTEN1
0000
FLTEN0
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-22:
File Name
FBP
Addr
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0500051E
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
See definition when WIN = x
C2RXFUL1
0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10
RXFUL0
0000
C2RXFUL2
0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
RXFUL9
RXFUL8
RXFUL7
RXFUL6
0000
C2RXOVF1
0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7
0000
C2RXOVF2
052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
0000
TXEN1
TX
ABAT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
TX1PRI
TXEN0
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
TX0PRI
0000
C2TR23CON 0532
TXEN3
TX
ABAT3
TX
LARB3
TX
ERR3
TX
REQ3
RTREN3
TX3PRI
TXEN2
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
RTREN2
TX2PRI
0000
C2TR45CON 0534
TXEN5
TX
ABAT5
TX
LARB5
TX
ERR5
TX
REQ5
RTREN5
TX5PRI
TXEN4
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
RTREN4
TX4PRI
0000
C2TR67CON 0536
TXEN7
TX
ABAT7
TX
LARB7
TX
ERR7
TX
REQ7
RTREN7
TX7PRI
TXEN6
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
RTREN6
TX6PRI
xxxx
C2RXD
0540
Recieved Data Word
xxxx
C2TXD
0542
Transmit Data Word
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33F
DS70165E-page 61
C2TR01CON 0530
File Name
Addr
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0500
051E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Reset
s
See definition when WIN = x
C2BUFPNT1
0520
F3BP
F2BP
F1BP
F0BP
0000
C2BUFPNT2
0522
F7BP
F6BP
F5BP
F4BP
0000
C2BUFPNT3
0524
F11BP
F10BP
F9BP
F8BP
0000
C2BUFPNT4
0526
F15BP
F14BP
F13BP
F12BP
C2RXM0SID
0530
SID
Preliminary
© 2007 Microchip Technology Inc.
C2RXM0EID
0532
EID
C2RXM1SID
0534
SID
C2RXM1EID
0536
EID
C2RXM2SID
0538
SID
C2RXM2EID
053A
EID
C2RXF0SID
0540
SID
C2RXF0EID
0542
EID
C2RXF1SID
0544
SID
C2RXF1EID
0546
EID
C2RXF2SID
0548
SID
C2RXF2EID
054A
EID
C2RXF3SID
054C
SID
C2RXF3EID
054E
EID
C2RXF4SID
0550
SID
C2RXF4EID
0552
EID
C2RXF5SID
0554
SID
C2RXF5EID
0556
EID
C2RXF6SID
0558
SID
C2RXF6EID
055A
EID
C2RXF7SID
055C
SID
