Data Sheet
November 2016
MAX24287
1Gbps Parallel-to-Serial MII Converter
General Description
Highlighted Features
The MAX24287 is a flexible, low-cost Ethernet
interface conversion IC. The parallel interface can be
configured for GMII, RGMII, TBI, RTBI, or 10/100 MII,
while the serial interface can be configured for
1.25Gbps SGMII or 1000BASE-X operation. In
SGMII mode, the device interfaces directly to
Ethernet switch ICs, ASIC MACs, and 1000BASE-T
electrical SFP modules. In 1000BASE-X mode, the
device interfaces directly to 1Gbps 1000BASE-X SFP
optical modules. The MAX24287 performs automatic
translation of link speed and duplex autonegotiation
between parallel MII MDIO and the serial interface.
Bidirectional Wire-Speed Ethernet Interface
Conversion
Can Interface Directly to SFP Modules and
SGMII PHY and Switch ICs
Serial Interface Configurable as 1000BASE-X or
SGMII Revision 1.8 (4-, 6-, or 8-Pin)
Parallel Interface Configurable as GMII, RGMII,
Serial Interface Has Clock and Data Recovery
Block (CDR) and Does Not Require a Clock
Input
This device is ideal for interfacing single-channel
GMII/MII devices such as microprocessors, FPGAs,
network processors, Ethernet-over-SONET or -PDH
mappers, and TDM-over-packet circuit emulation
devices. The device also provides a convenient
solution to interface such devices with electrical or
optical Ethernet SFP modules.
Translates Link Speed and Duplex Mode
Negotiation Between MDIO and SGMII PCS
Supports 10/100 MII or RGMII Operation with
SGMII Running at the Same Rate
Configurable for 10/100 MII DTE or DCE
Modes (i.e., Connects to PHY or MAC)
Can Also Be Configured as General-Purpose
1:10 SerDes with Optional Comma Alignment
Supports Synchronous Ethernet by Providing
a 25MHz or 125MHz Recovered Clock and
Accepting a Transmit Clock
Can Provide a 125MHz Clock for the MAC to
Use as GTXCLK
Accepts 10MHz, 12.8MHz, 25MHz or 125MHz
Reference Clock
Software Control Through MDIO Interface
GPIO Pins Can Be Configured as Clocks,
Status Signals and Interrupt Outputs
1.2V Operation with 3.3V I/O
Small, 8mm x 8mm, 68-Pin TQFN Package
Applications
Any System with a Need to Interface a Component
with a Parallel MII Interface (GMII, RGMII, TBI RTBI,
10/100 MII) to a Component with an SGMII or
1000BASE-X Interface
Switches and Routers
Telecom Equipment
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX24287ETK+
-40C to +85C
MAX24287ETK+T
-40C to +85C
68 TQFN-EP*
68 TQFN-EP*
Tape and Reel
TBI, RTBI, or 10/100 MII
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Block Diagram appears on page 7.
Register Map appears on page 42.
1
MAX24287
Table of Contents
1.
APPLICATION EXAMPLES .......................................................................................................... 6
2.
BLOCK DIAGRAM ........................................................................................................................ 7
3.
DETAILED FEATURES ................................................................................................................. 7
4.
ACRONYMS, ABBREVIATIONS, AND GLOSSARY .................................................................... 8
5.
PIN DESCRIPTIONS ..................................................................................................................... 8
6.
FUNCTIONAL DESCRIPTION .................................................................................................... 17
6.1
6.2
PIN CONFIGURATION DURING RESET ........................................................................................... 17
GENERAL-PURPOSE I/O.............................................................................................................. 18
6.2.1
6.3
6.3.1
6.3.2
6.4
Reset .................................................................................................................................................... 19
Processor Interrupts ............................................................................................................................. 19
MDIO INTERFACE....................................................................................................................... 20
6.4.1
6.4.2
MDIO Overview .................................................................................................................................... 20
Examples of MAX24287 and PHY Management Using MDIO ............................................................ 22
SERIAL INTERFACE – 1000BASE-X OR SGMII ............................................................................. 24
PARALLEL INTERFACE – GMII, RGMII, TBI, RTBI, MII .................................................................. 25
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.7
GMII Mode ........................................................................................................................................... 25
TBI Mode .............................................................................................................................................. 26
RGMII Mode ......................................................................................................................................... 27
RTBI Mode ........................................................................................................................................... 29
MII Mode .............................................................................................................................................. 30
AUTO-NEGOTIATION (AN) ........................................................................................................... 31
6.7.1
6.7.2
6.8
1000BASE-X Auto-Negotiation ............................................................................................................ 31
SGMII Control Information Transfer ..................................................................................................... 33
DATA PATHS .............................................................................................................................. 36
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.9
GMII, RGMII and MII Serial to Parallel Conversion and Decoding ...................................................... 36
GMII, RGMII and MII Parallel to Serial Conversion and Encoding ...................................................... 36
TBI, RTBI Serial to Parallel Conversion and Decoding ....................................................................... 36
TBI Parallel to Serial Conversion and Encoding .................................................................................. 36
Rate Adaption Buffers, Jumbo Packets and Clock Frequency Differences ......................................... 36
TIMING PATHS ............................................................................................................................ 37
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.10
6.11
6.12
6.13
6.14
RX PLL ................................................................................................................................................. 38
TX PLL ................................................................................................................................................. 38
Input Jitter Tolerance ........................................................................................................................... 38
Output Jitter Generation ....................................................................................................................... 38
TX PLL Jitter Transfer .......................................................................................................................... 38
GPIO Pins as Clock Outputs ................................................................................................................ 39
LOOPBACKS ............................................................................................................................ 39
6.10.1
6.10.2
6.10.3
7.
Receive Recovered Clock Squelch Criteria ......................................................................................... 19
RESET AND PROCESSOR INTERRUPT ........................................................................................... 19
Diagnostic Loopback ............................................................................................................................ 39
Terminal Loopback ............................................................................................................................... 39
Remote Loopback ................................................................................................................................ 39
DIAGNOSTIC AND TEST FUNCTIONS .......................................................................................... 40
DATA PATH LATENCIES ............................................................................................................ 40
POWER SUPPLY CONSIDERATIONS ........................................................................................... 40
STARTUP PROCEDURE ............................................................................................................ 41
REGISTER DESCRIPTIONS ....................................................................................................... 42
7.1
REGISTER MAP .......................................................................................................................... 42
2
MAX24287
7.2
REGISTER DESCRIPTIONS ........................................................................................................... 42
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
8.
BMCR ................................................................................................................................................... 43
BMSR ................................................................................................................................................... 44
ID1 and ID2 .......................................................................................................................................... 45
AN_ADV ............................................................................................................................................... 46
AN_RX ................................................................................................................................................. 46
AN_EXP ............................................................................................................................................... 46
EXT_STAT ........................................................................................................................................... 47
JIT_DIAG ............................................................................................................................................. 47
PCSCR ................................................................................................................................................. 48
GMIICR ................................................................................................................................................ 49
CR ........................................................................................................................................................ 50
IR .......................................................................................................................................................... 51
PAGESEL ............................................................................................................................................ 52
ID .......................................................................................................................................................... 53
GPIOCR1 ............................................................................................................................................. 53
GPIOCR2 ............................................................................................................................................. 53
GPIOSR ............................................................................................................................................... 54
PTPCR1 ............................................................................................................................................... 55
JTAG AND BOUNDARY SCAN .................................................................................................. 56
8.1
8.2
8.3
8.4
JTAG DESCRIPTION ................................................................................................................... 56
JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................. 56
JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................... 58
JTAG TEST REGISTERS .............................................................................................................. 59
ELECTRICAL CHARACTERISTICS ........................................................................................... 60
9.1
9.2
RECOMMENDED OPERATING CONDITIONS .................................................................................... 60
DC ELECTRICAL CHARACTERISTICS ............................................................................................ 60
9.
9.2.1
9.2.2
9.3
CMOS/TTL DC Characteristics ............................................................................................................ 61
SGMII/1000BASE-X DC Characteristics.............................................................................................. 61
AC ELECTRICAL CHARACTERISTICS ............................................................................................. 62
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
REFCLK AC Characteristics ................................................................................................................ 62
SGMII/1000BASE-X Interface Receive AC Characteristics ................................................................. 62
SGMII/1000BASE-X Interface Transmit AC Characteristics ................................................................ 62
Parallel Interface Receive AC Characteristics ..................................................................................... 63
Parallel Interface Transmit AC Characteristics .................................................................................... 65
MDIO Interface AC Characteristics ...................................................................................................... 67
JTAG Interface AC Characteristics ...................................................................................................... 68
10.
PIN ASSIGNMENTS.................................................................................................................... 69
11.
PACKAGE AND THERMAL INFORMATION .............................................................................. 70
12.
DATA SHEET REVISION HISTORY ........................................................................................... 71
3
MAX24287
List of Figures
Figure 2-1. Block Diagram ........................................................................................................................................... 7
Figure 6-1. MDIO Slave State Machine ..................................................................................................................... 21
Figure 6-2. Management Information Flow Options, Case 1,Tri-Mode PHY ............................................................. 22
Figure 6-3. Management Information Flow Options, Case 2, SGMII Switch Chip .................................................... 22
Figure 6-4. Management Information Flow Options, Case 3, 1000BASE-X Interface .............................................. 23
Figure 6-5. Recommended External Components for High-Speed Serial Interface ................................................. 24
Figure 6-6. Auto-Negotiation with a Link Partner over 1000BASE-X ........................................................................ 32
Figure 6-7. 1000BASE-X Auto-Negotiation tx_Config_Reg and rx_Config_Reg Fields ........................................... 32
Figure 6-8. SGMII Control Information Generation, Reception and Acknowledgement ............................................ 34
Figure 6-9. SGMII tx_Config_Reg and rx_Config_Reg Fields .................................................................................. 34
Figure 6-10. Timing Path Diagram............................................................................................................................. 37
Figure 8-1. JTAG Block Diagram ............................................................................................................................... 56
Figure 8-2. JTAG TAP Controller State Machine ...................................................................................................... 58
Figure 9-1. MII/GMII/RGMII/TBI/RTBI Receive Timing Waveforms .......................................................................... 63
Figure 9-2. MII/GMII/RGMII/TBI/RTBI Transmit Timing Waveforms ......................................................................... 65
Figure 9-3. MDIO Interface Timing ............................................................................................................................ 67
Figure 9-4. JTAG Timing Diagram ............................................................................................................................. 68
4
MAX24287
List of Tables
Table 5-1. Pin Type Definitions .................................................................................................................................... 8
Table 5-2. Detailed Pin Descriptions – Global Pins (2 Pins) ....................................................................................... 8
Table 5-3. Detailed Pin Descriptions – MDIO Interface (2 Pins) ................................................................................. 9
Table 5-4. Detailed Pin Descriptions – JTAG Interface (5 pins) .................................................................................. 9
Table 5-5. Detailed Pin Descriptions – GPIO signals (5 dedicated pins, 4 shared pins) ............................................ 9
Table 5-6. Detailed Pin Descriptions – SGMII/1000BASE-X Serial Interface (7 pins) .............................................. 11
Table 5-7. Detailed Pin Descriptions – Parallel Interface (25 pins) ........................................................................... 11
Table 5-8. Detailed Pin Descriptions – Power and Ground Pins (17 pins) ................................................................ 16
Table 6-1. Reset Configuration Pins, 15-Pin Mode (COL=0) .................................................................................... 17
Table 6-2. Parallel Interface Configuration ................................................................................................................ 17
Table 6-3. Reset Configuration Pins, 3-Pin Mode (COL=1) ...................................................................................... 18
Table 6-4. GPO1, GPIO1 and GPIO3 Configuration Options ................................................................................... 18
Table 6-5. GPO2 and GPIO2 Configuration Options ................................................................................................. 18
Table 6-6. GPIO4, GPIO5, GPIO6 and GPIO7 Configuration Options ..................................................................... 19
Table 6-7. Parallel Interface Modes ........................................................................................................................... 25
Table 6-8. GMII Parallel Bus Pin Naming .................................................................................................................. 25
Table 6-9. TBI Parallel Bus Pin Naming (Normal Mode} ........................................................................................... 26
Table 6-10. TBI Parallel Bus Pin Naming (One-Clock Mode) ................................................................................... 26
Table 6-11. RGMII Parallel Bus Pin Naming ............................................................................................................. 28
Table 6-12. RTBI Parallel Bus Pin Naming ............................................................................................................... 29
Table 6-13. MII Parallel Bus Pin Naming ................................................................................................................... 30
Table 6-14. AN_ADV 1000BASE-X Auto-Negotiation Ability Advertisement Register (MDIO 4) .............................. 32
Table 6-15. AN_RX 1000BASE-X Auto-negotiation Ability Receive Register (MDIO 5) ........................................... 33
Table 6-16. AN_ADV SGMII Configuration Information Register (MDIO 4) .............................................................. 35
Table 6-17. AN_RX SGMII Configuration Information Receive Register (MDIO 5) .................................................. 35
Table 6-18. Timing Path Muxes – No Loopback ....................................................................................................... 37
Table 6-19. Timing Path Muxes – DLB Loopback ..................................................................................................... 37
Table 6-20. Timing Path Muxes – RLB Loopback ..................................................................................................... 38
Table 6-21. GMII Data Path Latencies ...................................................................................................................... 40
Table 7-1. Register Map ............................................................................................................................................ 42
Table 8-1. JTAG Instruction Codes ........................................................................................................................... 58
Table 8-2. JTAG ID Code .......................................................................................................................................... 59
Table 9-1. Recommended DC Operating Conditions ................................................................................................ 60
Table 9-2. DC Characteristics.................................................................................................................................... 60
Table 9-3. DC Characteristics for Parallel and MDIO Interfaces ............................................................................... 61
Table 9-4. SGMII/1000BASE-X Transmit DC Characteristics ................................................................................... 61
Table 9-5. SGMII/1000BASE-X Receive DC Characteristics .................................................................................... 61
Table 9-6. REFCLK AC Characteristics .................................................................................................................... 62
Table 9-7. 1000BASE-X and SGMII Receive AC Characteristics ............................................................................. 62
Table 9-8. 1000BASE-X and SGMII Receive Jitter Tolerance .................................................................................. 62
Table 9-9. SGMII and 1000BASE-X Transmit AC Characteristics ............................................................................ 62
Table 9-10. 1000BASE-X Transmit Jitter Characteristics ......................................................................................... 62
Table 9-11. GMII and TBI Receive AC Characteristics ............................................................................................. 63
Table 9-12. RGMII-1000 and RTBI Receive AC Characteristics ............................................................................... 64
Table 9-13. RGMII-10/100 Receive AC Characteristics ............................................................................................ 64
Table 9-14. MII–DCE Receive AC Characteristics .................................................................................................... 64
Table 9-15. MII–DTE Receive AC Characteristics .................................................................................................... 65
Table 9-16. GMII, TBI, RGMII-1000 and RTBI Transmit AC Characteristics ............................................................ 65
Table 9-17. RGMII-10/100 Transmit AC Characteristics ........................................................................................... 66
Table 9-18. MII–DCE Transmit AC Characteristics ................................................................................................... 66
Table 9-19. MII–DTE Transmit AC Characteristics ................................................................................................... 66
Table 9-20. MDIO Interface AC Characteristics ........................................................................................................ 67
Table 9-21. JTAG Interface Timing............................................................................................................................ 68
Table 11-1. Package Thermal Properties, Natural Convection ................................................................................. 71
5
MAX24287
1. Application Examples
a) Copper Media
RXD[7:0]
Processor, M
ASIC,
A
FPGA
C
RX_CLK
125 MHz
TXD[7:0]
CDR
MAX
24287
TX_CLK
125 MHz
RD
TD
SGMII
PHY
TCLK
625 MHz
(Optional)
b) Connect Parallel MII Component to SGMII Component
RXD[7:0]
Processor, M
ASIC,
A
FPGA
C
RX_CLK
125 MHz
TXD[7:0]
CDR
MAX
24287
TX_CLK
125 MHz
Processor, M
ASIC,
A
FPGA
C
c2)
RX_CLK
125 MHz
TXD[7:0]
CDR
RD
MAX
24287
TX_CLK
125 MHz
TD
RXD[7:0]
Processor, M
ASIC,
A
FPGA
C
TD
RX_CLK
125 MHz
TXD[7:0]
M Ethernet
A Switch
Chip
C
TCLK
625 MHz
(Optional)
c1) Long PCB Trace Card-to-Card
RXD[7:0]
RD
CDR
RD
MAX
24287
TX_CLK
125 MHz
TD
C
o
n
n
e
c
t
o
r
100 Ohm
PCB Trace
C
o
n
n
e
c
t
o
r
100 Ohm
PCB Trace
100 Ohm
PCB Trace
C
o
n
n
e
c
t
o
r
TD
TXD[7:0]
MAX
24287
RD
CDR
TXCLK
125 MHz
RXD[7:0]
GMII
PHY
RXCLK
125 MHz
100 Ohm
PCB Trace
C
o
n
n
e
c
t
o
r
TD
SGMII
PHY
RD
d) Fiber Module
RXD[7:0]
Processor, M
ASIC,
A
FPGA
C
RX_CLK
125 MHz
TXD[7:0]
TX_CLK
125 MHz
1000BASE-SX/LX
CDR
RD
MAX
24287
Optical
Module
TD
6
MAX24287
2. Block Diagram
Figure 2-1. Block Diagram
MAX24287
TXD[7:0]
GTXCLK
TXCLK
TX_EN
TX_ER
Transmit
GMII
RGMII
TBI
RTBI
MII
D
D
C
C
PCS
Decoder
(10b/8b)
Rate
Adaption
Buffer
RD[9:0]
RD
125MHz
1.25GHz
DeSerializer
AutoNegotiate
Receive
CDR
RDP
RDN
TLB Loopback
Receive
GMII
RGMII
TBI
RTBI
MII
DLB Loopback
RLB Loopback
RXD[7:0]
RXCLK
RX_DV
RX_ER
COL
CRS
TDP
D
C
Rate
Adaption
Buffer
D
PCS
Encoder
(8b/10b)
C
TD[9:0]
TD
Serializer
125MHz
625MHz
Transmit
Driver
TDN
TCLKP
TCLKN
625MHz
125MHz, 62.5MHz, 25MHz, 2.5MHz
Control
and
Status
125MHz
TX PLL
REFCLK
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPO2
GPIO Control
GPO1
MDIO
MDC
RST_N
ALOS
3. Detailed Features
General Features
High-speed MDIO interface (12.5MHz slave only) with optional preamble suppression
Operates from a 10, 12.8, 20, 25, or 125MHz reference clock
Optional 125MHz output clock for MAC to use as GTXCLK
Parallel-Serial MII Conversion Features
Bidirectional wire-speed interface conversion
Serial Interface: 1000BASE-X or SGMII revision 1.8 (4-, 6-, or 8-Pin)
Parallel Interface: GMII, RGMII (10, 100 and 1000Mbps), TBI, RTBI or 10/100 MII (DTE or DCE)
8-pin source-clocked SGMII mode
4-pin 1000BASE-X SerDes mode to interface with optical modules
Connects processors with parallel MII interfaces to 1000BASE-X SFP optical modules
Connects processors with parallel MII interfaces to PHY or switch ICs with SGMII interfaces
Interface conversion is transparent to MAC layer and higher layers
Translates link speed and duplex mode between GMII/MII MDIO and SGMII PCS
Configurable for 10/100 MII DTE or DCE Modes (i.e., connects to PHY or MAC)
Synchronous Ethernet Features
Receive path bit clock can be output on a GPIO pin to line-time the system from the Ethernet port
Transmit path can be frequency-locked to a system clock signal connected to the REFCLK pin
7
MAX24287
4. Acronyms, Abbreviations, and Glossary
DCE
DDR
DTE
PCB
PHY
Data Communication Equipment
Dual Data Rate (data driven and latched on both clock edges)
Data Terminating Equipment
Printed Circuit Board
Physical. Refers to either a transceiver device or a protocol layer
Ingress
Egress
Receive
Transmit
The serial (SGMII) to parallel (GMII) direction
The parallel (GMII) to serial (SGMII) direction
The serial (SGMII) to parallel (GMII) direction
The parallel (GMII) to serial (SGMII) direction
5. Pin Descriptions
Note that some pins have different pin names and functions under different configurations.
Table 5-1. Pin Type Definitions
Type
Definition
I
Input
Idiff
Input, differential
Ipu
Input, with pullup
Ipd
Input, with pulldown
IO
Bidirectional
IOr
Bidirectional, sampled at reset
IOz
Bidirectional, can go high impedance
O
Output
Odiff
Output, differential (CML)
Oz
Output, can go high impedance
Table 5-2. Detailed Pin Descriptions – Global Pins (2 Pins)
Pin Name
PIN # Type
Pin Description
Reset (active low, asynchronous)
RST_N
67
I
This signal resets all logic, state machines and registers in the device. Pin states
are sampled and used to set the default values of several register fields as
described in 6.1. RST_N should be held low for at least 100s. See section
6.3.1.
Reference Clock
REFCLK
68
I
This signal is the reference clock for the device. The frequency can be 10MHz,
12.8MHz, 25MHz or 125MHz ± 100 ppm. At reset the frequency is specified
using the RXD[3:2] pins (see section 6.1). The REFCLK signal is the input clock
to the TX PLL. See section 6.9.
Note: REFCLK frequency cannot be changed dynamically among the
frequencies listed above. To change REFCLK frequency, (1) power down
MAX24287, (2) change REFCLK frequency, then (3) power up MAX24287.
REFCLK is an analog input that is internally biased with a 10k resistor to 1.2V.
This support AC-coupling if desired.
8
MAX24287
Pin Name
TEST0
PIN #
45
Type
I
Pin Description
Factory Test. Connect to DVDD33.
TEST1
64
I
Factory Test. Connect to DVDD33 or DVSS.
TEST2
63
I
Factory Test. Connect to DVDD33 or DVSS.
TEST3
62
I/O
Factory Test. Connect to DVDD33 or DVSS.
Table 5-3. Detailed Pin Descriptions – MDIO Interface (2 Pins)
Pin Name
PIN # Type
Pin Description
MDIO Clock.
MDC
41
I
MDC is the clock signal of the 2-wire MDIO interface. It can be any frequency up
to 12.5MHz. See section 6.4.
MDIO Data.
MDIO
42
IOz
This is the bidirectional, half-duplex data signal of the MDIO interface. It is
sampled and updated on positive edges of MDC. IEEE 802.3 requires a 2k±5%
pulldown resistor on this signal at the MAC. See section 6.4.
Table 5-4. Detailed Pin Descriptions – JTAG Interface (5 pins)
Pin Name
PIN # Type
Pin Description
JTAG Test Reset (active low).
JTRST_N
43
I
Asynchronously resets the test access port (TAP) controller. JTRST_N should be
held low during device power-up. If not used, JTRST_N can be held low or high
after power-up. See section 7.2.18.
JTAG Test Clock.
JTCLK
21
I
This clock signal can be any frequency up to 10MHz. JTDI and JTMS are
sampled on the rising edge of JTCLK, and JTDO is updated on the falling edge
of JTCLK. If not used, connect to DVDD33 or DVSS. See section 7.2.18.
JTAG Test Mode Select.
JTMS
22
I
Sampled on the rising edge of JTCLK. Used to place the port into the various
defined IEEE 1149.1 states. If not used, connect to DVDD33. See section
7.2.18.
JTAG Test Data Input.
JTDI
23
I
Test instructions and data are clocked in on this pin on the rising edge of JTCLK.
If not used, connect to DVDD33. See section 7.2.18.
JTAG Test Data Output.
JTDO
44
Oz
Test instructions and data are clocked out on this pin on the falling edge of
JTCLK. If not used leave unconnected. See section 7.2.18.
Table 5-5. Detailed Pin Descriptions – GPIO signals (5 dedicated pins, 4 shared pins)
Pin Name
PIN # Type
Pin Description
General Purpose Output 1.
GPO1
24
IOr
After reset, this pin can either be high impedance (TBI or RTBI mode) or an
output that indicates link status, 0=link down, 1=link up.
The function can be changed after reset. See section 6.2.
General Purpose Output 2.
GPO2
25
IOr
After reset, this pin can either be high impedance (TBI or RTBI mode) or an
output that indicates CRS (carrier sense).
The function can be changed after reset. See section 6.2.
9
MAX24287
Pin Name
GPIO1
PIN #
61
Type
IOz
GPIO2
60
IOz
GPIO3
59
IOz
GPIO4/TXD[4]
52
IOz
GPIO5/TXD[5]
53
IOz
GPIO6/TXD[6]
54
IOz
GPIO7/TXD[7]
55
IOz
Pin Description
General Purpose Input or Output 1.
After reset this pin can be either high impedance or generating a 125MHz
clock signal.
GPO1=0 at reset: After reset, GPIO1 is high impedance.
GPO1=1 at reset: After reset, GPIO1 is 125MHz clock out
The function can be changed after reset. See section 6.2.
General Purpose Input or Output 2.
After reset this pin is high impedance. The function can be changed after
reset. See section 6.2.
General Purpose Input or Output 3.
After reset this pin is high impedance. The function can be changed after
reset. See section 6.2.
General Purpose Input or Output 4.
Available for use as a GPIO pin when the parallel interface is configured for
MII, RGMII or RTBI modes.
After reset this pin is high impedance. The function can be changed after
reset. See section 6.2.
General Purpose Input or Output 5.
Available for use as a GPIO pin when the parallel interface is configured for
MII, RGMII or RTBI modes.
After reset this pin is high impedance. The function can be changed after
reset. See section 6.2.
General Purpose Input or Output 6.
Available for use as a GPIO pin when the parallel interface is configured for
MII, RGMII or RTBI modes.
After reset this pin is high impedance. The function can be changed after
reset. See section 6.2.
General Purpose Input or Output 7.
Available for use as a GPIO pin when the parallel interface is configured for
MII, RGMII or RTBI modes.
After reset this pin is high impedance. The function can be changed after
reset. See section 6.2.
10
MAX24287
Table 5-6. Detailed Pin Descriptions – SGMII/1000BASE-X Serial Interface (7 pins)
Pin Name
PIN # Type
Pin Description
TDP,
9
Odiff Transmit Data Output
TDN
8
These pins form a differential CML output for the 1.25Gbaud SGMII transmit
signal to a neighboring 1000BASE-X optical module (SFP, etc.) or PHY with
SGMII interface. See section 6.5.
TCLKP,
6
Odiff Transmit Clock Output
TCLKN
5
These pins form a differential CML output for an optional 625MHz clock for
the SGMII transmit signal on TDP/TDN. This output is disabled at reset but is
enabled by setting CR.TCLK_EN=1. See section 6.5.
Receive Data Input
RDP,
13
Idiff
RDN
14
These pins form a differential input for the 1.25Gbaud SGMII receive signal
from a neighboring 1000BASE-X optical module (SFP, etc.) or PHY with
SGMII interface. A receive clock signal is not necessary because the device
uses a built-in CDR to recover the receive clock from the signal on RDP/RDN.
See section 6.5.
Analog Loss of Signal
ALOS
19
I
This pin receives analog loss-of-signal from a neighboring optical transceiver
module. If the optical module does not have an ALOS output, this pin should
be connected to DVSS for proper operation. See section 6.5.
0 = ALOS not detected or not required, normal operation
1 = ALOS detected, loss of signal
Table 5-7. Detailed Pin Descriptions – Parallel Interface (25 pins)
Pin Name
RXCLK
PIN #
Type
40
IO
Pin Description
Receive Clock
In all modes the frequency tolerance is ± 100 ppm.
GMII Mode: RXCLK is the 125MHz receive clock.
RGMII Modes: RXCLK is the 125MHz (RGMII-1000), 25MHz (RGMII-100) or
2.5MHz (RGMII-10) receive clock (DDR).
TBI Mode: In normal TBI mode (GMIICR.TBI_RATE=1 or RX_DV=1 at
reset), RXCLK is the 62.5MHz receive clock for odd code groups and
TXCLK/RCXCLK1 is the 62.5MHz receive clock for even code groups.
In one-clock TBI mode (GMIICR.TBI_RATE=0 or RX_DV=0 at reset),
RXCLK is the 125MHz receive clock.
RTBI Mode: RXCLK is the 125MHz receive clock (DDR).
MII Mode: RXCLK is the 25MHz (100Mbps MII) or 2.5MHz (10Mbps MII)
receive clock.
In DTE mode (DCE_DTE)=1, RXCLK is an input.
In DCE mode (DCE_DTE)=0, RXCLK is an output.
11
MAX24287
Pin Name
PIN #
Type
RXD[0]
38
IOr
RXD[1]
37
IOr
RXD[2]
36
IOr
RXD[3]
35
IOr
RXD[4]
34
IOr
RXD[5]
33
IOr
RXD[6]
32
IOr
RXD[7]
31
IOr
RX_DV
29
IOr
Pin Description
Receive Data Outputs
During reset these pins are configuration inputs. See section 6.1. After reset
they are driven as outputs.
GMII Mode: receive_data[7:0] is output on RXD[7:0] on the rising edge of
RXCLK.
MII, RGMII-10 and RGMII-100 Modes: receive_data[3:0] is output on
RXD[3:0] on the rising edge of RXCLK. RXD[7:4] are high impedance.
RGMII-1000 Mode: receive_data[3:0] is output on RXD[3:0] on the rising edge
of RXCLK, and receive_data[7:4] is output on the falling edge of RXCLK.
RXD[7:4] are high impedance.
TBI Mode: In normal TBI mode (GMIICR.TBI_RATE=1 or RX_DV=1 at reset),
receive_data[7:0] is output on RXD[7:0], receive_data[8] is output on RX_DV,
and receive_data[9] is output on RX_ER on the rising edge of RXCLK and the
rising edge of RXCLK1 (both 62.5MHz, 180 degrees out of phase).
In one-clock TBI mode (GMIICR.TBI_RATE=0 or RX_DV=0 at reset), these
same signals are output on the rising edge of RXCLK (125MHz).
RTBI Mode: Receive_data[3:0] is output on RXD[3:0] and
Receive_data[4] is output on RX_DV on the rising edge of RXCLK.
Receive_data[8:5] is output on RXD[3:0] and receive_data[9] is output on
RX_DV on the falling edge of RXCLK. RXD[7:4] are high impedance.
Receive Data Valid
During reset this pin is a configuration input. See section 6.1. After reset it is
driven as an output.
MII Mode and GMII Mode: RX_DV is output on the rising edge of RXCLK.
RGMII Modes: The RX_CTL signal is output on RX_DV on both edges of
RXCLK.
TBI Mode: In normal TBI mode (GMIICR.TBI_RATE=1 or RX_DV=1 at reset),
receive_data[8] is output on RX_DV on the rising edge of RXCLK and the
rising edge of RXCLK1 (both 62.5MHz, 180 degrees out of phase).
In one-clock TBI mode (GMIICR.TBI_RATE=0 or RX_DV=0 at reset),
receive_data[8] is output on RX_DV on the rising edge of RXCLK (125MHz).
RX_ER
28
IOr
RTBI Mode: Receive_data[4} is output on RX_DV on the rising edge of
RXCLK. Receive_data[9] is output on RX_DV on the falling edge of RXCLK.
Receive Error
During reset this pin is a configuration input. See section 6.1. After reset it is
driven as an output.
MII Mode and GMII Mode: RX_ER is output on the rising edge of RXCLK.
RGMII Mode and RTBI Mode: RX_ER pin is high impedance.
TBI Mode: In normal TBI mode (GMIICR.TBI_RATE=1 or RX_DV=1 at reset),
receive_data[9] is output on RX_ER on the rising edge of RXCLK and the
rising edge of RXCLK1 (both 62.5MHz, 180 degrees out of phase).
In one-clock TBI mode (GMIICR.TBI_RATE=0 or RX_DV=0 at reset),
receive_data[9] is output on the rising edge of RXCLK (125MHz).
12
MAX24287
Pin Name
COL
PIN #
Type
27
IOr
Pin Description
Collision Detect
During reset this pin is a configuration input. See section 6.1. After reset it is
driven as an output.
MII Mode. GMII Mode and RGMII Modes: COL indicates that a Tx/Rx collision
is occurring. It is meaningful only in half duplex operation. It is asynchronous
to any of the clocks. COL is driven low at all times when BMCR.DLB=1 and
BMCR.COL_TEST=0. When BMCR.DLB=1 and BMCR.COL_TEST=1, COL
behaves as described in the COL_TEST bit description.
1 = Collision is occurring
0 = Collision is not occurring
CRS/COMMA
26
IOr
TBI Mode and RTBI Mode: This pin is high impedance.
Carrier Sense / Comma Detect
During reset this pin is a configuration input. See section 6.1. After reset it is
driven as an output.
MII Mode. GMII Mode and RGMII Modes: CRS is asserted by the device
when either the transmit data path or the receive data path is active. This
signal is asynchronous to any of the clocks.
TXCLK/
RXCLK1
46
IO
TBI Mode and RTBI Mode: COMMA is asserted by the device when a comma
pattern is detected in the receive data stream. In normal TBI mode
(GMIICR.TBI_RATE=1 or RX_DV=1 at reset), COMMA is updated on the
rising edge of RXCLK and the rising edge of RXCLK1 (both 62.5MHz, 180
degrees out of phase). In one-clock TBI mode (GMIICR.TBI_RATE=0 or
RX_DV=0 at reset) and RTBI mode, COMMA is updated on the rising edge of
RXCLK (125MHz).
MII Transmit Clock
When TXCLK is an input, frequency tolerance is ±100ppm.
MII Mode: TXCLK is the 25MHz (100Mbps MII) or 2.5MHz 10Mbps MII)
transmit clock.
In DTE mode (DCE_DTE)=1, TXCLK is an input.
In DCE mode (DCE_DTE)=0, TXCLK is an output.
GMII Mode, RGMII Mode and RTBI Mode: TXCLK can output a 125MHz
clock for use by neighboring components (e.g. a MAC) when
GMIICR.TXCLK_EN=1 (or TXCLK=1 at reset).
TBI Mode: In normal TBI mode (GMIICR.TBI_RATE=1 or RX_DV=1 at
reset), this pin becomes the 62.5MHz RXCLK1 output for even code groups.
In one-clock TBI mode (GMIICR.TBI_RATE=0 or RX_DV=0 at reset), TXCLK
can output a 125MHz clock for use by neighboring components (e.g. a MAC)
when GMIICR.TXCLK_EN=1 (or TXCLK=1 at reset).
13
MAX24287
Pin Name
GTXCLK
PIN #
Type
66
I
Pin Description
GMII/RGMII Transmit Clock
In all modes the frequency tolerance is ± 100ppm.
GMII Mode: GTXCLK is the 125MHz transmit clock.
RGMII Modes: GTXCLK is the 125MHz (RGMII-1000), 25MHz (RGMII-100)
or 2.5MHz (RGMII-10) transmit clock (DDR).
TBI Mode: GTXCLK is the 125MHz transmit clock.
RTBI Mode: GTXCLK is the 125MHz transmit clock (DDR).
TXD[0]
48
I
TXD[1]
49
I
TXD[2]
50
I
TXD[3]
51
I
TXD[4]/GPIO4
52
IOz
TXD[5]/GPIO5
53
IOz
TXD[6]/GPIO6
54
IOz
TXD[7]/GPIO7
55
IOz
MII Mode: This pin is not used and should be pulled low. See the TXCLK pin
description.
Transmit Data Inputs
Depending on the parallel MII interface mode, four or eight of these pins are
used to accept transmit data from a neighboring component.
GMII Mode: The rising edge of GTXCLK latches transmit_data[7:0] from
TXD[7:0].
MII, RGMII-10 and RGMII-100 Modes: The rising edge of TXCLK (MII) or
GTXCLK (RGMII) latches transmit_data[3:0] from TXD[3:0].
TXD[7:4] become GPIO7 – GPIO4.
RGMII-1000 Mode: The rising edge of GTXCLK latches transmit_data[3:0]
from TXD[3:0]. The falling edge of GTXCLK latches transmit_data[7:4] from
TXD[3:0].
TXD[7:4] become GPIO7 – GPIO4.
TBI Mode: The rising edge of GTXCLK latches transmit_data[7:0] from
TXD[7:0], transmit_data[8] from TX_EN and transmit_data[9] from TX_ER.
TX_EN
57
I
RTBI Mode: The rising edge of GTXCLK latches transmit_data[3:0] from
TXD[3:0] and transmit_data[4] from TX_EN. The falling edge of GTXCLK
latches transmit_data[8:5] from TXD[3:0] and transmit data[9] from TX_EN.
TXD[7:4] become GPIO7 – GPIO4.
Transmit Enable
MII Mode and GMII Mode: The rising edge of TXCLK (MII) or GTXCLK (GMII)
latches the TX_EN signal from this pin.
RGMII Modes: Both edges of GTXCLK latch the TX_CTL signal from this pin.
TBI Mode: The rising edge of GTXCLK latches transmit_data[7:0] from
TXD[7:0], transmit_data[8] from TX_EN and transmit_data[9] from TX_ER.
RTBI Mode: The rising edge of GTXCLK latches transmit_data[3:0] from
TXD[3:0] and transmit_data[4] from TX_EN. The falling edge of GTXCLK
latches transmit_data[8:5] from TXD[3:0] and transmit data[9] from TX_EN.
14
MAX24287
Pin Name
TX_ER
PIN #
Type
58
I
Pin Description
Transmit Error
MII Mode and GMII Mode: The rising edge of TXCLK (MII) or GTXCLK (GMII)
latches the TX_ER signal from this pin.
RGMII Modes: This pin is not used.
TBI Mode: The rising edge of GTXCLK latches transmit_data[7:0] from
TXD[7:0], transmit_data[8] from TX_EN and transmit_data[9] from TX_ER.
RTBI Mode: This pin is not used.
15
MAX24287
Table 5-8. Detailed Pin Descriptions – Power and Ground Pins (17 pins)
Pin Name
PIN #
Pin Description
DVDD12
30, 56
Digital Power Supply, 1.2V (2 pins)
DVDD33
20, 39, 65 Digital Power Supply, 3.3V
DVSS
47
Return for DVDD12 and DVDD33
RVDD12
16
1.25G Receiver Analog Power Supply, 1.2V
RVDD33
12
1.25G Receiver Analog Power Supply, 3.3V
RVSS
15
Return for RVDD12 and RVDD33
TVDD12
11
1.25G Transmitter Analog Power Supply, 1.2V
TVDD33
7
1.25G Transmitter Analog Power Supply, 3.3V
TVSS
10
Return for TVDD12 and TVDD33
CVDD12
3
TX PLL Analog Power Supply, 1.2V
CVDD33
2
TX PLL Analog Power Supply, 3.3V
CVSS
4
Return for CVDD12 and CVDD33
GVDD12
18
Analog Power Supply, 1.2V
GVSS
1
Return for GVDD12.
Exposed pad (die paddle). Connect to ground plane. EP also functions as a
Exposed Pad
EP
heatsink. Solder to the circuit-board ground plane to maximize thermal
dissipation.
16
MAX24287
6. Functional Description
6.1
Pin Configuration During Reset
The MAX24287 initial configuration is determined by pins that are sampled at reset. The values on these pins are
used to set the reset values of several register bits. Note that the behavior described in this section cannot be used
for “hardware-only” operation. Some register accesses through the MDIO interface are required for proper
operation as described in section 6.14.
The pins that are sampled at reset to pin-configure the device are listed described in Table 6-1. During reset these
pins are high-impedance inputs and require 10k pullup or pulldown resistors to set pin-configuration values. After
reset, the pins can become outputs if configured to do so and operate as configured. There are two pin
configuration modes: 15-pin mode and 3-pin mode.
In 15-pin mode (COL=0 during reset, see Table 6-1) all major settings associated with the PCS block are
configurable. In addition, the input reference clock frequency on the REFCLK pin is configured during reset using
the RXD[3:2] pins.
Table 6-1. Reset Configuration Pins, 15-Pin Mode (COL=0)
Pin
CRS
Function
Double Date Rate
Register Bit Affected
GMIICR:DDR=CRS
10/100 MII: DTE or DCE
10/100 MII: GMIICR:DTE_DCE
Other: Serial Interface
Other: PCSCR:BASEX
GPO1
GPIO1 Configuration
GPIOCR1.GPIO1_SEL[2]
RXD[1:0]
Parallel Interface Speed
GMIICR:SPD[1:0]
RXD[3:2]
REFCLK Frequency
None
RXD[7:4]
RX_ER
MDIO PHYAD[3:0].
MDIO PHYAD[4].
Internal MDIO PHYAD register
(device address on MDIO bus).
TBI Mode
GMIICR:TBI_RATE
Other: Auto-negotiation
BMCR:AN_EN
TXCLK Enable
GMIICR:TXCLK_EN
GPO2
RX_DV
TXCLK
Table 6-2. Parallel Interface Configuration
SPD[1] SPD[0]
Speed
DDR=0
0
0
10Mbps
MII
0
1
100Mbps
MII
1
0
1000Mbps
GMII
1
1
1000Mbps
TBI
Notes
See Table 6-2.
0=DCE, 1=DTE
(serial interface is configured for
SGMII mode, PCSCR:BASEX=0)
0=SGMII, 1=1000BASE=X
0=high impedance
1=125MHz from TX PLL
See Table 6-2.
00=10MHz, 01=12.8MHz,
10=25MHz, 11=125MHz
Note: PHYAD[4:0]=11111 enables
factory test mode. Do not use.
0=one-clock mode (125MHz)
1=normal mode (62.5MHz x 2)
0=Disable, 1=Enable
0=high impedance
1=125MHz from TX PLL
Ignored in MII mode and TBI with
two 62.5MHz Rx clocks
DDR=1
RGMII-10
RGMII-100
RGMII-1000
RTBI
In 3-pin mode (COL=1 during reset, see Table 6-3) the device is configured for a 1000Mbps RGMII or GMII parallel
interface. This mode is targeted to the application of connecting an ASIC, FPGA or processor with an RGMII or
GMII interface to a switch device with an SGMII interface or to a 1000BASE-X optical interface. In 3-pin mode, the
REFCLK pin is configured for 25MHz, the PHY address is set to 0x04, 1000BASE-X auto-negotiation (or automatic
transmission of SGMII control information) is enabled, TXCLK is configured to output a 125MHz clock, and the
17
MAX24287
TCLKP/TCLKN differential pair is disabled. Note: if RX_ER and RXD[7:4] are all high when the device exits reset
then the device enters factory test mode; for normal operation set these pins to any other combination of values.
Table 6-3. Reset Configuration Pins, 3-Pin Mode (COL=1)
Pin
CRS
GPO2
Function
Double Date Rate
Serial Interface
Register Bit Affected
GMIICR:DDR=CRS
PCSCR:BASEX
Notes
0=GMII, 1=RGMII
0=SGMII, 1=1000BASE=X
Note: In 3-pin mode register fields are automatically set as follows: REFCLK clock rate to 25MHz, GMIICR:SPD[1:0]=10, MDIO PHYAD is set to
0x04, BMCR:AN_EN=1, GMIICR:TXCLK_EN=1, GPIOCR1=0 and GPIOCR2=0. All other registers are reset to normal defaults listed in the
register descriptions.
6.2
General-Purpose I/O
The MAX24287 has two general-purpose output pins, GPO1, GPO2, and seven general-purpose input/output pins,
GPIO1 through GPIO7. Each pin can be configured to drive low or high or be in a high-impedance state. Other
uses for the GPO and GPIO pins are listed in Table 6-4 through Table 6-6. The GPO and GPIO pins are each
configured using a GPxx_SEL field in registers GPIOCR1 or GPIOCR2 with values as indicated in the tables
below.
When a GPIO pin is configured as high impedance it can be used as an input. The real-time state of GPIOx can be
read from GPIOSR.GPIOx. In addition, a latched status bit GPIOSR.GPIOxL is available for each GPIO pin. This
latched status bit is set when the transition specified by GPIOCR2.GPIO13_LSC (for GPIO1 through GPIO3) or by
GPIOCR2.GPIO47_LSC (for GPIO4 through GPIO7) occurs on the pin.
Note that GPIO4 through GPIO7 are alternate pin functions to TXD[7:4] and therefore are only available when the
parallel MII is configured for MII, RGMII or RTBI.
Table 6-4. GPO1, GPIO1 and GPIO3 Configuration Options
GPxx_SEL
Description
000
High impedance, not driven, can be an used as an input
001
Drive logic 0
010
Drive logic 1
011
Interrupt output, active low. GPO1 drives low and high, GPIO1 and GPIO3 are open-drain.
100
Output 125MHz from the TX PLL
101
Output 25MHz or 125MHz from receive clock recovery PLL. Not squelched. Frequency specified
by CR.RCFREQ.
110
Output real-time link status, 0=link down, 1=link up
111
reserved value, do not use
Table 6-5. GPO2 and GPIO2 Configuration Options
GPxx_SEL
Description
000
High impedance, not driven, can be an used as an input
001
Drive logic 0
010
Drive logic 1
011
reserved value, do not use
100
Output 125MHz from TX PLL
101
Output 25MHz or 125MHz from receive clock recovery PLL. The frequency is specified by
CR.RCFREQ. Signal is automatically squelched (driven low) when CR.RCSQL=1 and any of
several conditions occur. See section 6.2.1.
110
Output CRS (carrier sense) status
111
reserved value, do not use
18
MAX24287
Table 6-6. GPIO4, GPIO5, GPIO6 and GPIO7 Configuration Options
GPxx_SEL
Description
000
High impedance, not driven, can be an used as an input
001
Drive logic 0
010
Drive logic 1
011
reserved value, do not use
100
Output 125MHz from TX PLL
101
Output 25MHz or 125MHz from receive clock recovery PLL. The frequency is specified by
CR.RCFREQ. Signal is automatically squelched (driven low) when CR.RCSQL=1 and any of
several conditions occur. See section 6.2.1.
110
reserved value, do not use
111
reserved value, do not use
6.2.1 Receive Recovered Clock Squelch Criteria
A 25MHz or 125MHz clock from the receive clock recovery PLL can be output on any of GPO2, GPIO2 and
GPIO4-7. When CR.RCSQL=1, this clock is squelched (driven low) when any of the following conditions occur:
IR.ALOS=1 (analog loss-of-signal occurred)
IR.RLOS=1 (CDR loss-of-signal occurred))
IR.RLOL=1 (CDR PLL loss-of-lock occurred)
IR.LINK_ST=0 (auto-negotiation link down occurred, latched low)
Since each of these criteria is a latched status bit, the output clock signal remains squelched until all of these
latched status bits go inactive (as described in section 7.2).
6.3
Reset and Processor Interrupt
6.3.1 Reset
The following reset functions are available in the device:
1. Hardware reset pin (RST_N): This pin asynchronously resets all logic, state machines and registers in the
device except the JTAG logic. When the RST_N pin is low, all internal registers are reset to their default
values. Pin states are sampled and used to set the default values of several register fields as described in
section 6.1. RST_N should be asserted for at least 100s.
2. Global reset bit, GPIOCR1.RST: Setting this bit is equivalent to asserting the RST_N pin. This bit is selfclearing.
3. Datapath reset bit, BMCR.DP_RST. This bit resets the entire datapath from parallel MII interface through PCS
encoder and decoder. It also resets the deserializer. It does not reset any registers, GPIO logic, or the TX PLL.
The DP_RST bit is self-clearing.
4. JTAG reset pin JTRST_N. This pin resets the JTAG logic. See section 7.2.18 for details about JTAG operation.
6.3.2 Processor Interrupts
Any of pins GPO1, GPIO1 and GPIO3 can be configured as an active low interrupt output by setting the
appropriate field in GPIOCR1 to 011. GPO1 drives high and low while GPIO1 and GPIO3 are open-drain and
require pullup resistors.
Status bits than can cause an interrupt are located in the IR register. The corresponding interrupt enable bits are
also located in the IR register. The PAGESEL register has a top-level IR status bit to indicate the presence of
19
MAX24287
active interrupt sources. The PAGESEL register is available on all pages through the MDIO interface, allowing the
interrupt routine to read the register without changing the MDIO page.
6.4
MDIO Interface
6.4.1 MDIO Overview
The MAX24287's MDIO interface is compliant to IEEE 802.3 clause 22. MAX24287 always behaves as a PHY on
the MDIO bus. Because MAX24287 is not a complete PHY but rather a device that sits between a MAC and a
PHY, it implements only a subset of the registers and register fields specified in 802.3 clause 22 as shown in the
table below.
MDIO
Address
0
1
2, 3
4
5
6
15
802.3 Name
Control
Status
PHY Identifier
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Base Page Ability
Auto-Negotiation Expansion
Extended Status
MAX24287
Name
BMCR
BMSR
ID1, ID2
AN_ADV
AN_RX
AN_EXP
EXT_STAT
The MDIO consists of a bidirectional, half-duplex serial data signal (MDIO) and a ≤12.5MHz clock signal (MDC)
driven by a bus master, usually a MAC. The format of management frames transmitted over the MDIO interface is
shown below (see IEEE 802.3 clause 22.2.4.5 for more information). MDIO DC electrical characteristics are listed
in section 9.2.1. AC electrical characteristics are listed in section 9.3.6. The MAX24287's MDIO slave state
machine is shown in Figure 6-1.
READ Command
WRITE Command
PRE
32 ‘1’s
32 ‘1’s
ST
01
01
Management Frame Fields
OP PHYAD REGAD TA
10 AAAAA RRRRR Z0
01 AAAAA RRRRR 10
DATA
16-bit
16-bit
IDLE
Z
Z
The transmission and reception bit order is MSB first for the PHYAD, REGAD and DATA fields
MAX24287 supports preamble suppression. This allows quicker bursts of read and write transfers to occur by
shortening the minimum transfer cycle time from 65 clock periods to 33 clock periods. There must be at least a
32-bit preamble on the first transfer after reset, but on subsequent transfers the preamble can be suppressed or
shortened. When the preamble is completely suppressed the 0 in the ST symbol follows the single IDLE Z, which is
one clock period duration.
Like any MDIO slave, MAX24287 only performs the read or write operation specified if the PHYAD bits of the MDIO
command match the device PHY address. The device PHY address is latched during device reset from the
RXD[7:4] and RX_ER pins. See section 6.1.
The MAX24287 does not support the 802.3 clause 45 MDIO extensions. Management frames with ST bits other
than 01 or OP bits other than 01 or 10 are ignored and put the device in a state where it ignores the MDIO traffic
until it sees a full preamble (32 ones). If Clause 45 ICs and the MAX24287 are connected to the same MDIO
management interface, the station management entity must put a full preamble on the bus after communicating
with clause 45 ICs before communicating with the MAX24287.
20
MAX24287
Figure 6-1. MDIO Slave State Machine
HW RESET
PREAMBLE
INIT
MDIO=Z
32 consecutive 1s
PREAMBLE
/ IDLE
MDIO=Z
0
0
1
ST 2nd bit
MDIO=Z
1
00 or 11
OP 2 bits
MDIO=Z
24 clocks
01 or 10
PHYAD 5 bits
MDIO=Z
No match
match
REGAD 5 bits
MDIO=Z
OP=10 (read)
NOT PHY
MDIO=Z
19 clocks
No match
NOT REG
MDIO=Z
OP=01 (write)
TA-Z
MDIO=Z
TA 2 bits
MDIO=Z
TA-0
MDIO=0
DATA 16 bits
MDIO=Z
16 clocks
DATA 16 bits
MDIO=D[15:0]
16 clocks
IDLE
MDIO=Z
21
MAX24287
6.4.2 Examples of MAX24287 and PHY Management Using MDIO
The MDIO interface is typically provided by the MAC function within a neighboring processor, ASIC or FPGA
component. It can be used to configure the registers in the MAX24287 and/or the registers in a PHY or switch chip
connected to the MAX24287 via the SGMII interface.
Case 1 in Figure 6-2 shows a typical application where the MAX24287 connects a MAC with a 3-speed RGMII
interface to a 3-speed PHY with an SGMII interface. Through the MDIO interface, system software configures the
MAX24287 and optionally the PHY. (The PHY may not need to be configured if it is operating in a hardware-only
auto-negotiation 1000BASE-T mode). After initial configuration and after the PHY auto-negotiates link details with
its 1000BASE-T link partner, the speed and mode are transferred to the MAX24287 over the SGMII interface as
specified in the SGMII specification and are available in the MAX24287 AN_RX register. The processor reads this
information and configures the MAC and the MAX24287 to match the mode the PHY is in.
Figure 6-2. Management Information Flow Options, Case 1,Tri-Mode PHY
Transfer Speed Control
Acknowledge Speed Control
RGMII
MAC
(RGMII)
RXD[3:0]
RX_CLK
2.5/25/125MHz
TXD[3:0]
SGMII
CDR
MAX24287
GTX_CLK
2.5/25/125MHz
RD
TD
TCLK
625MHz
10BASE-T
100BASE-T
1000BASE-T
PHY
MDIO
Case 2 in Figure 6-3 shows a typical application where the MAX24287 connects a MAC with a GMII interface to an
SGMII switch chip. Through the MDIO interface, system software configures the MAX24287 to match the MAC
mode and writes the MAX24287's AN_ADV register to also match the MAC mode. The MAX24287 then transfers
the speed and mode over the SGMII interface as specified in the SGMII specification. The switch chip receives this
information and configures its port to match.
Figure 6-3. Management Information Flow Options, Case 2, SGMII Switch Chip
Transfer Speed Control
Acknowledge Speed Control
GMII
RXD[7:0]
RX_CLK
125MHz
MAC
(GMII)
TXD[7:0]
SGMII
CDR
MAX24287
RD
TD
Switch
Chip
GTX_CLK
125MHz
MDIO
Case 3 in Figure 6-4 shows a typical application where the MAX24287 connects a MAC with a GMII interface to an
optical interface. In this case the MAX24287 provides the 1000BASE-X PCS and PMA functions for the optical
interface. Through the MDIO interface, system software configures the MAX24287 to match the MAC mode, both
of which need to be 1000 Mbps speed. The MAX24287 then auto-negotiates with its link partner. This 1000BASEX auto-negotiation is primarily to establish the pause functionality of the link. The MAX24287's auto-negotiation
support is described in section 6.7.
22
MAX24287
Figure 6-4. Management Information Flow Options, Case 3, 1000BASE-X Interface
1000BASE-X Auto-negotiation
GMII
RXD[7:0]
RX_CLK
125MHz
MAC
(GMII)
1000BASE-X
CDR
TXD[7:0]
GTX_CLK
125MHz
MAX24287
RD
TD
Optical
Interface
(e.g. SFP Module)
MDIO
23
MAX24287
6.5
Serial Interface – 1000BASE-X or SGMII
The high-speed serial interface is compatible with the specification of the 1000BASE-CX PMD service interface
TP1 as defined in 802.3 clause 39. It is also compatible with the specification of the SGMII interface and can
connect to optical PMD modules in 1000BASE-SX/LX interfaces.
On this interface the MAX24287 transmits a 1250Mbaud differential signal on the TDP/TDN output pins. DDR
clocking is used, and the transmit interface outputs a 625MHz differential clock signal on the TCLKP/TCLKN output
pins. In the receive direction the clock and data recovery (CDR) block recovers both clock and data from the
incoming 1250Mbaud signal on RDP/RDN. A separate receive clock signal is not needed.
Signal Format, Coupling, Termination. The serial interface passes data at 1.25 Gbaud using a CML differential
output and an any-format differential input. The CML TDP/TDN outputs have internal 50 pullup resistors to
TVDD33. The differential input RDP/RDN does not have internal termination, and an external 100 termination
resistor between RDP and RDN is recommended. The high-speed serial interface pins are typically connected with
neighboring components using AC coupling as shown in Figure 6-5.
Figure 6-5. Recommended External Components for High-Speed Serial Interface
50
100
Signal
Source
10k
50
Signal
Destination
MAX24287
+
50
Receiver
100
-
40k
50
40k
CML
Driver
RVDD33
10k
50
50
MAX24287 TVDD33
16mA
Receive Loss-of-Signal. The device's receiver logic has an ALOS input pin through which analog loss-of-signal
(ALOS) can be received from a neighboring optical transceiver module, if the high-speed serial signal is
transmitted/received optically. The IR.ALOS bit is set when the ALOS pin goes high. ALOS can cause an interrupt
if enabled by IR.ALOS_IE.
In addition, the clock-and-data recovery block (CDR) indicates loss-of-signal when it does not detect any transitions
in 24 bit times. The IR.RLOS latched status bit is set when the CDR indicates loss-of-signal. RLOS can cause an
interrupt if enabled by IR.RLOS_IE.
Receive Loss-of-Lock. The receive clock PLL in the CDR locks to the recovered clock from the RDP/RDN pins
and produces several receive-side clock signals. If the receive clock PLL loses lock, it sets IR.RLOL, which can
cause an interrupt if enabled by IR.RLOL_IE.
Transmit Clock. The TCLKP/TCLKN differential output can be enabled and disabled using CR.TCLK_EN.
Disabled means the output drivers for TCLKP and TCLKN are disabled (high impedance) and the internal 50
termination resistors pull both TCLKP and TCLKN up to 3.3V.
DC Electrical Characteristics. See section 9.2.2.
AC Electrical Characteristics. See section 9.3.3.
24
MAX24287
6.6
Parallel Interface – GMII, RGMII, TBI, RTBI, MII
The parallel interface can be configured as GMII, MII or TBI compliant to IEEE 802.3 clauses 35, 22 and 36,
respectively. It can also be configured as reduced pin count RGMII or RTBI compliant to the HP document RGMII
Version 1.3 12/10/2000. A summary of the parallel interface modes is show in Table 6-7 below.
Table 6-7. Parallel Interface Modes
Mode
TBI, normal
TBI, 1 Rx clock
RTBI
GMII
RGMII-1000
RGMII-100
RGMII-10
MII-100 DCE
MII-10 DCE
MII-100 DTE
MII-10 DTE
Baud Rate,
Mbps
1250
1250
1250
1000
1000
100
10
100
10
100
10
Data Transfer Per Cycle,
# of Wires Per Direction
10-bit codes, 10 wires
10-bit codes, 10 wires
10-bit codes, 5 wires, DDR
8-bit data, 8 wires
8-bit data, 4 wires, DDR
4-bit data, 4 wires
4-bit data, 4 wires
4-bit data, 4 wires
4-bit data, 4 wires
4-bit data, 4 wires
4-bit data, 4 wires
Transmit Clock
Input, 125MHz
Input, 125MHz
Input, 125MHz
Input, 125MHz
Input, 125MHz
Input, 25MHz
Input, 2.5MHz
Output, 25MHz
Output, 2.5MHz
Input, 25MHz
Input ,2.5MHz
Receive Clock
Output, 2 62.5MHz
Output, 1 125MHz
Output, 125MHz
Output, 125MHz
Output, 125MHz
Output 25MHz
Output, 2.5MHz
Output, 25MHz
Output, 2.5MHz
Input, 25MHz
Input, 2.5MHz
Full
Duplex
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Half
Duplex
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
The parallel interface mode is controlled by GMIICR.SPD[1:0]. TBI and MII options are specified by
GMIICR.TBI_RATE and GMIICR.DTE_DCE, respectively.
6.6.1 GMII Mode
The MAX24287's GMII interface is compliant to IEEE 802.3 clause 35 but only operates full duplex. Half duplex
operation is not supported, and the TX_ER pin is ignored. The PHY therefore does not receive the following from
the MAC: carrier extend, carrier extend error, and transmit error propagation as described in 802.3 section
35.2.1.6, section 35.2.2.5 and Table 35-1. These features are not needed for full duplex operation.
The parallel interface can be configured for GMII mode using software configuration or pin configuration at reset.
For pin configuration (see section 6.1) one of the following combinations of pin states must be present during
device reset:
COL=0, RXD[1:0]=10, CRS=0
COL=1, CRS=0
For software configuration, the following register fields must be set: GMIICR.SPD[1:0]=10 and GMIICR.DDR=0.
See IEEE 802.3 clause 35 for functional timing diagrams. GMII DC electrical characteristics are listed in section
9.2.1. AC electrical characteristics are listed in section 9.3.4 and 9.3.5.
Table 6-8. GMII Parallel Bus Pin Naming
Pin Name
802.3 Pin Name
Function
RXCLK
RX_CLK
Receive 125MHz clock output
RXD[7:0]
RXD[7:0]
Receive data output
RX_DV
RX_DV
Receive data valid output
RX_ER
RX_ER
Receive data error output
CRS
CRS
Receive carrier sense
COL
COL
Receive collision (held low in GMII mode)
TXCLK
--Outputs 125MHz from the TX PLL for MAC when GMIICR.TXCLK_EN=1.
GTXCLK
GTX_CLK
Transmit 125MHz clock input
TXD[7:0]
TXD[7:0]
Transmit data input
TX_EN
TX_EN
Transmit data enable input
TX_ER
TX_ER
Transmit data error input (not used - ignored)
25
MAX24287
6.6.2 TBI Mode
6.6.2.1 Configuration
The TBI and RTBI interfaces are used when a neighboring component implements the 802.3 PCS layer and
therefore transmits and receives 10-bit 8B/10B-encoded data. The parallel interface can be configured for TBI
mode using software configuration or pin configuration at reset. For pin configuration (see section 6.1) device pins
must be set as follows during device reset: COL=0, RXD[1:0]=11, CRS=0. For software configuration, the following
register fields must be set: GMIICR.SPD[1:0]=11 and GMIICR.DDR=0. When the parallel interface is in TBI mode,
the MAX24287 does not perform 8B/10B encoding or decoding or any auto-negotiation functions.
6.6.2.2 Normal TBI with Two 62.5MHz Receive Clocks
The normal TBI interface specified in IEEE 802.3 section 36.3.3 has a 10-bit data bus in each direction, a 125MHz
transmit clock (GTXCLK), two 62.5MHz receive clocks (RXCLK and RXCLK1) and a receive COMMA signal. See
Table 6-9. In the transmit path the MAX24287 samples tx_code_group[9:0] on rising edges of GTXCLK. In the
receive path, RXCLK and RXCLK1 are 180 degrees out of phase from each other (i.e. inverted) and together
provide rising edges every 8 ns. The MAX24287 updates the rx_code_group[9:0] and COMMA signals before
every RXCLK rising edge and every RXCLK1 rising edge. The neighboring component then samples
rx_code_group[9:0] and COMMA every RXCLK rising edge and every RXCLK1 rising edge. The normal TBI
interface is selected with pin configuration by setting RX_DV=1 during device reset or in software by setting
GMIICR:TBI_RATE=1. See IEEE 802.3 section 36.3.3 for functional timing diagrams. TBI DC electrical
characteristics are listed in section 9.2.1. AC electrical characteristics are listed in section 9.3.4 and 9.3.5.
Table 6-9. TBI Parallel Bus Pin Naming (Normal Mode}
Pin Name
802.3 Pin Name
Function
RXCLK
PMA_RX_CLK0
Receive 62.5MHz clock output phase 0, odd numbered code-groups
RXD[7:0]
rx_code_group[7:0] Receive data bits 7 to 0 output
RX_DV
rx_code_group[8]
Receive data bit 8 output
RX_ER
rx_code_group[9]
Receive data bit 9 output
CRS
COM_DET
Comma detection output
COL
--Not used
TXCLK/RXCLK1 PMA_RX_CLK1
Receive 62.5MHz clock output phase 1, even numbered code-groups
GTXCLK
PMA_TX_CLK
Transmit 125MHz clock input
TXD[7:0]
tx_code_group[7:0] Transmit data bits 7 to 0 input
TX_EN
tx_code_group[8]
Transmit data bit 8 input
TX_ER
tx_code_group[9]
Transmit data bit 9 input
6.6.2.3 One-Clock TBI Mode
An alternate TBI receive clocking scheme is also available in which the two 62.5MHz receive clocks are replaced
by a single 125MHz receive clock on the RXCLK pin. See Table 6-10. In this mode a neighboring component uses
rising edges of the RXCLK signal to sample rx_code_group[9:0]. The alternate TBI receive clocking scheme is
selected with pin configuration by setting RX_DV=0 during device reset or in software by setting
GMIICR:TBI_RATE=0.
Table 6-10. TBI Parallel Bus Pin Naming (One-Clock Mode)
Pin Name
802.3 Pin Name
Function
RXCLK
--Receive 125MHz clock output
RXD[7:0]
rx_code_group[7:0] Receive data bits 7 to 0 output
RX_DV
rx_code_group[8]
Receive data bit 8 output
RX_ER
rx_code_group[9]
Receive data bit 9 output
CRS
COM_DET
Comma detection output
COL
--Not used
TXCLK
--Outputs 125MHz from the TX PLL for use by the MAC when
GMIICR.TXCLK_EN=1.
26
MAX24287
Pin Name
GTXCLK
TXD[7:0]
TX_EN
TX_ER
802.3 Pin Name
PMA_TX_CLK
tx_code_group[7:0]
tx_code_group[8]
tx_code_group[9]
Function
Transmit 125MHz clock input
Transmit data bits 7 to 0 input
Transmit data bit 8 input
Transmit data bit 9 input
6.6.2.4 Frequency-Locked Through Clocking, No Buffers
The REFCLK signal is internally multiplied to produce the 1250MHz clock used to transmit data on the serial
interface TDP/TDN pins. This 1250MHz clock is also used to create the 625MHz clock on the serial interface
TCLKP/TCLKN pins. The REFCLK signal must therefore be ±100ppm and low jitter (
