Short Form Data Sheet
April 2012
MAX24305, MAX24310
5- or 10-Output Any-Rate Timing ICs
with Internal EEPROM
General Description
The MAX24305 and MAX24310 are flexible, highperformance timing and clock synthesizer ICs that
include a DPLL and two independent APLLs. When
locked to one of two input clock signals, the device
performs any-to-any frequency conversion. From any
input clock frequency 1Hz to 750MHz the device can
produce frequency-locked APLL output frequencies up
to 750MHz and as many as 10 output clock signals that
are integer divisors of the APLL frequencies. Input jitter
can be attenuated by an internal low-bandwidth DPLL.
The DPLL also provides truly hitless switching between
input clocks and a high-resolution holdover capability.
Input switching can be manual or automatic. Using only
a low-cost crystal or oscillator, the device can also serve
as a frequency synthesizer IC. Output jitter is less than
1ps RMS (12kHz to 20MHz) on all outputs and can be
as low as 0.24ps RMS.
For telecom systems, the device has all required
features and functions to serve as a central timing
function or as a line card timing IC. With a suitable
oscillator the device meets the requirements of Stratum
2, 3E, 3, 4E, and 4; G.812 Types I to IV; G.813; and
G.8262.
Features
♦
♦
♦
Applications
Frequency Conversion and Synthesis Applications in a
Wide Variety of Equipment Types
Telecom Timing Cards or Line Cards for SONET/SDH,
Synchronous Ethernet and/or OTN
Ordering Information
PART
OUTPUTS
TEMP
RANGE
PINPACKAGE
MAX24305EXG+
5
-40 to +85
81-CSBGA
MAX24310EXG+
10
-40 to +85
81-CSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
♦
Input Clocks
♦
One Crystal Input
♦
Two Differential or CMOS/TTL Inputs
♦
Differential to 750MHz, CMOS/TTL to 125MHz
♦
Continuous Input Clock Quality Monitoring
♦
Automatic or Manual Clock Selection
♦
Hitless Reference Switching on Loss of Input
Low-Bandwidth DPLL
♦
Programmable Bandwidth, 0.5mHz to 400Hz
♦
Attenuates Jitter up to Several UI
♦
Free-Run or Holdover on Loss of All Inputs
♦
Hitless Reference Switching on Loss of Input
♦
Manual Phase Adjustment
Two APLLs Plus 5 or 10 Output Clocks
♦
APLLs Perform High Resolution Fractional-N
Clock Multiplication
♦
Any Output Frequency from
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