MAX24710EXG2

Short Form Dat a Sheet February 2013 MAX24705, MAX24710 5- or 10-Output Any-Rate Line Card Timing ICs with Internal EEPROM General Description The MAX24705 and MAX24710 are flexible, highperformance timing and clock synthesizer ICs that include a DPLL and two independent APLLs. When locked to one of two input clock signals, the device performs any-to-any frequency conversion. From any input clock frequency 1Hz to 750MHz the device can produce frequency-locked APLL output frequencies up to 750MHz and as many as 10 output clock signals that are integer divisors of the APLL frequencies. Input jitter can be attenuated by an internal low-bandwidth DPLL. The DPLL also provides truly hitless switching between input clocks and a high-resolution holdover capability. Input switching can be manual or automatic. Using only a low-cost crystal or oscillator, the device can also serve as a frequency synthesizer IC. Output jitter is typically 0.18 to 0.3ps RMS for an APLL-only integer multiply and 0.25 to 0.4ps RMS for APLL-only fractional multiply or DPLL+APLL operation. For telecom systems, the device has all required features and functions to serve as a line card timing IC. Features ♦ ♦ ♦ Applications Input Clocks ♦ One Crystal Input ♦ Two Differential or CMOS/TTL Inputs ♦ Differential to 750MHz, C MOS/TTL to 160MH z ♦ Continuous Input Clock Quality Monitoring ♦ Automatic or Manual Clock Selection ♦ Hitless Reference Switching on Loss of Input Low-Bandwidth DPLL ♦ Programmable Bandwidth, 4Hz to 400Hz ♦ Attenuates Jitter up to Several UI ♦ Free-Run or Holdover on Loss of All Inputs ♦ Hitless Reference Switching on Loss of Input ♦ Manual Phase Adjustment Two APLLs Plus 5 or 10 Output Clocks ♦ APLLs Perform High Resolution Fractional-N Clock Multiplication ♦ An y Output Frequency from