MAX3610AU/D

19-3286; Rev 0; 5/04 EVALUATION KIT AVAILABLE Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator The MAX3610 is a low-jitter, high-performance, dual-rate clock generator optimized for 1Gbps/2Gbps/4Gbps Fibre-Channel applications. When connected with an external AT-cut crystal, the device generates a precision clock output by integrating a crystal oscillator with Maxim’s low-noise phase-locked loop (PLL) providing a low-cost solution. By coupling Maxim’s low-noise PLL design featuring a low-jitter generation VCO with an inexpensive fundamental mode crystal, the MAX3610 provides the optimum combination of low cost, flexibility, and high performance. The MAX3610 output frequency is selectable. When using a 26.5625MHz crystal, the output clock rate can be set to either 106.25MHz or 212.5MHz. When operating at 106.25MHz, the typical phase jitter is 0.7psRMS from 12kHz to 20MHz. The MAX3610A has low-voltage positive-emitter-coupled logic (LVPECL) clock output drivers. The MAX3610B has low-voltage differential-signal (LVDS) clock output drivers. The MAX3610 output drivers can also be disabled. The MAX3610 operates from a single +3.3V supply. The PECL version typically consumes 165mW, while the LVDS version typically consumes 174mW. Both devices are available in die form and have a 0°C to +85°C operating temperature range. Applications Features ♦ Clock Output Frequencies: 106.25MHz or 212.5MHz ♦ Phase Jitter: 0.7psRMS ♦ LVPECL or LVDS Output ♦ Excellent Power-Supply Noise Rejection ♦ Supply Current: 50mA at +3.3V Supply (LVPECL) 53mA at +3.3V Supply (LVDS) ♦ 0°C to +85°C Temperature Range ♦ Optional Output Disable Ordering Information PINPACKAGE PART TEMP RANGE OUTPUTS MAX3610AU/D MAX3610BU/D 0°C to +85°C Die LVPECL 0°C to +85°C Die LVDS Dice are designed to operate from 0°C to +85°C, but are tested and guaranteed only at TA = +25°C. Fibre-Channel Hard Disk Drives Host Bus Adapters Raid Controllers Fibre-Channel Switches Typical Operating Circuits +3.3V +3.3V 0.1µF 0.1µF OE VCC FREQSET OE +3.3V AT CUT CRYSTAL AT CUT CRYSTAL X1 MAX3610A X1 OUT+ VCC FREQSET MAX3610B OUT+ DEVICE WITH LVPECL INPUTS GND 100Ω 50Ω 50Ω DEVICE WITH LVDS INPUTS OUT- X2 OUT- X2 +3.3V GND OPERATING AT 106.25MHz LVPECL OUTPUTS VCC -2V OPERATING AT 106.25MHz LVDS OUTPUTS 1 MAX3610 General Description MAX3610 Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator ABSOLUTE MAXIMUM RATINGS Supply Voltage ......................................................-0.5V to +5.0V Voltage at FREQSET, OE............................-0.5V to (VCC + 0.5V) Voltage at X1 .........................................................-0.5V to +0.8V Voltage at X2 .....................................................................0 to 2V PECL Output Current ..........................................................56mA LVDS Output Voltage .................................-0.5V to (VCC + 0.5V) Operating Temperature Range...............................0°C to +85°C Storage Temperature Range .............................-65°C to +160°C Processing Temperature..................................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1 ) PARAMETER SYMBOL Supply Current ICC CONDITIONS (Note 2) TYP MAX LVPECL MIN 50 65 LVDS 53 67 UNITS mA LVPECL OUTPUT SPECIFICATIONS (Note 3) Output High Voltage VOH 0°C to +85°C VCC 1.025 VCC 0.88 V Output Low Voltage VOL 0°C to +85°C VCC 1.81 VCC 1.62 V 1.475 V 400 mV 25 mV 1.275 V 25 mV 140 Ω 12 mA 0.8 V LVDS OUTPUT SPECIFICATIONS (Figure 1) LVDS Output High Voltage LVDS Output Low Voltage LVDS Differential Output Voltage LVDS Change in Magnitude of Differential Output for Complementary States LVDS Offset Output Voltage (Output Common-Mode Voltage) LVDS Change in Magnitude of Output Offset Voltage for Complementary States VOH VOL 0.925 |VOD| 250 V ∆|VOD| 1.125 VOS ∆|VOS| LVDS Differential Output Impedance 80 LVDS Output Current 100 Outputs shorted together CONTROL INPUT SPECIFICATIONS (FREQSET, OE) TTL Control Input-Voltage High VIH TTL Control Input-Voltage Low VIL 2 V Input Current (Input High) IIH -10 +10 µA Input Current (Input Low) IIL -50 +10 µA CLOCK OUTPUT SPECIFICATIONS Clock Output Frequency Crystal Oscillation Circuit Input Capacitance 2 FREQSET = TTL High, VCC, or NC FREQSET = TTL Low or GND 106.25 212.5 12 _______________________________________________________________________________________ MHz pF Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1 ) PARAMETER SYMBOL Phase Jitter PJRMS CONDITIONS MIN 12kHz to 20MHz Accumulated Deterministic Jitter Due to Reference Spurs MAX UNITS 0.7 1.0 psRMS 3.0 Accumulated Deterministic Jitter Due to Power-Supply Noise Clock-Output Edge Speeds TYP (Note 4) tR, tF 20% to 80% 10kHz 3.0 100kHz 27 69 200kHz 15 43 1MHz 7 LVPECL outputs 250 600 200 600 49 51 % 5 ms (Note 5) Clock-Output SSB Phase Noise Measured at 106.25MHz psP-P LVDS outputs Clock-Output Duty Cycle Oscillation Startup Time psP-P 100Hz -90 1kHz -112 10kHz -115 100kHz -123 1MHz -142 10MHz -147 ps dBc/Hz Note 1: AC parameters are guaranteed by design and characterization. Note 2: Outputs are enabled and unloaded. Note 3: When LVPECL output is disabled to high impedance, the typical output off-current is