19-2166; Rev 2; 9/09
EVALUATION KIT AVAILABLE
Low-Jitter 155MHz/622MHz
Clock Generator
Features
The MAX3670 is a low-jitter 155MHz/622MHz reference
clock generator IC designed for system clock distribution
and frequency synchronization in OC-48 and OC-192
SONET/SDH and WDM transmission systems. The
MAX3670 integrates a phase/frequency detector, an
operational amplifier (op amp), prescaler dividers and
input/output buffers. Using an external VCO, the
MAX3670 can be configured easily as a phase-lock loop
with bandwidth programmable from 15Hz to 20kHz.
The MAX3670 operates from a single +3.3V or +5.0V
supply, and dissipates 150mW (typ) at 3.3V. The operating temperature range is from -40°C to +85°C. The chip
is available in a 5mm ✕ 5mm, 32-pin QFN package.
♦ Single +3.3V or +5.0V Supply
♦ Power Dissipation: 150mW at +3.3V Supply
♦ External VCO Center Frequencies (fVCO): 155MHz
to 670MHz
♦ Reference Clock Frequencies: fVCO, fVCO/2, fVCO/8
♦ Main Clock Output Frequency: fVCO
♦ Optional Output Clock Frequencies: fVCO, fVCO/2,
fVCO/4, fVCO/8
♦ Low Intrinsic Jitter: < 0.4psRMS
♦ Loss-of-Lock Indicator
♦ PECL Clock Output Interface
Applications
Ordering Information
OC-12 to OC-192 SONET/WDM Transport
Systems
PART
Clock Jitter Clean-Up and Frequency
Synchronization
Frequency Conversion
TEMP RANGE
PIN-PACKAGE
MAX3670EGJ
-40°C to +85°C
32 QFN-EP*
MAX3670ETJ+
-40°C to +85°C
32 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
System Clock Distribution
Pin Configuration appears at end of data sheet.
Typical Application Circuit
3.3V
142Ω
155MHz
REFCLK+
VCCD
16:1
SERIALIZER
MOUT-
REFCLK3.3V
MAX3892
MOUT+
142Ω
142Ω
VCOIN+
VCO
KVCO = 25kHz/V
155MHz
100Ω
VCOIN-
RSEL
N.C.
VSEL
N.C.
GSEL1
N.C.
MAX3670
142Ω
332Ω
GSEL2
VC
0.01μF
4700pF
GSEL3
500kΩ
OPAMPOPAMP+
4700pF
POLAR
3.3V
GND
500kΩ
SETUP FOR 10kHz LOOP
BANDWIDTH
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX3670
General Description
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range..............................................-0.5V to +7V
Voltage Range at C2+, C2-, THADJ, CTH, GSEL1, GSEL2,
GSEL3, LOL, RSEL, REFCLK-, REFCLK+, VSEL, VCOIN+,
VCOIN-, VC, POLAR, PSEL1, PSEL2, COMP,
OPAMP+, OPAMP- ..................................-0.5V to (VCC + 0.5V)
Continuous Power Dissipation (TA = +70°C)
32 QFN (derate 33.3mW/°C above +70°C) .....................2.7W
32 Thin QFN (derate 34.5mW/°C above +70°C)..............2.8W
PECL Output Current (MOUT+,
MOUT-, POUT+, POUT-).................................................56mA
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range. ............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Current
SYMBOL
ICC
CONDITIONS
MIN
(Note 2)
TYP
MAX
UNITS
48
72
mA
INPUT SPECIFICATIONS (REFCLK±, VCOIN±)
Input High Voltage
VIH
VCC 1.16
VCC 0.88
V
Input Low Voltage
VIL
VCC 1.81
VCC 1.48
V
VCC 1.3
Input Bias Voltage
V
Common-Mode Input Resistance
7.5
11.5
17.5
kΩ
Differential Input Resistance
12.8
21.0
32.5
kΩ
mVp-p
Differential Input Voltage Swing
AC-coupled
300
1900
0°C to +85°C
VCC 1.025
VCC 0.88
-40°C to 0°C
VCC 1.085
VCC 0.88
0°C to +85°C
VCC 1.81
VCC 1.62
-40°C to 0°C
VCC 1.83
VCC 1.556
2.4
VCC
V
0.4
V
PECL OUTPUT SPECIFICATIONS
Output High Voltage
Output Low Voltage
VOH
V
VOL
V
TTL SPECIFICATIONS
2
Output High Voltage
VOH
Sourcing 20µA
Output Low Voltage
VOL
Sinking 2mA
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
(VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3)
Op Amp Output Voltage Range
VCC = +3.3V ±10%
0.3
VCC 0.3
VCC = +5.0V ±10%
0.5
VCC 0.5
VO
Op Amp Input Offset Voltage
| VOS |
Op Amp Open-Loop Gain
3
AOL
90
V
mV
dB
PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4)
Full-Scale PFD/CP Output
Current
| IPD |
PFD/CP Offset Current
High gain
16
20
24.4
Low gain
4
5
6.2
High gain
0.80
Low gain
1.08
µA
%
| IPD |
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
670
MHz
CLOCK OUTPUT SPECIFICATIONS
Clock Output Frequency
Optional Clock Output
Frequency
fVCO = 622MHz
622/311/
155/78
fVCO = 155MHz
155/78/
38/19
Clock Output Rise/Fall Time
Measured from 20% to 80%
Clock Output Duty Cycle
(Note 6)
45
MHz
280
ps
55
%
1.14
µVRMS
/√Hz
NOISE SPECIFICATIONS
Random Noise Voltage at LoopFilter Output
VNOISE
Spurious Noise Voltage at LoopFilter Output
Power-Supply Rejection at LoopFilter Output
Freq > 1kHz (Note 7)
(Note 8)
PSR
(Note 9)
50
µVRMS
30
dB
REFERENCE CLOCK INPUT SPECIFICATIONS
622/
155/78
Reference Clock Frequency
Reference Clock Duty Cycle
30
670
MHz
70
%
_______________________________________________________________________________________
3
MAX3670
DC ELECTRICAL CHARACTERISTICS (continued)
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL SPECIFICATIONS
PLL Jitter Transfer Bandwidth
BW
(Note 10)
15
FJITTER ≤ BW (Note 11)
Jitter Transfer Function
20,000
Hz
0.1
dB
OP AMP SPECIFICATION
Unity-Gain Bandwidth
7
MHz
VCO INPUT SPECIFICATION
VCO Input Frequency
VCO Input Slew Rate
fVCO
622/155
0.5
670
MHz
V/ns
Specifications at -40°C are guaranteed by design and characterization.
Measured with PECL outputs unterminated.
OPAMP specifications met with 10kΩ load to ground or 5kΩ load to VCC (POLAR = 0 and POLAR = VCC).
PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 3 for gain settings.
AC characteristics are guaranteed by design and characterization.
Measured with 50% VCO input duty cycle.
Random noise voltage at op amp output with 800kΩ resistor connected between VC and OPAMP-, PFD/CP gain (KPD) =
5µA/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input.
Note 8: Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R1 = 800kΩ, KPD = 5µA/UI, and
compare frequency 400 times greater than the higher-order pole frequency (see Design Procedure).
Note 9: PSR measured with a 100mVp-p sine wave on VCC in a frequency range from 100Hz to 2MHz. External resistors R1 matched
to within 1%, external capacitors C1 matched to within 10%. Measured closed loop with PLL bandwidth set to 200Hz.
Note 10: The PLL 3dB bandwidth is adjusted from 15Hz to 20kHz by changing external components R1 and C1, by selecting the internal programmable divider ratio and phase-detector gain. Measured with VCO gain of 220ppm/V and C1 limited to 2.2µF.
Note 11: Measured at BW = 20kHz. When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rolls
off at -20dB/decade.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
4
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
EDGE SPEED
vs. TEMPERATURE
40
30
20
-20
0
20
40
60
80
-30
LOOP FILTER OUTPUT
-40
-50
155.52MHz
-60
-40
-20
0
20
40
60
80
1k
TEMPERATURE (°C)
TEMPERATURE (°C)
10k
100k
1M
10M
FREQUENCY (Hz)
622MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)
200mV/
div
MAX3670 toc03
-20
155MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)
MAX3670 toc05
-40
622.08MHz
BW = 1kHz
HOP = 5kHz
-10
SUPPLY REJECTION (dB)
3.3V
0
MAX3670 toc04
SUPPLY CURRENT (mA)
5.0V
50
280
270
260
250
240
230
220
210
200
190
180
170
160
150
POWER-SUPPLY REJECTION
vs. FREQUENCY
MAX3670 toc02
MAX3670 toc01
60
EDGE SPEED 20%-80% (ps)
SUPPLY CURRENT
vs. TEMPERATURE
200mV/
div
500ps/div
2.0ns/div
_______________________________________________________________________________________
5
MAX3670
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
Pin Description
PIN
FUNCTION
1
C2+
Positive Filter Input. External capacitor connected between C2+ and C2- used for setting the higherorder pole frequency (see Setting the Higher-Order Poles).
2
C2-
Negative Filter Input. External capacitor connected between C2+ and C2- used for setting the higherorder pole frequency (see Setting the Higher-Order Poles).
3, 9, 15
VCCD
Positive Digital Supply Voltage
4
THADJ
Threshold Adjust Input. Used to adjust the Loss-of-Lock threshold (see LOL Setup).
5
CTH
6
GSEL1
Gain Select 1 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequencydivider ratio (N2) (see Table 3).
7
GSEL2
Gain Select 2 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequencydivider ratio (N2) (see Table 3).
8
GSEL3
Gain Select 3 Input. Three-level pin used to set the phase-detector gain (KPD) and the frequencydivider ratio (N2) (see Table 3).
10
LOL
Loss-of-Lock. LOL signals a TTL low when the reference frequency differs from the VCO frequency.
LOL signals a TTL high when the reference frequency equals the VCO frequency.
11
GND
Supply Ground
12
RSEL
Reference Clock Select Input. Three-level pin used to set the predivider ratio (N3) for the input
reference clock (see Table 1).
13
REFCLK
14
REFCLK-
Threshold Capacitor Input. A capacitor connected between CTH and ground used to control the Lossof-Lock conditions (see LOL Setup).
Positive Reference Clock Input
Negative Reference Clock Input
16
VSEL
VCO Clock Select Input. Three-level pin used to set the predivider ratio (N1) for the input VCO clock
(see Table 2).
17
POUT-
Negative Optional Clock Output, PECL
18
POUT+
Positive Optional Clock Output, PECL
19, 22
VCCO
Positive Supply Voltage for PECL Outputs
20
MOUT-
Negative Main Clock Output, PECL
21
MOUT+
Positive Main Clock Output, PECL
23
VCOIN-
Negative VCO Clock Input
24
VCOIN+
Positive VCO Clock Input
25
VC
Control Voltage Output. The voltage output from the op amp that controls the VCO.
26
POLAR
Polarity Control Input. Polarity control of op amp input. POLAR = GND for VCOs with positive gain
transfer. POLAR = VCC for VCOs with negative gain transfer.
27
PSEL1
Optional Clock Select 1 Input. Used to set the divider ratio for the optional clock output (see Table 4).
28
PSEL2
Optional Clock Select 2 Input. Used to set the divider ratio for the optional clock output (see Table 4).
29
VCCA
Positive Analog Supply Voltage for the Charge Pump and Op Amp
30
COMP
Compensation Control Input. Op amp compensation reference control input. COMP = GND for VCOs
whose control pin is VCC referenced. COMP = VCC for VCOs whose control pin is GND referenced.
31
OPAMP-
32
OPAMP+
—
6
NAME
EP
Negative Op Amp Input (POLAR = 0), Positive Op Amp Input (POLAR = 1)
Positive Op Amp Input (POLAR = 0), Negative Op Amp Input (POLAR = 1)
Exposed Pad. The exposed pad must be soldered to the circuit board ground plane for proper thermal
and electrical performance.
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
R3
VCO
KVCO
C3
LOL
THADJ
CTH
VC
C1
R1
C1
R1
COMP
POLAR
OPAMP-
OPAMP+
OPAMP
LOL
REFCLK+
REFCLK-
DIV
(N3)
DIV
(N2)
PFD/CP
KPD
RSEL
C2-
VSEL
VCOIN+
DIV
(N1)
C2+
DIV
(N2)
MOUT+
PECL
VCOIN-
MOUTPOUT+
GAIN-CONTROL LOGIC
MAX3670
GSEL1 GSEL2
GSEL3
Detailed Description
The MAX3670 contains all the blocks needed to form a
PLL except for the VCO, which must be supplied separately. The MAX3670 consists of input buffers for the reference clock and VCO, input and output clock-divider
circuitry, LOL detection circuitry, gain-control logic, a
phase-frequency detector and charge pump, an op
amp, and PECL output buffers.
This device is designed to clean up the noise on the
reference clock input and provide a low-jitter system
clock output.
DIV
1/2/4/8
PSEL1
PECL
POUT-
PSEL2
Input Buffer for Reference
Clock and VCO
The MAX3670 contains differential inputs for the reference clock and the VCO. These inputs can be DC-coupled and are internally biased with high impedance so
that they can be AC-coupled (Figure 1 in the Interface
Schematic section). A single-ended VCO or reference
clock can also be applied.
Input and Output Clock-Divider Circuitry
The reference clock and VCO input buffers are followed
by a pair of clock dividers that prescale the input frequency of the reference clock and VCO to 77.76MHz.
_______________________________________________________________________________________
7
MAX3670
Functional Diagram
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
Depending on the input clock frequency of 77.76MHz,
155.52MHz, or 622.08MHz, the clock divider ratio must
be set to 1, 2, or 8, respectively. The POUT output
buffer is preceded by a clock divider that scales the
main clock output by 1, 2, 4, or 8 to provide an optional
clock.
Table 1. Reference Clock Divider
INPUT
PIN
RSEL
REFERENCE
CLOCK INPUT
FREQ. (MHz)
DIVIDER
RATIO N3
PREDIVIDER
OUTPUT
FREQ. (MHz)
VCC
77.76
1
77.76
LOL Detection Circuitry
OPEN
155.52
2
77.76
The MAX3670 incorporates a loss-of-lock (LOL) monitor
that consists of an XOR gate, filter, and comparator
with adjustable threshold (see “LOL Setup” in the
Applications section). A loss-of-lock condition is signaled with a TTL low when the reference clock frequency differs from the VCO frequency.
GND
622.08
8
77.76
Gain-Control Logic
The gain-control circuitry facilitates the tuning of the
loop bandwidth by setting phase-detector gain and frequency-divider ratio. The gain-control logic can be programmed to divide from 1 to 1024, in binary multiples,
and to adjust the phase detector gain to 5µA/UI or
20µA/UI (see Table 3 in Setting the Loop Bandwidth
section).
Phase-Frequency Detector and
Charge Pump
The phase-frequency detector incorporated into the
MAX3670 produces pulses proportional to the phase
difference between the reference clock and the VCO
input. The charge pump converts this pulse train to a
current signal that is fed to the op amp.
Op Amp
The op amp is used to form an active PLL loop filter
capable of driving the VCO control voltage input. Using
the POLAR input, the op amp input polarity can be selected to work with VCOs having positive or negative gaintransfer functions. The COMP pin selects the op amp
internal compensation. Connect COMP to ground if the
VCO control voltage is VCC referenced. Connect COMP
to VCC if the VCO control voltage is ground referenced.
Design Procedure
Setting Up the VCO and
Reference Clock
The MAX3670 accepts 77.76MHz, 155.52MHz, or
622.08MHz (including FEC rates) reference clock frequencies. The RSEL input must be set so that the reference clock is prescaled to 77.76MHz (or FEC rate), to
provide the proper range for the PFD and LOL detection circuitry. Table 1 shows the divider ratio for the different reference frequencies.
8
The MAX3670 is designed to accept 77.76MHz,
155.52MHz, or 622.08MHz (including FEC rates) voltage-controlled oscillator (VCO) frequencies. The VSEL
input must be set so that the VCO input is prescaled to
77.76MHz (or FEC rate), to provide the proper range for
the PFD and LOL detection circuitry. Table 2 shows the
divider ratio for the different VCO frequencies.
Table 2. VCO Clock Divider
INPUT
PIN
VSEL
VCO CLOCK
INPUT FREQ.
(MHz)
DIVIDER
RATIO N1
PREDIVIDER
OUTPUT
FREQ. (MHz)
VCC
77.76
1
77.76
OPEN
155.52
2
77.76
GND
622.08
8
77.76
Setting the Loop Bandwidth
To eliminate jitter present on the reference clock, the
proper selection of loop bandwidth is critical. If the total
output jitter is dominated by the noise at the reference
clock input, then lowering the loop bandwidth will
reduce system jitter. The loop bandwidth (K) is a function of the VCO gain (KVCO), the gain of the phase
detector (KPD), the loop filter resistor (R1), and the total
feedback-divider ratio (N = N1 ✕ N2). The loop bandwidth of the MAX3670 can be approximated by
K RK
K = PD 1 VCO
2πN
For stability, a zero must be added to the loop in the form
of resistor R1 in series with capacitor C1 (see Functional
Diagram). The location of the zero can be approximated as
fZ =
1
2πR1C1
Due to the second-order nature of the PLL jitter transfer, peaking will occur and is proportional to fZ/K. For
certain applications, it may be desirable to limit jitter
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
INPUT
PIN
GSEL1
VCC
INPUT
PIN
GSEL2
VCC
INPUT
PIN
GSEL3
VCC
20
DIVIDER
RATIO
N2
1
OPEN
VCC
VCC
20
2
GND
VCC
VCC
20
4
KPD
(µA/UI)
VCC
OPEN
VCC
20
8
OPEN
OPEN
VCC
20
16
GND
OPEN
VCC
20
32
VCC
GND
VCC
20
64
The HOP can be implemented either by providing a
compensation capacitor C2, which produces a pole at
f HOP =
1
2π(20kΩ)(C2 )
or by adding a lowpass filter, consisting of R3 and C3,
directly on the VCO tuning port, which produces a pole at
f HOP =
1
2πR3C3
OPEN
GND
VCC
20
128
GND
GND
VCC
20
256
VCC
VCC
GND
20
512
OPEN
VCC
GND
20
1024
VCC
VCC
OPEN
5
1
OPEN
VCC
OPEN
5
2
Setting the Optional Output
GND
VCC
OPEN
5
4
VCC
OPEN
OPEN
5
8
The MAX3670 optional clock output can be set to binary subdivisions of the main clock frequency. The PSEL1
and PSEL2 pins control the binary divisions. Table 4
shows the pin configuration along with the possible
divider ratios.
OPEN
OPEN
OPEN
5
16
GND
OPEN
OPEN
5
32
VCC
GND
OPEN
5
64
OPEN
GND
OPEN
5
128
GND
GND
OPEN
5
256
VCC
OPEN
GND
5
512
OPEN
OPEN
GND
5
1024
peaking in the PLL passband region to less than 0.1dB.
This can be achieved by setting fZ ≤ K/100.
The three-level GSEL pins (see Functional Diagram)
select the phase-detector gain (KPD) and the frequencydivider ratio (N2). Table 3 summarizes the settings for
the GSEL pins. A more detailed analysis of the loop filter
is located in application note HFDN-13.0 . on
www.maxim-ic.com.
Setting the Higher-Order Poles
Spurious noise is generated by the phase detector
switching at the compare frequency, where fCOMPARE
= fVCO/(N1 ✕ N2). Reduce the spurious noise from the
digital phase detector by placing a higher-order pole
(HOP) at a frequency much less than the compare frequency. The HOP should, however, be placed high
enough in frequency that it does not decrease the overall loop-phase margin and impact jitter peaking. These
two conditions can be met by selecting the HOP fre-
Using R3 and C3 may be preferable for filtering more
noise in the PLL, but it may still be necessary to provide
filtering via C2 when using large values of R1 and N1 ✕ N2
to prevent clipping in the op amp.
Table 4. Setting the Optional Clock
Output Driver
INPUT PIN
PSEL1
INPUT PIN
PSEL2
VCO TO POUT
DIVIDER RATIO
VCC
VCC
1
GND
VCC
2
VCC
GND
4
GND
GND
8
Applications Information
PECL Interfacing
The MAX3670 outputs (MOUT+, MOUT-, POUT+,
POUT-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A
circuit that provides a Thévenin equivalent of 50Ω to
VCC - 2V can be used with fixed-impedance transmission lines with proper termination. To ensure best performance, the differential outputs must have balanced
loads. It is important to note that if optional clock output
is not used, it should be left unconnected to save
power (see Figure 2).
_______________________________________________________________________________________
9
MAX3670
quency to be (K ✕ 4) < fHOP ≤ fCOMPARE, where K is
the loop bandwidth.
Table 3. Gain Logic Pin Setup
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
Layout
The MAX3670 performance can be significantly affected by circuit board layout and design. Use good highfrequency design techniques, including minimizing
ground inductance and using fixed-impedance transmission lines on the reference and VCO clock signals.
Power-supply decoupling should be placed as close to
VCC pins as possible. Take care to isolate the input
from the output signals to reduce feedthrough.
quencies above the loop bandwidth may degrade LOL
functionality.
The user can set the amount of frequency or phase difference between VCO and reference clock at which
LOL indicates an out-of-lock condition. The frequency
difference is called the beat frequency. The CTH pin
can be connected to an external capacitor, which sets
the lowpass filter frequency to approximately
f L=
VCO Selection
The MAX3670 is designed to accommodate a wide
range of VCO gains, positive or negative transfer
slopes, and VCC-referenced or ground-referenced control voltages. These features allow the user a wide
range of options in VCO selection; however, the proper
VCO must be selected to allow the clock generator circuitry to operate at the optimum levels. When selecting
a VCO, the user needs to take into account the phase
noise and modulation bandwidth. Phase noise is important because the phase noise above the PLL bandwidth
will be dominated by the VCO noise performance.
The modulation bandwidth of the VCO contributes an
additional higher-order pole (HOP) to the system and
should be greater than the HOP set with the external filter components.
1
2πCTH 60kΩ
This lowpass filter frequency should be set about 10
times lower than the beat frequency to make sure the
filtered signal at CTH does not drop below the THADJ
threshold voltage. The internal compare frequency of
the part is 77.78MHz. For a 1ppm sensitivity (beat frequency of 77Hz), the filter needs to be at 7.7Hz, and
CTH should be at 0.33µF.
The voltage at THADJ will determine the level at which
the LOL output flags. THADJ is set to a default value of
0.6V which corresponds in a 45° phase difference. This
value can be overridden by applying the desired
threshold voltage to the pin. The range of THADJ is
from 0V (0°) to 2.4V (180°).
Noise Performance Optimization
Depending on the application, there are many different
ways to optimize the PLL performance. The following
are general guidelines to improve the noise on the system output clock.
Interface Schematics
1) If the reference clock noise dominates the total system-clock output jitter, then decreasing the loop
bandwidth (K) reduces the output jitter.
VCC
2) If the VCO noise dominates the total system clock
output jitter, then increasing the loop bandwidth (K)
reduces the output jitter.
3) Smaller total divider ratio (N1 ✕ N2), lower HOP, and
smaller R1 reduce the spurious output jitter.
4) Smaller R1 reduces the random noise due to the op amp.
VCC - 1.3V
10.5kΩ
10.5kΩ
REFLCK+
LOL Setup
The LOL output indicates if the PLL has locked onto the
reference clock using an XOR gate and comparator.
The comparator threshold can be adjusted with THADJ,
and the XOR gate output can be filtered with a capacitor between CTH and ground (Figure 3 in the Interface
Schematic section). When the voltage at pin CTH
exceeds the voltage at pin THADJ, then the LOL output
goes low and indicates that the PLL is not locked. Note
that excessive jitter on the reference clock input at fre-
10
REFLCK-
MAX3670
Figure 1. Input Interface
______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
VCC
LOL
60kΩ
THADJ
OUT+
OUT-
0.6V
CTH
60kΩ
REFCLK
MAX3670
MAX3670
VCO
Figure 2. Output Interface
Figure 3. Loss-of-Lock Indicator
Pin Configuration
OPAMP+
OPAMP-
COMP
VCCA
PSEL2
PSEL1
POLAR
VC
TRANSISTOR COUNT: 2478
32
31
30
29
28
27
26
25
Package Information
C2+
1
24
VCOIN+
C2-
2
23
VCOIN-
VCCD
3
22
VCCO
THADJ
4
21
MOUT+
20
MOUT-
19
VCCO
18
POUT+
17
POUT-
5
GSEL1
6
GSEL2
7
For the latest package outline information and land
patterns, go to www.microsemi.com. Note that a “+”, “#”,
or“-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of
RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 QFN-EP
G3255-1
21-0091
32 TQFN-EP
T3255+3
21-0140
*EP
12
13
14
15
16
REFCLK-
VCCD
VSEL
11
REFCLK+
10
RSEL
9
GND
8
LOL
GSEL3
MAX3670
VCCD
CTH
Chip Information
QFN/TQFN
*THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND.
______________________________________________________________________________________
11
MAX3670
Interface Schematics (continued)
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/01
Initial release.
1
5/03
Added the PKG CODE column to the Ordering Information table; updated the
package outline drawing in the Package Information section.
1, 12
2
9/09
Added the lead(Pb)-free TQFN package to the Ordering Information table; replaced
the package outline drawing with a table in the Package Information section.
1, 11
DESCRIPTION
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2009
12 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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