MCP1405T-E/SNVAO

MCP1403/4/5 4.5A Dual High-Speed Power MOSFET Drivers Features General Description • High Peak Output Current: 4.5A (typ.) • Low Shoot-Through/Cross-Conduction Current in Output Stage • Wide Input Supply Voltage Operating Range: - 4.5V to 18V • High Capacitive Load Drive Capability: - 2200 pF in 15 ns - 5600 pF in 34 ns • Short Delay Times: 40 ns (typ.) • Low Supply Current: - With Logic ‘1’ Input – 1.0 mA (typ.) - With Logic ‘0’ Input – 150 µA (typ.) • Latch-Up Protected: Will Withstand 1.5A Reverse Current • Logic Input Will Withstand Negative Swing Up To 5V • Packages: 8-Pin SOIC, PDIP, 8-Pin 6x5 DFN, and 16-Pin SOIC The MCP1403/4/5 are a family of dual-inverting, dualnon-inverting, or complimentary output drivers. They can delivery high peak currents of 4.5A typically into capacitive loads. These devices also feature low shootthrough current, matched rise/fall times and propagation delays. Applications • • • • The MCP1403/4/5 drivers operate from a 4.5V to 18V single power supply and can easily charge and discharge 2200 pF gate capacitance in under 15 ns (typ). They provide low enough impedances in both the on and off states to ensure the MOSFETs intended state will not be affected, even by large transients. The input to the MCP1403/4/5 may be driven directly from either TTL or CMOS (3V to 18V). The MCP1403/4/5 dual-output 4.5A driver family is offered in both surface-mount and pin-through-hole packages with a -40oC to +125oC temperature rating. The low thermal resistance of the thermally enhanced DFN package allows for greater power dissipation capability for driving heavier capacitive or resistive loads. These devices are highly latch-up resistant under any conditions within their power and voltage ratings. They are not subject to damage when up to 5V of noise spiking (of either polarity) occurs on the ground pin. All terminals are fully protect against Electrostatic Discharge (ESD) up to 4 kV. Switch Mode Power Supplies Pulse Transformer Drive Line Drivers Motor and Solenoid Drive Package Types MCP1404 8-Pin MCP1405 MCP1403 PDIP/SOIC NC IN A GND IN B 1 8 2 7 3 6 4 5 NC OUT A VDD OUT B NC OUT A VDD OUT B NC OUT A VDD OUT B MCP1404 MCP1403 MCP1405 8-Pin DFN(2) NC 1 8 NC NC NC IN A 2 7 OUT A OUT A OUT A GND 3 6 VDD VDD VDD 4 5 OUT B OUT B OUT B IN B © 2007 Microchip Technology Inc. MCP1404 MCP1403 MCP1405 16-Pin SOIC NC IN A NC GND GND NC IN B NC 1 16 2 15 3 14 4 13 5 6 7 8 12 11 10 9 NC OUT A OUT A VDD VDD OUT B OUT B NC NC OUT A OUT A VDD VDD OUT B OUT B NC NC OUT A OUT A VDD VDD OUT B OUT B NC Note 1: Duplicate pins must both be connected for proper operation. 2: Exposed pad of the DFN package is electrically isolated. DS22022B-page 1 MCP1403/4/5 Functional Block Diagram (1) VDD Inverting 730 µA 300 mV Output Non-inverting Input Effective Input C = 20 pF (Each Input) 4.7V MCP1403 Dual Inverting MCP1404 Dual Non-inverting MCP1405 Inverting / Non-inverting GND Note 1: Unused inputs should be grounded. DS22022B-page 2 © 2007 Microchip Technology Inc. MCP1403/4/5 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † Supply Voltage ................................................................+20V Input Voltage ............................... (VDD + 0.3V) to (GND – 5V) Input Current (VIN>VDD)................................................50 mA DC CHARACTERISTICS (NOTE 2) Electrical Specifications: Unless otherwise indicated, TA = +25°C, with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Units Logic ‘1’, High Input Voltage VIH 2.4 1.5 — V Logic ‘0’, Low Input Voltage VIL — 1.3 0.8 V Input Current IIN –1 — 1 µA Input Voltage VIN -5 — VDD+0.3 V Conditions Input 0V ≤ VIN ≤ VDD Output High Output Voltage VOH VDD – 0.025 — — V DC Test Low Output Voltage VOL — — 0.025 V DC Test IOUT = 10 mA, VDD = 18V Output Resistance, High ROH — 2.2 3.0 Ω Output Resistance, Low ROL — 2.8 3.5 Ω IOUT = 10 mA, VDD = 18V Peak Output Current IPK — 4.5 — A VDD = 18V (Note 2) Latch-Up Protection Withstand Reverse Current IREV — >1.5 — A Duty cycle ≤ 2%, t ≤ 300 µsec. Rise Time tR — 15 28 ns Figure 4-1, Figure 4-2 CL = 2200 pF Fall Time tF — 18 28 ns Figure 4-1, Figure 4-2 CL = 2200 pF Delay Time tD1 — 40 48 ns Figure 4-1, Figure 4-2 Delay Time tD2 — 40 48 ns Figure 4-1, Figure 4-2 VDD 4.5 — 18.0 V IS — 1.0 2.0 mA VIN = 3V (Both Inputs) IS — 0.15 0.25 mA VIN = 0V (Both Inputs) Switching Time (Note 1) Power Supply Supply Voltage Power Supply Current Note 1: 2: Switching times ensured by design. Tested during characterization, not production tested. © 2007 Microchip Technology Inc. DS22022B-page 3 MCP1403/4/5 DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE) Electrical Specifications: Unless otherwise indicated, operating temperature range with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Units Logic ‘1’, High Input Voltage VIH 2.4 Logic ‘0’, Low Input Voltage VIL — Input Current IIN High Output Voltage Low Output Voltage Conditions — — V — 0.8 V –10 — +10 µA 0V ≤ VIN ≤ VDD VOH VDD – 0.025 — — V DC TEST VOL — — 0.025 V DC TEST Output Resistance, High ROH — 3.1 6.0 Ω IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL — 3.7 7 Ω IOUT = 10 mA, VDD = 18V Rise Time tR — 25 40 ns Figure 4-1, Figure 4-2 CL = 2200 pF Fall Time tF — 25 40 ns Figure 4-1, Figure 4-2 CL = 2200 pF Delay Time tD1 — 50 65 ns Figure 4-1, Figure 4-2 Delay Time tD2 — 50 65 ns Figure 4-1, Figure 4-2 IS — — 2.0 0.2 3.0 0.3 mA VIN = 3V (Both Inputs) VIN = 0V (Both Inputs) Input Output Switching Time (Note 1) Power Supply Power Supply Current Note 1: 2: Switching times ensured by design. Tested during characterization, not production tested. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V ≤ VDD ≤ 18V. Parameters Sym Min Typ Max Units °C Conditions Temperature Ranges Specified Temperature Range TA –40 — +125 Maximum Junction Temperature TJ — — +150 °C Storage Temperature Range TA –65 — +150 °C Thermal Resistance, 8L-6x5 DFN θJA — 33.2 — °C/W Thermal Resistance, 8L-PDIP θJA — 125 — °C/W Thermal Resistance, 8L-SOIC θJA — 155 — °C/W Thermal Resistance, 16L-SOIC θJA — 155 — °C/W Package Thermal Resistances DS22022B-page 4 Typical four-layer board with vias to ground plane 4-Layer JC51-7 Standard Board, Natural Convection © 2007 Microchip Technology Inc. MCP1403/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. 100 100 90 4700 pF 70 2200 pF 60 50 40 30 1800 pF 20 6800 pF 80 Fall Time (ns) 80 Rise Time (ns) 90 6800 pF 4700 pF 70 2200 pF 60 50 40 30 1800 pF 20 10 10 4 6 8 10 12 14 16 4 18 6 8 FIGURE 2-4: Voltage. 100 70 90 12V 50 5V 40 30 20 18V 60 50 5V 40 30 18V 10 1000 10000 FIGURE 2-2: Load. Rise Time vs. Capacitive 10000 Capacitive Load (pF) FIGURE 2-5: Load. Fall Time vs. Capacitive 160 Propagation Delay (ns) CLOAD = 1800 pF 22 Time (ns) 18 12V 70 Capacitive Load (pF) tFALL 18 16 14 16 Fall Time vs. Supply 20 10 1000 20 14 80 60 Fall Time (ns) Rise Time (ns) Rise Time vs. Supply 80 24 12 Supply Voltage (V) Supply Voltage (V) FIGURE 2-1: Voltage. 10 tRISE 12 VDD = 12V CLOAD = 1800 pF 135 110 85 60 tD1 tD2 35 -40 -25 -10 5 20 35 50 65 80 95 110 125 2 o Temperature ( C) FIGURE 2-3: Temperature. Rise and Fall Times vs. © 2007 Microchip Technology Inc. 3 4 5 6 7 8 9 10 Input Amplitude (V) FIGURE 2-6: Amplitude. Propagation Delay vs. Input DS22022B-page 5 MCP1403/4/5 Typical Performance Curves (Continued) Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. CLOAD = 1800 pF 90 tD1 80 tD2 70 60 50 40 0.5 Quiescent Current (mA) Propagation Delay (ns) 100 0.4 Both Inputs = 1 0.3 0.2 Both Inputs = 0 0.1 0 30 4 6 8 10 12 14 16 -40 -25 -10 18 5 20 35 50 65 80 95 110 125 o Supply Voltage (V) FIGURE 2-7: Supply Voltage. Temperature ( C) Propagation Delay Time vs. FIGURE 2-10: Temperature. 7 CLOAD = 1800 pF 65 60 55 50 tD1 45 40 5 4 TJ = +25oC 3 2 35 30 1 -40 -25 -10 5 20 35 50 65 80 95 110 125 4 6 8 o Temperature ( C) FIGURE 2-8: Temperature. Propagation Delay Time vs. 12 14 16 18 FIGURE 2-11: Output Resistance (Output High) vs. Supply Voltage. 0.5 8 0.4 7 0.3 10 Supply Voltage (V) ROUT-LO ( :) Quiescent Current (mA) VIN = 5V (MCP1404) VIN = 0V (MCP1403) TJ = +150oC 6 tD2 ROUT-HI ( :) Propagation Delay (ns) 70 Quiescent Current vs. Both Inputs = 1 0.2 VIN = 0V (MCP1404) VIN = 5V (MCP1403) TJ = +150oC 6 5 TJ = +25oC 4 Both Inputs = 0 0.1 3 0 2 4 6 8 10 12 14 16 Supply Voltage (V) FIGURE 2-9: Supply Voltage. DS22022B-page 6 Quiescent Current vs. 18 4 6 8 10 12 14 16 18 Supply Voltage (V) FIGURE 2-12: Output Resistance (Output Low) vs. Temperature. © 2007 Microchip Technology Inc. MCP1403/4/5 Typical Performance Curves (Continued) 100 VDD = 18V 90 80 70 60 50 40 200 kHz 30 20 10 0 100 80 650 kHz Supply Current (mA) Supply Current (mA) Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. 400 kHz 50 kHz 100 kHz VDD = 18V 70 60 4,700 pF 50 2,200 pF 40 30 20 10 100 pF 0 1000 10 10000 100 Capacitive Load (pF) Supply Current (mA) 120 Supply Current vs. FIGURE 2-16: Frequency. 140 VDD = 12V 2 MHz 100 1 MHz 100 kHz 80 60 500 kHz 40 200 kHz 20 0 100 VDD = 12V 100 2,200 pF 80 60 100 pF 40 20 10000 10 Supply Current vs. FIGURE 2-17: Frequency. 140 VDD = 6V 3.5 MHz 100 2 MHz 80 200 kHz 1 MHz 500 kHz 40 20 0 100 1000 10000 Supply Current vs. VDD = 6V 6,800 pF 120 100 4,700 pF 80 60 2,200 pF 40 20 100 pF 0 1000 10000 10 Capacitive Load (pF) FIGURE 2-15: Capacitive Load. 100 Frequency (kHz) Supply Current (mA) Supply Current (mA) 4,700 pF 6,800 pF 0 1000 FIGURE 2-14: Capacitive Load. 60 Supply Current vs. 120 Capacitive Load (pF) 120 1000 Frequency (kHz) Supply Current (mA) FIGURE 2-13: Capacitive Load. 6,800 pF Supply Current vs. © 2007 Microchip Technology Inc. 100 1000 10000 Frequency (kHz) FIGURE 2-18: Frequency. Supply Current vs. DS22022B-page 7 MCP1403/4/5 Typical Performance Curves (Continued) Note: Unless otherwise indicated, TA = +25°C with 4.5V ≤ VDD ≤ 18V. Crossover Energy (A*sec) 1.00E-06 -6 10 10 -7 10 -8 10 -9 1.00E-07 1.00E-08 1.00E-09 4 6 8 10 12 14 16 18 Supply Voltage (V) Note: The values on this graph represent the loss seen by both drivers in a package during one complete cycle. For a single driver, divide the stated value by 2. For a single transition of a single driver divide the stated value by 4. FIGURE 2-19: Supply Voltage. DS22022B-page 8 Crossover Energy vs. © 2007 Microchip Technology Inc. MCP1403/4/5 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. PIN FUNCTION TABLE (1) TABLE 3-1: 8-Pin PDIP SOIC 8-Pin DFN 16-Pin SOIC Symbol 1 1 1 NC No Connection 2 2 2 IN A Control Input for Output A — — 3 NC 3 3 4 GND — — 5 GND — — 6 NC No Connection 4 4 7 IN B Control Input for Output B — — 8 NC No Connection — — 9 NC No Connection 5 5 10 OUT B — — 11 OUT B 6 6 12 VDD Supply Input — — 13 VDD Supply Input No Connection Ground Ground Output B Output B 7 7 14 OUT A Output A — — 15 OUT A Output A 8 8 16 NC No Connection PAD — NC Exposed Metal Pad — Note 1: 3.1 Description Duplicate pins must be connected for proper operation. Supply Input (VDD) VDD is the bias supply input for the MOSFET driver and has a voltage range of 4.5V to 18V. This input must be decoupled to ground with a local capacitor. This bypass capacitor provides a localized low-impedance path for the peak currents that are to be provided to the load. 3.2 Control Inputs A and B The MOSFET driver input is a high-impedance, TTL/ CMOS-compatible input. The input also has hysteresis between the high and low input levels, allowing them to be driven from slow rising and falling signals, and to provide noise immunity. 3.3 3.4 Outputs A and B Outputs A and B are CMOS push-pull output that is capable of sourcing and sinking 4.5A of peak current (VDD = 18V). The low output impedance ensures the gate of the external MOSFET will stay in the intended state even during large transients. These output also has a reverse current latch-up rating of 1.5A. 3.5 Exposed Metal Pad The exposed metal pad of the DFN package is not internally connected to any potential. Therefore, this pad can be connected to a ground plane or other copper plane on a printed circuit board to aid in heat removal from the package. Ground (GND) Ground is the device return pin. The ground pin should have a low impedance connection to the bias supply source return. High peak currents will flow out the ground pin when the capacitive load is being discharged. © 2007 Microchip Technology Inc. DS22022B-page 9 MCP1403/4/5 4.0 APPLICATION INFORMATION 4.1 General Information VDD = 18V MOSFET drivers are high-speed, high current devices which are intended to source/sink high peak currents to charge/discharge the gate capacitance of external MOSFETs or IGBTs. In high frequency switching power supplies, the PWM controller may not have the drive capability to directly drive the power MOSFET. A MOSFET driver like the MCP1403/4/5 family can be used to provide additional source/sink current capability. 4.2 1 µF Input MCP1404 (1/2 MCP1405) The ability of a MOSFET driver to transition from a fully off state to a fully on state are characterized by the drivers rise time (tR), fall time (tF), and propagation delays (tD1 and tD2). The MCP1403/4/5 family of drivers can typically charge and discharge a 2200 pF load capacitance in 15 ns along with a typical matched propagation delay of 40 ns. Figure 4-1 and Figure 4-2 show the test circuit and timing waveform used to verify the MCP1403/4/5 timing. +5V 0V 0.1 µF Ceramic 18V Output 4.3 90% Input 18V Output tD1 tF tD2 tR 90% 90% 0V FIGURE 4-1: Waveform. DS22022B-page 10 10% tR tD2 10% 90% tF 10% Non-Inverting Driver Timing Decoupling Capacitors Careful layout and decoupling capacitors are highly recommended when using MOSFET drivers. Large currents are required to charge and discharge capacitive loads quickly. For example, 2.5A are needed to charge a 2200 pF load with 18V in 16 ns. MCP1403 (1/2 MCP1405) 10% tD1 90% FIGURE 4-2: Waveform. Input 0V 10% 0V Output CL = 2200 pF +5V 90% Input VDD = 18V Input Output CL = 2200 pF Input MOSFET Driver Timing 1 µF 0.1 µF Ceramic 10% Inverting Driver Timing To operate the MOSFET driver over a wide frequency range with low supply impedance a ceramic and low ESR film capacitor are recommended to be placed in parallel between the driver VDD and GND. A 1.0 µF low ESR film capacitor and a 0.1 µF ceramic capacitor placed between VDD and GND pins should be used. These capacitors should be placed close to the driver to minimized circuit board parasitics and provide a local source for the required current. 4.4 PCB Layout Considerations Proper PCB layout is important in a high current, fast switching circuit to provide proper device operation and robustness of design. PCB trace loop area and inductance should be minimized by the use of ground planes or trace under MOSFET gate drive signals, separate analog and power grounds, and local driver decoupling. © 2007 Microchip Technology Inc. MCP1403/4/5 Placing a ground plane beneath the MCP1403/4/5 will help as a radiated noise shield as well as providing some heat sinking for power dissipated within the device. 4.5 Power Dissipation The total internal power dissipation in a MOSFET driver is the summation of three separate power dissipation elements. P T = P L + P Q + P CC 4.5.2 The power dissipation associated with the quiescent current draw depends upon the state of the input pin. The MCP1403/4/5 devices have a quiescent current draw when both inputs are high of 1.0 mA (typ) and 0.15 mA (typ) when both inputs are low. The quiescent power dissipation is: P Q = ( I QH × D + I QL × ( 1 – D ) ) × V DD Where: IQH = Quiescent current in the high state Where: D = Duty cycle PT = Total power dissipation IQL = Quiescent current in the low state PL = Load power dissipation VDD = MOSFET driver supply voltage PQ = Quiescent power dissipation PCC = Operating power dissipation 4.5.1 CAPACITIVE LOAD DISSIPATION The power dissipation caused by a capacitive load is a direct function of frequency, total capacitive load, and supply voltage. The power lost in the MOSFET driver for a complete charging and discharging cycle of a MOSFET is: P L = f × C T × V DD QUIESCENT POWER DISSIPATION 2 Where: f = Switching frequency 4.5.3 OPERATING POWER DISSIPATION The operating power dissipation occurs each time the MOSFET driver output transitions because for a very short period of time both MOSFETs in the output stage are on simultaneously. This cross-conduction current leads to a power dissipation describes as: P CC = CC × f × V DD Where: CC = Cross-conduction constant (A*sec) f = Switching frequency VDD = MOSFET driver supply voltage CT = Total load capacitance VDD = MOSFET driver supply voltage © 2007 Microchip Technology Inc. DS22022B-page 11 MCP1403/4/5 5.0 PACKAGING INFORMATION 5.1 Package Marking Information (Not to Scale) Example: 8-Lead DFN XXXXXXX XXXXXXX XXYYWW NNN MCP1403 e3 E/MF^^ 0648 256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW MCP1403 e3 E/P^^256 0648 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN e3 * Note: DS22022B-page 12 Example: MCP1405E SN^^0648 e3 256 16-Lead SOIC (300 mil) Legend: XX...X Y YY WW NNN Example: Example: MCP1405 e3 E/SO^^ 0648256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. MCP1403/4/5 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e b N L N K E E2 E1 EXPOSED PAD NOTE 1 2 2 1 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW φ A2 A A1 A3 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC 0.85 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 Exposed Pad Length D2 Overall Width E Molded Package Width E1 Exposed Pad Width E2 2.16 2.31 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12° 1.00 4.67 BSC 3.85 4.00 4.15 5.99 BSC 5.74 BSC 2.46 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-113B © 2007 Microchip Technology Inc. DS22022B-page 13 MCP1403/4/5 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B DS22022B-page 14 © 2007 Microchip Technology Inc. MCP1403/4/5 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC 1.75 6.00 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B © 2007 Microchip Technology Inc. DS22022B-page 15 MCP1403/4/5 16-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α h A c φ A2 L A1 Units Dimension Limits Number of Pins β L1 MILLIMETERS MIN N NOM MAX 16 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E Molded Package Width E1 7.50 BSC Overall Length D 10.30 BSC 2.65 10.30 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle φ 0° – 8° Lead Thickness c 0.20 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-102B DS22022B-page 16 © 2007 Microchip Technology Inc. MCP1403/4/5 APPENDIX A: REVISION HISTORY Revision B (May 2007) • • • • • • Page 13: Updated Package Outline Drawing Page 14: Updated Package Outline Drawing Page 15: Updated Package Outline Drawing Page 16: Updated Package Outline Drawing Page 17: Updated Revision History Page 19: Corrected Package Codes in Product Identification System Revision A (December 2006) • Original Release of this Document. © 2007 Microchip Technology Inc. DS22022B-page 17 MCP1403/4/5 NOTES: DS22022B-page 18 © 2007 Microchip Technology Inc. MCP1403/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X XX Temperature Range Package Examples: a) b) Device: MCP1403: 4.5A Dual MOSFET Driver, Inverting MCP1403T: 4.5A Dual MOSFET Driver, Inverting (Tape and Reel) MCP1404: 4.5A Dual MOSFET Driver, Non-Inverting MCP1404T: 4.5A Dual MOSFET Driver, Non-Inverting (Tape and Reel) MCP1405: 4.5A Dual MOSFET Driver, Complementary MCP1405T: 4.5A Dual MOSFET Driver, Complementary (Tape and Reel) Temperature Range: E Package: * MF P SN SO = -40°C to +125°C = = = = Dual, Flat, No-Lead (6x5 mm Body), 8-lead Plastic DIP, (300 mil body), 8-lead Plastic SOIC (150 mil Body), 8-Lead Plastic SOIC (Wide), 16-Lead * All package offerings are Pb Free (Lead Free) c) d) a) b) a) b) c) © 2007 Microchip Technology Inc. MCP1403-E/SN: 4.5A Dual Inverting MOSFET Driver, 8LD SOIC package. MCP1403-E/P: 4.5A Dual Inverting MOSFET Driver, 8LD PDIP package. MCP1403-E/MF: 4.5A Dual Inverting MOSFET Driver, 8LD DFN package. MCP1403-E/SO: 4.5A Dual Inverting MOSFET Driver, 16LD SOIC package. MCP1404T-E/SN: Tape and Reel. 4.5A Dual Non-Inverting, MOSFET Driver, 8LD SOIC package, MCP1404-E/P: 4.5A Dual Non-Inverting, MOSFET Driver, 8LD PDIP package. MCP1405-E/SN: 4.5A Dual Complementary, MOSFET Driver, 8LD SOIC package. MCP1405-E/P: 4.5A Dual Complementary, MOSFET Driver, 8LD PDIP package. MCP1405T-E/SO: Tape and Reel, 4.5A Dual Complementary MOSFET Driver, 16LD SOIC package. DS22022B-page 19 MCP1403/4/5 NOTES: DS22022B-page 20 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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