MCP14628
2A Synchronous Buck Power MOSFET Driver
Features
General Description
• Dual Output MOSFET Driver for Synchronous
Applications
• High Peak Output Current: 2A (typical)
• Adaptive Cross Conduction Protection
• Internal Bootstrap Blocking Device
• +36V BOOT Pin Maximum Rating
• Enhanced Light Load Efficiency Mode
• Low Supply Current: 80 µA (typical)
• High Capacitive Load Drive Capability:
- 3300 pF in 10 ns (typical)
• Tri-State PWM Pin for Power Stage Shutdown
• Input Voltage Undervoltage Lockout Protection
• Space Saving Packages:
- 8-Lead SOIC
- 8-Lead 3x3 DFN
The MCP14628 is a dual MOSFET gate driver
designed to optimally drive two N-Channel MOSFETs
arranged in a non-isolated synchronous buck converter
topology. With the capability to source 2A peaks
typically from both the high-side and low-side drives,
the MCP14628 is an ideal companion to buck controllers that lack integrated gate drivers. Additionally,
greater design flexibility is offered by allowing the gate
drivers to be placed close to the power MOSFETs.
Applications
• High Efficient Synchronous DC/DC Buck
Converters
• High Current Low Output Voltage Synchronous
DC/DC Buck Converters
• High Input Voltage Synchronous DC/DC Buck
Converters
• Core Voltage Supplies for Microprocessors
The MCP14628 features the capability to sink 3.5A
peak typically for the low-side gate drive. This allows
the MCP14628 the capability of holding off the low-side
power MOSFET during the rising edge of the PHASE
node. Internal adaptive cross conduction protection
circuitry is also used to mitigate both external power
MOSFETs from simultaneously conducting.
The low resistance pull-up and pull-down drives allow
the MCP14628 to quickly transition a 3300 pF load in
typically 10 ns and with a propagation time of typically
20 ns. Bootstrapping for the high-side drive is internally
implemented which allows for a reduced system cost
and design complexity.
The PWM input to the MCP14628 can be tri-stated to
force both drive outputs low for true power stage
shutdown. Light load system efficiency is improved by
using the diode emulation feature of the MCP14628.
When the FCCM pin is grounded, diode emulation
mode is entered. In this mode, discontinuous conduction is allowed by sensing when the inductor current
reach zero and turning off the low-side power
MOSFET.
Package Types
8-Lead DFN
8-Lead SOIC
HIGHDR
1
8
PHASE
BOOT
2
7
FCCM
VCC
PWM
3
6
VCC
LOWDR
GND
4
5
LOWDR
HIGHDR
1
8
PHASE
BOOT
2
7
FCCM
PWM
3
6
GND
4
5
Note 1: Exposed pad on the DFN is electrically isolated.
© 2008 Microchip Technology Inc.
DS22083A-page 1
MCP14628
Typical Application Schematic
CBOOT
VSUPPLY = 12V
CURRENT
SENSE
BOOT
MCP14628
VCC = 5V
FCCM
CONTROL
VCC
UGATE
FCCM
PHASE
PWM
LGATE
QH
QL
GND
VEXT
MCP1630
VCC
CURRENT
SENSE
FB
CS
COMP
OSC IN
VREF
GND
REFERENCE VOLTAGE
OSCILLATOR
FROM MCU
Functional Block Diagram
VCC
BOOT
FCCM
HIGHDR
Level
Shift
R
PWM
R
PHASE
Control
Logic &
Protection
VCC
LOWDR
GND
DS22083A-page 2
© 2008 Microchip Technology Inc.
MCP14628
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VCC, Device Supply Voltage............................. -0.3V to +7.0V
VBOOT, BOOT Voltage.................................... -0.3V to +36.0V
VPHASE, Phase Voltage........... VBOOT - 7.0V to VBOOT + 0.3V
VFCCM, FCCM Voltage ........................... -0.3V to VCC + .0.3V
VPWM, PWM Voltage ............................... -0.3V to VCC + 0.3V
VUGATE, UGATE Voltage ....... VPHASE - 0.3V to VBOOT + 0.3V
VLGATE, LGATE Voltage .......................... -0.3V to VCC + 0.3V
ESD Protection on all Pins ....................................2 kV (HBM)
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational sections of this specification is not intended.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VCC = 5V, TJ = -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
Recommended Operating Range
VCC
4.5
5.0
5.5
V
Bias Supply Voltage
IVCC
—
80
—
µA
Conditions
VCC Supply Requirements
PWM pin floating,
VFCCM = 5V
UVLO (Rising VCC)
—
3.40
3.90
V
UVLO (Falling VCC)
2.40
2.90
—
V
—
500
—
mV
—
250
—
µA
VPWM = 5V
VPWM = 0V
Hysteresis
PWM Input Requirements
PWM Input Current
IPWM
—
-250
—
µA
PWM Rising Threshold
0.70
1.00
1.30
V
PWM Falling Threshold
3.50
3.80
4.10
V
100
175
250
ns
FCCM Low Threshold
0.50
—
—
V
FCCM High Threshold
—
—
2.0
V
High Drive Source Resistance
—
1.0
2.5
Ω
500 mA source current,
Note 1
High Drive Sink Resistance
—
1.0
2.5
Ω
500 mA sink current,
Note 1
High Drive Source Current
—
2.0
—
A
Note 1
High Drive Sink Current
—
2.0
—
A
Note 1
Low Drive Source Resistance
—
1
2.5
Ω
500 mA source current,
Note 1
Low Drive Sink Resistance
—
0.5
1.0
Ω
500 mA sink current,
Note 1
Tri-State Shutdown Hold-off Time
tTSSHD
TA = +25°C, Note 2
FCCM input Requirements
Output Requirements
Low Drive Source Current
—
2.0
—
A
Note 1
Low Drive Sink Current
—
3.5
—
A
Note 1
Note 1:
2:
Parameter ensured by design, not production tested.
See Figure 4-1 for parameter definition.
© 2008 Microchip Technology Inc.
DS22083A-page 3
MCP14628
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VCC = 5V, TJ = -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
Conditions
HIGHDR Rise Time
tRH
—
10
—
ns
CL = 3.3nF,
Note 1, Note 2
LOWDR Rise Time
tRL
—
10
—
ns
CL = 3.3nF,
Note 1, Note 2
HIGHDR Fall Time
tFH
—
10
—
ns
CL = 3.3nF,
Note 1, Note 2
LOWDR Fall Time
tFL
—
6.0
—
ns
CL = 3.3nF,
Note 1, Note 2
HIGHDR Turn-off Propagation
Delay
tPDLH
—
15
—
ns
No Load, Note 2
LOWDR Turn-off Propagation
Delay
tPDLL
—
16
—
ns
No Load, Note 2
HIGHDR Turn-on Propagation
Delay
tPDHH
10
18
30
ns
No Load, Note 2
LOWDR Turn-on Propagation
Delay
tPDHL
10
22
30
ns
No Load, Note 2
Tri-State Propagation Delay
tPTS
—
35
—
ns
No Load, Note 2
Minimum LOWDR On Time in DCM tLGMIN
—
400
Note 1: Parameter ensured by design, not production tested.
2: See Figure 4-1 for parameter definition.
—
ns
FCCM pin low Note 1
Switching Times
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with VCC = 5V.
Parameter
Sym
Min
Typ
Max
Units
TA
-40
—
+85
°C
Comments
Temperature Ranges
Specified Temperature Range
Maximum Junction Temperature
TJ
—
—
+150
°C
Storage Temperature
TA
-65
—
+150
°C
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 8L-DFN (3x3)
θJA
—
60.0
—
°C/W
Package Thermal Resistances
DS22083A-page 4
Typical Four-layer board
with vias to ground plane
© 2008 Microchip Technology Inc.
MCP14628
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C with VCC = 5.0V.
25
25
tRH
tFH
20
Fall Time (ns)
Rise Time (ns)
20
tRL
15
10
5
15
10
tFL
5
0
0
0
1500
3000
4500
6000
7500
0
1500
Capacitive Load (pF)
FIGURE 2-1:
Load.
Rise Times vs. Capacitive
FIGURE 2-4:
Load.
14
Time (ns)
11
tRH
12
11
9
CLOAD = 3,300 pF
tRL
8
7
6
7
5
6
tFL
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
Temperature (°C)
FIGURE 2-2:
vs. Temperature.
20 35 50 65 80 95 110 125
Temperature (°C)
HIGHDR Rise and Fall Time
FIGURE 2-5:
vs. Temperature.
LOWDR Rise and Fall Time
30
24
CLOAD = 3,300 pF
28
CLOAD = 3,300 pF
26
20
tPDLH
tPDHH
16
Time (ns)
Propagation Delay (ns)
7500
9
8
18
6000
Fall Times vs. Capacitive
10
tFH
10
22
4500
12
CLOAD = 3,300 pF
Time (ns)
13
3000
Capacitive Load (pF)
24
22
18
14
16
12
14
10
12
-40 -25 -10
5
20 35 50 65 80 95 110 125
tPDHL
20
tPDLL
-40 -25 -10
FIGURE 2-3:
vs. Temperature.
HIGHDR Propagation Delay
© 2008 Microchip Technology Inc.
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
FIGURE 2-6:
vs. Temperature.
LOWDR Propagation Delay
DS22083A-page 5
MCP14628
Typical Performance Curves (Continued)
Note: Unless otherwise indicated, TA = +25°C with VCC = 5.0V.
60
700
CLOAD = 3,300 pF
Duty Cycle = 30%
Supply Current (µA)
Supply Current (mA)
70
50
40
30
20
10
0
100
CLOAD = 3,300 pF
FSW = 12.5 kHz
Duty Cycle = 30%
680
660
640
620
600
580
1000
10000
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Frequency (kHz)
FIGURE 2-7:
Frequency.
Supply Current vs.
FIGURE 2-10:
Temperature.
Supply Current vs.
FIGURE 2-8:
Operation.
DCM to CCM Transition
FIGURE 2-11:
Operation.
CCM to DCM Transition
FIGURE 2-9:
(0.5A - 15A).
Load Transition
FIGURE 2-12:
(15A - 0.5A).
Load Transition
DS22083A-page 6
© 2008 Microchip Technology Inc.
MCP14628
Typical Performance Curves (Continued)
Note: Unless otherwise indicated, TA = +25°C with VCC = 5.0V.
FIGURE 2-13:
Operation.
HIGHDR and LOWDR
© 2008 Microchip Technology Inc.
DS22083A-page 7
MCP14628
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
PIN FUNCTION TABLE .
SOIC
3x3 DFN
Symbol
Description
1
1
HIGHDR
2
2
BOOT
3
3
PWM
PWM Input Control Pin
4
4
GND
Ground
5
5
LOWDR
High-side Gate Driver Pin
Floating Bootstrap Supply Pin
Low-side Gate Driver Pin
6
6
VCC
7
7
FCCM
Forced Continuous Conduction Mode Pin
8
8
PHASE
Switch Node Pin
—
PAD
NC
High-side Gate Driver Pin
(HIGHDR)
Supply Input Voltage
Exposed Metal Pad
3.6
Supply Input Voltage Pin (VCC)
The HIGHDR pin provides the gate drive signal to
control the high-side power MOSFET. The gate of the
high-side power MOSFET is connected to this pin.
The VCC pin provides bias to the MCP14628. A bypass
capacitor is to be placed between this pin and the GND
pin. This capacitor should be placed as close to the
MCP14628 as possible.
3.2
3.7
Floating Bootstrap Supply Pin
(BOOT)
The BOOT pin is the floating bootstrap supply pin for
the high-side gate drive. A capacitor is connected
between this pin and the PHASE pin to provide the
necessary charge to turn on the high-side power MOSFET.
3.3
PWM Input Control Pin (PWM)
The control input signal is supplied to the PWM pin.
This tri-state pin controls the state of the HIGHDR and
LOWDR pins. Placing a voltage equal to VCC/2 on this
pin causes both the HIGHDR and LOWDR to a low
state.
The FCCM pin enables or disables the forced
continuous conduction mode. With the FCCM pin connected to ground the MCP14628 enters a diode emulation mode to improve system efficiency at light loads.
Continuous conduction is forced if the FCCM pin is
connected to VCC.
3.8
Ground Pin (GND)
The GND pin provides ground for the MCP14628 circuitry. It should have a low impedance connection to
the bias supply source return. High peak currents will
flow out the GND pin when the low-side power
MOSFET is being turned off.
3.5
Switch Node Pin (PHASE)
The PHASE pin provides the return path for the highside gate driver. The source of the high-side power
MOSFET is connected to this pin.
3.9
3.4
Forced Continuous Conduction
Mode Pin (FCCM)
DFN Exposed Pad
The exposed metal pad of the DFN package is not
internally connected to any potential. Therefore, this
pad can be connected to a ground plane or other
copper plane on a printed circuit board to aid in heat
removal from the package.
Low-side Gate Driver Pin
(LOWDR)
The LOWDR pin provides the gate drive signal to
control the low-side power MOSFET. The gate of the
low-side power MOSFET is connected to this pin.
DS22083A-page 8
© 2008 Microchip Technology Inc.
MCP14628
4.0
DETAILED DESCRIPTION
4.1
Device Overview
The MCP14628 is a dual MOSFET gate driver
designed to optimally drive both high-side and low-side
N-channel MOSFETs arranged in a non-isolated
synchronous buck converter topology.
The MCP14628 is capable of suppling 2A (typical)
peak current to the floating high-side power MOSFET
that is connected to the HIGHDR pin. With the exception of a capacitor, all of the circuitry needed to drive
this high-side N-channel MOSFET is internal to the
MCP14628. A blocking device is placed between the
VCC and BOOT pins that allows the bootstrap capacitor
to be charged to VCC when the low-side power MOSFET is conducting. Refer to Section 5.1, for information on determining the proper size of the bootstrap
capacitor. The HIGHDR is also capable of sinking 2A
(typical) peak current.
The LOWDR is capable of sourcing 2A (typical) peak
current and sinking 3.5A (typical) peak current. This
helps ensure that the low-side power MOSFET stays
turned off during the high dv/dt of the PHASE node.
4.2
4.4
Tri-State PWM
The PWM input pin of the MCP14628 controls the high
current LOWDR and HIGHDR drive signals. These
signals have three distinct operating modes depending
upon the state of the PWM input signal.
A logic low on the PWM pin cause the LOWDR drive
signal to be high and the HIGHDR drive signal to be
low. When the PWM signal transitions to a logic high,
the LOWDR signal goes low and the HIGHDR signal go
high. To ensure proper operation the PWM input signal
should be capable of a logic low of 0V and a logic high
of 5V.
The third operating mode of the drive signals occurs
when the PWM signal is set to a value equal to VCC/2
(typically). When the PWM signal dwells at this voltage
for 175 ns (typically) the MCP14628 disables both
LOWDR and HIGHDR drive signals. Both drive signals
are pulled and held low. Once the PWM signal moves
beyond VCC/2, the MCP14628 removes the shutdown
state of the drive signals.
Adaptive Cross-Conduction
Protection
The MCP14628 prevents cross-conduction power loss
by adaptively ensuring that the high-side and low-side
power MOSFETs are not conducting simultaneously.
When the PWM signal goes low, the HIGHDR is pulled
low and the LOWDR signal is held low until the
HIGHDR reach 1V (typically). At that time, the LOWDR
is allowed to turn on.
4.3
FCCM Mode
The MCP14628 features a diode emulation mode to
enhance the light load system efficiency. The FCCM
pin enables or disables the diode emulating mode. With
the FCCM pin grounded, diode emulation mode is
entered. The forced continuous conduction mode is
entered when the FCCM pin is connected to VCC.
In diode emulation mode, the MCP14628 turns off the
low-side power MOSFET when the inductor current
reaches approximately zero even if the PWM input signal is still low. The LOWDR and HIGHDR both stay low
until the next switching cycle begins. To prevent false
termination of the LOWDR signal, there is a 400 ns
minimum on time, tLGMIN, of the LOWDR. This also
ensures that the bootstrap capacitor is fully charged.
In forced continuous conduction mode, the LOWDR of
the MCP14628 does not terminate until the PWM input
signal transitions from a low to a high.
© 2008 Microchip Technology Inc.
DS22083A-page 9
MCP14628
4.5
Timing Diagram
The PWM signal applied to the MCP14628 is suppled
by a controller IC that regulates the power supply
output. The timing diagram in Figure 4-1 graphically
depicts the PWM signal and the output signals of the
MCP14628.
VCC
PWM
tPDHH
tPDLH
tFH
1V
HIGHDR
tRH
LOWDR
1V
tPDLL
tRL
tPDHL
tFL
VCC
VCC/2
PWM
tTSSHD
tRH
0V
tFH
tPTS
HIGHDR
LOWDR
1V
tTSSHD
FIGURE 4-1:
DS22083A-page 10
tFL
tPTS
MCP14628 Timing Diagram.
© 2008 Microchip Technology Inc.
MCP14628
5.0
APPLICATION INFORMATION
5.1
Bootstrap Capacitor Select
EQUATION 5-2:
P Q = I VCC × V CC
Where:
The selection of the bootstrap capacitor is based upon
the total gate charge of the high-side power MOSFET
and the allowable droop in gate drive voltage while the
high-side power MOSFET is conducting.
EQUATION 5-1:
Q GATE
C BOOT ≥ ----------------------ΔV DROOP
Where:
PQ
=
Quiescent Power Loss
IVCC
=
No Load Bias Current
VCC
=
Bias Voltage
The main power loss occurs from the gate charge
power loss. This power loss can be defined in terms of
both the high-side and low-side power MOSFETs.
EQUATION 5-3:
P GATE = P HIGHDR + P LOWDR
CBOOT
=
bootstrap capacitor value
QGATE
=
total gate charge of the highside MOSFET
P HIGHDR = V CC × Q HIGH × F SW
ΔVDROOP
=
allowable gate drive voltage
droop
P LOWDR = V CC × Q LOW × F SW
Where:
For example:
QGATE = 30 nC
PGATE
=
Total Gate Charge Power Loss
PHIGHDR
=
High-Side Gate Charge Power
Loss
PLOWDR
=
Low-Side Gate Charge Power
Loss
ΔVDROOP = 200 mV
CBOOT ≥ 0.15 uF
A low ESR ceramic capacitor is recommend with a
maximum voltage rating that exceeds the maximum
input voltage, VCC, plus the maximum supply voltage,
VSUPPLY. It is also recommended that the capacitance
of CBOOT not exceed 1.2 uF.
5.2
Decoupling Capacitor
Proper decoupling of the MCP14628 is highly recommended to help ensure reliable operation. This decoupling capacitor should be placed as close to the
MCP14628 as possible. The large currents required to
quickly charge the capacitive loads are provided by this
capacitor. A low ESR ceramic capacitor is
recommended.
5.3
Power Dissipation
The power dissipated in the MCP14628 consists of the
power loss associated with the quiescent power and
the gate charge power.
The quiescent power loss can be calculated by the
following equation and is typically negligible compared
to the gate drive power loss.
© 2008 Microchip Technology Inc.
5.4
VCC
=
Bias Supply Voltage
QHIGH
=
High-Side MOSFET Total Gate
Charge
QLOW
=
Low-Side MOSFET Total GAte
Charge
FSW
=
Switching Frequency
PCB Layout
Proper PCB layout is important in a high current, fast
switching circuit to provide proper device operation.
Improper component placement may cause errant
switching, excessive voltage ringing, or circuit latch-up.
There are two important states of the MCP14628
outputs, high and low. Figure 5-1 depicts the current
flow paths when the outputs of the MCP14628 are high
and the power MOSFETs are turned on. Charge
needed to turn on the low-side power MOSFET comes
from the decoupling capacitor CVCC. Current flows from
this capacitor through the internal LOWDR circuitry,
into the gate of the low-side power MOSFET, out the
source, into the ground plane, and back to CVCC. To
reduce any excess voltage ringing or spiking, the
inductance and area of this current loop must be
minimized.
DS22083A-page 11
MCP14628
CBOOT
The following recommendations should be followed to
allow for optimal circuit performance.
VSUPPLY
MCP14628
PWM
Control
Logic
VCC
CVCC
FIGURE 5-1:
- The components that construct the high
current paths previously mentioned should be
placed close the MCP14628. The traces
used to construct these current loops should
be wide and short to keep the inductance and
impedance low.
- A ground plane should be used to keep both
the parasitic inductance and impedance
minimized. The MCP14628 is capable of
sourcing and sinking high peaks current and
any extra parasitic inductance or impedance
will result in non-optimal performance.
Turn On Current Paths.
The charge needed for the turning on of the high-side
power MOSFET comes from the bootstrap capacitor
CBOOT. Current flows from CBOOT through the internal
HIGHDR circuitry, into the gate of the high-side power
MOSFET, out the source, and back to CBOOT. The
printed circuit board traces that construct this current
loop need to have a small area and low inductance. To
control the inductance, short and wide traces must be
used.
Figure 5-2 depicts the current flow paths when the
outputs of the MCP14628 are low and the power
MOSFETs are turned off. These current paths should
also have low inductance and a small loop area to
minimize voltage ringing and spiking.
CBOOT
VSUPPLY
MCP14628
PWM
Control
Logic
VCC
CVCC
FIGURE 5-2:
DS22083A-page 12
Turn Off Current Paths.
© 2008 Microchip Technology Inc.
MCP14628
6.0
PACKAGING INFORMATION
6.1
Package Marking Information (Not to Scale)
8-Lead DFN
Example:
XXXX
YYWW
NNN
CABA
0812
256
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
14628E
SN^^812
e3
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3)
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS22083A-page 13
MCP14628
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