MCP14A0303/4/5
3A Dual MOSFET Driver
with Low Threshold Input and Enable
Features
General Description
• High-Peak Output Current: 3A (typical)
• Wide Input Supply Voltage Operating Range:
- 4.5 to 18V
• Low Shoot-Through/Cross-Conduction Current in
Output Stage
• High Capacitive Load Drive Capability:
- 1800 pF in 12 ns (typical)
• Short Delay Times: 17 ns (tD1), 21 ns (tD2) (typical)
• Low Supply Current: 620 µA (typical)
• Low-Voltage Threshold Input and Enable with
Hysteresis
• Latch-Up Protected: Withstands 500 mA Reverse
Current
• Space-Saving Packages:
- 8-Lead MSOP
- 8-Lead SOIC
- 8-Lead 2 x 3 TDFN
The MCP14A0303/4/5 devices are high-speed dual
MOSFET drivers that are capable of providing up to 3A
of peak current while operating from a single 4.5V to
18V supply. There are three output configurations
available: dual inverting (MCP14A0303), dual
noninverting (MCP14A0304) and complementary
(MCP14A0305).
These
devices
feature
low
shoot-through current, matched rise and fall times, and
short propagation delays, which make them ideal for
high switching frequency applications.
Applications
•
•
•
•
•
Switch Mode Power Supplies
Pulse Transformer Drive
Line Drivers
Level Translator
Motor and Solenoid Drive
The MCP14A0303/4/5 family of devices offers
enhanced control with enable functionality. The
active-high Enable pins can be driven low to drive the
corresponding outputs of the MCP14A0303/4/5 low,
regardless of the status of the input pins. Integrated
pull-up resistors allow the user to leave the Enable pins
floating for standard operation.
These devices are highly latch-up resistant under any
condition within their power and voltage ratings. They
can accept up to 500 mA of reverse current being
forced back into their outputs without damage or logic
upset. All terminals are fully protected against
electrostatic discharge (ESD) up to 2 kV (HBM) and
200V (MM).
Package Types
MCP14A0303/4/5
MCP14A0303/4/5
8-pin MSOP/SOIC
ENA
1
8
INA
2
7 OUTA/OUTA/OUTA
GND
3
6
VDD
INB
4
5
OUTB/OUTB/OUTB
ENB
2 x 3 TDFN*
ENA
1
INA
2
GND
INB
8
ENB
7
OUTA/OUTA/OUTA
3
6
VDD
4
5
OUTB/OUTB/OUTB
EP
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2018 Microchip Technology Inc.
DS20006046A-page 1
MCP14A0303/4/5
Functional Block Diagram
VD D
Internal
Pull-Up
Enable
VR EF
GND
Inverting
Output
VD D
Input
VR EF
Noninverting
GND
MCP14A0303: Dual Inverting
MCP14A0304: Dual Noninverting
MCP14A0305: Complementary: One Inverting, One Noninverting
DS20006046A-page 2
2018 Microchip Technology Inc.
MCP14A0303/4/5
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VDD, Supply Voltage..................................................................................................................................................+20V
VIN, Input Voltage............................................................................................................... (VDD + 0.3V) to (GND – 0.3V)
VEN, Enable Voltage........................................................................................................... (VDD + 0.3V) to (GND – 0.3V)
Package Power Dissipation (TA = +50°C)
8L MSOP .................................................................................................................................................0.63W
8L SOIC ...................................................................................................................................................1.00W
8L 2 x 3 TDFN..........................................................................................................................................1.85W
ESD Protection on all pins .............................................................................................................................2 kV (HBM)
ESD Protection on all pins ............................................................................................................................. 200V (MM)
† Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2018 Microchip Technology Inc.
DS20006046A-page 3
MCP14A0303/4/5
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TA = +25°C, with 4.5V VDD 18V.
Parameters
Sym.
Min.
Typ.
Max.
Input Voltage Range
VIN
Logic ‘1’ High Input Voltage
VIH
Units
GND – 0.3V
—
VDD + 0.3
V
2.0
1.6
—
V
Conditions
Input
Logic ‘0’ Low Input Voltage
VIL
—
1.3
0.8
V
VHYST(IN)
—
0.3
—
V
IIN
–1
—
+1
µA
Enable Voltage Range
VEN
GND – 0.3V
—
VDD + 0.3
V
Logic ‘1’ High Enable Voltage
VEH
2.0
1.6
—
V
Input Voltage Hysteresis
Input Current
0V VIN VDD
Enable
Logic ‘0’ Low Enable Voltage
Enable Voltage Hysteresis
Enable Pin Pull-Up Resistance
VEL
—
1.3
0.8
V
VHYST(EN)
—
0.3
—
V
RENBL
—
1.8
—
MΩ
VDD = 18V, ENB = AGND
Enable Input Current
IEN
—
12
—
µA
VDD = 18V, ENB = AGND
Propagation Delay
tD3
—
17
23
ns
VDD = 18V, VEN = 5V,
see Figure 4-3 (Note 1)
Propagation Delay
tD4
—
21
26
ns
VDD = 18V, VEN = 5V,
see Figure 4-3 (Note 1)
Output
High Output Voltage
VOH
VDD – 0.025
—
—
V
IOUT = 0A
Low Output Voltage
VOL
—
—
0.025
V
IOUT = 0A
Output Resistance, High
ROH
—
2.4
4
Ω
IOUT = 10 mA, VDD = 18V
Output Resistance, Low
ROL
—
1.6
3
Ω
IOUT = 10 mA, VDD = 18V
Peak Output Current
IPK
—
3
—
A
VDD = 18V (Note 1)
Latch-Up Protection Withstand
Reverse Current
IREV
0.5
—
—
A
Duty cycle 2%, t 300 µs
(Note 1)
Rise Time
tR
—
12
17
ns
VDD = 18V, CL = 1800 pF,
see Figure 4-1, Figure 4-2
Fall Time
tF
—
12
17
ns
VDD = 18V, CL = 1800 pF,
see Figure 4-1, Figure 4-2
Delay Time
tD1
—
17
23
ns
VDD = 18V, VIN = 5V,
see Figure 4-1, Figure 4-2
tD2
—
21
26
ns
VDD = 18V, VIN = 5V,
see Figure 4-1, Figure 4-2
VDD
4.5
—
18
V
IDD
—
620
900
µA
VINA/B = 3V, VENA/B = 3V
IDD
—
620
900
µA
VINA/B = 0V, VENA/B = 3V
IDD
—
620
900
µA
VINA/B = 3V, VENA/B = 0V
IDD
—
620
900
µA
VINA/B = 0V, VENA/B = 0V
Switching Time (Note 1)
Power Supply
Supply Voltage
Power Supply Current
Note 1:
Tested during characterization, not production tested.
DS20006046A-page 4
2018 Microchip Technology Inc.
MCP14A0303/4/5
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE)
Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V.
Parameters
Sym.
Min.
Typ.
Max.
Units
Input Voltage Range
VIN
Logic ‘1’ High Input Voltage
VIH
GND – 0.3V
—
VDD + 0.3
V
2.0
1.6
—
V
Conditions
Input
Logic ‘0’ Low Input Voltage
VIL
—
1.3
0.8
V
VHYST(IN)
—
0.3
—
V
IIN
–10
—
+10
µA
Enable Voltage Range
VEN
GND – 0.3V
—
VDD + 0.3
V
Logic ‘1’ High Enable Voltage
VEH
2.0
1.6
—
V
Input Voltage Hysteresis
Input Current
0V VIN VDD
Enable
Logic ‘0’ Low Enable Voltage
VEL
—
1.3
0.8
V
VHYST(EN)
—
0.3
—
V
Enable Input Current
IEN
—
12
—
µA
VDD = 18V, ENB = AGND
Propagation Delay
tD3
—
21
27
ns
VDD = 18V, VEN = 5V,
TA = +125°C, see Figure 4-3
(Note 1)
Propagation Delay
tD4
—
25
31
ns
VDD = 18V, VEN = 5V,
TA = +125°C, see Figure 4-3
(Note 1)
High Output Voltage
VOH
VDD – 0.025
—
—
V
DC Test
Low Output Voltage
VOL
—
—
0.025
V
DC Test
Output Resistance, High
ROH
—
—
5
Ω
IOUT = 10 mA, VDD = 18V
Output Resistance, Low
ROL
—
—
4
Ω
IOUT = 10 mA, VDD = 18V
Enable Voltage Hysteresis
Output
Note 1:
Tested during characterization, not production tested.
2018 Microchip Technology Inc.
DS20006046A-page 5
MCP14A0303/4/5
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE)
Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Rise Time
tR
—
14
19
ns
VDD = 18V, CL = 1800 pF,
TA = +125°C, see Figure 4-1,
Figure 4-2
Fall Time
tF
—
14
19
ns
VDD = 18V, CL = 1800 pF,
TA = +125°C, see Figure 4-1,
Figure 4-2
Delay Time
tD1
—
21
27
ns
VDD = 18V, VIN = 5V, TA = +125°C,
see Figure 4-1, Figure 4-2
tD2
—
25
31
ns
VDD = 18V, VIN = 5V, TA = +125°C,
see Figure 4-1, Figure 4-2
VDD
4.5
—
18
V
IDD
—
—
1100
µA
VINA/B = 3V, VENA/B = 3V
IDD
—
—
1100
µA
VINA/B = 0V, VENA/B = 3V
IDD
—
—
1100
µA
VINA/B = 3V, VENA/B = 0V
IDD
—
—
1100
µA
VINA/B = 0V, VENA/B = 0V
Switching Time (Note 1)
Power Supply
Supply Voltage
Power Supply Current
Note 1:
Tested during characterization, not production tested.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V
Parameters
Sym.
Min.
Typ.
Max.
Units
°C
Comments
Temperature Ranges
Specified Temperature Range
TA
–40
—
+125
Maximum Junction Temperature
TJ
—
—
+150
°C
Storage Temperature Range
TA
–65
—
+150
°C
Junction-to-Ambient Thermal Resistance, 8LD MSOP
JA
—
158
—
°C/W
Note 1
Junction-to-Ambient Thermal Resistance, 8LD SOIC
JA
—
100
—
°C/W
Note 1
Junction-to-Ambient Thermal Resistance, 8LD TDFN
JA
—
54
—
°C/W
Note 1
Junction-to-Top Characterization Parameter, 8LD MSOP
JT
—
2.4
—
°C/W
Note 1
Junction-to-Top Characterization Parameter, 8LD SOIC
JT
—
5.9
—
°C/W
Note 1
Junction-to-Top Characterization Parameter, 8LD TDFN
JT
—
0.5
—
°C/W
Note 1
Junction-to-Board Characterization Parameter, 8LD MSOP
JB
—
115
—
°C/W
Note 1
Junction-to-Board Characterization Parameter, 8LD SOIC
JB
—
65
—
°C/W
Note 1
Junction-to-Board Characterization Parameter, 8LD TDFN
JB
—
24
—
°C/W
Note 1
Package Thermal Resistances
Note 1:
Parameter is determined using High K 2S2P 4-Layer board as described in JESD 51-7, as well as JESD
51-5 for packages with exposed pads.
DS20006046A-page 6
2018 Microchip Technology Inc.
MCP14A0303/4/5
2.0
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
160
Rise Time (ns)
120
100
Fall Time (ns)
10000 pF
6800 pF
4700 pF
3300 pF
1800 pF
1000 pF
140
80
60
40
20
0
4
6
8
16
18
160
26
140
24
120
22
100
20
80
60
12V
18V
10000
FIGURE 2-4:
Load.
Rise Time vs. Supply
5V
5V
Capacitive Load (pF)
Time (ns)
Rise Time (ns)
FIGURE 2-1:
Voltage.
10
12
14
Supply Voltage (V)
100
90
80
70
60
50
40
30
20
10
0
1000
12V
40
Fall Time vs. Capacitive
VDD = 18V
tR, 3600 pF
18
tF, 3600 pF
16
14
tR, 1800 pF
12
20
18V
10
0
1000
tF, 1800 pF
8
10000
-40 -25 -10
Capacitive Load (pF)
FIGURE 2-2:
Load.
Rise Time vs. Capacitive
20 35 50 65 80 95 110 125
Temperature (°C)
Rise and Fall Time vs.
10000
100
60
Crossover Current (μA)
10000 pF
6800 pF
4700 pF
3300 pF
1800 pF
1000 pF
80
Fall Time (ns)
FIGURE 2-5:
Temperature.
5
40
20
0
4
FIGURE 2-3:
Voltage.
6
8
10
12
14
Supply Voltage (V)
16
Fall Time vs. Supply
2018 Microchip Technology Inc.
18
1 MHz
500 kHz
200 kHz
100 kHz
50 kHz
1000
100
10
4
6
FIGURE 2-6:
Supply Voltage.
8
10
12
14
Supply Voltage (V)
16
18
Crossover Current vs.
DS20006046A-page 7
MCP14A0303/4/5
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
40
35
30
tD2
25
20
tD1
15
10
4
6
8
FIGURE 2-7:
Supply Voltage.
10
12
14
Supply Voltage (V)
16
VDD = 18V
tD2
20
tD1
10
2
4
6
8
10
12
14
Input Voltage Amplitude (V)
16
Input Propagation Delay (ns)
24
VDD = 18V
VIN = 5V
tD2
22
20
18
tD1
16
14
12
-40 -25 -10
5
FIGURE 2-9:
Temperature.
DS20006046A-page 8
35
30
20 35 50 65 80 95 110 125
Temperature (°C)
Input Propagation Delay vs.
tD4
25
20
tD3
15
10
6
8
10
12
14
Supply Voltage (V)
16
18
FIGURE 2-10:
Enable Propagation Delay
vs. Supply Voltage.
30
VDD = 18V
25
tD4
20
15
tD3
10
2
18
FIGURE 2-8:
Input Propagation Delay
Time vs. Input Amplitude.
26
40
4
Enable Propagation Delay (ns)
Input Propogation Delay (ns)
25
VEN = 5V
45
18
Input Propagation Delay vs.
15
50
Enable Propagation Delay (ns)
VIN = 5V
45
4
6
8
10
12
14
Enable Voltage Amplitude (V)
16
18
FIGURE 2-11:
Enable Propagation Delay
Time vs. Enable Voltage Amplitude.
Enable Propagation Delay (ns)
Input Propagation Delay (ns)
50
26
VDD = 18V
VEN = 5V
24
tD4
22
20
tD3
18
16
14
-40 -25 -10
FIGURE 2-12:
vs. Temperature.
5
20 35 50 65 80 95 110 125
Temperature (°C)
Enable Propagation Delay
2018 Microchip Technology Inc.
MCP14A0303/4/5
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
1.80
1.70
Input Threshold (V)
Quiescent Current (μA)
650
600
1.50
1.40
1.30
1.10
1.00
4
6
8
10
12
14
Supply Voltage (V)
16
800
4
18
FIGURE 2-13:
Quiescent Supply Current
vs. Supply Voltage.
10
12
14
Supply Voltage (V)
650
600
550
16
18
Input Threshold vs. Supply
VDD = 18V
1.7
700
VEH
1.6
1.5
1.4
1.3
VEL
1.2
1.1
1
500
-40 -25 -10
5
FIGURE 2-14:
vs. Temperature.
-40 -25 -10
20 35 50 65 80 95 110 125
Temperature (°C)
Quiescent Supply Current
5
FIGURE 2-17:
Temperature.
20 35 50 65 80 95 110 125
Temperature (°C)
Enable Threshold vs.
1.8
1.8
VDD = 18V
1.7
Enable Threshold (V)
1.7
VIH
1.5
1.4
1.3
8
1.8
VDD = 18V
750
1.6
6
FIGURE 2-16:
Voltage.
Enable Threshold (V)
Quiescent Current (μA)
VIL
1.20
550
Input Threshold (V)
VIH
1.60
VIL
1.2
1.1
VEH
1.6
1.5
1.4
1.3
VEL
1.2
1.1
1
1
-40 -25 -10
FIGURE 2-15:
Temperature.
5
20 35 50 65 80 95 110 125
Temperature (°C)
Input Threshold vs.
2018 Microchip Technology Inc.
4
6
FIGURE 2-18:
Supply Voltage.
8
10
12
14
Supply Voltage (V)
16
18
Enable Threshold vs.
DS20006046A-page 9
MCP14A0303/4/5
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
6.0
Supply Current (mA)
ROH - Output Resistance (Ω)
VIN = 0V (MCP14A0303)
VIN = 5V (MCP14A0304)
5.0
4.0
TA = +125°C
3.0
TA = +25°C
2.0
4
6
8
10
12
14
Supply Voltage (V)
16
50
45
40
35
30
25
20
15
10
5
0
Supply Current (mA)
ROL - Output Resistance (Ω)
VDD = 6V
3.0
2.5
TA = +125°C
2.0
TA = +25°C
1.0
6
8
10
12
14
Supply Voltage (V)
16
1000
Capacitive Load (pF)
FIGURE 2-21:
Supply Current vs.
Capacitive Load (VDD = 18V).
DS20006046A-page 10
10000
15
10
5
1000
Capacitive Load (pF)
10000
FIGURE 2-23:
Supply Current vs.
Capacitive Load (VDD = 6V).
Supply Current (mA)
Supply Current (mA)
100
1 MHz
500 kHz
200 kHz
100 kHz
50 kHz
10 kHz
20
100
VDD = 18V
1 MHz
500 kHz
200 kHz
100 kHz
50 kHz
10 kHz
25
0
18
FIGURE 2-20:
Output Resistance (Output
Low) vs. Supply Voltage.
100
90
80
70
60
50
40
30
20
10
0
10000
30
VIN = 5V (MCP14A0303)
VIN = 0V (MCP14A0304)
4
1000
Capacitive Load (pF)
FIGURE 2-22:
Supply Current vs.
Capacitive Load (VDD = 12V).
3.5
1.5
1 MHz
500 kHz
200 kHz
100 kHz
50 kHz
10 kHz
100
18
FIGURE 2-19:
Output Resistance (Output
High) vs. Supply Voltage.
VDD = 12V
100
90
80
70
60
50
40
30
20
10
0
VDD = 18V
10000 pF
6800 pF
3300 pF
1000 pF
470 pF
100 pF
10
100
Switching Frequency (kHz)
1000
FIGURE 2-24:
Supply Current vs.
Frequency (VDD = 18V).
2018 Microchip Technology Inc.
MCP14A0303/4/5
Supply Current (mA)
Note: Unless otherwise indicated, TA = +25°C with 4.5V VDD 18V.
50
45
40
35
30
25
20
15
10
5
0
VDD = 12V
10000 pF
6800 pF
3300 pF
1000 pF
470 pF
100 pF
10
100
Switching Frequency (kHz)
1000
FIGURE 2-25:
Supply Current vs.
Frequency (VDD = 12V).
30
Supply Current (mA)
VDD = 6V
25
10000 pF
6800 pF
3300 pF
1000 pF
470 pF
100 pF
20
15
10
5
0
10
100
Switching Frequency (kHz)
1000
FIGURE 2-26:
Supply Current vs.
Frequency (VDD = 6V).
14
Enable Current (μA)
13.5
13
12.5
12
11.5
11
10.5
10
4
FIGURE 2-27:
Voltage.
6
8
10
12
14
Supply Voltage (V)
16
18
Enable Current vs. Supply
2018 Microchip Technology Inc.
DS20006046A-page 11
MCP14A0303/4/5
NOTES:
DS20006046A-page 12
2018 Microchip Technology Inc.
MCP14A0303/4/5
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP14A0303/4/5
Symbol
Description
8L 2 x 3 TDFN
8L MSOP/SOIC
1
1
ENA
Enable for Driver A
2
2
INA
Input for Driver A
3
3
GND
Device Ground
4
4
INB
Input for Driver B
5
5
OUTB/OUTB/OUTB
3.1
6
6
VDD
7
7
OUTA/OUTA/OUTA
8
8
ENB
EP
—
EP
Output Pins (OUTA/OUTA/OUTA,
OUTB/OUTB/OUTB)
The outputs are CMOS push-pull circuits that are
capable of sourcing and sinking 3A of peak current
(VDD = 18V). The low output impedance ensures the
gate of the external MOSFET stays in the intended
state, even during large transients. This output also has
a reverse current latch-up rating of 500 mA.
3.2
Device Ground Pin (GND)
GND is the device return pin for the input and output
stages. The GND pin should have a low-impedance
connection to the bias supply source return. When the
capacitive load is discharged, high-peak currents flow
through the ground pin.
3.3
Device Enable Pins (ENA, ENB)
The MOSFET driver device enable pins are
high-impedance inputs featuring low threshold levels.
The enable inputs also have hysteresis between the
high and low input levels, allowing them to be driven
from slow rising and falling signals, and to provide
noise immunity. Driving the enable pins below the
threshold disables the corresponding output of the
device, pulling OUT/OUT low, regardless of the status
of the input pin. Driving the enable pins above the
threshold allows normal operation of the OUT/OUT pin
based on the status of the input pin. The enable pins
utilize internal pull-up resistors, allowing the pins to be
left floating for standard driver operation.
2018 Microchip Technology Inc.
Push-Pull for Output B
Supply Input Voltage
Push-Pull for Output A
Enable for Driver B
Exposed Thermal Pad (GND)
3.4
Control Input Pins (INA, INB)
The MOSFET driver control inputs are high-impedance
inputs featuring low threshold levels. The inputs also
have hysteresis between the high and low input levels,
allowing them to be driven from slow rising and falling
signals, and to provide noise immunity.
3.5
Supply Input Pin (VDD)
VDD is the bias supply input for the MOSFET driver and
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local capacitor. This bypass
capacitor provides a localized low-impedance path for
the peak currents that are provided to the load.
3.6
Exposed Metal Pad Pin (EP)
The exposed metal pad of the TDFN package is
internally connected to GND. Therefore, this pad
should be connected to a ground plane to aid in heat
removal from the package.
DS20006046A-page 13
MCP14A0303/4/5
NOTES:
DS20006046A-page 14
2018 Microchip Technology Inc.
MCP14A0303/4/5
4.0
APPLICATION INFORMATION
4.1
General Information
VDD = 18V
1 µF
MOSFET drivers are high-speed, high-current devices
that are intended to source/sink high-peak currents to
charge/discharge the gate capacitance of external
MOSFETs or Insulated-Gate Bipolar Transistors
(IGBTs). In high-frequency switching power supplies,
the Pulse-Width Modulation (PWM) controller may not
have the drive capability to directly drive the power
MOSFET. A MOSFET driver such as the
MCP14A0303/4/5 family can be used to provide
additional source/sink current capability.
4.2
Input
The ability of a MOSFET driver to transition from a
fully-off state to a fully-on state is characterized by the
driver’s rise time (tR), fall time (tF) and propagation
delays (tD1 and tD2). Figure 4-1 and Figure 4-2 show
the test circuit and timing waveform used to verify the
MCP14A0303/4/5 timing.
MCP14A030 4
Input
VIH (Typ.)
0V
VIL (Typ.)
tD1
1 µF
10%
Input S ignal: tRISE = tFALL ≤ 10 ns,
100 Hz, 0-5V Squa re Wa ve
4.3
Output
CL = 180 0 pF
MCP14A030 3
5V
Input
VIL (Typ.)
tD2
18V
tR
90%
Output
10%
0V
tF
Output
0.1 µF
Input
Input S ignal: tRISE = tFALL ≤ 10 ns,
100 Hz, 0-5V Squa re Wa ve
FIGURE 4-1:
Waveform.
tD2
90%
FIGURE 4-2:
Waveform.
tF
tR
18V
0V
VDD = 18V
tD1
Output
C L = 180 0 pF
5V
MOSFET Driver Timing
VIH (Typ.)
0V
0.1 µF
Inverting Driver Timing
Noninverting Driver Timing
Enable Function
The enable pins (ENA, ENB) provide additional control
of the output pins (OUT). These pins are active-high
and are internally pulled up to VDD so that the pins can
be left floating to provide standard MOSFET driver
operation.
When the enable pin input voltages are above the
enable pin high-voltage threshold (VEN_H), the
corresponding output is enabled and allowed to react to
the status of the input pin. However, when the voltage
applied to the enable pins falls below the low threshold
voltage (VEN_L), the driver’s corresponding output is
disabled and does not respond to changes in the status
of the input pins. When the driver is disabled, the output
is pulled down to a low state. Refer to Table 4-1 for the
enable pin logic. The threshold voltage levels for the
enable pin are similar to the threshold voltage levels of
the input pin and are TTL compatible. Hysteresis is
provided to help increase the noise immunity of the
enable function, avoiding false triggers of the enable
signal during driver switching.
There are propagation delays associated with the
driver receiving an enable signal and the output
reacting. These propagation delays, tD3 and tD4, are
graphically represented in Figure 4-3.
2018 Microchip Technology Inc.
DS20006046A-page 15
MCP14A0303/4/5
TABLE 4-1:
4.6
ENABLE PIN LOGIC
EN
IN
OUT
OUT
H
H
L
H
H
L
H
L
L
X
L
L
Power Dissipation
The total internal power dissipation in a MOSFET driver
is the summation of three separate power dissipation
elements, as shown in Equation 4-1.
EQUATION 4-1:
P T = P L + P Q + P CC
5V
Where:
Enable
VEH (Typ.)
tD3
PQ = Quiescent power dissipation
90%
PCC = Operating power dissipation
Output
10%
0V
Enable Signal: tRISE = tFALL ≤ 10 ns,
100 Hz, 0-5V Square Wave
FIGURE 4-3:
Enable Timing Waveform.
4.6.1
CAPACITIVE LOAD DISSIPATION
The power dissipation caused by a capacitive load is a
direct function of the frequency, total capacitive load
and supply voltage. The power lost in the MOSFET
driver for a complete charging and discharging cycle of
a MOSFET is shown in Equation 4-2.
Decoupling Capacitors
Careful Printed Circuit Board (PCB) layout and
decoupling capacitors are required when using power
MOSFET drivers. Large current is required to charge
and discharge capacitive loads quickly. For example,
approximately 720 mA are needed to charge a 1000 pF
load with 18V in 25 ns.
To operate the MOSFET driver over a wide frequency
range with low supply impedance, it is recommended to
place 1.0 µF and 0.1 µF low ESR ceramic capacitors in
parallel between the driver VDD and GND. These
capacitors should be placed close to the driver to
minimize circuit board parasitics and provide a local
source for the required current.
4.5
PL = Load power dissipation
tD4
18V
4.4
PT = Total power dissipation
VEL (Typ.)
0V
PCB Layout Considerations
Proper PCB layout is important in high-current, fastswitching circuits to provide proper device operation
and robustness of design. Improper component
placement may cause errant switching, excessive
voltage ringing or circuit latch-up. The PCB trace loop
length and inductance should be minimized by the use
of ground planes or traces under the MOSFET gate
drive signal. Separate analog and power grounds and
local driver decoupling should also be used.
Placing a ground plane beneath the MCP14A0303/4/5
devices will help as a radiated noise shield, as well as
providing some heat sinking for power dissipated within
the device.
DS20006046A-page 16
EQUATION 4-2:
P L = f C T V DD
2
Where:
f = Switching frequency
CT = Total load capacitance
VDD = MOSFET driver supply voltage
4.6.2
QUIESCENT POWER DISSIPATION
The power dissipation associated with the quiescent
current draw depends on the state of the Input and
Enable
pins.
See
Section 1.0
“Electrical
Characteristics” for typical quiescent current draw
values in different operating states. The quiescent
power dissipation is shown in Equation 4-3.
EQUATION 4-3:
P Q = I QH D + I QL 1 – D V DD
Where:
IQH
=
Quiescent current in the High state
D
=
Duty cycle
IQL
=
Quiescent current in the Low state
VDD
=
MOSFET driver supply voltage
2018 Microchip Technology Inc.
MCP14A0303/4/5
4.6.3
OPERATING POWER DISSIPATION
The operating power dissipation occurs each time the
MOSFET driver output transitions because, for a very
short period of time, both MOSFETs in the output stage
are on simultaneously. This cross-conduction current
leads to a power dissipation described in Equation 4-4.
EQUATION 4-4:
P CC =
V DD I CO
Where:
ICO
=
Crossover current
VDD
=
MOSFET driver supply voltage
2018 Microchip Technology Inc.
DS20006046A-page 17
MCP14A0303/4/5
NOTES:
DS20006046A-page 18
2018 Microchip Technology Inc.
MCP14A0303/4/5
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
8-Lead MSOP
Example:
Part Number
Code
MCP14A0303-E/MS
A0303
MCP14A0304-E/MS
A0304
MCP14A0305-E/MS
A0305
8-Lead SOIC
Example:
Part Number
Code
MCP14A0303-E/SN
14A0303
MCP14A0304-E/SN
14A0304
MCP14A0305-E/SN
14A0305
8-Lead TDFN
e3
*
Note:
14A0303
e3 1826
256
Example:
Part Number
Legend: XX...X
Y
YY
WW
NNN
A0303
826256
Code
MCP14A0303-E/MNY
EG9
MCP14A0304-E/MNY
EH1
MCP14A0305-E/MNY
EH2
EG9
826
25
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over
to the next line, thus limiting the number of available characters for customer-specific
information.
2018 Microchip Technology Inc.
DS20006046A-page 19
MCP14A0303/4/5
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006046A-page 20
2018 Microchip Technology Inc.
MCP14A0303/4/5
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc.
DS20006046A-page 21
MCP14A0303/4/5
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006046A-page 22
2018 Microchip Technology Inc.
MCP14A0303/4/5
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc.
DS20006046A-page 23
MCP14A0303/4/5
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006046A-page 24
2018 Microchip Technology Inc.
MCP14A0303/4/5
!"#$%
&
2018 Microchip Technology Inc.
DS20006046A-page 25
MCP14A0303/4/5
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1
2X
0.15 C
2
TOP VIEW
0.10 C
C
SEATING
PLANE
(A3)
A
8X
A1
0.08 C
SIDE VIEW
0.10
C A B
D2
L
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
e
BOTTOM VIEW
0.10
0.05
C A B
C
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2
DS20006046A-page 26
2018 Microchip Technology Inc.
MCP14A0303/4/5
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
A
Overall Height
A1
Standoff
Contact Thickness
A3
D
Overall Length
E
Overall Width
Exposed Pad Length
D2
Exposed Pad Width
E2
b
Contact Width
L
Contact Length
Contact-to-Exposed Pad
K
MIN
0.70
0.00
1.35
1.25
0.20
0.25
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.75
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
1.30
0.25
0.30
-
MAX
0.80
0.05
1.45
1.35
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2
2018 Microchip Technology Inc.
DS20006046A-page 27
MCP14A0303/4/5
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.50
2.90
0.25
0.85
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MNY Rev. B
DS20006046A-page 28
2018 Microchip Technology Inc.
MCP14A0303/4/5
APPENDIX A:
REVISION HISTORY
Revision A (June 2018)
• Original Release of this Document.
2018 Microchip Technology Inc.
DS20006046A-page 29
MCP14A0303/4/5
NOTES:
DS20006046A-page 30
2018 Microchip Technology Inc.
MCP14A0303/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
[X](1)
–X
Device Tape and Reel Temperature
Range
/XX
Package
Device:
MCP14A0303: High-Speed MOSFET Driver
MCP14A0303T: High-Speed MOSFET Driver
(Tape and Reel)
MCP14A0304: High-Speed MOSFET Driver
MCP14A0304T: High-Speed MOSFET Driver
(Tape and Reel)
MCP14A0305: High-Speed MOSFET Driver
MCP14A0305T: High-Speed MOSFET Driver
(Tape and Reel)
Temperature Range:
E
Package:
MS = Plastic Micro Small Outline Package (MSOP), 8-lead
SN = Plastic Small Outline Package (SOIC), 8-lead
MNY = Plastic Dual Flat, No Lead Package (TDFN), 8-lead
= -40°C to +125°C (Extended)
2018 Microchip Technology Inc.
Examples:
a) MCP14A0303T-E/MS: Tape and Reel,
Extended temperature,
8LD MSOP package
b) MCP14A0304T-E/SN: Tape and Reel,
Extended temperature,
8LD SOIC package
c) MCP14A0305T-E/MNY: Tape and Reel
Extended temperature,
8LD TDFN package
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
DS20006046A-page 31
MCP14A0303/4/5
NOTES:
DS20006046A-page 32
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3269-2
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20006046A-page 33
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DS20006046A-page 34
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2018 Microchip Technology Inc.
10/25/17