MCP1755/MCP1755S
300 mA, 16V, High-Performance LDO
Features:
Description:
•
•
•
•
•
•
The MCP1755/MCP1755S is a family of CMOS LowDropout (LDO) voltage regulators that can deliver up to
300 mA of current while consuming only 68.0 µA of
quiescent current (typical). The input operating range is
specified from 3.6V to 16.0V, making it an ideal choice for
four to six primary cell battery-powered applications, 12V
mobile applications and one to three-cell Li-Ion-powered
applications.
•
•
•
•
•
•
•
•
•
High PSRR: >70 dB @ 1 kHz, Typical
68.0 µA Typical Quiescent Current
Input Operating Voltage Range: 3.6V to 16.0V
300 mA Output Current for all Output Voltages
Low-Dropout Voltage, 300 mV typical @ 300 mA
Standard Output Voltage Options (1.8V, 2.5V,
2.8V, 3.0V, 3.3V, 4.0V, 5.0V)
Output Voltage Range: 1.8V to 5.5V in 0.1V
Increments (tighter increments are also possible
per design)
Output Voltage Tolerances of ±2.0% Over Entire
Temperature Range
Stable with Minimum 1.0 µF Output Capacitance
Power Good Output
Shutdown Input
True Current Foldback Protection
Short-Circuit Protection
Overtemperature Protection
The MCP1755/MCP1755S Devices Pass the
Automotive AEC-Q100 Reliability Testing
Applications:
•
•
•
•
•
•
•
•
•
•
•
Battery-Powered Devices
Battery-Powered Alarm Circuits
Smoke Detectors
CO2 Detectors
Pagers and Cellular Phones
Smart Battery Packs
Portable Digital Assistant (PDA)
Digital Cameras
Microcontroller Power
Consumer Products
Battery-Powered Data Loggers
The MCP1755/MCP1755S is capable of delivering
300 mA with only 300 mV (typical) of input-to-output
voltage differential. The output voltage tolerance of the
MCP1755 is typically +0.85% at +25°C and ±2.0%
maximum over the operating junction temperature
range of -40°C to +125°C. Line regulation is ±0.01%
typical at +25°C.
Output voltages available for the MCP1755/MCP1755S
range from 1.8V to 5.5V. The LDO output is stable when
using only 1 µF of output capacitance. Ceramic,
tantalum or aluminum electrolytic capacitors may all be
used for input and output. Overcurrent limit and
overtemperature shutdown provide a robust solution for
any application.
The MCP1755/MCP1755S family has a true current
foldback feature. When the load impedance decreases
beyond the MCP1755/MCP1755S load rating, the
output current and voltage will gracefully fold back
towards 30 mA at about 0V output. When the load
impedance increases and returns to the rated load, the
MCP1755/MCP1755S will follow the same foldback
curve as the device comes out of the current foldback.
Package options for the MCP1755 include the
SOT-23-5, SOT-223-5 and 8-lead 2 x 3 DFN.
Package options for the MCP1755S device include the
SOT-223-3 and 8-lead 2 x 3 DFN.
Related Literature:
• AN765, “Using Microchip’s Micropower LDOs”
(DS00765), Microchip Technology Inc., 2007
• AN766, “Pin-Compatible CMOS Upgrades to
Bipolar LDOs” (DS00766), Microchip Technology
Inc., 2003
• AN792, “A Method to Determine How Much
Power a SOT-23 Can Dissipate in an Application”
(DS00792), Microchip Technology Inc., 2001
2012-2021 Microchip Technology Inc.
DS20005160B-page 1
MCP1755/MCP1755S
Package Types – MCP1755
SOT23-5
VOUT
PWRGD
SOT-223-5
5
4
EP-6
2 x 3 DFN*
VOUT 1
PWRGD 2
NC 3
GND 4
1
VIN
2
1
3
2
3
SHDN VIN
GND SHDN
4
8 VIN
EP
9
7 NC
6 NC
5 SHDN
5
* Includes Exposed Thermal Pad (EP); see Table 3-1
GND VOUT PWRGD
Package Types – MCP1755S
SOT-223-3
2 x 3 DFN*
VOUT 1
EP-4
NC 2
NC 3
GND 4
DS20005160B-page 2
1
2
3
VIN
GND
VOUT
8 VIN
EP
9
7 NC
6 NC
5 NC
* Includes Exposed Thermal Pad (EP); see Table 3-2
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
Functional Block Diagrams
MCP1755S
VOUT
VIN
Error Amplifier
+VIN
Voltage
Reference
+
Overcurrent
Overtemperature
GND
MCP1755
PMOS
VIN
VOUT
Undervoltage
Lockout
(UVLO)
Sense
ISNS
Cf
Rf
SHDN
Overtemperature
Sensing
+
Driver w/Limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Soft Start
GND
Reference
Comp
TDELAY
PWRGD
92% of VREF
2012-2021 Microchip Technology Inc.
DS20005160B-page 3
MCP1755/MCP1755S
Typical Application Circuits
EP
MCP1755S
DS20005160B-page 4
CIN
1 µF Ceramic
VOUT
+
GND
VIN
12V
VOUT
5.0V
COUT
1 µF Ceramic
IOUT
30 mA
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Input Voltage, VIN .........................................................+17.6V
VIN, PWRGD, SHDN................. (GND – 0.3V) to (VIN + 0.3V)
VOUT................................................. (GND – 0.3V) to (+5.5V)
Internal Power Dissipation .............Internally Limited (Note 6)
Output Short-Circuit Current ................................. Continuous
Storage Temperature ....................................-55°C to +150°C
Maximum Junction Temperature ...................+165°C (Note 7)
Operating Junction Temperature...................-40°C to +150°C
ESD Protection on All Pins3 kV HBM and 400V MM
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V(1), ILOAD = 1 mA,
COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5 V/µs, SHDN = VIN, PWRGD = 10K to VOUT.
Boldface type applies for Junction Temperatures, TJ of -40°C to +125°C.(7)
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input/Output Characteristics
Input Operating Voltage
VIN
3.6
—
16.0
V
VOUT-RANGE
1.8
—
5.5
V
Input Quiescent Current
Iq
—
68
100
µA
IL = 0 mA
Input Quiescent Current
for SHDN Mode
ISHDN
—
0.1
4
µA
SHDN = GND
Ground Current
IGND
—
300
400
µA
ILOAD = 300 mA
Output Voltage Operating
Range
Maximum Output Current
IOUT_mA
300
—
—
mA
Output Soft Current Limit
SCL
—
450
—
mA
VOUT 0.1V, VIN = VIN(MIN),
current measured 10 ms after
the load is applied
Output Pulse Current Limit
PCL
—
350
—
mA
Pulse Duration < 100 ms,
Duty Cycle < 50%,
VOUT 0.1V (Note 6)
IOUT_SC
—
30
—
mA
VIN = VIN(MIN), VOUT = GND
Output Short-Circuit
Foldback Current
Note 1:
2:
3:
4:
5:
6:
7:
8:
The minimum VIN must meet two conditions: VIN 3.6V and VIN VR + VDROPOUT(MAX).
VR is the nominal regulator output voltage when the input voltage, VIN = VRated + VDROPOUT(MAX) or VIN = 3.6V
(whichever is greater); IOUT = 1 mA.
TCVOUT = (VOUT-HIGH – VOUT-LOW) x 106/(VR x Temperature), VOUT-HIGH = highest voltage measured over the
temperature range. VOUT-LOW = lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are determined using thermal regulation specification, TCVOUT.
Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of VIN = VR + 1V or VIN = 3.6V
(whichever is greater).
The maximum allowable power dissipation is a function of Ambient Temperature, the maximum allowable
Junction Temperature and the thermal resistance from Junction to Air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to
the desired junction temperature. The test time is small enough such that the rise in the junction
temperature over the ambient temperature is not significant.
See Section 4.6 “Shutdown Input (SHDN)” and Figure 2-34.
2012-2021 Microchip Technology Inc.
DS20005160B-page 5
MCP1755/MCP1755S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V(1), ILOAD = 1 mA,
COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5 V/µs, SHDN = VIN, PWRGD = 10K to VOUT.
Boldface type applies for Junction Temperatures, TJ of -40°C to +125°C.(7)
Parameters
Sym.
Min.
Typ.
Max.
Output Voltage Overshoot
on Start-up
VOVER
—
0.5
—
Output Voltage Regulation
VOUT
VOUT Temperature
Coefficient
VR – 2.0% VR +0.85% VR + 2.0%
Units
Conditions
%VOUT VIN = 0 to 16V,
ILOAD = 300 mA
V
Note 2
TCVOUT
—
35
—
Line Regulation
VOUT/
(VOUT x VIN)
-0.05
±0.01
+0.05
%/V
Load Regulation
VOUT/VOUT
-0.5
±0.1
+0.5
%
VDROPOUT
—
300
500
mV
IL = 300 mA
IDO
—
75
120
µA
VIN = 0.95 VR, IOUT = 0 mA
Undervoltage Lockout
UVLO
—
3.0
—
V
Rising VIN
Undervoltage Lockout
Hysteresis
UVLOHYS
—
300
—
mV
Falling VIN
Logic High Input
VSHDN-HIGH
2.4
—
VIN(MAX)
V
Logic Low Input
VSHDN-LOW
0.0
—
0.8
V
SHDNILK
—
0.02
0.2
µA
SHDN = 16V
PWRGD Input
Voltage Operating Range
VPWRGD_VIN
1.7
—
VIN
V
ISINK = 1 mA
PWRGD Threshold Voltage
(referenced to VOUT)
VPWRGD_TH
90
92
94
%VOUT Falling edge of VOUT
PWRGD Threshold
Hysteresis
VPWRGD_HYS
—
2.0
—
%VOUT Rising edge of VOUT
Dropout Voltage (Note 5)
Dropout Current
ppm/°C Note 3
VR + 1V VIN 16V
IL = 1.0 mA to 300 mA
(Note 4)
Undervoltage Lockout
Shutdown Input
Shutdown Input Leakage
Current
Power Good Output
Note 1:
2:
3:
4:
5:
6:
7:
8:
The minimum VIN must meet two conditions: VIN 3.6V and VIN VR + VDROPOUT(MAX).
VR is the nominal regulator output voltage when the input voltage, VIN = VRated + VDROPOUT(MAX) or VIN = 3.6V
(whichever is greater); IOUT = 1 mA.
TCVOUT = (VOUT-HIGH – VOUT-LOW) x 106/(VR x Temperature), VOUT-HIGH = highest voltage measured over the
temperature range. VOUT-LOW = lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are determined using thermal regulation specification, TCVOUT.
Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of VIN = VR + 1V or VIN = 3.6V
(whichever is greater).
The maximum allowable power dissipation is a function of Ambient Temperature, the maximum allowable
Junction Temperature and the thermal resistance from Junction to Air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to
the desired junction temperature. The test time is small enough such that the rise in the junction
temperature over the ambient temperature is not significant.
See Section 4.6 “Shutdown Input (SHDN)” and Figure 2-34.
DS20005160B-page 6
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V(1), ILOAD = 1 mA,
COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5 V/µs, SHDN = VIN, PWRGD = 10K to VOUT.
Boldface type applies for Junction Temperatures, TJ of -40°C to +125°C.(7)
Parameters
Sym.
Min.
Typ.
Max.
Units
PWRGD Output
Voltage Low
VPWRGD_L
—
0.2
0.45
V
PWRGD Output
Sink Current
IPWRGD_L
5.0
—
—
mA
VPWRGD 0.45V
PWRGD Leakage Current
IPWRGD_LK
—
50
200
nA
VPWRGD Pull-up = 10 k
to VIN, VIN = 16V
TPG
—
100
—
µs
Rising Edge of VOUT
—
200
—
µs
Falling edge of VOUT after
transition from
VOUT = VPRWRGD_TH + 50 mV
to VPWRGD_TH – 50 mV,
RPULLUP = 10 k to VIN
TDELAY
—
200
—
µs
VIN = 0V to 16V,
VOUT = 90% VR,
tr(VIN) = 5 V/µs
Output Delay from VIN to
VOUT > 0.1V
TDELAY_START
—
80
—
µs
VIN = 0V to 16V, VOUT 0.1V,
tr(VIN) = 5 V/µs
Output Delay From SHDN
(Note 8)
TDELAY_SHDN
—
235
—
µs
VIN = 6V, VOUT = 90% VR,
VR = 5V, SHDN = GND to VIN
—
940
—
µs
VIN = 7V, VOUT = 90% VR,
VR = 5V, SHDN = GND to VIN
—
210
—
µs
VIN = 16V, VOUT = 90% VR,
VR = 5V, SHDN = GND to VIN
—
0.3
—
PWRGD Time Delay
Detect Threshold to
TVDET_PWRGD
PWRGD Active Time Delay
Conditions
IPWRGD_SINK = 5.0 mA,
VOUT = 0V
AC Performance
Output Delay from VIN
to VOUT = 90% VREG
Output Noise
Note 1:
2:
3:
4:
5:
6:
7:
8:
eN
µV/(Hz) IL = 50 mA, f = 1 kHz
The minimum VIN must meet two conditions: VIN 3.6V and VIN VR + VDROPOUT(MAX).
VR is the nominal regulator output voltage when the input voltage, VIN = VRated + VDROPOUT(MAX) or VIN = 3.6V
(whichever is greater); IOUT = 1 mA.
TCVOUT = (VOUT-HIGH – VOUT-LOW) x 106/(VR x Temperature), VOUT-HIGH = highest voltage measured over the
temperature range. VOUT-LOW = lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are determined using thermal regulation specification, TCVOUT.
Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of VIN = VR + 1V or VIN = 3.6V
(whichever is greater).
The maximum allowable power dissipation is a function of Ambient Temperature, the maximum allowable
Junction Temperature and the thermal resistance from Junction to Air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to
the desired junction temperature. The test time is small enough such that the rise in the junction
temperature over the ambient temperature is not significant.
See Section 4.6 “Shutdown Input (SHDN)” and Figure 2-34.
2012-2021 Microchip Technology Inc.
DS20005160B-page 7
MCP1755/MCP1755S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V(1), ILOAD = 1 mA,
COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5 V/µs, SHDN = VIN, PWRGD = 10K to VOUT.
Boldface type applies for Junction Temperatures, TJ of -40°C to +125°C.(7)
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
PSRR
—
80
—
dB
VR = 5V, f = 1 kHz,
IL = 100 mA, VINAC = 1VPK-PK,
CIN = 0 µF,
VIN VR + 1.5V 3.6V
Thermal Shutdown
Temperature
TSD
—
150
—
°C
Note 6
Thermal Shutdown
Hysteresis
TSD
—
10
—
°C
Power Supply Ripple
Rejection Ratio
Note 1:
2:
3:
4:
5:
6:
7:
8:
The minimum VIN must meet two conditions: VIN 3.6V and VIN VR + VDROPOUT(MAX).
VR is the nominal regulator output voltage when the input voltage, VIN = VRated + VDROPOUT(MAX) or VIN = 3.6V
(whichever is greater); IOUT = 1 mA.
TCVOUT = (VOUT-HIGH – VOUT-LOW) x 106/(VR x Temperature), VOUT-HIGH = highest voltage measured over the
temperature range. VOUT-LOW = lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are determined using thermal regulation specification, TCVOUT.
Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output voltage value that was measured with an applied input voltage of VIN = VR + 1V or VIN = 3.6V
(whichever is greater).
The maximum allowable power dissipation is a function of Ambient Temperature, the maximum allowable
Junction Temperature and the thermal resistance from Junction to Air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to
the desired junction temperature. The test time is small enough such that the rise in the junction
temperature over the ambient temperature is not significant.
See Section 4.6 “Shutdown Input (SHDN)” and Figure 2-34.
TEMPERATURE SPECIFICATIONS(1)
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TJ
-40
—
+150
°C
Storage Temperature Range
TA
-55
—
+150
°C
Conditions
Temperature Ranges
Thermal Package Resistance
Thermal Resistance, SOT-223-3
Thermal Resistance, SOT-223-5
Thermal Resistance, SOT-23-5
Thermal Resistance, 2 x 3 DFN-8
Note 1:
JA
—
62
—
JC
—
15
—
JA
—
62
—
JC
—
15
—
JA
—
256
—
JC
—
81
—
JA
—
70
—
JC
—
13.4
—
°C/W
°C/W
°C/W
°C/W
The maximum allowable power dissipation is a function of Ambient Temperature, the maximum allowable
Junction Temperature and the thermal resistance from Junction to Air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.
DS20005160B-page 8
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note 1:
Unless otherwise indicated, VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA, TA = +25°C,
VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.
Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in junction temperature over the ambient
temperature is not significant.
350
100
90
80
70
60
50
40
30
20
10
0
+130°C
0°C
+25°C
Grou
und Current (µA)
Quies
scent Current (µA)
2:
+90°C
-45°C
VOUT = 1.8V
IOUT = 0 µA
2
4
6
8
10
Input Voltage (V)
FIGURE 2-1:
Input Voltage.
VOUT = 5.0V
VOUT = 3.3V
200
VOUT = 1.8V
150
100
50
12
14
16
Quiescent Current vs.
0
50
100
150
200
Load Current (mA)
FIGURE 2-4:
Current.
250
300
Ground Current vs. Load
90
90
+130°C
80
Quiescent Current (µA)
Quies
scent Current (µA)
250
0
0
70
60
50
-45°C
40
0°C
+25°C
+90°C
30
20
VOUT = 3.3V
IOUT = 0 µA
10
VOUT = 5.0V
80
VOUT = 1.8V
70
60
50
VOUT = 3.3V
40
30
20
10
0
0
0
2
4
FIGURE 2-2:
Input Voltage.
6
8
10
Input Voltage (V)
12
14
-40 -25 -10
16
Quiescent Current vs.
2.5
+130°C
80
Output Voltage (V)
70
60
50
-45°C
40
0°C
5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
FIGURE 2-5:
Quiescent Current vs.
Junction Temperature.
90
Quies
scent Current (µA)
300
+25°C
+90°C
30
20
VOUT = 5.0V
IOUT = 0 µA
10
0
2.0
1.5
-45°C
0°C
+25°C
+90°C
+130°C
+130
C
1.0
0.5
VOUT = 1.8V
IOUT = 1 mA
0.0
0
2
FIGURE 2-3:
Input Voltage.
4
6
8
10
Input Voltage (V)
12
14
Quiescent Current vs.
2012-2021 Microchip Technology Inc.
16
0
2
FIGURE 2-6:
Voltage.
4
6
8
10
Input Voltage (V)
12
14
16
Output Voltage vs. Input
DS20005160B-page 9
MCP1755/MCP1755S
Note 1:
Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,
TA = +25°C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.
3.330
Outtput Voltage (V)
3.0
Ou
utput Voltage (V)
3.5
-45°C
0°C
+25°C
+90°C
+130°C
2.5
2.0
1.5
10
1.0
+90°C
+130°C
3.320
3.310
0°C
3.300
-45°C
3.290
3.280
0.5
VOUT = 3.3V
IOUT = 1 mA
0.0
0
2
4
6
8
10
12
14
VOUT = 3.3V
VIN = 4.3V
3.270
0
16
50
Output Voltage vs. Input
FIGURE 2-10:
Current.
6
5.02
5
5.01
Outtput Voltage (V)
Outtput Voltage (V)
FIGURE 2-7:
Voltage.
-45°C
0°C
+25°C
+90°C
+130°C
4
3
2
1
4
6
8
10
250
300
12
14
Output Voltage vs. Load
+25°C
+90°C
5.00
+130°C
0°C
4.99
4.98
-45°C
4 97
4.97
VOUT = 5.0V
VIN = 6.0V
0
16
50
100
150
200
250
300
Load Current (mA)
Input Voltage (V)
FIGURE 2-8:
Voltage.
200
4.95
0
2
150
4.96
VOUT = 5.0V
IOUT = 1 mA
0
100
Load Current (mA)
Input Voltage (V)
Output Voltage vs. Input
FIGURE 2-11:
Current.
1.830
Output Voltage vs. Load
0.6
+130°C
+90°C
VOUT = 3.3V
+25°C
1.820
Drop
pout Voltage (V)
Ou
utput Voltage (V)
+25°C
1.810
-45°C
0°C
1.800
1.790
VOUT = 1.8V
VIN = 3.6V
50
FIGURE 2-9:
Current.
DS20005160B-page 10
100
150
200
Load Current (mA)
250
0.4
+25°C
0.3
+90°C
+130°C
0.2
0°C
0.1
-45°C
0
1.780
0
0.5
300
Output Voltage vs. Load
0
50
FIGURE 2-12:
Current.
100
150
200
Load Current (mA)
250
300
Dropout Voltage vs. Load
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,
TA = +25°C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
VOUT = 5.0V
Output Current (A)
Drop
pout Voltage (V)
Note 1:
+25°C
+90°C
+130°C
0°C
-45°C
0
50
100
150
200
250
300
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOUT = 3.3V
Hard Short Circuit
ROUT < 0.1:
-40 C
+125 C
+25 C
2
4
6
Load Current (mA)
FIGURE 2-13:
Current.
Dropout Voltage vs. Load
8
10
12
14
16
Input Voltage (V)
FIGURE 2-16:
Input Voltage.
Short-Circuit Current vs.
0.7
5.3V
VIN 4.3V
VOUT (AC coupled, 20 mV/Div)
VOUT = 3.3V
0.6
Outp
put Current (A)
VOUT=3.3V
VIN=4.3V to 5.3V
IOUT=10 mA
Soft Short Circuit
ROUT = 5.5:
0.5
0.4
+125°C
0.3
-40°C
+25°C
0.2
0.1
0
Time=10 µs/Div
2
FIGURE 2-14:
Dynamic Line Response.
4
6
FIGURE 2-17:
Input Voltage.
8
10
12
Input Voltage (V)
14
16
Short-Circuit Current vs.
0.40
5.3V
VIN 4.3V
VOUT (AC coupled, 20 mv/Div)
0.30
VIN = 12V
0.25
VIN = 10V
0.20
0.15
VIN = 6V
VIN = 4.3V
0.10
VIN = 3.6V
0.05
0.00
-0.05
Time=10 µs/Div
VIN = 16V
0.35
Load
d Regulation (%)
VOUT=3.3V
VIN=4.3V to 5.3V
IOUT=100 mA
VOUT = 1.8V
IOUT = 1 mA to 300 mA
-40 -25 -10 5
20 35 50 65 80 95 110 125
Temperature (ºC)
FIGURE 2-15:
Dynamic Line Response.
2012-2021 Microchip Technology Inc.
FIGURE 2-18:
Temperature.
Load Regulation vs.
DS20005160B-page 11
MCP1755/MCP1755S
Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,
TA = +25°C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.
0.030
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0 05
0.05
0.00
-0.05
-0.10
VOUT = 3.3V
VIN = 16V
VIN = 12V
VIN = 10V
VIN = 6V
VIN = 4.3V
VOUT = 3.3V
IOUT = 1 mA to 300 mA
-40 -25 -10 5
Line Regulation (%/V)
Load
d Regulation (%)
Note 1:
0.025
300 mA
0.020
150 mA
50 mA
0 mA
0.010
0 005
0.005
0.000
10 mA
-0.005
-40 -25 -10 5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-19:
Temperature.
FIGURE 2-22:
Temperature.
0.35
VIN = 12V
0.15
VIN = 10V
0.05
VIN = 6V
0.00
VOUT = 5.0V
IOUT = 1 mA to 300 mA
-0.05
Line Regulation (%/V)
Load Regulation (%)
VOUT = 5.0V
0.20
0.10
Line Regulation vs.
0.03
VIN = 16V
0.25
0.03
0.02
300 mA
150 mA
0.02
100 mA
50 mA
0.01
10 mA
0.01
0.00
0 mA
-0.10
-0.01
-40 -25 -10 5
20 35 50 65 80 95 110 125
-40 -25 -10 5
Temperature ( C)
FIGURE 2-20:
Temperature.
Load Regulation vs.
0.040
FIGURE 2-23:
Temperature.
VOUT = 1.8V
300 mA
-20
0.035
-40
150 mA
0.025
100 mA
0.020
50 mA
0 mA
0.015
0.010
Line Regulation vs.
0.000
-40 -25 -10 5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-21:
Temperature.
DS20005160B-page 12
VOUT = 1.8V
VIN = 4.1V
VINAC = 1Vpk-pk
CIN = 0 µF
-60
Line Regulation vs.
IOUT = 300 mA
-80
100
-100
-120
10 mA
0.005
PSRR (dB)
0.030
20 35 50 65 80 95 110 125
Temperature ( C)
0
0.045
Line Regulation (%/V)
20 35 50 65 80 95 110 125
Temperature (°C)
Load Regulation vs.
0.30
100 mA
0.015
-140
0.01
IOUT = 10 mA
0.1
1
Frequency (kHz)
10
100
FIGURE 2-24:
Power Supply Ripple
Rejection vs. Frequency.
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,
TA = +25°C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.
0
VOUT = 5.0V
-10
VIN = 6.5V
VINAC = 1Vpk-pk
-20
CIN = 0 µF
-30
IOUT = 10 mA
-40
-50
-60
IOUT = 300 mA
70
-70
-80
-90
-100
0.01
0.1
1
10
Frequency (kHz)
SHDN
100
0.010
0.01
VOUT = 3.3V
VIN = 4.3V
0.1
1
10
Frequency (kHz)
100
VOUT=3.3V
VIN=0 to 4.3V
VIN
0V
VOUT
3.3V
3.3V
0V
PWRGD
ILOAD=1 mA
PWRGD=10K to VOUT
0V
Time=80 µs/Div
FIGURE 2-27:
VIN = 3.6V
VOUT = 1.8V
Increasing Load
Decreasing Load
0
2012-2021 Microchip Technology Inc.
0.1
0.2
0.3
0.4
0.5
Output Current (A)
FIGURE 2-29:
Foldback.
Short-Circuit Current
3.5
3.0
2.5
2.0
VIN = 4.3V
VOUT = 3.3V
1.5
10
1.0
0.5
Increasing Load
Decreasing Load
0.0
0
Start-up from VIN.
Start-up from SHDN.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
06
0.6
0.4
0.2
0.0
1000
FIGURE 2-26:
Output Noise vs. Frequency
(3 Lines, VR = 1.8V, 3.3V, 5.0V).
4.3V
0V
Time=80 µs/Div
Ou
utput Voltage (V)
Outpu
ut Noise (μV/¥Hz)
VOUT = 5.0V
5 0V
VIN = 6.0V
ILOAD=1 mA
PWRGD=10K to VOUT
3.3V
0V
FIGURE 2-28:
VOUT = 1.8V
VIN = 3.6V
0.100
3.3V
PWRGD
CIN = 1 μF, COUT = 1 μF, IOUT = 50 mA
1.000
0V
VOUT
FIGURE 2-25:
Power Supply Ripple
Rejection vs. Frequency.
10.000
VOUT=3.3V
VIN=4.3V
4.3V
Outtput Voltage (V)
PSRR (dB)
Note 1:
FIGURE 2-30:
Foldback.
0.1
0.2
0.3
Output Current (A)
0.4
0.5
Short-Circuit Current
DS20005160B-page 13
MCP1755/MCP1755S
Note 1:
Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,
TA = +25°C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.
Ou
utput Voltage (V)
6.0
VOUT (AC coupled, 200 mV/Div)
5.0
4.0
VIN = 6.0V
VOUT = 5.0V
3.0
2.0
VOUT=3.3V
IOUT=1 mA to 300 mA
IOUT (200 mA/Div)
1.0
Increasing Load
Decreasing Load
0.0
0.1
FIGURE 2-31:
Foldback.
0.2
0.3
Output Current (A)
0.4
0.5
Short-Circuit Current
VOUT (AC coupled, 200 mV/Div)
IOUT (200 mA/Div)
VOUT=3.3V
IOUT=100 µA to 300 mA
Time=20 µs/Div
Time=20 µs/Div
FIGURE 2-33:
Startup
p Delay Time (µs)
0
Dynamic Load Response.
1000
900
800
700
600
500
400
300
200
100
0
VOUT = 5.0V
+25 °C
-20 °C
+90 °C
+125 °C
6
8
10
12
-40 °C
14
16
Input Voltage (V)
FIGURE 2-32:
DS20005160B-page 14
Dynamic Load Response.
FIGURE 2-34:
to 90% VOUT.
Start-up Delay from SHDN
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1 and Table 3-2.
TABLE 3-1: MCP1755 PIN FUNCTION TABLE
SOT-223-5
SOT-23-5
2 x 3 DFN
Name
4
5
1
VOUT
Function
Regulated Voltage Output
5
4
2
PWRGD
—
—
3, 6, 7
NC
Open-Drain Power Good Output
3
2
4
GND
Ground Terminal
1
3
5
SHDN
Shutdown Input
2
1
8
VIN
Unregulated Supply Voltage
6
—
9
EP
Exposed Pad, Connected to GND
No Connection
TABLE 3-2: MCP1755S PIN FUNCTION TABLE
SOT-223-3
2 x 3 DFN
Name
3
1
VOUT
—
2, 3, 5, 6, 7
NC
2
4
GND
1
8
VIN
Unregulated Supply Voltage
4
9
EP
Exposed Pad, Connected to GND
2012-2021 Microchip Technology Inc.
Function
Regulated Voltage Output
No Connection
Ground Terminal
DS20005160B-page 15
MCP1755/MCP1755S
3.1
Regulated Output Voltage (VOUT)
Connect VOUT to the positive side of the load and the
positive side of the output capacitor. The positive side
of the output capacitor should be physically located as
close to the LDO VOUT pin as is practical. The current
flowing out of this pin is equal to the DC load current.
3.2
Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 100 µs (typical) from the
time the LDO output is within 92% + 3% (maximum
hysteresis) of the regulated output value on power-up.
This delay time is internally fixed. The PWRGD pin may
be pulled up to VIN or VOUT. Pulling up to VOUT
conserves power when the device is in Shutdown
(SHDN = 0V) mode.
3.3
Ground Terminal (GND)
Regulator ground. Tie GND to the negative side of the
output capacitor and also to the negative side of the
input capacitor. Only the LDO bias current flows out of
this pin; there is no high current. The LDO output
regulation is referenced to this pin. Minimize voltage
drops between this pin and the negative side of the
load.
3.4
3.5
Unregulated Input Voltage (VIN)
Connect VIN to the input unregulated source voltage.
Like all low dropout linear regulators, low source
impedance is necessary for the stable operation of the
LDO. The amount of capacitance required to ensure
low source impedance will depend on the proximity of
the input source capacitors or battery type. For most
applications, 1 µF of capacitance will ensure stable
operation of the LDO circuit. The input capacitor should
have a capacitance value equal to or larger than the
output capacitor for performance applications. The
input capacitor will supply the load current during
transients and improve performance. For applications
that have load currents below 10 mA, the input
capacitance requirement can be lowered. The type of
capacitor used may be ceramic, tantalum or aluminum
electrolytic. The low-ESR characteristics of the ceramic
will yield better noise and PSRR performance at high
frequency.
3.6
Exposed Pad (EP)
Some of the packages have an exposed metal pad on
the bottom of the package. The exposed metal pad
gives the device better thermal characteristics by
providing a good thermal path to either the PCB or heat
sink to remove heat from the device. The exposed pad
of the package is internally connected to GND.
Shutdown Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state.
DS20005160B-page 16
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
4.0
DEVICE OVERVIEW
4.3
The MCP1755/MCP1755S is a 300 mA output current,
Low-Dropout (LDO) voltage regulator. The low-dropout
voltage of 300 mV typical at 300 mA of current makes
it ideal for battery-powered applications. The input
voltage range is 3.6V to 16.0V. Unlike other high output
current LDOs, the MCP1755/MCP1755S typically
draws only 300 µA of quiescent current for a 300 mA
load. The MCP1755 adds a shutdown control input pin
and a power good output pin. The output voltage
options are fixed.
4.1
LDO Output Voltage
The MCP1755 LDO has a fixed output voltage. The
output voltage range is 1.8V to 5.5V. The MCP1755S
LDO is available as a fixed voltage device.
4.2
Output Current and
Current Limiting
The MCP1755/MCP1755S LDO is tested and ensured to
supply a minimum of 300 mA of output current. The
MCP1755/MCP1755S has no minimum output load, so
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within tolerance.
The MCP1755/MCP1755S also incorporates a true
output current foldback. If the output load presents an
excessive load due to a low-impedance short-circuit
condition, the output current and voltage will fold back
towards 30 mA and 0V, respectively. The output
voltage and current will resume normal levels when the
excessive load is removed. If the overload condition is
a soft overload, the MCP1755/MCP1755S will supply
higher load currents of up to typically 350 mA. This
allows for device usage in applications that have
pulsed load currents having an average output current
value of 300 mA or less.
Output overload conditions may also result in an
overtemperature shutdown of the device. If the junction
temperature rises above +150°C (typical), the LDO will
shut down the output. See Section 4.8, Overtemperature Protection for more information on overtemperature
shutdown.
6.0
Output Capacitor
The MCP1755/MCP1755S requires a minimum output
capacitance of 1 µF for output voltage stability. Ceramic
capacitors are recommended because of their size,
cost and environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
should be no greater than 2ohms. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials, X7R and X5R, have lowtemperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF
X7R 0805 capacitor has an ESR of 50 milliohms.
Larger LDO output capacitors can be used with the
MCP1755/MCP1755S to improve dynamic performance
and power supply ripple rejection performance. A maximum of 1000 µF is recommended. Aluminum-electrolytic
capacitors are not recommended for low temperature
applications of < -25°C.
4.4
Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from, in order to respond quickly to
the output load step. For good step response performance, the input capacitor should be of equivalent or
higher value than the output capacitor. The capacitor
should be placed as close to the input of the LDO as is
practical. Larger input capacitors will also help reduce
any high-frequency noise on the input and output of the
LDO, and reduce the effects of any inductance that
exists between the input source voltage and the input
capacitance of the LDO.
Ou
utput Voltage (V)
5.0
4.0
VIN = 6.0V
VOUT = 5.0V
3.0
2.0
1.0
Increasing Load
Decreasing Load
0.0
0
FIGURE 4-1:
0.1
0.2
0.3
Output Current (A)
0.4
0.5
Typical Current Foldback.
2012-2021 Microchip Technology Inc.
DS20005160B-page 17
MCP1755/MCP1755S
4.5
Power Good Output (PWRGD)
The open-drain PWRGD output is used to indicate when
the output voltage of the LDO is within 92% (typical
value, see Section 1.0 “Electrical Characteristics” for
Minimum and Maximum specifications) of its nominal
regulation value.
As the output voltage of the LDO rises, the open-drain
PWRGD output will actively be held low until the output
voltage has exceeded the power good threshold plus
the hysteresis value. Once this threshold has been
exceeded, the power good time delay is started (shown
as TPG in the AC/DC Characteristics table). The
power good time delay is fixed at 100 µs (typical). After
the time delay period, the PWRGD open-drain output
becomes inactive and may be pulled high by an external pull-up resistor, indicating that the output voltage is
stable and within regulation limits. The power good
output is typically pulled up to VIN or VOUT. Pulling the
signal up to VOUT conserves power during Shutdown
mode.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 200 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
a minimum of 5 mA (VPWRGD < 0.45V).
VPWRGD_TH
VOUT
TPG
VOH
TVDET_PWRGD
PWRGD
VIN
TDELAY_SHDN
TPG
SHDN
VOUT
PWRGD
CLOAD = 1.0 µF
FIGURE 4-3:
Shutdown.
4.6
Power Good Timing from
Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a fixed
voltage level. The minimum value of this shutdown
threshold required to turn the output on is 2.4V. The
maximum value required to turn the output off is 0.8V.
The SHDN input will ignore low going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 135 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 135 µs delay, the LDO output enters its soft start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 135 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 235 µs. See Figure 4-4 for a timing diagram of
the SHDN input.
VOL
FIGURE 4-2:
DS20005160B-page 18
Power Good Timing.
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
TDELAY_SHDN
400 ns (typical)
135 µs
SHDN
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 3.0V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.8
VOUT
CLOAD = 1.0 µF
FIGURE 4-4:
Diagram.
4.7
Shutdown Input Timing
Dropout Voltage and Undervoltage
Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 1.0V differential applied. The MCP1755/
MCP1755S LDO has a very Low-Dropout voltage
specification of 300 mV (typical) at 300 mA of output
current. See Section 1.0 “Electrical Characteristics”
for maximum dropout voltage specifications.
Overtemperature Protection
The MCP1755/MCP1755S LDO has temperature
sensing circuitry to prevent the junction temperature
from exceeding approximately +150°C. If the LDO
junction temperature does reach +150°C, the LDO
output will be turned off until the junction temperature
cools to approximately +140°C, at which point, the
LDO output will automatically resume normal
operation. If the internal power dissipation continues to
be excessive, the device will again shut off. The
junction temperature of the die is a function of power
dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Circuits
and Issues” for more information on LDO power
dissipation and junction temperature.
The MCP1755/MCP1755S LDO operates across an
input voltage range of 3.6V to 16.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that keeps
the LDO output voltage off until the input voltage
reaches a minimum of 3.00V (typical) on the rising
edge of the input voltage. As the input voltage falls, the
LDO output will remain on until the input voltage level
reaches 2.70V (typical).
2012-2021 Microchip Technology Inc.
DS20005160B-page 19
MCP1755/MCP1755S
NOTES:
DS20005160B-page 20
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
5.0
APPLICATION CIRCUITS
AND ISSUES
5.1
Typical Application
The MCP1755/MCP1755S is most commonly used as a
voltage regulator. The low quiescent current and LowDropout voltage make it ideal for many battery-powered
applications.
TJ(MAX) = Maximum continuous junction
temperature
MCP1755S
VOUT
GND
VIN
VOUT
1.8V
CIN
1 µF Ceramic
5.1.1
IOUT
50 mA
COUT
1 µF Ceramic
FIGURE 5-1:
Typical Application Circuit.
APPLICATION INPUT CONDITIONS
Package Type = SOT-223
Input Voltage Range = 3.6V to 4.8V
VIN Maximum = 4.8V
VOUT Typical = 1.8V
IOUT = 50 mA Maximum
5.2
Power Calculations
5.2.1
EQUATION 5-2:
T J MAX = P TOTAL R JA + T AMAX
EP
VIN
3.6V to 4.8V
The maximum continuous operating junction
temperature specified for the MCP1755/MCP1755S is
+150°C. To estimate the internal junction temperature
of the MCP1755/MCP1755S, the total internal power
dissipation is multiplied by the thermal Resistance from
Junction to Ambient (RJA). The thermal resistance
from junction to ambient for the SOT-223 package is
estimated at 62°C/W.
POWER DISSIPATION
The internal power dissipation of the MCP1755/
MCP1755S is a function of input voltage, output
voltage and output current. The power dissipation, as
a result of the quiescent current draw, is so low, it is
insignificant (68.0 µA x VIN). The following equation
can be used to calculate the internal power dissipation
of the LDO.
EQUATION 5-1:
PLDO = V IN MAX – V OUT MIN I OUT MAX
PLDO = LDO pass device internal power
dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage
PTOTAL = Total device power dissipation
RJA = Thermal resistance from junction
to ambient
TAMAX = Maximum ambient temperature
The maximum power dissipation capability for a
package can be calculated given the junction-toambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package maximum
internal power dissipation.
EQUATION 5-3:
T J MAX – T A MAX
PD MAX = --------------------------------------------------R JA
PD(MAX) = Maximum device power dissipation
TJ(MAX) = Maximum continuous junction
temperature
TA(MAX) = Maximum ambient temperature
RJA = Thermal resistance from junction
to ambient
EQUATION 5-4:
T J RISE = P D MAX R JA
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PD(MAX) = Maximum device power dissipation
RJA = Thermal resistance from junction
to ambient
EQUATION 5-5:
T J = T J RISE + T A
TJ = Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA = Ambient temperature
2012-2021 Microchip Technology Inc.
DS20005160B-page 21
MCP1755/MCP1755S
5.3
Voltage Regulator
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation, as a result of ground current, is small
enough to be neglected.
EXAMPLE 5-1:
POWER DISSIPATION
Package
Package Type = SOT-223
Input Voltage
VIN = 3.6V to 4.8V
LDO Output Voltages and Currents
VOUT = 1.8V
IOUT = 50 mA
Maximum Ambient Temperature
TA(MAX) = +40°C
Internal Power Dissipation
Internal Power dissipation is the product of the LDO
output current times the voltage across the LDO
(VIN to VOUT).
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)
PLDO = (4.8V – (0.98 x 1.8V)) x 50 mA
PLDO = 151.8 mW
5.3.1
DEVICE JUNCTION
TEMPERATURE RISE
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The
Thermal Resistance from Junction to Ambient (RJA) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7, “High
Effective Thermal Conductivity Test Board for Leaded
Surface Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors, such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT-23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
EXAMPLE 5-2:
5.3.2
JUNCTION TEMPERATURE
ESTIMATE
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below.
EXAMPLE 5-3:
TJ = TJRISE + TA(MAX)
TJ = 49.4°C
Maximum Package Power Dissipation Examples at
+40°C Ambient Temperature
SOT-23 (256°C/Watt = RJA)
PD(MAX) = (125°C – 40°C)/256°C/W
PD(MAX) = 332 mW
2 x 3 8-Lead DFN (70°C/Watt = RJA)
PD(MAX) = (125°C – 40°C)/70°C/W
PD(MAX) = 1214 mW
5.4
Voltage Reference
The MCP1755/MCP1755S can be used not only as a
regulator, but also as a low quiescent current voltage
reference. In many microcontroller applications, the initial
accuracy of the reference can be calibrated using
production test equipment or by using a ratio
measurement. When the initial accuracy is calibrated, the
thermal stability and line regulation tolerance are the only
errors introduced by the MCP1755/MCP1755S LDO.
The low-cost, low quiescent current and small ceramic
output capacitor are all advantages when using the
MCP1755/MCP1755S as a voltage reference.
Ratio Metric Reference
68 µA Bias
CIN
1 µF
PIC®
Microcontroller
MCP1755S
VIN
VOUT
GND
COUT
1 µF
VREF
ADO
AD1
Bridge Sensor
FIGURE 5-2:
Using the MCP1755/
MCP1755S as a Voltage Reference.
TJ(RISE) = PTOTAL x RJA
TJRISE = 151.8 mW x 62°C/Watt
TJRISE = 9.4°C
DS20005160B-page 22
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
5.5
Pulsed Load Applications
For some applications, there are pulsed load current
events that may exceed the specified 300 mA
maximum specification of the MCP1755/MCP1755S.
The internal current limit of the MCP1755/MCP1755S
will prevent high peak load demands from causing nonrecoverable damage. The 300 mA rating is a maximum
average continuous rating. As long as the average
current does not exceed 300 mA, higher pulsed load
currents can be applied to the MCP1755/MCP1755S.
The typical foldback current limit for the MCP1755/
MCP1755S is 350 mA (TA = +25°C).
2012-2021 Microchip Technology Inc.
DS20005160B-page 23
MCP1755/MCP1755S
NOTES:
DS20005160B-page 24
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
3-Lead SOT-223 (MCP1755S only)
Part Number
XXXXXXX
XXXYYWW
NNN
Example
First Line
Code
MCP1755S-1802E/DB
1755S18
MCP1755ST-1802E/DB
1755S18
MCP1755S-3302E/DB
1755S33
MCP1755ST-3302E/DB
1755S33
MCP1755S-5002E/DB
1755S50
MCP1755ST-5002E/DB
1755S50
5-Lead SOT-223 (MCP1755 only)
Example
Part Number
First Line
Code
MCP1755T-1802E/DC
175518
MCP1755T-3302E/DC
175533
MCP1755T-5002E/DC
175550
5-Lead SOT-23 (MCP1755 only)
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
175518
EDCY1240
256
Example
Part Number
XXNN
1755S18
EDBY1240
256
Code
MCP1755T-1802E/OT
2SNN
MCP1755T-3302E/OT
3CNN
MCP1755T-5002E/OT
3DNN
MCP1755T-3302E/OTV01
3CNN
MCP1755T-3302E/OTVAO
3CNN
2S25
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3)
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.
2012-2021 Microchip Technology Inc.
DS20005160B-page 25
MCP1755/MCP1755S
Package Marking Information (Continued)
Example
8-Lead DFN (2x3)
Part Number
MCP1755-1802E/MC
DS20005160B-page 26
First Line
Code
ALZ
MCP1755T-1802E/MC
ALZ
MCP1755-3302E/MC
AKA
MCP1755T-3302E/MC
AKA
MCP1755-5002E/MC
AKB
MCP1755T-5002E/MC
AKB
MCP1755S-1802E/MC
AMA
MCP1755ST-1802E/MC
AMA
MCP1755S-3302E/MC
AMB
MCP1755ST-3302E/MC
AMB
MCP1755S-5002E/MC
AMC
MCP1755ST-5002E/MC
AMC
ALZ
240
256
2012-2021 Microchip Technology Inc.
MCP1755/MCP1755S
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
D
b2
E1
E
3
2
1
e
e1
A2
A
b
c
φ
L
A1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI/HDGV
0,//,0(7(56
0,1
120
0$;
1
/HDG3LWFK
H
%6&
2XWVLGH/HDG3LWFK
H
2YHUDOO+HLJKW
$
±
±
6WDQGRII
$
±
0ROGHG3DFNDJH+HLJKW
$
2YHUDOO:LGWK
(
0ROGHG3DFNDJH:LGWK
(
2YHUDOO/HQJWK
'
/HDG7KLFNQHVV
F
/HDG:LGWK
E
7DE/HDG:LGWK
E
)RRW/HQJWK
/
±
±
/HDG$QJOH
±
%6&
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(
工商网监
湘ICP备2023018690号
