MCP1790/MCP1791
70 mA, High Voltage Regulator
Features
General Description
• 48V (43.5V ±10%) load dump protected for 2.4V.
Boldface type applies for junction temperatures, TJ (Note 5) of -40°C to +125°C.
Parameters
Input Operating Voltage
Input Quiescent Current
Symbol
Min
Typ
Max
Units
Conditions
VIN
6.0
—
30.0
V
+48VDC Load Dump Peak
< 500 ms
Iq
—
70
130
µA
IL = 0 mA
Input Quiescent Current for SHDN
Mode
ISHDN
—
10
25
µA
SHDN = GND
Ground Current
IGND
—
110
210
µA
IL = 70 mA
Maximum Output Current
IOUT
70
—
—
mA
Line Regulation
ΔVOUT/
(VOUTXΔVIN)
—
±0.0002
±0.05
%/V
Load Regulation
ΔVOUT/VOUT
-0.45
±0.2
0.45
%
IOUT = 1 mA to 70 mA
(Note 3)
IOUT_SC
—
VR/10
—
A
RLOAD < 0.1Ω,
Peak Current
VOUT
VR-2.5%
VR
VR+2.5%
V
—
TCVOUT
—
65
—
ppm/°C
VON
—
5.5
6.0
V
Output Peak Short Circuit Current
Output Voltage Regulation
VOUT Temperature Coefficient
Input Voltage to Turn On Output
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
6.0V < VIN < 30V
Note 9
Rising VIN
The minimum VIN, VIN(MIN) must meet two conditions: VIN ≥ 6.0V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage.
Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum 165°C rating. Sustained
junction temperatures above 165°C can impact the device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
ambient temperature is not significant.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VR + VDROPOUT(MAX).
Sustained junction temperatures above 165°C can impact the device reliability.
The Short Circuit Recovery Time test is done by placing the device into a short circuit condition and then removing the
short circuit condition before the device die temperature reaches 125 °C. If the device goes into thermal shutdown, then
the Short Circuit Recovery Time will depend upon the thermal dissipation properties of the package and circuit board.
TCVOUT = (VOUT-HIGH - VOUT-LOW) *10^6/(VR * ΔTemperature), VOUT-HIGH = highest voltage measured over the temperature
range. VOUT-LOW = lowest voltage measured over the temperature range.
DS22075B-page 4
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), (Note 1), IOUT = 1 mA,
COUT = 4.7 µF (X7R Ceramic), CIN = 4.7 µF (X7R Ceramic), TA = +25°C, SHDN > 2.4V.
Boldface type applies for junction temperatures, TJ (Note 5) of -40°C to +125°C.
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Short Circuit Foldback Voltage Corner
VFOLDBACK
—
4.2
—
V
VR = 5.0V
Falling VOUT, RLOAD < 0.1Ω
—
3.0
—
V
VR = 3.3V
Falling VOUT, RLOAD < 0.1Ω
—
2.7
—
V
VR = 3.0V
Falling VOUT, RLOAD < 0.1Ω
—
105
—
mA
VOUT ~= 0V,
RLOAD < 0.1Ω,
VR = 5.0V (Note 2)
—
99
—
mA
VR = 3.3V (Note 2)
—
99
—
mA
VR = 3.0V (Note 2)
Short Circuit Foldback Current
VOVER
—
0.10
—
% VOUT
Dropout Voltage
VDROPOUT
—
700
1300
mV
IOUT = 70 mA, (Note 6)
Dropout Current
IOUT = 0 mA
IDO
—
130
—
µA
VR = 5.0V, VIN = 4.500V
—
75
—
µA
VR = 3.3V, VIN = 4.500V
—
75
—
µA
VR = 3.0V, VIN = 4.500V
Startup Voltage Overshoot
VIN = 0V to 6.0V
Shutdown Input
Logic High Input
VSHDN-HIGH
2.4
—
VIN(MAX)
V
—
Logic Low Input
VSHDN-LOW
0
—
0.8
V
—
SHDNILK
—
—
0.100
3.0
0.500
5.0
µA
SHDN = GND
SHDN = 6V
PWRGD Input Voltage Operating
Range
VPWRGD_VIN
2.8
—
—
V
—
PWRGD Threshold Voltage
(Referenced to VOUT)
VPWRGD_TH
88
90
92
%VOUT
PWRGD Threshold Hysteresis
VPWRGD_HYS
1.0
2.0
3.0
%VOUT
PWRGD Output Voltage LOW
VPWRGD_L
—
0.2
0.4
V
Shutdown Input Leakage Current
Power Good Characteristics
PWRGD Output Sink Current
PWRGD Leakage
PWRGD Time Delay
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Falling Edge of VOUT
Rising Edge of VOUT
IPWRGD SINK = 5.0 mA,
VOUT = 0V
IPWRGD_L
5.0
—
—
mA
VPWRGD 2.4V.
Boldface type applies for junction temperatures, TJ (Note 5) of -40°C to +125°C.
Parameters
Detect Threshold to PWRGD Active
Time Delay
Symbol
Min
Typ
Max
Units
TVDET-PWRG
—
235
—
µs
VOUT = VPWRGD_TH +
100 mV to VPWRGD_TH 100 mV
TOR
—
200
—
µs
SHDN = GND to VIN,
VOUT = GND to 95% VR,
COUT = 1.0 µF
TSHDN_PG
—
400
—
ns
SHDN = VIN to GND,
COUT = 1.0 µF
eN
—
1.2
—
(µV/√Hz)
IOUT = 50 mA, f = 1 kHz
dB
VIN = 7.0V, CIN = 0 µF,
IOUT = 10 mA,
VINAC = 400 mVpp
D
Conditions
AC Performance
Output Delay from SHDN
PWRGD Delay from SHDN
Output Noise
Power Supply Ripple Rejection Ratio
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Short Circuit Recovery Time
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
PSRR
—
90
—
f = 100 Hz
—
75
—
f = 1 kHz, VR = 5.0V
—
80
—
TSD
—
157
—
ΔTSD
—
20
—
°C
Falling Temperature
tTHERM
—
0
—
ms
(Note 8)
f = 1 kHz, VR = < 5.0V
°C
Rising Temperature
The minimum VIN, VIN(MIN) must meet two conditions: VIN ≥ 6.0V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage.
Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum 165°C rating. Sustained
junction temperatures above 165°C can impact the device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
ambient temperature is not significant.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VR + VDROPOUT(MAX).
Sustained junction temperatures above 165°C can impact the device reliability.
The Short Circuit Recovery Time test is done by placing the device into a short circuit condition and then removing the
short circuit condition before the device die temperature reaches 125 °C. If the device goes into thermal shutdown, then
the Short Circuit Recovery Time will depend upon the thermal dissipation properties of the package and circuit board.
TCVOUT = (VOUT-HIGH - VOUT-LOW) *10^6/(VR * ΔTemperature), VOUT-HIGH = highest voltage measured over the temperature
range. VOUT-LOW = lowest voltage measured over the temperature range.
DS22075B-page 6
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
TEMPERATURE SPECIFICATIONS
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Specified Temperature Range
TJ
-40
—
+125
°C
—
Operating Temperature Range
TJ
-40
—
+125
°C
—
Storage Temperature Range
TA
-55
—
+150
°C
—
Thermal Resistance, 3LD DDPAK
θJA
θJC
—
31.4
3
—
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
Thermal Resistance, 3LD SOT-223
θJA
θJC
—
62
15
—
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
Thermal Resistance, 5LD DDPAK
θJA
θJC
—
31.4
3
—
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
Thermal Resistance, 5LD SOT-223
θJA
θJC
—
62
15
—
°C/W
EIA/JEDEC JESD51-751-7
4 Layer Board
Temperature Ranges
Package Thermal Resistances
© 2010 Microchip Technology Inc.
DS22075B-page 7
MCP1790/MCP1791
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 uF Ceramic (X7R), CIN = 10.0 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C,
VIN = 6.0V, RPWRGD_PULLUP = 10 kΩ To VOUT, VSHDN = VIN, and device is MCP1790.
Note: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired
junction temperature. The test time is small enough such that the rise in Junction Temperature over the Ambient temperature is not
significant.
120.00
VOUT = 5.0V
IOUT = 0 µA
40
Quiescent Current (µA)
PWRGD Time Delay (µs)
50
VIN = 10V,15V,25V,30V
30
VIN = 6V
20
10
0
VIN = 6V
IOUT = 0µA
100.00
VOUT = 3.3V
80.00
60.00
VOUT = 5.0V
40.00
20.00
0.00
-45
-20
5
30
55
80
105
130
-45
-20
Temperature (°C)
140
VOUT = 3.3V
IOUT = 0 µA
120
+90°C
80
+25°C
0°C
60
55
80
105
130
VOUT = 3.3V
120
+130°C
100
30
FIGURE 2-4:
Quiescent Current vs.
Junction Temperature.
GND Current (µA)
Quiescent Current (µA)
140
5
Junction Temperature (°C)
FIGURE 2-1:
Power Good Time Delay vs.
Temperature (MCP1791).
-45°C
40
20
0
100
VOUT = 3.0V
VOUT = 5.0V
80
60
40
20
0
0
5
10
15
20
25
30
35
0
10
20
Input Voltage (V)
FIGURE 2-2:
Voltage.
Quiescent Current vs. Input
FIGURE 2-5:
Current.
120
60
70
Ground Current vs. Load
VREG = 3.0V
VSHDN = 0V
20
ISHDN (µA)
60
50
24
+130°C
+90°C
+25°C
0°C
-45°C
80
40
28
VOUT = 5.0V
IOUT = 0 µA
100
30
Load Current (mA)
140
Quiescent Current (µA)
VOUT = 3.0V
16
40
8
20
4
0
VIN = 10V, 30V
12
VIN = 6.0V
0
0
5
10
15
20
25
30
35
-45
-20
Input Voltage (V)
FIGURE 2-3:
Voltage.
DS22075B-page 8
Quiescent Current vs. Input
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-6:
ISHDN vs Temperature.
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
Note: Unless otherwise indicated, COUT = 4.7 uF Ceramic (X7R), CIN = 10.0 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C,
VIN = 6.0V, RPWRGD_PULLUP = 10 kΩ To VOUT, VSHDN = VIN, and device is MCP1790.
VOUT = 3.3V
VIN = 6V to 30V
0.004
0 mA
10 mA
0.002
Output Voltage (V)
Line Regulation (%/V)
0.006
0.000
-0.002
70 mA
-0.004
-0.006
-45
-20
5
30
55
80
105
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
4.94
VOUT = 5.0V
VIN = 6.3V
-45°C
0
130
10
0°C
20
Temperature (°C)
FIGURE 2-7:
Temperature.
Dropout Voltage (V)
Line Regulation (%/V)
FIGURE 2-10:
Current.
VOUT = 5.0V
VIN = 6V to 30V
0.004
0 mA
0.002
0.000
30 mA
-0.002
70 mA
-0.004
-0.006
-45
-20
5
30
55
80
105
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
130
Dropout Voltage (V)
Load Regulation (%)
VREG=5.0V
VREG=3.3V
-0.20
VREG=3.0V
-0.25
-0.30
-45
-20
5
30
55
80
105
Load Regulation vs.
© 2010 Microchip Technology Inc.
70
+130°C
10
20
+25°C
0°C
-45°C
30
40
50
60
70
130
Dropout Voltage vs. Load
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOUT = 5.0V
70 mA
50 mA
30 mA
1 mA
10 mA
-45
-20
Temperature (°C)
FIGURE 2-9:
Temperature.
60
+90°C
FIGURE 2-11:
Current.
-0.10
-0.15
50
VOUT = 5.0V
0
ILOAD = 1 mA to 70 mA
-0.05
40
Load Current (mA)
Line Regulation vs.
0.00
30
+130°C
Output Voltage vs. Load
Temperature (°C)
FIGURE 2-8:
Temperature.
+90°C
Load Current (mA)
Line Regulation vs.
0.006
+25°C
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-12:
Temperature.
Dropout Voltage vs.
DS22075B-page 9
MCP1790/MCP1791
Note: Unless otherwise indicated, COUT = 4.7 uF Ceramic (X7R), CIN = 10.0 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C,
130
ROUT < 0.1Ω
125
120
VOUT = 5.0V
115
PSRR (dB)
Short Circuit Current (mA)
VIN = 6.0V, RPWRGD_PULLUP = 10 kΩ To VOUT, VSHDN = VIN, and device is MCP1790.
VOUT = 3.3V
110
105
VOUT = 3.0V
100
6
10
14
18
22
26
30
Input Voltage (V)
FIGURE 2-13:
Input Voltage.
Short Circuit Current vs
10.00
Noise (μV/Hz)
VR=5.0V
100
1000
FIGURE 2-16:
Power Supply Ripple
Rejection vs. Frequency.
IOUT=50mA
1.00
VR=3.3V
0.10
0.01
0.00
0.01
0.1
1
10
Frequency (kHz)
100
1000
FIGURE 2-14:
Output Noise Voltage
Density vs. Frequency.
-20
-30
-40
PSRR (dB)
-20
VR=5.0V
-30
VIN=7.0V
-40
VINAC = 400 mV p-p
-50
CIN=0 μF
-60
IOUT=10 mA
-70
-80
-90
-100
-110
-120
0.01
0.1
1
10
Frequency (kHz)
-50
-60
FIGURE 2-17:
(MCP1791).
Startup from VIN
FIGURE 2-18:
(MCP1791).
Startup from Shutdown
VR=3.3V
VIN=7.0V
VINAC = 400 mV p-p
CIN=0 μF
IOUT=10 mA
-70
-80
-90
-100
-110
0.01
0.1
1
10
Frequency (kHz)
100
FIGURE 2-15:
Power Supply Ripple
Rejection vs. Frequency.
DS22075B-page 10
1000
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
Note: Unless otherwise indicated, COUT = 4.7 uF Ceramic (X7R), CIN = 10.0 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C,
VIN = 6.0V, RPWRGD_PULLUP = 10 kΩ To VOUT, VSHDN = VIN, and device is MCP1790.
Dynamic Line Response.
FIGURE 2-22:
Output Voltage (V)
FIGURE 2-19:
Dynamic Load Response.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT = 3.3V
VOUT = 3.0V
0
20
40
60
80
100
120
140
Output Current (mA)
FIGURE 2-20:
Dynamic Line Response.
FIGURE 2-23:
Short Circuit Response.
Output Voltage (V)
7
VOUT = 5.0V
VIN = 6.3V
6
5
4
3
2
1
0
0
20
40
60
80
100
120
140
Output Current (mA)
FIGURE 2-21:
Dynamic Load Response.
© 2010 Microchip Technology Inc.
FIGURE 2-24:
Short Circuit Response.
DS22075B-page 11
MCP1790/MCP1791
Note: Unless otherwise indicated, COUT = 4.7 uF Ceramic (X7R), CIN = 10.0 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C,
Startup Ground Current (µA)
VIN = 6.0V, RPWRGD_PULLUP = 10 kΩ To VOUT, VSHDN = VIN, and device is MCP1790.
90
80
70
60
50
40
30
20
10
0
IOUT = 1 mA
VOUT = 5.0V
VOUT = 3.3V
0
1
2
3
4
5
6
7
Input Voltage (V)
FIGURE 2-25:
DS22075B-page 12
Startup Ground Current.
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1 and Table 3-2.
TABLE 3-1:
Pin No.
SOT-223-3
MCP1790 PIN FUNCTION TABLE
Pin No.
DDPAK-3
Symbol
Function
1
1
VIN
2,Tab
2,Tab
GND
Ground Terminal
3
3
VOUT
Regulated Output Voltage
TABLE 3-2:
Unregulated Supply Voltage
MCP1791 PIN FUNCTION TABLE
Pin No.
SOT-223-5
Pin No.
DDPAK-5
Symbol
1
1
SHDN
2
2
VIN
3
3
GND
Ground Terminal
4
4
VOUT
Regulated Output Voltage
5
5
PWRGD
Tab
Tab
—
—
—
N/C
3.1
Function
Shutdown Input
Unregulated Supply Voltage
Power Good Open-Drain Output
Connected to Ground
No connection
Input Voltage Supply (VIN)
3.4
Shutdown (SHDN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the regulator or the input
source is a battery, it is recommended that an input
capacitor is used. A typical input capacitance value of
1 µF to 10 µF should be sufficient for most applications.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high-frequency.
The SHDN pin is an active-low input signal that turns
the regulator output voltage on and off. When the
SHDN input is at a logic-high level, the regulator output
voltage is enabled. When the SHDN input is pulled to a
logic-low level, the regulator output voltage is disabled.
When the SHDN input is pulled low, the PWRGD output
signal also goes low and the regulator enters a low
quiescent current shutdown state where the typical quiescent current is 10 µA. The SHDN pin is bonded to VIN
in the 3-pin versions of the regulator. See Table 4-1.
3.2
3.5
Ground (GND)
Tie GND to the negative side of the output and the
negative side of the input capacitor. Only the regulator
bias current flows out of this pin; there is no high
current. The regulator output regulation is referenced to
this pin. Minimize voltage drops between this pin and
the negative side of the load.
3.3
Regulated Output Voltage (VOUT)
The VIN pin is the regulated output voltage of the
regulator. A minimum output capacitance of 1.0 µF
tantalum, 1.0 µF electrolytic, or 4.7 µF ceramic is
required for stability. The MCP1790 is stable with
ceramic, tantalum, and electrolytic capacitors. See
Section 4.7 “Output Capacitor” for output capacitor
selection guidance.
Power Good Output (PWRGD)
The PWRGD pin is an open-drain output signal that is
used to indicate when the regulator output voltage is
within 90% (typically) of its nominal regulation value.
The PWRGD threshold has a typical hysteresis value
of 2%. The typical PWRGD delay time due to VOUT
rising above 90% +3% (maximum hysteresis) is 30 µs.
The typical PWRGD delay time due to VOUT falling
below 90% is 235 µs. These delay times are internally
fixed.
3.6
Exposed Pad (EP)
The DDPAK package has an exposed tab on the
package. A heat sink may be mounted to the tab to aid
in the removal of heat from the package during
operation.
The exposed tab or pad of all of the available packages
is at the ground potential of the regulator.
© 2010 Microchip Technology Inc.
DS22075B-page 13
MCP1790/MCP1791
4.0
DEVICE OVERVIEW
4.4
The MCP1790/MCP1791 are high input voltage
regulators capable of providing up to 70 mA of current
at output voltages up to 5.0V. The devices have an
input voltage operating range from 6.0V to 30V, 48V
absolute max. The MCP1790 devices are 3-pin devices
consisting of VIN, VOUT and GND. The MCP1791
devices have 5 or more pins which add Shutdown and
Power-Good functions to the MCP1790 device.
4.1
4.4.1
While not necessary, good design practice dictates
adding an external transient suppressor, between VBB
and ground, with a low value resistor in series with the
battery supply and the VIN pin, to limit currents and voltages due to electrical transients. Because of the regulator startup current, the resistor value should be less
than (VBAT -6V) / 200 mA. For a 12V battery voltage,
the resistor value should be less than 30 ohms.
Startup
Thermal Shutdown
The regulator has a thermal shutdown. If the thermal
protection circuit detects an over temperature
condition, typically 157°C junction temperature, the
regulator will shut down. The device will recover from
the thermal shutdown when the junction temperature
drops to 137°C (typical).
4.3
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
The regulator is capable of withstanding a 48V
(43.5V ±10) load dump transient for a duration of
500 ms and a repetition rate of 30 seconds
(ES-XW7T-1A278-AC, Ford Motor Company, Test
Pulse G Loaded).
In the start phase, the device must see at least 6.0V to
initiate operation during power up. In the Power-down
mode, the VIN monitor will be turned off.
4.2
External Protection
4.4.2
REVERSE BATTERY PROTECTION
An external reverse battery blocking diode may be
used to provide polarity protection.
Regulator Output Voltage
The MCP1790/MCP1791 regulators are available in
fixed output voltage configurations. The standard
output voltages are 3.0V, 3.3V, and 5.0V.
VIN
T1
T2
Monitoring
Temperature
Soft Start
Reference
Voltage
T1
en
Error Amplifier
T2
Temp
Sensor
+
Short Circuit
Protection
Logical Block
VOUT
en
510k
VIN
490k
Delay
SHDN
Monitoring VOUT
Delay
PWRGD
Monitoring VIN
GND
FIGURE 4-1:
DS22075B-page 14
MCP1790/MCP1791 Block Diagram.
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
4.5
Shutdown (SHDN)
4.6
The MCP1791 has a Shutdown (SHDN) input signal
that enables or disables the regulator output voltage.
When the SHDN input signal is greater than 2.40V, the
regulator output voltage is enabled. Note that the
regulator output may still be disabled by the
undervoltage lockout incorporated within the VIN
circuitry.
The value of the SHDN signal to put the regulator into
Shutdown mode is ≤0.8V. The SHDN pin is pulled low
by an internal resistor. If the SHDN pin is left floating,
the internal pull-down resistor will put the regulator into
shutdown mode.
When the SHDN input signal is pulled to a logic-low, the
PWRGD output signal will also go low and the regulator
will enter a low quiescent current state where the
typical quiescent current is 10 µA. There is a short time
delay (approximately 400 ns) when the SHDN input
signal transitions from high-to-low to prevent signal
noise from disabling the regulator. The SHDN pin will
ignore low-going pulses that are up to 400 ns in pulse
width. If the SHDN input is pulled low for more than
400 ns, the regulator will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the SHDN input signal.
On the rising edge of the SHDN input, the shutdown
circuitry will have a 100 µs delay before allowing the
regulator output to turn on. This delay helps to reject
any false turn-on signals or noise on the SHDN input
signal. After the 100 µs delay, the regulator will start
charging the output capacitor as the regulator output
voltage rises from 0V to its final regulated value. The
charging current will be limited by the short circuit
current value of the device. If the SHDN input signal is
pulled low during the 100 µs delay period, the timer will
be reset and the delay time will start over again on the
next rising edge of the SHDN input. The total time from
the SHDN input going high (turn-on) to the regulator
output being in regulation shall typically be 200 µs
(100 µs + 100 µs) for a CLOAD = 1.0 µF.
CLOAD CHARGING TIME
TOR
400 ns (typ)
100 µs
Low Voltage Shutdown
The MCP1790/MCP1791 incorporates a Low Voltage
Shutdown circuit that turns off the output of the
regulator whenever the input voltage, VIN, is below the
specified turn off voltage, VOFF. When the input voltage
(VB) drops below the differential needed to provide
stable regulation, the output voltage (VREG) shall track
the input down to approximately +4.00V. The regulator
will turn off the output at this point.
The output will turn on when VIN rises above the VON
value specified in the data sheet. This feature is
independent of the Shutdown input signal (SHDN) that
is provided for external regulator control. If the SHDN
input signal is active (LOW), then the output of the
regulator shall be disabled regardless of input voltage.
TABLE 4-1:
VIN
4.7
SHUTDOWN LOGIC
SHDN
VOUT
< VOFF
L
OFF
< VOFF
H
OFF
> VON
L
OFF
> VON
H
ON
Output Capacitor
The MCP1790/MCP1791 requires a minimum output
capacitance of 1 µF tantalum or electrolytic
capacitance. The minimum value for ceramic
capacitors is 4.7 µF. The regulator is stable for all three
types of capacitors from 4.7 µF to 1000 µF (see
Figure 4-3). The MCP1790/MCP1791 regulator may
be used with a 1 µF ceramic output capacitor if a
0.300Ω resistor is placed in series with the capacitor.
The low ESR and corresponding pole of the ceramic
capacitor causes the instability below 4.7 µF.
The Equivalent Series Resistance (ESR) of the output
capacitor must be no greater than 3 ohms. The output
capacitor should be located as close to the regulator
output as is practical. Ceramic materials X7R and X5R
have low temperature coefficients and are
recommended because of their size, cost and
environmental robustness qualities.
100 µs
SHDN
VOUT
CLOAD = 1.0 µF
FIGURE 4-2:
Diagram.
Shutdown Input Timing
© 2010 Microchip Technology Inc.
DS22075B-page 15
MCP1790/MCP1791
4.8
Output Current and Current
Limiting
The MCP1790/MCP1791 devices are tested and
ensured to supply a minimum of 70 mA of output
current.
The MCP1790/MCP1791 also incorporate an output
current limit foldback. When the regulator is in an
overcurrent condition, VOUT will decrease with
increasing load. When VOUT falls below 30% (typical)
of VR, the output current will start to fold back. The
output current will fold back to less than 100 mA
(typical) when VOUT is near 0 volts.
The 5.0V regulator has an overload current limiting of
approximately 120 mA. If VREG is lower than 3.5V, IOUT
will start to fold back and decrease along with VREG
until IOUT is less than 105 mA and VREG is near 0 volts.
The 3.3V regulator has an overload current limiting of
approximately 130 mA. If VREG is lower than 2.5V, IOUT
will start to fold back and decrease along with VREG
until IOUT is less than 99 mA and VREG is near 0 volts.
ESR Curves
10
Instable
Stable only
ESR [ohm]
1
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Instable
0.1
0.01
Instable
0.001
0.1
1
10
100
1000
Load Capacitor [uF]
FIGURE 4-3:
DS22075B-page 16
ESR Curves for Load Capacitor Selection.
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
4.9
Power Good Output (PWRGD)
The MCP1791 has an open-drain Power Good
(PWRGD) output signal capable of sinking a minimum
of 5.0 mA of current while maintaining a PWRGD
output voltage of 0.4V or less.
VPWRGD_TH
VOUT
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold (VPWRGD_TH) level
by an amount equal to the power good hysteresis value
((VPWRGD_HYS), typically 2% of VR. Once this threshold
has been exceeded, the power good output signal will
be pulled high by an external pull-up resistor, indicating
that the output voltage is stable and within regulation
limits.
If the output voltage of the LDO falls below the power
good threshold (VPWRGD_TH) level, the power good
output will transition low. The power good circuitry has
a 235 µs delay when detecting a falling output voltage,
which helps to increase noise immunity of the power
good output and avoid false triggering of the power
good output during fast output transients. See
Figure 4-4 for power good timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low within
400 ns typical, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-5.
The PWRGD output may be pulled up to either VIN or
VOUT. When pulled to VOUT, the PWRGD output will
sink very little current during shutdown. When PWRGD
is pulled up to VIN , the PWRGD output will sink current
during shutdown. That is because VOUT is 0 during
shutdown while VIN is still active. When the PWRGD
output is pulled to VIN , the PWRGD output signal will
track VIN at startup until the threshold of the PWRGD
circuitry has been reached and the PWRGD circuitry
pulls the signal back low. Therefore, when pulling
PWRGD to VIN instead of VOUT, the designer must be
aware of the PWRGD signal going high while the input
voltage is rising at startup. Pulling PWRGD to VOUT
removes the startup pulse.
© 2010 Microchip Technology Inc.
VPWRGD_HYS
TPG
30 µs
VON
TVDET_PWRGD
235 µs
PWRGD
VOL
FIGURE 4-4:
Power Good Timing.
CLOAD = 1.0 ΜF
VIN
TOR
100 µs
SHDN
100 µs
TPG
VOUT
PWRGD
FIGURE 4-5:
Shutdown.
Power Good Timing from
DS22075B-page 17
MCP1790/MCP1791
5.0
APPLICATION CIRCUITS/
ISSUES
5.1
Typical Application
The MCP1790/MCP1791 is most commonly used as a
voltage regulator. It is a high voltage input capability
and thermal protection make it ideal for automotive and
24V industrial applications.
MCP1791
1
VIN
5
5
4
FIGURE 5-1:
PWRGD
10 kΩ
CIN
1 µF
Ceramic
24 VDC
5.1.1
3
2
1N4002
+
VOUT
+
COUT
4.7 µF Ceramic
5V@70 mA
Typical Application.
APPLICATION INPUT CONDITIONS
Package Type = SOT-223-5
EQUATION 5-2:
T J ( MAX ) = P TOTAL × Rθ JA + T AMAX
TJ(MAX)
=
Maximum continuous junction
temperature
PTOTAL
=
Total device power dissipation
RθJA
=
Thermal resistance from junction
to ambient
TAMAX
=
Maximum ambient temperature
The maximum power dissipation capability for a
package can be calculated given the junction-toambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package maximum
internal power dissipation.
EQUATION 5-3:
( T J ( MAX ) – T A ( MAX ) )
P D ( MAX ) = --------------------------------------------------Rθ JA
PD(MAX) = Maximum device power
dissipation
TJ(MAX)
=
Maximum continuous junction
temperature
VIN maximum = 24V
TA(MAX)
=
Maximum ambient temperature
VOUT typical = 5.0V
RθJA
=
Thermal resistance from junction
to ambient
Input Voltage Range = 8V to 24V
IOUT = 70 mA maximum
5.2
Power Calculations
5.2.1
POWER DISSIPATION
The internal power dissipation of the MCP1790/
MCP1791 is a function of input voltage, output voltage
and output current. The power dissipation, as a result
of the quiescent current draw, is so low, it is
insignificant (70.0 µA x VIN). The following equation
can be used to calculate the internal power dissipation
of the LDO.
EQUATION 5-4:
T J ( RISE ) = P TOTAL × Rθ JA
TJ(RISE)
=
Rise in device junction
temperature over the ambient
temperature
PTOTAL
=
Total device power dissipation
RθJA
=
Thermal resistance from
junction-to-ambient
EQUATION 5-1:
P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) )
PLDO
=
LDO Pass device internal power
dissipation
VIN(MAX)
=
Maximum input voltage
VOUT(MIN)
=
LDO minimum output voltage
The maximum continuous operating junction
temperature specified for the MCP1790/MCP1791 is
+125°C. To estimate the internal junction temperature
of the MCP1790/MCP1791, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA). The thermal resistance
from junction to ambient for the SOT-223-5 package is
estimated at 62°C/W.
DS22075B-page 18
EQUATION 5-5:
T J = T J ( RISE ) + T A
TJ
=
Junction Temperature
TJ(RISE)
=
Rise in device junction
temperature over the ambient
temperature
TA
=
Ambient temperature
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
5.3
Power Dissipation Example
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation, as a result of ground current, is small
enough to be neglected.
5.3.1
5.3.1.2
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below.
TJ = TJRISE + TA(MAX)
TJ = 99.2°C
POWER DISSIPATION EXAMPLE
Package:
5.3.1.3
Package Type = SOT-223-5
Input Voltage:
VIN = 8V to 24V
LDO Output Voltages and Currents:
Maximum Ambient Temperature:
PD(MAX) = (125°C - 40°C) / 62°C/W
PD(MAX) = 1.371 Watts
DDPAK-5 (32°C/Watt = Rθ JA)
PD(MAX) = (125°C - 40°C) / 32°C/W
TA(MAX) = +40°C
PD(MAX) = 2.656 Watts
Internal Power Dissipation:
Internal Power dissipation is the product of the LDO
output current times the voltage across the LDO
(VIN to VOUT).
PLDO(MAX) = (VIN(MAX) - VOUT(MIN)) x IOUT(MAX)
PLDO = (24V - (0.98 x 5.0V)) x 50 mA
PLDO = 955 milli-Watts
5.3.1.1
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The
thermal resistance from junction to ambient (RθJA) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface mount packages.
The EIA/JEDEC specification is JESD51-7, “High
Effective Thermal Conductivity Test Board for Leaded
Surface Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors, such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application”, (DS00792), for more information
regarding this subject.
Maximum Package Power
Dissipation at +40°C Ambient
Temperature
SOT-223-5 (62°C/Watt = RθJA)
VOUT = 5.0V
IOUT = 50 mA
Junction Temperature Estimate
5.4
Pulsed Load Applications
For some applications, there are pulsed load current
events that may exceed the specified 70 mA maximum
specification of the MCP1790/MCP1791. The internal
current foldback feature of the MCP1790/MCP1791 will
prevent high peak load demands from causing
non-recoverable damage. The Current Foldback
feature of the device will limit the output voltage and
output current during pulsed applications. As the
current rises above the foldback current threshold, the
output voltage will decrease.
TJ(RISE) = PTOTAL x RqJA
TJRISE = 955 milli-Watts x 62°C/Watt
TJRISE = 59.2°C
© 2010 Microchip Technology Inc.
DS22075B-page 19
MCP1790/MCP1791
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
3-Lead DDPAK (MCP1790)
XXXXXXXXX
XXXXXXXXX
YYWWNNN
1
2
MCP1790
e3
50EEB^^
1005256
3
1
3-Lead SOT-223 (MCP1790)
XXXXXXX
XXXYYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS22075B-page 20
Example:
2
3
Example:
179050
EDB1005
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2010 Microchip Technology Inc.
MCP1790/MCP1791
6.1
Package Marking Information (Continued)
5-Lead DDPAK (Fixed) (MCP1791)
Example:
XXXXXXXXX
XXXXXXXXX
YYWWNNN
MCP1791
e3
50EET^^
1005256
1 2 3 4 5
1 2 3 4 5
5-Lead SOT-223 (MCP1791)
XXXXXXX
XXXYYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
179150
EDC1005
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2010 Microchip Technology Inc.
DS22075B-page 21
MCP1790/MCP1791
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