MCP1792T-5002H/DB

MCP1792/3 100 mA High-Voltage Automotive LDO Features Description • AEC-Q100 with Grade 0 and PPAP Capable • Wide Input Voltage Range: 4.5V to 55V - Up to 70V transient - Under Voltage Lock Out (UVLO): 2.7V typical • Extended Operating Temperature Range: -40°C to +150°C • Standard Output Regulated Voltages (VR): 3.3V and 5.0V (Note) - Tolerance  2.0% typical • Low Quiescent Supply Current: 25 µA typical • Low Shutdown Quiescent Supply Current: 2 µA typical • Output Current Capability: 100 mA typical - Short Circuit Current Foldback Protection - Thermal Shutdown Protection: 175°C • Stable with Ceramic Output Capacitor: 2.2 µF • High PSRR: - 80 dB @ 100 Hz typical - 55 dB @ 100 kHz typical • Available in the following packages: - 3-Lead SOT-223 (MCP1792) - 3-Lead SOT-23A (MCP1792) - 5-Lead SOT-223 (MCP1793) - 5-Lead SOT-23 (MCP1793) The MCP1792/3 family devices are high-voltage, low dropout (LDO) regulators, capable of generating 100 mA output current. The input voltage range of 4.5V to 55V makes it suitable in 12V to 48V power rails and in high-voltage battery packs. A low UVLO at shutdown of 2.4V makes it adequate for cold cranking conditions in automotive applications. The MCP1792/3 comes in two standard fixed output voltage versions: 3.3V and 5.0V. The regulator output is stable with 2.2 µF ceramic capacitors. The device is protected from short-circuit events by the current foldback function and from overheating by means of thermal shutdown protection. The MCP1792 is the 3-lead version of the MCP1792/3 device family and the MCP1793 is the 5-lead version, which offers shutdown functionality (SHDN pin). While in shutdown, the quiescent current drops to 2 µA, allowing for lower, overall power consumption. The device itself has a ground current of 100 µA typical, while delivering maximum output current of 100 mA. Note: For other voltage options, contact your local sales office. Applications • Automotive Electronics • Microcontroller Biasing • High-Voltage Battery Packs for Power Tools, ebikes, etc • Smoke Detectors and other Alarm Sensors Typical Application 9 9 9 9 9 9%$7 9 &,1 9 *1' PV PV PV 6+'1 —) 9 *1' V PV PV &287 0&3 —) 9 9 —&RQWUROOHU 9287 9,1 PV W *1' Overvoltage Line Transient  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 1 MCP1792/3 Package Types 3-Pin SOT-23A 5-Pin SOT-23 VIN TOP VIEW 3-Pin SOT-223 5-Pin SOT-223 GND GND 6 4 3 VIN 1 1 2 GND 2 SHDN 3 GND VOUT  2019-2022 Microchip Technology Inc. and its subsidiaries 5 VOUT 4 NC 1 VIN 2 3 GND VOUT 1 2 3 4 5 SHDN VIN GND VOUT NC DS20006229D-page 2 MCP1792/3 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Input Voltage ..........................................................................................................................................................+70.0V Maximum Voltage on VIN, SHDN ........................................................................................ (GND – 0.3V) to (VIN + 0.3V) Maximum Voltage on VOUT- ........................................................................................................... (GND – 0.3V) to 5.5V Output Short-Circuit Duration................................................................................... ............................Unlimited (Note 2) Storage Temperature ............................................................................................................................. -55°C to +175°C Maximum Junction Temperature, TJ ..................................................................................................................... +175°C Operating Junction Temperature, TJ ....................................................................................................... -40°C to +150°C ESD protection on all pins: HBM ....................................................................................................................................................................... ≥ 2 kV CDM ...................................................................................................................................................................... ≥ 750V MM .........................................................................................................................................................................≥ 200V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = VR + 1.2V (Note 1), IOUT = 1 mA, CIN = COUT = 2.2 µF ceramic (X7R), TA = +25°C, SHDN > 2.4V. Boldface type applies for ambient temperatures TA of -40°C to +150°C (Note 2). Parameters Input Operating Voltage Output Voltage Range Sym. Min. Typ. Max. Units VIN 4.5 — 55 V — VR – 2% VR VR + 2% — TA of -40°C to +85°C VOUT Conditions VR – 3% VR VR + 3% — TA of -40°C to +150°C Input Quiescent Current IQ — 25 45 µA IOUT = 0A Input Quiescent Current for SHDN Mode ISHDN — 2 12 µA SHDN = GND, VIN = 55V Ground Current IGND — 100 150 — 25 — Maximum Continuous Output Current IOUT 100 — — mA (Note 2) IOUT_SC — 230 370 mA VIN ≤ 55V Note 5) IFOLDBACK — 10 — mA VOUT~0V, RLOAD ≥ 0.1 VIN ≤ 55V,Note 5) Foldback Current Corner Foldback Current Note 1: 2: 3: 4: 5: µA IOUT = 100 mA IOUT = 1 mA VR is the nominal output voltage. The minimum input voltage is VIN = VR + 1.2V or VIN = VIN_MIN, whichever is greater. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). See the Temperature Specifications table and Section 5.0 “Application Information”. Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 150°C can impact the device reliability. Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VR + 1.2V. PSRR measurement is carried out with CIN = 0 µF, VIN = 7V, IOUT = 10 mA, VINAC = 0.4 Vpkpk. Not production tested.  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 3 MCP1792/3 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VR + 1.2V (Note 1), IOUT = 1 mA, CIN = COUT = 2.2 µF ceramic (X7R), TA = +25°C, SHDN > 2.4V. Boldface type applies for ambient temperatures TA of -40°C to +150°C (Note 2). Parameters Line Regulation Load Regulation Dropout Voltage Sym. Min. Typ. Max. Units VOUT/ (VOUTxVIN) — ±0.0002 ±0.05 %/V -1 0.2 +1 -2 0.2 +2 IOUT = 1 mA to 100 mA, TA of -40°C to +150°C — 250 400 TA of -40°C to +85°C, IOUT = 100 mA — 250 1200 VOUT/VOUT % VDROPOUT mV Conditions 4.5V < VIN < 55V, 6.2V < VIN < 55V IOUT = 1 mA to 100 mA, TA of -40°C to +85°C TA of -40°C to +150°C, IOUT = 100 mA (Note 3) Input Voltage to Turn On Output VUVLO_High — 2.7 — V VR = 3.3V, VR = 5.0V, rising VIN, VIN = 0 to VIN_MIN Input Voltage to Turn Off Output VUVLO_Low — 2.4 — V VR = 3.3V, VR = 5.0V, failing VIN, VIN = VIN_MIN to 0 Logic High Input VSHDN-HIGH 2.4 — VIN V — Logic Low Input VSHDN-LOW 0 — 0.8 V — SHDNILK — 0.2 0.4 µA SHDN = GND, or SHDN = 6.2V TDELAY — 800 1200 µs VIN = 0 to 6.2V VOUT = GND to 10% of VR, RLOAD = 50Note 5) TRISE — 400 — µs VIN = 0 to 6.2V VOUT = 10% to 90% of VR, RLOAD = 50 Note 5) eN — 400 — — 80 — — 55 — Shutdown Input Shutdown Input Leakage Current AC Performance Output Voltage Delay Time Output Rise Time Output Noise Power Supply Ripple Rejection Ratio Note 1: 2: 3: 4: 5: PSRR f = 10 Hz to 100 kHz, µVrms VR = 3.3V, IOUT = 10 mA (Note 5) dB f = 100 Hz (Note 4, Note 5) f = 100 kHz (Note 4, Note 5) VR is the nominal output voltage. The minimum input voltage is VIN = VR + 1.2V or VIN = VIN_MIN, whichever is greater. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). See the Temperature Specifications table and Section 5.0 “Application Information”. Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 150°C can impact the device reliability. Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VR + 1.2V. PSRR measurement is carried out with CIN = 0 µF, VIN = 7V, IOUT = 10 mA, VINAC = 0.4 Vpkpk. Not production tested.  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 4 MCP1792/3 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions TSD — 175 181 °C Rising Temperature TSD — 15 — °C Falling Temperature Temperature Ranges Thermal Shutdown Thermal Shutdown Hysteresis Thermal Package Resistances Thermal Resistance, SOT-23A-3LD Thermal Resistance, SOT23-5LD Thermal Resistance, SOT-223-3LD Thermal Resistance, SOT-223-5LD JA — 147 — JC — 115 — JA — 165 — JC — 96 — JA — 70 — JC — 60 — JA — 75 — JC — 60 —  2019-2022 Microchip Technology Inc. and its subsidiaries °C/W JEDEC® standard 4-layer FR4 board with 1 oz. copper DS20006229D-page 5 MCP1792/3 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, CIN = COUT = 2.2 µF ceramic (X7R), IOUT = 1 mA, TA = +25°C, VIN = VR + 1.2V, SHDN = 1 M pull-up to VIN.  ,287 P$ 7$ ƒ& 7$ ƒ&    7$ ƒ&  95 9 9,1 9  2XWSXW9ROWDJH9  2XWSXW9ROWDJH9  95 9  7$ ƒ&  7$ ƒ&    7$ ƒ&          ,QSXW9ROWDJH9 FIGURE 2-1: Output Voltage vs. Input Voltage (VR = 3.3V).  'URSRXW9ROWDJHP9 2XWSXW9ROWDJH9   7$ ƒ& 7$ ƒ&    7$ ƒ&  7$ ƒ&  7$ ƒ&              ,QSXW9ROWDJH9    /RDG&XUUHQWP$ FIGURE 2-2: Output Voltage vs. Input Voltage (VR = 5.0V). FIGURE 2-5: Current. Dropout Voltage vs. Load   95 9  9,1 9  /RDG5HJXODWLRQ 2XWSXW9ROWDJH9  95 9  7$ ƒ&    ,287 P$   FIGURE 2-4: Output Voltage vs. Output Current (VR = 3.3V). 95 9   2XWSXW&XUUHQWP$ 7$ ƒ&   7$ ƒ& 7$ ƒ&   ,287 P$WR  P$ 95 9 9,1 9              2XWSXW&XUUHQWP$ FIGURE 2-3: Output Voltage vs. Output Current (VR = 5.0V).  2019-2022 Microchip Technology Inc. and its subsidiaries          $PELHQW7HPSHUDWXUHƒ& FIGURE 2-6: Load Regulation vs. Temperature (VR = 5.0V). DS20006229D-page 6 MCP1792/3 Note: Unless otherwise indicated, CIN = COUT = 2.2 µF ceramic (X7R), IOUT = 1 mA, TA = +25°C, VIN = VR + 1.2V, SHDN = 1 M pull-up to VIN.  ,287 P$WR  P$ 95 9 9,1 9     95 9          7$ ƒ&  4XLHVFHQW&XUUHQW—$ /RDG5HJXODWLRQ    7$ ƒ&  7$ ƒ&       $PELHQW7HPSHUDWXUHƒ& 95 9 9,1 9WR9 ,287 P$                          7$ ƒ& 7$ ƒ& 7$ ƒ&     95 9   6+'1,4—$ /LQH5HJXODWLRQ9  95 9 9,1 9WR9 ,287 P$     7$ ƒ&  7$ ƒ&      FIGURE 2-11: Quiescent Current vs. Input Voltage (VR = 5.0V).    ,QSXW9ROWDJH9 FIGURE 2-8: Line Regulation vs. Ambient Temperature (VR = 5.0V).   95 9 $PELHQW7HPSHUDWXUHƒ&   FIGURE 2-10: Quiescent Current vs. Input Voltage (VR = 3.3V). 4XLHVFHQW&XUUHQW—$ /LQH5HJXODWLRQ9   ,QSXW9ROWDJH9 FIGURE 2-7: Load Regulation vs. Temperature (VR = 3.3V).         $PELHQW7HPSHUDWXUHƒ& FIGURE 2-9: Line Regulation vs. Ambient Temperature (VR = 3.3V).  2019-2022 Microchip Technology Inc. and its subsidiaries 7$ ƒ&        ,QSXW9ROWDJH9 FIGURE 2-12: Shutdown Quiescent Current vs. Input Voltage (VR = 5.0V). DS20006229D-page 7 MCP1792/3 Note: Unless otherwise indicated, CIN = COUT = 2.2 µF ceramic (X7R), IOUT = 1 mA, TA = +25°C, VIN = VR + 1.2V, SHDN = 1 M pull-up to VIN.   95 9 2XWSXW9ROWDJH9  6+'1,4 —$ 95 9 7$ ƒ&  7$ ƒ&   7$ ƒ&  7$ ƒ&   5HFRYHU\   )DOO                      ,QSXW9ROWDJH9 2XWSXW/RDGP$ FIGURE 2-13: Shutdown Quiescent Current vs. Input Voltage (VR = 3.3V). FIGURE 2-16: (VR = 3.3V).    7$ ƒ&  95 9 7$ ƒ&  7$ ƒ& 2XWSXW9ROWDJH9 *URXQG&XUUHQW—$ 95 9 7$ ƒ&   Current Foldback  5HFRYHU\  )DOO                            2XWSXW/RDGP$ 2XWSXW/RDGP$ FIGURE 2-14: Ground Current vs. Output Current (VR = 3.3V). FIGURE 2-17: (VR = 5.0V). Current Foldback  95 9 *URXQG&XUUHQW—$   7$ ƒ& 7$ ƒ& 7$ ƒ&                 2XWSXW/RDGP$ FIGURE 2-15: Ground Current vs. Output Current (VR = 5.0V).  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 8 MCP1792/3 Note: Unless otherwise indicated, CIN = COUT = 2.2 µF ceramic (X7R), IOUT = 1 mA, TA = +25°C, VIN = VR + 1.2V, SHDN = 1 M pull-up to VIN.  1RLVH—9¥+]  VIN 1V/div   UVLO (VR = 3.3V). 3655G% FIGURE 2-21: (VR = 5.0V). 1V/div VOUT 1V/div UVLO (VR = 5V). 3655G%   9,1 9 9287 9 ,/2$' P$ &287 —) 2XWSXW1RLVH+]N+] —9506      )UHTXHQF\N+] FIGURE 2-20: (VR = 3.3V). Noise vs. Frequency  2019-2022 Microchip Technology Inc. and its subsidiaries   Noise vs. Frequency  9 9  &5 QRWXVHG ,1  &287 —) 9,1 993.3.  ,/2$' P$              FIGURE 2-22: Power Supply Ripple Rejection vs. Frequency (VR = 3.3V).     )UHTXHQF\N+] 200 ms/div FIGURE 2-19:  )UHTXHQF\N+] 200 ms/div VIN 1RLVH—9¥+] 9,1 9 9287 9 ,/2$' P$ &287 —) 2XWSXW1RLVH+]N+] —9506   FIGURE 2-18:    VOUT 1V/div     95 9  &,1 QRWXVHG &287 —)  9,1 993.3.  ,/2$' P$              )UHTXHQF\N+] FIGURE 2-23: Power Supply Ripple Rejection vs. Frequency (VR = 5.0V). DS20006229D-page 9 MCP1792/3 Note: Unless otherwise indicated, CIN = COUT = 2.2 µF ceramic (X7R), IOUT = 1 mA, TA = +25°C, VIN = VR + 1.2V, SHDN = 1 M pull-up to VIN. IOUT = 10 mA Step from 6V to 14V VOUT 100 mV/div, BW = 20 MHz 3.3V DC Offset VIN 2V/div BW = 20 MHz 6V DC Offset Step from 1 mA to 50 mA Rise and Fall Slope = 1V/µs 6V IOUT 20 mA/div VOUT 100 mV/div, BW = 20 MHz 5.0V DC Offset 100 µs/div 400 µs/div FIGURE 2-24: (VR = 3.3V). Dynamic Load Step FIGURE 2-27: (VR = 5.0V). Dynamic Line Step IOUT = 10 mA 14V Rise Slope = 1V/µs VOUT 100 mV/div, BW = 20 MHz 5V DC Offset Step from 1 mA to 50 mA VIN 2V/div IOUT 20 mA/div VOUT 1V/Div 200 µs/div 400 µs/div FIGURE 2-25: (VR = 5.0V). FIGURE 2-28: Start-up From VIN (0V to 14V, VR = 3.3V). Dynamic Load Step IOUT = 10 mA IOUT = 10 mA Step from 4.5V to 14V VIN 2V/div BW = 20 MHz 4.5V DC Offset 14V Rise Slope = 1V/µs Rise and Fall Slope = 1V/µs VIN 2V/div VOUT 100 mV/div, BW = 20 MHz 3.3V DC Offset 100 µs/div FIGURE 2-26: (VR = 3.3V). Dynamic Line Step  2019-2022 Microchip Technology Inc. and its subsidiaries VOUT 1V/Div 200 µs/div FIGURE 2-29: Start-up From VIN (0V to 14V, VR = 5.0V). DS20006229D-page 10 MCP1792/3 Note: Unless otherwise indicated, CIN = COUT = 2.2 µF ceramic (X7R), IOUT = 1 mA, TA = +25°C, VIN = VR + 1.2V, SHDN = 1 M pull-up to VIN. IOUT = 10 mA IOUT = 10 mA 5V 48V SHDN 1V/div Rise Slope = 1V/µs VIN 10V/div VOUT 1V/div VOUT 1V/div 200 µs/div 200 µs/div FIGURE 2-30: Start-up From VIN (0V to 48V, VR = 3.3V). FIGURE 2-33: (VR = 5.0V). Start-up From SHDN IOUT = 10 mA IOUT = 10 mA 48V VIN 20V/div Rise Slope = 1V/µs 70V 58V 48V 48V VIN 10V/div VOUT 100 mV/div, AC Coupled VOUT 1V/div 200 µs/div FIGURE 2-31: Start-up From VIN (0V to 48V, VR = 5V). 100 ms/div FIGURE 2-34: Overvoltage Line Transient Response (VR = 5V). IOUT = 10 mA 5V IOUT = 10 mA VIN 20V/div SHDN 1V/div 58V 48V 48V VOUT 100 mV/div VOUT 1V/div 200 µs/div FIGURE 2-32: (VR = 3.3V). 70V Start-up From SHDN  2019-2022 Microchip Technology Inc. and its subsidiaries 100 ms/div FIGURE 2-35: Overvoltage Line Transient Response (VR = 3.3V). DS20006229D-page 11 MCP1792/3 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: SOT 23A-3 1 3.1 PIN FUNCTION TABLE SOT 23-5 SOT 223-3 2 SOT 223-5 Symbol 3 GND Ground Regulated Output Voltage VR 2 Description 2 5 3 4 VOUT 3 1 1 2 VIN Input Voltage Supply — 4 — 5 NC Not connected pins (should either be left floating or connected to ground) — 3 — 1 SHDN Shutdown Control Input. Connect to GND to turn off the output. Do not leave this pin floating. — — 4 6 Tab Ground Pin (GND) Exposed Thermal Pad, connected to GND 3.3 Input Voltage Supply Pin (VIN) For optimal noise and Power Supply Rejection Ratio (PSRR) performance, the GND pin of the LDO should be tied to an electrically “quiet” circuit ground. This will ensure the LDO power supply rejection ratio and noise device performance. The GND pin of the LDO conducts only ground current and that is why a wide trace is not required. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower the inductance and, as a result, reduce the effect of fast current transients. Connect the input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 2.2 µF to 10 µF should be sufficient for most applications. The type of capacitor used is ceramic. However, the low ESR characteristics of the ceramic capacitor will yield better noise and PSRR performance at high frequency. 3.2 The SHDN input is used to turn the LDO output voltage off. When the SHDN input is at a logic high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the LDO enters a low-quiescent current shutdown state, where the typical quiescent current is 2 µA. Regulated Output Voltage Pin (VOUT) The VOUT pin is the regulated output voltage VR of the LDO. A minimum output capacitance of 2.2 µF is required for the LDO to ensure the stability in all the typical applications. The MCP1792/3 is stable with ceramic capacitors. See Section 4.2 “Output Capacitance Requirements” for output capacitor selection guidance.  2019-2022 Microchip Technology Inc. and its subsidiaries 3.4 Shutdown Control Input (SHDN) DS20006229D-page 12 MCP1792/3 4.0 DETAILED DESCRIPTION 4.1 Device Overview The MCP1792/3 is an AEC-Q100 qualified LDO capable of outputting 100 mA of current over the entire temperature range. The part is stable with a minimum 2.2 µF ceramic capacitor and features a high-voltage SHDN pin, current foldback protection and extended working temperature range: -40° to +150°. The device also features an adequate PSRR of 80 dB typical for low frequencies and 55 dB for high frequencies. P-ch PASS DEVICE VIN VOUT UVLO Thermal Shutdown Logic Control Current Sense Enable to All Blocks Bandgap Reference (1.218V) Short Circuit Protection ERROR AMP - Adaptive Bias + Soft Start Discharge Transistor RDS = 80Ω typ Feedback Network SHDN Internally Connected for parts without SHDN GND FIGURE 4-1: Functional Block Diagram. An innovative adaptive bias circuitry is used to lower the power consumption at no load and light loads, without compromising the dynamic response. The internal discharge transistor is useful in powering microcontrollers and other applications that require fast supply disconnect. For improved transitory behavior over the entire temperature range, a 3.3 μF output capacitor is recommended. The ceramic capacitor type should be X7R or X8R\L because their dielectrics are rated for use with temperatures between -40°C to +125°C or -55°C to +150°C, respectively. 4.2 4.3 Output Capacitance Requirements The MCP1792/3 requires a minimum output capacitance of 2.2 μF for output voltage stability. The output capacitor should be located as close to the LDO output as it is practical. The device is designed to work with low ESR ceramic capacitors. Ceramic materials X8R\L or X7R have low temperature coefficients and are well within the acceptable ESR range required. A typical 2.2 μF X7R 0805 capacitor has an ESR of 50 mΩ. It is recommended to use an appropriate voltage rating capacitor, and the derating of the capacitance as a function of voltage and temperature needs to be taken into account.  2019-2022 Microchip Technology Inc. and its subsidiaries Input Capacitance Requirements Low input-source impedance is necessary for the LDO output to operate properly. When operating on batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, adding input capacitance is recommended. A minimum of 2.2 µF to 10 µF of capacitance is sufficient for most applications. Given the high input voltage capability of the MCP1792/3, of up to 55V DC, it is recommended to use an appropriate voltage rating capacitor, and the derating of the capacitance as a function of voltage and temperature needs to be taken into account. The ceramic capacitor type should be X7R or X8R\L because their dielectrics are rated for use with temperatures between -40°C to +125°C or -55°C to +150°C, respectively. DS20006229D-page 13 MCP1792/3 4.4 Circuit Protection The MCP1792/3 features current foldback protection during an output short-circuit event that occurs in normal operation. When the current foldback block detects an increase in load current, over the typical value of 230 mA, the output current and output voltage will start to decrease until the output current reaches a value of typically 10 mA (see Figure 2-16 and Figure 2-17). If a short circuit is present during power-up, the part will enter current limit protection. The MCP1792/3 was tested using the AEC-Q100 test set-up in Figure 4-2. The testing conditions require the use of very high parasitic inductances on the input and output. For cases like this, it is required to prevent the output voltage going below ground with more than 1V. Note that the VOUT pin can withstand a maximum of -0.3 VDC (see Absolute Maximum Ratings(†)). This can be achieved by placing a Schottky diode with the cathode to VOUT and the anode to ground. Thermal shutdown functionality is present on the device and adds to the protection features of the part. Thermal shutdown is triggered at a typical value of 175°C and has a typical hysteresis of 15°C. /VKRUW —+ ,GHDO 6XSSO\ /VKRUW —+ &,1 5VKRUW Pɏ *1' &287 0&3 —) 9 9287 9,1 21 5VKRUW Pɏ —) 6+'1 9 2)) *1' *1' *1' FIGURE 4-2: 4.5 Short Circuit Test Set-Up. Dropout Operation 4.6 For VR = 5V, MCP1792/3 can be found operating in a dropout condition (the minimum input voltage is 4.5V), which can happen during cold crank event, when the supply voltage can drop down to 3V. It is preferred to ensure that the part does not operate in dropout during DC operation so that the AC performance is maintained. The device has a dropout voltage of approximately 250 mV at full load and room temperature, but because of the extended temperature range at 150°C, due to increased leakage at hot, it reaches up to 1200 mV. For a 5V output, the minimum supply voltage required in order to have a regulated output, within specification, is 6.2V. 11V *1' IOUT = 10 mA VR = 5V VIN 2V/div 3V VOUT 2V/div Shutdown Input (SHDN) and Input UVLO The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold has a logic HIGH level of minimum 2.4V and a logic LOW level of maximum 0.8V. The SHDN pin ignores low-going pulses that are up to 30 µs. This blanking window helps to reject any system noise spikes on the SHDN input signal. Then, on the rising edge of the SHDN input, the shutdown circuitry adds 770 µs delay before allowing the regulator output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the (30 + 770) µs delay, the regulator starts charging the load capacitor as the output rises from 0V to its regulated value. The charging current amplitude will be limited by the short circuit current value of the device. If the SHDN input signal is pulled low during the 800 µs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. Figure 4-4 shows a timing diagram of the SHDN input. The MCP1792/3 has an internal discharge transistor connected to the VOUT PIN that is enabled when the SHDN pin goes low. The discharge occurs through a typical resistance of 80. 200 ms/div FIGURE 4-3: Line Step from Dropout.  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 14 MCP1792/3 The UVLO block helps prevent false start-ups during the power-up sequence, until the input voltage reaches a value of 2.7V. The minimum input voltage required for normal operation is 4.5V. 9 75,6( 7'(/$< 6+'1 7\SLFDOO\—V —V &287 —) 9287 7LPH FIGURE 4-4: 4.7 Shutdown Input Timing Diagram. Package and Device Qualifications The MCP1792/3 are AEC-Q100 with Grade 0 and PPAP Capable. The Grade 0 qualification allows the MCP1792/3 to be used within an extended temperature range from -40°C to +150°C. Additionally, the package has a moisture sensitivity level (MSL) of 1 for SOT223-5L, SOT23A-3L and SOT23-5L; for SOT223-3L the package has MSL 2 rating.  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 15 MCP1792/3 5.0 APPLICATION INFORMATION 5.1 Typical Application The MCP1792/3 is used for applications that require high input voltage and are prone to high transient voltages on the input. 9%$7 9WR9 *1' &287 0&3 —) 9 —&RQWUROOHU 9287 9,1 &,1 —) 6+'1 9 *1' *1' FIGURE 5-1: 5.2 Typical Application Circuit using a High-Voltage Battery Pack. Power Calculations 5.2.1 POWER DISSIPATION The internal power dissipation within the MCP1792/3 is a function of input voltage, output voltage, output current and quiescent current. Equation 5-1 can be used to calculate the internal power dissipation for the LDO. EQUATION 5-1: P LDO =  V IN  MAX  – V OUT  MIN    I OUT  MAX  Where: PLDO = Internal power dissipation of the LDO pass device VIN(MAX) = Maximum input voltage VOUT(MIN) = LDO minimum output voltage The total power dissipated within the MCP1792/3 is the sum of the power dissipated in the LDO pass device and the PI(GND) term. Because of the CMOS construction, the typical IGND for the MCP1792/3 is typical 100 µA at full load. Operating at a maximum VIN of 55V results in a power dissipation of 5.5 mW. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1792/3 is +150°C. To estimate the internal junction temperature of the MCP1792/3, the total internal power dissipation is multiplied by the thermal resistance from junction-to-ambient (JA) of the device. For example, the thermal resistance from junction-to-ambient for the 5-Lead SOT223 package is estimated at 75°C/W. EQUATION 5-3: IOUT(MAX) = Maximum output current In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1792/3 as a result of quiescent or ground current. The power dissipation as a result of ground current can be calculated by applying Equation 5-2: EQUATION 5-2: P I  GND  = V IN  MAX   I GND Where: PI(GND) = Power dissipation due to the ground current of the LDO VIN(MAX) = Maximum input voltage IGND = Current flowing into the GND pin  2019-2022 Microchip Technology Inc. and its subsidiaries T J  MAX  = P LDO   JA + T A  MAX  Where: TJ(MAX) = Maximum continuous junction temperature PLDO = Total power dissipation of the device JA = Thermal resistance from junction-to-ambient TA(MAX) = Maximum ambient temperature The maximum power dissipation capability for a package can be calculated given the junction-to-ambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation. DS20006229D-page 16 MCP1792/3 EQUATION 5-4: P D  MAX   T J  MAX  – T A  MAX   = ---------------------------------------------------  JA Where: IOUT = 50 mA Maximum Ambient Temperature TA(MAX) = +60°C Internal Power Dissipation PD(MAX) = Maximum power dissipation of the device PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX) PLDO = (14.7 – 4.9) x 50 mA TJ(MAX) = Maximum continuous junction temperature TA(MAX) = Maximum ambient temperature JA = Thermal resistance from junction-to-ambient EQUATION 5-5: T J  RISE  = P D  MAX    JA Where: TJ(RISE) = Rise in the device junction temperature over the ambient temperature PD(MAX) = Maximum power dissipation of the device JA = Thermal resistance from junction-to-ambient PLDO = 0.49 Watts 5.3.1.1 Device Junction Temperature Rise The internal junction temperature rise is a function of internal power dissipation and of the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (JA) is derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is JESD51. The standard describes the test method and board specifications for measuring the thermal resistance from junction-to-ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to Application Note AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. EXAMPLE 5-2: EQUATION 5-6: T J = T J  RISE  + T A TJ(RISE) = 36.75°C Where: TJ = Junction temperature TJ(RISE) = Rise in the device junction temperature over the ambient temperature TA = Ambient temperature 5.3 Typical Application Examples Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected. 5.3.1 TJ(RISE) = PTOTAL x JA TJ(RISE) = 0.49W x 75°C/W POWER DISSIPATION EXAMPLE EXAMPLE 5-1: Package 5.3.1.2 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: EXAMPLE 5-3: TJ = TJ(RISE) + TA(MAX) TJ = 36.75°C + 60.0°C TJ = 96.75°C 5.3.1.3 Maximum Package Power Dissipation at +60°C Ambient Temperature EXAMPLE 5-4: 5Lead SOT223 (JA = 75°C/W): Package Type = 5-Lead SOT223 PD(MAX) = (150°C – 60°C)/75°C/W Input Voltage PD(MAX) = 1.2W VIN = 14V ± 5% LDO Output Voltage and Current VOUT = 5V  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 17 MCP1792/3 6.0 BATTERY PACK APPLICATION The MCP1792/3’s features make it suitable for use in smart battery packs. The high SHDN and input voltage range of up to 55V and the transient voltage capability make it adequate for powering low-power microcontrollers used for monitoring battery health. FIGURE 6-1: Smart Battery Pack.  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 18 MCP1792/3 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 3-Lead SOT-223 Example XXXXXXX MCP1792 3302150 256 XXXYYWW NNN 3-Lead SOT-23A XXNN Example Part Number Code MCP1792T-3302H/CB(VAO) 33 MCP1792T-4102H/CB(VAO) 41 MCP1792T-5002H/CB(VAO) 50 Note: 3325 The content of this table applies to 3-Lead SOT-23A. Example 5-Lead SOT-223 MCP1793 5002149 256 5-Lead SOT-23 Example XXNN Part Number Code MCP1793T-3302H/OT(VAO) 33 MCP1793T-4102H/OT(VAO) 41 MCP1793T-5002H/OT(VAO) 50 Note: Legend: XX...X Y YY WW NNN e3 * Note: 5025 The content of this table applies to 5-Lead SOT-23. Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019-2022 Microchip Technology Inc. and its subsidiaries DS20006229D-page 19 MCP1792/3 /HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'%>627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D b2 E1 E 3 2 1 e e1 A2 A b c φ L A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 120 0$; 1  /HDG3LWFK H %6& 2XWVLGH/HDG3LWFK H 2YHUDOO+HLJKW $ ± ±  6WDQGRII $  ±  0ROGHG3DFNDJH+HLJKW $    2YHUDOO:LGWK (    0ROGHG3DFNDJH:LGWK (    2YHUDOO/HQJWK '    /HDG7KLFNQHVV F    /HDG:LGWK E    7DE/HDG:LGWK E    )RRW/HQJWK /  ± ± /HDG$QJOH  ƒ ± ƒ %6& 1RWHV  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(